From 846fb16d12e343eaf100e761018684a1aac796a3 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Sat, 15 Aug 2026 20:04:36 -0400 Subject: [PATCH 01/27] [rocjitsu][docs] Refresh architecture support documentation (#10197) Align the public documentation with the simulator and translation coverage currently represented in the tree. Mark CDNA3, CDNA4, CDNA5, RDNA3, and RDNA4 simulation support as Beta; keep CDNA5 scoped to gfx1250; use family target names where appropriate; remove the DBT and DBI table columns; and document the experimental CDNA4-to-CDNA3 translation path. Refresh the emulation overview without a brittle ISA count, and expand the configuration guide to list every checked-in simulator and DBT guest configuration. (cherry picked from commit b6d838028e5b2cdf657c7de38bad36656baf92d4) --- emulation/README.md | 4 ++-- emulation/rocjitsu/README.md | 28 ++++++++++++---------- emulation/rocjitsu/docs/configuration.md | 30 ++++++++++++++++++------ 3 files changed, 40 insertions(+), 22 deletions(-) diff --git a/emulation/README.md b/emulation/README.md index 2dfbc92463d8..3058e14a6f56 100644 --- a/emulation/README.md +++ b/emulation/README.md @@ -12,7 +12,7 @@ - [DBT](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/) — Dynamic binary translation: encoding and semantic translation. - [Patch / DBI](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/) — Patch points and (planned) instrumentation, spill/restore. - [Analysis Layer](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/) — Register liveness, def-use chains, hazard scheduling, lane permutation. See [liveness.cpp](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/liveness.cpp) and [def_use_chain.cpp](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp). - - [ISA Layer](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/) — Per-ISA decoders, operand types, machine instruction structs, encoding formats (CDNA1–4, RDNA1–4, RDNA3.5). Entry points: [decoder.cpp](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp), [rj_decode.cpp](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp); per-arch tables in [arch/](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/). + - [ISA Layer](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/) — Per-ISA decoders, operand types, machine instruction structs, encoding formats (CDNA1–5, RDNA1–4). Entry points: [decoder.cpp](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp), [rj_decode.cpp](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp); per-arch tables in [arch/](emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/). - [simdojo](emulation/rocjitsu/lib/simdojo/) — Decoupled parallel discrete-event simulation engine that orchestrates composable models. See [DESIGN.md](emulation/rocjitsu/lib/simdojo/DESIGN.md) and [src/](emulation/rocjitsu/lib/simdojo/src/) ([simulation.cpp](emulation/rocjitsu/lib/simdojo/src/simulation.cpp), [topology.cpp](emulation/rocjitsu/lib/simdojo/src/topology.cpp), [component.cpp](emulation/rocjitsu/lib/simdojo/src/component.cpp)). - [amdisa](emulation/rocjitsu/lib/python/amdisa/) — Python codegen that consumes AMD machine-readable ISA specs to auto-generate decoders, semantics, encoding/legalization tables, and cross-ISA translators. Key modules: [parser.py](emulation/rocjitsu/lib/python/amdisa/parser.py), [semantics.py](emulation/rocjitsu/lib/python/amdisa/semantics.py), [encoding_translator_codegen.py](emulation/rocjitsu/lib/python/amdisa/encoding_translator_codegen.py), [legalization_codegen.py](emulation/rocjitsu/lib/python/amdisa/legalization_codegen.py), [cross_isa.py](emulation/rocjitsu/lib/python/amdisa/cross_isa.py), [codegen/](emulation/rocjitsu/lib/python/amdisa/codegen/). - [rocjitsu_vllm](emulation/rocjitsu/lib/python/rocjitsu_vllm/) — Python integration glue for running vLLM on top of rocjitsu. @@ -106,7 +106,7 @@ flowchart TB CODEAPI --> DBI --> ANA end subgraph ISA["ISA Layer"] - I1["Per-ISA: decoders, execution, operand types, machine instr structs, encoding formats
9 ISAs: CDNA1–4, RDNA1–4, RDNA3.5"] + I1["Per-ISA: decoders, execution, operand types, machine instr structs, encoding formats
CDNA1–5, RDNA1–4"] subgraph AMDISA["amdisa (Python codegen)"] AM1["Leverages the AMD machine-readable ISA specs to auto-generate
ISA description and semantics for simulation, instrumentation, and translation"] end diff --git a/emulation/rocjitsu/README.md b/emulation/rocjitsu/README.md index 5cf18c20aad3..41c4bb150052 100644 --- a/emulation/rocjitsu/README.md +++ b/emulation/rocjitsu/README.md @@ -14,19 +14,21 @@ real hardware. Supports three execution strategies: ## Supported architectures -| Architecture | GFX Target | ISA Family | Simulation | DBT | DBI | -|---|---|---|---|---|---| -| CDNA1™ | gfx908 | GFX9 | Experimental | Experimental | Planned | -| CDNA2™ | gfx90a | GFX9 | Experimental | Experimental | Planned | -| CDNA3™ | gfx94x | GFX9 | Experimental | Experimental | Planned | -| CDNA4™ | gfx950 | GFX9 | Beta | Experimental | Planned | -| RDNA1™ | gfx1010 | GFX10 | Experimental | Experimental | Planned | -| RDNA2™ | gfx1030 | GFX10 | Experimental | Experimental | Planned | -| RDNA3™ | gfx1100 | GFX11 | Experimental | Experimental | Planned | -| RDNA3.5™ | gfx1150 | GFX11 | Experimental | Experimental | Planned | -| RDNA4™ | gfx1200 | GFX12 | Experimental | Experimental | Planned | -| CDNA5™ | gfx1250 | GFX12 | Experimental | Experimental | Planned | -| RISC-V | RV64I | RV | Experimental | — | — | +| Architecture | GFX Target | ISA Family | Simulation | +|---|---|---|---| +| CDNA1™ | gfx908 | GFX9 | Experimental | +| CDNA2™ | gfx90a | GFX9 | Experimental | +| CDNA3™ | gfx94x | GFX9 | Beta | +| CDNA4™ | gfx950 | GFX9 | Beta | +| CDNA5™ | gfx1250 | GFX12.5 | Beta | +| RDNA1™ | gfx1010 | GFX10 | Experimental | +| RDNA2™ | gfx1030 | GFX10 | Experimental | +| RDNA3™ | gfx110x | GFX11 | Beta | +| RDNA3.5™ | gfx1151 | GFX11.5 | Experimental | +| RDNA4™ | gfx120x | GFX12 | Beta | +| RISC-V | RV64I | RV | Experimental | + +CDNA4™ to CDNA3™ dynamic binary translation is experimental. diff --git a/emulation/rocjitsu/docs/configuration.md b/emulation/rocjitsu/docs/configuration.md index 020c38efa978..aa82b127c8f3 100644 --- a/emulation/rocjitsu/docs/configuration.md +++ b/emulation/rocjitsu/docs/configuration.md @@ -1,24 +1,40 @@ # Configuration -Simulation topologies are defined declaratively in JSON. The config -specifies the component hierarchy, link connectivity, and simulation -parameters. +Rocjitsu behavior is configured declaratively in JSON. Simulator configs +specify the component hierarchy, link connectivity, and simulation parameters; +DBT guest configs select the guest and host targets and execution backend. -## Config files +## Simulator configs -Pre-built configs are in `configs/`: +Pre-built simulator configs are in `configs/`: | File | Description | |---|---| +| `gfx942_cdna3.json` | Single CDNA3 GPU (standalone simulation) | +| `gfx942_cdna3_kmd.json` | Single CDNA3 GPU (daemon/KFD mode) | | `gfx950_cdna4.json` | Single CDNA4 GPU (standalone simulation) | | `gfx950_cdna4_kmd.json` | Single CDNA4 GPU (daemon/KFD mode) | | `gfx950_cdna4_kmd_2gpu.json` | Two CDNA4 GPUs (multi-GPU daemon mode) | -| `gfx942_cdna3.json` | Single CDNA3 GPU (standalone simulation) | -| `gfx942_cdna3_kmd.json` | Single CDNA3 GPU (daemon/KFD mode) | | `gfx1250.json` | Single gfx1250 GPU (standalone simulation, no KMD) | +| `gfx1100_w7900.json` | Single RDNA3 GPU (standalone simulation) | +| `gfx1151.json` | Single RDNA3.5 GPU (standalone simulation) | +| `gfx1201_r9700.json` | Single RDNA4 GPU (standalone simulation) | + +## DBT guest configs + +The checked-in [DBT guest-mode](rocjitsu_dbt_guest.md) configs cover hardware +and simulated host execution: + +| File | Description | +|---|---| +| `guest_gfx950_on_gfx942.json` | CDNA4 guest on a CDNA3 hardware host | +| `guest_gfx950_on_simulated_gfx942.json` | CDNA4 guest on a simulated CDNA3 host | +| `guest_gfx950_on_gfx1201.json` | CDNA4 guest on an RDNA4 hardware host | ## JSON structure +The remaining sections describe simulator topology configs. + ```json { "max_ticks": 100000, From db5c58b1bed38ab7d3cca444261ba81b674ebcb4 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Sat, 15 Aug 2026 20:17:08 -0400 Subject: [PATCH 02/27] [rocjitsu] Define standalone decoder ownership (#10200) Contain decoder failures inside the C API and clear writable outputs on every failure path. Document successful standalone decode results as caller-owned, provide a matching destroy API, and cover invalid encodings plus leak-free lifetime behavior. Fixes #8810 Fixes #8814 (cherry picked from commit 5c8e33e391c01c7cb433ea5fd50702ed4a5e3f11) --- .../rocjitsu/include/rocjitsu/code/rj_code.h | 33 ++++- .../rocjitsu/src/rocjitsu/code/rj_code.cpp | 26 +++- .../lib/rocjitsu/src/rocjitsu/isa/decoder.cpp | 16 +- .../lib/rocjitsu/src/rocjitsu/isa/decoder.h | 6 +- .../rocjitsu/src/rocjitsu/isa/instruction.h | 57 +++++++ .../rocjitsu/src/rocjitsu/isa/rj_decode.cpp | 79 ++++++---- emulation/rocjitsu/tests/CMakeLists.txt | 1 + .../tests/code/code_object_target_id_test.cpp | 14 ++ .../rocjitsu/tests/decoder_c_api_test.cpp | 140 ++++++++++++++++++ 9 files changed, 322 insertions(+), 50 deletions(-) create mode 100644 emulation/rocjitsu/tests/decoder_c_api_test.cpp diff --git a/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h b/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h index dbdd55c9fe75..0f0d93990e81 100644 --- a/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h +++ b/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h @@ -57,6 +57,13 @@ typedef enum rj_code_arch_e { typedef uint32_t rj_code_binary_inst_t; /// @brief Instruction object. +/// +/// @details A mutable pointer returned by rj_code_decoder_decode is an +/// independent caller-owned object. Const pointers returned by basic-block +/// accessors are borrowed from their owning list. Passing a borrowed pointer +/// to the standalone instruction destruction API after casting away const is +/// invalid. These are the two instruction ownership modes currently exposed +/// by this API. typedef struct rj_code_inst_t rj_code_inst_t; /// @brief Opaque handle to a decoder object. @@ -64,18 +71,22 @@ typedef struct rj_code_decoder_t rj_code_decoder_t; /// @brief Create a decoder for the architecture specified by @p arch. /// @param[in] arch Architecture to create a decoder for. -/// @param[out] decoder Newly created decoder handle (refcount = 0). +/// @param[out] decoder Newly created decoder handle (refcount = 0). Set to NULL +/// on any failure when @p decoder itself is non-NULL. /// @retval ROCJITSU_STATUS_SUCCESS Decoder was created successfully. /// @retval ROCJITSU_STATUS_INVALID_ARGUMENT if @p arch is invalid or @p decoder is NULL. +/// @retval ROCJITSU_STATUS_OUT_OF_RESOURCES Allocation failed. /// @retval ROCJITSU_STATUS_ERROR if this component did not bind @p arch. RJ_API_EXPORT rj_status_t rj_code_decoder_create(rj_code_arch_t arch, rj_code_decoder_t **decoder); /// @brief Create a decoder by canonical target ID or alias. /// @param[in] target_id Null-terminated target identity selected in this /// component's statically composed registry. -/// @param[out] decoder Newly created decoder handle (refcount = 0). +/// @param[out] decoder Newly created decoder handle (refcount = 0). Set to NULL +/// on any failure when @p decoder itself is non-NULL. /// @retval ROCJITSU_STATUS_SUCCESS Decoder was created successfully. /// @retval ROCJITSU_STATUS_INVALID_ARGUMENT if an argument is NULL or empty. +/// @retval ROCJITSU_STATUS_OUT_OF_RESOURCES Allocation failed. /// @retval ROCJITSU_STATUS_ERROR if this component did not include @p target_id. RJ_API_EXPORT rj_status_t rj_code_decoder_create_for_target(const char *target_id, rj_code_decoder_t **decoder); @@ -99,16 +110,31 @@ RJ_API_EXPORT void rj_code_decoder_release(rj_code_decoder_t *decoder); RJ_API_EXPORT void rj_code_decoder_destroy(rj_code_decoder_t *decoder); /// @brief Decode an instruction from raw binary bits. +/// +/// @details On success, @p inst receives an independent caller-owned +/// instruction that remains valid after @p decoder is destroyed. Release it +/// with rj_code_inst_destroy. On any failure, @p inst is set to NULL. /// @param[in] decoder The decoder object to use for decoding. /// @param[in] binary_inst Pointer to raw instruction bits in the instruction stream. /// @param[out] inst Pointer to the newly decoded instruction object. /// @retval ROCJITSU_STATUS_SUCCESS Instruction was decoded successfully. /// @retval ROCJITSU_STATUS_INVALID_ARGUMENT A required argument is NULL. +/// @retval ROCJITSU_STATUS_OUT_OF_RESOURCES Allocation failed. /// @retval ROCJITSU_STATUS_ERROR Decoding failed. RJ_API_EXPORT rj_status_t rj_code_decoder_decode(rj_code_decoder_t *decoder, const rj_code_binary_inst_t *binary_inst, rj_code_inst_t **inst); +/// @brief Destroy a caller-owned standalone decoded instruction. +/// +/// @details This instruction type is not reference counted; destruction frees +/// the object immediately. Only mutable instructions returned by +/// rj_code_decoder_decode may be passed to this function. Const instructions +/// returned by basic-block accessors are borrowed and remain owned by their +/// list. +/// @param[in] inst Caller-owned instruction to destroy (may be NULL). +RJ_API_EXPORT void rj_code_inst_destroy(rj_code_inst_t *inst); + /// @brief GPU target identifiers. typedef enum rj_code_target_id_t { /// @brief gfx90a target ID (CDNA2). @@ -368,7 +394,8 @@ rj_code_basic_block_first_inst(const rj_code_basic_block_t *block); /// @brief Get the next instruction in the same basic block. /// @param[in] inst Current instruction. -/// @returns Pointer to the next instruction, or NULL if at the end of the block. +/// @returns Pointer to the next instruction, or NULL if at the end of the block +/// or if @p inst is a standalone instruction returned by rj_code_decoder_decode. RJ_API_EXPORT const rj_code_inst_t *rj_code_inst_next(const rj_code_inst_t *inst); /// @} diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp index 26bb03987654..df14f9046386 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp @@ -124,6 +124,7 @@ rj_status_t rj_code_inst_list_create(rj_code_object_t *obj, rj_code_target_id_t return ROCJITSU_STATUS_INVALID_ARGUMENT; try { + Instruction::ScopedHeapAllocation heap_allocation; auto owned = std::make_unique(); // DBT local caves are emitted into .text, so instruction-list callers only @@ -158,15 +159,19 @@ void rj_code_inst_list_retain(rj_code_inst_list_t *inst_list) { void rj_code_inst_list_release(rj_code_inst_list_t *inst_list) { if (!inst_list) return; - if (inst_list->release()) + if (inst_list->release()) { + Instruction::ScopedHeapAllocation heap_allocation; delete inst_list; + } } void rj_code_inst_list_destroy(rj_code_inst_list_t *inst_list) { if (!inst_list) return; - if (inst_list->destroy()) + if (inst_list->destroy()) { + Instruction::ScopedHeapAllocation heap_allocation; delete inst_list; + } } rj_status_t rj_code_basic_block_list_create(rj_code_object_t *obj, rj_code_target_id_t target_id, @@ -184,6 +189,7 @@ rj_status_t rj_code_basic_block_list_create(rj_code_object_t *obj, rj_code_targe return ROCJITSU_STATUS_INVALID_ARGUMENT; try { + Instruction::ScopedHeapAllocation heap_allocation; auto owned = std::make_unique(); owned->blocks = BasicBlock::build(*obj->co, *decoder, arch); *list = owned.release(); @@ -201,15 +207,19 @@ void rj_code_basic_block_list_retain(rj_code_basic_block_list_t *list) { void rj_code_basic_block_list_release(rj_code_basic_block_list_t *list) { if (!list) return; - if (list->release()) + if (list->release()) { + Instruction::ScopedHeapAllocation heap_allocation; delete list; + } } void rj_code_basic_block_list_destroy(rj_code_basic_block_list_t *list) { if (!list) return; - if (list->destroy()) + if (list->destroy()) { + Instruction::ScopedHeapAllocation heap_allocation; delete list; + } } uint32_t rj_code_basic_block_list_size(const rj_code_basic_block_list_t *list) { @@ -239,15 +249,19 @@ void rj_code_basic_block_retain(rj_code_basic_block_t *block) { void rj_code_basic_block_release(rj_code_basic_block_t *block) { if (!block) return; - if (block->release()) + if (block->release()) { + Instruction::ScopedHeapAllocation heap_allocation; delete block; + } } void rj_code_basic_block_destroy(rj_code_basic_block_t *block) { if (!block) return; - if (block->destroy()) + if (block->destroy()) { + Instruction::ScopedHeapAllocation heap_allocation; delete block; + } } uint64_t rj_code_basic_block_start_offset(const rj_code_basic_block_t *block) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp index 2dc2e673b578..4b379bbdbd97 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp @@ -20,13 +20,13 @@ std::unique_ptr Decoder::create(const IsaTargetRegistry ®istry, rj_c } Decoder::~Decoder() { - // If this decoder's pool is still the active one, deactivate it so - // surviving instructions (held by callers in unique_ptr/vectors) fall - // back to ::operator delete instead of following a dangling pool pointer. - if (Instruction::alloc_pool_ == &pool_) - deactivate_pool(); + // Clear direct and temporarily suppressed references to this pool so no + // later allocation scope can restore a pointer into a destroyed decoder. + Instruction::invalidate_allocator_pool(&pool_); } +void Decoder::disable_pool() { Instruction::invalidate_allocator_pool(&pool_); } + void Decoder::validate_instruction_operands(const Instruction &inst) { for (int index = 0; index < inst.num_src_operands(); ++index) { if (const Operand *operand = inst.src_operand(index)) @@ -51,10 +51,4 @@ void Decoder::activate_pool(AllocFn alloc, DeallocFn dealloc, void *pool) { Instruction::alloc_pool_ = pool; } -void Decoder::deactivate_pool() { - Instruction::alloc_fn_ = nullptr; - Instruction::dealloc_fn_ = nullptr; - Instruction::alloc_pool_ = nullptr; -} - } // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h index 38f8821ff99f..2d6829a5e118 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h @@ -31,6 +31,8 @@ struct IsaExecutionBackend; /// (e.g., the ComputeUnit simulation loop). class Decoder { public: + using Pool = util::ArenaAlloc<512, 128>; + virtual ~Decoder(); /// @brief Decode a binary instruction. @@ -71,15 +73,13 @@ class Decoder { } /// @brief Disable pool allocation; future allocations use the heap. - void disable_pool() { deactivate_pool(); } + void disable_pool(); protected: - using Pool = util::ArenaAlloc<512, 128>; using AllocFn = void *(*)(void *, size_t); using DeallocFn = void (*)(void *, void *); static void activate_pool(AllocFn alloc, DeallocFn dealloc, void *pool); - static void deactivate_pool(); static void validate_instruction_operands(const Instruction &inst); Pool pool_; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h index 906a2feba9d0..c04367dc8f7c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h @@ -109,6 +109,63 @@ class Instruction : public util::IListNodeprevious_scope_) { + if (scope->saved_alloc_pool_ != pool) + continue; + scope->saved_alloc_fn_ = nullptr; + scope->saved_dealloc_fn_ = nullptr; + scope->saved_alloc_pool_ = nullptr; + } + } + static void *operator new(size_t size) { if (alloc_fn_) return alloc_fn_(alloc_pool_, size); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp index 673657c7d917..eef2f4ee7462 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp @@ -7,9 +7,9 @@ #include "rocjitsu/isa/instruction.h" #include "rocjitsu/isa/target_registry.h" #include "rocjitsu/refcount.h" -#include "util/except.h" #include +#include using namespace rocjitsu; @@ -17,31 +17,47 @@ struct rj_code_decoder_t : RefCounted { std::unique_ptr decoder; }; -rj_status_t rj_code_decoder_create(rj_code_arch_t arch, rj_code_decoder_t **decoder) { - if (!decoder || arch < ROCJITSU_CODE_ARCH_CDNA1 || arch >= ROCJITSU_CODE_ARCH_NUM_ARCHS) - return ROCJITSU_STATUS_INVALID_ARGUMENT; +namespace { - auto d = Decoder::create(arch); - if (!d) +template +rj_status_t create_decoder_handle(Factory &&factory, rj_code_decoder_t **decoder) { + try { + auto implementation = factory(); + if (!implementation) + return ROCJITSU_STATUS_ERROR; + + auto handle = std::make_unique(); + handle->decoder = std::move(implementation); + *decoder = handle.release(); + return ROCJITSU_STATUS_SUCCESS; + } catch (const std::bad_alloc &) { + return ROCJITSU_STATUS_OUT_OF_RESOURCES; + } catch (...) { return ROCJITSU_STATUS_ERROR; + } +} - *decoder = new rj_code_decoder_t{}; - (*decoder)->decoder = std::move(d); - return ROCJITSU_STATUS_SUCCESS; +} // namespace + +rj_status_t rj_code_decoder_create(rj_code_arch_t arch, rj_code_decoder_t **decoder) { + if (!decoder) + return ROCJITSU_STATUS_INVALID_ARGUMENT; + *decoder = nullptr; + if (arch < ROCJITSU_CODE_ARCH_CDNA1 || arch >= ROCJITSU_CODE_ARCH_NUM_ARCHS) + return ROCJITSU_STATUS_INVALID_ARGUMENT; + + return create_decoder_handle([arch] { return Decoder::create(arch); }, decoder); } rj_status_t rj_code_decoder_create_for_target(const char *target_id, rj_code_decoder_t **decoder) { - if (target_id == nullptr || target_id[0] == '\0' || decoder == nullptr) + if (decoder == nullptr) + return ROCJITSU_STATUS_INVALID_ARGUMENT; + *decoder = nullptr; + if (target_id == nullptr || target_id[0] == '\0') return ROCJITSU_STATUS_INVALID_ARGUMENT; - std::unique_ptr target_decoder = - Decoder::create(default_isa_target_registry(), target_id); - if (!target_decoder) - return ROCJITSU_STATUS_ERROR; - - *decoder = new rj_code_decoder_t{}; - (*decoder)->decoder = std::move(target_decoder); - return ROCJITSU_STATUS_SUCCESS; + return create_decoder_handle( + [target_id] { return Decoder::create(default_isa_target_registry(), target_id); }, decoder); } void rj_code_decoder_retain(rj_code_decoder_t *decoder) { @@ -66,19 +82,28 @@ void rj_code_decoder_destroy(rj_code_decoder_t *decoder) { rj_status_t rj_code_decoder_decode(rj_code_decoder_t *decoder, const rj_code_binary_inst_t *binary_inst, rj_code_inst_t **inst) { - if (!decoder || !decoder->decoder || !binary_inst || !inst) + if (!inst) return ROCJITSU_STATUS_INVALID_ARGUMENT; - *inst = nullptr; - Instruction *decoded = nullptr; + if (!decoder || !decoder->decoder || !binary_inst) + return ROCJITSU_STATUS_INVALID_ARGUMENT; + try { - decoded = decoder->decoder->decode(binary_inst); - } catch (const util::InvalidInst &) { + Instruction::ScopedHeapAllocation heap_allocation; + std::unique_ptr decoded(decoder->decoder->decode(binary_inst)); + if (!decoded) + return ROCJITSU_STATUS_ERROR; + + *inst = reinterpret_cast(decoded.release()); + return ROCJITSU_STATUS_SUCCESS; + } catch (const std::bad_alloc &) { + return ROCJITSU_STATUS_OUT_OF_RESOURCES; + } catch (...) { return ROCJITSU_STATUS_ERROR; } - if (!decoded) - return ROCJITSU_STATUS_ERROR; +} - *inst = reinterpret_cast(decoded); - return ROCJITSU_STATUS_SUCCESS; +void rj_code_inst_destroy(rj_code_inst_t *inst) { + Instruction::ScopedHeapAllocation heap_allocation; + delete reinterpret_cast(inst); } diff --git a/emulation/rocjitsu/tests/CMakeLists.txt b/emulation/rocjitsu/tests/CMakeLists.txt index 05897a247e3a..7f212db8901a 100644 --- a/emulation/rocjitsu/tests/CMakeLists.txt +++ b/emulation/rocjitsu/tests/CMakeLists.txt @@ -415,6 +415,7 @@ add_executable( partitioning_test.cpp simulated_kfd_test.cpp decode_smoke_test.cpp + decoder_c_api_test.cpp buffer_operand_test.cpp smem_sbase_operand_test.cpp shared_infra_test.cpp diff --git a/emulation/rocjitsu/tests/code/code_object_target_id_test.cpp b/emulation/rocjitsu/tests/code/code_object_target_id_test.cpp index 8521f247c17e..d8e54ed64b90 100644 --- a/emulation/rocjitsu/tests/code/code_object_target_id_test.cpp +++ b/emulation/rocjitsu/tests/code/code_object_target_id_test.cpp @@ -19,6 +19,7 @@ #include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/kernel_symbol.h" #include "rocjitsu/code/rj_code.h" +#include "rocjitsu/isa/decoder.h" #include "scoped_temp.h" #include @@ -149,11 +150,24 @@ void expect_c_api_accepts_target(uint32_t mach_flag, rj_code_target_id_t target) // The returned code-object handle must keep its executable storage alive. rj_code_executable_destroy(exec); + auto pooled_decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); + ASSERT_NE(pooled_decoder, nullptr); + pooled_decoder->enable_pool(); + + rj_code_inst_list_t *instructions = nullptr; + ASSERT_EQ(rj_code_inst_list_create(obj, target, &instructions), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(instructions, nullptr); + rj_code_basic_block_list_t *blocks = nullptr; EXPECT_EQ(rj_code_basic_block_list_create(obj, target, &blocks), ROCJITSU_STATUS_SUCCESS) << "rj_code_basic_block_list_create must succeed for a target whose decoder is wired in"; ASSERT_NE(blocks, nullptr); + // Both C API list types own their decoded instructions independently of an + // unrelated decoder pool that was active while they were constructed. + rj_code_inst_list_destroy(instructions); + pooled_decoder.reset(); + rj_code_basic_block_t *block = nullptr; ASSERT_EQ(rj_code_basic_block_list_get(blocks, 0, &block), ROCJITSU_STATUS_SUCCESS); ASSERT_NE(block, nullptr); diff --git a/emulation/rocjitsu/tests/decoder_c_api_test.cpp b/emulation/rocjitsu/tests/decoder_c_api_test.cpp new file mode 100644 index 000000000000..15eda922d849 --- /dev/null +++ b/emulation/rocjitsu/tests/decoder_c_api_test.cpp @@ -0,0 +1,140 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#include "rocjitsu/code/rj_code.h" +#include "rocjitsu/isa/decoder.h" +#include "rocjitsu/isa/instruction.h" + +#include + +#include +#include +#include +#include + +namespace { + +// s_endpgm in the GFX9/CDNA SOPP encoding, which gfx1250 rejects. +constexpr rj_code_binary_inst_t kCdnaSEndpgm = 0xBF810000u; + +static_assert(std::is_same_v, + "standalone destruction must not accept borrowed const instructions"); +static_assert( + std::is_same_v, + "borrowed instructions must remain const-qualified"); +static_assert(std::is_same_v, + "instruction traversal must preserve the borrowed const qualification"); + +TEST(DecoderCApiTest, InvalidInstructionReturnsErrorAndClearsOutput) { + rj_code_decoder_t *decoder = nullptr; + ASSERT_EQ(rj_code_decoder_create(ROCJITSU_CODE_ARCH_GFX1250, &decoder), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(decoder, nullptr); + + auto *instruction = reinterpret_cast(static_cast(1)); + EXPECT_EQ(rj_code_decoder_decode(decoder, &kCdnaSEndpgm, &instruction), ROCJITSU_STATUS_ERROR); + EXPECT_EQ(instruction, nullptr); + + rj_code_decoder_destroy(decoder); +} + +TEST(DecoderCApiTest, InvalidArgumentsClearWritableOutputs) { + auto *instruction = reinterpret_cast(static_cast(1)); + EXPECT_EQ(rj_code_decoder_decode(nullptr, &kCdnaSEndpgm, &instruction), + ROCJITSU_STATUS_INVALID_ARGUMENT); + EXPECT_EQ(instruction, nullptr); + + auto *decoder = reinterpret_cast(static_cast(1)); + EXPECT_EQ(rj_code_decoder_create(ROCJITSU_CODE_ARCH_INVALID, &decoder), + ROCJITSU_STATUS_INVALID_ARGUMENT); + EXPECT_EQ(decoder, nullptr); + + decoder = reinterpret_cast(static_cast(1)); + EXPECT_EQ(rj_code_decoder_create_for_target(nullptr, &decoder), ROCJITSU_STATUS_INVALID_ARGUMENT); + EXPECT_EQ(decoder, nullptr); + + decoder = reinterpret_cast(static_cast(1)); + EXPECT_EQ(rj_code_decoder_create_for_target("", &decoder), ROCJITSU_STATUS_INVALID_ARGUMENT); + EXPECT_EQ(decoder, nullptr); +} + +TEST(DecoderCApiTest, StandaloneInstructionsAreCallerOwned) { + rj_code_decoder_t *decoder = nullptr; + ASSERT_EQ(rj_code_decoder_create(ROCJITSU_CODE_ARCH_CDNA3, &decoder), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(decoder, nullptr); + + rj_code_inst_t *instruction = nullptr; + ASSERT_EQ(rj_code_decoder_decode(decoder, &kCdnaSEndpgm, &instruction), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(instruction, nullptr); + EXPECT_STREQ(rj_code_inst_mnemonic(instruction), "s_endpgm"); + rj_code_inst_destroy(instruction); + + rj_code_inst_t *survivor = nullptr; + ASSERT_EQ(rj_code_decoder_decode(decoder, &kCdnaSEndpgm, &survivor), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(survivor, nullptr); + rj_code_decoder_destroy(decoder); + + EXPECT_STREQ(rj_code_inst_mnemonic(survivor), "s_endpgm"); + EXPECT_GT(rj_code_inst_size(survivor), 0u); + char disassembly[64]{}; + EXPECT_EQ(rj_code_inst_disassemble(survivor, disassembly, sizeof(disassembly)), + ROCJITSU_STATUS_SUCCESS); + EXPECT_NE(std::strstr(disassembly, "s_endpgm"), nullptr); + EXPECT_EQ(rj_code_inst_next(survivor), nullptr); + + rj_code_inst_destroy(survivor); + rj_code_inst_destroy(nullptr); +} + +TEST(DecoderCApiTest, StandaloneInstructionIgnoresAmbientDecoderPool) { + auto pooled_decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); + ASSERT_NE(pooled_decoder, nullptr); + pooled_decoder->enable_pool(); + const auto *active_pool = + static_cast(rocjitsu::Instruction::alloc_pool_); + ASSERT_NE(active_pool, nullptr); + + rj_code_decoder_t *decoder = nullptr; + ASSERT_EQ(rj_code_decoder_create(ROCJITSU_CODE_ARCH_CDNA3, &decoder), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(decoder, nullptr); + + rj_code_inst_t *instruction = nullptr; + ASSERT_EQ(rj_code_decoder_decode(decoder, &kCdnaSEndpgm, &instruction), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(instruction, nullptr); + EXPECT_FALSE(active_pool->owns(instruction)); + EXPECT_EQ(rocjitsu::Instruction::alloc_pool_, active_pool); + rj_code_inst_destroy(instruction); + EXPECT_EQ(rocjitsu::Instruction::alloc_pool_, active_pool); + + instruction = nullptr; + ASSERT_EQ(rj_code_decoder_decode(decoder, &kCdnaSEndpgm, &instruction), ROCJITSU_STATUS_SUCCESS); + ASSERT_NE(instruction, nullptr); + EXPECT_FALSE(active_pool->owns(instruction)); + + rj_code_decoder_destroy(decoder); + pooled_decoder.reset(); + EXPECT_EQ(rocjitsu::Instruction::alloc_pool_, nullptr); + + EXPECT_STREQ(rj_code_inst_mnemonic(instruction), "s_endpgm"); + rj_code_inst_destroy(instruction); +} + +TEST(DecoderCApiTest, HeapAllocationScopeForgetsDestroyedPool) { + auto pooled_decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); + ASSERT_NE(pooled_decoder, nullptr); + pooled_decoder->enable_pool(); + ASSERT_NE(rocjitsu::Instruction::alloc_pool_, nullptr); + + { + rocjitsu::Instruction::ScopedHeapAllocation heap_allocation; + pooled_decoder.reset(); + } + EXPECT_EQ(rocjitsu::Instruction::alloc_pool_, nullptr); + + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); + ASSERT_NE(decoder, nullptr); + std::unique_ptr instruction(decoder->decode(&kCdnaSEndpgm)); + ASSERT_NE(instruction, nullptr); + EXPECT_EQ(instruction->mnemonic(), "s_endpgm"); +} + +} // namespace From ed102baf1caf8e537782ec3ecfd97b631e870e08 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Sat, 15 Aug 2026 20:46:55 -0400 Subject: [PATCH 03/27] [rocjitsu] Apply async IOFFSET to LDS addresses (#10199) Apply the signed 24-bit IOFFSET to both the global and LDS addresses for ordinary and cluster async loads and async stores, matching CDNA5 section 10.8.1 and expressions 95-102 and 106-109. Reject LDS destinations outside the issuing workgroup allocation, keep cluster remapping widened through validation, and filter invalid lanes from writeback and race detection. Add generator, execution, multicast, and plugin coverage for signed offsets, allocation bounds, and wraparound addresses. Fixes #8829 (cherry picked from commit be1f91998fccd6cc3470e549155354404c004c8a) --- .../lib/python/amdisa/codegen/_generator.py | 24 +- .../tests/test_generator_profile_gates.py | 82 ++++ .../isa/arch/amdgpu/cdna5/addr_calc.cpp | 21 +- .../isa/arch/amdgpu/cdna5/addr_calc.h | 11 + .../amdgpu/generated/cdna5/vglobal_exec.cpp | 60 ++- .../vm/amdgpu/cluster_lds_multicast.cpp | 34 +- .../vm/amdgpu/cluster_lds_multicast.h | 6 +- .../rocjitsu/vm/amdgpu/command_processor.cpp | 1 + .../lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds.h | 27 +- .../rocjitsu/vm/amdgpu/memory_pipeline.cpp | 6 + .../lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h | 1 + .../src/rocjitsu/vm/amdgpu/wavefront.h | 8 + .../vm/plugins/race_detector/plugin.cpp | 9 +- .../rocjitsu/tests/cdna5_cluster_test.cpp | 451 +++++++++++++++--- .../tests/cdna5_dispatch_memory_test.cpp | 19 + .../rocjitsu/tests/cdna5_instruction_test.cpp | 1 + .../rocjitsu/tests/execution_plugin_test.cpp | 48 ++ 17 files changed, 675 insertions(+), 134 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index b09f69553134..a5192c28f2d3 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -5847,6 +5847,7 @@ def _gen_global_load_async_to_lds( L = [] esz, ne = sem.elem_size, sem.num_elems _, _, nt = self._coherency_exprs() + stride = esz * ne L.append( ' auto d = std::make_unique(amdgpu::GLOBAL_MEM);' ) @@ -5869,7 +5870,7 @@ def _gen_global_load_async_to_lds( L.append(' auto &cu = wf.cu();') L.append(' uint64_t exec = wf.exec();') L.append( - ' // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent.' + ' // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses.' ) L.append(f" uint32_t lds_addr_base = {self._vgpr_base_expr('vdst')};") L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') @@ -5877,7 +5878,9 @@ def _gen_global_load_async_to_lds( L.append( ' uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane);' ) - L.append(' d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr;') + L.append( + f' d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, {stride});' + ) L.append(' }') L.append(' set_data(std::move(d));') return '\n'.join(L) @@ -5903,14 +5906,20 @@ def _gen_global_store_async_from_lds( L.append(' const auto &lds = cu.lds();') L.append(' uint64_t exec = wf.exec();') L.append( - ' // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent.' + ' // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses.' ) L.append(f" uint32_t lds_addr_base = {self._vgpr_base_expr('vsrc')};") L.append(f' d->store_data.resize(wf.wf_size() * {stride});') L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') L.append( - ' uint32_t lds_addr = wf.lds_base() + amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane);' + ' uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane);' + ) + L.append( + f' uint32_t lds_addr = async_lds_lane_address(inst_, wf, lane_lds_addr, {stride});' + ) + L.append( + ' // Out-of-range LDS reads return zero; the global store still issues.' ) L.append(f' lds.read(lds_addr, &d->store_data[lane * {stride}], {stride});') L.append(' }') @@ -5925,9 +5934,12 @@ def _append_global_addtid_addresses(self, L: list[str]) -> None: L.append(' d->wg_id = wf.wg_id(); d->wf_id = wf.wf_id();') L.append(' d->cu_path = wf.cu().full_path();') L.append(' uint64_t base = amdgpu::RegisterAccess(wf).read_scalar64(saddr);') - L.append( - ' int64_t offset = static_cast(static_cast(inst_.ioffset << 8) >> 8);' + offset_expr = ( + 'signed_ioffset(inst_.ioffset)' + if self.isa_spec.arch_name == 'gfx1250' + else 'static_cast(inst_.ioffset << 8) >> 8' ) + L.append(f' int64_t offset = static_cast({offset_expr});') L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') L.append( diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index 9c42cd3262c3..d0897df78914 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -3926,6 +3926,88 @@ def test_gfx1250_cluster_load_generators_force_request_l1_bypass(): assert 'd->request_force_l1_bypass = true;' not in global_async_body +def test_gfx1250_async_lds_generators_apply_signed_ioffset(): + codegen = object.__new__(CodeGenerator) + codegen.isa_spec = SimpleNamespace( + arch_name='gfx1250', + profile=Gfx1250Profile(), + ) + + expected_load_address = ( + 'd->per_lane_lds_addr[lane] = ' + 'async_lds_lane_address(inst_, wf, lane_lds_addr, 4);' + ) + + global_async = SimpleNamespace( + name='GLOBAL_LOAD_ASYNC_TO_LDS_B32', + elem_size=4, + num_elems=1, + ) + global_async_body = codegen._gen_global_load_async_to_lds([], [], global_async) + assert expected_load_address in global_async_body + + cluster_async_cases = [ + ('CLUSTER_LOAD_ASYNC_TO_LDS_B8', 1, 1), + ('CLUSTER_LOAD_ASYNC_TO_LDS_B32', 4, 1), + ('CLUSTER_LOAD_ASYNC_TO_LDS_B64', 4, 2), + ('CLUSTER_LOAD_ASYNC_TO_LDS_B128', 4, 4), + ] + for name, elem_size, num_elems in cluster_async_cases: + cluster_async = SimpleNamespace( + name=name, + elem_size=elem_size, + num_elems=num_elems, + ) + cluster_async_body = codegen._gen_global_load_async_to_lds( + [], [], cluster_async + ) + assert ( + 'd->per_lane_lds_addr[lane] = ' + f'async_lds_lane_address(inst_, wf, lane_lds_addr, {elem_size * num_elems});' + in cluster_async_body + ) + + global_store_cases = [ + ('GLOBAL_STORE_ASYNC_FROM_LDS_B8', 1, 1), + ('GLOBAL_STORE_ASYNC_FROM_LDS_B32', 4, 1), + ('GLOBAL_STORE_ASYNC_FROM_LDS_B64', 4, 2), + ('GLOBAL_STORE_ASYNC_FROM_LDS_B128', 4, 4), + ] + for name, elem_size, num_elems in global_store_cases: + global_store = SimpleNamespace( + name=name, + elem_size=elem_size, + num_elems=num_elems, + ) + global_store_body = codegen._gen_global_store_async_from_lds( + [], [], global_store + ) + assert ( + 'uint32_t lds_addr = ' + f'async_lds_lane_address(inst_, wf, lane_lds_addr, {elem_size * num_elems});' + in global_store_body + ) + + addtid_lines = [] + codegen._append_global_addtid_addresses(addtid_lines) + assert ( + ' int64_t offset = static_cast(signed_ioffset(inst_.ioffset));' + in addtid_lines + ) + + rdna4_codegen = object.__new__(CodeGenerator) + rdna4_codegen.isa_spec = SimpleNamespace( + arch_name='gfx1201', + profile=Rdna4Profile(), + ) + rdna4_addtid_lines = [] + rdna4_codegen._append_global_addtid_addresses(rdna4_addtid_lines) + assert ( + ' int64_t offset = static_cast(' + 'static_cast(inst_.ioffset << 8) >> 8);' in rdna4_addtid_lines + ) + + def test_gfx1250_buffer_cmpswap_payload_width_is_independent_of_element_width(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp index d1010e25a9db..1d82aa44c2bf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp @@ -6,6 +6,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand_types.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" +#include "rocjitsu/vm/amdgpu/lds.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" @@ -117,7 +118,7 @@ void flat_global_calculate_addresses(const Inst &inst, amdgpu::Wavefront &wf, auto &cu = wf.cu(); init_vector_mem_state(wf, d); uint64_t exec = d.exec_mask; - int64_t offset = static_cast(static_cast(inst.ioffset << 8) >> 8); + int64_t offset = static_cast(signed_ioffset(inst.ioffset)); bool saddr_present = has_saddr(inst.saddr); uint64_t saddr_val = saddr_present ? read_sreg64_operand(wf, inst.saddr) : 0; uint32_t scale = saddr_present && inst.scale_offset ? scaled_vaddr_factor(d) : 1; @@ -156,7 +157,7 @@ uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront & uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | amdgpu::RegisterAccess(cu).read_sgpr(sbase); - int64_t off = static_cast(static_cast(inst.ioffset << 8) >> 8); + int64_t off = static_cast(signed_ioffset(inst.ioffset)); uint32_t scale = inst.scale_offset ? access_size_bytes : 1; if (has_smem_offset(inst.soffset)) off += static_cast(read_sreg_m0_operand(wf, inst.soffset)) * scale; @@ -176,12 +177,24 @@ void flat_calculate_addresses(const VglobalMachineInst &inst, amdgpu::Wavefront flat_global_calculate_addresses(inst, wf, d, false); } +uint32_t async_lds_lane_address(const VglobalMachineInst &inst, const amdgpu::Wavefront &wf, + uint32_t lds_operand, uint32_t access_size_bytes) { + int64_t relative_addr = static_cast(lds_operand) + signed_ioffset(inst.ioffset); + if (relative_addr < 0 || static_cast(relative_addr) + access_size_bytes > wf.lds_size()) + return amdgpu::kInvalidLdsAddress; + + uint64_t absolute_addr = static_cast(wf.lds_base()) + relative_addr; + if (absolute_addr >= UINT32_MAX) + return amdgpu::kInvalidLdsAddress; + return static_cast(absolute_addr); +} + void flat_calculate_addresses(const VscratchMachineInst &inst, amdgpu::Wavefront &wf, amdgpu::VectorMemState &d) { auto &cu = wf.cu(); init_vector_mem_state(wf, d); uint64_t exec = d.exec_mask; - int64_t offset = static_cast(static_cast(inst.ioffset << 8) >> 8); + int64_t offset = static_cast(signed_ioffset(inst.ioffset)); uint64_t scratch_base = wf.scratch_base(); uint32_t saddr_val = 0; if (has_saddr(inst.saddr)) @@ -225,7 +238,7 @@ void mubuf_calculate_addresses(const VbufferMachineInst &inst, amdgpu::Wavefront uint32_t stride = buffer_stride(srd3); bool oob_raw = buffer_oob_raw(srd3); uint32_t soffset_val = has_smem_offset(inst.soffset) ? read_sreg_m0_operand(wf, inst.soffset) : 0; - int64_t ioff = static_cast(static_cast(inst.ioffset << 8) >> 8); + int64_t ioff = static_cast(signed_ioffset(inst.ioffset)); uint32_t vbase = 0; if (inst.idxen || inst.offen) vbase = resolved_vgpr_base(wf, inst.vaddr, amdgpu::VgprMsbRole::Src0); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h index ecf38bf4bfb5..2b954116be6c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h @@ -18,6 +18,9 @@ struct VectorMemState; namespace rocjitsu::cdna5 { +/// @brief Sign-extend a CDNA5 24-bit IOFFSET field. +inline int32_t signed_ioffset(uint32_t ioffset) { return static_cast(ioffset << 8) >> 8; } + uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf, uint32_t access_size_bytes); @@ -27,6 +30,14 @@ void flat_calculate_addresses(const VflatMachineInst &inst, amdgpu::Wavefront &w void flat_calculate_addresses(const VglobalMachineInst &inst, amdgpu::Wavefront &wf, amdgpu::VectorMemState &d); +/// @brief Compute an absolute async LDS address within the workgroup allocation. +/// +/// @returns amdgpu::kInvalidLdsAddress when any byte in the access is outside +/// the allocation or the absolute address equals the reserved invalid value or +/// cannot be represented in 32 bits. +uint32_t async_lds_lane_address(const VglobalMachineInst &inst, const amdgpu::Wavefront &wf, + uint32_t lds_operand, uint32_t access_size_bytes); + void flat_calculate_addresses(const VscratchMachineInst &inst, amdgpu::Wavefront &wf, amdgpu::VectorMemState &d); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal_exec.cpp index a6dd7722cf4d..dd0c124b24be 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal_exec.cpp @@ -470,7 +470,7 @@ void GlobalLoadAddtidB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { d->wf_id = wf.wf_id(); d->cu_path = wf.cu().full_path(); uint64_t base = amdgpu::RegisterAccess(wf).read_scalar64(saddr); - int64_t offset = static_cast(static_cast(inst_.ioffset << 8) >> 8); + int64_t offset = static_cast(signed_ioffset(inst_.ioffset)); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; @@ -498,7 +498,7 @@ void GlobalStoreAddtidB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { d->wf_id = wf.wf_id(); d->cu_path = wf.cu().full_path(); uint64_t base = amdgpu::RegisterAccess(wf).read_scalar64(saddr); - int64_t offset = static_cast(static_cast(inst_.ioffset << 8) >> 8); + int64_t offset = static_cast(signed_ioffset(inst_.ioffset)); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; @@ -1726,7 +1726,7 @@ void GlobalLoadAsyncToLdsB8Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -1734,7 +1734,7 @@ void GlobalLoadAsyncToLdsB8Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 1); } set_data(std::move(d)); } @@ -1753,7 +1753,7 @@ void GlobalLoadAsyncToLdsB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -1761,7 +1761,7 @@ void GlobalLoadAsyncToLdsB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 4); } set_data(std::move(d)); } @@ -1780,7 +1780,7 @@ void GlobalLoadAsyncToLdsB64Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -1788,7 +1788,7 @@ void GlobalLoadAsyncToLdsB64Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 8); } set_data(std::move(d)); } @@ -1807,7 +1807,7 @@ void GlobalLoadAsyncToLdsB128Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -1815,7 +1815,7 @@ void GlobalLoadAsyncToLdsB128Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 16); } set_data(std::move(d)); } @@ -1832,7 +1832,7 @@ void GlobalStoreAsyncFromLdsB8Vglobal::execute_impl(amdgpu::Wavefront &wf) { auto &cu = wf.cu(); const auto &lds = cu.lds(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vsrc.opr_type_, vsrc.encoding_value_, vsrc.vgpr_msb_role()); @@ -1840,7 +1840,9 @@ void GlobalStoreAsyncFromLdsB8Vglobal::execute_impl(amdgpu::Wavefront &wf) { for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; - uint32_t lds_addr = wf.lds_base() + amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lds_addr = async_lds_lane_address(inst_, wf, lane_lds_addr, 1); + // Out-of-range LDS reads return zero; the global store still issues. lds.read(lds_addr, &d->store_data[lane * 1], 1); } set_data(std::move(d)); @@ -1858,7 +1860,7 @@ void GlobalStoreAsyncFromLdsB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { auto &cu = wf.cu(); const auto &lds = cu.lds(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vsrc.opr_type_, vsrc.encoding_value_, vsrc.vgpr_msb_role()); @@ -1866,7 +1868,9 @@ void GlobalStoreAsyncFromLdsB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; - uint32_t lds_addr = wf.lds_base() + amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lds_addr = async_lds_lane_address(inst_, wf, lane_lds_addr, 4); + // Out-of-range LDS reads return zero; the global store still issues. lds.read(lds_addr, &d->store_data[lane * 4], 4); } set_data(std::move(d)); @@ -1884,7 +1888,7 @@ void GlobalStoreAsyncFromLdsB64Vglobal::execute_impl(amdgpu::Wavefront &wf) { auto &cu = wf.cu(); const auto &lds = cu.lds(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vsrc.opr_type_, vsrc.encoding_value_, vsrc.vgpr_msb_role()); @@ -1892,7 +1896,9 @@ void GlobalStoreAsyncFromLdsB64Vglobal::execute_impl(amdgpu::Wavefront &wf) { for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; - uint32_t lds_addr = wf.lds_base() + amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lds_addr = async_lds_lane_address(inst_, wf, lane_lds_addr, 8); + // Out-of-range LDS reads return zero; the global store still issues. lds.read(lds_addr, &d->store_data[lane * 8], 8); } set_data(std::move(d)); @@ -1910,7 +1916,7 @@ void GlobalStoreAsyncFromLdsB128Vglobal::execute_impl(amdgpu::Wavefront &wf) { auto &cu = wf.cu(); const auto &lds = cu.lds(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vsrc.opr_type_, vsrc.encoding_value_, vsrc.vgpr_msb_role()); @@ -1918,7 +1924,9 @@ void GlobalStoreAsyncFromLdsB128Vglobal::execute_impl(amdgpu::Wavefront &wf) { for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; - uint32_t lds_addr = wf.lds_base() + amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); + uint32_t lds_addr = async_lds_lane_address(inst_, wf, lane_lds_addr, 16); + // Out-of-range LDS reads return zero; the global store still issues. lds.read(lds_addr, &d->store_data[lane * 16], 16); } set_data(std::move(d)); @@ -1989,7 +1997,7 @@ void ClusterLoadAsyncToLdsB8Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -1997,7 +2005,7 @@ void ClusterLoadAsyncToLdsB8Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 1); } set_data(std::move(d)); } @@ -2019,7 +2027,7 @@ void ClusterLoadAsyncToLdsB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -2027,7 +2035,7 @@ void ClusterLoadAsyncToLdsB32Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 4); } set_data(std::move(d)); } @@ -2049,7 +2057,7 @@ void ClusterLoadAsyncToLdsB64Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -2057,7 +2065,7 @@ void ClusterLoadAsyncToLdsB64Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 8); } set_data(std::move(d)); } @@ -2079,7 +2087,7 @@ void ClusterLoadAsyncToLdsB128Vglobal::execute_impl(amdgpu::Wavefront &wf) { flat_calculate_addresses(inst_, wf, *d); auto &cu = wf.cu(); uint64_t exec = wf.exec(); - // flat_calculate_addresses applies ioffset to the global side; the LDS operand is independent. + // CDNA5 ISA 10.8.1 and expressions 95-102 and 106-109 add IOFFSET to global and LDS addresses. uint32_t lds_addr_base = wf.vgpr_alloc().base + *Isa::resolved_vgpr_offset(wf, vdst.opr_type_, vdst.encoding_value_, vdst.vgpr_msb_role()); @@ -2087,7 +2095,7 @@ void ClusterLoadAsyncToLdsB128Vglobal::execute_impl(amdgpu::Wavefront &wf) { if (!(exec & (1ULL << lane))) continue; uint32_t lane_lds_addr = amdgpu::RegisterAccess(cu).read_vgpr(lds_addr_base, lane); - d->per_lane_lds_addr[lane] = wf.lds_base() + lane_lds_addr; + d->per_lane_lds_addr[lane] = async_lds_lane_address(inst_, wf, lane_lds_addr, 16); } set_data(std::move(d)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.cpp index f4606e877b86..fefb46ba9b4d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.cpp @@ -35,34 +35,42 @@ void write_cluster_lds_target(const ClusterLdsMulticastTransaction &txn, "cluster LDS multicast payload too small: lane={} offset={} bytes={} payload={}", lane, data_offset, txn.bytes_per_lane, txn.payload.size())); } - uint32_t lds_addr = cluster_lds_lane_addr(txn, lane, target.lds_base); - if (uint64_t(lds_addr) + txn.bytes_per_lane > lds.size_bytes()) { - throw std::runtime_error(std::format( - "cluster LDS multicast target address out of range: lane={} target_wg={} addr={:#x} " - "bytes={} lds_size={}", - lane, target.wg_id, lds_addr, txn.bytes_per_lane, lds.size_bytes())); + uint64_t lds_addr = cluster_lds_lane_addr(txn, lane, target.lds_base); + if (txn.per_lane_addr && lds_addr == kInvalidLdsAddress) + continue; + if (lds_addr + txn.bytes_per_lane > lds.size_bytes()) { + if (!txn.per_lane_addr) { + throw std::runtime_error(std::format( + "cluster LDS multicast target out of range: lane={} wg={} address={:#x} bytes={} " + "LDS={}", + lane, target.wg_id, lds_addr, txn.bytes_per_lane, lds.size_bytes())); + } + continue; } for (uint32_t b = 0; b < txn.bytes_per_lane; ++b) - lds.write8(lds_addr + b, txn.payload[data_offset + b]); + lds.write8(static_cast(lds_addr + b), txn.payload[data_offset + b]); } } } // namespace -uint32_t remap_cluster_lds_addr(uint32_t source_lds_base, uint32_t target_lds_base, - uint32_t source_lds_addr) { +uint64_t remap_cluster_lds_addr(uint32_t source_lds_base, uint32_t target_lds_base, + uint64_t source_lds_addr) { if (source_lds_addr < source_lds_base) { throw std::runtime_error(std::format("cluster LDS source address {:#x} precedes base {:#x}", source_lds_addr, source_lds_base)); } - return target_lds_base + (source_lds_addr - source_lds_base); + return static_cast(target_lds_base) + (source_lds_addr - source_lds_base); } -uint32_t cluster_lds_lane_addr(const ClusterLdsMulticastTransaction &txn, uint32_t lane, +uint64_t cluster_lds_lane_addr(const ClusterLdsMulticastTransaction &txn, uint32_t lane, uint32_t target_lds_base) { - uint32_t source_lds_addr = txn.source_lds_base + lane * txn.bytes_per_lane; - if (txn.per_lane_addr) + uint64_t source_lds_addr = static_cast(txn.source_lds_base) + lane * txn.bytes_per_lane; + if (txn.per_lane_addr) { source_lds_addr = txn.per_lane_lds_addr[lane]; + if (source_lds_addr == kInvalidLdsAddress || source_lds_addr < txn.source_lds_base) + return kInvalidLdsAddress; + } return remap_cluster_lds_addr(txn.source_lds_base, target_lds_base, source_lds_addr); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.h index 6d7de48a210b..b162b25eb06a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/cluster_lds_multicast.h @@ -62,15 +62,15 @@ enum class [[nodiscard]] ClusterLdsMulticastResult { using ClusterLdsMulticastCompletion = std::function; /// @brief Remap a source WG LDS address into an equivalent target WG LDS window. -uint32_t remap_cluster_lds_addr(uint32_t source_lds_base, uint32_t target_lds_base, - uint32_t source_lds_addr); +uint64_t remap_cluster_lds_addr(uint32_t source_lds_base, uint32_t target_lds_base, + uint64_t source_lds_addr); /// @brief Return the lane LDS address remapped into one target LDS window. /// /// @details Immediate functional writeback only uses this with the issuing /// participant's own target, where the remap is identity. Deferred/timing /// backends can reuse it when modeling peer-visible multicast responses. -uint32_t cluster_lds_lane_addr(const ClusterLdsMulticastTransaction &txn, uint32_t lane, +uint64_t cluster_lds_lane_addr(const ClusterLdsMulticastTransaction &txn, uint32_t lane, uint32_t target_lds_base); /// @brief Return true when the transaction mask selects the issuing workgroup. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp index 813a67aa9778..7ac10722dfc6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp @@ -1040,6 +1040,7 @@ uint32_t CommandProcessor::dispatch_workgroups(DispatchEntry &entry) { for (uint32_t w = 0; w < entry.wfs_per_workgroup; ++w) { Wavefront *wf = wg_wavefronts[w]; wf->set_lds_base(lds_base); + wf->set_lds_size(aligned_lds_bytes_per_workgroup(entry)); wf->set_lds(placement.lds); wf->set_dispatch_id(entry.dispatch_id); wf->set_process_id(entry.process_id); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds.h index 920d50703e3c..ad4274a13bd7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds.h @@ -14,6 +14,9 @@ namespace rocjitsu { namespace amdgpu { +/// Reserved value used when an instruction lane has no valid LDS address. +constexpr uint32_t kInvalidLdsAddress = UINT32_MAX; + /// @brief Local Data Share (LDS) memory backing for a dispatch placement. /// /// @details CU-mode workgroups use the backing owned by one ComputeUnitCore. @@ -44,7 +47,7 @@ class Lds : public simdojo::MemoryInterface { /// @brief Read 16 bits (little-endian) from LDS. OOB returns 0. uint16_t read16(uint32_t addr) const { - if (addr + 1 >= data_.size()) + if (!contains(addr, 2)) return 0; uint16_t val; std::memcpy(&val, &data_[addr], 2); @@ -53,14 +56,14 @@ class Lds : public simdojo::MemoryInterface { /// @brief Write 16 bits (little-endian) to LDS. OOB writes are dropped. void write16(uint32_t addr, uint16_t val) { - if (addr + 1 >= data_.size()) + if (!contains(addr, 2)) return; std::memcpy(&data_[addr], &val, 2); } /// @brief Read 32 bits (little-endian) from LDS. OOB returns 0. uint32_t read32(uint32_t addr) const { - if (addr + 3 >= data_.size()) + if (!contains(addr, 4)) return 0; uint32_t val; std::memcpy(&val, &data_[addr], 4); @@ -69,14 +72,14 @@ class Lds : public simdojo::MemoryInterface { /// @brief Write 32 bits (little-endian) to LDS. OOB writes are dropped. void write32(uint32_t addr, uint32_t val) { - if (addr + 3 >= data_.size()) + if (!contains(addr, 4)) return; std::memcpy(&data_[addr], &val, 4); } /// @brief Read 64 bits (little-endian) from LDS. OOB returns 0. uint64_t read64(uint32_t addr) const { - if (addr + 7 >= data_.size()) + if (!contains(addr, 8)) return 0; uint64_t val; std::memcpy(&val, &data_[addr], 8); @@ -85,14 +88,14 @@ class Lds : public simdojo::MemoryInterface { /// @brief Write 64 bits (little-endian) to LDS. OOB writes are dropped. void write64(uint32_t addr, uint64_t val) { - if (addr + 7 >= data_.size()) + if (!contains(addr, 8)) return; std::memcpy(&data_[addr], &val, 8); } /// @brief Bulk read of arbitrary size from LDS. OOB returns 0. void read(uint32_t addr, uint8_t *dst, uint32_t size) const { - if (addr + size > data_.size()) { + if (!contains(addr, size)) { std::memset(dst, 0, size); return; } @@ -101,7 +104,7 @@ class Lds : public simdojo::MemoryInterface { /// @brief Bulk write of arbitrary size to LDS. OOB writes are dropped. void write(uint32_t addr, const uint8_t *src, uint32_t size) { - if (addr + size > data_.size()) + if (!contains(addr, size)) return; std::memcpy(&data_[addr], src, size); } @@ -109,14 +112,14 @@ class Lds : public simdojo::MemoryInterface { /// @brief MemoryInterface read (truncates addr to 32-bit local address). void read(uint64_t addr, uint8_t *dst, uint32_t size) override { auto a = static_cast(addr); - assert(a + size <= data_.size()); + assert(contains(a, size)); std::memcpy(dst, &data_[a], size); } /// @brief MemoryInterface write (truncates addr to 32-bit local address). void write(uint64_t addr, const uint8_t *src, uint32_t size) override { auto a = static_cast(addr); - assert(a + size <= data_.size()); + assert(contains(a, size)); std::memcpy(&data_[a], src, size); } @@ -182,6 +185,10 @@ class Lds : public simdojo::MemoryInterface { uint8_t *data() { return data_.data(); } private: + bool contains(uint32_t addr, uint32_t size) const { + return static_cast(addr) + size <= data_.size(); + } + std::vector data_; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp index 72367e4f0438..566606290a64 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp @@ -69,6 +69,8 @@ void write_lds_dst_load_direct(const VectorMemState &d, Lds &lds, uint32_t per_l } uint32_t lds_addr = d.lds_per_lane_addr ? d.per_lane_lds_addr[lane] : d.lds_base + lane * per_lane_bytes; + if (lds_addr == kInvalidLdsAddress) + continue; lds.write(lds_addr, &d.response_data[data_offset], per_lane_bytes); } } @@ -100,6 +102,10 @@ MemoryAccessCompletion complete_lds_dst_load(VectorMemState &d, Wavefront &wf, C std::memcpy(&v, &d.response_data[ln * per_lane_bytes], 4); uint32_t lds_addr = d.lds_per_lane_addr ? d.per_lane_lds_addr[ln] : d.lds_base + ln * per_lane_bytes; + if (lds_addr == kInvalidLdsAddress) { + os << std::format(" L{}:@{:#x}->lds[dropped]", ln, d.per_lane_addr[ln]); + continue; + } os << std::format(" L{}:@{:#x}->lds[{:#x}]={:#x}", ln, d.per_lane_addr[ln], lds_addr, v); } }); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h index 295a9f51044c..a20af86c4ca2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h @@ -111,6 +111,7 @@ class ShaderProcessorInput { wg.entry->sgprs_per_wf, wg.entry->vgprs_per_wf); assert(wf && "dispatch_wf failed after select_cu returned a CU"); wf->set_lds_base(lds_base); + wf->set_lds_size(util::align_up(wg.entry->group_segment_fixed_size, 256u)); wf->set_lds(placement->lds); wf->set_dispatch_id(wg.entry->dispatch_id); wf->set_process_id(wg.entry->process_id); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h index 1e67d43a65dc..51427b0ae2b6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h @@ -170,6 +170,12 @@ class Wavefront : public ThreadContext { /// @brief Set the per-WG LDS base offset. void set_lds_base(uint32_t base) { lds_base_ = base; } + /// @brief Return the aligned LDS allocation size for this workgroup. + uint32_t lds_size() const { return lds_size_; } + + /// @brief Set the aligned LDS allocation size for this workgroup. + void set_lds_size(uint32_t size) { lds_size_ = size; } + /// @brief Return the LDS backing selected for this workgroup placement. /// /// CU-mode workgroups use their owning CU's LDS. WGP-mode workgroups can @@ -476,6 +482,7 @@ class Wavefront : public ThreadContext { dispatch_id_ = 0; process_id_ = 0; lds_base_ = 0; + lds_size_ = 0; lds_ = nullptr; cluster_rank_ = 0; cluster_size_ = 1; @@ -520,6 +527,7 @@ class Wavefront : public ThreadContext { uint32_t dispatch_id_ = 0; ///< Dispatch ID (set per dispatch, unique per dispatch). uint32_t process_id_ = 0; ///< Owning process ID (PASID analog, set per dispatch). uint32_t lds_base_ = 0; ///< Per-WG LDS base offset (set per dispatch). + uint32_t lds_size_ = 0; ///< Aligned per-WG LDS allocation size. Lds *lds_ = nullptr; ///< Placement-selected LDS backing; nullptr means CU-local LDS. uint32_t cluster_rank_ = 0; ///< Workgroup rank inside the dispatch cluster. uint32_t cluster_size_ = 1; ///< Number of workgroups in the dispatch cluster. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/plugin.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/plugin.cpp index 63a9dbf0a910..fea188bbade5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/plugin.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/plugin.cpp @@ -4,6 +4,7 @@ #include "rocjitsu/vm/plugins/race_detector/plugin.h" #include "rocjitsu/isa/instruction.h" +#include "rocjitsu/vm/amdgpu/lds.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/wavefront.h" #include "util/log.h" @@ -297,10 +298,14 @@ void RaceDetectorPlugin::onAmdgpuRouteMemoryInstruction(const Instruction &inst, return; } uint32_t ldsAddrs[64]; - for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) + uint64_t validLaneMask = d.lane_mask; + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { ldsAddrs[lane] = d.lds_per_lane_addr ? d.per_lane_lds_addr[lane] : d.lds_base + lane * perLaneBytes; - rs->registerLdsEvent(wf.pc, MemoryEventType::GLOBAL_TO_LDS, {}, d.lane_mask, wf.wf_size(), + if (ldsAddrs[lane] == amdgpu::kInvalidLdsAddress) + validLaneMask &= ~(1ULL << lane); + } + rs->registerLdsEvent(wf.pc, MemoryEventType::GLOBAL_TO_LDS, {}, validLaneMask, wf.wf_size(), std::span(ldsAddrs, wf.wf_size()), perLaneBytes); } else if (d.is_load && d.dst_reg_base >= wf.vgpr_alloc().base) { uint32_t logicalBase = d.dst_reg_base - wf.vgpr_alloc().base; diff --git a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp index eeeff178f054..33f09bfe2772 100644 --- a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: MIT #include "cdna5_sim_test_common.h" +#include "rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h" namespace { @@ -68,6 +69,7 @@ TEST(Gfx1250ExecutionTest, ClusterLoadsDecodeAndPopulateVectorMemState) { ASSERT_NE(wf, nullptr); wf->set_exec(0x3u); wf->set_lds_base(cu->allocate_lds(256)); + wf->set_lds_size(256); wf->set_m0(0xffff0003u); constexpr uint64_t kGlobalBase = 0x180000u; @@ -75,9 +77,9 @@ TEST(Gfx1250ExecutionTest, ClusterLoadsDecodeAndPopulateVectorMemState) { write_wave_sgpr(*cu, *wf, 1, static_cast(kGlobalBase >> 32)); const uint32_t vgpr_base = wf->vgpr_alloc().base; - auto write_vgpr_lane_offsets = [&](uint32_t reg, uint32_t stride) { - cu->write_vgpr(vgpr_base + reg, 0, 0); - cu->write_vgpr(vgpr_base + reg, 1, stride); + auto write_vgpr_lane_offsets = [&](uint32_t reg, uint32_t stride, uint32_t base_offset = 0) { + cu->write_vgpr(vgpr_base + reg, 0, base_offset); + cu->write_vgpr(vgpr_base + reg, 1, base_offset + stride); }; auto write_vgpr_lane_indices = [&](uint32_t reg) { cu->write_vgpr(vgpr_base + reg, 0, 0); @@ -131,70 +133,87 @@ TEST(Gfx1250ExecutionTest, ClusterLoadsDecodeAndPopulateVectorMemState) { uint32_t lds_addr_reg; uint32_t global_stride; uint32_t lds_stride; - uint32_t offset; + uint32_t base_offset; + int32_t instruction_offset; bool scale_offset; bool cluster_multicast; }; const AsyncCase async_cases[] = { - {{0xEE1A8000u, 0x00000000u, 0x00000000u}, - "cluster_load_async_to_lds_b8", - 1, - 1, - 0, - 1, - 1, - 0, - false, - true}, - {{0xEE180000u, 0x00000000u, 0x00000800u}, - "global_load_async_to_lds_b32", - 4, - 1, - 0, - 16, - 16, - 8, - false, - false}, - {{0xEE1AC000u, 0x00000000u, 0x00000800u}, - "cluster_load_async_to_lds_b32", - 4, - 1, - 0, - 16, - 16, - 8, - false, - true}, - {{0xEE1B0000u, 0x00000004u, 0x00000004u}, - "cluster_load_async_to_lds_b64", - 4, - 2, - 4, - 16, - 16, - 0, - false, - true}, - {{0xEE1B4000u, 0x00010001u, 0x00000000u}, - "cluster_load_async_to_lds_b128", - 4, - 4, - 1, - 16, - 16, - 0, - true, - true}, + {.words = {0xEE1A8000u, 0x00000000u, 0x00000000u}, + .mnemonic = "cluster_load_async_to_lds_b8", + .elem_size = 1, + .num_elems = 1, + .lds_addr_reg = 0, + .global_stride = 1, + .lds_stride = 1, + .base_offset = 0, + .instruction_offset = 0, + .scale_offset = false, + .cluster_multicast = true}, + {.words = {0xEE180000u, 0x00000000u, 0x00000800u}, + .mnemonic = "global_load_async_to_lds_b32", + .elem_size = 4, + .num_elems = 1, + .lds_addr_reg = 0, + .global_stride = 16, + .lds_stride = 16, + .base_offset = 0, + .instruction_offset = 8, + .scale_offset = false, + .cluster_multicast = false}, + {.words = {0xEE1AC000u, 0x00000000u, 0x00000800u}, + .mnemonic = "cluster_load_async_to_lds_b32", + .elem_size = 4, + .num_elems = 1, + .lds_addr_reg = 0, + .global_stride = 16, + .lds_stride = 16, + .base_offset = 0, + .instruction_offset = 8, + .scale_offset = false, + .cluster_multicast = true}, + {.words = {0xEE1AC000u, 0x00000000u, 0xFFFFC000u}, + .mnemonic = "cluster_load_async_to_lds_b32", + .elem_size = 4, + .num_elems = 1, + .lds_addr_reg = 0, + .global_stride = 16, + .lds_stride = 16, + .base_offset = 128, + .instruction_offset = -64, + .scale_offset = false, + .cluster_multicast = true}, + {.words = {0xEE1B0000u, 0x00000004u, 0x00000004u}, + .mnemonic = "cluster_load_async_to_lds_b64", + .elem_size = 4, + .num_elems = 2, + .lds_addr_reg = 4, + .global_stride = 16, + .lds_stride = 16, + .base_offset = 0, + .instruction_offset = 0, + .scale_offset = false, + .cluster_multicast = true}, + {.words = {0xEE1B4000u, 0x00010001u, 0x00000800u}, + .mnemonic = "cluster_load_async_to_lds_b128", + .elem_size = 4, + .num_elems = 4, + .lds_addr_reg = 1, + .global_stride = 16, + .lds_stride = 16, + .base_offset = 0, + .instruction_offset = 8, + .scale_offset = true, + .cluster_multicast = true}, }; for (const AsyncCase &tc : async_cases) { if (tc.scale_offset) { write_vgpr_lane_indices(0); - write_vgpr_lane_offsets(tc.lds_addr_reg, 16); + write_vgpr_lane_offsets(tc.lds_addr_reg, 16, tc.base_offset); } else { - write_vgpr_lane_offsets(tc.lds_addr_reg, tc.global_stride); + write_vgpr_lane_offsets(tc.lds_addr_reg, tc.global_stride, tc.base_offset); } auto inst = decode_gfx1250(tc.words, tc.mnemonic); @@ -214,36 +233,45 @@ TEST(Gfx1250ExecutionTest, ClusterLoadsDecodeAndPopulateVectorMemState) { EXPECT_EQ(state->request_force_l1_bypass, tc.cluster_multicast); EXPECT_EQ(state->wait_counter_type, amdgpu::WaitCounterType::ASYNCCNT); EXPECT_EQ(state->lane_mask, 0x3u); - EXPECT_EQ(state->per_lane_addr[0], kGlobalBase + tc.offset); - EXPECT_EQ(state->per_lane_addr[1], kGlobalBase + tc.offset + tc.global_stride); - EXPECT_EQ(state->per_lane_lds_addr[0], wf->lds_base()); - EXPECT_EQ(state->per_lane_lds_addr[1], wf->lds_base() + tc.lds_stride); + uint64_t expected_global_base = static_cast( + static_cast(kGlobalBase + tc.base_offset) + tc.instruction_offset); + uint32_t expected_lds_offset = tc.base_offset + static_cast(tc.instruction_offset); + EXPECT_EQ(state->per_lane_addr[0], expected_global_base); + EXPECT_EQ(state->per_lane_addr[1], expected_global_base + tc.global_stride); + EXPECT_EQ(state->per_lane_lds_addr[0], wf->lds_base() + expected_lds_offset); + EXPECT_EQ(state->per_lane_lds_addr[1], wf->lds_base() + expected_lds_offset + tc.lds_stride); } } -TEST(Gfx1250ExecutionTest, GlobalStoreAsyncFromLdsKeepsIoffsetOnGlobalDestination) { +TEST(Gfx1250ExecutionTest, GlobalStoreAsyncFromLdsAppliesIoffsetToGlobalAndLdsSource) { Gfx1250Sim sim; auto *cu = sim.cu(); auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); ASSERT_NE(wf, nullptr); wf->set_exec(0x3u); wf->set_lds_base(cu->allocate_lds(256)); + wf->set_lds_size(256); constexpr uint64_t kGlobalBase = 0x190000u; constexpr uint32_t kLane0Value = 0x12345678u; constexpr uint32_t kLane1Value = 0xabcdef01u; - constexpr uint32_t kIoffset = 8; + constexpr uint32_t kVgprOffset = 128; + constexpr int32_t kIoffset = -64; + constexpr uint32_t kEffectiveOffset = + static_cast(static_cast(kVgprOffset) + kIoffset); write_wave_sgpr(*cu, *wf, 0, static_cast(kGlobalBase)); write_wave_sgpr(*cu, *wf, 1, static_cast(kGlobalBase >> 32)); const uint32_t vgpr_base = wf->vgpr_alloc().base; - cu->write_vgpr(vgpr_base, 0, 0); - cu->write_vgpr(vgpr_base, 1, 16); - cu->lds().write32(wf->lds_base(), kLane0Value); - cu->lds().write32(wf->lds_base() + 16, kLane1Value); + cu->write_vgpr(vgpr_base, 0, kVgprOffset); + cu->write_vgpr(vgpr_base, 1, kVgprOffset + 16); + cu->lds().write32(wf->lds_base() + kVgprOffset, ~kLane0Value); + cu->lds().write32(wf->lds_base() + kVgprOffset + 16, ~kLane1Value); + cu->lds().write32(wf->lds_base() + kEffectiveOffset, kLane0Value); + cu->lds().write32(wf->lds_base() + kEffectiveOffset + 16, kLane1Value); auto inst = - decode_gfx1250({0xEE190000u, 0x00000000u, 0x00000800u}, "global_store_async_from_lds_b32"); + decode_gfx1250({0xEE190000u, 0x00000000u, 0xFFFFC000u}, "global_store_async_from_lds_b32"); ASSERT_NE(inst, nullptr); inst->execute(*inst, wf); auto *state = inst->data_as(); @@ -252,8 +280,8 @@ TEST(Gfx1250ExecutionTest, GlobalStoreAsyncFromLdsKeepsIoffsetOnGlobalDestinatio EXPECT_FALSE(state->is_load); EXPECT_EQ(state->wait_counter_type, amdgpu::WaitCounterType::ASYNCCNT); EXPECT_EQ(state->lane_mask, 0x3u); - EXPECT_EQ(state->per_lane_addr[0], kGlobalBase + kIoffset); - EXPECT_EQ(state->per_lane_addr[1], kGlobalBase + 16 + kIoffset); + EXPECT_EQ(state->per_lane_addr[0], kGlobalBase + kEffectiveOffset); + EXPECT_EQ(state->per_lane_addr[1], kGlobalBase + kEffectiveOffset + 16); ASSERT_GE(state->store_data.size(), 8u); uint32_t lane0_value = 0; @@ -264,6 +292,51 @@ TEST(Gfx1250ExecutionTest, GlobalStoreAsyncFromLdsKeepsIoffsetOnGlobalDestinatio EXPECT_EQ(lane1_value, kLane1Value); } +TEST(Gfx1250ExecutionTest, GlobalStoreAsyncFromOutOfRangeLdsSourceProducesZeroPayload) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_exec(0x1u); + wf->set_lds_base(cu->allocate_lds(256)); + wf->set_lds_size(256); + + constexpr uint64_t kGlobalBase = 0x1a0000u; + write_wave_sgpr(*cu, *wf, 0, static_cast(kGlobalBase)); + write_wave_sgpr(*cu, *wf, 1, static_cast(kGlobalBase >> 32)); + cu->write_vgpr(wf->vgpr_alloc().base, 0, 256); + + auto inst = + decode_gfx1250({0xEE190000u, 0x00000000u, 0x00000000u}, "global_store_async_from_lds_b32"); + ASSERT_NE(inst, nullptr); + inst->execute(*inst, wf); + auto *state = inst->data_as(); + ASSERT_NE(state, nullptr); + EXPECT_EQ(state->lane_mask, 0x1u); + ASSERT_GE(state->store_data.size(), sizeof(uint32_t)); + uint32_t value = UINT32_MAX; + std::memcpy(&value, state->store_data.data(), sizeof(value)); + EXPECT_EQ(value, 0u); +} + +TEST(Gfx1250ExecutionTest, AsyncLdsAddressRejectsAccessOutsideAllocation) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + wf->set_lds_size(256); + + cdna5::VglobalMachineInst inst{}; + inst.ioffset = 0xfffffcu; + EXPECT_EQ(cdna5::signed_ioffset(inst.ioffset), -4); + EXPECT_EQ(cdna5::async_lds_lane_address(inst, *wf, 0, 4), amdgpu::kInvalidLdsAddress); + EXPECT_EQ(cdna5::async_lds_lane_address(inst, *wf, 8, 4), wf->lds_base() + 4); + EXPECT_EQ(cdna5::async_lds_lane_address(inst, *wf, 256, 4), wf->lds_base() + 252); + EXPECT_EQ(cdna5::async_lds_lane_address(inst, *wf, 256, 16), amdgpu::kInvalidLdsAddress); + EXPECT_EQ(cdna5::async_lds_lane_address(inst, *wf, 260, 4), amdgpu::kInvalidLdsAddress); +} + TEST(Gfx1250ExecutionTest, DispatchEntryClusterMathCoversMultiDimensionalShapes) { auto expect_rank_period = [](const amdgpu::DispatchEntry &candidate, uint64_t expected_period) { ASSERT_TRUE(candidate.cluster_grid_is_complete()); @@ -523,7 +596,7 @@ TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineRejectsUndersizedPa EXPECT_THROW((void)engine.submit(std::move(txn), []() {}), std::runtime_error); } -TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineRejectsOutOfRangeTarget) { +TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineDropsOutOfRangeTarget) { Gfx1250Sim sim; auto *cu = sim.cu(); @@ -538,10 +611,72 @@ TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineRejectsOutOfRangeTa txn.targets = {{cu, /*wg_id=*/0, static_cast(cu->lds().size_bytes()) - 2, /*cluster_rank=*/0}}; + amdgpu::ImmediateClusterLdsMulticastEngine engine; + EXPECT_EQ(engine.submit(std::move(txn), []() {}), amdgpu::ClusterLdsMulticastResult::Complete); +} + +TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineRejectsStridedOutOfRangeTarget) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + + amdgpu::ClusterLdsMulticastTransaction txn{}; + txn.source_lds_base = 0; + txn.bytes_per_lane = 4; + txn.wf_size = 1; + txn.lane_mask = 0x1; + txn.payload.resize(4); + txn.targets = {{cu, /*wg_id=*/0, static_cast(cu->lds().size_bytes()) - 2, + /*cluster_rank=*/0}}; + amdgpu::ImmediateClusterLdsMulticastEngine engine; EXPECT_THROW((void)engine.submit(std::move(txn), []() {}), std::runtime_error); } +TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineDropsWidenedRemapOverflow) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + constexpr uint32_t kSentinel = 0xa5a5a5a5u; + cu->lds().write32(0, kSentinel); + + amdgpu::ClusterLdsMulticastTransaction txn{}; + txn.source_lds_base = 0x100; + txn.bytes_per_lane = 4; + txn.wf_size = 1; + txn.lane_mask = 0x1; + txn.per_lane_addr = true; + txn.per_lane_lds_addr[0] = 0xffffff00u; + txn.payload.resize(4, 0x5a); + txn.targets = {{cu, /*wg_id=*/0, /*lds_base=*/0x200, /*cluster_rank=*/0}}; + + EXPECT_EQ(amdgpu::cluster_lds_lane_addr(txn, 0, txn.targets[0].lds_base), 0x100000000ULL); + amdgpu::ImmediateClusterLdsMulticastEngine engine; + EXPECT_EQ(engine.submit(std::move(txn), []() {}), amdgpu::ClusterLdsMulticastResult::Complete); + EXPECT_EQ(cu->lds().read32(0), kSentinel); +} + +TEST(Gfx1250ExecutionTest, ImmediateClusterLdsMulticastEngineDropsInvalidSignedOffsetAddress) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + cu->clear_lds(); + + constexpr uint32_t kLdsBase = 0x200; + constexpr uint32_t kValue = 0x12345678; + amdgpu::ClusterLdsMulticastTransaction txn{}; + txn.source_lds_base = kLdsBase; + txn.bytes_per_lane = sizeof(kValue); + txn.wf_size = 1; + txn.lane_mask = 0x1; + txn.per_lane_addr = true; + txn.per_lane_lds_addr[0] = amdgpu::kInvalidLdsAddress; + txn.payload.resize(sizeof(kValue)); + std::memcpy(txn.payload.data(), &kValue, sizeof(kValue)); + txn.targets = {{cu, /*wg_id=*/0, kLdsBase, /*cluster_rank=*/0}}; + + amdgpu::ImmediateClusterLdsMulticastEngine engine; + EXPECT_EQ(engine.submit(std::move(txn), []() {}), amdgpu::ClusterLdsMulticastResult::Complete); + EXPECT_EQ(cu->lds().read32(kLdsBase), 0u); +} + TEST(Gfx1250ExecutionTest, ClusterLdsPinPreventsAllocatorReuseUntilClusterCompletes) { Gfx1250Sim sim; auto *cu = sim.cu(); @@ -1086,6 +1221,182 @@ TEST(Gfx1250SimulationTest, ClusterLoadAsyncToLdsWritesEachIssuingParticipant) { } } +TEST(Gfx1250SimulationTest, GlobalLoadAsyncToLdsDropsNetNegativeDestination) { + constexpr uint64_t kernel_addr = 0x10000; + constexpr uint64_t input_addr = 0x2600; + constexpr uint32_t lds_bytes_per_wg = 256; + constexpr uint32_t kSentinel = 0xa5a5a5a5u; + + const uint32_t code[] = { + 0xBE8000FFu, static_cast(input_addr + 4), // s_mov_b32 s0, input_addr + 4 + 0xBE810080u, // s_mov_b32 s1, 0 + 0x7E000280u, // v_mov_b32_e32 v0, 0 + 0xEE180000u, 0x00000000u, + 0xFFFFFC00u, // global_load_async_to_lds_b32 v0, v0, s[0:1] offset:-4 + 0xBFCA0000u, // s_wait_asynccnt 0 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + uint64_t kernel_object = sim.write_kernel(kernel_addr, code, std::size(code), 128); + sim.memory->write32(input_addr, 0x12345678u); + + hsa_kernel_dispatch_packet_t pkt{}; + pkt.header = HSA_PACKET_TYPE_KERNEL_DISPATCH; + pkt.setup = 1; + pkt.workgroup_size_x = 32; + pkt.workgroup_size_y = 1; + pkt.workgroup_size_z = 1; + pkt.grid_size_x = 32; + pkt.grid_size_y = 1; + pkt.grid_size_z = 1; + pkt.group_segment_size = lds_bytes_per_wg; + pkt.kernel_object = kernel_object; + test::AqlQueue queue(sim.memory, sim.cp()); + queue.submit(pkt); + ASSERT_TRUE(sim.engine->step()); + + auto *wf = sim.cu()->wf(0); + ASSERT_NE(wf, nullptr); + ASSERT_EQ(wf->lds_size(), lds_bytes_per_wg); + sim.cu()->lds().write32(wf->lds_base(), kSentinel); + EXPECT_NO_THROW(sim.engine->run()); + EXPECT_EQ(sim.cu()->lds().read32(wf->lds_base()), kSentinel); +} + +TEST(Gfx1250SimulationTest, GlobalLoadAsyncToLdsDropsDestinationPastWorkgroupAllocation) { + constexpr uint64_t kernel_addr = 0x10000; + constexpr uint64_t input_addr = 0x2800; + constexpr uint32_t lds_bytes_per_wg = 256; + constexpr uint32_t kSentinel = 0xa5a5a5a5u; + + const uint32_t code[] = { + 0xBE8000FFu, static_cast(input_addr - lds_bytes_per_wg), + 0xBE810080u, // s_mov_b32 s1, 0 + 0x7E000280u, // v_mov_b32_e32 v0, 0 + 0xEE180000u, 0x00000000u, + 0x00010000u, // global_load_async_to_lds_b32 v0, v0, s[0:1] offset:256 + 0xBFCA0000u, // s_wait_asynccnt 0 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + uint64_t kernel_object = sim.write_kernel(kernel_addr, code, std::size(code), 128); + sim.memory->write32(input_addr, 0x12345678u); + + hsa_kernel_dispatch_packet_t pkt{}; + pkt.header = HSA_PACKET_TYPE_KERNEL_DISPATCH; + pkt.setup = 1; + pkt.workgroup_size_x = 32; + pkt.workgroup_size_y = 1; + pkt.workgroup_size_z = 1; + pkt.grid_size_x = 32; + pkt.grid_size_y = 1; + pkt.grid_size_z = 1; + pkt.group_segment_size = lds_bytes_per_wg; + pkt.kernel_object = kernel_object; + test::AqlQueue queue(sim.memory, sim.cp()); + queue.submit(pkt); + ASSERT_TRUE(sim.engine->step()); + + auto *wf = sim.cu()->wf(0); + ASSERT_NE(wf, nullptr); + ASSERT_EQ(wf->lds_size(), lds_bytes_per_wg); + const uint32_t outside_allocation = wf->lds_base() + lds_bytes_per_wg; + sim.cu()->lds().write32(outside_allocation, kSentinel); + EXPECT_NO_THROW(sim.engine->run()); + EXPECT_EQ(sim.cu()->lds().read32(outside_allocation), kSentinel); +} + +TEST(Gfx1250SimulationTest, ClusterLoadAsyncToLdsDropsNetNegativeDestination) { + constexpr uint64_t kernel_addr = 0x10000; + constexpr uint64_t input_addr = 0x2700; + constexpr uint32_t lds_bytes_per_wg = 256; + constexpr uint32_t kSentinel = 0xa5a5a5a5u; + + const uint32_t code[] = { + 0xBE8000FFu, static_cast(input_addr + 4), // s_mov_b32 s0, input_addr + 4 + 0xBE810080u, // s_mov_b32 s1, 0 + 0xBEFD0083u, // s_mov_b32 m0, 0x3 + 0x7E000280u, // v_mov_b32_e32 v0, 0 + 0xEE1AC000u, 0x00000000u, + 0xFFFFFC00u, // cluster_load_async_to_lds_b32 v0, v0, s[0:1] offset:-4 + 0xBFCA0000u, // s_wait_asynccnt 0 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + uint64_t kernel_object = sim.write_kernel(kernel_addr, code, std::size(code), 128); + sim.memory->write32(input_addr, 0x12345678u); + + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch_clustered(kernel_object, /*cluster_count_x=*/1, /*cluster_size_x=*/2, + /*workgroup_size_x=*/32, /*kernarg_addr=*/0, lds_bytes_per_wg); + ASSERT_TRUE(sim.engine->step()); + + auto targets = sim.cp()->cluster_lds_targets(/*dispatch_id=*/1, /*wg_id=*/0, + /*mcast_mask=*/0x3); + ASSERT_EQ(targets.size(), 2u); + for (const auto &target : targets) + target.cu->lds().write32(target.lds_base, kSentinel); + EXPECT_NO_THROW(sim.engine->run()); + for (const auto &target : targets) + EXPECT_EQ(target.cu->lds().read32(target.lds_base), kSentinel); +} + +TEST(Gfx1250SimulationTest, ClusterLoadAsyncToLdsAppliesIoffsetToGlobalAndLds) { + constexpr uint64_t kernel_addr = 0x10000; + constexpr uint64_t input_addr = 0x2800; + constexpr uint32_t lds_bytes_per_wg = 256; + constexpr uint32_t instruction_offset = 4; + + const uint32_t code[] = { + 0xBE8000FFu, static_cast(input_addr), // s_mov_b32 s0, input_addr + 0xBE810080u, // s_mov_b32 s1, 0 + 0xBEFD0083u, // s_mov_b32 m0, 0x3 + 0x30000082u, // v_lshlrev_b32_e32 v0, 2, v0 + 0xEE1AC000u, 0x00000000u, + 0x00000400u, // cluster_load_async_to_lds_b32 v0, v0, s[0:1] offset:4 + 0xBFCA0000u, // s_wait_asynccnt 0 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + uint64_t kernel_object = sim.write_kernel(kernel_addr, code, std::size(code), 128); + for (uint32_t byte = 0; byte < 256; ++byte) + sim.memory->write8(input_addr + byte, static_cast(0xc0u + byte)); + + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch_clustered(kernel_object, /*cluster_count_x=*/1, /*cluster_size_x=*/2, + /*workgroup_size_x=*/32, /*kernarg_addr=*/0, lds_bytes_per_wg); + ASSERT_TRUE(sim.engine->step()); + + auto targets = sim.cp()->cluster_lds_targets(/*dispatch_id=*/1, /*wg_id=*/0, + /*mcast_mask=*/0x3); + ASSERT_EQ(targets.size(), 2u); + ASSERT_NE(targets[0].cu, nullptr); + ASSERT_NE(targets[1].cu, nullptr); + EXPECT_NE(targets[0].cu, targets[1].cu); + sim.engine->run(); + + auto read_unaligned_input = [&](uint32_t byte_offset) { + uint32_t value = 0; + for (uint32_t byte = 0; byte < 4; ++byte) + value |= static_cast(sim.memory->read8(input_addr + byte_offset + byte)) + << (byte * 8); + return value; + }; + + for (uint32_t lane = 0; lane < 32; ++lane) { + const uint32_t lds_offset = lane * 4 + instruction_offset; + const uint32_t expected_value = read_unaligned_input(lds_offset); + EXPECT_EQ(targets[0].cu->lds().read32(targets[0].lds_base + lds_offset), expected_value) + << "lane " << lane; + EXPECT_EQ(targets[1].cu->lds().read32(targets[1].lds_base + lds_offset), expected_value) + << "lane " << lane; + } +} + TEST(Gfx1250SimulationTest, Ttmp7ClusterGridYDoesNotBleedIntoZAt16BitBoundary) { const uint32_t code[] = {S_ENDPGM_GFX12}; diff --git a/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp b/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp index e4d110c452c8..1d53ac4a1a8b 100644 --- a/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp @@ -19,6 +19,25 @@ namespace { using namespace rocjitsu; using namespace rocjitsu::test::cdna5; +TEST(Gfx1250ExecutionTest, LdsAccessesRejectWrappedRanges) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto &lds = cu->lds(); + constexpr uint32_t kWrappedAddress = UINT32_MAX - 3; + constexpr uint32_t kValue = 0x12345678u; + + lds.write32(kWrappedAddress, kValue); + EXPECT_EQ(lds.read32(kWrappedAddress), 0u); + + std::array bytes{}; + std::memcpy(bytes.data(), &kValue, sizeof(kValue)); + lds.write(kWrappedAddress, bytes.data(), bytes.size()); + bytes.fill(0xff); + const auto &const_lds = lds; + const_lds.read(kWrappedAddress, bytes.data(), bytes.size()); + EXPECT_EQ(bytes, (std::array{})); +} + TEST(Gfx1250SimulationTest, DispatchesEndpgmThroughConfig) { Gfx1250Sim sim; const uint32_t code[] = {S_ENDPGM_GFX12}; diff --git a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp index 22ac7c1e9df8..06bf97c8db61 100644 --- a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp @@ -1131,6 +1131,7 @@ TEST(Gfx1250SimulationTest, AsyncToLdsUsesDstAndSrc0HighBanks) { const uint32_t vb = wf->vgpr_alloc().base; auto &cu = *sim.cu(); wf->set_lds_base(cu.allocate_lds(256)); + wf->set_lds_size(256); wf->set_vgpr_msb_mode((kDstBank << 6) | kSrc0Bank); cu.write_vgpr(vb + kSrc0Bank * kBankStride + kVaddr, 0, static_cast(kGlobalAddr)); cu.write_vgpr(vb + kSrc0Bank * kBankStride + kVaddr + 1, 0, diff --git a/emulation/rocjitsu/tests/execution_plugin_test.cpp b/emulation/rocjitsu/tests/execution_plugin_test.cpp index 1b7152a8a678..b860dd2eb775 100644 --- a/emulation/rocjitsu/tests/execution_plugin_test.cpp +++ b/emulation/rocjitsu/tests/execution_plugin_test.cpp @@ -37,6 +37,7 @@ #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/gpu_memory.h" #include "rocjitsu/vm/amdgpu/l2_cache.h" +#include "rocjitsu/vm/amdgpu/lds.h" #include "rocjitsu/vm/amdgpu/memory_pipeline.h" #include "rocjitsu/vm/soc.h" #include "scoped_temp.h" @@ -2849,6 +2850,53 @@ TEST(RaceDetectorPluginOutputTest, DispatchLineUsesReadableNameAndExactSymbol) { std::string::npos); } +TEST(RaceDetectorPluginTest, DroppedAsyncLdsLaneDoesNotCreateLowAddressRace) { + PluginFixture f(/*num_wf_slots=*/2, /*arch=*/"gfx1250", /*wavefront_size=*/32); + PluginSinkConfig sink_config; + StringSink &sink = sink_config.emplace(); + f.plugin_group_ = std::make_shared(std::move(sink_config)); + ASSERT_TRUE(f.plugin_group_->add(std::make_unique())); + f.soc->set_plugin_group(f.plugin_group_); + f.plugin_group_->onInit(); + + auto *cu = f.cu(); + auto *writer = cu->dispatch_wf(/*wg_id=*/0, /*pc=*/0, /*sgprs=*/104, /*vgprs=*/256); + auto *reader = cu->dispatch_wf(/*wg_id=*/0, /*pc=*/0, /*sgprs=*/104, /*vgprs=*/256); + ASSERT_NE(writer, nullptr); + ASSERT_NE(reader, nullptr); + writer->set_exec(0x1u); + reader->set_exec(0x1u); + std::array waves{writer, reader}; + f.plugin_group_->onAmdgpuWorkgroupDispatched(/*dispatch_id=*/1, /*wg_id=*/0, + /*physical_vgpr_count=*/512, /*sgpr_count=*/208, + waves); + + auto dropped = std::make_unique(GLOBAL_MEM); + dropped->elem_size = 4; + dropped->num_elems = 1; + dropped->is_load = true; + dropped->lds_dst = true; + dropped->lds_per_lane_addr = true; + dropped->wf_size = writer->wf_size(); + dropped->lane_mask = 0x1u; + dropped->per_lane_lds_addr[0] = amdgpu::kInvalidLdsAddress; + TestMemoryInstruction dropped_inst(std::move(dropped)); + f.plugin_group_->onAmdgpuRouteMemoryInstruction(dropped_inst, *writer); + + auto read = std::make_unique(LOCAL_MEM); + read->elem_size = 4; + read->num_elems = 1; + read->is_load = true; + read->wf_size = reader->wf_size(); + read->lane_mask = 0x1u; + read->per_lane_addr[0] = 0; + read->dst_reg_base = reader->vgpr_alloc().base; + TestMemoryInstruction read_inst(std::move(read)); + f.plugin_group_->onAmdgpuRouteMemoryInstruction(read_inst, *reader); + + EXPECT_EQ(sink.str().find("RACE "), std::string::npos); +} + TEST(ExecutionPluginGroupTest, OwnsConfiguredSinkForRetainedGroupLifetime) { std::vector events; std::shared_ptr plugin_group; From ad32ff7c18374437d1cdd997cdb48539543f73b8 Mon Sep 17 00:00:00 2001 From: Tony Gutierrez Date: Sat, 15 Aug 2026 14:38:40 -0700 Subject: [PATCH 04/27] [rocjitsu] Extract per-scope rollback and object-level checks from translate() BinaryTranslator::translate() had grown to roughly 2280 lines because the class holds almost no state: the arch pair, the options, three engine handles. Everything the translation actually works on lived in function locals, which is why fifteen lambdas had accumulated -- each existed to reach a local a free function could not. Nothing could be extracted while the state stayed anonymous. Name the state first. The five per-scope rollback locals become one ScopeTransaction, so the twenty-six failure sites drop from seven arguments to three; output_begin turned out to be consumed entirely by those calls, which is the evidence the bundling is complete rather than partial. This is deliberately not an RAII guard: rollback is conditional on skip_failed_kernels and the failing scope still contributes a stub body, so unwinding has to be an explicit call. The five local types move to file scope, which is what makes any further promotion possible, and three lambdas that captured nothing follow them. The object-level refusals become translation_refusal(), returning a diagnostic rather than a bool because one of them -- an object with no executable text whose target already matches -- is a successful no-op whose warning severity must survive; the image-size and decoder checks stay behind because they gate constructing the patcher and decoder the rest of translation needs, which leaves that function reading an ELF header the caller has already sized, so the precondition is asserted rather than left to the reader. resolve_pending_code_relocations() comes out whole, being the one tail block that sits outside the scope loop and so needs no skip-cascade threading. Comments travel with the code they describe: both hoisted checkpoint structs keep the text that documented them in situ, and the remaining local types gain a brief, which matters more now that they sit hundreds of lines from their only use. Nothing in the rollback body aliases the transaction back into the five names it replaced, so a sixth participant can only be added in one place. No behavior changes. Each step was verified against a binary built before any of them by translating all 905 gfx1250 objects in the corpus with idempotence checking: byte-identical output every time, cumulatively against the original rather than against the previous step. The remaining extractions all sit inside the scope loop, where four separate skip_scope break cascades mean a naive bool return would silently change which of translated_text, text_relocations, and canonical_placement roll back -- a wrong rollback still produces self-consistent bytes, so the corpus would not catch it. Those need a tri-state status and are left for a follow-on. Signed-off-by: Tony Gutierrez (cherry picked from commit fda635e5b4f66c40ec259b6089c2cff17bbde860) --- .../rocjitsu/code/dbt/binary_translator.cpp | 639 ++++++++++-------- .../rocjitsu/tests/dbt/translate_test.cpp | 159 +++++ 2 files changed, 524 insertions(+), 274 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp index 533813e011bd..8b1c3a762507 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp @@ -413,6 +413,95 @@ void append_diagnostics(std::vector &dst, dst.insert(dst.end(), src.begin(), src.end()); } +/// @brief First condition that stops this object from being translated, if any. +/// +/// @details Every result leaves the object unchanged, but not every result is a failure: an +/// object with no executable text and a matching target is a successful no-op, so the caller +/// must preserve the returned severity rather than assuming an error. +/// +/// Check order is observable, because only the first match is reported. Existing checks must not +/// be permuted, and a new one should be appended unless it is deliberately more specific than a +/// check already present. +/// +/// Everything this needs comes from @p patcher, including the text span, so there is no second +/// view of the same bytes to keep consistent. The ELF-header read below bounds itself rather than +/// trusting the caller's earlier size check: that check exists to gate constructing the patcher, +/// and a bound enforced hundreds of lines away is not one this function can rely on. +/// +/// The decoder check stays with the caller because it gates constructing the decoder that the +/// rest of translation needs. +[[nodiscard]] std::optional +translation_refusal(const CodeObjectPatcher &patcher, rj_code_arch_t guest_arch, + rj_code_arch_t host_arch, uint32_t target_mach, + const BinaryTranslatorOptions &options) { + const auto error = [](DiagnosticKind kind, std::string message) { + return TranslationDiagnostic{.severity = DiagnosticSeverity::Error, + .kind = kind, + .guest_offset = std::nullopt, + .mnemonic = {}, + .message = std::move(message), + .required_work = {}}; + }; + + // A same-architecture gfx1250 translation is direction-specific: A0 and B0 share an ELF machine + // ID, so both revisions must be given. Enforce this here as well as in the C API. + if (guest_arch == ROCJITSU_CODE_ARCH_GFX1250 && host_arch == ROCJITSU_CODE_ARCH_GFX1250) { + if (options.input_revision == ProcessorRevision::Unspecified || + options.output_revision == ProcessorRevision::Unspecified) { + return error(DiagnosticKind::Legalization, + "gfx1250 same-target translation requires both input and output silicon " + "revisions"); + } + // Only the B0-to-A0 direction is implemented. + if (options.input_revision == ProcessorRevision::Gfx1250A0 && + options.output_revision == ProcessorRevision::Gfx1250B0) + return error(DiagnosticKind::Legalization, "gfx1250 A0-to-B0 translation is not supported"); + } + + if (patcher.text_bytes().empty()) { + const std::span image = patcher.image_bytes(); + if (image.size() < sizeof(Elf64_Ehdr)) + return error(DiagnosticKind::ResourceLimit, "code object is too small to contain an ELF " + "header"); + Elf64_Ehdr header{}; + std::memcpy(&header, image.data(), sizeof(header)); + const uint32_t source_mach = header.e_flags & EF_AMDGPU_MACH; + if (guest_arch == host_arch && source_mach == (target_mach & EF_AMDGPU_MACH)) { + return TranslationDiagnostic{ + .severity = DiagnosticSeverity::Warning, + .kind = DiagnosticKind::DataOnly, + .guest_offset = std::nullopt, + .mnemonic = {}, + .message = "code object has no executable sections, segments, or callable symbols; " + "leaving unchanged", + .required_work = {}}; + } + return error(DiagnosticKind::ResourceLimit, + "code object does not expose a non-empty .text section for translation"); + } + + // DBT relocates instructions within .text (compaction, expansion, per-kernel block placement) + // but does not rewrite relocation places that land inside .text. An in-.text relocation would + // therefore be applied to the wrong translated bytes. Fail closed rather than silently + // miscompile. + if (patcher.has_relocations_within_text()) { + return error(DiagnosticKind::Legalization, + "code object has a relocation place inside .text; relocating instructions would " + "apply it to the wrong bytes and is not supported"); + } + + // The patcher can retarget ordinary zero-addend symbol references and symbol-less RELATIVE64 + // addends through the final source-to-target offset map. Keep less explicit forms fail-closed + // until their relocation-specific addend semantics are modeled. + if (patcher.has_unsupported_relocation_to_text()) { + return error(DiagnosticKind::Legalization, + "code object has an unsupported relocation referencing .text; section symbols, " + "implicit addends, and named-symbol addends cannot be remapped safely"); + } + + return std::nullopt; +} + /// @brief Return a human-readable kernel label for diagnostics. /// /// @details Some code objects carry empty kernel symbol names. Falling back to @@ -1453,6 +1542,218 @@ adopted_root_return_offsets(const BlockOffsetIndex &block_index, return std::move(patcher).emit(); } +/// @brief One instruction's source and translated form, held until its target offset is known. +/// +/// @details Traces cannot be emitted during lowering because a body's final placement is only +/// fixed after relocation, so each is queued with its source-relative offset and rebased later. +struct PendingTrace { + uint64_t source_offset = 0; + uint32_t source_size = 0; + std::vector source_words; + const InstructionLegalization *legalization = nullptr; + bool copied_original = false; + bool semantic_lowering = false; + bool changed = false; + uint64_t target_offset = 0; + std::vector target_words; +}; + +/// @brief A per-kernel lowering failure, before it is turned into a diagnostic. +/// +/// @details Carried rather than reported immediately because skip_failed_kernels decides whether +/// it becomes an object-level error or the prose of a KernelSkipped warning. +struct KernelFailure { + DiagnosticKind kind = DiagnosticKind::Legalization; + std::string message; + std::optional guest_offset; + std::string mnemonic; + std::vector required_work; +}; + +/// @brief Build a per-kernel failure record. +[[nodiscard]] KernelFailure make_kernel_failure(DiagnosticKind kind, std::string message, + std::optional guest_offset = std::nullopt, + std::string mnemonic = {}, + std::vector required_work = {}) { + return KernelFailure{kind, std::move(message), guest_offset, std::move(mnemonic), + std::move(required_work)}; +} + +/// @brief Map a control-flow relocation failure onto the diagnostic kind that reports it. +[[nodiscard]] DiagnosticKind relocation_diagnostic_kind(const TextRelocationResult &relocation) { + if (relocation.failure == TextLayoutFailureCategory::ResourceLimit) + return DiagnosticKind::ResourceLimit; + return DiagnosticKind::Legalization; +} + +/// @brief Map a body-materialization failure onto the diagnostic kind that reports it. +[[nodiscard]] DiagnosticKind +materialization_diagnostic_kind(const KernelTextAppendResult &materialization) { + if (materialization.failure == TextLayoutFailureCategory::ResourceLimit) + return DiagnosticKind::ResourceLimit; + return DiagnosticKind::KernelDescriptor; +} + +/// @brief A code-address builder awaiting the final placement of the body it names. +struct PendingCodeRelocation { + uint64_t target_getpc_offset = 0; + uint64_t target_literal_offset = 0; + uint64_t source_target_text_offset = 0; +}; + +/// @brief Point every deferred code-address builder at the placement its target received. +/// +/// @details Runs after every scope is placed, which is the first moment a target's final offset +/// is known. A source offset emitted more than once has no single answer -- a runtime-dereferenced +/// code address cannot choose between clones -- so that fails closed rather than picking one, +/// matching how relocate_relative_text_addends treats a conflicting relocation addend. +/// +/// @returns false when the object must be left unchanged. +[[nodiscard]] bool resolve_pending_code_relocations( + const std::vector &pending, + const std::vector &text_relocations, + const std::unordered_map &canonical_placement, + const std::unordered_set &canonical_placement_variant_conflict, + std::vector &code_relocations, + std::vector &diagnostics) { + if (pending.empty()) + return true; + + std::unordered_map placement; + std::unordered_set conflicting; + for (const TextOffsetRelocation &relocation : text_relocations) { + auto [it, inserted] = placement.try_emplace(relocation.source_offset, relocation.target_offset); + if (!inserted && it->second != relocation.target_offset) + conflicting.insert(relocation.source_offset); + } + + for (const PendingCodeRelocation &entry : pending) { + // A canonical copy only answers for its clones when they are interchangeable. Offsets whose + // clones disagreed on kernel-scope variant are not, so they fall through to the placement map + // below and fail closed there rather than silently naming whichever clone was nominated first. + if (const auto canonical = canonical_placement.find(entry.source_target_text_offset); + canonical != canonical_placement.end() && + !canonical_placement_variant_conflict.contains(entry.source_target_text_offset)) { + code_relocations.push_back({.target_getpc_offset = entry.target_getpc_offset, + .target_literal_offset = entry.target_literal_offset, + .target_text_offset = canonical->second}); + continue; + } + const auto placed = placement.find(entry.source_target_text_offset); + if (placed == placement.end() || conflicting.contains(entry.source_target_text_offset)) { + append_error(diagnostics, DiagnosticKind::Legalization, + conflicting.contains(entry.source_target_text_offset) + ? "PC-relative code address names a body emitted at more than one " + "placement; leaving code object unchanged" + : "PC-relative code address names a body this translation did not emit; " + "leaving code object unchanged", + entry.source_target_text_offset); + return false; + } + code_relocations.push_back({.target_getpc_offset = entry.target_getpc_offset, + .target_literal_offset = entry.target_literal_offset, + .target_text_offset = placed->second}); + } + return true; +} + +/// @brief What one scope added to the three code-address containers, so a skipped scope can take +/// it back. +/// +/// @details The two vectors only ever grow within a scope, so a length restores them; +/// canonical_placement is keyed by source offset and needs the inserted keys named. +struct ScopeRelocationCheckpoint { + size_t code_relocations_begin = 0; + size_t pending_code_relocations_begin = 0; + std::vector canonical_placements_added; + // Variant conflicts this scope raised. A skipped scope's text is discarded, so the clone it + // disagreed about no longer exists; leaving the conflict behind would withhold a canonical + // placement whose surviving clones actually agree and refuse the object over a scope that + // contributes nothing. The companion is_sidecar entry is restored with it so a later scope + // compares against the variant that really nominated the canonical copy. + std::vector canonical_variant_conflicts_added; + // The resource verdict is set before descriptor recomputation, which can still skip the scope. + // Rolling the placements back without also restoring this would leave a skipped host's verdict + // standing and refuse the object over a scope that no longer contributes anything. + bool canonical_host_outgrew_its_descriptor = false; +}; + +/// @brief The object-level state a scope appends to, gathered so capture and rollback name one +/// set rather than two open-coded lists that can drift apart. +struct ObjectRollbackState { + std::vector &translated_text; + std::vector &text_relocations; + std::vector &data_relocations; + std::vector &code_relocations; + std::vector &pending_code_relocations; + std::unordered_map &canonical_placement; + std::unordered_map &canonical_placement_is_sidecar; + std::unordered_set &canonical_placement_variant_conflict; + bool &canonical_host_outgrew_its_descriptor; + std::vector &descriptor_translations; +}; + +/// @brief Everything one scope must be able to give back if it fails. +/// +/// @details capture() and rollback() are the only two places that name the rollback set, so the +/// two halves sit next to each other and can be read against one another. That is a legibility +/// guarantee, not a compiler-enforced one: adding a member to ObjectRollbackState and binding it +/// still compiles without a matching capture or restore, so both methods must be updated by hand. +/// This is also not a RAII guard: rollback is conditional on skip_failed_kernels, and a failing +/// scope still contributes a stub body, so unwinding is an explicit call. +struct ScopeTransaction { + size_t output_begin = 0; + size_t text_relocations_begin = 0; + size_t data_relocations_begin = 0; + std::vector descriptors; + ScopeRelocationCheckpoint relocations; + + /// @brief Record where every object-level container stands before a scope emits into it. + [[nodiscard]] static ScopeTransaction capture(const ObjectRollbackState &state, + const KdTranslation &translation) { + return ScopeTransaction{ + .output_begin = state.translated_text.size(), + .text_relocations_begin = state.text_relocations.size(), + .data_relocations_begin = state.data_relocations.size(), + .descriptors = checkpoint_scope_descriptors(state.descriptor_translations, translation), + .relocations = {.code_relocations_begin = state.code_relocations.size(), + .pending_code_relocations_begin = state.pending_code_relocations.size(), + .canonical_placements_added = {}, + .canonical_variant_conflicts_added = {}, + .canonical_host_outgrew_its_descriptor = + state.canonical_host_outgrew_its_descriptor}}; + } + + /// @brief Return every container to its captured state. + /// + /// @details The code-address records and canonical placements name offsets inside the text this + /// discards. A later scope reuses those offsets for its own body, so keeping the records would + /// write a 64-bit literal into instructions that never asked for one. + /// + /// @returns false if a descriptor checkpoint no longer indexes its translation, which the caller + /// must report rather than silently restore the wrong entry. + [[nodiscard]] bool rollback(const ObjectRollbackState &state) const { + state.translated_text.resize(output_begin); + state.text_relocations.resize(text_relocations_begin); + state.data_relocations.resize(data_relocations_begin); + state.code_relocations.resize(relocations.code_relocations_begin); + state.pending_code_relocations.resize(relocations.pending_code_relocations_begin); + for (const uint64_t placed : relocations.canonical_placements_added) { + state.canonical_placement.erase(placed); + state.canonical_placement_is_sidecar.erase(placed); + } + for (const uint64_t conflicted : relocations.canonical_variant_conflicts_added) + state.canonical_placement_variant_conflict.erase(conflicted); + state.canonical_host_outgrew_its_descriptor = relocations.canonical_host_outgrew_its_descriptor; + for (const DescriptorVariantCheckpoint &saved : descriptors) { + if (saved.index >= state.descriptor_translations.size()) + return false; + state.descriptor_translations[saved.index] = saved.translation; + } + return true; + } +}; + } // namespace namespace internal { @@ -1590,68 +1891,17 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { } CodeObjectPatcher patcher(obj); - - // A same-architecture gfx1250 translation is direction-specific: A0 and B0 - // share an ELF machine ID, so both revisions must be given. Enforce this here - // as well as in the C API. - if (guest_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && host_arch_ == ROCJITSU_CODE_ARCH_GFX1250) { - if (options_.input_revision == ProcessorRevision::Unspecified || - options_.output_revision == ProcessorRevision::Unspecified) { - append_error(result.diagnostics, DiagnosticKind::Legalization, - "gfx1250 same-target translation requires both input and output silicon " - "revisions"); - return leave_unchanged(); - } - // Only the B0-to-A0 direction is implemented. - if (options_.input_revision == ProcessorRevision::Gfx1250A0 && - options_.output_revision == ProcessorRevision::Gfx1250B0) { - append_error(result.diagnostics, DiagnosticKind::Legalization, - "gfx1250 A0-to-B0 translation is not supported"); - return leave_unchanged(); - } - } - auto text = patcher.text_bytes(); - if (text.empty()) { - Elf64_Ehdr header{}; - std::memcpy(&header, obj.image_data(), sizeof(header)); - const uint32_t source_mach = header.e_flags & EF_AMDGPU_MACH; - if (guest_arch_ == host_arch_ && source_mach == (target_mach_ & EF_AMDGPU_MACH)) { - append_warning(result.diagnostics, DiagnosticKind::DataOnly, - "code object has no executable sections, segments, or callable symbols; " - "leaving unchanged"); - return leave_unchanged(); - } - append_error(result.diagnostics, DiagnosticKind::ResourceLimit, - "code object does not expose a non-empty .text section for translation"); + if (auto refusal = + translation_refusal(patcher, guest_arch_, host_arch_, target_mach_, options_)) { + result.diagnostics.push_back(std::move(*refusal)); return leave_unchanged(); } + std::unordered_set generated_island_pool_candidates; if (guest_arch_ == host_arch_) generated_island_pool_candidates = generated_branch_island_pool_offsets(text, guest_arch_); - // DBT relocates instructions within .text (compaction, expansion, per-kernel - // block placement) but does not rewrite relocation places that land inside - // .text. An in-.text relocation would therefore be applied to the wrong - // translated bytes. Fail closed rather than silently miscompile. - if (patcher.has_relocations_within_text()) { - append_error(result.diagnostics, DiagnosticKind::Legalization, - "code object has a relocation place inside .text; relocating instructions would " - "apply it to the wrong bytes and is not supported"); - return leave_unchanged(); - } - - // The patcher can retarget ordinary zero-addend symbol references and - // symbol-less RELATIVE64 addends through the final source-to-target offset - // map. Keep less explicit forms fail-closed until their relocation-specific - // addend semantics are modeled. - if (patcher.has_unsupported_relocation_to_text()) { - append_error(result.diagnostics, DiagnosticKind::Legalization, - "code object has an unsupported relocation referencing .text; section symbols, " - "implicit addends, and named-symbol addends cannot be remapped safely"); - return leave_unchanged(); - } - // Per-kernel text relocation strategy: // 1. Translate descriptors first so their source entries and ABI state define // the normal and sidecar kernel scopes. @@ -2163,18 +2413,6 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { translated_text.reserve(text.size()); const bool continue_after_failure = options_.debug_continue_after_failure; - struct PendingTrace { - uint64_t source_offset = 0; - uint32_t source_size = 0; - std::vector source_words; - const InstructionLegalization *legalization = nullptr; - bool copied_original = false; - bool semantic_lowering = false; - bool changed = false; - uint64_t target_offset = 0; - std::vector target_words; - }; - auto queue_trace = [&](std::vector &pending, const Instruction &inst, uint64_t offset, const InstructionLegalization *leg, bool copied_original, bool semantic_lowering, bool changed, uint64_t target_offset, @@ -2233,34 +2471,6 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { return true; }; - auto relocation_diagnostic_kind = [&](const TextRelocationResult &relocation) { - if (relocation.failure == TextLayoutFailureCategory::ResourceLimit) - return DiagnosticKind::ResourceLimit; - return DiagnosticKind::Legalization; - }; - - auto materialization_diagnostic_kind = [&](const KernelTextAppendResult &materialization) { - if (materialization.failure == TextLayoutFailureCategory::ResourceLimit) - return DiagnosticKind::ResourceLimit; - return DiagnosticKind::KernelDescriptor; - }; - - struct KernelFailure { - DiagnosticKind kind = DiagnosticKind::Legalization; - std::string message; - std::optional guest_offset; - std::string mnemonic; - std::vector required_work; - }; - - auto make_kernel_failure = [](DiagnosticKind kind, std::string message, - std::optional guest_offset = std::nullopt, - std::string mnemonic = {}, - std::vector required_work = {}) { - return KernelFailure{kind, std::move(message), guest_offset, std::move(mnemonic), - std::move(required_work)}; - }; - auto emit_skipped_kernel = [&](const KernelTranslationScope &scope, KernelFailure failure) -> bool { assert(scope.translation != nullptr && "kernel scope should have descriptor translation"); @@ -2332,11 +2542,6 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { // scope not yet emitted, and a body reached from several kernels is cloned once per scope, so the // final offset is only knowable once every placement is recorded. Hold the source-side answer and // resolve against the completed map below. - struct PendingCodeRelocation { - uint64_t target_getpc_offset = 0; - uint64_t target_literal_offset = 0; - uint64_t source_target_text_offset = 0; - }; std::vector pending_code_relocations; std::vector code_relocations; // Final offset of the one copy of each adopted body. Code addresses name this copy, so a body a @@ -2357,30 +2562,23 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { // value -- hence the tightening handed to replace_text() below. bool relied_on_relocated_by_construction = false; - // What one scope added to the three code-address containers, so a skipped scope can take it back. - // The two vectors only ever grow within a scope, so a length restores them; canonical_placement - // is keyed by source offset and needs the inserted keys named. - struct ScopeRelocationCheckpoint { - size_t code_relocations_begin = 0; - size_t pending_code_relocations_begin = 0; - std::vector canonical_placements_added; - // Variant conflicts this scope raised. A skipped scope's text is discarded, so the clone it - // disagreed about no longer exists; leaving the conflict behind would withhold a canonical - // placement whose surviving clones actually agree and refuse the object over a scope that - // contributes nothing. The companion is_sidecar entry is restored with it so a later scope - // compares against the variant that really nominated the canonical copy. - std::vector canonical_variant_conflicts_added; - // The resource verdict is set before descriptor recomputation, which can still skip the scope. - // Rolling the placements back without also restoring this would leave a skipped host's verdict - // standing and refuse the object over a scope that no longer contributes anything. - bool canonical_host_outgrew_its_descriptor = false; - }; - - auto fail_or_skip_kernel = - [&](const KernelTranslationScope &scope, KernelFailure failure, size_t output_begin, - const std::vector &descriptor_snapshot, - size_t text_relocations_begin, size_t data_relocations_begin, - const ScopeRelocationCheckpoint &relocation_snapshot) -> bool { + // Reports the failure, or rolls the scope back and emits a stub in its place, depending on + // skip_failed_kernels. Returns true when the caller should continue with the next scope. + // Bound once so capture and rollback cannot be handed different views of the object state. + const ObjectRollbackState rollback_state{ + .translated_text = translated_text, + .text_relocations = text_relocations, + .data_relocations = data_relocations, + .code_relocations = code_relocations, + .pending_code_relocations = pending_code_relocations, + .canonical_placement = canonical_placement, + .canonical_placement_is_sidecar = canonical_placement_is_sidecar, + .canonical_placement_variant_conflict = canonical_placement_variant_conflict, + .canonical_host_outgrew_its_descriptor = canonical_host_outgrew_its_descriptor, + .descriptor_translations = descriptor_translations}; + + auto fail_or_skip_kernel = [&](const KernelTranslationScope &scope, KernelFailure failure, + const ScopeTransaction &transaction) -> bool { if (!skip_failed_kernels) { append_error(result.diagnostics, failure.kind, std::move(failure.message), failure.guest_offset, std::move(failure.mnemonic), @@ -2389,30 +2587,10 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { } const uint64_t source_entry = scope.translation->entry_text_offset; - translated_text.resize(output_begin); - // Discard any relocation records this scope committed before failing. - text_relocations.resize(text_relocations_begin); - data_relocations.resize(data_relocations_begin); - // The code-address records and the canonical placements name offsets inside the text this - // rollback just discarded. A later scope reuses those offsets for its own body, so keeping the - // records would write a 64-bit literal into instructions that never asked for one. - code_relocations.resize(relocation_snapshot.code_relocations_begin); - pending_code_relocations.resize(relocation_snapshot.pending_code_relocations_begin); - for (const uint64_t placed : relocation_snapshot.canonical_placements_added) { - canonical_placement.erase(placed); - canonical_placement_is_sidecar.erase(placed); - } - for (const uint64_t conflicted : relocation_snapshot.canonical_variant_conflicts_added) - canonical_placement_variant_conflict.erase(conflicted); - canonical_host_outgrew_its_descriptor = - relocation_snapshot.canonical_host_outgrew_its_descriptor; - for (const DescriptorVariantCheckpoint &saved : descriptor_snapshot) { - if (saved.index >= descriptor_translations.size()) { - append_error(result.diagnostics, DiagnosticKind::KernelDescriptor, - "descriptor checkpoint index changed during skip rollback", source_entry); - return false; - } - descriptor_translations[saved.index] = saved.translation; + if (!transaction.rollback(rollback_state)) { + append_error(result.diagnostics, DiagnosticKind::KernelDescriptor, + "descriptor checkpoint index changed during skip rollback", source_entry); + return false; } KernelTranslationScope restored_scope = scope; @@ -2447,17 +2625,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { if (scope.translation->skipped) continue; - const size_t output_begin = translated_text.size(); - const size_t text_relocations_begin = text_relocations.size(); - const size_t data_relocations_begin = data_relocations.size(); - ScopeRelocationCheckpoint relocation_snapshot{ - .code_relocations_begin = code_relocations.size(), - .pending_code_relocations_begin = pending_code_relocations.size(), - .canonical_placements_added = {}, - .canonical_variant_conflicts_added = {}, - .canonical_host_outgrew_its_descriptor = canonical_host_outgrew_its_descriptor}; - const auto descriptor_snapshot = - checkpoint_scope_descriptors(descriptor_translations, *scope.translation); + ScopeTransaction transaction = ScopeTransaction::capture(rollback_state, *scope.translation); bool skip_scope = false; if (!scope.translation->supported) { @@ -2474,8 +2642,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { failure.required_work = diagnostic.required_work; break; } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -2500,9 +2667,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { auto failure = make_kernel_failure( DiagnosticKind::ResourceLimit, "virtual LDS lowering cannot reserve a backing-buffer SGPR pair", layout.source_entry); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -2524,9 +2689,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { DiagnosticKind::ResourceLimit, "virtual LDS backing-pointer spill offset overflows the 32-bit private segment", layout.source_entry); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -2540,9 +2703,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { DiagnosticKind::KernelDescriptor, "virtual LDS lowering cannot materialize backing-buffer pointer entry prologue", layout.source_entry); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -2560,8 +2721,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { "kernel descriptor prologue does not fit in the 256-byte kernarg preload compatibility " "window", layout.source_entry); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -2856,9 +3016,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { make_kernel_failure(DiagnosticKind::Legalization, "recovered indirect branch has inconsistent consumer metadata", source_call_offset, "indirect branch"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -2886,9 +3044,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { "recovered indirect branch has an unconstrained predecessor path that cannot be " "relocated", source_call_offset, "indirect branch"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3118,9 +3274,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { DiagnosticKind::Legalization, "generated direct branch island pool contains malformed live slot", source_branch_offset); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3134,9 +3288,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { DiagnosticKind::Legalization, "generated direct branch island pool targets outside source .text", source_branch_offset); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3273,9 +3425,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3305,9 +3455,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3319,9 +3467,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { auto failure = make_kernel_failure(DiagnosticKind::Legalization, "direct branch is missing raw encoding", offset, std::string(inst.mnemonic())); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3414,9 +3560,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3451,9 +3595,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3486,9 +3628,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3515,9 +3655,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3568,9 +3706,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { continue; } } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3686,9 +3822,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { DiagnosticKind::Legalization, "recovered indirect branch builder is not fully present in the relocated body", fixup.source_call_offset, "indirect branch"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -3857,8 +3991,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { auto failure = make_kernel_failure(relocation_diagnostic_kind(patched_control_flow), patched_control_flow.message, patched_control_flow.source_offset); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -3867,8 +4000,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { !patched.ok) { auto failure = make_kernel_failure(relocation_diagnostic_kind(patched), patched.message, patched.source_offset, "indirect branch"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } else { @@ -3889,8 +4021,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { if (!materialized.ok) { auto failure = make_kernel_failure(materialization_diagnostic_kind(materialized), materialized.message, materialized.source_offset); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -3904,7 +4035,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { if (placed == target_offset_by_source_offset.end()) continue; if (canonical_placement.try_emplace(taken, placed->second + target_delta).second) { - relocation_snapshot.canonical_placements_added.push_back(taken); + transaction.relocations.canonical_placements_added.push_back(taken); canonical_placement_is_sidecar[taken] = scope_is_sidecar; continue; } @@ -3916,7 +4047,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { const auto variant = canonical_placement_is_sidecar.find(taken); if (variant != canonical_placement_is_sidecar.end() && variant->second != scope_is_sidecar && canonical_placement_variant_conflict.insert(taken).second) { - relocation_snapshot.canonical_variant_conflicts_added.push_back(taken); + transaction.relocations.canonical_variant_conflicts_added.push_back(taken); } } for (const auto &[source_offset, target_offset] : target_offset_by_source_offset) { @@ -4010,9 +4141,12 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { const uint64_t source_target = builder.target_vaddr - text_vaddr; // An adopted body has one canonical copy; every code address names it, whatever scope the // builder lives in. Resolving that here rather than after the loop keeps the address stable - // even when a caller also clones the body. + // even when a caller also clones the body. Offsets whose clones disagreed on kernel-scope + // variant are excluded: those clones are lowered against different LDS models, so no single + // one of them can answer for the rest. if (const auto canonical = canonical_placement.find(source_target); - canonical != canonical_placement.end()) { + canonical != canonical_placement.end() && + !canonical_placement_variant_conflict.contains(source_target)) { code_relocations.push_back( {.target_getpc_offset = getpc->second + target_delta, .target_literal_offset = add->second + target_delta + sizeof(uint32_t), @@ -4060,7 +4194,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { // GFX10+ the wavefront SGPR count is a reserved field, so the decoded 8 is the granule-0 // artifact rather than a budget, and a long-branch thunk needing an SGPR pair above it raises // nothing and starves nobody. VGPR and private are encoded on every target and still count. - if (!relocation_snapshot.canonical_placements_added.empty() && + if (!transaction.relocations.canonical_placements_added.empty() && (kernel_context.required_vgpr_count > kernel_context.num_vgprs || (arch_descriptor_encodes_sgpr_allocation(host_arch_) && kernel_context.required_sgpr_count > kernel_context.num_sgprs) || @@ -4102,9 +4236,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { auto failure = make_kernel_failure(DiagnosticKind::KernelDescriptor, "kernel descriptor translation could not be recomputed"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -4122,9 +4254,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { auto failure = make_kernel_failure( DiagnosticKind::KernelDescriptor, "virtual LDS lowering cannot materialize backing-buffer pointer entry prologue"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -4146,9 +4276,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { failure.required_work = diagnostic.required_work; break; } - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -4165,9 +4293,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { auto failure = make_kernel_failure( DiagnosticKind::KernelDescriptor, "kernel descriptor prologue changed after relocated text was emitted"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) { + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) { skip_scope = true; break; } @@ -4185,9 +4311,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { if (!recomputed_descriptor) { auto failure = make_kernel_failure(DiagnosticKind::KernelDescriptor, "kernel descriptor translation could not be recomputed"); - if (fail_or_skip_kernel(scope, std::move(failure), output_begin, descriptor_snapshot, - text_relocations_begin, data_relocations_begin, - relocation_snapshot)) + if (fail_or_skip_kernel(scope, std::move(failure), transaction)) continue; return leave_unchanged(); } @@ -4214,43 +4338,10 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { return leave_unchanged(); } - // Every scope has been placed, so a code-target builder can finally be told where its target - // landed. A source offset emitted more than once has no single answer -- a runtime-dereferenced - // code address cannot choose between clones -- so that fails closed rather than picking one, - // matching how relocate_relative_text_addends treats a conflicting relocation addend. - if (!pending_code_relocations.empty()) { - std::unordered_map placement; - std::unordered_set conflicting; - for (const TextOffsetRelocation &relocation : text_relocations) { - auto [it, inserted] = - placement.try_emplace(relocation.source_offset, relocation.target_offset); - if (!inserted && it->second != relocation.target_offset) - conflicting.insert(relocation.source_offset); - } - for (const PendingCodeRelocation &pending : pending_code_relocations) { - if (const auto canonical = canonical_placement.find(pending.source_target_text_offset); - canonical != canonical_placement.end()) { - code_relocations.push_back({.target_getpc_offset = pending.target_getpc_offset, - .target_literal_offset = pending.target_literal_offset, - .target_text_offset = canonical->second}); - continue; - } - const auto placed = placement.find(pending.source_target_text_offset); - if (placed == placement.end() || conflicting.contains(pending.source_target_text_offset)) { - append_error(result.diagnostics, DiagnosticKind::Legalization, - conflicting.contains(pending.source_target_text_offset) - ? "PC-relative code address names a body emitted at more than one " - "placement; leaving code object unchanged" - : "PC-relative code address names a body this translation did not emit; " - "leaving code object unchanged", - pending.source_target_text_offset); - return leave_unchanged(); - } - code_relocations.push_back({.target_getpc_offset = pending.target_getpc_offset, - .target_literal_offset = pending.target_literal_offset, - .target_text_offset = placed->second}); - } - } + if (!resolve_pending_code_relocations(pending_code_relocations, text_relocations, + canonical_placement, canonical_placement_variant_conflict, + code_relocations, result.diagnostics)) + return leave_unchanged(); if (continue_after_failure && has_error_diagnostic(result.diagnostics)) return leave_unchanged(); diff --git a/emulation/rocjitsu/tests/dbt/translate_test.cpp b/emulation/rocjitsu/tests/dbt/translate_test.cpp index 29200cd4e573..93a611e0b530 100644 --- a/emulation/rocjitsu/tests/dbt/translate_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_test.cpp @@ -2194,5 +2194,164 @@ TEST(BinaryTranslatorE2E, IncompleteConsumerFailsClosedAtKernargPreloadFirmwareE // path is already covered end-to-end by // IncompleteIndirectConsumerTranslatesWhenScopeHasNoStalePcValues above. +// A device function reached by more than one kernel scope is cloned once per scope, so each +// scope's branches resolve through its own placement map. A stored function pointer holds exactly +// one value and cannot choose between clones, so the translator nominates one clone canonical and +// rewrites every R_AMDGPU_RELATIVE64 addend to name it. +// +// That nomination is only sound while the clones are interchangeable, and a virtual-LDS sidecar +// scope is not interchangeable with its hardware-LDS twin: the sidecar clone is lowered against a +// different LDS model, so a pointer that reached it under a dispatch configured for the hardware +// model -- or the reverse -- would execute the wrong lowering. When two scopes emitting the same +// address-taken body disagree on that variant, the offset is recorded as variant-conflicted and +// withheld from the canonical map, which leaves the addend path fail-closed on it instead of +// silently answering with whichever clone happened to be nominated first. +// +// Sidecar variants exist only for the CDNA4 -> CDNA3 pair, so both tests below use it. They share +// one fixture and differ in a single input field -- kernel 0's group_segment_fixed_size -- which is +// what makes the refusal attributable to the variant disagreement rather than to the cloning. +namespace { + +constexpr uint16_t kSharedHelperReturnSreg = 30; +constexpr size_t kSharedHelperEntryWord = 4; +/// @brief Static LDS beyond the CDNA3 host's 64 KiB per-workgroup limit, which is what makes the +/// hosting scope acquire a virtual-LDS sidecar variant alongside its hardware-LDS one. +constexpr uint32_t kOversizedGroupSegmentBytes = 105600u; + +/// @brief Two kernels that both call one address-taken helper, so the helper is cloned per scope. +/// +/// @details The helper is named by an R_AMDGPU_RELATIVE64 slot, which is what makes it +/// address-taken, and is reached by a direct call from each kernel, which is what makes every +/// scope emit its own clone rather than leaving it to be adopted by one. +/// +/// @param oversized_kernel0_lds Give kernel 0 more static LDS than the host can dispatch, so its +/// scope gains a sidecar variant and the two variants disagree about the helper they both emit. +[[nodiscard]] std::vector +make_shared_address_taken_helper_image(bool oversized_kernel0_lds) { + const std::vector words = { + // word 0: kernel 0 entry, calls the helper at word 4. + build_s_call_b64(kSharedHelperReturnSreg, 3, ROCJITSU_CODE_ARCH_CDNA4), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA4), // word 1 + // word 2: kernel 1 entry, calls the same helper. + build_s_call_b64(kSharedHelperReturnSreg, 1, ROCJITSU_CODE_ARCH_CDNA4), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA4), // word 3 + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA4), // word 4: helper entry + build_s_setpc_b64(kSharedHelperReturnSreg, ROCJITSU_CODE_ARCH_CDNA4), // word 5: helper return + }; + + auto image = test_support::make_minimal_amdgpu_elf_with_two_kernels_and_function_pointers( + words, /*kernel1_entry_word=*/2, {{.offset_word = kSharedHelperEntryWord, .words = 2}}); + if (!oversized_kernel0_lds) + return image; + + AmdGpuCodeObject layout(image.data(), image.size()); + const auto *rodata = find_section(layout, ".rodata"); + if (rodata == nullptr) + return image; + // Kernel 0's descriptor is first in .rodata, so this leaves kernel 1 on the hardware-LDS model. + write_value_for_test( + image, rodata->sectionOffset() + offsetof(TestKernelDescriptor, group_segment_fixed_size), + kOversizedGroupSegmentBytes); + // The sidecar descriptor owns a wrapper ABI that needs an initialized workgroup id and room in + // the User SGPRs, so the source descriptor has to declare both for the variant to be computable. + uint32_t rsrc2 = 0; + AMDHSA_BITS_SET(rsrc2, rocr::llvm::amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1); + AMDHSA_BITS_SET(rsrc2, rocr::llvm::amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT, 2); + write_value_for_test( + image, rodata->sectionOffset() + offsetof(TestKernelDescriptor, compute_pgm_rsrc2), rsrc2); + uint16_t properties = 0; + AMDHSA_BITS_SET(properties, + rocr::llvm::amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR, 1); + write_value_for_test( + image, rodata->sectionOffset() + offsetof(TestKernelDescriptor, kernel_code_properties), + properties); + return image; +} + +/// @brief `.text`-relative offsets of every clone of the helper body in a translated image. +/// +/// @details Each clone ends in the helper's `s_setpc_b64` return, so counting those locates the +/// clones without depending on where the layout placed them. +[[nodiscard]] std::vector +translated_helper_entry_offsets(const AmdGpuCodeObject &object) { + std::vector entries; + if (object.text_sections().empty()) + return entries; + const Section &text = *object.text_sections().front(); + const auto *words = reinterpret_cast(text.data()); + const size_t word_count = text.size() / sizeof(uint32_t); + const uint32_t ret = build_s_setpc_b64(kSharedHelperReturnSreg, ROCJITSU_CODE_ARCH_CDNA3); + for (size_t i = 1; i < word_count; ++i) { + if (words[i] == ret) + entries.push_back((i - 1) * sizeof(uint32_t)); + } + return entries; +} + +/// @brief The single `R_AMDGPU_RELATIVE64` addend the fixture's pointer slot carries. +[[nodiscard]] std::optional only_relative64_addend(const AmdGpuCodeObject &object) { + const auto *rela = find_section(object, ".rela.dyn"); + if (rela == nullptr || rela->size() != sizeof(Elf64_Rela)) + return std::nullopt; + Elf64_Rela entry{}; + std::memcpy(&entry, rela->data(), sizeof(entry)); + if (elf_reloc_type(entry.r_info) != R_AMDGPU_RELATIVE64 || entry.r_addend < 0) + return std::nullopt; + return static_cast(entry.r_addend); +} + +} // namespace + +// The control. Both kernels stay on the hardware-LDS model, so the two scopes that clone the +// helper agree on variant, nothing is recorded as conflicted, and the stored pointer is answered +// from the canonical placement -- the clone the lowest-offset scope emitted. Without this the +// refusal below could be passing because the body is cloned at all rather than because the clones +// are not equivalent. +TEST(BinaryTranslatorE2E, AgreeingScopesResolveAnAddressTakenCloneThroughCanonicalPlacement) { + const auto image = make_shared_address_taken_helper_image(/*oversized_kernel0_lds=*/false); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_CDNA3); + const auto result = translator.translate(source); + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + + AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_TRUE(translated.is_valid()); + ASSERT_FALSE(translated.text_sections().empty()); + + const auto clones = translated_helper_entry_offsets(translated); + ASSERT_EQ(clones.size(), 2u) << "each kernel scope emits its own clone of the shared helper"; + + const auto addend = only_relative64_addend(translated); + ASSERT_TRUE(addend.has_value()); + const uint64_t text_vaddr = translated.text_sections().front()->vaddr(); + ASSERT_GE(*addend, text_vaddr); + EXPECT_EQ(*addend - text_vaddr, clones.front()) + << "the stored pointer names the canonical clone, not the caller-local one"; +} + +// The same fixture with kernel 0 given more static LDS than the host can dispatch. Its scope now +// has a hardware-LDS variant and a virtual-LDS sidecar variant, both emitting the shared helper +// and disagreeing about how LDS in it is lowered, so no single clone can answer for the pointer. +// The object must be refused whole rather than translated with the addend pointing at whichever +// clone was nominated first: that artifact would look correct and would run the hardware-LDS +// lowering under a sidecar dispatch. +TEST(BinaryTranslatorE2E, VariantConflictedAddressTakenCloneRefusesInsteadOfNamingOneClone) { + const auto image = make_shared_address_taken_helper_image(/*oversized_kernel0_lds=*/true); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_CDNA3); + const auto result = translator.translate(source); + EXPECT_FALSE(result.ok()) + << "a code address whose clones disagree on kernel-scope variant has no single answer"; + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::ResourceLimit, + "relocated .text could not be materialized safely")) + << (result.diagnostics.empty() ? "" : result.diagnostics.front().message); + EXPECT_EQ(result.elf_bytes, image) << "fail-closed must leave the object unchanged"; +} + } // namespace } // namespace rocjitsu From 4c0cb052077652f336c0ea1ea1e9313ad84fa0ee Mon Sep 17 00:00:00 2001 From: Tony Gutierrez Date: Sun, 16 Aug 2026 09:36:16 -0700 Subject: [PATCH 05/27] [rocjitsu] Emit leading V_NOPs ahead of a gfx1250 MODE write On this target an s_setreg* naming the MODE register requires two V_NOPs immediately before it to be ordered against the instructions that precede it, and compiler output does not supply them. Register a semantic expansion that emits the missing V_NOPs followed by the original instruction. What identifies such a write is the hardware-register selector in SIMM16 rather than the mnemonic, so the rule discriminates on that and declines every other register, which leaves it on the verbatim copy path. The scope is the setreg instruction rather than MODE as a location, so the other writers of MODE state -- s_set_vgpr_msb and the SOPP round- and denorm-mode forms -- are excluded. V_NOPs already present immediately before the write are counted and only the missing slots emitted, so a repeated translation is a fixed point. The integer WMMA spacing rule needed the same block-local scan, so both now share one walk, and both record that V_NOP is the best available filler rather than a guarantee: ordinary VALU is skipped when EXEC==0, while V_NOP issues but occupies no slot there. Rule tables are binary-searched, so each now static_asserts that it is strictly ordered by encoding id and opcode; a misplaced or duplicated entry otherwise misses its own rule with no diagnostic. Rejecting a duplicate holds only while the rule comparison orders by key alone, so a same-key pair differing in everything else is asserted to be rejected too. The diff report gains a label for a semantic lowering that carries an instruction with no legalization entry, which is how this rule is registered. Signed-off-by: Tony Gutierrez (cherry picked from commit 8f75eb781e15694dfecd3caaa88907cda85633d8) --- .../dbt/legalization/gfx1250_b0_to_a0.cpp | 12 ++ .../code/dbt/semantic/cdna4_to_cdna3.cpp | 5 +- .../code/dbt/semantic/cdna4_to_rdna3.cpp | 5 +- .../code/dbt/semantic/cdna4_to_rdna4.cpp | 5 +- .../code/dbt/semantic/gfx1250_b0_to_a0.cpp | 162 ++++++++++++-- .../rocjitsu/code/dbt/semantic_translator.cpp | 9 + .../src/rocjitsu/code/dbt/translation_rule.h | 43 ++++ .../dbt/gfx1250_b0_a0_expected_rewrites.json | 2 +- .../gfx1250_b0_a0_semantic_rewrites.json | 30 +-- .../tests/dbt/translate_gfx1250_test.cpp | 197 +++++++++++++++--- .../tools/rj_dbt_translate_smoke_test.cpp | 67 ++++++ emulation/rocjitsu/tools/dbt_translate.h | 18 ++ .../rocjitsu/tools/dbt_translate_cli.cpp | 31 +-- 13 files changed, 513 insertions(+), 73 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp index 9a16cb907525..8acb526b8705 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp @@ -31,6 +31,18 @@ namespace { /// rules. Prefix-classified WMMA/SWMMAC and cluster-load instructions are /// handled separately by family-level translation rules. /// +/// A rule keyed on an exact (encoding id, opcode) that only inserts spacing and +/// leaves the opcode alone needs no entry here at all: with no classification +/// the instruction reaches the semantic rule table on its own and, when the rule +/// declines, takes the verbatim copy path. The MODE-write separation rule is +/// registered that way, and the diff report is what shows it, as "expand +/// semantic" with no legalization action. +/// +/// An entry here does more than label the report when it is a mnemonic prefix +/// that covers more instructions than the semantic table implements: the +/// unimplemented siblings then fail closed instead of passing through silently. +/// That is why the integer WMMA prefixes below keep their entry. +/// /// Separately, a 64-bit source reading FLAT_SCRATCH_BASE is classified via /// operand inspection (see gfx1250_reads_flat_scratch_base_64bit), and the /// barrier-state query and s_monitor_sleep are DEFERRED with a pass-through diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3.cpp index aa63ff951344..aa1d78131d28 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3.cpp @@ -1855,7 +1855,7 @@ ExpandResult expand_dot2_f32_bf16_cdna4_to_cdna3(const Instruction &inst, uint32 } // Table MUST be sorted by (src_encoding_id, src_opcode) for binary search. -const TranslationRule kExpandRules_cdna4_to_cdna3[] = { +constexpr TranslationRule kExpandRules_cdna4_to_cdna3[] = { {cdna4::encoding::kVop1, cdna4::kVPermlane16SwapB32Vop1, RuleAction::Expand, 0, 0, nullptr, expand_permlane16_swap_b32_cdna4_to_cdna3, nullptr, nullptr}, {cdna4::encoding::kVop1, cdna4::kVPermlane32SwapB32Vop1, RuleAction::Expand, 0, 0, nullptr, @@ -1910,6 +1910,9 @@ const TranslationRule kExpandRules_cdna4_to_cdna3[] = { expand_buffer_load_dwordx4_lds_cdna4_to_cdna3, nullptr, nullptr}, }; +static_assert(translation_rules_sorted(kExpandRules_cdna4_to_cdna3), + "the CDNA4-to-CDNA3 rule table must stay sorted by (encoding id, opcode)"); + } // namespace std::span semantic_expand_rules_cdna4_to_cdna3() { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna3.cpp index 2d95dc1a68f7..1c0907c0b201 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna3.cpp @@ -36,13 +36,16 @@ ExpandResult expand_waitcnt_gfx9_to_gfx11(const Instruction &inst, uint32_t, uin } // Table MUST be sorted by (src_encoding_id, src_opcode) for binary search. -const TranslationRule kExpandRules_cdna4_to_rdna3[] = { +constexpr TranslationRule kExpandRules_cdna4_to_rdna3[] = { {cdna4::encoding::kSopp, cdna4::kSWaitcnt, RuleAction::Expand, 0, 0, nullptr, expand_waitcnt_gfx9_to_gfx11, nullptr, nullptr}, {cdna4::encoding::kVop3OpHi4, cdna4::kVLshlAddU64, RuleAction::Expand, 0, 0, nullptr, expand_cdna4_v_lshl_add_u64_for_rdna, nullptr, nullptr}, }; +static_assert(translation_rules_sorted(kExpandRules_cdna4_to_rdna3), + "the CDNA4-to-RDNA3 rule table must stay sorted by (encoding id, opcode)"); + } // namespace std::span semantic_expand_rules_cdna4_to_rdna3() { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna4.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna4.cpp index 32f02e5b8ec4..26888e233680 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna4.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_rdna4.cpp @@ -289,7 +289,7 @@ ExpandResult expand_mfma_f32_16x16x16_f16(const Instruction &inst, uint32_t, uin } // Table MUST be sorted by (src_encoding_id, src_opcode) for binary search. -const TranslationRule kExpandRules_cdna4_to_rdna4[] = { +constexpr TranslationRule kExpandRules_cdna4_to_rdna4[] = { {cdna4::encoding::kSopp, cdna4::kSWaitcnt, RuleAction::Expand, 0, 0, nullptr, expand_waitcnt, nullptr, nullptr}, {cdna4::encoding::kVop3OpHi4, cdna4::kVLshlAddU64, RuleAction::Expand, 0, 0, nullptr, @@ -302,6 +302,9 @@ const TranslationRule kExpandRules_cdna4_to_rdna4[] = { expand_accvgpr_write, nullptr, nullptr}, }; +static_assert(translation_rules_sorted(kExpandRules_cdna4_to_rdna4), + "the CDNA4-to-RDNA4 rule table must stay sorted by (encoding id, opcode)"); + static_assert(rocjitsu::kMatrixConversionCount >= 2, "Auto-generated matrix conversion table too small"); static_assert(rocjitsu::kMatrixConversions[1].xor_byte_mask == 192, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp index 1a0954ebfd26..ca309f9f4394 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp @@ -13,6 +13,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/opcodes.h" +#include "rocjitsu/isa/arch/amdgpu/shared/vgpr_msb.h" #include "rocjitsu/isa/instruction.h" #include "rocjitsu/isa/operand.h" @@ -24,6 +25,7 @@ #include #include #include +#include #include namespace rocjitsu { @@ -397,6 +399,113 @@ ExpandResult expand_gfx1250_s_clause(const Instruction &inst, uint32_t, uint64_t return ExpandResult::success(std::vector(nop.begin(), nop.end())); } +/// @brief Count canonical V_NOPs adjacent to @p inst inside its own basic block. +/// +/// @details @p step picks the side to count. `previous_instruction` counts words +/// before @p inst, `next_instruction` counts words after it. Both stop at the +/// block boundary, and that is what makes the count usable: a counted word is in +/// the same block and therefore stays adjacent to @p inst after layout, whereas +/// a branch landing between the two would have started a new block and ended the +/// walk. Counting stops at @p limit, and a noncanonical NOP ends it, so credit is +/// never overstated. +[[nodiscard]] int count_adjacent_canonical_v_nops(const Instruction &inst, int limit, + const Instruction *(Instruction::*step)() const) { + const uint32_t v_nop = cdna5::build_vop1(cdna5::kVNopVop1)[0]; + int counted = 0; + for (const Instruction *at = (inst.*step)(); + counted < limit && at != nullptr && at->size() == static_cast(sizeof(uint32_t)) && + at->raw_encoding() != nullptr && at->raw_encoding()[0] == v_nop; + at = (at->*step)()) + ++counted; + return counted; +} + +/// @brief Give a MODE-register write its required leading V_NOP separation. +/// +/// @details On this target an `s_setreg*` naming the MODE register requires two +/// V_NOPs immediately before it to be ordered against the instructions that +/// precede it. Compiler output does not supply that separation. The write is +/// commonly the first instruction of a kernel or device function, and sometimes +/// follows a short prefetch prologue. +/// +/// The filler is V_NOP because the requirement names it, and because the +/// separation is required in the VALU pipeline, so it has to occupy VALU issue +/// slots. A scalar wait does not -- `s_nop 1` inserts two wait states in the +/// scalar path and orders nothing in the vector one -- so it is not a substitute +/// despite executing unconditionally. An arbitrary independent VALU instruction +/// is worse than V_NOP rather than better, being skipped outright under an empty +/// mask. +/// +/// A V_NOP has no architectural result, so emitting the missing ones cannot +/// change what the program computes; it supplies the ordering distance and +/// nothing else. +/// +/// Under EXEC==0 the filler contributes no VALU spacing, and the setreg still +/// executes -- but ordinary VALU is skipped under an empty mask, so there is +/// correspondingly little VALU work in flight. The separation is therefore +/// effective where EXEC != 0 and best effort in fully inactive control flow, and +/// no filler this translator may emit improves on that without touching EXEC, +/// which it must not do. The IU8 spacing rule below rests on the same reasoning. +/// +/// Every MODE write gets the separation rather than some subset, because the +/// requirement is stated for the register and not for individual fields within +/// it. +/// +/// The scope is the `s_setreg*` instruction, not the MODE register as a +/// location, so the other instructions that write MODE state are deliberately +/// excluded: `s_set_vgpr_msb`, whose banks this profile models as MODE fields, +/// and the SOPP writers `s_round_mode` and `s_denorm_mode`. What has to be +/// separated is the setreg's own execution against the instructions ahead of it; +/// a different opcode reaching the same fields is a different case and is not +/// covered by widening this rule. Writes naming any other hardware register are +/// declined and copied through unchanged. +/// +/// V_NOPs already immediately before the write are counted and only the missing +/// slots are emitted, so a second translation is a fixed point. A counted V_NOP +/// reaches the target unchanged and with nothing appended to it: it matches no +/// expansion rule, takes no legalization entry, and needs no completion wait, so +/// it can only take the verbatim copy path. +/// +/// TODO: Count separation an adjacent rule is about to emit, not just what the +/// source already holds. A dense IU8 WMMA immediately followed by a MODE write +/// yields eleven V_NOPs -- nine from the spacing rule, then two here -- where +/// nine already separate the write. It is a fixed point and costs only two issue +/// slots, and no corpus object has that adjacency. Fixing it needs the emitted +/// stream rather than the source, which is the same whole-kernel pass the IU8 +/// rule's own TODO asks for; do both together. +ExpandResult expand_gfx1250_setreg_mode_ordering(const Instruction &inst, uint32_t, uint64_t, + std::span, const LivenessAnalysis &, + TranslationContext &, const LaneLayout *, + const LaneLayout *) { + constexpr int kRequiredLeadingVNops = 2; + + if (inst.mnemonic() != "s_setreg_b32" && inst.mnemonic() != "s_setreg_imm32_b32") + return ExpandResult::failed("gfx1250 MODE setreg rule received an unsupported instruction"); + const int size_bytes = inst.size(); + if (size_bytes < static_cast(sizeof(uint32_t)) || + size_bytes % static_cast(sizeof(uint32_t)) != 0 || inst.raw_encoding() == nullptr) + return ExpandResult::failed("gfx1250 MODE setreg rule received an unsupported encoding"); + + // SOPK carries the hardware-register selector in SIMM16. Only MODE requires + // the separation, so the mnemonic alone cannot decide this. + const uint16_t simm16 = static_cast(inst.raw_encoding()[0] & 0xffffu); + if (amdgpu::decode_vgpr_msb_hwreg(simm16).id != amdgpu::MODE_HWREG) + return ExpandResult::not_handled(); + + const int existing_slots = count_adjacent_canonical_v_nops(inst, kRequiredLeadingVNops, + &Instruction::previous_instruction); + if (existing_slots == kRequiredLeadingVNops) + return ExpandResult::not_handled(); + + const size_t words_in_encoding = static_cast(size_bytes) / sizeof(uint32_t); + std::vector words; + words.reserve(words_in_encoding + kRequiredLeadingVNops); + words.insert(words.end(), static_cast(kRequiredLeadingVNops - existing_slots), + cdna5::build_vop1(cdna5::kVNopVop1)[0]); + words.insert(words.end(), inst.raw_encoding(), inst.raw_encoding() + words_in_encoding); + return ExpandResult::success(std::move(words)); +} + /// @brief Decline the one barrier id this profile excludes. /// /// @details Barrier id -3 is the only one this instruction may not name; every @@ -1098,6 +1207,15 @@ ExpandResult expand_gfx1250_wmma_scale16(const Instruction &inst, uint32_t, uint /// the missing slots. Limiting credit to the block guarantees that every /// credited word remains adjacent after layout. Noncanonical NOPs and following /// control-flow successors conservatively receive no credit. +/// +/// The slots are VALU issue slots, so this shares the MODE separation rule's +/// filler reasoning: an ordinary VALU instruction is skipped when EXEC==0, and a +/// V_NOP still issues but occupies no slot there, which makes V_NOP the best +/// available filler rather than a guarantee. The exposure is narrower here than +/// at the MODE write, because the producer is itself EXEC-masked: a wholly +/// inactive shadow ran no WMMA and so has nothing to separate. What remains is +/// an EXEC clear between the WMMA and its shadow, which is the case the TODO +/// below has to rule out before it can count anything but a V_NOP. ExpandResult expand_gfx1250_wmma_iu8_spacing(const Instruction &inst, uint32_t, uint64_t, std::span, const LivenessAnalysis &, TranslationContext &, const LaneLayout *, @@ -1111,20 +1229,15 @@ ExpandResult expand_gfx1250_wmma_iu8_spacing(const Instruction &inst, uint32_t, std::vector words(inst.raw_encoding(), inst.raw_encoding() + inst.size() / sizeof(uint32_t)); const int required_slots = inst.mnemonic() == "v_wmma_i32_16x16x64_iu8" ? 9 : 5; - const uint32_t v_nop = cdna5::build_vop1(cdna5::kVNopVop1)[0]; - int existing_slots = 0; - const Instruction *next = inst.next_instruction(); - while (existing_slots < required_slots && next != nullptr && - next->size() == static_cast(sizeof(uint32_t)) && next->raw_encoding() != nullptr && - next->raw_encoding()[0] == v_nop) { - ++existing_slots; - next = next->next_instruction(); - } + const int existing_slots = + count_adjacent_canonical_v_nops(inst, required_slots, &Instruction::next_instruction); // TODO: Replace canonical V_NOP counting with whole-kernel scheduling that - // can also credit independent VALU in each reachable successor. - for (int slot = existing_slots; slot < required_slots; ++slot) - words.push_back(v_nop); + // can also credit independent VALU in each reachable successor. Crediting real + // VALU needs EXEC != 0 proved on the credited path first; without that proof + // only V_NOP counts, because ordinary VALU is skipped under an empty mask. + words.insert(words.end(), static_cast(required_slots - existing_slots), + cdna5::build_vop1(cdna5::kVNopVop1)[0]); return ExpandResult::success(std::move(words)); } @@ -2319,9 +2432,25 @@ ExpandResult expand_gfx1250_k128_wmma(const Instruction &inst, uint32_t, uint64_ } // The semantic translator binary-searches this table, so entries must stay -// sorted by the full encoding ID and then opcode. VDS encoding IDs include the -// high opcode bits, hence the four consecutive kVdsOpHi* groups below. -inline constexpr std::array kGfx1250B0ToA0ExpandRules = {{ +// sorted by the full encoding ID and then opcode; the static_assert after the +// table enforces that. VDS encoding IDs include the high opcode bits, hence the +// four consecutive kVdsOpHi* groups below. +// An encoding id is the top nine bits of the first word, so a SOPK id is the +// SOPK base plus its opcode. The generated header names only the ids the ISA +// description needed, which is why one of these two has no constant to use; the +// assertions below pin the derivation against the one that does. +constexpr uint16_t kSetregB32EncodingId = cdna5::encoding::kSopk + cdna5::kSSetregB32Sopk; +constexpr uint16_t kSetregImm32B32EncodingId = cdna5::encoding::kSopk + cdna5::kSSetregImm32B32Sopk; +static_assert(kSetregB32EncodingId == cdna5::encoding::kSopkOpHi18, + "SOPK encoding ids must remain the SOPK base plus the opcode"); +static_assert(kSetregImm32B32EncodingId == kSetregB32EncodingId + 1, + "consecutive SOPK opcodes must yield consecutive encoding ids"); + +inline constexpr std::array kGfx1250B0ToA0ExpandRules = {{ + {kSetregB32EncodingId, cdna5::kSSetregB32Sopk, RuleAction::Expand, 0, 0, nullptr, + expand_gfx1250_setreg_mode_ordering, nullptr, nullptr, false}, + {kSetregImm32B32EncodingId, cdna5::kSSetregImm32B32Sopk, RuleAction::Expand, 0, 0, nullptr, + expand_gfx1250_setreg_mode_ordering, nullptr, nullptr, false}, {cdna5::encoding::kSop1, cdna5::kSBarrierSignalIsfirstSop1, RuleAction::Expand, 0, 0, nullptr, expand_gfx1250_barrier_signal_isfirst, nullptr, nullptr, false}, {cdna5::encoding::kSopp, cdna5::kSClauseSopp, RuleAction::Expand, 0, 0, nullptr, @@ -2406,6 +2535,9 @@ inline constexpr std::array kGfx1250B0ToA0ExpandRules = {{ nullptr, expand_gfx1250_cluster_load, nullptr, nullptr}, }}; +static_assert(translation_rules_sorted(kGfx1250B0ToA0ExpandRules), + "the gfx1250 B0-to-A0 rule table must stay sorted by (encoding id, opcode)"); + } // namespace std::span semantic_expand_rules_gfx1250_b0_to_a0() { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp index 630bf861f68c..e7dcd88749fd 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp @@ -10,6 +10,8 @@ #include "rocjitsu/isa/instruction.h" #include +#include +#include namespace rocjitsu { @@ -49,6 +51,13 @@ SemanticTranslator::SemanticTranslator(rj_code_arch_t guest, rj_code_arch_t host expand_rule_keys_.push_back(packed_rule_key(rule.src_encoding_id, rule.src_opcode)); max_encoding_id = std::max(max_encoding_id, rule.src_encoding_id); } + // Every table in the tree static_asserts translation_rules_sorted(), so this + // is the catch-all for one added later without it. Strict ordering, matching + // that predicate: a duplicated key would leave the second rule unreachable + // behind the first. + assert(std::adjacent_find(expand_rule_keys_.begin(), expand_rule_keys_.end(), + std::greater_equal<>{}) == expand_rule_keys_.end() && + "semantic rule tables must stay strictly sorted by (encoding id, opcode)"); if (!expand_rules_.empty()) { // Candidate collection scans every decoded instruction in large kernels. // Most encodings have no handwritten semantic rules, so this tiny bitset diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h index 713fba901ae4..e9184ca2e259 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h @@ -24,8 +24,11 @@ #include "util/bit.h" +#include +#include #include #include +#include #include #include #include @@ -436,6 +439,46 @@ struct TranslationRule { } }; +/// @brief Whether a semantic rule table is strictly ordered for binary search. +/// +/// @details SemanticTranslator::find_expand_rule() binary-searches these tables, +/// so an entry in the wrong place misses its own rule rather than failing. +/// Encoding ids are derived rather than written down -- a SOPK id, for instance, +/// is the SOPK base plus the opcode -- which makes a misplaced entry easy to +/// introduce and silent to observe. Every table static_asserts this. +/// +/// Strict rather than merely nondecreasing: the search takes the first match, so +/// a duplicated (encoding id, opcode) leaves the second rule permanently +/// unreachable -- the same silent miss, arrived at from the other direction. +/// Catching that case depends on the comparison below ordering rules by their +/// key alone, which is what makes two entries that share a key but differ in +/// action or handler compare greater-equal here. Defaulting those operators +/// would keep the out-of-order half working and silently drop the duplicate +/// half. +[[nodiscard]] constexpr bool translation_rules_sorted(std::span rules) { + return std::ranges::adjacent_find(rules, std::ranges::greater_equal{}) == rules.end(); +} + +namespace translation_rule_detail { + +/// @brief Two rules sharing a key but differing in everything else. +/// +/// @details The duplicate half of translation_rules_sorted() works only while +/// the comparison ignores these trailing fields. Defaulting the operators would +/// order this pair by them instead, so the pair would compare ascending, every +/// table in the tree would still satisfy its own assertion, and the duplicate +/// check would be silently gone. Pinning it here fails at the definition rather +/// than at some future table that happens to duplicate a key. +inline constexpr std::array kSameKeyDifferentTail = {{ + {1, 2, RuleAction::Identity, 0, 0, nullptr, nullptr, nullptr, nullptr, true}, + {1, 2, RuleAction::Expand, 3, 0, nullptr, nullptr, nullptr, nullptr, false}, +}}; +static_assert(!translation_rules_sorted(kSameKeyDifferentTail), + "TranslationRule must order by (encoding id, opcode) alone, or " + "translation_rules_sorted() stops rejecting duplicate keys"); + +} // namespace translation_rule_detail + // --------------------------------------------------------------------------- // Tier 3: Lane Layout Descriptor // --------------------------------------------------------------------------- diff --git a/emulation/rocjitsu/tests/corpus/dbt/gfx1250_b0_a0_expected_rewrites.json b/emulation/rocjitsu/tests/corpus/dbt/gfx1250_b0_a0_expected_rewrites.json index f88739b07044..18c4c2981a57 100644 --- a/emulation/rocjitsu/tests/corpus/dbt/gfx1250_b0_a0_expected_rewrites.json +++ b/emulation/rocjitsu/tests/corpus/dbt/gfx1250_b0_a0_expected_rewrites.json @@ -1,7 +1,7 @@ { "expected_rewrites": { "00023c9f3fc277f35d928cca3a2e5614bba26b581e71abd3bbcff3fe3a417405": { - "instructions_requiring_rewrite": 9 + "instructions_requiring_rewrite": 10 } }, "input_revision": "b0", diff --git a/emulation/rocjitsu/tests/corpus/gfx1250_b0_a0_semantic_rewrites.json b/emulation/rocjitsu/tests/corpus/gfx1250_b0_a0_semantic_rewrites.json index d9ffd20d421c..c517e47169cc 100644 --- a/emulation/rocjitsu/tests/corpus/gfx1250_b0_a0_semantic_rewrites.json +++ b/emulation/rocjitsu/tests/corpus/gfx1250_b0_a0_semantic_rewrites.json @@ -2,49 +2,49 @@ "schema": 1, "tests": { "barrier_signal_isfirst_test": { - "instructions_requiring_rewrite": 0 + "instructions_requiring_rewrite": 1 }, "cluster_load_test": { - "instructions_requiring_rewrite": 14 + "instructions_requiring_rewrite": 15 }, "ds_2addr_test": { - "instructions_requiring_rewrite": 9 + "instructions_requiring_rewrite": 10 }, "ds_addtid_test": { - "instructions_requiring_rewrite": 3 + "instructions_requiring_rewrite": 4 }, "ds_storexchg_2addr_test": { - "instructions_requiring_rewrite": 6 + "instructions_requiring_rewrite": 7 }, "fp8_e5m3_unpack_test": { - "instructions_requiring_rewrite": 5 + "instructions_requiring_rewrite": 6 }, "integer_wmma_hazard_test": { - "instructions_requiring_rewrite": 3 + "instructions_requiring_rewrite": 4 }, "s_clause_test": { - "instructions_requiring_rewrite": 1 + "instructions_requiring_rewrite": 2 }, "tensor_load_to_lds_test": { - "instructions_requiring_rewrite": 4 + "instructions_requiring_rewrite": 6 }, "wmma_scale16_m16_test": { - "instructions_requiring_rewrite": 5 + "instructions_requiring_rewrite": 6 }, "wmma_scale16_m32_test": { - "instructions_requiring_rewrite": 8 + "instructions_requiring_rewrite": 9 }, "wmma_scale_regular_test": { - "instructions_requiring_rewrite": 11 + "instructions_requiring_rewrite": 12 }, "wmma_split_f16_test": { - "instructions_requiring_rewrite": 6 + "instructions_requiring_rewrite": 7 }, "wmma_split_f32_test": { - "instructions_requiring_rewrite": 7 + "instructions_requiring_rewrite": 8 }, "wmma_split_fp4_test": { - "instructions_requiring_rewrite": 8 + "instructions_requiring_rewrite": 9 } } } diff --git a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp index c9c415dccdb1..87e59cc0151e 100644 --- a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp @@ -8351,6 +8351,12 @@ TEST(SemanticTranslator, Gfx1250ClassifiesLivenessFreeExpandRules) { } const std::vector expected = { + // A SOPK encoding id is the SOPK base plus the opcode, so the MODE-write + // separation rules sort ahead of everything else in the table. + (static_cast(cdna5::encoding::kSopk + cdna5::kSSetregB32Sopk) << 16) | + cdna5::kSSetregB32Sopk, + (static_cast(cdna5::encoding::kSopk + cdna5::kSSetregImm32B32Sopk) << 16) | + cdna5::kSSetregImm32B32Sopk, (static_cast(cdna5::encoding::kSop1) << 16) | cdna5::kSBarrierSignalIsfirstSop1, (static_cast(cdna5::encoding::kSopp) << 16) | cdna5::kSClauseSopp, (static_cast(cdna5::encoding::kVop3p) << 16) | cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, @@ -8416,7 +8422,7 @@ TEST(BinaryTranslatorE2E, Gfx1250UsesNeutralScaledK128Fp8Bf8Wmma) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr auto completion_wait = kGfx1250WmmaCompletionWait; - EXPECT_EQ(rocjitsu::semantic_expand_rules_gfx1250_b0_to_a0().size(), 41u); + EXPECT_EQ(rocjitsu::semantic_expand_rules_gfx1250_b0_to_a0().size(), 43u); for (const WmmaCase &test_case : cases) { SCOPED_TRACE(test_case.name); auto source_wmma = cdna5::build_vop3p(test_case.source_opcode, fields); @@ -10401,15 +10407,19 @@ TEST(BinaryTranslatorE2E, Gfx1250GeneratedVgprMsbTransitionsCarryPreviousState) rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_GE(decoded.size(), 5u); - EXPECT_EQ(decoded[0]->mnemonic(), "s_setreg_imm32_b32"); + // The guest MODE write opens the block, so its separation rule puts two V_NOPs + // ahead of it before anything this test is about. + ASSERT_GE(decoded.size(), 7u); + EXPECT_EQ(decoded[0]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[1]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[2]->mnemonic(), "s_setreg_imm32_b32"); // The dependency barrier also separates the guest MODE write from the // generated transition. The transition retains its dedicated memory drain. - EXPECT_EQ(decoded[1]->mnemonic(), "s_wait_idle"); - EXPECT_EQ(decoded[2]->mnemonic(), "s_wait_xcnt"); - EXPECT_EQ(decoded[3]->mnemonic(), "s_set_vgpr_msb"); - ASSERT_NE(decoded[3]->raw_encoding(), nullptr); - EXPECT_EQ(decoded[3]->raw_encoding()[0] & 0xffffu, 0x0100u); + EXPECT_EQ(decoded[3]->mnemonic(), "s_wait_idle"); + EXPECT_EQ(decoded[4]->mnemonic(), "s_wait_xcnt"); + EXPECT_EQ(decoded[5]->mnemonic(), "s_set_vgpr_msb"); + ASSERT_NE(decoded[5]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[5]->raw_encoding()[0] & 0xffffu, 0x0100u); // Every generated s_set_vgpr_msb must be immediately preceded by an s_wait_xcnt. std::vector generated_modes; @@ -12771,6 +12781,137 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesFallthroughIntoZeroPadding) { /*guest_offset=*/4)); } +// On this target an s_setreg* naming MODE requires two V_NOPs immediately ahead of it to be ordered +// against the instructions that precede it, and the compiler emits none. The requirement is +// specific to MODE, so a write naming any other hardware register must stay untouched. Both +// spellings carry the selector the same way, so both are covered: the immediate form (opcode 19, +// which carries a literal) and the register-source form (opcode 18, which does not). +TEST(BinaryTranslatorE2E, Gfx1250SeparatesModeWriteWithLeadingVNops) { + // s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 32), 0 -- register id 1. + constexpr uint32_t kSetregWaveMode = 0xb980f801u; + // The same write naming HW_REG_WAVE_STATUS -- register id 2. + constexpr uint32_t kSetregWaveStatus = 0xb980f802u; + // s_setreg_b32 hwreg(HW_REG_WAVE_MODE, 0, 32), s0 -- register id 1, no literal. + constexpr uint32_t kSetregB32WaveMode = 0xb900f801u; + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text( + {kSetregWaveMode, 0u, kSetregWaveStatus, 0u, kSetregB32WaveMode, kGfx1250SEndpgm}); + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + rocjitsu::BinaryTranslator translator( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + auto result = translator.translate(source); + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + + rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_FALSE(translated.text_sections().empty()); + const auto decoded = + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + + ASSERT_EQ(decoded.size(), 8u); + EXPECT_EQ(decoded[0]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[1]->mnemonic(), "v_nop_e32"); + ASSERT_NE(decoded[2]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[2]->raw_encoding()[0], kSetregWaveMode) + << "the MODE write itself must be preserved, only separated"; + // The status write follows the MODE write with no V_NOPs of its own, which is what proves the + // rule discriminates on the hardware-register selector rather than the mnemonic. + ASSERT_NE(decoded[3]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[3]->raw_encoding()[0], kSetregWaveStatus); + // The register-source form is separated on the same terms. Its predecessor is the status write + // rather than a V_NOP, so it receives a fresh pair rather than counting anything. + EXPECT_EQ(decoded[4]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[5]->mnemonic(), "v_nop_e32"); + ASSERT_NE(decoded[6]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[6]->mnemonic(), "s_setreg_b32"); + EXPECT_EQ(decoded[6]->raw_encoding()[0], kSetregB32WaveMode); + EXPECT_EQ(decoded[7]->mnemonic(), "s_endpgm"); + + // Separation already present must be counted, or a repeated translation would keep prepending. + rocjitsu::BinaryTranslator verifier( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + auto second = verifier.translate(translated); + ASSERT_TRUE(second.ok()) << (second.diagnostics.empty() ? "" + : second.diagnostics.front().message); + EXPECT_EQ(second.elf_bytes, result.elf_bytes); +} + +// Counting V_NOPs that are already present is only sound inside one basic block: a V_NOP that a +// branch can jump past does not run before the write on every path that reaches it. The write here +// is a branch target, so its textual predecessors are in another block and must not be counted, +// even though they are canonical V_NOPs sitting immediately in front of it. +TEST(BinaryTranslatorE2E, Gfx1250IgnoresLeadingVNopsAcrossABlockBoundary) { + constexpr uint32_t kSetregWaveMode = 0xb980f801u; + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + const uint32_t v_nop = cdna5::build_vop1(cdna5::kVNopVop1)[0]; + + // s_cbranch_scc0 +2 lands on the MODE write, so the two V_NOPs it skips open no path to it. + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text( + {cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 2})[0], v_nop, v_nop, kSetregWaveMode, + 0u, kGfx1250SEndpgm}); + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + rocjitsu::BinaryTranslator translator( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + auto result = translator.translate(source); + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + + rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_FALSE(translated.text_sections().empty()); + const auto decoded = + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + + ASSERT_EQ(decoded.size(), 7u) + << "the write must receive a fresh pair, not count the skipped ones"; + EXPECT_EQ(decoded[0]->mnemonic(), "s_cbranch_scc0"); + for (size_t i = 1; i < 5; ++i) + EXPECT_EQ(decoded[i]->mnemonic(), "v_nop_e32") << "at index " << i; + ASSERT_NE(decoded[5]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[5]->raw_encoding()[0], kSetregWaveMode); + EXPECT_EQ(decoded[6]->mnemonic(), "s_endpgm"); + + // The branch must land on the separation rather than on the bare write, or the path through it + // would reach the write with no V_NOPs in front at all -- the case this rule exists to prevent. + ASSERT_NE(decoded[0]->raw_encoding(), nullptr); + const size_t landing_word = + 1 + static_cast(static_cast(decoded[0]->raw_encoding()[0] & 0xffffu)); + size_t word = 0; + size_t landing_index = 0; + while (landing_index < decoded.size() && word < landing_word) { + word += static_cast(decoded[landing_index]->size()) / sizeof(uint32_t); + ++landing_index; + } + ASSERT_EQ(word, landing_word) << "the branch must land on an instruction boundary"; + ASSERT_LT(landing_index + 2, decoded.size()); + EXPECT_EQ(decoded[landing_index]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[landing_index + 1]->mnemonic(), "v_nop_e32"); + ASSERT_NE(decoded[landing_index + 2]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[landing_index + 2]->raw_encoding()[0], kSetregWaveMode) + << "exactly two V_NOPs must separate the branch target from the write"; + + // Retargeting moved the write, so this is the case where a second pass could disagree with the + // first about which V_NOPs belong to the write's own block. + rocjitsu::BinaryTranslator verifier( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + auto second = verifier.translate(translated); + ASSERT_TRUE(second.ok()) << (second.diagnostics.empty() ? "" + : second.diagnostics.front().message); + EXPECT_EQ(second.elf_bytes, result.elf_bytes); +} + TEST(BinaryTranslatorE2E, Gfx1250TerminatesSetupFallthroughIntoZeroPadding) { // clang emits this one-instruction body for rocPRIM target-specialized // trampolines whose source ends in __builtin_unreachable(). The following @@ -12794,18 +12935,21 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesSetupFallthroughIntoZeroPadding) { ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_EQ(decoded.size(), 2u) + // The MODE write opens its block, so its separation rule contributes both V_NOPs here. + ASSERT_EQ(decoded.size(), 4u) << "the synthesized endpgm must be the only instruction after the stub body"; - ASSERT_NE(decoded[0]->raw_encoding(), nullptr); - EXPECT_EQ(decoded[0]->mnemonic(), "s_setreg_imm32_b32"); - EXPECT_EQ(decoded[0]->raw_encoding()[0], kSetReplayMode); - EXPECT_EQ(decoded[0]->raw_encoding()[1], kLiteralOne); - EXPECT_EQ(decoded[1]->mnemonic(), "s_endpgm"); + EXPECT_EQ(decoded[0]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[1]->mnemonic(), "v_nop_e32"); + ASSERT_NE(decoded[2]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[2]->mnemonic(), "s_setreg_imm32_b32"); + EXPECT_EQ(decoded[2]->raw_encoding()[0], kSetReplayMode); + EXPECT_EQ(decoded[2]->raw_encoding()[1], kLiteralOne); + EXPECT_EQ(decoded[3]->mnemonic(), "s_endpgm"); const auto kernel_symbol = rocjitsu::test_support::find_elf_symbol_for_test(result.elf_bytes, "kernel"); ASSERT_TRUE(kernel_symbol.has_value()); - EXPECT_EQ(kernel_symbol->st_size, 3 * sizeof(uint32_t)) + EXPECT_EQ(kernel_symbol->st_size, 5 * sizeof(uint32_t)) << "the translated function extent must include its synthesized terminator"; } @@ -12833,15 +12977,18 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesPrefetchSetupFallthroughIntoZeroPaddi ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_EQ(decoded.size(), 4u) + // The prologue's own V_NOP counts toward the MODE write's separation, so it needs + // only one more rather than a fresh pair. + ASSERT_EQ(decoded.size(), 5u) << "the synthesized endpgm must be the only instruction after the stub body"; EXPECT_EQ(decoded[0]->mnemonic(), "global_prefetch_b8"); EXPECT_EQ(decoded[1]->mnemonic(), "v_nop_e32"); - EXPECT_EQ(decoded[2]->mnemonic(), "s_setreg_imm32_b32"); - ASSERT_NE(decoded[2]->raw_encoding(), nullptr); - EXPECT_EQ(decoded[2]->raw_encoding()[0], kSetReplayMode[0]); - EXPECT_EQ(decoded[2]->raw_encoding()[1], kSetReplayMode[1]); - EXPECT_EQ(decoded[3]->mnemonic(), "s_endpgm"); + EXPECT_EQ(decoded[2]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[3]->mnemonic(), "s_setreg_imm32_b32"); + ASSERT_NE(decoded[3]->raw_encoding(), nullptr); + EXPECT_EQ(decoded[3]->raw_encoding()[0], kSetReplayMode[0]); + EXPECT_EQ(decoded[3]->raw_encoding()[1], kSetReplayMode[1]); + EXPECT_EQ(decoded[4]->mnemonic(), "s_endpgm"); } // A stub whose last instruction ends exactly at the end of `.text` has no padding after it, but it @@ -12865,9 +13012,11 @@ TEST(BinaryTranslatorE2E, Gfx1250MaterializesSectionFinalClangUnreachableKernelS rocjitsu::AmdGpuCodeObject first_output(first.elf_bytes.data(), first.elf_bytes.size()); const auto decoded = decode_text_instructions(*first_output.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_EQ(decoded.size(), 2u); - EXPECT_EQ(decoded[0]->mnemonic(), "s_setreg_imm32_b32"); - EXPECT_EQ(decoded[1]->mnemonic(), "s_endpgm"); + ASSERT_EQ(decoded.size(), 4u); + EXPECT_EQ(decoded[0]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[1]->mnemonic(), "v_nop_e32"); + EXPECT_EQ(decoded[2]->mnemonic(), "s_setreg_imm32_b32"); + EXPECT_EQ(decoded[3]->mnemonic(), "s_endpgm"); // Section end is the same inferred boundary as padding, so it must be reported the same way. EXPECT_TRUE(rocjitsu::test_support::has_warning_at(first, rocjitsu::DiagnosticKind::Legalization, "synthesized s_endpgm boundary", diff --git a/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp b/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp index 91e151dc84c9..f4e5db15b759 100644 --- a/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp +++ b/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -280,6 +281,28 @@ bool contains(std::string_view haystack, std::string_view needle) { return haystack.find(needle) != std::string_view::npos; } +/// @brief Read one `name=` field out of the summary line. +/// +/// @details The counters are space-separated, so a substring search for +/// "expand=1" also matches "expand=10". Anchoring on the leading space and +/// reading to the next delimiter makes the comparison numeric, so a count that +/// drifts fails instead of still matching a prefix. +std::optional summary_counter(std::string_view text, std::string_view name) { + const std::string key = " " + std::string(name) + "="; + const size_t at = text.find(key); + if (at == std::string_view::npos) + return std::nullopt; + const size_t first = at + key.size(); + const size_t last = text.find_first_not_of("0123456789", first); + if (last == first) + return std::nullopt; + long long value = 0; + const auto digits = text.substr(first, last - first); + for (const char digit : digits) + value = value * 10 + (digit - '0'); + return value; +} + bool command_succeeded(int status) { return status != -1 && WIFEXITED(status) && WEXITSTATUS(status) == 0; } @@ -724,6 +747,50 @@ TEST(RjDbtTranslate, VerifiesGfx1250ClusterLoadIdempotence) { EXPECT_TRUE(contains(stdout_text, "idempotence_diagnostics: 0")) << stdout_text; } +// A rule registered in the semantic table with no legalization entry reports through a label and a +// counter branch that no other fixture reaches: the existing ones all translate through a +// legalization-classified rule. The MODE separation rule is the only one shaped this way, so +// without this the label and the partition can drift while the suite stays green. +TEST(RjDbtTranslate, ReportsUnclassifiedSemanticExpansionInTheDiff) { + const rocjitsu::test::ScopedTempDirectory temp_dir("rj_dbt_translate_unclassified_semantic_"); + const std::filesystem::path temp_path(temp_dir.path()); + const std::filesystem::path input = temp_path / "mode_setreg_gfx1250.co"; + const std::filesystem::path output = temp_path / "stdout.txt"; + const std::filesystem::path error = temp_path / "stderr.txt"; + + // s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 0, 32), 0 -- the one write the rule separates. + constexpr std::array text_words = {0xb980f801u, 0x00000001u, 0xbfb00000u}; + { + const std::vector image = make_gfx1250_smoke_code_object(text_words); + std::ofstream out(input, std::ios::binary); + out.write(reinterpret_cast(image.data()), + static_cast(image.size())); + } + + const std::string command = shell_quote(g_translate_tool.string()) + " " + + shell_quote(input.string()) + + " --input-target gfx1250 --input-revision b0 --output-target gfx1250 " + "--output-revision a0 --verify-idempotence --output-mode diff > " + + shell_quote(output.string()) + " 2> " + shell_quote(error.string()); + + const int status = std::system(command.c_str()); + const std::string stdout_text = read_text_file(output); + const std::string stderr_text = read_text_file(error); + + ASSERT_TRUE(command_succeeded(status)) << "stderr:\n" + << stderr_text << "\nstdout:\n" + << stdout_text; + EXPECT_TRUE(stderr_text.empty()) << stderr_text; + + // The label must name the rule that rewrote the instruction rather than a re-encode. + EXPECT_TRUE(contains(stdout_text, "expand semantic")) << stdout_text; + // The counters must still partition the total: the expansion belongs to expand, not encode. + EXPECT_EQ(summary_counter(stdout_text, "expand"), 1) << stdout_text; + EXPECT_EQ(summary_counter(stdout_text, "encode"), 0) << stdout_text; + EXPECT_EQ(summary_counter(stdout_text, "semantic"), 1) << stdout_text; + EXPECT_TRUE(contains(stdout_text, "idempotence: verified")) << stdout_text; +} + int main(int argc, char **argv) { if (argc < 2) { std::cerr << "usage: rj_dbt_translate_smoke_test \n"; diff --git a/emulation/rocjitsu/tools/dbt_translate.h b/emulation/rocjitsu/tools/dbt_translate.h index f8051bc90880..c9c4c9c52a8c 100644 --- a/emulation/rocjitsu/tools/dbt_translate.h +++ b/emulation/rocjitsu/tools/dbt_translate.h @@ -63,6 +63,24 @@ struct InstructionTranslationReport { uint64_t target_offset = 0; std::vector target_words; std::vector target_instructions; + + /// @brief What actually happened to this instruction, as one value. + /// + /// @details The label and the action counters must agree, and reconstructing + /// the rules for that at each consumer is how they drift apart. The one case + /// that is not simply `action` is a semantic rule carrying an instruction with + /// no legalization entry naming it: that is an expansion, and reporting it as + /// a re-encode would hide the rule that rewrote the instruction. + /// + /// @returns The effective legalization action, or nullopt when the instruction + /// was copied verbatim or re-encoded without a rule. + [[nodiscard]] std::optional effective_action() const { + if (copied_original) + return std::nullopt; + if (!has_legalization) + return semantic_lowering ? std::optional(Action::Expand) : std::nullopt; + return action; + } }; struct TranslateOptions { diff --git a/emulation/rocjitsu/tools/dbt_translate_cli.cpp b/emulation/rocjitsu/tools/dbt_translate_cli.cpp index 1e241d52fe7f..a725cbd9cad4 100644 --- a/emulation/rocjitsu/tools/dbt_translate_cli.cpp +++ b/emulation/rocjitsu/tools/dbt_translate_cli.cpp @@ -386,10 +386,15 @@ void print_diagnostic(std::ostream &os, const TranslationDiagnostic &diagnostic, [[nodiscard]] std::string translation_action_text(const InstructionTranslationReport &translation) { if (translation.copied_original) return "copy_original"; - if (!translation.has_legalization) + + // An unclassified semantic lowering deliberately reads the same as a + // classified expansion: whether a legalization entry also named the opcode is + // internal to the profile, and the action the reader sees is the same one. + const auto action = translation.effective_action(); + if (!action) return "encode"; - std::string text = legalization_action_name(translation.action); + std::string text = legalization_action_name(*action); if (translation.semantic_lowering) text += " semantic"; return text; @@ -404,23 +409,19 @@ void print_diagnostic(std::ostream &os, const TranslationDiagnostic &diagnostic, [[nodiscard]] size_t count_action(const std::vector &translations, Action action) { - size_t count = 0; - for (const auto &translation : translations) { - if (!translation.copied_original && translation.has_legalization && - translation.action == action) - ++count; - } - return count; + return static_cast(std::ranges::count_if( + translations, [action](const InstructionTranslationReport &translation) { + return translation.effective_action() == action; + })); } +/// @brief Instructions re-encoded with no rule: not copied, and no action. [[nodiscard]] size_t count_runtime_encode(const std::vector &translations) { - size_t count = 0; - for (const auto &translation : translations) { - if (!translation.copied_original && !translation.has_legalization) - ++count; - } - return count; + return static_cast( + std::ranges::count_if(translations, [](const InstructionTranslationReport &translation) { + return !translation.copied_original && !translation.effective_action(); + })); } [[nodiscard]] size_t From ded43b17877ce848952f4fee4e0e319e41d2bd47 Mon Sep 17 00:00:00 2001 From: James Newling Date: Mon, 17 Aug 2026 10:10:04 -0700 Subject: [PATCH 06/27] fix(rocjitsu): disable zero-count TDM descriptors (#9941) ## Summary This small change makes tensor-DMA load and store operations honor a zero descriptor count as a disabled transfer. The gap was found while reducing the stock gfx1250 TensileLite TDM workload tracked by #9935. Generated TensileLite code explicitly writes zero to the descriptor Group 0 count field when disabling TDM loads in the final prefetch iterations, but rocJITsu previously ignored that field and executed the transfer. ## Related contract evidence - ROCm/rocm-libraries#7453 introduced the HalfPLR TDM disable convention by conditionally clearing descriptor Group 0 and restoring it before the tail loop. - ROCm/rocm-systems#7361 established the shared TDM wait-counter and atomic barrier sequencing that this PR preserves inside the common load/store executor. ## Failure before this fix A descriptor that generated code had disabled could still copy global data into LDS or store LDS data to global memory. If the descriptor requested an atomic-barrier arrival, that side effect was also performed. ## Fix - Parse the two-bit count field from descriptor Group 0. - Represent descriptor activity as part of the parsed descriptor contract. - Route load and store through one common tensor-DMA executor, which performs no copy or barrier side effect for an inactive descriptor. ## Test coverage The focused regression initializes global memory, LDS, and an atomic barrier with distinct values, executes decoded load and store instructions, and verifies that both operations leave all three unchanged. Existing tensor-DMA execution tests continue to pass. ## Workload status This PR fixes one independent descriptor contract. It does not claim to resolve the complete TensileLite reproducer or the remaining tail-loop semantic question. ## Issue tracking Progress toward #9935. (cherry picked from commit 00aa1e260fed071474909b4869c1a448dcf059c1) --- .../isa/arch/amdgpu/shared/tensor_dma.h | 31 ++++--- .../rocjitsu/tests/cdna5_tensor_dma_test.cpp | 87 +++++++++++++++++++ 2 files changed, 108 insertions(+), 10 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h index 56639e0a531d..b45a6949233f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h @@ -58,6 +58,7 @@ struct TensorDmaDescriptor { std::array d1{}; std::array d2{}; std::array d3{}; + uint32_t count = 0; uint64_t global_base = 0; uint32_t lds_base = 0; uint32_t elem_size = 0; @@ -78,6 +79,8 @@ struct TensorDmaDescriptor { bool iterate = false; bool pad = false; + bool active() const { return count != 0; } + uint32_t rank() const { if (gather) { if (tensor_dims[1] != 0) @@ -112,6 +115,7 @@ inline TensorDmaDescriptor parse_descriptor(std::array d0, std::arr // Descriptor bit layout follows LLVM MLIR's gfx1250 TDM lowering in // mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp. + desc.count = d0[0] & 0x3u; desc.gather_indices_32bit = (d0[0] & (1u << 30)) != 0; desc.gather = (d0[0] & (1u << 31)) != 0; desc.lds_base = d0[1]; @@ -180,6 +184,10 @@ inline TensorDmaDescriptor parse_descriptor(std::array d0, std::arr } inline void validate_supported_descriptor(const TensorDmaDescriptor &desc, bool store_from_lds) { + // The in-tree HIP descriptor API and LLVM lowering only produce the boolean + // count encodings 0 (disabled) and 1 (active). + if (desc.count > 1) + throw util::UnimplementedInst("tensor DMA count encoding"); // LLVM MLIR's AMDGPU dialect documents padding only for memory-to-LDS copies. if (desc.pad && store_from_lds) throw util::UnimplementedInst("tensor DMA padded store descriptor"); @@ -340,22 +348,25 @@ TensorDmaDescriptor read_descriptor(const Inst &inst, const Wavefront &wf) { read_sgpr_group<4>(wf, inst.vaddr3.encoding_value(), true)); } +template +void execute_tensor_dma(const Inst &inst, Wavefront &wf, bool store_from_lds) { + ScopedWaitCounter counter(wf, WaitCounterType::TENSORCNT); + const auto desc = read_descriptor(inst, wf); + if (!desc.active()) + return; + copy_tensor(desc, wf, store_from_lds); + if (desc.atomic_barrier) + arrive_atomic_barrier(desc, wf); +} + } // namespace tensor_dma_detail template void execute_tensor_load_to_lds(const Inst &inst, Wavefront &wf) { - tensor_dma_detail::ScopedWaitCounter counter(wf, WaitCounterType::TENSORCNT); - const auto desc = tensor_dma_detail::read_descriptor(inst, wf); - tensor_dma_detail::copy_tensor(desc, wf, false); - if (desc.atomic_barrier) - tensor_dma_detail::arrive_atomic_barrier(desc, wf); + tensor_dma_detail::execute_tensor_dma(inst, wf, false); } template void execute_tensor_store_from_lds(const Inst &inst, Wavefront &wf) { - tensor_dma_detail::ScopedWaitCounter counter(wf, WaitCounterType::TENSORCNT); - const auto desc = tensor_dma_detail::read_descriptor(inst, wf); - tensor_dma_detail::copy_tensor(desc, wf, true); - if (desc.atomic_barrier) - tensor_dma_detail::arrive_atomic_barrier(desc, wf); + tensor_dma_detail::execute_tensor_dma(inst, wf, true); } } // namespace amdgpu diff --git a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp index a8f19a1fedb5..0d3b70b837f2 100644 --- a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp @@ -352,6 +352,93 @@ TEST(Gfx1250ExecutionTest, TensorDmaIterateCopiesMultipleTiles) { EXPECT_EQ(cu->lds().read32(wf->lds_base() + 7 * 4), kSentinel); } +TEST(Gfx1250ExecutionTest, TensorDmaZeroCountDisablesLoadStoreAndBarrier) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kLoadGlobal = 0x133000; + constexpr uint64_t kStoreGlobal = 0x134000; + constexpr uint32_t kElements = 4; + constexpr uint32_t kBarrierLdsAddr = 64; + constexpr uint32_t kLdsSentinel = 0xC0DEC0DEu; + constexpr uint32_t kGlobalSentinel = 0xA11CA11Cu; + + write_tensor_dma_d0(*cu, *wf, 0, kLoadGlobal); + write_wave_sgpr(*cu, *wf, 0, 0); // Count zero disables this descriptor. + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 18)); // i32, atomic barrier enabled. + write_wave_sgpr(*cu, *wf, 13, (kElements << 16) | (kBarrierLdsAddr >> 3)); + write_wave_sgpr(*cu, *wf, 14, 0); + write_wave_sgpr(*cu, *wf, 15, kElements << 16); + write_wave_sgpr(*cu, *wf, 16, 0); + write_wave_sgpr(*cu, *wf, 17, 0); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + + for (uint32_t i = 0; i < kElements; ++i) { + write_global_u32(*sim.memory, kLoadGlobal + i * sizeof(uint32_t), 0x47000000u + i); + write_global_u32(*sim.memory, kStoreGlobal + i * sizeof(uint32_t), kGlobalSentinel); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kLdsSentinel); + } + cu->lds().write64(wf->lds_base() + kBarrierLdsAddr, 0); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c7c0c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), kLdsSentinel); + EXPECT_EQ(cu->lds().read64(wf->lds_base() + kBarrierLdsAddr), 0u); + EXPECT_TRUE(wf->wait_counters().empty()); + + for (uint32_t i = 0; i < kElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), 0x48000000u + i); + write_tensor_dma_d0(*cu, *wf, 0, kStoreGlobal); + write_wave_sgpr(*cu, *wf, 0, 0); // Keep the store descriptor disabled. + + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x7c7c0c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + + for (uint32_t i = 0; i < kElements; ++i) + EXPECT_EQ(read_global_u32(*sim.memory, kStoreGlobal + i * sizeof(uint32_t)), kGlobalSentinel); + EXPECT_EQ(cu->lds().read64(wf->lds_base() + kBarrierLdsAddr), 0u); + EXPECT_TRUE(wf->wait_counters().empty()); +} + +TEST(Gfx1250ExecutionTest, TensorDmaUnsupportedCountEncodingsAreRejected) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + write_tensor_dma_d0(*cu, *wf, 0, 0x138000); + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32. + write_wave_sgpr(*cu, *wf, 13, 1u << 16); + write_wave_sgpr(*cu, *wf, 14, 0); + write_wave_sgpr(*cu, *wf, 15, 1u << 16); + write_wave_sgpr(*cu, *wf, 16, 0); + write_wave_sgpr(*cu, *wf, 17, 0); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c7c0c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + + for (uint32_t count : {2u, 3u}) { + SCOPED_TRACE("count=" + std::to_string(count)); + write_wave_sgpr(*cu, *wf, 0, count); + EXPECT_THROW(load->execute(*load, wf), util::UnimplementedInst); + EXPECT_TRUE(wf->wait_counters().empty()); + } +} + TEST(Gfx1250ExecutionTest, TensorDmaAtomicBarrierArrivesAfterCopy) { Gfx1250Sim sim; auto *cu = sim.cu(); From 50ca7f1732a7e7de8e3c5f2cb030929c0a4caf40 Mon Sep 17 00:00:00 2001 From: Fei Kou Date: Mon, 17 Aug 2026 12:52:41 -0700 Subject: [PATCH 07/27] [rocjitsu] Apply MUBUF LDS-load instruction offset to the LDS address (#10192) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Motivation `buffer_load_* ... lds` ignores the instruction's immediate `offset` when computing the LDS destination address in the simulator. Per the CDNA3/CDNA4 ISA reference guides, §9.1.9 "Memory Buffer Load to LDS": ``` LDS_ADDR = LDSbase + LDS_offset (M0) + inst_offset + (TIDinWave * 4) MEM_ADDR = Base + mem_offset (soffset) + inst_offset + off_vgpr + stride * (idx_vgpr + TIDinWave) ``` `inst_offset` feeds both addresses (LLVM `IntrinsicsAMDGPU.td`, `int_amdgcn_load_to_lds`, which also covers buffer fat pointers: "imm offset (applied to both input and LDS address)"). Kernels that set M0 once and issue several `buffer_load_dword ... offen offset:0/256/512 lds` to fill consecutive LDS tiles therefore kept overwriting the first tile under the simulator. ## Technical Details - `lib/python/amdisa/codegen/_generator.py`: the MUBUF LDS-load template now sets `d->lds_base = wf.m0() + inst_.offset + wf.lds_base()`. `soffset` and the VGPR offset stay memory-side only, matching the formula above. - Regenerated `generated/{cdna1,cdna2,cdna3,cdna4,rdna1,rdna2}/mubuf_exec.cpp` (documented `python -m amdisa --multi ... --gen-isas` flow + clang-format). With the in-tree ISA XMLs the unmodified generator reproduces every checked-in `mubuf*` file byte-for-byte; the only resulting change is that one line in the 18 `buffer_load_*` LDS branches per file. gfx1250's `*_load_async_to_lds_*` (per-lane VGPR LDS address, separate template) and rdna3_5's `buffer_load_lds_*` stubs (`UnimplementedInst`) are untouched; rdna3/rdna4 generate no MUBUF LDS-load path. - `tests/amdgpu_vm_test.cpp`: `MubufLdsTest.LoadDwordLdsAppliesInstOffset` (CPU-only, cdna1-4): M0 = 0x200, two encoded `buffer_load_dword v1, s[4:7], 0 offen [offset:256] lds` from two distinct source rows, all 64 lanes of both LDS rows checked. ## Issue Tracking No existing issue; related: #5747 (workgroup `lds_base` term on the same path). ## Test Plan - `rocjitsu_tests --gtest_filter='MubufLdsTest.*'` before and after the generator change. - `python -m pytest lib/python/amdisa/tests` and full `ctest` for regressions. ## Test Result - `MubufLdsTest.LoadDwordLdsAppliesInstOffset`: on unmodified `develop` it fails for all four CDNA targets (lane 0: LDS+0x200 reads 0xB0000000 instead of 0xA0000000 because the `offset:256` load overwrote row 0; LDS+0x300 still holds the 0xDEADBEEF fill); passes with this change. - Cross-checked on gfx950 hardware (ROCm 7.2.0) with an equivalent inline-asm kernel: the two rows land at LDS+0 and LDS+256 on hardware; the simulator matches only with this change. - Full `ctest`: no status changes versus `develop` other than the added `MubufLdsTest.LoadDwordLdsAppliesInstOffset`. - `python -m pytest lib/python/amdisa/tests`: 1319 passed, 46 skipped. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit c810647609524ae45f9521f58d0ca2cc5542bc0a) --- .../lib/python/amdisa/codegen/_generator.py | 2 +- .../amdgpu/generated/cdna1/mubuf_exec.cpp | 36 +++++----- .../amdgpu/generated/cdna2/mubuf_exec.cpp | 36 +++++----- .../amdgpu/generated/cdna3/mubuf_exec.cpp | 36 +++++----- .../amdgpu/generated/cdna4/mubuf_exec.cpp | 36 +++++----- .../amdgpu/generated/rdna1/mubuf_exec.cpp | 36 +++++----- .../amdgpu/generated/rdna2/mubuf_exec.cpp | 36 +++++----- emulation/rocjitsu/tests/amdgpu_vm_test.cpp | 72 +++++++++++++++++++ 8 files changed, 181 insertions(+), 109 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index a5192c28f2d3..fbaa203c37c2 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -6402,7 +6402,7 @@ def _gen_buffer_load( if counter is not None: L.append(f' d->wait_counter_type = {counter};') L.append(' d->lds_dst = true;') - L.append(' d->lds_base = wf.m0() + wf.lds_base();') + L.append(' d->lds_base = wf.m0() + inst_.offset + wf.lds_base();') L.append(f' d->mtype = {self._mtype_expr()};') L.append(f' d->non_temporal = {nt};') L.append(f' {addr_fn}(inst_, wf, *d);') diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf_exec.cpp index a928e8986296..c4a848debfa9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf_exec.cpp @@ -32,7 +32,7 @@ void BufferLoadFormatXMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -59,7 +59,7 @@ void BufferLoadFormatXyMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -86,7 +86,7 @@ void BufferLoadFormatXyzMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -113,7 +113,7 @@ void BufferLoadFormatXyzwMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -280,7 +280,7 @@ void BufferLoadUbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -307,7 +307,7 @@ void BufferLoadSbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -335,7 +335,7 @@ void BufferLoadUshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -362,7 +362,7 @@ void BufferLoadSshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -390,7 +390,7 @@ void BufferLoadDwordMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -417,7 +417,7 @@ void BufferLoadDwordx2Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -444,7 +444,7 @@ void BufferLoadDwordx3Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -471,7 +471,7 @@ void BufferLoadDwordx4Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -688,7 +688,7 @@ void BufferLoadUbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -716,7 +716,7 @@ void BufferLoadUbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -744,7 +744,7 @@ void BufferLoadSbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -773,7 +773,7 @@ void BufferLoadSbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -802,7 +802,7 @@ void BufferLoadShortD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -830,7 +830,7 @@ void BufferLoadShortD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf_exec.cpp index 356198d6cb3c..d4e23643d2af 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf_exec.cpp @@ -32,7 +32,7 @@ void BufferLoadFormatXMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -59,7 +59,7 @@ void BufferLoadFormatXyMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -86,7 +86,7 @@ void BufferLoadFormatXyzMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -113,7 +113,7 @@ void BufferLoadFormatXyzwMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -280,7 +280,7 @@ void BufferLoadUbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -307,7 +307,7 @@ void BufferLoadSbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -335,7 +335,7 @@ void BufferLoadUshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -362,7 +362,7 @@ void BufferLoadSshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -390,7 +390,7 @@ void BufferLoadDwordMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -417,7 +417,7 @@ void BufferLoadDwordx2Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -444,7 +444,7 @@ void BufferLoadDwordx3Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -471,7 +471,7 @@ void BufferLoadDwordx4Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -688,7 +688,7 @@ void BufferLoadUbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -716,7 +716,7 @@ void BufferLoadUbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -744,7 +744,7 @@ void BufferLoadSbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -773,7 +773,7 @@ void BufferLoadSbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -802,7 +802,7 @@ void BufferLoadShortD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -830,7 +830,7 @@ void BufferLoadShortD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf_exec.cpp index 289b34927510..e93b33698d2a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf_exec.cpp @@ -34,7 +34,7 @@ void BufferLoadFormatXMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -61,7 +61,7 @@ void BufferLoadFormatXyMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -88,7 +88,7 @@ void BufferLoadFormatXyzMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -115,7 +115,7 @@ void BufferLoadFormatXyzwMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -282,7 +282,7 @@ void BufferLoadUbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -309,7 +309,7 @@ void BufferLoadSbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -337,7 +337,7 @@ void BufferLoadUshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -364,7 +364,7 @@ void BufferLoadSshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -392,7 +392,7 @@ void BufferLoadDwordMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -419,7 +419,7 @@ void BufferLoadDwordx2Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -446,7 +446,7 @@ void BufferLoadDwordx3Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -473,7 +473,7 @@ void BufferLoadDwordx4Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -690,7 +690,7 @@ void BufferLoadUbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -718,7 +718,7 @@ void BufferLoadUbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -746,7 +746,7 @@ void BufferLoadSbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -775,7 +775,7 @@ void BufferLoadSbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -804,7 +804,7 @@ void BufferLoadShortD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -832,7 +832,7 @@ void BufferLoadShortD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf_exec.cpp index b8bd9f8d8678..36157cc3375c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf_exec.cpp @@ -34,7 +34,7 @@ void BufferLoadFormatXMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -61,7 +61,7 @@ void BufferLoadFormatXyMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -88,7 +88,7 @@ void BufferLoadFormatXyzMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -115,7 +115,7 @@ void BufferLoadFormatXyzwMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -282,7 +282,7 @@ void BufferLoadUbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -309,7 +309,7 @@ void BufferLoadSbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -337,7 +337,7 @@ void BufferLoadUshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -364,7 +364,7 @@ void BufferLoadSshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -392,7 +392,7 @@ void BufferLoadDwordMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -419,7 +419,7 @@ void BufferLoadDwordx2Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -446,7 +446,7 @@ void BufferLoadDwordx3Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -473,7 +473,7 @@ void BufferLoadDwordx4Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -690,7 +690,7 @@ void BufferLoadUbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -718,7 +718,7 @@ void BufferLoadUbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -746,7 +746,7 @@ void BufferLoadSbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -775,7 +775,7 @@ void BufferLoadSbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -804,7 +804,7 @@ void BufferLoadShortD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); @@ -832,7 +832,7 @@ void BufferLoadShortD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx940(inst_.sc0, inst_.sc1, inst_.nt); d->non_temporal = inst_.nt; mubuf_calculate_addresses(inst_, wf, *d); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf_exec.cpp index fb9d44a2bd59..35cd50b559b2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf_exec.cpp @@ -33,7 +33,7 @@ void BufferLoadFormatXMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -60,7 +60,7 @@ void BufferLoadFormatXyMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -87,7 +87,7 @@ void BufferLoadFormatXyzMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -114,7 +114,7 @@ void BufferLoadFormatXyzwMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -241,7 +241,7 @@ void BufferLoadUbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -268,7 +268,7 @@ void BufferLoadSbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -296,7 +296,7 @@ void BufferLoadUshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -323,7 +323,7 @@ void BufferLoadSshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -351,7 +351,7 @@ void BufferLoadDwordMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -378,7 +378,7 @@ void BufferLoadDwordx2Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -405,7 +405,7 @@ void BufferLoadDwordx4Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -432,7 +432,7 @@ void BufferLoadDwordx3Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -649,7 +649,7 @@ void BufferLoadUbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -677,7 +677,7 @@ void BufferLoadUbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -705,7 +705,7 @@ void BufferLoadSbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -734,7 +734,7 @@ void BufferLoadSbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -763,7 +763,7 @@ void BufferLoadShortD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -791,7 +791,7 @@ void BufferLoadShortD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf_exec.cpp index 8fa566d4e48d..4e66df2e8e83 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf_exec.cpp @@ -33,7 +33,7 @@ void BufferLoadFormatXMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -60,7 +60,7 @@ void BufferLoadFormatXyMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -87,7 +87,7 @@ void BufferLoadFormatXyzMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -114,7 +114,7 @@ void BufferLoadFormatXyzwMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -241,7 +241,7 @@ void BufferLoadUbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -268,7 +268,7 @@ void BufferLoadSbyteMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -296,7 +296,7 @@ void BufferLoadUshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -323,7 +323,7 @@ void BufferLoadSshortMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -351,7 +351,7 @@ void BufferLoadDwordMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -378,7 +378,7 @@ void BufferLoadDwordx2Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -405,7 +405,7 @@ void BufferLoadDwordx4Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -432,7 +432,7 @@ void BufferLoadDwordx3Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -649,7 +649,7 @@ void BufferLoadUbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -677,7 +677,7 @@ void BufferLoadUbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -705,7 +705,7 @@ void BufferLoadSbyteD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -734,7 +734,7 @@ void BufferLoadSbyteD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -763,7 +763,7 @@ void BufferLoadShortD16Mubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); @@ -791,7 +791,7 @@ void BufferLoadShortD16HiMubuf::execute_impl(amdgpu::Wavefront &wf) { d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::VMCNT; d->lds_dst = true; - d->lds_base = wf.m0() + wf.lds_base(); + d->lds_base = wf.m0() + inst_.offset + wf.lds_base(); d->mtype = amdgpu::mtype_from_flags_gfx10(inst_.glc, inst_.dlc, inst_.slc); d->non_temporal = 0; mubuf_calculate_addresses(inst_, wf, *d); diff --git a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp index 8409f26342c9..4bd69697e2b9 100644 --- a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp +++ b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp @@ -2197,6 +2197,9 @@ constexpr uint32_t v_add_u32(uint32_t vdst, uint32_t s0, uint32_t vs1) { constexpr uint32_t v_cndmask_b32(uint32_t vdst, uint32_t s0, uint32_t vs1) { return vop2(0, vdst, s0, vs1); } +constexpr uint32_t v_lshlrev_b32(uint32_t vdst, uint32_t s0, uint32_t vs1) { + return vop2(18, vdst, s0, vs1); +} // VOPC: encoding[31:25]=0x3E, op[24:17], vsrc1[16:9], src0[8:0] constexpr uint32_t vopc(uint32_t op, uint32_t src0, uint32_t vsrc1) { @@ -2226,6 +2229,20 @@ constexpr uint32_t flat_hi(uint32_t vdst, uint32_t data, uint32_t addr, uint32_t return (vdst << 24) | (saddr << 16) | (data << 8) | addr; } +// MUBUF (64-bit): CDNA layout. +// dword0: offset[11:0], offen[12], idxen[13], sc0[14], sc1[15], lds[16], nt[17], +// op[24:18], encoding[31:26]=0x38 +// dword1: vaddr[7:0], vdata[15:8], srsrc[20:16], acc[23], soffset[31:24] +constexpr uint32_t mubuf_lo(uint32_t op, uint32_t offset = 0, uint32_t offen = 0, + uint32_t idxen = 0, uint32_t lds = 0) { + return (0x38u << 26) | (op << 18) | (lds << 16) | (idxen << 13) | (offen << 12) | + (offset & 0xFFFu); +} +constexpr uint32_t mubuf_hi(uint32_t vdata, uint32_t vaddr, uint32_t srsrc, + uint32_t soffset = INLINE_CONST(0)) { + return (soffset << 24) | (srsrc << 16) | (vdata << 8) | vaddr; +} + constexpr uint32_t S_WAITCNT_0 = sopp(12, 0); constexpr uint32_t S_ENDPGM = sopp(1, 0); @@ -3072,6 +3089,61 @@ TEST(AtomicStressTest, GlobalAtomicAdd_MultiWorkgroup) { EXPECT_EQ(final_val, 1256u) << "1000 + 256 global atomic adds = 1256"; } +// buffer_load_dword lds: offset:0 -> LDS+0x200, offset:256 -> LDS+0x300; M0 supplies the base. +TEST(MubufLdsTest, LoadDwordLdsAppliesInstOffset) { + constexpr uint64_t kSrcAddr = 0x2000ULL; + constexpr uint32_t kRowBytes = 64 * sizeof(uint32_t); + constexpr uint32_t kLdsBase = 0x200; // M0 + constexpr uint32_t kSrd = 4; // s[4:7] + constexpr uint32_t kBufferLoadDword = 20; + constexpr uint32_t kM0 = 124; + constexpr uint32_t kSentinel = 0xDEADBEEFu; + + using namespace enc; + const uint32_t code[] = { + s_mov_b32(SGPR(kSrd), 255), + static_cast(kSrcAddr), // SRD base + s_mov_b32(SGPR(kSrd + 1), INLINE_CONST(0)), + s_mov_b32(SGPR(kSrd + 2), 255), + 2 * kRowBytes, // num_records + s_mov_b32(SGPR(kSrd + 3), 255), + 0x00020000u, // word3: dword format + s_mov_b32(kM0, 255), + kLdsBase, + v_lshlrev_b32(1, INLINE_CONST(2), 0), // v1 = lane * 4 + mubuf_lo(kBufferLoadDword, /*offset=*/0, /*offen=*/1, /*idxen=*/0, /*lds=*/1), + mubuf_hi(/*vdata=*/0, /*vaddr=*/1, kSrd / 4), + mubuf_lo(kBufferLoadDword, /*offset=*/kRowBytes, /*offen=*/1, /*idxen=*/0, /*lds=*/1), + mubuf_hi(/*vdata=*/0, /*vaddr=*/1, kSrd / 4), + S_WAITCNT_0, + S_ENDPGM, + }; + + for (std::string_view arch : {"cdna1", "cdna2", "cdna3", "cdna4"}) { + SCOPED_TRACE(arch); + VmFixture f(arch); + uint64_t ko = f.write_kernel(0x1000, code, sizeof(code)); + + for (uint32_t lane = 0; lane < 64; ++lane) { + f.mem()->write32(kSrcAddr + lane * 4, 0xA0000000u | lane); + f.mem()->write32(kSrcAddr + kRowBytes + lane * 4, 0xB0000000u | lane); + } + for (uint32_t i = 0; i < 2 * kRowBytes; i += 4) + f.cu()->lds().write32(kLdsBase + i, kSentinel); + + test::AqlQueue queue(f.mem(), f.cp()); + queue.dispatch(ko, 64, 64); + ASSERT_NO_THROW(f.engine->run()); + + for (uint32_t lane = 0; lane < 64; ++lane) { + EXPECT_EQ(f.cu()->lds().read32(kLdsBase + lane * 4), 0xA0000000u | lane) + << "row 0 lane " << lane; + EXPECT_EQ(f.cu()->lds().read32(kLdsBase + kRowBytes + lane * 4), 0xB0000000u | lane) + << "row 1 lane " << lane; + } + } +} + // Verify that ds_read_b64_tr_b16 with acc=1 writes to AccVGPR (vb+256+vdst), // not to VGPR (vb+vdst). TEST(DsTransposeTest, ReadB64TrB16_AccBit) { From 2e6bf26943e0163a54151c8f1f4087e8be292a29 Mon Sep 17 00:00:00 2001 From: Austin Lu Date: Mon, 17 Aug 2026 16:39:54 -0400 Subject: [PATCH 08/27] [rocjitsu] code rewrite condition validator (#9560) ## Motivation Add another rewrite validator similar to the idempotence check. This confirms that no registered rewrite condition remains after rewrites are applied. (Idempotence would not, for example, detect a rewrite that happened to be the identity rewrite). ## Technical Details - refactor rewrites into central registry shared by both the existing rewrite system and the new validator. -Include operand-driven rewrites in the refactored registry, since they were not representable by the existing opcode-keyed table. - Implement read only pass over translated binary to check for remaining rewrite sites. ## Issue Tracking N/A ## Test Plan Enable this checking pass over the existing rewrite tests + add tests for remaining added interface. ## Test Result Tests pass ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit 1d7866269d301cfe90bd5fb780e2b5fcfc2caa5c) --- .github/workflows/rocjitsu-corpus-tests.yml | 2 +- emulation/rocjitsu/docs/dbt-design.md | 17 +- .../rocjitsu/docs/isa-target-providers.md | 6 + emulation/rocjitsu/docs/rj_dbt_translate.md | 90 + .../lib/python/amdisa/codegen/_generator.py | 73 +- .../tests/test_generator_profile_gates.py | 125 + .../analysis/indirect_branch_discovery.cpp | 1 - .../src/rocjitsu/code/amdgpu_code_object.cpp | 50 +- .../src/rocjitsu/code/amdgpu_code_object.h | 3 + .../rocjitsu/src/rocjitsu/code/amdgpu_elf.h | 190 +- .../rocjitsu/src/rocjitsu/code/code_object.h | 13 + .../rocjitsu/code/dbt/binary_translator.cpp | 562 +++- .../src/rocjitsu/code/dbt/binary_translator.h | 16 + .../code/dbt/binary_translator_internal.h | 31 + .../code/dbt/gfx1250_b0_to_a0_library.cpp | 3 + .../code/dbt/kernel_descriptor_translator.cpp | 12 +- .../code/dbt/kernel_descriptor_translator.h | 3 +- .../dbt/legalization/gfx1250_b0_to_a0.cpp | 16 +- .../code/dbt/semantic/gfx1250_b0_to_a0.cpp | 330 ++- .../semantic/gfx1250_flat_scratch_base.cpp | 24 + .../dbt/semantic/gfx1250_flat_scratch_base.h | 8 + .../src/rocjitsu/code/dbt/semantic/rules.h | 3 + .../rocjitsu/code/dbt/semantic_translator.cpp | 116 +- .../rocjitsu/code/dbt/semantic_translator.h | 56 +- .../code/dbt/translation_diagnostic.h | 13 +- .../src/rocjitsu/code/dbt/translation_rule.h | 150 ++ .../rocjitsu/src/rocjitsu/code/executable.cpp | 13 +- .../rocjitsu/code/kernel_descriptor_scan.cpp | 20 +- .../rocjitsu/code/kernel_descriptor_scan.h | 5 +- .../code/patch/code_object_patcher.cpp | 245 +- .../rocjitsu/code/patch/code_object_patcher.h | 20 +- .../code/relocation_function_table.cpp | 2 + .../src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp | 5 + .../isa/arch/amdgpu/generated/cdna1/decoder.h | 3 + .../isa/arch/amdgpu/generated/cdna2/decoder.h | 3 + .../isa/arch/amdgpu/generated/cdna3/decoder.h | 3 + .../isa/arch/amdgpu/generated/cdna4/decoder.h | 3 + .../isa/arch/amdgpu/generated/cdna5/decoder.h | 3 + .../isa/arch/amdgpu/generated/rdna1/decoder.h | 3 + .../isa/arch/amdgpu/generated/rdna2/decoder.h | 3 + .../isa/arch/amdgpu/generated/rdna3/decoder.h | 3 + .../arch/amdgpu/generated/rdna3_5/decoder.h | 3 + .../isa/arch/amdgpu/generated/rdna4/decoder.h | 3 + .../src/rocjitsu/isa/arch/risc_v/decoder.h | 2 + .../lib/rocjitsu/src/rocjitsu/isa/decoder.h | 8 + .../rocjitsu/tests/analysis/liveness_test.cpp | 2 + .../tests/code/amdgpu_code_object_test.cpp | 44 + .../code/relocation_function_table_test.cpp | 50 + .../dbt/gfx1250_b0_to_a0_library_test.cpp | 1 + .../relocation_function_table_hip_test.cpp | 73 + .../dbt/support/translate_test_support.cpp | 86 +- .../dbt/support/translate_test_support.h | 18 +- .../tests/dbt/translate_gfx1250_test.cpp | 485 +++- .../rocjitsu/tests/dbt/translate_test.cpp | 2265 +++++++++++++++-- .../tests/fixtures/downstream_isa_fixture.h | 3 + .../tests/isa_target_registry_test.cpp | 1 + .../tests/patch/spill_manager_test.cpp | 2 + .../tools/rj_dbt_translate_smoke_test.cpp | 133 + emulation/rocjitsu/tools/dbt_translate.cpp | 20 +- emulation/rocjitsu/tools/dbt_translate.h | 6 + .../rocjitsu/tools/dbt_translate_cli.cpp | 19 + 61 files changed, 4976 insertions(+), 495 deletions(-) diff --git a/.github/workflows/rocjitsu-corpus-tests.yml b/.github/workflows/rocjitsu-corpus-tests.yml index 7c90b39816c4..d477508ab69b 100644 --- a/.github/workflows/rocjitsu-corpus-tests.yml +++ b/.github/workflows/rocjitsu-corpus-tests.yml @@ -442,7 +442,7 @@ jobs: DBT_TRANSLATOR="${DBT_TRANSLATOR_BINARY}" if [[ "${{ matrix.verify_dbt_idempotence }}" == "1" ]]; then DBT_TRANSLATOR="${RUNNER_TEMP}/rj_dbt_translate-verify-idempotence" - printf '#!/usr/bin/env bash\nexec %q --verify-idempotence "$@"\n' \ + printf '#!/usr/bin/env bash\nexec %q --verify-idempotence --verify-rewrite-discharge "$@"\n' \ "${DBT_TRANSLATOR_BINARY}" \ > "${DBT_TRANSLATOR}" chmod +x "${DBT_TRANSLATOR}" diff --git a/emulation/rocjitsu/docs/dbt-design.md b/emulation/rocjitsu/docs/dbt-design.md index c780afdace34..bf094dc0234c 100644 --- a/emulation/rocjitsu/docs/dbt-design.md +++ b/emulation/rocjitsu/docs/dbt-design.md @@ -321,13 +321,24 @@ handwritten semantic EXPAND rule matched? emit replacement sequence virtual-LDS lowering matched? | yes | no v v - emit LDS replacement legalization says EXPAND? + emit LDS replacement registered operand rewrite? | yes | no v v - fail generated - re-encoding + emit replacement legalization says EXPAND? + | yes | no + v v + fail generated + re-encoding ``` +Opcode expansions and registered operand rewrites are selected by one +`RewriteRegistry`. For audited profiles, each registry entry also provides a +read-only residual predicate. When requested, the post-materialization verifier +runs those predicates over the final executable stream and fails if a +registry-owned rewrite remains actionable. This check does not certify +independent pipeline augmentations, such as WMMA completion-wait insertion, +which retain their own ownership and tests. + Control-flow instructions take a related but separate path: DBT emits or reserves a relocation window and records a fixup instead of trusting the source PC-relative value. diff --git a/emulation/rocjitsu/docs/isa-target-providers.md b/emulation/rocjitsu/docs/isa-target-providers.md index 76c349e086b3..6cb5cef1b7bc 100644 --- a/emulation/rocjitsu/docs/isa-target-providers.md +++ b/emulation/rocjitsu/docs/isa-target-providers.md @@ -49,6 +49,12 @@ std::unique_ptr create_target_decoder() { } ``` +`VendorIsa::Decoder` must publish a nonzero `kMaxInstructionWords`, measured in +32-bit words, that bounds both every raw-pointer read performed while decoding +and the size of every successfully decoded instruction. Providers that implement +`rocjitsu::Decoder` directly must return the same bound from +`max_instruction_words()`. + Mark the ISA implementation target as a provider. The provider source is compiled with that existing target; CMake records only its declaration header. diff --git a/emulation/rocjitsu/docs/rj_dbt_translate.md b/emulation/rocjitsu/docs/rj_dbt_translate.md index 8ae66e8973e0..5e4670886fef 100644 --- a/emulation/rocjitsu/docs/rj_dbt_translate.md +++ b/emulation/rocjitsu/docs/rj_dbt_translate.md @@ -48,6 +48,10 @@ Options: requests whose input and output architecture families differ. A second-pass failure or byte difference makes the command fail. This option cannot be combined with `--skip-failed-kernels` or `--list-code-objects`. +- `--verify-rewrite-discharge`: scan the final gfx1250 B0-to-A0 output with the + applicability checks owned by its opcode and operand rewrite registry. The + command fails if any registered rewrite remains actionable. This option + cannot be combined with `--skip-failed-kernels` or `--list-code-objects`. - `--list-code-objects`: list extractable code objects and exit. - `--help`: print command-line help. @@ -96,6 +100,92 @@ verification fail. A failure does not by itself mean that the first output is invalid; it means the translation is not a byte-level fixed point. This mode is intended to expose such instability while developing or auditing the translator. +## Rewrite-discharge Verification + +Use `--verify-rewrite-discharge` to check that gfx1250 B0-to-A0 translation +discharged the applicability conditions of its registered opcode and operand +rewrites: + +```sh +rj_dbt_translate input.gfx1250.co \ + --input-target gfx1250 --input-revision b0 \ + --output-target gfx1250 --output-revision a0 \ + --verify-rewrite-discharge --output-mode code-object > output.gfx1250-a0.co +``` + +The verifier decodes the final executable stream after all translation and ELF +materialization have finished. It reconstructs executable entry boundaries and +stream-checks instruction-local applicability predicates without retaining the +complete decoded stream. If a candidate uses predecessor or successor context, +the verifier reconstructs the full CFG and runs every predicate there instead. +It reports any residual site as an error at its final `.text` offset. One profile +registry supplies both opcode-keyed and operand-driven rewrites to lowering and +verification. Every rule in an audited profile must explicitly register either +a residual predicate and its required decode context, or a no-success contract; +a no-success rule that later begins emitting output fails its registry contract +instead of silently escaping verification. + +This is deliberately a registry-level guarantee. It does not certify separate +pipeline augmentations that are not selected through the rewrite registry, such +as WMMA completion-wait insertion; those remain covered by their existing +implementation-specific tests. + +Translation and final verification require every runtime-loaded executable byte +to reside in one `SHF_ALLOC | SHF_EXECINSTR` section named `.text`. Inputs with +another allocated executable section, or with executable bytes only in a +differently named section, fail closed instead of leaving an unaudited stream in +the output object. + +Executable entries use the same preservation contract as translation and ELF +patching: kernel descriptors, relocation-backed function tables, allocated +target-less dynamic zero-addend `R_AMDGPU_ABS32_LO`, `R_AMDGPU_ABS32_HI`, +`R_AMDGPU_ABS64`, and `R_AMDGPU_ABS32` relocations to ordinary text symbols, and +`R_AMDGPU_RELATIVE64` addends into `.text`. The explicit-symbol forms store, +respectively, the low 32 bits, high 32 bits, full 64 bits, or truncated 32 bits +of the relocated symbol value. + +ROCr derives dynamic `STT_OBJECT`, `STT_AMDGPU_HSA_KERNEL`, and `STT_FUNC` +addresses from `st_value`; only `STT_FUNC` is treated here as a +relocation-backed executable entry. ROCr instead resolves `STT_NOTYPE` as an +external agent symbol by name, so a text-defined `STT_NOTYPE` relocation is not +accepted as a local code reference. Global or weak `STT_FUNC` symbols without a +supported runtime reference remain symbol-table metadata rather than independent +execution roots. + +ROCr skips explicit-target/static relocation sections for supported code objects, +so they retain the translator's broader metadata-preservation policy rather than +the dynamic-loader allowlist above. An allocated, zero-addend explicit-target +`RELA` reference to a text `STT_FUNC` creates an executable entry for every +non-`R_AMDGPU_NONE` relocation type. An explicit-target `STT_NOTYPE` reference +also creates an entry for `R_AMDGPU_ABS64`; other ordinary non-section text +symbols require only symbol remapping. Explicit-target `R_AMDGPU_NONE` records +are ignored. + +An `ET_DYN` `SHT_RELA` section is malformed when its nonzero `sh_info` is out of +range or names an `SHT_NULL` section. Translation rejects that section metadata +before inspecting individual relocation records. The later `R_AMDGPU_NONE` and +text-relocation compatibility checks therefore skip malformed sections; the +earlier structural rejection owns the diagnostic. + +Relocation sections explicitly targeting non-allocated sections are likewise +metadata and do not create executable entries. If a runtime-referenced source +entry is emitted at multiple output placements, materialization fails closed: +neither a named symbol nor a relative addend can safely select one kernel-local +clone on behalf of every caller. + +This is an opt-in offline development audit. The implementation lives beside +translation because it needs the final materialized ELF and decoded CFG, while +`rj_dbt_translate` is the enabling consumer. Runtime translation leaves the +check disabled; when explicitly requested, an unavailable profile or failed +scan is reported as an ordinary translation error. + +This check proves only that the current rewrite payloads clear the conditions +recognized by their corresponding applicability checks. It does not establish +that those checks are complete or correct, prove semantic equivalence, or +validate runtime prerequisites. `--verify-idempotence` can be enabled alongside +this option when both the residual-trigger property and byte-level fixed-point +property are desired. + ### Generated Artifact Markers Translated control-flow artifacts use `s_nop` immediates `0x1250` and `0x1251` diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index fbaa203c37c2..699dec4fbca1 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -2511,6 +2511,58 @@ def gen_machine_inst_encodings(self) -> None: ) cpp_file.gen_code() + def _encoding_extension_word_capacity(self, inst_enc: InstEncoding) -> int: + """Return the largest extension storage owned by an encoding.""" + dpp_struct, dpp8_struct = self._vop_dpp_struct_names(inst_enc.enc_name) + owns_dpp_extension = ( + dpp_struct is not None + and self._supports_dpp_for_encoding(inst_enc.enc_name) + ) or dpp8_struct is not None + default_cond = dict(inst_enc.enc_conds).get('default_encoding', 'true') + has_real_default_check = inst_enc.bit_cnt < 64 and default_cond != 'false' + literal32_condition = any( + name.startswith('has_lit') and not name.startswith('has_lit64') + for name, _ in inst_enc.enc_conds + ) + + capacity = int(owns_dpp_extension) + if has_real_default_check and default_cond != 'true': + capacity = max(capacity, 1) + if literal32_condition: + capacity = max(capacity, 1) + if self._literal64_condition_names(inst_enc): + capacity = max(capacity, 2) + if inst_enc.has_implied_literal_ops: + capacity = max(capacity, 1, *inst_enc.implied_literal_ops.values()) + return capacity + + def _max_instruction_word_count(self) -> int: + """Return the maximum encoded width and lookahead for this generated decoder.""" + maximum = 1 + for inst_enc in self.isa_spec.inst_encodings: + if not inst_enc.insts: + continue + base_words = (inst_enc.bit_cnt + 31) // 32 + maximum = max( + maximum, + base_words + self._encoding_extension_word_capacity(inst_enc), + ) + + for size_bytes in self.isa_spec.profile.inst_size_overrides.values(): + maximum = max(maximum, (size_bytes + 3) // 4) + + # Bespoke generated decoders do not necessarily have a matching XML + # encoding object. VOPD can own one literal DWORD, while VOP3PX2 forms + # are a two-DWORD prefix followed by a two-DWORD instruction. + if self._supports_generated_vopd(): + maximum = max(maximum, 3) + if ( + self._supports_gfx1250_scaled_wmma_vop3px2() + or self._supports_cdna_mfma_f8f6f4_vop3px2() + ): + maximum = max(maximum, 4) + return maximum + def gen_encodings(self) -> None: """Generate encoding classes wrapping raw encoding types.""" enc_classes = [] @@ -2744,21 +2796,7 @@ def gen_encodings(self) -> None: # not the architecture-wide operand selector table. For example, # gfx1250 defines selector 254 for 64-bit literals, but the 64-bit # VOP3 and VOP3P encodings only support a 32-bit literal extension. - extension_word_capacity = 0 - if owns_dpp_extension: - extension_word_capacity = 1 - if has_real_default_check and default_cond != 'true': - extension_word_capacity = max(extension_word_capacity, 1) - if literal32_condition: - extension_word_capacity = max(extension_word_capacity, 1) - if literal64_condition: - extension_word_capacity = max(extension_word_capacity, 2) - if inst_enc.has_implied_literal_ops: - extension_word_capacity = max( - extension_word_capacity, - 1, - *inst_enc.implied_literal_ops.values(), - ) + extension_word_capacity = self._encoding_extension_word_capacity(inst_enc) owns_extension_words = extension_word_capacity > 0 extension_size_line = '' if literal64_condition and size_condition is not None: @@ -12152,6 +12190,9 @@ def gen_decoder(self) -> None: 'Decoder', [ cgen.Line('public:'), + cgen.Statement( + f'static constexpr std::size_t kMaxInstructionWords = {self._max_instruction_word_count()}' + ), cgen.FunctionDeclaration( cgen.Value('static std::unique_ptr', 'decode'), [cgen.Value('const MachineInst *', 'opcode')], @@ -12550,6 +12591,8 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: ), False, ), + ('array', True), + ('cstddef', True), ('memory', True), ], ['Instruction'], diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index d0897df78914..392002bbb62d 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -3373,6 +3373,131 @@ def test_gfx1250_helper_blocks_emit_scaled_wmma_table_decoder( assert 'if (!isVop3pOp(opcode[2], 0x33)' in decoder +def test_generated_decoders_publish_instruction_lookahead_bounds( + amdgpu_generated_root: Path, +) -> None: + expected_bounds = { + 'cdna1': 4, + 'cdna2': 4, + 'cdna3': 4, + 'cdna4': 4, + 'cdna5': 4, + 'rdna1': 3, + 'rdna2': 3, + 'rdna3': 3, + 'rdna3_5': 3, + 'rdna4': 3, + } + emitted_bounds = {} + for decoder_path in amdgpu_generated_root.glob('*/decoder.h'): + match = re.search(r'kMaxInstructionWords\s*=\s*(\d+)', decoder_path.read_text()) + assert match is not None, decoder_path + emitted_bounds[decoder_path.parent.name] = int(match.group(1)) + + assert emitted_bounds == expected_bounds + + +@pytest.mark.parametrize( + ('arch_name', 'profile_type', 'expected_bound'), + [ + ('cdna1', Cdna1Profile, 4), + ('cdna2', Cdna2Profile, 4), + ('cdna3', CdnaProfile, 4), + ('cdna4', CdnaProfile, 4), + ('gfx1250', Gfx1250Profile, 4), + ('rdna1', Rdna1Profile, 3), + ('rdna2', Rdna2Profile, 3), + ('rdna3', Rdna3Profile, 3), + ('rdna3_5', Rdna3_5Profile, 3), + ('rdna4', Rdna4Profile, 3), + ], +) +def test_instruction_lookahead_bound_is_derived_from_isa( + arch_name: str, profile_type, expected_bound: int +) -> None: + isa_xml = _mrisa_dir() / f'amdgpu_isa_{arch_name}.xml' + if not isa_xml.is_file(): + pytest.skip(f'{arch_name} semantics XML not available') + spec = Parser(str(isa_xml), profile_type()).parse() + generator = CodeGenerator(spec, '', derive_all_semantics(spec)) + assert generator._max_instruction_word_count() == expected_bound + + +def test_instruction_lookahead_derivation_covers_each_width_source() -> None: + def generator_for( + *, + bit_count: int = 32, + conditions=(), + implied_words=(), + size_overrides=None, + has_vopd: bool = False, + arch_name: str = 'synthetic', + scaled_wmma: bool = False, + owns_dpp_extension: bool = False, + ) -> CodeGenerator: + instruction = SimpleNamespace( + name='SYNTHETIC', + enc_name='SYNTHETIC_INST', + is_implied_literal_enc=False, + ) + implied = dict(implied_words) + encoding = SimpleNamespace( + enc_name='SYNTHETIC_ENC', + bit_cnt=bit_count, + insts=[instruction], + enc_conds=list(conditions), + has_implied_literal_ops=bool(implied), + implied_literal_ops=implied, + ) + profile = SimpleNamespace( + inst_size_overrides=size_overrides or {}, + has_vopd=has_vopd, + generate_scaled_wmma_vop3px2=scaled_wmma, + ) + generator = object.__new__(CodeGenerator) + generator.isa_spec = SimpleNamespace( + arch_name=arch_name, + profile=profile, + inst_encodings=[encoding], + ) + generator._vop_dpp_struct_names = lambda _name: ( + ('SyntheticDppMachineInst', None) if owns_dpp_extension else (None, None) + ) + return generator + + assert generator_for(bit_count=96)._max_instruction_word_count() == 3 + assert generator_for(owns_dpp_extension=True)._max_instruction_word_count() == 2 + assert ( + generator_for( + conditions=(('default_encoding', 'inst.op == 0'),) + )._max_instruction_word_count() + == 2 + ) + assert ( + generator_for( + conditions=(('has_literal', 'inst.src0 == 255'),) + )._max_instruction_word_count() + == 2 + ) + assert ( + generator_for(conditions=(('has_lit64', 'true'),))._max_instruction_word_count() + == 3 + ) + assert generator_for(implied_words=((1, 3),))._max_instruction_word_count() == 4 + assert ( + generator_for(size_overrides={'SYNTHETIC': 20})._max_instruction_word_count() + == 5 + ) + assert generator_for(has_vopd=True)._max_instruction_word_count() == 3 + assert generator_for(arch_name='cdna4')._max_instruction_word_count() == 4 + assert ( + generator_for( + arch_name='gfx1250', scaled_wmma=True + )._max_instruction_word_count() + == 4 + ) + + @pytest.mark.parametrize( ('arch_name', 'expected_vopd_indices'), [ diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp index a2f907fbabbf..8145c0f2e7be 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp @@ -1427,7 +1427,6 @@ explicit_external_entries(const std::vector &blocks, std::vector entries(blocks.size(), 0); if (!entries.empty()) entries[0] = 1; - // Analysis blocks are built from the ordered instruction stream. Both input // sequences are therefore ascending and can be matched in one merge pass. assert(std::ranges::is_sorted(blocks, {}, &AnalysisBlock::offset)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.cpp index 141daaf77a68..a6411976f20c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.cpp @@ -40,17 +40,20 @@ class HsaHeader : public Header { class HsaSection : public Section { public: - HsaSection(std::string name, std::unique_ptr data, const Elf64_Shdr &shdr) - : Section(std::move(name), std::move(data)), shdr_(shdr) {} + HsaSection(std::string name, std::unique_ptr data, const Elf64_Shdr &shdr, + size_t section_index) + : Section(std::move(name), std::move(data)), shdr_(shdr), section_index_(section_index) {} std::size_t size() const override { return shdr_.sh_size; } uint64_t flags() const override { return shdr_.sh_flags; } uint64_t vaddr() const override { return shdr_.sh_addr; } uint32_t sectionHeaderNameIdx() const override { return shdr_.sh_name; } + std::optional sectionHeaderIndex() const override { return section_index_; } uint64_t sectionOffset() const override { return shdr_.sh_offset; } private: Elf64_Shdr shdr_; + size_t section_index_; }; bool is_elf(const Elf64_Ehdr &ehdr) { return !std::memcmp(ehdr.e_ident, EI_MAGIC, EI_MAGIC_SIZE); } @@ -79,6 +82,8 @@ AmdGpuCodeObject::AmdGpuCodeObject(AmdGpuCodeObject &&other) noexcept header_ = std::move(other.header_); sections_ = std::move(other.sections_); text_sections_ = std::move(other.text_sections_); + executable_nobits_sections_ = std::move(other.executable_nobits_sections_); + allocated_executable_sections_ = std::move(other.allocated_executable_sections_); rodata_sections_ = std::move(other.rodata_sections_); } @@ -190,12 +195,23 @@ void AmdGpuCodeObject::load_sections() { } const char *shstrtab_data = image_.data() + shstrtab.sh_offset; - for (const auto &shdr : section_hdrs) { - if (shdr.sh_type == SHT_NULL || shdr.sh_type == SHT_NOBITS) + for (size_t section_index = 0; section_index < section_hdrs.size(); ++section_index) { + const Elf64_Shdr &shdr = section_hdrs[section_index]; + if (shdr.sh_type == SHT_NULL) continue; - if (shdr.sh_name >= shstrtab.sh_size) + const bool allocated_executable = + (shdr.sh_flags & (SHF_ALLOC | SHF_EXECINSTR)) == (SHF_ALLOC | SHF_EXECINSTR); + if (shdr.sh_type == SHT_NOBITS && !allocated_executable) continue; - if (!fits_in_bounds(shdr.sh_offset, shdr.sh_size, image_.size())) { + if (shdr.sh_name >= shstrtab.sh_size) { + if (allocated_executable) { + is_valid_ = false; + return; + } + continue; + } + if (shdr.sh_type != SHT_NOBITS && + !fits_in_bounds(shdr.sh_offset, shdr.sh_size, image_.size())) { is_valid_ = false; return; } @@ -204,10 +220,26 @@ void AmdGpuCodeObject::load_sections() { std::string sec_name(shstrtab_data + shdr.sh_name, strnlen(shstrtab_data + shdr.sh_name, max_len)); - auto sec_data = std::make_unique(shdr.sh_size); - std::memcpy(sec_data.get(), image_.data() + shdr.sh_offset, shdr.sh_size); - sections_.emplace_back(std::make_unique(sec_name, std::move(sec_data), shdr)); + std::unique_ptr sec_data; + if (shdr.sh_type != SHT_NOBITS) { + sec_data = std::make_unique(shdr.sh_size); + std::memcpy(sec_data.get(), image_.data() + shdr.sh_offset, shdr.sh_size); + } + // SHT_NOBITS has no executable bytes to decode. Retain allocated executable + // metadata above so the translator's sole-PROGBITS-.text gate rejects the + // layout, but keep all_sections() restricted to readable section data. + if (shdr.sh_type == SHT_NOBITS) { + executable_nobits_sections_.emplace_back( + std::make_unique(sec_name, nullptr, shdr, section_index)); + allocated_executable_sections_.push_back(executable_nobits_sections_.back().get()); + continue; + } + + sections_.emplace_back( + std::make_unique(sec_name, std::move(sec_data), shdr, section_index)); + if (allocated_executable) + allocated_executable_sections_.push_back(sections_.back().get()); if (sec_name == ".text") text_sections_.push_back(sections_.back().get()); else if (sec_name == ".rodata") diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.h index 11f05c6bca82..22182cc26461 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_code_object.h @@ -90,6 +90,9 @@ class AmdGpuCodeObject : public CodeObject { private: void load_sections(); + /// Section-header metadata for executable SHT_NOBITS ranges. These are not + /// materialized in all_sections(), whose entries always own readable bytes. + std::vector> executable_nobits_sections_; rj_code_target_id_t target_id_ = ROCJITSU_CODE_TARGET_INVALID; std::string offload_kind_; std::string target_triple_; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h index 1b9ce53d0bba..9cca6213ea3c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h @@ -7,6 +7,7 @@ #include "rocjitsu/code/rj_code.h" #include +#include namespace rocjitsu { @@ -175,21 +176,26 @@ inline constexpr uint32_t SHT_NOBITS = 8; // ELF spec: section occupies no file inline constexpr uint32_t SHT_REL = 9; inline constexpr uint32_t SHT_DYNSYM = 11; -// AMDGPU ELF relocation types used by linked code-object function tables. -// Keep the numeric values local to the ELF layer so DBT does not depend on -// LLVM's ELF headers merely to inspect loader relocations. +// AMDGPU ELF relocation types used by linked code objects. Keep the numeric +// values local to the ELF layer so DBT does not depend on LLVM's ELF headers +// merely to inspect loader relocations. +inline constexpr uint32_t R_AMDGPU_NONE = 0; +inline constexpr uint32_t R_AMDGPU_ABS32_LO = 1; +inline constexpr uint32_t R_AMDGPU_ABS32_HI = 2; inline constexpr uint32_t R_AMDGPU_ABS64 = 3; +inline constexpr uint32_t R_AMDGPU_ABS32 = 6; inline constexpr uint32_t R_AMDGPU_RELATIVE64 = 13; inline constexpr uint8_t kElfSymbolBindLocal = 0; inline constexpr uint8_t kElfSymbolBindGlobal = 1; inline constexpr uint8_t kElfSymbolBindWeak = 2; -inline constexpr uint8_t kElfSymbolVisibilityHidden = 2; // STV_HIDDEN -inline constexpr uint8_t kElfSymbolVisibilityInternal = 1; // STV_INTERNAL -inline constexpr uint8_t kElfSymbolTypeNone = 0; // STT_NOTYPE -inline constexpr uint8_t kElfSymbolTypeObject = 1; // STT_OBJECT -inline constexpr uint8_t kElfSymbolTypeFunc = 2; // STT_FUNC -inline constexpr uint8_t kElfSymbolTypeSection = 3; // STT_SECTION +inline constexpr uint8_t kElfSymbolVisibilityHidden = 2; // STV_HIDDEN +inline constexpr uint8_t kElfSymbolVisibilityInternal = 1; // STV_INTERNAL +inline constexpr uint8_t kElfSymbolTypeNone = 0; // STT_NOTYPE +inline constexpr uint8_t kElfSymbolTypeObject = 1; // STT_OBJECT +inline constexpr uint8_t kElfSymbolTypeFunc = 2; // STT_FUNC +inline constexpr uint8_t kElfSymbolTypeSection = 3; // STT_SECTION +inline constexpr uint8_t kElfSymbolTypeAmdGpuHsaKernel = 10; // STT_AMDGPU_HSA_KERNEL inline constexpr uint8_t elf_symbol_bind(uint8_t info) { return info >> 4; } inline constexpr uint8_t elf_symbol_type(uint8_t info) { return info & 0xf; } @@ -220,6 +226,11 @@ inline constexpr uint32_t elf_reloc_type(uint64_t info) { return static_cast(info & 0xffffffffu); } +/// @brief Whether an AMDGPU ELF relocation record has no effect. +inline constexpr bool elf_relocation_is_inert(uint64_t info) { + return elf_reloc_type(info) == R_AMDGPU_NONE; +} + // R_AMDGPU_RELATIVE64 uses symbol index 0 and forms its value from the load bias // plus r_addend, so its addend can name an in-.text virtual address with no // owning symbol. @@ -340,6 +351,167 @@ struct Elf64_Rela { int64_t r_addend; }; +/// @brief Whether ROCr's dynamic loader forms this relocation from a symbol value. +inline constexpr bool rocr_dynamic_relocation_uses_symbol_value(uint32_t relocation_type) { + switch (relocation_type) { + case R_AMDGPU_ABS32_LO: + case R_AMDGPU_ABS32_HI: + case R_AMDGPU_ABS64: + case R_AMDGPU_ABS32: + return true; + default: + return false; + } +} + +/// @brief Whether ROCr derives this dynamic symbol's runtime address from st_value. +inline constexpr bool rocr_dynamic_symbol_address_follows_st_value(uint8_t symbol_type) { + switch (symbol_type) { + case kElfSymbolTypeObject: + case kElfSymbolTypeFunc: + case kElfSymbolTypeAmdGpuHsaKernel: + return true; + default: + return false; + } +} + +/// @brief Whether this symbol type can introduce a relocation-backed code entry. +inline constexpr bool elf_symbol_is_executable_entry(uint8_t symbol_type) { + return symbol_type == kElfSymbolTypeFunc; +} + +/// @brief How ROCr dispatches one relocation section in a modern code object. +enum class RocrRelocationSectionMode : uint8_t { + NotApplicable, + Dynamic, + ExplicitTarget, + Malformed, +}; + +/// @brief Classify the relocation section using ROCr's targetSection() decision. +/// +/// @details ROCr materializes SHT_RELA sections, resolves sh_info to a section pointer, and uses +/// dynamic relocation processing when that pointer is null. Only section zero safely represents +/// that null target: ROCr skips index zero during its later section passes, but dereferences every +/// nonzero section entry before relocation dispatch. A valid non-null section selects the +/// explicit/static path; a nonzero SHT_NULL entry or out-of-range index is malformed. Other ELF +/// and relocation-section forms retain their existing non-ROCr handling. +inline constexpr RocrRelocationSectionMode +classify_rocr_relocation_section(const Elf64_Ehdr &ehdr, std::span shdrs, + const Elf64_Shdr &relocs) { + if (ehdr.e_type != ET_DYN || relocs.sh_type != SHT_RELA) + return RocrRelocationSectionMode::NotApplicable; + if (relocs.sh_info == SHN_UNDEF) + return RocrRelocationSectionMode::Dynamic; + if (relocs.sh_info >= shdrs.size() || shdrs[relocs.sh_info].sh_type == SHT_NULL) + return RocrRelocationSectionMode::Malformed; + return RocrRelocationSectionMode::ExplicitTarget; +} + +/// @brief ROCr's handling of an R_AMDGPU_NONE record before place or symbol lookup. +enum class RocrNoneRelocationAction : uint8_t { + NotNone, + Ignored, + Rejected, +}; + +/// @brief Classify R_AMDGPU_NONE from the shared ROCr relocation-section mode. +inline constexpr RocrNoneRelocationAction +classify_rocr_none_relocation(RocrRelocationSectionMode mode, uint64_t relocation_info) { + if (elf_reloc_type(relocation_info) != R_AMDGPU_NONE) + return RocrNoneRelocationAction::NotNone; + if (mode == RocrRelocationSectionMode::Dynamic || mode == RocrRelocationSectionMode::Malformed) { + return RocrNoneRelocationAction::Rejected; + } + return RocrNoneRelocationAction::Ignored; +} + +/// @brief How a relocation reference to an ordinary symbol in rewritten .text must be handled. +enum class TextSymbolRelocationAction : uint8_t { + Ignored, + RequiresSymbolMapping, + RequiresExecutableEntry, + Unsupported, +}; + +/// @brief Classify one relocation reference to a symbol defined in rewritten .text. +/// +/// @details A required executable entry also requires the symbol's st_value to be remapped. +/// ROCr rejects R_AMDGPU_NONE in target-less dynamic relocation sections, but skips +/// explicit-target/static relocation sections for supported code objects. Other ROCr dynamic +/// relocations follow the loader's supported symbol-valued forms, while explicit-target/static +/// sections retain the broader pre-existing policy that any ordinary zero-addend RELA reference +/// follows the symbol value. +inline constexpr TextSymbolRelocationAction +classify_text_symbol_relocation(RocrRelocationSectionMode mode, uint64_t relocation_info, + bool has_explicit_addend, int64_t addend, const Elf64_Sym &symbol) { + const uint32_t relocation_type = elf_reloc_type(relocation_info); + if (mode == RocrRelocationSectionMode::Malformed) + return TextSymbolRelocationAction::Unsupported; + const bool rocr_dynamic = mode == RocrRelocationSectionMode::Dynamic; + if (relocation_type == R_AMDGPU_NONE) { + return rocr_dynamic ? TextSymbolRelocationAction::Unsupported + : TextSymbolRelocationAction::Ignored; + } + if (!has_explicit_addend || addend != 0 || elf_reloc_sym(relocation_info) == 0) + return TextSymbolRelocationAction::Unsupported; + + const uint8_t symbol_type = elf_symbol_type(symbol.st_info); + if (rocr_dynamic) { + if (relocation_type == R_AMDGPU_RELATIVE64) { + return symbol_type == kElfSymbolTypeSection + ? TextSymbolRelocationAction::Unsupported + : TextSymbolRelocationAction::RequiresSymbolMapping; + } + if (!rocr_dynamic_relocation_uses_symbol_value(relocation_type) || + !rocr_dynamic_symbol_address_follows_st_value(symbol_type)) { + return TextSymbolRelocationAction::Unsupported; + } + return elf_symbol_is_executable_entry(symbol_type) + ? TextSymbolRelocationAction::RequiresExecutableEntry + : TextSymbolRelocationAction::RequiresSymbolMapping; + } + + if (symbol_type == kElfSymbolTypeSection) + return TextSymbolRelocationAction::Unsupported; + if (elf_symbol_is_executable_entry(symbol_type) || + (symbol_type == kElfSymbolTypeNone && relocation_type == R_AMDGPU_ABS64)) { + return TextSymbolRelocationAction::RequiresExecutableEntry; + } + return TextSymbolRelocationAction::RequiresSymbolMapping; +} + +/// @brief Return whether a relocation record applies to storage loaded at runtime. +/// +/// Relocation sections with an explicit sh_info target inherit that section's allocation +/// state. Generic ET_DYN relocation sections use SHN_UNDEF and identify their target storage +/// through each record's virtual r_offset instead. Keeping this ABI rule here prevents entry +/// discovery and final ELF patching from disagreeing about debug-only relocation metadata. +[[nodiscard]] inline bool elf_relocation_place_is_allocated(const Elf64_Ehdr &ehdr, + std::span shdrs, + const Elf64_Shdr &relocs, + uint64_t relocation_offset) { + const RocrRelocationSectionMode mode = classify_rocr_relocation_section(ehdr, shdrs, relocs); + if (mode == RocrRelocationSectionMode::Malformed) + return false; + if (mode == RocrRelocationSectionMode::ExplicitTarget) { + return (shdrs[relocs.sh_info].sh_flags & SHF_ALLOC) != 0; + } + if (mode == RocrRelocationSectionMode::NotApplicable && relocs.sh_info != SHN_UNDEF) { + return relocs.sh_info < shdrs.size() && (shdrs[relocs.sh_info].sh_flags & SHF_ALLOC) != 0; + } + if (mode == RocrRelocationSectionMode::NotApplicable && ehdr.e_type != ET_DYN) + return false; + for (const Elf64_Shdr §ion : shdrs) { + if ((section.sh_flags & SHF_ALLOC) != 0 && relocation_offset >= section.sh_addr && + relocation_offset - section.sh_addr < section.sh_size) { + return true; + } + } + return false; +} + } // namespace rocjitsu #endif // ROCJITSU_CODE_AMDGPU_ELF_H_ diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/code_object.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/code_object.h index 9ed14a8620bb..2aae0f84386a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/code_object.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/code_object.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -79,6 +80,10 @@ class Section { /// @returns String table index. virtual uint32_t sectionHeaderNameIdx() const = 0; + /// @brief Index of this section in its owning ELF section-header table. + /// @returns Section index when the section is backed by ELF metadata. + virtual std::optional sectionHeaderIndex() const { return std::nullopt; } + /// @brief File offset of this section in the ELF image. /// @returns Byte offset from the start of the file. virtual uint64_t sectionOffset() const = 0; @@ -106,6 +111,13 @@ class CodeObject { /// @returns Vector of pointers to .text sections. const std::vector &text_sections() const { return text_sections_; } + /// @brief Runtime-loaded ranges declared executable by ELF metadata. + /// @returns Sections carrying both SHF_ALLOC and SHF_EXECINSTR, including + /// unmaterialized SHT_NOBITS ranges used for layout validation. + const std::vector &allocated_executable_sections() const { + return allocated_executable_sections_; + } + /// @brief .rodata sections containing read-only data. /// @returns Vector of pointers to .rodata sections. const std::vector &rodata_sections() const { return rodata_sections_; } @@ -189,6 +201,7 @@ class CodeObject { std::unique_ptr
header_; std::vector> sections_; std::vector text_sections_; + std::vector allocated_executable_sections_; std::vector rodata_sections_; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp index 8b1c3a762507..0d549a628cf9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp @@ -23,7 +23,6 @@ #include "rocjitsu/code/dbt/lds_virtualization.h" #include "rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.h" #include "rocjitsu/code/dbt/scoped_cfg_edges.h" -#include "rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.h" #include "rocjitsu/code/dbt/semantic_translator.h" #include "rocjitsu/code/dbt/virtual_lds.h" #include "rocjitsu/code/patch/code_object_patcher.h" @@ -39,7 +38,6 @@ #include "util/except.h" #include -#include #include #include #include @@ -389,6 +387,7 @@ void append_diagnostic(std::vector &diagnostics, Diagnost diagnostics.push_back({.severity = severity, .kind = kind, .guest_offset = guest_offset, + .output_offset = std::nullopt, .mnemonic = std::move(mnemonic), .message = std::move(message), .required_work = std::move(required_work)}); @@ -408,6 +407,19 @@ void append_warning(std::vector &diagnostics, DiagnosticK guest_offset, std::move(mnemonic), std::move(required_work)); } +void append_rewrite_discharge_error(std::vector &diagnostics, + std::string message, + std::optional output_offset = std::nullopt, + std::string mnemonic = {}) { + diagnostics.push_back({.severity = DiagnosticSeverity::Error, + .kind = DiagnosticKind::ResidualRewrite, + .guest_offset = std::nullopt, + .output_offset = output_offset, + .mnemonic = std::move(mnemonic), + .message = std::move(message), + .required_work = {}}); +} + void append_diagnostics(std::vector &dst, const std::vector &src) { dst.insert(dst.end(), src.begin(), src.end()); @@ -438,6 +450,7 @@ translation_refusal(const CodeObjectPatcher &patcher, rj_code_arch_t guest_arch, return TranslationDiagnostic{.severity = DiagnosticSeverity::Error, .kind = kind, .guest_offset = std::nullopt, + .output_offset = std::nullopt, .mnemonic = {}, .message = std::move(message), .required_work = {}}; @@ -471,6 +484,7 @@ translation_refusal(const CodeObjectPatcher &patcher, rj_code_arch_t guest_arch, .severity = DiagnosticSeverity::Warning, .kind = DiagnosticKind::DataOnly, .guest_offset = std::nullopt, + .output_offset = std::nullopt, .mnemonic = {}, .message = "code object has no executable sections, segments, or callable symbols; " "leaving unchanged", @@ -583,6 +597,169 @@ kernel_hardware_entry_offsets(std::span kernels) { return offsets; } +[[nodiscard]] bool elf_image_contains(std::span image, uint64_t offset, + uint64_t size) { + const uint64_t image_size = image.size(); + return offset <= image_size && size <= image_size - offset; +} + +/// @brief Collect relocation-backed entries within one executable section. +/// +/// @details Kernel descriptors and relocation-backed function tables are +/// collected by their owning subsystems. This helper adds ordinary text symbols +/// demonstrably consumed through an allocated relocation and anonymous +/// R_AMDGPU_RELATIVE64 addends into .text. Symbol visibility alone is not an +/// executable-entry contract: ROCr does not promote an ordinary STT_FUNC merely +/// because it is visible and resolves STT_NOTYPE externally rather than from its +/// text st_value. The patcher intentionally does not require unreferenced +/// tooling/debug symbols to have output mappings. Keeping those symbols out of +/// this set makes reachability, relocation, and final verification agree on +/// which entries DBT preserves. +[[nodiscard]] std::optional> +text_relocation_block_leaders(std::span image, const Section &text) { + if (!elf_image_contains(image, 0, sizeof(Elf64_Ehdr))) + return std::nullopt; + + Elf64_Ehdr ehdr{}; + std::memcpy(&ehdr, image.data(), sizeof(ehdr)); + if (ehdr.e_shentsize != sizeof(Elf64_Shdr) || + !elf_image_contains(image, ehdr.e_shoff, + static_cast(ehdr.e_shnum) * sizeof(Elf64_Shdr))) { + return std::nullopt; + } + + std::vector shdrs(ehdr.e_shnum); + if (!shdrs.empty()) + std::memcpy(shdrs.data(), image.data() + ehdr.e_shoff, shdrs.size() * sizeof(Elf64_Shdr)); + + const auto text_index = text.sectionHeaderIndex(); + if (!text_index || *text_index >= shdrs.size()) + return std::nullopt; + const Elf64_Shdr &text_header = shdrs[*text_index]; + if (text_header.sh_type == SHT_NOBITS || text_header.sh_name != text.sectionHeaderNameIdx() || + text_header.sh_flags != text.flags() || text_header.sh_addr != text.vaddr() || + text_header.sh_offset != text.sectionOffset() || text_header.sh_size != text.size()) { + return std::nullopt; + } + + std::vector leaders; + + for (size_t relocation_section_index = 0; relocation_section_index < shdrs.size(); + ++relocation_section_index) { + const Elf64_Shdr &relocs = shdrs[relocation_section_index]; + if (relocs.sh_type != SHT_RELA) + continue; + const RocrRelocationSectionMode section_mode = + classify_rocr_relocation_section(ehdr, shdrs, relocs); + if (section_mode == RocrRelocationSectionMode::Malformed) + return std::nullopt; + if (section_mode != RocrRelocationSectionMode::Dynamic && relocs.sh_info != SHN_UNDEF) { + if (relocs.sh_info >= shdrs.size()) + return std::nullopt; + if ((shdrs[relocs.sh_info].sh_flags & SHF_ALLOC) == 0) { + continue; + } + } + if (relocs.sh_entsize != sizeof(Elf64_Rela) || relocs.sh_size % sizeof(Elf64_Rela) != 0 || + !elf_image_contains(image, relocs.sh_offset, relocs.sh_size)) { + return std::nullopt; + } + + const size_t count = relocs.sh_size / sizeof(Elf64_Rela); + for (size_t relocation_index = 0; relocation_index < count; ++relocation_index) { + Elf64_Rela relocation{}; + std::memcpy(&relocation, + image.data() + relocs.sh_offset + relocation_index * sizeof(Elf64_Rela), + sizeof(relocation)); + const uint32_t relocation_type = elf_reloc_type(relocation.r_info); + const uint32_t symbol_index = elf_reloc_sym(relocation.r_info); + const RocrNoneRelocationAction none_action = + classify_rocr_none_relocation(section_mode, relocation.r_info); + if (none_action == RocrNoneRelocationAction::Rejected) + return std::nullopt; + if (none_action == RocrNoneRelocationAction::Ignored) + continue; + if (!elf_relocation_place_is_allocated(ehdr, shdrs, relocs, relocation.r_offset)) + continue; + + const bool rocr_dynamic = section_mode == RocrRelocationSectionMode::Dynamic; + const bool may_require_text_symbol_classification = + symbol_index != 0 && + (!rocr_dynamic || rocr_dynamic_relocation_uses_symbol_value(relocation_type)); + if (may_require_text_symbol_classification) { + if (relocs.sh_link >= shdrs.size()) + return std::nullopt; + const Elf64_Shdr &symtab = shdrs[relocs.sh_link]; + if ((symtab.sh_type != SHT_SYMTAB && symtab.sh_type != SHT_DYNSYM) || + symtab.sh_entsize != sizeof(Elf64_Sym) || symtab.sh_size % sizeof(Elf64_Sym) != 0 || + !elf_image_contains(image, symtab.sh_offset, symtab.sh_size)) { + return std::nullopt; + } + const size_t symbol_count = symtab.sh_size / sizeof(Elf64_Sym); + if (symbol_index >= symbol_count) + return std::nullopt; + + Elf64_Sym symbol{}; + std::memcpy(&symbol, image.data() + symtab.sh_offset + symbol_index * sizeof(Elf64_Sym), + sizeof(symbol)); + if (symbol.st_shndx == *text_index && + classify_text_symbol_relocation(section_mode, relocation.r_info, + /*has_explicit_addend=*/true, relocation.r_addend, + symbol) == + TextSymbolRelocationAction::RequiresExecutableEntry) { + uint64_t offset = symbol.st_value; + if (ehdr.e_type != ET_REL) { + if (symbol.st_value < text.vaddr()) + return std::nullopt; + offset = symbol.st_value - text.vaddr(); + } + if (offset > text.size()) + return std::nullopt; + if (offset < text.size()) + leaders.push_back(offset); + } + } + + if (ehdr.e_type != ET_DYN || relocation_type != R_AMDGPU_RELATIVE64 || + relocation.r_addend < 0) { + continue; + } + const uint64_t target = static_cast(relocation.r_addend); + if (target < text.vaddr()) + continue; + const uint64_t offset = target - text.vaddr(); + if (offset < text.size()) + leaders.push_back(offset); + } + } + + std::ranges::sort(leaders); + leaders.erase(std::ranges::unique(leaders).begin(), leaders.end()); + return leaders; +} + +[[nodiscard]] bool has_invalid_block_leader(const std::vector> &blocks, + std::span block_leaders, + uint64_t text_size) { + std::unordered_set decoded_block_starts; + decoded_block_starts.reserve(blocks.size()); + for (const auto &block : blocks) { + if (block != nullptr) + decoded_block_starts.insert(block->start_offset()); + } + return std::ranges::any_of(block_leaders, [&](uint64_t leader) { + return leader >= text_size || !decoded_block_starts.contains(leader); + }); +} + +[[nodiscard]] bool has_supported_executable_section_layout(const AmdGpuCodeObject &object) { + const auto &text = object.text_sections(); + const auto &executable = object.allocated_executable_sections(); + if (text.empty() && executable.empty()) + return true; + return text.size() == 1 && executable.size() == 1 && text.front() == executable.front(); +} + struct KernelTranslationScope { KdTranslation *translation = nullptr; BasicBlock *entry = nullptr; @@ -1758,6 +1935,33 @@ struct ScopeTransaction { namespace internal { +RewriteDischargeInstructionDecoder::RewriteDischargeInstructionDecoder(Decoder &decoder) + : decoder_(decoder), lookahead_words_(decoder.max_instruction_words()) {} + +RewriteDischargeDecodeStatus +RewriteDischargeInstructionDecoder::decode(std::span remaining_bytes, + uint64_t source_offset, + std::unique_ptr &instruction) { + instruction.reset(); + if (lookahead_words_.empty()) + return RewriteDischargeDecodeStatus::InvalidLookaheadBound; + + std::ranges::fill(lookahead_words_, 0u); + const size_t remaining_words = remaining_bytes.size() / sizeof(uint32_t); + const size_t copied_words = std::min(remaining_words, lookahead_words_.size()); + std::memcpy(lookahead_words_.data(), remaining_bytes.data(), copied_words * sizeof(uint32_t)); + instruction.reset(decoder_.decode(lookahead_words_.data(), source_offset)); + if (instruction == nullptr || instruction->size() <= 0 || + instruction->size() % static_cast(sizeof(uint32_t)) != 0) { + return RewriteDischargeDecodeStatus::InvalidInstructionSize; + } + + const size_t decoded_words = static_cast(instruction->size()) / sizeof(uint32_t); + if (decoded_words > lookahead_words_.size() || decoded_words > remaining_words) + return RewriteDischargeDecodeStatus::TruncatedInstruction; + return RewriteDischargeDecodeStatus::Success; +} + /// @brief Prove that every external entry into an incomplete-consumer scope is /// an entry-state root that cannot carry an original `.text` pointer. /// @@ -1859,17 +2063,225 @@ BinaryTranslator::lookup_legalization(const Instruction &inst) const { // tables cannot express their revision-specific behavior. Instructions in // the B0-to-A0 profile use handwritten legalization; everything else follows // the raw same-ISA copy path. + const InstructionLegalization *legalization = nullptr; if (is_gfx1250_b0_to_a0()) - return gfx1250_b0_to_a0_legalization(inst); - - return legalization_lookup_ ? legalization_lookup_(inst.encoding_id(), inst.opcode()) : nullptr; + legalization = gfx1250_b0_to_a0_legalization(inst); + else if (legalization_lookup_) + legalization = legalization_lookup_(inst.encoding_id(), inst.opcode()); + return legalization; } void BinaryTranslator::set_trace_callback(TranslationTraceCallback callback) { trace_callback_ = std::move(callback); } +void BinaryTranslator::verify_rewrite_discharge(TranslatedCodeObject &result) const { + result.rewrite_discharge_checked = true; + if (!semantic_translator_->supports_rewrite_discharge()) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification is unavailable for this translation profile"); + return; + } + + try { + AmdGpuCodeObject output(result.elf_bytes.data(), result.elf_bytes.size()); + if (!output.is_valid()) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification could not parse the final code object"); + return; + } + if (!has_supported_executable_section_layout(output)) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification requires exactly one allocated executable section " + "named .text"); + return; + } + if (output.allocated_executable_sections().empty()) { + result.rewrite_discharge_verified = true; + return; + } + + auto decoder = Decoder::create(host_arch_); + if (!decoder) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification has no decoder for the final architecture"); + return; + } + + const Section *text = output.text_sections().front(); + if (text->size() == 0) { + result.rewrite_discharge_verified = true; + return; + } + const auto image = std::span(result.elf_bytes); + const auto text_bytes = + std::span(reinterpret_cast(text->data()), text->size()); + if (text_bytes.size() % sizeof(uint32_t) != 0) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification found a partial instruction word in final output", + text_bytes.size() - text_bytes.size() % sizeof(uint32_t)); + return; + } + + KernelDescriptorTranslator descriptor_parser(host_arch_, host_arch_); + const auto descriptor_translations = descriptor_parser.translate_image( + image, text->sectionOffset(), text->size(), KernelDescriptorTranslationOptions{}, + text->sectionHeaderIndex()); + auto block_leaders = kernel_block_leaders(descriptor_translations, text_bytes); + + for (const RelocationFunctionTable &table : discover_relocation_function_tables(output)) { + for (const RelocationFunctionPointer &entry : table.entries) + block_leaders.push_back(entry.target_text_offset); + } + + const auto relocation_leaders = text_relocation_block_leaders(image, *text); + if (!relocation_leaders) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification could not recover final executable entries"); + return; + } + block_leaders.insert(block_leaders.end(), relocation_leaders->begin(), + relocation_leaders->end()); + std::ranges::sort(block_leaders); + block_leaders.erase(std::ranges::unique(block_leaders).begin(), block_leaders.end()); + + // Most residual predicates inspect only one decoded instruction. Scan those + // with constant live memory and retain the full CFG path only when a rule + // explicitly requires basic-block neighbors. Besides reducing peak RSS, + // delaying CFG construction preserves the existing contextual behavior for + // tensor, cluster-load, and IU8-WMMA sequence checks. + std::vector streaming_diagnostics; + const size_t instruction_word_count = text->size() / sizeof(uint32_t); + internal::RewriteDischargeInstructionDecoder instruction_decoder(*decoder); + if (!instruction_decoder.has_valid_lookahead_bound()) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification decoder reported an invalid lookahead bound"); + return; + } + size_t instruction_word_index = 0; + uint64_t instruction_offset = 0; + size_t next_block_leader = 0; + bool invalid_block_leader = false; + bool needs_basic_block = false; + while (instruction_word_index < instruction_word_count) { + if (next_block_leader < block_leaders.size() && + block_leaders[next_block_leader] < instruction_offset) { + invalid_block_leader = true; + break; + } + + uint32_t first_word = 0; + std::memcpy(&first_word, text_bytes.data() + instruction_offset, sizeof(first_word)); + if (host_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && first_word == 0) { + ++instruction_word_index; + instruction_offset += sizeof(uint32_t); + continue; + } + + if (next_block_leader < block_leaders.size() && + block_leaders[next_block_leader] == instruction_offset) { + ++next_block_leader; + } + + std::unique_ptr inst; + const auto decode_status = instruction_decoder.decode(text_bytes.subspan(instruction_offset), + instruction_offset, inst); + if (decode_status == internal::RewriteDischargeDecodeStatus::InvalidLookaheadBound) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification decoder reported an invalid lookahead bound"); + return; + } + if (decode_status == internal::RewriteDischargeDecodeStatus::InvalidInstructionSize) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification decoded an invalid instruction size in final output", + instruction_offset); + return; + } + const size_t instruction_size = static_cast(inst->size()); + const size_t decoded_words = instruction_size / sizeof(uint32_t); + if (decode_status == internal::RewriteDischargeDecodeStatus::TruncatedInstruction) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification found a truncated instruction in final output", + instruction_offset, std::string(inst->mnemonic())); + return; + } + if (semantic_translator_->residual_rewrite_needs_basic_block(*inst)) + needs_basic_block = true; + if (semantic_translator_->instruction_local_residual_rewrite_applies(*inst)) { + append_rewrite_discharge_error(streaming_diagnostics, + "registered rewrite remains actionable in final output", + inst->src_loc(), std::string(inst->mnemonic())); + } + instruction_word_index += decoded_words; + instruction_offset += instruction_size; + } + + invalid_block_leader |= next_block_leader != block_leaders.size(); + invalid_block_leader |= instruction_offset != text_bytes.size(); + if (invalid_block_leader) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification found an invalid final executable entry"); + return; + } + + if (!needs_basic_block) { + const bool found_residual = !streaming_diagnostics.empty(); + result.diagnostics.insert(result.diagnostics.end(), + std::make_move_iterator(streaming_diagnostics.begin()), + std::make_move_iterator(streaming_diagnostics.end())); + result.rewrite_discharge_verified = !found_residual; + return; + } + + const auto blocks = BasicBlock::build(output, *decoder, host_arch_, block_leaders, + ExternalEntryPolicy::ExplicitOnly); + if (has_invalid_block_leader(blocks, block_leaders, text->size())) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification found an invalid final executable entry"); + return; + } + + bool found_residual = false; + for (const auto &block : blocks) { + for (const Instruction &inst : block->instructions()) { + if (!semantic_translator_->residual_rewrite_applies(inst)) + continue; + found_residual = true; + append_rewrite_discharge_error(result.diagnostics, + "registered rewrite remains actionable in final output", + inst.src_loc(), std::string(inst.mnemonic())); + } + } + + result.rewrite_discharge_verified = !found_residual; + } catch (const std::exception &error) { + append_rewrite_discharge_error( + result.diagnostics, + std::string("rewrite-discharge verification failed to decode final output: ") + + error.what()); + } +} + TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { + TranslatedCodeObject result = translate_impl(obj); + if (options_.verify_rewrite_discharge && result.ok()) + verify_rewrite_discharge(result); + return result; +} + +TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &obj) { TranslatedCodeObject result; result.host_arch = host_arch_; @@ -1884,13 +2296,69 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { return result; }; + if (options_.verify_rewrite_discharge && options_.skip_failed_kernels) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "rewrite-discharge verification cannot be combined with skip-failed-kernels"); + return leave_unchanged(); + } + if (obj.image_size() < sizeof(Elf64_Ehdr)) { append_error(result.diagnostics, DiagnosticKind::ResourceLimit, "code object is too small to contain an ELF header"); return leave_unchanged(); } + if (!obj.is_valid()) { + append_error(result.diagnostics, DiagnosticKind::ResourceLimit, + "translation could not parse input code object"); + return leave_unchanged(); + } + + // A same-architecture gfx1250 translation is direction-specific: A0 and B0 + // share an ELF machine ID, so both revisions must be given. Enforce this here + // as well as in the C API. + if (guest_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && host_arch_ == ROCJITSU_CODE_ARCH_GFX1250) { + if (options_.input_revision == ProcessorRevision::Unspecified || + options_.output_revision == ProcessorRevision::Unspecified) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "gfx1250 same-target translation requires both input and output silicon " + "revisions"); + return leave_unchanged(); + } + // Only the B0-to-A0 direction is implemented. + if (options_.input_revision == ProcessorRevision::Gfx1250A0 && + options_.output_revision == ProcessorRevision::Gfx1250B0) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "gfx1250 A0-to-B0 translation is not supported"); + return leave_unchanged(); + } + } + + if (!has_supported_executable_section_layout(obj)) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "translation requires exactly one allocated executable section named .text"); + return leave_unchanged(); + } CodeObjectPatcher patcher(obj); + + // Reject relocation-section metadata ROCr cannot materialize before examining + // individual records. ROCr then processes target-less SHT_RELA sections as + // dynamic relocations and rejects R_AMDGPU_NONE there; reject that form by + // record identity before place, symbol, executable-entry, or data-only handling. + if (patcher.has_malformed_rocr_relocation_section()) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "code object has malformed ROCr relocation-section metadata; a nonzero " + "SHT_NULL or out-of-range sh_info cannot identify a relocation target"); + return leave_unchanged(); + } + + if (patcher.has_rocr_rejected_none_relocation()) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "code object has R_AMDGPU_NONE outside a valid explicit-target relocation " + "section; ROCr rejects this dynamic relocation form"); + return leave_unchanged(); + } + auto text = patcher.text_bytes(); if (auto refusal = translation_refusal(patcher, guest_arch_, host_arch_, target_mach_, options_)) { @@ -1927,9 +2395,9 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { const bool can_emit_sidecar_descriptors = supports_virtual_lds_sidecars(guest_arch_, host_arch_); KernelDescriptorTranslationOptions initial_descriptor_options; initial_descriptor_options.allow_oversized_lds = can_emit_sidecar_descriptors; - auto descriptor_translations = - descriptor_translator.translate_image(patcher.image_bytes(), patcher.text_offset(), - patcher.text_size(), initial_descriptor_options); + auto descriptor_translations = descriptor_translator.translate_image( + patcher.image_bytes(), patcher.text_offset(), patcher.text_size(), initial_descriptor_options, + obj.text_sections().front()->sectionHeaderIndex()); bool descriptors_supported = true; for (const auto &translation : descriptor_translations) { if (translation.supported || !skip_failed_kernels) @@ -1960,10 +2428,25 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { const auto relocation_function_tables = discover_relocation_function_tables(obj); auto block_leaders = kernel_block_leaders(descriptor_translations, text); + std::vector required_external_entries; for (const RelocationFunctionTable &table : relocation_function_tables) { for (const RelocationFunctionPointer &entry : table.entries) - block_leaders.push_back(entry.target_text_offset); + required_external_entries.push_back(entry.target_text_offset); } + const auto relocation_leaders = + text_relocation_block_leaders(patcher.image_bytes(), *obj.text_sections().front()); + if (!relocation_leaders) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "translation could not recover relocation-backed executable entries"); + return leave_unchanged(); + } + required_external_entries.insert(required_external_entries.end(), relocation_leaders->begin(), + relocation_leaders->end()); + std::ranges::sort(required_external_entries); + required_external_entries.erase(std::ranges::unique(required_external_entries).begin(), + required_external_entries.end()); + block_leaders.insert(block_leaders.end(), required_external_entries.begin(), + required_external_entries.end()); std::ranges::sort(block_leaders); block_leaders.erase(std::ranges::unique(block_leaders).begin(), block_leaders.end()); @@ -2020,6 +2503,11 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { append_error(result.diagnostics, DiagnosticKind::Legalization, error.what()); return leave_unchanged(); } + if (has_invalid_block_leader(blocks, block_leaders, text.size())) { + append_error(result.diagnostics, DiagnosticKind::Legalization, + "translation found an invalid executable entry"); + return leave_unchanged(); + } const BlockOffsetIndex block_index = build_block_offset_index(blocks); const uint64_t text_vaddr = obj.text_sections().front()->vaddr(); const auto relocation_pair_analysis = @@ -2402,6 +2890,30 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { const std::unordered_set adopted_return_offsets = adopted_root_return_offsets(block_index, adopted_roots, text); + // An address consumed by loaded data must survive translation even when no direct branch reaches + // it. Function-table targets may have been adopted into the emitted scopes above; fail before + // lowering only when an entry remains outside every scope. The patcher would also reject its + // missing offset mapping during commit, but enforcing the contract here keeps reachability, + // emission, and verification in agreement and avoids doing a complete translation that cannot + // commit. + if (!required_external_entries.empty()) { + std::unordered_set uncovered_external_entries(required_external_entries.begin(), + required_external_entries.end()); + for (const KernelTranslationScope &scope : scopes) { + for (const BasicBlock *block : scope.blocks) { + if (block != nullptr) + uncovered_external_entries.erase(block->start_offset()); + } + } + if (!uncovered_external_entries.empty()) { + const uint64_t uncovered_entry = *std::ranges::min_element(uncovered_external_entries); + append_error(result.diagnostics, DiagnosticKind::Legalization, + "relocation-backed executable entry is outside every kernel translation scope", + uncovered_entry); + return leave_unchanged(); + } + } + const size_t expected_scope_count = kernel_translation_scope_count(descriptor_translations); if (scopes.size() != expected_scope_count) { append_error(result.diagnostics, DiagnosticKind::KernelDescriptor, @@ -2769,13 +3281,7 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { if (block == nullptr) continue; for (const Instruction &inst : block->instructions()) { - // The gfx1250 flat-scratch-base rewrite is selected by operand rather - // than by (encoding, opcode), so the rule-table query above cannot see - // it. It borrows an SGPR pair for vector reads and therefore carries - // its own live-before requirement. - const bool operand_driven_rewrite = - is_gfx1250_b0_to_a0() && gfx1250_reads_flat_scratch_base_64bit(inst); - if (semantic_translator_->expand_rule_requires_liveness(inst) || operand_driven_rewrite) { + if (semantic_translator_->rewrite_requires_liveness(inst)) { scope_requires_liveness = true; live_before_instructions.push_back(&inst); } @@ -3611,16 +4117,16 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { } } - // Operand-driven gfx1250 rewrites cannot be keyed by (encoding, opcode) - // the way the semantic rule table is, so they run after that lookup - // misses and before the missing-rule failure below. - if (is_gfx1250_b0_to_a0()) { - auto base_expansion = - gfx1250_lower_flat_scratch_base_source(inst, offset, text, liveness, kernel_context); - if (base_expansion.status == ExpandStatus::Failed) { - auto failure = make_kernel_failure(DiagnosticKind::ExpandFailed, base_expansion.message, - offset, std::string(inst.mnemonic()), - std::move(base_expansion.required_work)); + // Non-opcode-keyed rewrites retain their historical position after + // virtual-LDS lowering. Their registry supplies the same applicability + // test to liveness collection and the corresponding final-stream check. + if (semantic_translator_ != nullptr) { + auto registered_expansion = semantic_translator_->try_lower_instruction_rewrite( + inst, offset, text, liveness, kernel_context); + if (registered_expansion.status == ExpandStatus::Failed) { + auto failure = make_kernel_failure( + DiagnosticKind::ExpandFailed, registered_expansion.message, offset, + std::string(inst.mnemonic()), std::move(registered_expansion.required_work)); if (continue_after_failure && !skip_failed_kernels) { append_error(result.diagnostics, failure.kind, failure.message, failure.guest_offset, failure.mnemonic, failure.required_work); @@ -3634,8 +4140,8 @@ TranslatedCodeObject BinaryTranslator::translate(const AmdGpuCodeObject &obj) { } return leave_unchanged(); } - if (base_expansion.status == ExpandStatus::Success) { - std::vector target_words = std::move(base_expansion.words); + if (registered_expansion.status == ExpandStatus::Success) { + std::vector target_words = std::move(registered_expansion.words); append_words(kernel_text, target_words); queue_trace(pending_traces, inst, offset, leg, false, true, true, target_offset, std::move(target_words)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.h index a0300d9e73e4..d8b538a30b1e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.h @@ -133,6 +133,13 @@ struct BinaryTranslatorOptions { /// skipped-kernel warning. The symbol remains loadable so other kernels in the /// same code object are not blocked by one untranslated kernel. bool skip_failed_kernels = false; + + /// @brief Audit registered rewrites that remain actionable in final output. + /// + /// @details The audit is available only for translation profiles with registered semantic or + /// operand-level residual checks. Requesting it for any other profile produces an error + /// diagnostic. Runtime translation does not enable this development check by default. + bool verify_rewrite_discharge = false; }; /// @brief Result of translating a code object. @@ -140,6 +147,8 @@ struct TranslatedCodeObject { std::vector elf_bytes; ///< Translated ELF for the host ISA. rj_code_arch_t host_arch = ROCJITSU_CODE_ARCH_INVALID; ///< Host ISA architecture. std::vector diagnostics; ///< Translation warnings/errors. + bool rewrite_discharge_checked = false; ///< Final output scan was attempted. + bool rewrite_discharge_verified = false; ///< No registered rewrite remained actionable. /// @brief True if translation produced no error diagnostics. /// @@ -193,9 +202,16 @@ class BinaryTranslator { [[nodiscard]] TranslatedCodeObject translate(const AmdGpuCodeObject &obj); private: + /// @brief Translate without final-output validation. + /// @details Keeping the translation body in a separate call ensures its + /// analysis state is destroyed before translate() audits the resulting ELF. + [[nodiscard]] TranslatedCodeObject translate_impl(const AmdGpuCodeObject &obj); + /// @brief Whether this translator is running the gfx1250 B0-to-A0 profile. [[nodiscard]] bool is_gfx1250_b0_to_a0() const; + void verify_rewrite_discharge(TranslatedCodeObject &result) const; + /// @brief Return the generated or revision-specific legalization for an instruction. [[nodiscard]] const InstructionLegalization *lookup_legalization(const Instruction &inst) const; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h index 30829ba098a5..13e4856bb050 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h @@ -13,15 +13,46 @@ #pragma once #include +#include #include #include +#include namespace rocjitsu { class BasicBlock; +class Decoder; +class Instruction; namespace internal { +enum class RewriteDischargeDecodeStatus : uint8_t { + Success, + InvalidLookaheadBound, + InvalidInstructionSize, + TruncatedInstruction, +}; + +/// @brief Decode final output through exactly the lookahead declared by one ISA decoder. +/// +/// @details The reusable buffer is zero-padded on every call. This keeps raw-pointer decoders +/// within their declared read window while allowing the caller to distinguish an invalid bound, +/// an invalid decoded size, and an instruction truncated by either the bound or remaining input. +class RewriteDischargeInstructionDecoder { +public: + explicit RewriteDischargeInstructionDecoder(Decoder &decoder); + + [[nodiscard]] bool has_valid_lookahead_bound() const { return !lookahead_words_.empty(); } + + [[nodiscard]] RewriteDischargeDecodeStatus decode(std::span remaining_bytes, + uint64_t source_offset, + std::unique_ptr &instruction); + +private: + Decoder &decoder_; + std::vector lookahead_words_; +}; + /// @brief Decide whether every external entry into an incomplete-consumer scope /// is an entry-state root that cannot carry an original `.text` pointer. /// diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp index 98870c3033ed..12d03bf6ce0d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp @@ -34,6 +34,7 @@ constexpr char kKindTranslatorDataOnly[] = "translator-data-only"; constexpr char kKindTranslatorNothingToTranslate[] = "translator-nothing-to-translate"; constexpr char kKindTranslatorResourceLimit[] = "translator-resource-limit"; constexpr char kKindTranslatorKernelSkipped[] = "translator-kernel-skipped"; +constexpr char kKindTranslatorResidualRewrite[] = "translator-residual-rewrite"; const char *diagnostic_severity_name(rocjitsu::DiagnosticSeverity severity) noexcept { switch (severity) { @@ -65,6 +66,8 @@ const char *diagnostic_kind_name(rocjitsu::DiagnosticKind kind) noexcept { return kKindTranslatorResourceLimit; case rocjitsu::DiagnosticKind::KernelSkipped: return kKindTranslatorKernelSkipped; + case rocjitsu::DiagnosticKind::ResidualRewrite: + return kKindTranslatorResidualRewrite; } return "unknown"; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp index 846543402b49..1f7aecad8910 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp @@ -437,6 +437,7 @@ void append_descriptor_error(KdTranslation &result, std::string message) { result.diagnostics.push_back({.severity = DiagnosticSeverity::Error, .kind = DiagnosticKind::KernelDescriptor, .guest_offset = std::nullopt, + .output_offset = std::nullopt, .mnemonic = {}, .message = std::move(message), .required_work = {}}); @@ -884,12 +885,15 @@ void KdTranslation::configure_skipped_stub() { prologue_words.clear(); } -std::vector KernelDescriptorTranslator::translate_image( - std::span image, uint64_t text_offset, uint64_t text_size, - const KernelDescriptorTranslationOptions &options) const { +std::vector +KernelDescriptorTranslator::translate_image(std::span image, uint64_t text_offset, + uint64_t text_size, + const KernelDescriptorTranslationOptions &options, + std::optional text_section_index) const { std::vector translations; - for (KernelDescriptorInfo &kd : scan_kernel_descriptors(image, text_offset, text_size)) { + for (KernelDescriptorInfo &kd : + scan_kernel_descriptors(image, text_offset, text_size, text_section_index)) { translations.push_back(translate_one_descriptor( guest_arch_, host_arch_, kd.descriptor_file_offset, std::move(kd.kernel_name), kd.entry_text_offset, kd.descriptor, options)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.h index cf7040a2a52c..f882fca80a67 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.h @@ -407,7 +407,8 @@ class KernelDescriptorTranslator { [[nodiscard]] std::vector translate_image(std::span image, uint64_t text_offset, uint64_t text_size, - const KernelDescriptorTranslationOptions &options) const; + const KernelDescriptorTranslationOptions &options, + std::optional text_section_index = std::nullopt) const; /// @brief Recompute one already-discovered kernel descriptor. /// diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp index 8acb526b8705..05457ec07e69 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.cpp @@ -43,10 +43,10 @@ namespace { /// unimplemented siblings then fail closed instead of passing through silently. /// That is why the integer WMMA prefixes below keep their entry. /// -/// Separately, a 64-bit source reading FLAT_SCRATCH_BASE is classified via -/// operand inspection (see gfx1250_reads_flat_scratch_base_64bit), and the -/// barrier-state query and s_monitor_sleep are DEFERRED with a pass-through -/// report rather than fail-closed (see gfx1250_b0_to_a0_is_deferred_family). +/// Separately, non-opcode-keyed rewrites are classified by SemanticTranslator's +/// profile registry, and the barrier-state and sleep/monitor families are +/// DEFERRED with a pass-through report rather than fail-closed (see +/// gfx1250_b0_to_a0_is_deferred_family). inline constexpr std::array kExactB0ToA0TranslationMnemonics = { "ds_load_2addr_b32", "ds_load_2addr_b64", @@ -260,13 +260,7 @@ const InstructionLegalization *gfx1250_b0_to_a0_legalization(const Instruction & if (fp8_clamp_family && !requires_fp8_clamp_emulation(inst)) return nullptr; - // Reading FLAT_SCRATCH_BASE through a 64-bit source position is a property of - // the operand rather than the mnemonic, so it is classified separately. - // Deferred families reach here and stay on the copy path. Reporting that - // omission is the translation loop's job: see - // gfx1250_b0_to_a0_is_deferred_family. - if (!requires_b0_to_a0_expansion(inst.mnemonic()) && - !gfx1250_reads_flat_scratch_base_64bit(inst)) { + if (!requires_b0_to_a0_expansion(inst.mnemonic())) { return nullptr; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp index ca309f9f4394..e14dfed5130a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_b0_to_a0.cpp @@ -6,6 +6,7 @@ #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/analysis/liveness.h" +#include "rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.h" #include "rocjitsu/code/dbt/semantic/rules.h" #include "rocjitsu/code/dbt/semantic_scratch.h" #include "rocjitsu/code/dbt/translation_rule.h" @@ -32,6 +33,41 @@ namespace rocjitsu { namespace { +[[nodiscard]] bool always_residual(const Instruction &) { return true; } +[[nodiscard]] bool scale16_residual(const Instruction &inst); +[[nodiscard]] bool cvt_f32_fp8_e5m3_residual(const Instruction &inst); +[[nodiscard]] bool cvt_pk_fp8_f32_e5m3_residual(const Instruction &inst); +[[nodiscard]] bool cvt_sr_fp8_f32_e5m3_residual(const Instruction &inst); + +[[nodiscard]] constexpr RewriteDischarge checked_discharge(ResidualExpandFn check) { + return RewriteDischarge::checked(check, RewriteDischargeContext::Instruction); +} + +[[nodiscard]] constexpr RewriteDischarge block_checked_discharge(ResidualExpandFn check) { + return RewriteDischarge::checked(check, RewriteDischargeContext::BasicBlock); +} + +[[nodiscard]] constexpr RewriteDischarge no_success_discharge(const char *rationale) { + return RewriteDischarge::no_success(rationale); +} + +/// @brief Internal-linkage adapters keep registry callback addresses usable in +/// compile-time validation under GCC sanitizer builds. +[[nodiscard]] bool flat_scratch_base_rewrite_applies(const Instruction &inst) { + return gfx1250_reads_flat_scratch_base_64bit(inst); +} + +[[nodiscard]] ExpandResult lower_flat_scratch_base_rewrite(const Instruction &inst, uint64_t offset, + std::span source_text, + const LivenessAnalysis &liveness, + TranslationContext &context) { + return gfx1250_lower_flat_scratch_base_source(inst, offset, source_text, liveness, context); +} + +[[nodiscard]] bool flat_scratch_base_rewrite_residual(const Instruction &inst) { + return gfx1250_flat_scratch_base_residual(inst); +} + /// @brief gfx1250 special-scalar operand encodings. /// @details CRITICAL: on gfx1250 these are the INVERSE of CDNA — M0 = 125 and /// NULL = 124, whereas CDNA encodes M0 = 124. Every hand-written encoding below @@ -473,6 +509,25 @@ ExpandResult expand_gfx1250_s_clause(const Instruction &inst, uint32_t, uint64_t /// slots, and no corpus object has that adjacency. Fixing it needs the emitted /// stream rather than the source, which is the same whole-kernel pass the IU8 /// rule's own TODO asks for; do both together. +[[nodiscard]] bool setreg_mode_ordering_residual(const Instruction &inst) { + constexpr int kRequiredLeadingVNops = 2; + + if (inst.mnemonic() != "s_setreg_b32" && inst.mnemonic() != "s_setreg_imm32_b32") + return false; + const int size_bytes = inst.size(); + if (size_bytes < static_cast(sizeof(uint32_t)) || + size_bytes % static_cast(sizeof(uint32_t)) != 0 || inst.raw_encoding() == nullptr) + return true; + + const uint16_t simm16 = static_cast(inst.raw_encoding()[0] & 0xffffu); + if (amdgpu::decode_vgpr_msb_hwreg(simm16).id != amdgpu::MODE_HWREG) + return false; + + return count_adjacent_canonical_v_nops(inst, kRequiredLeadingVNops, + &Instruction::previous_instruction) < + kRequiredLeadingVNops; +} + ExpandResult expand_gfx1250_setreg_mode_ordering(const Instruction &inst, uint32_t, uint64_t, std::span, const LivenessAnalysis &, TranslationContext &, const LaneLayout *, @@ -775,6 +830,23 @@ struct TensorMaskWrapper { return has_canonical_predecessor(inst, build_tensor_mask_clear(descriptor_base)); } +/// @brief Whether the tensor-load expansion still needs to add its canonical prefix. +[[nodiscard]] bool tensor_load_residual(const Instruction &inst) { + if (inst.mnemonic() != "tensor_load_to_lds" || + inst.size() != static_cast(sizeof(cdna5::VimageMachineInst)) || + inst.raw_encoding() == nullptr) { + return true; + } + + cdna5::VimageMachineInst source{}; + std::memcpy(&source, inst.raw_encoding(), sizeof(source)); + constexpr uint8_t kLastOrdinarySgpr = 105; + const uint8_t descriptor_base = static_cast(source.vaddr1); + if (descriptor_base == kGfx1250Null || descriptor_base > kLastOrdinarySgpr - 7u) + return true; + return !has_tensor_mask_clear(inst, descriptor_base); +} + /// @brief Disable Tensor-DMA multicast for one A0 tensor load. /// /// @details TENSOR_LOAD_TO_LDS does not encode multicast in the instruction. @@ -811,7 +883,7 @@ ExpandResult expand_gfx1250_tensor_load_to_lds(const Instruction &inst, uint32_t {"Provide TENSOR_LOAD_TO_LDS VADDR1 as an ordinary eight-SGPR descriptor."}); } - if (has_tensor_mask_clear(inst, descriptor_base)) { + if (!tensor_load_residual(inst)) { return ExpandResult::success(std::vector( inst.raw_encoding(), inst.raw_encoding() + sizeof(cdna5::VimageMachineInst) / sizeof(uint32_t))); @@ -849,6 +921,22 @@ void set_word_field(uint32_t &word, uint32_t value, uint32_t shift, uint32_t wid word = (word & ~mask) | ((value << shift) & mask); } +/// @brief Whether a regular-Scale compound still needs normalization or splitting. +[[nodiscard]] bool regular_scale_residual(const Instruction &inst) { + if (!inst.mnemonic().starts_with("v_wmma_scale_f32_") || + inst.size() != 4 * static_cast(sizeof(uint32_t)) || inst.raw_encoding() == nullptr) { + return true; + } + + cdna5::Vop3pMachineInst scale{}; + cdna5::Vop3pMachineInst matrix{}; + std::memcpy(&scale, inst.raw_encoding(), sizeof(scale)); + std::memcpy(&matrix, inst.raw_encoding() + 2, sizeof(matrix)); + if (gfx1250_floating_wmma_control_error(matrix, &scale) != nullptr) + return true; + return matrix.op == cdna5::kVWmmaF3232x16x128F4Vop3p || scale.src2 != 0x100; +} + /// @brief Emit two A0 M=16 FP4 operations for one M=32 FP4 matrix operation. /// /// @details A0 has no M=32 FP4 matrix opcode. Rows 0..15 and 16..31 are @@ -981,8 +1069,10 @@ ExpandResult expand_gfx1250_wmma_scale_src2(const Instruction &inst, uint32_t, u return ExpandResult::failed(error); if (matrix.op != cdna5::kVWmmaF3232x16x128F4Vop3p) { std::vector words(inst.raw_encoding(), inst.raw_encoding() + 4); - // Instruction bits [58:50] occupy word 1 bits [26:18]. - set_word_field(words[1], 0x100, 18, 9); + if (regular_scale_residual(inst)) { + // Instruction bits [58:50] occupy word 1 bits [26:18]. + set_word_field(words[1], 0x100, 18, 9); + } return ExpandResult::success(std::move(words)); } @@ -1198,6 +1288,36 @@ ExpandResult expand_gfx1250_wmma_scale16(const Instruction &inst, uint32_t, uint return ExpandResult::success(std::move(words)); } +/// @brief Whether the shared structural key denotes an implemented Scale16 expansion. +[[nodiscard]] bool scale16_residual(const Instruction &inst) { + if (!inst.mnemonic().starts_with("v_wmma_scale16_f32_")) + return false; + if (inst.size() != 4 * static_cast(sizeof(uint32_t)) || inst.raw_encoding() == nullptr) + return true; + + cdna5::Vop3pMachineInst scale{}; + cdna5::Vop3pMachineInst matrix{}; + std::memcpy(&scale, inst.raw_encoding(), sizeof(scale)); + std::memcpy(&matrix, inst.raw_encoding() + 2, sizeof(matrix)); + if (scale.op != kWmmaScale16PrefixOp || + (matrix.op != cdna5::kVWmmaF3216x16x128F8f6f4Vop3p && + matrix.op != cdna5::kVWmmaF3232x16x128F4Vop3p) || + gfx1250_floating_wmma_control_error(matrix, &scale) != nullptr) { + return true; + } + + constexpr uint16_t kVgprEncoding = 256; + for (const uint16_t encoded_scale : + {static_cast(scale.src0), static_cast(scale.src1)}) { + if (encoded_scale < kVgprEncoding) + continue; + const uint16_t base = static_cast(encoded_scale - kVgprEncoding); + if ((base & 1u) != 0 || base > 254u) + return true; + } + return matrix.op == cdna5::kVWmmaF3232x16x128F4Vop3p || scale.src2 != 0x100; +} + /// @brief Conservatively separate B0 integer WMMA from its A0 successor. /// /// @details gfx1250 requires nine separating V_NOPs when dense IU8 WMMA feeds a @@ -1216,21 +1336,40 @@ ExpandResult expand_gfx1250_wmma_scale16(const Instruction &inst, uint32_t, uint /// inactive shadow ran no WMMA and so has nothing to separate. What remains is /// an EXEC clear between the WMMA and its shadow, which is the case the TODO /// below has to rule out before it can count anything but a V_NOP. +[[nodiscard]] int required_iu8_spacing_slots(const Instruction &inst) { + if (inst.mnemonic() == "v_wmma_i32_16x16x64_iu8") + return 9; + if (inst.mnemonic() == "v_swmmac_i32_16x16x128_iu8") + return 5; + return 0; +} + +[[nodiscard]] int existing_iu8_spacing_slots(const Instruction &inst, int required_slots) { + return count_adjacent_canonical_v_nops(inst, required_slots, &Instruction::next_instruction); +} + +[[nodiscard]] bool iu8_spacing_residual(const Instruction &inst) { + const int required_slots = required_iu8_spacing_slots(inst); + if (required_slots == 0) + return false; + if (inst.size() != 2 * static_cast(sizeof(uint32_t)) || inst.raw_encoding() == nullptr) + return true; + return existing_iu8_spacing_slots(inst, required_slots) < required_slots; +} + ExpandResult expand_gfx1250_wmma_iu8_spacing(const Instruction &inst, uint32_t, uint64_t, std::span, const LivenessAnalysis &, TranslationContext &, const LaneLayout *, const LaneLayout *) { - if (inst.mnemonic() != "v_wmma_i32_16x16x64_iu8" && - inst.mnemonic() != "v_swmmac_i32_16x16x128_iu8") + const int required_slots = required_iu8_spacing_slots(inst); + if (required_slots == 0) return ExpandResult::not_handled(); if (inst.size() != 2 * static_cast(sizeof(uint32_t)) || inst.raw_encoding() == nullptr) return ExpandResult::failed("gfx1250 IU8 WMMA rule received an unsupported VOP3P instruction"); std::vector words(inst.raw_encoding(), inst.raw_encoding() + inst.size() / sizeof(uint32_t)); - const int required_slots = inst.mnemonic() == "v_wmma_i32_16x16x64_iu8" ? 9 : 5; - const int existing_slots = - count_adjacent_canonical_v_nops(inst, required_slots, &Instruction::next_instruction); + const int existing_slots = existing_iu8_spacing_slots(inst, required_slots); // TODO: Replace canonical V_NOP counting with whole-kernel scheduling that // can also credit independent VALU in each reachable successor. Crediting real @@ -1264,6 +1403,14 @@ ExpandResult expand_gfx1250_wmma_iu8_spacing(const Instruction &inst, uint32_t, {.ssrc0 = kGfx1250InlineZero, .sdst = kGfx1250M0})[0]; } +[[nodiscard]] bool cluster_load_residual(const Instruction &inst) { + if (!is_gfx1250_cluster_load(inst.opcode())) + return false; + if (inst.size() != 3 * static_cast(sizeof(uint32_t)) || inst.raw_encoding() == nullptr) + return true; + return !has_canonical_predecessor(inst, build_cluster_m0_clear()); +} + /// @brief Rewrite a gfx1250 cluster load to run with M0 = 0. /// /// @details Every cluster-load form (both SADDR and off/NULL-saddr, all widths) @@ -1289,7 +1436,7 @@ ExpandResult expand_gfx1250_cluster_load(const Instruction &inst, uint32_t, uint return ExpandResult::failed("gfx1250 cluster-load rule received an unsupported instruction"); } - if (has_canonical_predecessor(inst, build_cluster_m0_clear())) { + if (!cluster_load_residual(inst)) { return ExpandResult::success( std::vector(inst.raw_encoding(), inst.raw_encoding() + 3)); } @@ -1967,7 +2114,7 @@ ExpandResult expand_gfx1250_cvt_f32_fp8_e5m3(const Instruction &inst, uint32_t, cdna5::Vop3MachineInst source{}; std::memcpy(&source, inst.raw_encoding(), sizeof(source)); constexpr uint16_t kVgprEncoding = 256; - if (source.clamp == 0) + if (!cvt_f32_fp8_e5m3_residual(inst)) return ExpandResult::not_handled(); // ABS, NEG, and OMOD are unsupported for this conversion and do not affect // its result, so their encoded values are intentionally ignored. @@ -2108,6 +2255,35 @@ ExpandResult expand_gfx1250_cvt_f32_fp8_e5m3(const Instruction &inst, uint32_t, return ExpandResult::success(std::move(words)); } +[[nodiscard]] bool cvt_f32_fp8_e5m3_residual(const Instruction &inst) { + if (!inst.mnemonic().starts_with("v_cvt_f32_fp8") || + inst.size() != 2 * static_cast(sizeof(uint32_t)) || inst.raw_encoding() == nullptr) { + return true; + } + cdna5::Vop3MachineInst source{}; + std::memcpy(&source, inst.raw_encoding(), sizeof(source)); + return source.clamp != 0; +} + +[[nodiscard]] bool cvt_fp8_f32_e5m3_residual(const Instruction &inst, std::string_view mnemonic) { + if (inst.mnemonic() != mnemonic || + inst.size() < static_cast(sizeof(cdna5::Vop3MachineInst)) || + inst.raw_encoding() == nullptr) { + return true; + } + cdna5::Vop3MachineInst source{}; + std::memcpy(&source, inst.raw_encoding(), sizeof(source)); + return source.clamp != 0; +} + +[[nodiscard]] bool cvt_pk_fp8_f32_e5m3_residual(const Instruction &inst) { + return cvt_fp8_f32_e5m3_residual(inst, "v_cvt_pk_fp8_f32"); +} + +[[nodiscard]] bool cvt_sr_fp8_f32_e5m3_residual(const Instruction &inst) { + return cvt_fp8_f32_e5m3_residual(inst, "v_cvt_sr_fp8_f32"); +} + /// @brief Wrap a standalone low-precision WMMA in an A0-safe neutral scale prefix. /// /// @details gfx1250 A0 cannot safely expose the bare F8F6F4 matrix instruction to @@ -2239,8 +2415,8 @@ ExpandResult expand_gfx1250_k128_wmma(const Instruction &inst, uint32_t, uint64_ // These operand restrictions belong to the packed-f16 lowering alone: it // addresses the accumulator and destination one dword at a time and needs // an f32 source it can materialize. The f32 path re-encodes VDST, SRC0, - // SRC1, and SRC2 unchanged, so it must keep accepting whatever the source - // instruction already encoded. + // SRC1, and SRC2 unchanged, so it separately rejects accumulator selectors + // that the scaled form cannot represent. if ((source.src0 & 1u) != 0 || (source.src1 & 1u) != 0 || (source.vdst & 1u) != 0) { return ExpandResult::failed( "gfx1250 f16 K=128 WMMA matrix operands and destination are not even VGPR ranges"); @@ -2411,6 +2587,11 @@ ExpandResult expand_gfx1250_k128_wmma(const Instruction &inst, uint32_t, uint64_ return ExpandResult::success(std::move(words)); } + if (source.src2 < kGfx1250InlineZero) { + return ExpandResult::failed( + "gfx1250 K=128 f32 WMMA scalar accumulator cannot be represented by the scaled form"); + } + if (!gfx1250_k128_wmma_formats(inst.opcode(), matrix_a_fmt, matrix_b_fmt)) return ExpandResult::failed("gfx1250 K=128 WMMA rule received an unsupported opcode"); @@ -2448,100 +2629,139 @@ static_assert(kSetregImm32B32EncodingId == kSetregB32EncodingId + 1, inline constexpr std::array kGfx1250B0ToA0ExpandRules = {{ {kSetregB32EncodingId, cdna5::kSSetregB32Sopk, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_setreg_mode_ordering, nullptr, nullptr, false}, + expand_gfx1250_setreg_mode_ordering, nullptr, nullptr, false, + block_checked_discharge(setreg_mode_ordering_residual)}, {kSetregImm32B32EncodingId, cdna5::kSSetregImm32B32Sopk, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_setreg_mode_ordering, nullptr, nullptr, false}, + expand_gfx1250_setreg_mode_ordering, nullptr, nullptr, false, + block_checked_discharge(setreg_mode_ordering_residual)}, {cdna5::encoding::kSop1, cdna5::kSBarrierSignalIsfirstSop1, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_barrier_signal_isfirst, nullptr, nullptr, false}, + expand_gfx1250_barrier_signal_isfirst, nullptr, nullptr, false, + no_success_discharge("the rule only rejects one unsupported source encoding and never emits")}, {cdna5::encoding::kSopp, cdna5::kSClauseSopp, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_s_clause, nullptr, nullptr, false}, + expand_gfx1250_s_clause, nullptr, nullptr, false, checked_discharge(always_residual)}, {cdna5::encoding::kVop3p, cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_bare_f8f6f4_wmma, nullptr, nullptr, false}, + nullptr, expand_gfx1250_bare_f8f6f4_wmma, nullptr, nullptr, false, + checked_discharge(always_residual)}, {cdna5::encoding::kVop3p, kWmmaScaleSrc2PrefixOp, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_wmma_scale_src2, nullptr, nullptr}, + expand_gfx1250_wmma_scale_src2, nullptr, nullptr, true, + checked_discharge(regular_scale_residual)}, {cdna5::encoding::kVop3p, kWmmaScale16PrefixOp, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_wmma_scale16, nullptr, nullptr}, + expand_gfx1250_wmma_scale16, nullptr, nullptr, true, checked_discharge(scale16_residual)}, {cdna5::encoding::kVop3p, cdna5::kVWmmaI3216x16x64Iu8Vop3p, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_wmma_iu8_spacing, nullptr, nullptr, false}, + expand_gfx1250_wmma_iu8_spacing, nullptr, nullptr, false, + block_checked_discharge(iu8_spacing_residual)}, {cdna5::encoding::kVop3p, cdna5::kVSwmmacI3216x16x128Iu8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_wmma_iu8_spacing, nullptr, nullptr, false}, + nullptr, expand_gfx1250_wmma_iu8_spacing, nullptr, nullptr, false, + block_checked_discharge(iu8_spacing_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF3216x16x128Fp8Fp8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false, + checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF3216x16x128Fp8Bf8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false, + checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF3216x16x128Bf8Fp8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false, + checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF3216x16x128Bf8Bf8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, false, + checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF1616x16x128Fp8Fp8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF1616x16x128Fp8Bf8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF1616x16x128Bf8Fp8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF1616x16x128Bf8Bf8Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr}, + nullptr, expand_gfx1250_k128_wmma, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVop3pOpHi1, cdna5::kVWmmaF3232x16x128F4Vop3p, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_wmma_32x16_f4, nullptr, nullptr}, + nullptr, expand_gfx1250_wmma_32x16_f4, nullptr, nullptr, true, + checked_discharge(always_residual)}, {cdna5::encoding::kVimage, cdna5::kTensorLoadToLdsVimage, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_tensor_load_to_lds, nullptr, nullptr}, + expand_gfx1250_tensor_load_to_lds, nullptr, nullptr, true, + block_checked_discharge(tensor_load_residual)}, {cdna5::encoding::kVop3OpHi3, cdna5::kVCvtF32Fp8Vop3, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_cvt_f32_fp8_e5m3, nullptr, nullptr}, + expand_gfx1250_cvt_f32_fp8_e5m3, nullptr, nullptr, true, + checked_discharge(cvt_f32_fp8_e5m3_residual)}, {cdna5::encoding::kVop3OpHi6, cdna5::kVCvtPkFp8F32Vop3, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_cvt_pk_fp8_f32_e5m3, nullptr, nullptr}, + expand_gfx1250_cvt_pk_fp8_f32_e5m3, nullptr, nullptr, true, + checked_discharge(cvt_pk_fp8_f32_e5m3_residual)}, {cdna5::encoding::kVop3OpHi6, cdna5::kVCvtSrFp8F32Vop3, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_cvt_sr_fp8_f32_e5m3, nullptr, nullptr}, + expand_gfx1250_cvt_sr_fp8_f32_e5m3, nullptr, nullptr, true, + checked_discharge(cvt_sr_fp8_f32_e5m3_residual)}, {cdna5::encoding::kVds, cdna5::kDsStore2addrB32Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds2, nullptr, nullptr}, + expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVds, cdna5::kDsStore2addrStride64B32Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds2, nullptr, nullptr}, + expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi1, cdna5::kDsStorexchg2addrRtnB32Vds, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi1, cdna5::kDsStorexchg2addrStride64RtnB32Vds, RuleAction::Expand, 0, - 0, nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + 0, nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi1, cdna5::kDsLoad2addrB32Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds2, nullptr, nullptr}, + expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi1, cdna5::kDsLoad2addrStride64B32Vds, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi2, cdna5::kDsStore2addrB64Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds2, nullptr, nullptr}, + expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi2, cdna5::kDsStore2addrStride64B64Vds, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi3, cdna5::kDsStorexchg2addrRtnB64Vds, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi3, cdna5::kDsStorexchg2addrStride64RtnB64Vds, RuleAction::Expand, 0, - 0, nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + 0, nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi3, cdna5::kDsLoad2addrB64Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds2, nullptr, nullptr}, + expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi3, cdna5::kDsLoad2addrStride64B64Vds, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_ds2, nullptr, nullptr}, + nullptr, expand_gfx1250_ds2, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi5, cdna5::kDsStoreAddtidB32Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds_addtid, nullptr, nullptr}, + expand_gfx1250_ds_addtid, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVdsOpHi5, cdna5::kDsLoadAddtidB32Vds, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_ds_addtid, nullptr, nullptr}, + expand_gfx1250_ds_addtid, nullptr, nullptr, true, checked_discharge(always_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadB32Vglobal, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_cluster_load, nullptr, nullptr}, + expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadB64Vglobal, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_cluster_load, nullptr, nullptr}, + expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadB128Vglobal, RuleAction::Expand, 0, 0, nullptr, - expand_gfx1250_cluster_load, nullptr, nullptr}, + expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadAsyncToLdsB8Vglobal, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_cluster_load, nullptr, nullptr}, + nullptr, expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadAsyncToLdsB32Vglobal, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_cluster_load, nullptr, nullptr}, + nullptr, expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadAsyncToLdsB64Vglobal, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_cluster_load, nullptr, nullptr}, + nullptr, expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, {cdna5::encoding::kVglobal, cdna5::kClusterLoadAsyncToLdsB128Vglobal, RuleAction::Expand, 0, 0, - nullptr, expand_gfx1250_cluster_load, nullptr, nullptr}, + nullptr, expand_gfx1250_cluster_load, nullptr, nullptr, true, + block_checked_discharge(cluster_load_residual)}, }}; static_assert(translation_rules_sorted(kGfx1250B0ToA0ExpandRules), "the gfx1250 B0-to-A0 rule table must stay sorted by (encoding id, opcode)"); +inline constexpr std::array kGfx1250B0ToA0InstructionRewriteRules = + {{ + {"flat-scratch-base-64bit-source", flat_scratch_base_rewrite_applies, + lower_flat_scratch_base_rewrite, true, + checked_discharge(flat_scratch_base_rewrite_residual)}, + }}; + +inline constexpr RewriteRegistry kGfx1250B0ToA0RewriteRegistry = { + kGfx1250B0ToA0ExpandRules, + kGfx1250B0ToA0InstructionRewriteRules, +}; + +static_assert(kGfx1250B0ToA0RewriteRegistry.has_complete_discharge()); + } // namespace std::span semantic_expand_rules_gfx1250_b0_to_a0() { return kGfx1250B0ToA0ExpandRules; } +RewriteRegistry rewrite_registry_gfx1250_b0_to_a0() { return kGfx1250B0ToA0RewriteRegistry; } + } // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.cpp index c1cb0c94ef27..d344e564f315 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.cpp @@ -369,6 +369,30 @@ bool gfx1250_reads_flat_scratch_base_64bit(const Instruction &inst) { return false; } +bool gfx1250_flat_scratch_base_residual(const Instruction &inst) { + const uint32_t *raw = inst.raw_encoding(); + if (raw == nullptr) + return false; + const std::optional layout = source_fields(raw[0]); + if (!layout) + return instruction_names_selector_in_any_64bit_source(inst); + + const size_t available = + inst.size() > 0 ? static_cast(inst.size()) / sizeof(uint32_t) : 0; + const std::span words(raw, std::min(modelled_word_count(*layout), available)); + const int sources = std::min(inst.num_src_operands(), static_cast(layout->count)); + for (int source_index = 0; source_index < sources; ++source_index) { + if (!is_flat_scratch_base_64bit_source(inst, source_index, *layout, words)) + continue; + if (layout->vector) + return true; + const Operand *operand = inst.src_operand(source_index); + if (operand != nullptr && operand->encoding_value() == kFlatScratchBaseHi) + return true; + } + return false; +} + ExpandResult gfx1250_lower_flat_scratch_base_source(const Instruction &inst, uint64_t offset, std::span source_text, const LivenessAnalysis &liveness, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.h index 5149cc87f47d..512e393bb0c4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/gfx1250_flat_scratch_base.h @@ -33,6 +33,14 @@ class LivenessAnalysis; /// mistaken for the selectors they collide with. [[nodiscard]] bool gfx1250_reads_flat_scratch_base_64bit(const Instruction &inst); +/// @brief True when a final A0 instruction still needs the 64-bit +/// FLAT_SCRATCH_BASE operand rewrite. +/// +/// @details Scalar A0 reads are canonical with selector 230, while selector +/// 231 remains actionable. Vector ALU source fields cannot retain either +/// selector and must name the ordinary SGPR pair produced by the lowering. +[[nodiscard]] bool gfx1250_flat_scratch_base_residual(const Instruction &inst); + /// @brief Rewrite a 64-bit FLAT_SCRATCH_BASE source for the A0 profile. /// /// @details Scalar reads keep their instruction and change the selector to 230. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/rules.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/rules.h index 0e3f0009c0b9..7637a48ddf1b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/rules.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/rules.h @@ -21,6 +21,9 @@ namespace rocjitsu { /// @brief gfx1250 B0-to-A0 semantic expansions. [[nodiscard]] std::span semantic_expand_rules_gfx1250_b0_to_a0(); +/// @brief Complete gfx1250 B0-to-A0 handwritten rewrite registry. +[[nodiscard]] RewriteRegistry rewrite_registry_gfx1250_b0_to_a0(); + /// @brief CDNA4 source rules for the RDNA3 target. [[nodiscard]] std::span semantic_expand_rules_cdna4_to_rdna3(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp index e7dcd88749fd..799c0f802d58 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp @@ -12,38 +12,53 @@ #include #include #include +#include namespace rocjitsu { namespace { -/// @brief Select the handwritten semantic rule table for one ISA pair. -/// @details Empty spans are intentional: most ISA pairs currently rely -/// entirely on generated legalization and encoding translation. -[[nodiscard]] std::span -semantic_expand_rules_for(rj_code_arch_t guest, rj_code_arch_t host, - ProcessorRevision input_revision, ProcessorRevision output_revision) { +/// @brief Select the handwritten rewrite registry for one ISA pair. +/// @details Most ISA pairs currently have only an opcode table and do not offer +/// complete registry-level rewrite-discharge verification. +[[nodiscard]] RewriteRegistry rewrite_registry_for(rj_code_arch_t guest, rj_code_arch_t host, + ProcessorRevision input_revision, + ProcessorRevision output_revision) { if (guest == ROCJITSU_CODE_ARCH_CDNA4 && host == ROCJITSU_CODE_ARCH_RDNA4) - return semantic_expand_rules_cdna4_to_rdna4(); + return {semantic_expand_rules_cdna4_to_rdna4(), {}}; if (guest == ROCJITSU_CODE_ARCH_CDNA4 && host == ROCJITSU_CODE_ARCH_CDNA3) - return semantic_expand_rules_cdna4_to_cdna3(); + return {semantic_expand_rules_cdna4_to_cdna3(), {}}; // gfx1250 A0 and B0 share one architectural target ID. Select the B0-to-A0 // profile only for that explicit revision pair. if (guest == ROCJITSU_CODE_ARCH_GFX1250 && host == ROCJITSU_CODE_ARCH_GFX1250 && input_revision == ProcessorRevision::Gfx1250B0 && output_revision == ProcessorRevision::Gfx1250A0) - return semantic_expand_rules_gfx1250_b0_to_a0(); + return rewrite_registry_gfx1250_b0_to_a0(); if (guest == ROCJITSU_CODE_ARCH_CDNA4 && host == ROCJITSU_CODE_ARCH_RDNA3) - return semantic_expand_rules_cdna4_to_rdna3(); + return {semantic_expand_rules_cdna4_to_rdna3(), {}}; return {}; } +[[nodiscard]] ExpandResult enforce_discharge_contract(std::string_view name, + const RewriteDischarge &discharge, + ExpandResult result) { + if (!discharge.allows(result.status)) { + return ExpandResult::failed("rewrite registry contract violation: '" + std::string(name) + + "' emitted output without a residual predicate"); + } + return result; +} + } // namespace SemanticTranslator::SemanticTranslator(rj_code_arch_t guest, rj_code_arch_t host, ProcessorRevision input_revision, ProcessorRevision output_revision) - : expand_rules_(semantic_expand_rules_for(guest, host, input_revision, output_revision)), + : rewrite_registry_(rewrite_registry_for(guest, host, input_revision, output_revision)), + expand_rules_(rewrite_registry_.opcode_rules), + instruction_rewrite_rules_(rewrite_registry_.instruction_rules), + instruction_rewrites_require_basic_block_( + rewrite_registry_.instruction_rewrites_require_basic_block()), host_arch_(host) { expand_rule_keys_.reserve(expand_rules_.size()); uint16_t max_encoding_id = 0; @@ -86,9 +101,29 @@ ExpandResult SemanticTranslator::try_lower_expand(const Instruction &inst, uint6 const LivenessAnalysis &liveness, TranslationContext &context) const { const TranslationRule *rule = find_expand_rule(inst); - if (rule != nullptr) - return rule->expand_fn(inst, static_cast(host_arch_), offset, source_text, liveness, - context, rule->guest_layout, rule->host_layout); + if (rule != nullptr) { + auto result = rule->expand_fn(inst, static_cast(host_arch_), offset, source_text, + liveness, context, rule->guest_layout, rule->host_layout); + return enforce_discharge_contract(inst.mnemonic(), rule->discharge, std::move(result)); + } + return ExpandResult::not_handled(); +} + +ExpandResult SemanticTranslator::try_lower_instruction_rewrite(const Instruction &inst, + uint64_t offset, + std::span source_text, + const LivenessAnalysis &liveness, + TranslationContext &context) const { + for (const RegisteredInstructionRewrite &rule : instruction_rewrite_rules_) { + if (!rule.applies(inst)) + continue; + auto result = rule.lower(inst, offset, source_text, liveness, context); + if (result.status == ExpandStatus::NotHandled) { + return ExpandResult::failed("registered instruction rewrite '" + std::string(rule.name) + + "' matched but declined lowering"); + } + return enforce_discharge_contract(rule.name, rule.discharge, std::move(result)); + } return ExpandResult::not_handled(); } @@ -96,9 +131,58 @@ bool SemanticTranslator::has_expand_rule(const Instruction &inst) const { return has_expand_rule(inst.encoding_id(), inst.opcode()); } -bool SemanticTranslator::expand_rule_requires_liveness(const Instruction &inst) const { +bool SemanticTranslator::has_instruction_rewrite(const Instruction &inst) const { + return std::ranges::any_of(instruction_rewrite_rules_, + [&](const RegisteredInstructionRewrite &rule) { + return rule.applies != nullptr && rule.applies(inst); + }); +} + +bool SemanticTranslator::rewrite_requires_liveness(const Instruction &inst) const { + const TranslationRule *rule = find_expand_rule(inst); + if (rule != nullptr && rule->requires_liveness) + return true; + return std::ranges::any_of(instruction_rewrite_rules_, + [&](const RegisteredInstructionRewrite &candidate) { + return candidate.requires_liveness && candidate.applies != nullptr && + candidate.applies(inst); + }); +} + +bool SemanticTranslator::residual_rewrite_applies(const Instruction &inst) const { + return residual_rewrite_applies(inst, RewriteDischargeContext::Instruction) || + residual_rewrite_applies(inst, RewriteDischargeContext::BasicBlock); +} + +bool SemanticTranslator::instruction_local_residual_rewrite_applies(const Instruction &inst) const { + return residual_rewrite_applies(inst, RewriteDischargeContext::Instruction); +} + +bool SemanticTranslator::residual_rewrite_needs_basic_block(const Instruction &inst) const { + if (instruction_rewrites_require_basic_block_) + return true; const TranslationRule *rule = find_expand_rule(inst); - return rule != nullptr && rule->requires_liveness; + if (rule != nullptr && rule->discharge.disposition == RewriteDischargeDisposition::Checked && + rule->discharge.context == RewriteDischargeContext::BasicBlock) { + return true; + } + return false; +} + +bool SemanticTranslator::residual_rewrite_applies(const Instruction &inst, + RewriteDischargeContext context) const { + const TranslationRule *rule = find_expand_rule(inst); + if (rule != nullptr && rule->discharge.check != nullptr && + rule->discharge.disposition == RewriteDischargeDisposition::Checked && + rule->discharge.context == context && rule->discharge.check(inst)) { + return true; + } + return std::ranges::any_of( + instruction_rewrite_rules_, [&](const RegisteredInstructionRewrite &candidate) { + return candidate.discharge.disposition == RewriteDischargeDisposition::Checked && + candidate.discharge.context == context && candidate.discharge.check != nullptr && + candidate.discharge.check(inst); + }); } } // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.h index f8e13e4f4303..7aceae04dfa6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.h @@ -53,10 +53,10 @@ struct SemanticReplacement { /// @brief Semantic translator for cross-ISA behavioral differences. /// -/// @details All expansion rules (waitcnt, MFMA→WMMA, AccVGPR, etc.) are -/// registered as TranslationRule entries with RuleAction::Expand. The -/// try_lower_expand() method looks up rules by (encoding_id, opcode) via -/// binary search. +/// @details Opcode-keyed expansion rules (waitcnt, MFMA→WMMA, AccVGPR, etc.) +/// remain TranslationRule entries looked up by binary search. Operand-driven +/// instruction rewrites use a small ordered list. One RewriteRegistry selects +/// both representations and supplies their final-stream audit contracts. class SemanticTranslator { public: SemanticTranslator(rj_code_arch_t guest_arch, rj_code_arch_t host_arch, @@ -73,6 +73,12 @@ class SemanticTranslator { const LivenessAnalysis &liveness, TranslationContext &context) const; + /// @brief Try the registered non-opcode-keyed instruction rewrites. + [[nodiscard]] ExpandResult try_lower_instruction_rewrite(const Instruction &inst, uint64_t offset, + std::span source_text, + const LivenessAnalysis &liveness, + TranslationContext &context) const; + /// @brief Whether @p inst has a registered semantic expansion rule. /// /// @details The rule can still decline expansion after inspecting operands or @@ -85,10 +91,39 @@ class SemanticTranslator { packed_rule_key(encoding_id, opcode)); } - /// @brief Whether the matching expansion can query kernel liveness. - [[nodiscard]] bool expand_rule_requires_liveness(const Instruction &inst) const; + /// @brief Whether a registered non-opcode-keyed rewrite matches @p inst. + [[nodiscard]] bool has_instruction_rewrite(const Instruction &inst) const; + + /// @brief Whether any matching rewrite can query kernel liveness. + [[nodiscard]] bool rewrite_requires_liveness(const Instruction &inst) const; + + /// @brief Whether an implemented expansion remains actionable at @p inst. + /// + /// @details This checks both opcode-keyed and non-table rules selected by the + /// same profile registry used for lowering. + [[nodiscard]] bool residual_rewrite_applies(const Instruction &inst) const; + + /// @brief Whether an instruction-local rewrite remains actionable at @p inst. + /// + /// @details Predicates requiring neighboring instructions are excluded so a + /// caller can use this during a constant-memory linear decode. + [[nodiscard]] bool instruction_local_residual_rewrite_applies(const Instruction &inst) const; - [[nodiscard]] bool has_rules() const { return !expand_rules_.empty(); } + /// @brief Whether final-stream analysis at @p inst requires a decoded basic block. + /// + /// @details Opcode rules are selected by @p inst. A registered non-opcode + /// BasicBlock rule forces a conservative fallback because its residual + /// predicate may require neighbors before it can decide whether it applies. + [[nodiscard]] bool residual_rewrite_needs_basic_block(const Instruction &inst) const; + + [[nodiscard]] bool has_rules() const { + return !expand_rules_.empty() || !instruction_rewrite_rules_.empty(); + } + + /// @brief Whether every selected rewrite has a valid explicit audit contract. + [[nodiscard]] bool supports_rewrite_discharge() const { + return rewrite_registry_.has_complete_discharge(); + } private: [[nodiscard]] static constexpr uint32_t packed_rule_key(uint16_t encoding_id, uint16_t opcode) { @@ -102,10 +137,15 @@ class SemanticTranslator { } [[nodiscard]] const TranslationRule *find_expand_rule(const Instruction &inst) const; + [[nodiscard]] bool residual_rewrite_applies(const Instruction &inst, + RewriteDischargeContext context) const; - std::span expand_rules_; ///< Sorted by (src_encoding_id, src_opcode). + RewriteRegistry rewrite_registry_; + std::span expand_rules_; ///< Sorted by (src_encoding_id, src_opcode). + std::span instruction_rewrite_rules_; std::vector expand_rule_keys_; ///< Packed keys parallel to expand_rules_. std::vector expand_rule_encoding_bits_; ///< Cheap encoding prefilter for hot scans. + bool instruction_rewrites_require_basic_block_ = false; rj_code_arch_t host_arch_; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_diagnostic.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_diagnostic.h index a87a73339836..e046e32ad685 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_diagnostic.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_diagnostic.h @@ -31,19 +31,22 @@ enum class DiagnosticKind { NothingToTranslate, ResourceLimit, KernelSkipped, + ResidualRewrite, }; /// @brief One user/developer-facing DBT diagnostic. /// -/// @details Instruction diagnostics use @c guest_offset and @c mnemonic to point -/// at the original guest instruction. Whole-image failures such as descriptor -/// translation can leave those fields empty. @c required_work is intentionally a -/// short checklist for EXPAND failures so missing lowerings document the next -/// implementation steps instead of only reporting that translation failed. +/// @details Translation diagnostics use @c guest_offset and @c mnemonic to point +/// at the original guest instruction. Final-output verification instead uses +/// @c output_offset. Whole-image failures such as descriptor translation can +/// leave both offsets empty. @c required_work is intentionally a short checklist +/// for EXPAND failures so missing lowerings document the next implementation +/// steps instead of only reporting that translation failed. struct TranslationDiagnostic { DiagnosticSeverity severity = DiagnosticSeverity::Warning; DiagnosticKind kind = DiagnosticKind::Legalization; std::optional guest_offset; + std::optional output_offset; std::string mnemonic; std::string message; std::vector required_work; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h index e9184ca2e259..e9881d4c5c35 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/translation_rule.h @@ -408,6 +408,98 @@ using ExpandFn = ExpandResult (*)(const Instruction &inst, uint32_t arch, uint64 const LivenessAnalysis &liveness, TranslationContext &context, const LaneLayout *guest_layout, const LaneLayout *host_layout); +/// @brief Read-only test for whether an implemented expansion is still actionable. +/// +/// @details The predicate observes only the decoded instruction stream. It must +/// share any operand or neighboring-instruction trigger checks used by the +/// corresponding ExpandFn, but must not allocate resources or emit words. +using ResidualExpandFn = bool (*)(const Instruction &inst); + +/// @brief Whether and how a rewrite participates in final-stream discharge. +enum class RewriteDischargeDisposition : uint8_t { + Unregistered, ///< No audit contract was declared; audited profiles reject this state. + Checked, ///< Run the registered read-only predicate on the final stream. + NoSuccessfulExpansion, ///< The rule may decline or fail, but must never emit output. +}; + +/// @brief Decoded context required by one residual rewrite predicate. +enum class RewriteDischargeContext : uint8_t { + Instruction, ///< The predicate observes only the candidate instruction. + BasicBlock, ///< The predicate observes neighboring instructions in the decoded basic block. +}; + +/// @brief Explicit final-stream audit contract for one rewrite. +/// +/// @details Audited profiles require every rewrite to use checked() or +/// no_success(). A checked predicate declares the least decoded context it +/// needs: instruction-local checks support a constant-memory stream scan, while +/// basic-block checks require the verifier to retain the decoded CFG. +/// The default Unregistered state keeps older, unaudited profiles source +/// compatible without allowing an audited profile to silently omit a rule. +class RewriteDischarge { +public: + RewriteDischargeDisposition disposition = RewriteDischargeDisposition::Unregistered; + ResidualExpandFn check = nullptr; + const char *rationale = nullptr; + RewriteDischargeContext context = RewriteDischargeContext::Instruction; + + [[nodiscard]] static constexpr RewriteDischarge + checked(ResidualExpandFn predicate, RewriteDischargeContext required_context) { + return {RewriteDischargeDisposition::Checked, predicate, nullptr, required_context}; + } + + [[nodiscard]] static constexpr RewriteDischarge no_success(const char *reason) { + return {RewriteDischargeDisposition::NoSuccessfulExpansion, nullptr, reason, + RewriteDischargeContext::Instruction}; + } + + [[nodiscard]] constexpr bool valid() const { + if (disposition == RewriteDischargeDisposition::Checked) { + const bool valid_context = context == RewriteDischargeContext::Instruction || + context == RewriteDischargeContext::BasicBlock; + return check != nullptr && rationale == nullptr && valid_context; + } + if (disposition == RewriteDischargeDisposition::NoSuccessfulExpansion) + return check == nullptr && rationale != nullptr && rationale[0] != '\0' && + context == RewriteDischargeContext::Instruction; + return false; + } + + /// @brief Whether @p status is compatible with the declared audit contract. + [[nodiscard]] constexpr bool allows(ExpandStatus status) const { + return disposition != RewriteDischargeDisposition::NoSuccessfulExpansion || + status != ExpandStatus::Success; + } +}; + +/// @brief Applicability test for a non-opcode-keyed instruction rewrite. +using InstructionRewriteAppliesFn = bool (*)(const Instruction &inst); + +/// @brief Lowering callback for a non-opcode-keyed instruction rewrite. +using InstructionRewriteFn = ExpandResult (*)(const Instruction &inst, uint64_t offset, + std::span source_text, + const LivenessAnalysis &liveness, + TranslationContext &context); + +/// @brief One rewrite selected by operands or other instruction-local state. +/// +/// @details These rules are kept separate from the sorted opcode table so that +/// table lookup remains cheap. The same declaration drives applicability, +/// liveness selection, lowering, and final-stream discharge. +class RegisteredInstructionRewrite { +public: + const char *name = nullptr; + InstructionRewriteAppliesFn applies = nullptr; + InstructionRewriteFn lower = nullptr; + bool requires_liveness = true; + RewriteDischarge discharge; + + [[nodiscard]] constexpr bool valid() const { + return name != nullptr && name[0] != '\0' && applies != nullptr && lower != nullptr && + discharge.valid(); + } +}; + /// @brief A single translation rule for one (source, target) instruction. /// /// @details Keyed by (src_encoding_id, src_opcode) for lookup via binary search. @@ -428,6 +520,18 @@ struct TranslationRule { const LaneLayout *guest_layout; ///< Source matrix layout (for matrix Expand). const LaneLayout *host_layout; ///< Target matrix layout (for matrix Expand). bool requires_liveness = true; ///< Conservative default; tables opt out after auditing. + /// Explicit final-stream audit disposition for this expansion. + RewriteDischarge discharge; + + constexpr TranslationRule(uint16_t source_encoding_id, uint16_t source_opcode, + RuleAction rule_action, uint16_t target_opcode, uint8_t field_map_count, + const FieldMap *maps, ExpandFn expansion, + const LaneLayout *source_layout, const LaneLayout *target_layout, + bool needs_liveness = true, RewriteDischarge audit = {}) + : src_encoding_id(source_encoding_id), src_opcode(source_opcode), action(rule_action), + dst_opcode(target_opcode), num_field_maps(field_map_count), field_maps(maps), + expand_fn(expansion), guest_layout(source_layout), host_layout(target_layout), + requires_liveness(needs_liveness), discharge(audit) {} constexpr auto operator<=>(const TranslationRule &rhs) const { if (auto cmp = src_encoding_id <=> rhs.src_encoding_id; cmp != 0) @@ -479,6 +583,52 @@ static_assert(!translation_rules_sorted(kSameKeyDifferentTail), } // namespace translation_rule_detail +/// @brief Complete handwritten rewrite declaration for one translation profile. +/// +/// @details Opcode-keyed expansions and non-table instruction rewrites retain +/// their existing dispatch mechanisms, but are selected here as one profile. +/// Verification is available only when the registry is nonempty, the opcode +/// rules have strictly ordered unique keys, and every declared rule carries a +/// valid checked or no-success disposition. +class RewriteRegistry { +public: + std::span opcode_rules; + std::span instruction_rules; + + /// @brief Whether a non-opcode rule requires contextual final-stream analysis. + /// + /// @details These predicates cannot be evaluated safely by the streaming + /// verifier because their neighboring instructions do not exist until the CFG + /// is built. Conservatively request that CFG independent of the lowering + /// selector, which is allowed to differ from the residual predicate. + [[nodiscard]] constexpr bool instruction_rewrites_require_basic_block() const { + for (const RegisteredInstructionRewrite &rule : instruction_rules) { + if (rule.discharge.disposition == RewriteDischargeDisposition::Checked && + rule.discharge.context == RewriteDischargeContext::BasicBlock) { + return true; + } + } + return false; + } + + [[nodiscard]] constexpr bool has_complete_discharge() const { + if (opcode_rules.empty() && instruction_rules.empty()) + return false; + for (size_t rule_index = 0; rule_index < opcode_rules.size(); ++rule_index) { + const TranslationRule &rule = opcode_rules[rule_index]; + if (rule.action != RuleAction::Expand || rule.expand_fn == nullptr || !rule.discharge.valid()) + return false; + if (rule_index != 0 && !(opcode_rules[rule_index - 1] < rule)) + return false; + } + for (const RegisteredInstructionRewrite &rule : instruction_rules) { + if (!rule.valid()) + return false; + } + return true; + } +}; + // --------------------------------------------------------------------------- // Tier 3: Lane Layout Descriptor // --------------------------------------------------------------------------- diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/executable.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/executable.cpp index 7aaf080ff08e..81c340c45a6b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/executable.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/executable.cpp @@ -36,16 +36,19 @@ class HsaHeader : public Header { class HsaSection : public Section { public: - HsaSection(std::string name, std::unique_ptr data, const Elf64_Shdr &shdr) - : Section(std::move(name), std::move(data)), shdr_(shdr) {} + HsaSection(std::string name, std::unique_ptr data, const Elf64_Shdr &shdr, + size_t section_index) + : Section(std::move(name), std::move(data)), shdr_(shdr), section_index_(section_index) {} std::size_t size() const override { return shdr_.sh_size; } uint64_t flags() const override { return shdr_.sh_flags; } uint32_t sectionHeaderNameIdx() const override { return shdr_.sh_name; } + std::optional sectionHeaderIndex() const override { return section_index_; } uint64_t sectionOffset() const override { return shdr_.sh_offset; } private: Elf64_Shdr shdr_; + size_t section_index_; }; bool is_elf(const Elf64_Ehdr &ehdr) { return !std::memcmp(ehdr.e_ident, EI_MAGIC, EI_MAGIC_SIZE); } @@ -156,7 +159,8 @@ void Executable::load_fat_binary() { } const char *shstrtab_data = image_.data() + shstrtab.sh_offset; - for (const auto &shdr : section_hdrs) { + for (size_t section_index = 0; section_index < section_hdrs.size(); ++section_index) { + const Elf64_Shdr &shdr = section_hdrs[section_index]; if (shdr.sh_type == SHT_NULL) continue; if (shdr.sh_name >= shstrtab.sh_size) @@ -173,7 +177,8 @@ void Executable::load_fat_binary() { if (sec_name == ".hip_fatbin") { std::unique_ptr sec_data(std::make_unique(shdr.sh_size)); std::memcpy(sec_data.get(), image_.data() + shdr.sh_offset, shdr.sh_size); - auto section = std::make_unique(sec_name, std::move(sec_data), shdr); + auto section = + std::make_unique(sec_name, std::move(sec_data), shdr, section_index); load_hip_fatbin(*section); sections_.emplace_back(std::move(section)); if (!is_valid_) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp index f0faa74b7530..25a659378387 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp @@ -58,10 +58,17 @@ kernel_descriptor_symbol_name(const Elf64_Sym &sym, const char *strtab, size_t s return std::string(name, len - 3); } -[[nodiscard]] std::optional text_vaddr_for_section(uint64_t text_offset, - uint64_t text_size, - const Elf64_Ehdr &ehdr, - const Elf64_Shdr *shdr) { +[[nodiscard]] std::optional +text_vaddr_for_section(uint64_t text_offset, uint64_t text_size, const Elf64_Ehdr &ehdr, + const Elf64_Shdr *shdr, std::optional text_section_index) { + if (text_section_index) { + if (*text_section_index >= ehdr.e_shnum) + return std::nullopt; + const Elf64_Shdr &text = shdr[*text_section_index]; + if (text.sh_type == SHT_NOBITS || text.sh_offset != text_offset || text.sh_size != text_size) + return std::nullopt; + return text.sh_addr; + } for (int i = 0; i < ehdr.e_shnum; ++i) { if (shdr[i].sh_offset == text_offset && shdr[i].sh_size == text_size) return shdr[i].sh_addr; @@ -72,7 +79,8 @@ kernel_descriptor_symbol_name(const Elf64_Sym &sym, const char *strtab, size_t s } // namespace std::vector -scan_kernel_descriptors(std::span image, uint64_t text_offset, uint64_t text_size) { +scan_kernel_descriptors(std::span image, uint64_t text_offset, uint64_t text_size, + std::optional text_section_index) { std::vector out; if (image.size() < sizeof(Elf64_Ehdr)) return out; @@ -83,7 +91,7 @@ scan_kernel_descriptors(std::span image, uint64_t text_offset, ui return out; const auto *shdr = reinterpret_cast(image.data() + ehdr->e_shoff); - auto text_vaddr = text_vaddr_for_section(text_offset, text_size, *ehdr, shdr); + auto text_vaddr = text_vaddr_for_section(text_offset, text_size, *ehdr, shdr, text_section_index); if (!text_vaddr) return out; constexpr uint64_t max_u64 = std::numeric_limits::max(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.h index 187e878c8701..a7c52d755479 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.h @@ -13,7 +13,9 @@ RJ_DIAGNOSTIC_IGNORE_PEDANTIC #include "hsa/AMDHSAKernelDescriptor.h" RJ_DIAGNOSTIC_POP +#include #include +#include #include #include #include @@ -35,7 +37,8 @@ struct KernelDescriptorInfo { /// The single discovery routine shared by DBT translation and DBI; operates on the /// raw, pre-growth image. [[nodiscard]] std::vector -scan_kernel_descriptors(std::span image, uint64_t text_offset, uint64_t text_size); +scan_kernel_descriptors(std::span image, uint64_t text_offset, uint64_t text_size, + std::optional text_section_index = std::nullopt); /// @brief Wavefront size (32 or 64) the launch hardware interprets for @p desc. /// diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp index 1cadc98e77de..97b48c0bbe7b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp @@ -153,13 +153,16 @@ void insert_file_bytes(std::vector &image, Elf64_Ehdr &ehdr, return alignment; } -[[nodiscard]] std::optional find_text_section(std::span shdrs, - uint64_t text_offset, uint64_t text_size) { - for (size_t i = 0; i < shdrs.size(); ++i) { - if (shdrs[i].sh_offset == text_offset && shdrs[i].sh_size == text_size) - return i; - } - return std::nullopt; +[[nodiscard]] std::optional validated_text_section(std::span shdrs, + std::optional text_index, + uint64_t text_offset, + uint64_t text_size) { + if (!text_index || *text_index >= shdrs.size()) + return std::nullopt; + const Elf64_Shdr &text = shdrs[*text_index]; + if (text.sh_type == SHT_NOBITS || text.sh_offset != text_offset || text.sh_size != text_size) + return std::nullopt; + return text_index; } [[nodiscard]] bool target_supports_wave32(rj_code_arch_t arch) { @@ -506,25 +509,42 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e } } -[[nodiscard]] bool relocate_text_symbols(std::vector &image, const Elf64_Ehdr &ehdr, - std::span shdrs, size_t text_index, - uint64_t old_text_size, uint64_t new_text_size, - std::span relocations, - bool require_every_text_symbol_mapped) { - if (relocations.empty()) - return true; - +struct TextPlacementIndex { std::unordered_map target_by_source; - target_by_source.reserve(relocations.size()); + std::unordered_set conflicting_sources; +}; + +/// @brief Build the one source-to-output placement policy used by every text reference. +/// +/// A shared source block can be emitted into multiple kernel-local bodies. The first +/// placement remains useful for unreferenced tooling/debug labels, but a runtime-dereferenced +/// ABS64 symbol or RELATIVE64 addend cannot safely choose among semantically distinct clones. +/// Construct this index once so named and anonymous runtime references cannot drift into +/// different ambiguity policies. +[[nodiscard]] std::optional +build_text_placement_index(uint64_t old_text_size, uint64_t new_text_size, + std::span relocations) { + TextPlacementIndex placements; + placements.target_by_source.reserve(relocations.size()); + placements.conflicting_sources.reserve(relocations.size()); for (const TextOffsetRelocation &relocation : relocations) { if (relocation.source_offset > old_text_size || relocation.target_offset > new_text_size) - return false; - // A helper block can be copied into more than one kernel-local body. ELF - // has only one value for its local label, so retain the first deterministic - // placement. Control-flow fixups remain kernel-local and do not depend on - // this tooling/debug symbol choice. - target_by_source.try_emplace(relocation.source_offset, relocation.target_offset); + return std::nullopt; + auto [it, inserted] = + placements.target_by_source.try_emplace(relocation.source_offset, relocation.target_offset); + if (!inserted && it->second != relocation.target_offset) + placements.conflicting_sources.insert(relocation.source_offset); } + return placements; +} + +[[nodiscard]] bool relocate_text_symbols(std::vector &image, const Elf64_Ehdr &ehdr, + std::span shdrs, size_t text_index, + uint64_t old_text_size, + const TextPlacementIndex &placements, + bool require_every_text_symbol_mapped) { + if (placements.target_by_source.empty()) + return true; const Elf64_Shdr &text = shdrs[text_index]; // Only referenced symbols are correctness-critical. Debug and tooling symbol @@ -535,10 +555,16 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e std::unordered_map> referenced_by_symtab; for (const Elf64_Shdr &relocs : shdrs) { if (relocs.sh_type != SHT_RELA || relocs.sh_entsize != sizeof(Elf64_Rela) || - relocs.sh_link >= shdrs.size() || + relocs.sh_size % sizeof(Elf64_Rela) != 0 || !image_contains_range(image.size(), relocs.sh_offset, relocs.sh_size)) { continue; } + const RocrRelocationSectionMode section_mode = + classify_rocr_relocation_section(ehdr, shdrs, relocs); + if (section_mode == RocrRelocationSectionMode::Malformed) + return false; + if (relocs.sh_link >= shdrs.size()) + continue; const Elf64_Shdr &symtab = shdrs[relocs.sh_link]; if (symtab.sh_entsize != sizeof(Elf64_Sym) || !image_contains_range(image.size(), symtab.sh_offset, symtab.sh_size)) { @@ -548,6 +574,8 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e for (size_t i = 0; i < count; ++i) { Elf64_Rela rela{}; std::memcpy(&rela, image.data() + relocs.sh_offset + i * sizeof(rela), sizeof(rela)); + if (!elf_relocation_place_is_allocated(ehdr, shdrs, relocs, rela.r_offset)) + continue; const uint32_t symbol_index = elf_reloc_sym(rela.r_info); if (symbol_index == 0 || static_cast(symbol_index) * sizeof(Elf64_Sym) + sizeof(Elf64_Sym) > @@ -557,8 +585,11 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e Elf64_Sym symbol{}; std::memcpy(&symbol, image.data() + symtab.sh_offset + symbol_index * sizeof(symbol), sizeof(symbol)); + const TextSymbolRelocationAction action = classify_text_symbol_relocation( + section_mode, rela.r_info, /*has_explicit_addend=*/true, rela.r_addend, symbol); if (symbol.st_shndx == text_index && - elf_symbol_type(symbol.st_info) != kElfSymbolTypeSection) { + (action == TextSymbolRelocationAction::RequiresSymbolMapping || + action == TextSymbolRelocationAction::RequiresExecutableEntry)) { referenced_by_symtab[relocs.sh_link].insert(symbol_index); } } @@ -661,8 +692,10 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e std::memcpy(image.data() + symbol_offset, &symbol, sizeof(symbol)); continue; } - const auto relocated_start = target_by_source.find(source_text_offset); - if (relocated_start == target_by_source.end()) { + if (must_relocate && placements.conflicting_sources.contains(source_text_offset)) + return false; + const auto relocated_start = placements.target_by_source.find(source_text_offset); + if (relocated_start == placements.target_by_source.end()) { if (must_relocate) return false; // The body this symbol names was not emitted, so its old st_value now points into @@ -693,8 +726,8 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e const uint64_t old_size = symbol.st_size; if (old_size <= old_text_size - source_text_offset) { - const auto relocated_end = target_by_source.find(source_text_offset + old_size); - if (relocated_end != target_by_source.end() && + const auto relocated_end = placements.target_by_source.find(source_text_offset + old_size); + if (relocated_end != placements.target_by_source.end() && relocated_end->second >= relocated_start->second) { symbol.st_size = relocated_end->second - relocated_start->second; } @@ -710,35 +743,11 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e [[nodiscard]] bool relocate_relative_text_addends( std::vector &image, const Elf64_Ehdr &ehdr, std::span shdrs, size_t text_index, uint64_t old_text_size, uint64_t new_text_size, - std::span relocations, + const TextPlacementIndex &placements, const std::unordered_map *canonical_code_pointer_placement) { - if (relocations.empty() || ehdr.e_type != ET_DYN) + if (placements.target_by_source.empty() || ehdr.e_type != ET_DYN) return true; - std::unordered_map target_by_source; - target_by_source.reserve(relocations.size()); - // A shared helper block is emitted once per kernel-local scope, so the same - // source offset can appear here with DIFFERENT target placements — and the - // scopes are not interchangeable (e.g. a hardware-LDS clone vs a virtual-LDS - // sidecar clone with different LDS lowering, liveness, and resources). For a - // RELATIVE64 addend (a RUNTIME-DEREFERENCED function pointer) we cannot know - // which clone a given dispatcher belongs to from the source offset alone, so - // collapsing to one clone would let a sidecar dispatch jump into the wrong one. - // Record which source offsets have conflicting placements and fail closed below - // if any such offset is actually referenced by a function-table addend. Source - // offsets that are copied to multiple scopes but never used as a RELATIVE64 - // pointer are harmless (control-flow fixups stay kernel-local), so a conflict - // that is never dereferenced does not reject the translation. - std::unordered_set conflicting_sources; - for (const TextOffsetRelocation &relocation : relocations) { - if (relocation.source_offset > old_text_size || relocation.target_offset > new_text_size) - return false; - auto [it, inserted] = - target_by_source.try_emplace(relocation.source_offset, relocation.target_offset); - if (!inserted && it->second != relocation.target_offset) - conflicting_sources.insert(relocation.source_offset); - } - const Elf64_Shdr &text = shdrs[text_index]; for (const Elf64_Shdr &relocs : shdrs) { if (relocs.sh_type != SHT_RELA || relocs.sh_entsize != sizeof(Elf64_Rela) || @@ -751,6 +760,8 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e const uint64_t rela_offset = relocs.sh_offset + i * sizeof(Elf64_Rela); Elf64_Rela rela{}; std::memcpy(&rela, image.data() + rela_offset, sizeof(rela)); + if (!elf_relocation_place_is_allocated(ehdr, shdrs, relocs, rela.r_offset)) + continue; if (elf_reloc_type(rela.r_info) != R_AMDGPU_RELATIVE64 || rela.r_addend < 0) continue; @@ -776,9 +787,9 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e have_canonical = true; } } - if (conflicting_sources.contains(source_offset) && !have_canonical) + if (placements.conflicting_sources.contains(source_offset) && !have_canonical) return false; - const auto relocated = target_by_source.find(source_offset); + const auto relocated = placements.target_by_source.find(source_offset); // Leaving an in-text addend unchanged would silently preserve a stale PC. // Compatibility was established from the relocation form, but final // materialization must also prove that this exact target was emitted. @@ -788,7 +799,7 @@ void grow_text_function_symbols(std::vector &image, const Elf64_Ehdr &e // canonical map as an independent input, so treating a canonical hit as its own proof would // let a stale or fabricated entry through -- the translator happens to derive both from the // same placements today, which is not something this function can check. - if (relocated == target_by_source.end()) + if (relocated == placements.target_by_source.end()) return false; const uint64_t placement = have_canonical ? canonical_target : relocated->second; // Whichever clone was chosen still has to lie inside the text actually emitted. @@ -854,6 +865,8 @@ void shift_relative_addends_into_moved_sections(std::vector &image, con std::memcpy(&rela, image.data() + place, sizeof(rela)); if (elf_reloc_type(rela.r_info) != R_AMDGPU_RELATIVE64 || rela.r_addend < 0) continue; + if (!elf_relocation_place_is_allocated(ehdr, shdrs, relocs, rela.r_offset)) + continue; const auto addend = static_cast(rela.r_addend); if (addend < old_text_end_vaddr || addend > std::numeric_limits::max() - delta) continue; @@ -861,7 +874,6 @@ void shift_relative_addends_into_moved_sections(std::vector &image, con std::memcpy(image.data() + place, &rela, sizeof(rela)); } } - (void)ehdr; } void shift_relocation_offsets_in_moved_sections(std::vector &image, const Elf64_Ehdr &ehdr, @@ -1033,6 +1045,7 @@ CodeObjectPatcher::CodeObjectPatcher(const AmdGpuCodeObject &obj) text_vaddr_(0), text_tail_size_(0) { auto &text_secs = obj.text_sections(); if (!text_secs.empty()) { + text_section_index_ = text_secs[0]->sectionHeaderIndex(); text_offset_ = text_secs[0]->sectionOffset(); text_size_ = text_secs[0]->size(); text_vaddr_ = text_secs[0]->vaddr(); @@ -1068,7 +1081,8 @@ bool CodeObjectPatcher::has_relocations_within_text() const { auto header = *reinterpret_cast(image_.data()); const auto shdrs = read_section_headers(image_, header); - const auto text_index = find_text_section(shdrs, text_offset_, text_size_); + const auto text_index = + validated_text_section(shdrs, text_section_index_, text_offset_, text_size_); if (!text_index) return false; @@ -1099,15 +1113,20 @@ bool CodeObjectPatcher::has_relocations_within_text() const { for (size_t i = 0; i < count; ++i) { const uint64_t offset = relocs.sh_offset + i * entsize; uint64_t r_offset = 0; + uint64_t r_info = 0; if (is_rela) { Elf64_Rela rela{}; std::memcpy(&rela, image_.data() + offset, sizeof(rela)); r_offset = rela.r_offset; + r_info = rela.r_info; } else { Elf64_Rel rel{}; std::memcpy(&rel, image_.data() + offset, sizeof(rel)); r_offset = rel.r_offset; + r_info = rel.r_info; } + if (elf_relocation_is_inert(r_info)) + continue; const bool in_text = is_rel_object ? r_offset < text_size_ : (r_offset >= text.sh_addr && r_offset < text.sh_addr + text_size_); @@ -1118,6 +1137,52 @@ bool CodeObjectPatcher::has_relocations_within_text() const { return false; } +bool CodeObjectPatcher::has_rocr_rejected_none_relocation() const { + if (image_.size() < sizeof(Elf64_Ehdr)) + return false; + + const auto header = *reinterpret_cast(image_.data()); + const auto shdrs = section_headers(); + if (shdrs.empty()) + return false; + + for (const Elf64_Shdr &relocs : shdrs) { + if (relocs.sh_type != SHT_RELA || relocs.sh_entsize != sizeof(Elf64_Rela) || + relocs.sh_size % sizeof(Elf64_Rela) != 0 || + !image_contains_range(image_.size(), relocs.sh_offset, relocs.sh_size)) { + continue; + } + const RocrRelocationSectionMode section_mode = + classify_rocr_relocation_section(header, shdrs, relocs); + if (section_mode == RocrRelocationSectionMode::Malformed) + continue; + const size_t count = relocs.sh_size / sizeof(Elf64_Rela); + for (size_t relocation_index = 0; relocation_index < count; ++relocation_index) { + Elf64_Rela relocation{}; + std::memcpy(&relocation, + image_.data() + relocs.sh_offset + relocation_index * sizeof(relocation), + sizeof(relocation)); + if (classify_rocr_none_relocation(section_mode, relocation.r_info) == + RocrNoneRelocationAction::Rejected) { + return true; + } + } + } + return false; +} + +bool CodeObjectPatcher::has_malformed_rocr_relocation_section() const { + if (image_.size() < sizeof(Elf64_Ehdr)) + return false; + + const auto header = *reinterpret_cast(image_.data()); + const auto shdrs = section_headers(); + return std::ranges::any_of(shdrs, [&](const Elf64_Shdr §ion) { + return classify_rocr_relocation_section(header, shdrs, section) == + RocrRelocationSectionMode::Malformed; + }); +} + bool CodeObjectPatcher::has_unsupported_relocation_to_text() const { if (text_size_ == 0) return false; @@ -1126,7 +1191,8 @@ bool CodeObjectPatcher::has_unsupported_relocation_to_text() const { auto header = *reinterpret_cast(image_.data()); const auto shdrs = read_section_headers(image_, header); - const auto text_index = find_text_section(shdrs, text_offset_, text_size_); + const auto text_index = + validated_text_section(shdrs, text_section_index_, text_offset_, text_size_); if (!text_index) return false; @@ -1138,8 +1204,8 @@ bool CodeObjectPatcher::has_unsupported_relocation_to_text() const { const uint64_t text_addr_hi = text.sh_addr + text_size_; // Return the referenced symbol only when it is defined in .text. Keeping the - // complete symbol is necessary because ordinary named symbols and STT_SECTION - // symbols require different relocation strategies. + // complete symbol is necessary because the shared relocation policy also + // classifies how the runtime derives its address. auto text_symbol = [&](const Elf64_Shdr &symtab, uint32_t sym_index) -> std::optional { if (symtab.sh_entsize != sizeof(Elf64_Sym)) return std::nullopt; @@ -1160,42 +1226,49 @@ bool CodeObjectPatcher::has_unsupported_relocation_to_text() const { continue; if (!image_contains_range(image_.size(), relocs.sh_offset, relocs.sh_size)) continue; + const bool is_rela = relocs.sh_type == SHT_RELA; + const size_t entsize = is_rela ? sizeof(Elf64_Rela) : sizeof(Elf64_Rel); + if (relocs.sh_entsize != entsize || relocs.sh_size % entsize != 0) + continue; + const RocrRelocationSectionMode section_mode = + classify_rocr_relocation_section(header, shdrs, relocs); + if (section_mode == RocrRelocationSectionMode::Malformed) + continue; // sh_link names the symbol table this relocation section indexes into. if (relocs.sh_link >= shdrs.size()) continue; const Elf64_Shdr &symtab = shdrs[relocs.sh_link]; - const bool is_rela = relocs.sh_type == SHT_RELA; - const size_t entsize = is_rela ? sizeof(Elf64_Rela) : sizeof(Elf64_Rel); - if (relocs.sh_entsize != entsize) - continue; const size_t count = relocs.sh_size / entsize; for (size_t i = 0; i < count; ++i) { const uint64_t offset = relocs.sh_offset + i * entsize; + Elf64_Rela rela{}; + uint64_t r_offset = 0; uint64_t r_info = 0; - int64_t r_addend = 0; if (is_rela) { - Elf64_Rela rela{}; std::memcpy(&rela, image_.data() + offset, sizeof(rela)); + r_offset = rela.r_offset; r_info = rela.r_info; - r_addend = rela.r_addend; } else { Elf64_Rel rel{}; std::memcpy(&rel, image_.data() + offset, sizeof(rel)); r_info = rel.r_info; + r_offset = rel.r_offset; } + if (classify_rocr_none_relocation(section_mode, r_info) != + RocrNoneRelocationAction::NotNone) { + continue; + } + if (!elf_relocation_place_is_allocated(header, shdrs, relocs, r_offset)) + continue; const uint32_t sym_index = elf_reloc_sym(r_info); if (sym_index != 0) { const auto symbol = text_symbol(symtab, sym_index); if (!symbol) continue; - // A zero-addend RELA reference to an ordinary text symbol follows the - // relocated symbol value written by relocate_text_symbols(). A section - // symbol leaves the source offset in the addend, while REL keeps an - // implicit addend at the relocation place; neither form can be repaired - // safely without interpreting the individual relocation type. - if (!is_rela || elf_symbol_type(symbol->st_info) == kElfSymbolTypeSection || - r_addend != 0) { + const TextSymbolRelocationAction action = + classify_text_symbol_relocation(section_mode, r_info, is_rela, rela.r_addend, *symbol); + if (action == TextSymbolRelocationAction::Unsupported) { return true; } continue; @@ -1206,7 +1279,7 @@ bool CodeObjectPatcher::has_unsupported_relocation_to_text() const { // replace_text() remaps an in-text addend exactly. Other symbol-zero forms // provide no generic way to identify a .text target here. if (is_rela && elf_reloc_type(r_info) == R_AMDGPU_RELATIVE64) { - const uint64_t target = static_cast(r_addend); + const uint64_t target = static_cast(rela.r_addend); if (target >= text_addr_lo && target < text_addr_hi) continue; } @@ -1233,15 +1306,22 @@ bool CodeObjectPatcher::replace_text( return false; if (!image_contains_range(image_.size(), text_offset_, text_size_)) return false; + if (has_malformed_rocr_relocation_section() || has_rocr_rejected_none_relocation()) + return false; if (!text_relocations.empty() && has_unsupported_relocation_to_text()) return false; + const auto text_placements = + build_text_placement_index(text_size_, new_text.size(), text_relocations); + if (!text_placements) + return false; auto *ehdr = reinterpret_cast(image_.data()); auto header = *ehdr; auto shdrs = section_headers(); auto phdrs = read_program_headers(image_, header); - const auto text_index = find_text_section(shdrs, text_offset_, text_size_); + const auto text_index = + validated_text_section(shdrs, text_section_index_, text_offset_, text_size_); if (!text_index) { assert(false && "text section header not found"); return false; @@ -1381,12 +1461,12 @@ bool CodeObjectPatcher::replace_text( sizeof(delta)); } shdrs[*text_index].sh_size = new_text.size(); - if (!relocate_text_symbols(image_, header, shdrs, *text_index, text_size_, new_text.size(), - text_relocations, require_every_text_symbol_mapped)) { + if (!relocate_text_symbols(image_, header, shdrs, *text_index, text_size_, *text_placements, + require_every_text_symbol_mapped)) { return false; } if (!relocate_relative_text_addends(image_, header, shdrs, *text_index, text_size_, - new_text.size(), text_relocations, + new_text.size(), *text_placements, canonical_code_pointer_placement)) { return false; } @@ -1465,7 +1545,8 @@ CodeObjectPatcher::append_sidecar_descriptor_translations( auto shdrs = read_section_headers(image_, header); auto phdrs = read_program_headers(image_, header); - const auto text_index = find_text_section(shdrs, text_offset_, text_size_); + const auto text_index = + validated_text_section(shdrs, text_section_index_, text_offset_, text_size_); if (!text_index) return std::nullopt; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.h index 4807de20cc58..206e3c3cef02 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.h @@ -101,17 +101,34 @@ class CodeObjectPatcher { bool require_every_text_symbol_mapped = false, const std::unordered_map *canonical_code_pointer_placement = nullptr); - /// @brief True if any relocation's place (r_offset) falls inside .text. + /// @brief True if any non-inert relocation's place (r_offset) falls inside .text. /// /// @details DBT compacts/expands/moves instructions within .text but does not /// remap relocation places that land in .text — replace_text() only shifts /// relocation offsets for whole sections moved *after* .text. An in-.text /// relocation would therefore be applied to the wrong translated bytes. + /// R_AMDGPU_NONE performs no write at its relocation place. Runtime acceptance + /// of that record is checked separately by has_rocr_rejected_none_relocation(). /// BinaryTranslator uses this to fail closed instead of miscompiling. Real /// AMDHSA kernel code objects carry no such relocations, so this rejects only /// genuinely unsupported inputs. [[nodiscard]] bool has_relocations_within_text() const; + /// @brief True if ROCr cannot resolve an ET_DYN SHT_RELA section target. + /// + /// @details ROCr accepts section zero as the target-less dynamic form and a + /// valid non-null section as an explicit target. A nonzero SHT_NULL target or + /// an out-of-range sh_info fails before relocation records are dispatched. + [[nodiscard]] bool has_malformed_rocr_relocation_section() const; + + /// @brief True if ROCr rejects an R_AMDGPU_NONE record before DBT can rewrite the image. + /// + /// @details Target-less SHT_RELA sections in ET_DYN code objects are processed as + /// dynamic relocations, where ROCr has no R_AMDGPU_NONE case. Detect those records by + /// section mode and type alone, before consulting their place or symbol metadata. + /// Malformed section metadata is owned by has_malformed_rocr_relocation_section(). + [[nodiscard]] bool has_rocr_rejected_none_relocation() const; + /// @brief True if any relocation references .text in a form DBT cannot remap. /// /// @details DBT can remap zero-addend RELA references to ordinary symbols @@ -189,6 +206,7 @@ class CodeObjectPatcher { private: std::vector image_; + std::optional text_section_index_; uint64_t text_offset_; uint64_t text_size_; uint64_t text_vaddr_; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/relocation_function_table.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/relocation_function_table.cpp index 05648538c519..6687711785a2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/relocation_function_table.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/relocation_function_table.cpp @@ -574,6 +574,8 @@ discover_relocation_function_tables(const AmdGpuCodeObject &object) { Elf64_Rela rela{}; if (!read_object(image, relocations.sh_offset + index * sizeof(Elf64_Rela), rela)) continue; + if (!elf_relocation_place_is_allocated(ehdr, sections, relocations, rela.r_offset)) + continue; const uint32_t type = elf_reloc_type(rela.r_info); if (type == R_AMDGPU_RELATIVE64) { if (rela.r_addend < 0) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp index b9e9d82d5d1c..ad12dd542b06 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp @@ -581,6 +581,8 @@ void trace_virtual_lds_kernarg(uint64_t packet_id, const void *kernarg, size_t s return "resource-limit"; case DiagnosticKind::KernelSkipped: return "kernel-skipped"; + case DiagnosticKind::ResidualRewrite: + return "residual-rewrite"; } return "unknown"; } @@ -592,6 +594,9 @@ void print_diagnostic(FILE *stream, const TranslationDiagnostic &diagnostic) { if (diagnostic.guest_offset) std::fprintf(stream, " .text+0x%llx", static_cast(*diagnostic.guest_offset)); + if (diagnostic.output_offset) + std::fprintf(stream, " output:.text+0x%llx", + static_cast(*diagnostic.output_offset)); if (!diagnostic.mnemonic.empty()) std::fprintf(stream, " %s", diagnostic.mnemonic.c_str()); std::fprintf(stream, ": %s\n", diagnostic.message.c_str()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h index 102ca66ceda0..e5aa422cf3d6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA1_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace cdna1 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 4; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h index 67093899267c..f2444ea7d812 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA2_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace cdna2 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 4; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h index 3d8443912408..063fee1de4be 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA3_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace cdna3 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 4; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h index 9da89bb88bb7..5da96952c00e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA4_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace cdna4 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 4; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h index fe498bc08861..984a4d721cdc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA5_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace cdna5 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 4; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h index 389dc11f5ffc..59b4c77a7b8b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA1_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace rdna1 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 3; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h index e597f267d414..0956717cd90b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA2_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace rdna2 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 3; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h index 44d8133ce391..102da776edc3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA3_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace rdna3 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 3; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h index bd43d2acc726..0ba661ab2a80 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA3_5_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace rdna3_5 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 3; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h index 642742ca182d..66e82569097b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h @@ -8,6 +8,8 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA4_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/machine_insts.h" +#include +#include #include namespace rocjitsu { @@ -18,6 +20,7 @@ namespace rdna4 { class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 3; static std::unique_ptr decode(const MachineInst *opcode); }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h index 12818f9ac29e..a70babaa65f8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h @@ -6,6 +6,7 @@ #include "rocjitsu/isa/instruction.h" +#include #include #include @@ -16,6 +17,7 @@ using DecodeFn = std::unique_ptr (*)(uint32_t); class Decoder { public: + static constexpr std::size_t kMaxInstructionWords = 1; static std::unique_ptr decode(uint32_t instr); static std::unique_ptr decode(const uint32_t *instr) { return instr == nullptr ? nullptr : decode(*instr); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h index 2d6829a5e118..799fe3de5d05 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h @@ -12,6 +12,7 @@ #include "rocjitsu/isa/execution_backend.h" #include "util/arena_alloc.h" +#include #include #include #include @@ -40,6 +41,11 @@ class Decoder { /// @returns Decoded Instruction pointer (pool or heap allocated). virtual Instruction *decode(const rj_code_binary_inst_t *inst) = 0; + /// @brief Maximum encoded instruction width and decode lookahead, in 32-bit words. + /// @returns A nonzero bound covering both every raw-pointer read and the size of every + /// successfully decoded instruction. + virtual std::size_t max_instruction_words() const = 0; + /// @brief Decode a binary instruction and record its source text offset. /// /// @details The generated ISA decoders construct instructions from raw @@ -101,6 +107,8 @@ template class IsaDecoder final : public Decoder { return result.release(); } + std::size_t max_instruction_words() const override { return Isa::Decoder::kMaxInstructionWords; } + private: const IsaExecutionBackend *execution_backend_; }; diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 03acaaeaaaf1..28880d95d410 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -201,6 +201,8 @@ enum class TestOpcode : uint32_t { class TestDecoder : public Decoder { public: + std::size_t max_instruction_words() const override { return 1; } + Instruction *decode(const rj_code_binary_inst_t *inst) override { auto op = static_cast(*inst); switch (op) { diff --git a/emulation/rocjitsu/tests/code/amdgpu_code_object_test.cpp b/emulation/rocjitsu/tests/code/amdgpu_code_object_test.cpp index a3b23a2a0515..7f3a094123bd 100644 --- a/emulation/rocjitsu/tests/code/amdgpu_code_object_test.cpp +++ b/emulation/rocjitsu/tests/code/amdgpu_code_object_test.cpp @@ -16,6 +16,7 @@ #include +#include #include #include #include @@ -170,6 +171,18 @@ make_elf_with_kds(const std::vector> &kernels) return image; } +void set_section_type_and_offset(std::vector &image, size_t section_index, uint32_t type, + uint64_t offset) { + Elf64_Ehdr ehdr{}; + std::memcpy(&ehdr, image.data(), sizeof(ehdr)); + Elf64_Shdr shdr{}; + const size_t shdr_offset = ehdr.e_shoff + section_index * sizeof(Elf64_Shdr); + std::memcpy(&shdr, image.data() + shdr_offset, sizeof(shdr)); + shdr.sh_type = type; + shdr.sh_offset = offset; + std::memcpy(image.data() + shdr_offset, &shdr, sizeof(shdr)); +} + // CDNA: a granulated field of 0 encodes a real 8-SGPR allocation. TEST(AmdGpuCodeObjectSgpr, CdnaGranulatedZeroIsEightSgprs) { const auto image = make_elf_with_kds({{"k", 0}}); @@ -217,5 +230,36 @@ TEST(AmdGpuCodeObjectSgpr, NoKernelDescriptorReturnsNullopt) { EXPECT_FALSE(obj.min_kernel_sgpr_count(ROCJITSU_CODE_ARCH_CDNA2).has_value()); } +TEST(AmdGpuCodeObjectSections, RetainsAllocatedExecutableNobitsForLayoutValidation) { + std::vector image = make_elf_with_kds({}); + set_section_type_and_offset(image, 1, SHT_NOBITS, image.size() + 0x1000); + + AmdGpuCodeObject obj(image.data(), image.size()); + ASSERT_TRUE(obj.is_valid()); + EXPECT_TRUE(obj.text_sections().empty()); + ASSERT_EQ(obj.allocated_executable_sections().size(), 1u); + const Section *section = obj.allocated_executable_sections().front(); + ASSERT_NE(section, nullptr); + EXPECT_EQ(section->name(), ".text"); + EXPECT_EQ(section->sectionHeaderIndex(), std::optional(1)); + EXPECT_EQ(section->data(), nullptr); + EXPECT_TRUE(std::ranges::none_of(obj.all_sections(), [](const auto &candidate) { + return candidate != nullptr && candidate->name() == ".text"; + })); +} + +TEST(AmdGpuCodeObjectSections, ContinuesToSkipOrdinaryNobits) { + std::vector image = make_elf_with_kds({}); + set_section_type_and_offset(image, 2, SHT_NOBITS, image.size() + 0x1000); + + AmdGpuCodeObject obj(image.data(), image.size()); + ASSERT_TRUE(obj.is_valid()); + ASSERT_EQ(obj.text_sections().size(), 1u); + EXPECT_TRUE(obj.rodata_sections().empty()); + EXPECT_TRUE(std::ranges::none_of(obj.all_sections(), [](const auto §ion) { + return section != nullptr && section->name() == ".rodata"; + })); +} + } // namespace } // namespace rocjitsu diff --git a/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp b/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp index 9f244859ca63..c34ea1d5ff7d 100644 --- a/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp +++ b/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -344,6 +345,35 @@ void edit_first_relative64(std::vector &image, FAIL() << "no R_AMDGPU_RELATIVE64 relocation found to edit"; } +void append_nonallocated_relocations(std::vector &image, + std::span relocations) { + Elf64_Ehdr ehdr{}; + std::memcpy(&ehdr, image.data(), sizeof(ehdr)); + std::vector sections(ehdr.e_shnum); + std::memcpy(sections.data(), image.data() + ehdr.e_shoff, sections.size() * sizeof(Elf64_Shdr)); + + const uint64_t relocation_offset = ehdr.e_shoff; + const auto *bytes = reinterpret_cast(relocations.data()); + image.insert(image.begin() + static_cast(relocation_offset), bytes, + bytes + relocations.size_bytes()); + + Elf64_Shdr metadata_relocations{}; + metadata_relocations.sh_type = SHT_RELA; + metadata_relocations.sh_offset = relocation_offset; + metadata_relocations.sh_size = relocations.size_bytes(); + metadata_relocations.sh_link = 4; + metadata_relocations.sh_info = ehdr.e_shstrndx; + metadata_relocations.sh_addralign = alignof(Elf64_Rela); + metadata_relocations.sh_entsize = sizeof(Elf64_Rela); + sections.push_back(metadata_relocations); + + ehdr.e_shoff += relocations.size_bytes(); + ehdr.e_shnum = static_cast(sections.size()); + image.resize(ehdr.e_shoff + sections.size() * sizeof(Elf64_Shdr)); + std::memcpy(image.data(), &ehdr, sizeof(ehdr)); + std::memcpy(image.data() + ehdr.e_shoff, sections.data(), sections.size() * sizeof(Elf64_Shdr)); +} + TEST(RelocationFunctionTable, DiscoversGotReferencedRelativeTextPointers) { const auto image = make_relocation_function_table_elf(); const AmdGpuCodeObject object(image.data(), image.size()); @@ -361,6 +391,26 @@ TEST(RelocationFunctionTable, DiscoversGotReferencedRelativeTextPointers) { EXPECT_EQ(tables[0].entries[1].target_text_offset, 12u); } +TEST(RelocationFunctionTable, IgnoresExplicitNonAllocatedRelocations) { + auto image = make_relocation_function_table_elf(); + const std::array metadata_relocations = { + Elf64_Rela{.r_offset = 0x2008u, + .r_info = relocation_info(0, R_AMDGPU_RELATIVE64), + .r_addend = 0x1008}, + Elf64_Rela{.r_offset = 0x3008u, .r_info = relocation_info(1, R_AMDGPU_ABS64), .r_addend = 0}, + }; + append_nonallocated_relocations(image, metadata_relocations); + const AmdGpuCodeObject object(image.data(), image.size()); + ASSERT_TRUE(object.is_valid()); + + const auto tables = discover_relocation_function_tables(object); + ASSERT_EQ(tables.size(), 1u); + EXPECT_EQ(tables[0].got_slot_vaddrs, std::vector{0x3000u}); + ASSERT_EQ(tables[0].entries.size(), 2u); + EXPECT_EQ(tables[0].entries[0].slot_vaddr, 0x2000u); + EXPECT_EQ(tables[0].entries[1].slot_vaddr, 0x2010u); +} + TEST(RelocationFunctionTable, DiscoveryRejectsMisalignedTableSlot) { // The first table entry's RELATIVE64 relocation points at table_vaddr + 4, which // is not a multiple of the 8-byte pointer stride from the table base. Discovery diff --git a/emulation/rocjitsu/tests/dbt/gfx1250_b0_to_a0_library_test.cpp b/emulation/rocjitsu/tests/dbt/gfx1250_b0_to_a0_library_test.cpp index 4f46d5230a3f..1ff26cc07efe 100644 --- a/emulation/rocjitsu/tests/dbt/gfx1250_b0_to_a0_library_test.cpp +++ b/emulation/rocjitsu/tests/dbt/gfx1250_b0_to_a0_library_test.cpp @@ -201,6 +201,7 @@ TEST(Gfx1250B0ToA0Library, FansOutRequiredWorkAsCallbackViews) { .severity = rocjitsu::DiagnosticSeverity::Error, .kind = rocjitsu::DiagnosticKind::ExpandMissing, .guest_offset = 8, + .output_offset = std::nullopt, .mnemonic = "v_test", .message = "primary diagnostic", .required_work = {"first required step", "second required step"}, diff --git a/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp b/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp index 1990d69d0ca2..be2407072ba4 100644 --- a/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp +++ b/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp @@ -9,6 +9,7 @@ #endif #include "rocjitsu/code/amdgpu_code_object.h" +#include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/basic_block.h" #include "rocjitsu/code/dbt/binary_translator.h" #include "rocjitsu/code/dbt/processor_revision.h" @@ -19,7 +20,9 @@ #include #include +#include #include +#include #include #include #include @@ -30,6 +33,40 @@ std::string relocation_table_kernel_path() { return std::string(KERNEL_DIR) + "/relocation_function_table_dispatch.o"; } +void append_nonallocated_relative64(std::vector &image, uint64_t slot_vaddr, + uint64_t target_vaddr) { + rocjitsu::Elf64_Ehdr ehdr{}; + std::memcpy(&ehdr, image.data(), sizeof(ehdr)); + std::vector sections(ehdr.e_shnum); + std::memcpy(sections.data(), image.data() + ehdr.e_shoff, + sections.size() * sizeof(rocjitsu::Elf64_Shdr)); + + const uint64_t relocation_offset = ehdr.e_shoff; + rocjitsu::Elf64_Rela relocation{}; + relocation.r_offset = slot_vaddr; + relocation.r_info = rocjitsu::R_AMDGPU_RELATIVE64; + relocation.r_addend = static_cast(target_vaddr); + image.insert(image.begin() + static_cast(relocation_offset), + reinterpret_cast(&relocation), + reinterpret_cast(&relocation) + sizeof(relocation)); + + rocjitsu::Elf64_Shdr metadata_relocations{}; + metadata_relocations.sh_type = rocjitsu::SHT_RELA; + metadata_relocations.sh_offset = relocation_offset; + metadata_relocations.sh_size = sizeof(relocation); + metadata_relocations.sh_info = ehdr.e_shstrndx; + metadata_relocations.sh_addralign = alignof(rocjitsu::Elf64_Rela); + metadata_relocations.sh_entsize = sizeof(rocjitsu::Elf64_Rela); + sections.push_back(metadata_relocations); + + ehdr.e_shoff += sizeof(relocation); + ehdr.e_shnum = static_cast(sections.size()); + image.resize(ehdr.e_shoff + sections.size() * sizeof(rocjitsu::Elf64_Shdr)); + std::memcpy(image.data(), &ehdr, sizeof(ehdr)); + std::memcpy(image.data() + ehdr.e_shoff, sections.data(), + sections.size() * sizeof(rocjitsu::Elf64_Shdr)); +} + } // namespace TEST(RelocationFunctionTableHip, TranslatesEightWayDeviceDispatch) { @@ -89,3 +126,39 @@ TEST(RelocationFunctionTableHip, TranslatesEightWayDeviceDispatch) { for (const auto &entry : translated_tables[0].entries) EXPECT_LT(entry.target_text_offset, translated_text_size); } + +TEST(RelocationFunctionTableHip, TranslationIgnoresExplicitNonAllocatedRelocation) { + rocjitsu::Executable executable(relocation_table_kernel_path()); + ASSERT_TRUE(executable.is_valid()) << "failed to load relocation table HIP fixture"; + const auto *source = executable.code_object(ROCJITSU_CODE_TARGET_GFX1250, 0); + ASSERT_NE(source, nullptr); + ASSERT_EQ(source->text_sections().size(), 1u); + + const auto source_tables = rocjitsu::discover_relocation_function_tables(*source); + ASSERT_EQ(source_tables.size(), 1u); + ASSERT_EQ(source_tables[0].entries.size(), 8u); + const uint64_t invalid_mid_instruction_target = source->text_sections()[0]->vaddr() + 2; + const auto *source_bytes = reinterpret_cast(source->image_data()); + std::vector image(source_bytes, source_bytes + source->image_size()); + append_nonallocated_relative64(image, source_tables[0].entries[0].slot_vaddr, + invalid_mid_instruction_target); + + rocjitsu::AmdGpuCodeObject augmented(image.data(), image.size()); + ASSERT_TRUE(augmented.is_valid()); + const auto augmented_tables = rocjitsu::discover_relocation_function_tables(augmented); + ASSERT_EQ(augmented_tables.size(), 1u); + EXPECT_EQ(augmented_tables[0].entries.size(), 8u); + + rocjitsu::BinaryTranslatorOptions options; + options.input_revision = rocjitsu::ProcessorRevision::Gfx1250B0; + options.output_revision = rocjitsu::ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + options); + const auto result = translator.translate(augmented); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); +} diff --git a/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp b/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp index 11fef895af9f..4f82253a89b8 100644 --- a/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp +++ b/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include #include #include @@ -47,6 +49,29 @@ static void write_bytes_for_test(std::vector &image, uint64_t offset, c assert(size <= image.size() - offset); std::memcpy(image.data() + offset, src, size); } + +uint16_t append_elf_section_for_test(std::vector &image, Elf64_Shdr section, + std::span contents) { + auto header = read_elf_struct_for_test(image, 0); + auto sections = read_elf_array_for_test(image, header.e_shoff, header.e_shnum); + assert(header.e_shnum < std::numeric_limits::max()); + assert(header.e_shoff <= image.size()); + + const uint64_t contents_offset = header.e_shoff; + image.insert(image.begin() + static_cast(contents_offset), contents.begin(), + contents.end()); + section.sh_offset = contents_offset; + section.sh_size = contents.size(); + sections.push_back(section); + + header.e_shoff += contents.size(); + header.e_shnum = static_cast(sections.size()); + image.resize(header.e_shoff + sections.size() * sizeof(Elf64_Shdr)); + write_elf_struct_for_test(image, 0, header); + write_bytes_for_test(image, header.e_shoff, sections.data(), + sections.size() * sizeof(Elf64_Shdr)); + return static_cast(sections.size() - 1); +} constexpr size_t kKernelDescriptorEntryOffset = offsetof(TestKernelDescriptor, kernel_code_entry_byte_offset); void write_kernel_descriptor_entry_offset(void *descriptor, int64_t entry_offset) { @@ -308,7 +333,6 @@ bool has_error_containing(const TranslatedCodeObject &result, DiagnosticKind kin diagnostic.message.find(message) != std::string::npos; }); } - bool has_warning_at(const TranslatedCodeObject &result, DiagnosticKind kind, std::string_view message, uint64_t guest_offset) { return std::any_of(result.diagnostics.begin(), result.diagnostics.end(), @@ -519,13 +543,15 @@ std::vector make_minimal_amdgpu_elf_with_two_kernels_and_function_point return image; } -std::vector -make_minimal_amdgpu_elf_with_two_kernel_descriptors(const std::vector &text_words) { +std::vector make_minimal_amdgpu_elf_with_two_kernel_descriptors( + const std::vector &text_words, + std::optional runtime_text_reference) { constexpr uint64_t text_offset = 0x100; constexpr uint64_t text_vaddr = 0x1100; const uint64_t text_size = text_words.size() * sizeof(uint32_t); constexpr uint64_t load_align = 0x1000; - constexpr uint64_t rodata_size = 2 * kKernelDescriptorSize; + const uint64_t rodata_size = + 2 * kKernelDescriptorSize + (runtime_text_reference ? sizeof(uint64_t) : 0); std::vector shstrtab{'\0'}; const uint32_t text_name = add_elf_name(shstrtab, ".text"); @@ -533,10 +559,15 @@ make_minimal_amdgpu_elf_with_two_kernel_descriptors(const std::vector const uint32_t symtab_name = add_elf_name(shstrtab, ".symtab"); const uint32_t strtab_name = add_elf_name(shstrtab, ".strtab"); const uint32_t shstrtab_name = add_elf_name(shstrtab, ".shstrtab"); + const uint32_t rela_name = runtime_text_reference ? add_elf_name(shstrtab, ".rela.dyn") : 0; std::vector strtab{'\0'}; const uint32_t kernel0_name = add_elf_name(strtab, "kernel0.kd"); const uint32_t kernel1_name = add_elf_name(strtab, "kernel1.kd"); + const uint32_t target_name = runtime_text_reference && runtime_text_reference->relocation == + TestRuntimeTextRelocation::Abs64 + ? add_elf_name(strtab, "runtime_text_target") + : 0; // The kernel descriptors require 8-byte alignment (tests reinterpret_cast the // .rodata bytes to TestKernelDescriptor). An odd text_words count leaves @@ -547,10 +578,14 @@ make_minimal_amdgpu_elf_with_two_kernel_descriptors(const std::vector const uint64_t rodata_vaddr = align_up_for_test(text_vaddr + text_size, 8) + load_align; const uint64_t strtab_offset = rodata_offset + rodata_size; const uint64_t symtab_offset = align_up_for_test(strtab_offset + strtab.size(), 8); - constexpr size_t sym_count = 3; - const uint64_t shstrtab_offset = symtab_offset + sym_count * sizeof(Elf64_Sym); + const size_t sym_count = runtime_text_reference && runtime_text_reference->relocation == + TestRuntimeTextRelocation::Abs64 + ? 4 + : 3; + const uint64_t rela_offset = symtab_offset + sym_count * sizeof(Elf64_Sym); + const uint64_t shstrtab_offset = rela_offset + (runtime_text_reference ? sizeof(Elf64_Rela) : 0); const uint64_t shoff = align_up_for_test(shstrtab_offset + shstrtab.size(), 8); - constexpr uint16_t section_count = 6; + const uint16_t section_count = runtime_text_reference ? 7 : 6; constexpr uint16_t phdr_count = 2; std::vector image(shoff + section_count * sizeof(Elf64_Shdr), 0); @@ -605,7 +640,7 @@ make_minimal_amdgpu_elf_with_two_kernel_descriptors(const std::vector std::memcpy(image.data() + rodata_offset, descriptors.data(), descriptors.size()); std::memcpy(image.data() + strtab_offset, strtab.data(), strtab.size()); - std::array syms{}; + std::vector syms(sym_count); syms[1].st_name = kernel0_name; syms[1].st_info = elf_symbol_info(kElfSymbolBindGlobal, kElfSymbolTypeObject); syms[1].st_shndx = 2; @@ -616,11 +651,33 @@ make_minimal_amdgpu_elf_with_two_kernel_descriptors(const std::vector syms[2].st_shndx = 2; syms[2].st_value = rodata_vaddr + kKernelDescriptorSize; syms[2].st_size = kKernelDescriptorSize; + if (runtime_text_reference && + runtime_text_reference->relocation == TestRuntimeTextRelocation::Abs64) { + syms[3].st_name = target_name; + syms[3].st_info = elf_symbol_info(kElfSymbolBindGlobal, kElfSymbolTypeFunc); + syms[3].st_shndx = 1; + syms[3].st_value = text_vaddr + runtime_text_reference->target_text_offset; + syms[3].st_size = sizeof(uint32_t); + } std::memcpy(image.data() + symtab_offset, syms.data(), syms.size() * sizeof(Elf64_Sym)); + if (runtime_text_reference) { + Elf64_Rela relocation{}; + relocation.r_offset = rodata_vaddr + 2 * kKernelDescriptorSize; + if (runtime_text_reference->relocation == TestRuntimeTextRelocation::Abs64) { + relocation.r_info = (static_cast(3) << 32) | + static_cast(runtime_text_reference->relocation_type); + } else { + relocation.r_info = R_AMDGPU_RELATIVE64; + relocation.r_addend = + static_cast(text_vaddr + runtime_text_reference->target_text_offset); + } + std::memcpy(image.data() + rela_offset, &relocation, sizeof(relocation)); + } + std::memcpy(image.data() + shstrtab_offset, shstrtab.data(), shstrtab.size()); - std::array shdrs{}; + std::vector shdrs(section_count); shdrs[1].sh_name = text_name; shdrs[1].sh_type = SHT_PROGBITS; shdrs[1].sh_flags = SHF_ALLOC | SHF_EXECINSTR; @@ -658,6 +715,17 @@ make_minimal_amdgpu_elf_with_two_kernel_descriptors(const std::vector shdrs[5].sh_size = shstrtab.size(); shdrs[5].sh_addralign = 1; + if (runtime_text_reference) { + shdrs[6].sh_name = rela_name; + shdrs[6].sh_type = SHT_RELA; + shdrs[6].sh_offset = rela_offset; + shdrs[6].sh_size = sizeof(Elf64_Rela); + shdrs[6].sh_link = 3; + shdrs[6].sh_info = SHN_UNDEF; + shdrs[6].sh_addralign = alignof(Elf64_Rela); + shdrs[6].sh_entsize = sizeof(Elf64_Rela); + } + std::memcpy(image.data() + shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); return image; } diff --git a/emulation/rocjitsu/tests/dbt/support/translate_test_support.h b/emulation/rocjitsu/tests/dbt/support/translate_test_support.h index 97885ea2cdec..4d7dcd8080d8 100644 --- a/emulation/rocjitsu/tests/dbt/support/translate_test_support.h +++ b/emulation/rocjitsu/tests/dbt/support/translate_test_support.h @@ -7,6 +7,7 @@ /// @brief Shared fixtures for CPU-only DBT translation tests. #include "rocjitsu/base/rj_compiler.h" +#include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/dbt/binary_translator.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/instruction.h" @@ -20,6 +21,7 @@ RJ_DIAGNOSTIC_POP #include #include #include +#include #include #include @@ -28,10 +30,23 @@ namespace rocjitsu::test_support { using TestKernelDescriptor = rocr::llvm::amdhsa::kernel_descriptor_t; inline constexpr size_t kKernelDescriptorSize = sizeof(TestKernelDescriptor); +enum class TestRuntimeTextRelocation : uint8_t { + Abs64, + Relative64, +}; + +struct TestRuntimeTextReference { + TestRuntimeTextRelocation relocation = TestRuntimeTextRelocation::Abs64; + uint32_t relocation_type = R_AMDGPU_ABS64; + uint64_t target_text_offset = 0; +}; + void write_kernel_descriptor_entry_offset(void *descriptor, int64_t entry_offset); [[nodiscard]] int64_t read_kernel_descriptor_entry_offset(const void *descriptor); [[nodiscard]] TestKernelDescriptor read_kernel_descriptor_for_test(const void *descriptor); void write_kernel_descriptor_for_test(void *descriptor, const TestKernelDescriptor &kd); +uint16_t append_elf_section_for_test(std::vector &image, Elf64_Shdr section, + std::span contents); [[nodiscard]] std::vector make_minimal_amdgpu_elf_with_descriptor_after_text( const std::vector &text_words, @@ -60,7 +75,8 @@ struct TestTextFunction { const std::vector &functions); [[nodiscard]] std::vector make_minimal_amdgpu_elf_with_two_kernel_descriptors( - const std::vector &text_words = {0xBF810000u, 0xBF810000u}); + const std::vector &text_words = {0xBF810000u, 0xBF810000u}, + std::optional runtime_text_reference = std::nullopt); [[nodiscard]] std::vector make_large_amdgpu_elf_with_waitcnt_entry(); [[nodiscard]] std::unique_ptr decode_one(uint32_t word, rj_code_arch_t arch); diff --git a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp index 87e59cc0151e..2a02f4a2a177 100644 --- a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp @@ -69,6 +69,7 @@ RJ_DIAGNOSTIC_POP #include #include #include +#include #include namespace rocjitsu { @@ -131,6 +132,8 @@ gfx1250_revision_options(rocjitsu::ProcessorRevision input_revision, rocjitsu::BinaryTranslatorOptions options; options.input_revision = input_revision; options.output_revision = output_revision; + options.verify_rewrite_discharge = input_revision == rocjitsu::ProcessorRevision::Gfx1250B0 && + output_revision == rocjitsu::ProcessorRevision::Gfx1250A0; return options; } @@ -3631,6 +3634,127 @@ TEST(BinaryTranslatorE2E, DuplicatesSharedReachableBlocksPerKernel) { EXPECT_EQ(target_words[second_entry_word + 1], kCdna4SEndpgm); } +TEST(BinaryTranslatorE2E, RejectsAmbiguousRuntimeEntryClonedAcrossKernelScopes) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + const std::vector words = { + rocjitsu::build_s_branch(1, ROCJITSU_CODE_ARCH_GFX1250), // kernel0 -> helper 0x08. + rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250), // kernel1 -> helper 0x08. + kGfx1250SEndpgm, + }; + for (const auto relocation : {rocjitsu::test_support::TestRuntimeTextRelocation::Abs64, + rocjitsu::test_support::TestRuntimeTextRelocation::Relative64}) { + SCOPED_TRACE(relocation == rocjitsu::test_support::TestRuntimeTextRelocation::Abs64 + ? "ABS64" + : "RELATIVE64"); + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_two_kernel_descriptors( + words, rocjitsu::test_support::TestRuntimeTextReference{ + .relocation = relocation, + .target_text_offset = 2 * sizeof(uint32_t), + }); + rocjitsu::test_support::write_value_for_test( + image, offsetof(rocjitsu::Elf64_Ehdr, e_flags), rocjitsu::EF_AMDGPU_MACH_AMDGCN_GFX1250); + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + rocjitsu::BinaryTranslator translator( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(rocjitsu::test_support::has_error_containing( + result, rocjitsu::DiagnosticKind::ResourceLimit, + "relocated .text could not be materialized safely")); + } +} + +TEST(BinaryTranslatorE2E, PreservesUniqueRelocationBackedTextEntries) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + constexpr uint64_t kReferencedEntry = sizeof(uint32_t); + struct RelocationCase { + rocjitsu::test_support::TestRuntimeTextRelocation fixture; + uint32_t relocation_type; + }; + constexpr std::array relocation_cases = { + RelocationCase{rocjitsu::test_support::TestRuntimeTextRelocation::Abs64, + rocjitsu::R_AMDGPU_ABS32_LO}, + RelocationCase{rocjitsu::test_support::TestRuntimeTextRelocation::Abs64, + rocjitsu::R_AMDGPU_ABS32_HI}, + RelocationCase{rocjitsu::test_support::TestRuntimeTextRelocation::Abs64, + rocjitsu::R_AMDGPU_ABS64}, + RelocationCase{rocjitsu::test_support::TestRuntimeTextRelocation::Abs64, + rocjitsu::R_AMDGPU_ABS32}, + RelocationCase{rocjitsu::test_support::TestRuntimeTextRelocation::Relative64, + rocjitsu::R_AMDGPU_RELATIVE64}, + }; + + for (const RelocationCase &test_case : relocation_cases) { + SCOPED_TRACE(test_case.relocation_type); + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, rocjitsu::test_support::TestRuntimeTextReference{ + .relocation = test_case.fixture, + .relocation_type = test_case.relocation_type, + .target_text_offset = kReferencedEntry, + }); + rocjitsu::test_support::write_value_for_test( + image, offsetof(rocjitsu::Elf64_Ehdr, e_flags), rocjitsu::EF_AMDGPU_MACH_AMDGCN_GFX1250); + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0); + options.verify_rewrite_discharge = true; + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + options); + const auto result = translator.translate(source); + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + + rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_TRUE(translated.is_valid()); + ASSERT_EQ(translated.text_sections().size(), 1u); + const auto *text = translated.text_sections().front(); + rocjitsu::KernelDescriptorTranslator parser(ROCJITSU_CODE_ARCH_GFX1250, + ROCJITSU_CODE_ARCH_GFX1250); + const auto infos = parser.translate_image(result.elf_bytes, text->sectionOffset(), text->size(), + rocjitsu::KernelDescriptorTranslationOptions{}); + ASSERT_EQ(infos.size(), 2u); + const auto referenced_descriptor = + std::ranges::find_if(infos, [](const auto &info) { return info.entry_text_offset != 0; }); + ASSERT_NE(referenced_descriptor, infos.end()); + const uint64_t expected_vaddr = text->vaddr() + referenced_descriptor->entry_text_offset; + + const auto output_ehdr = + rocjitsu::test_support::read_elf_struct_for_test(result.elf_bytes, 0); + const auto output_shdrs = rocjitsu::test_support::read_elf_array_for_test( + result.elf_bytes, output_ehdr.e_shoff, output_ehdr.e_shnum); + const auto rela = std::ranges::find_if(output_shdrs, [](const rocjitsu::Elf64_Shdr §ion) { + return section.sh_type == rocjitsu::SHT_RELA; + }); + ASSERT_NE(rela, output_shdrs.end()); + const auto relocation_record = + rocjitsu::test_support::read_elf_struct_for_test(result.elf_bytes, + rela->sh_offset); + EXPECT_EQ(rocjitsu::elf_reloc_type(relocation_record.r_info), test_case.relocation_type); + if (test_case.fixture == rocjitsu::test_support::TestRuntimeTextRelocation::Relative64) { + EXPECT_EQ(relocation_record.r_addend, static_cast(expected_vaddr)); + continue; + } + + ASSERT_LT(rela->sh_link, output_shdrs.size()); + const auto &symtab = output_shdrs[rela->sh_link]; + const auto symbols = rocjitsu::test_support::read_elf_array_for_test( + result.elf_bytes, symtab.sh_offset, symtab.sh_size / sizeof(rocjitsu::Elf64_Sym)); + const uint32_t symbol_index = rocjitsu::elf_reloc_sym(relocation_record.r_info); + ASSERT_LT(symbol_index, symbols.size()); + EXPECT_EQ(symbols[symbol_index].st_value, expected_vaddr); + } +} + TEST(BinaryTranslatorE2E, Cdna4ToCdna3SemanticExpandRulesHaveTranslationFixtures) { const auto test_cases = cdna4_to_cdna3_semantic_rule_cases(); const auto rules = rocjitsu::semantic_expand_rules_cdna4_to_cdna3(); @@ -7097,14 +7221,17 @@ TEST(BinaryTranslatorE2E, Gfx1250RelocatesDirectCallForB0ToA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); - rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, - gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, - rocjitsu::ProcessorRevision::Gfx1250A0)); + auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0); + options.verify_rewrite_discharge = true; + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + options); auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto *target_words = @@ -8396,6 +8523,243 @@ TEST(SemanticTranslator, Gfx1250ClassifiesLivenessFreeExpandRules) { EXPECT_FALSE(translator.has_expand_rule(*v_nop_inst)); } +TEST(SemanticTranslator, Gfx1250RegistryHasCompleteDischargeContracts) { + const rocjitsu::RewriteRegistry registry = rocjitsu::rewrite_registry_gfx1250_b0_to_a0(); + EXPECT_TRUE(registry.has_complete_discharge()); + ASSERT_EQ(registry.opcode_rules.size(), 43u); + ASSERT_EQ(registry.instruction_rules.size(), 1u); + + size_t checked_rules = 0; + size_t no_success_rules = 0; + std::vector no_success_rule_keys; + std::vector block_context_rule_keys; + for (const rocjitsu::TranslationRule &rule : registry.opcode_rules) { + EXPECT_TRUE(rule.discharge.valid()); + if (rule.discharge.disposition == rocjitsu::RewriteDischargeDisposition::Checked) { + ++checked_rules; + if (rule.discharge.context == rocjitsu::RewriteDischargeContext::BasicBlock) { + block_context_rule_keys.push_back((static_cast(rule.src_encoding_id) << 16) | + rule.src_opcode); + } + } + if (rule.discharge.disposition == + rocjitsu::RewriteDischargeDisposition::NoSuccessfulExpansion) { + ++no_success_rules; + no_success_rule_keys.push_back((static_cast(rule.src_encoding_id) << 16) | + rule.src_opcode); + EXPECT_FALSE(rule.discharge.allows(rocjitsu::ExpandStatus::Success)); + EXPECT_TRUE(rule.discharge.allows(rocjitsu::ExpandStatus::Failed)); + EXPECT_TRUE(rule.discharge.allows(rocjitsu::ExpandStatus::NotHandled)); + } + } + EXPECT_EQ(checked_rules, 42u); + EXPECT_EQ(no_success_rules, 1u); + const std::vector expected_no_success_rule_keys = { + (static_cast(cdna5::encoding::kSop1) << 16) | cdna5::kSBarrierSignalIsfirstSop1, + }; + EXPECT_EQ(no_success_rule_keys, expected_no_success_rule_keys); + const std::vector expected_block_context_rule_keys = { + (static_cast(cdna5::encoding::kSopk + cdna5::kSSetregB32Sopk) << 16) | + cdna5::kSSetregB32Sopk, + (static_cast(cdna5::encoding::kSopk + cdna5::kSSetregImm32B32Sopk) << 16) | + cdna5::kSSetregImm32B32Sopk, + (static_cast(cdna5::encoding::kVop3p) << 16) | cdna5::kVWmmaI3216x16x64Iu8Vop3p, + (static_cast(cdna5::encoding::kVop3p) << 16) | cdna5::kVSwmmacI3216x16x128Iu8Vop3p, + (static_cast(cdna5::encoding::kVimage) << 16) | cdna5::kTensorLoadToLdsVimage, + (static_cast(cdna5::encoding::kVglobal) << 16) | cdna5::kClusterLoadB32Vglobal, + (static_cast(cdna5::encoding::kVglobal) << 16) | cdna5::kClusterLoadB64Vglobal, + (static_cast(cdna5::encoding::kVglobal) << 16) | cdna5::kClusterLoadB128Vglobal, + (static_cast(cdna5::encoding::kVglobal) << 16) | + cdna5::kClusterLoadAsyncToLdsB8Vglobal, + (static_cast(cdna5::encoding::kVglobal) << 16) | + cdna5::kClusterLoadAsyncToLdsB32Vglobal, + (static_cast(cdna5::encoding::kVglobal) << 16) | + cdna5::kClusterLoadAsyncToLdsB64Vglobal, + (static_cast(cdna5::encoding::kVglobal) << 16) | + cdna5::kClusterLoadAsyncToLdsB128Vglobal, + }; + EXPECT_EQ(block_context_rule_keys, expected_block_context_rule_keys); + + const std::array out_of_order_rules = {registry.opcode_rules[1], registry.opcode_rules[0]}; + const rocjitsu::RewriteRegistry out_of_order_registry{out_of_order_rules, {}}; + EXPECT_FALSE(out_of_order_registry.has_complete_discharge()); + const std::array duplicate_rules = {registry.opcode_rules[0], registry.opcode_rules[0]}; + const rocjitsu::RewriteRegistry duplicate_registry{duplicate_rules, {}}; + EXPECT_FALSE(duplicate_registry.has_complete_discharge()); + + const rocjitsu::RegisteredInstructionRewrite divergent_selector_rule{ + "divergent-selector", + +[](const rocjitsu::Instruction &) { return false; }, + +[](const rocjitsu::Instruction &, uint64_t, std::span, + const rocjitsu::LivenessAnalysis &, + rocjitsu::TranslationContext &) { return rocjitsu::ExpandResult::not_handled(); }, + false, + rocjitsu::RewriteDischarge::checked( + +[](const rocjitsu::Instruction &) { return true; }, + rocjitsu::RewriteDischargeContext::BasicBlock), + }; + const std::array divergent_selector_rules = {divergent_selector_rule}; + const rocjitsu::RewriteRegistry divergent_selector_registry{{}, divergent_selector_rules}; + EXPECT_TRUE(divergent_selector_registry.has_complete_discharge()); + EXPECT_TRUE(divergent_selector_registry.instruction_rewrites_require_basic_block()) + << "CFG fallback must not depend on the lowering selector"; + + const rocjitsu::RegisteredInstructionRewrite &flat_scratch = registry.instruction_rules.front(); + EXPECT_STREQ(flat_scratch.name, "flat-scratch-base-64bit-source"); + EXPECT_TRUE(flat_scratch.requires_liveness); + EXPECT_TRUE(flat_scratch.valid()); + EXPECT_EQ(flat_scratch.discharge.disposition, rocjitsu::RewriteDischargeDisposition::Checked); + EXPECT_EQ(flat_scratch.discharge.context, rocjitsu::RewriteDischargeContext::Instruction); + + rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, + rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0); + EXPECT_TRUE(translator.supports_rewrite_discharge()); + rocjitsu::SemanticTranslator legacy_translator(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_RDNA3, + rocjitsu::ProcessorRevision::Unspecified, + rocjitsu::ProcessorRevision::Unspecified); + EXPECT_FALSE(legacy_translator.supports_rewrite_discharge()); + constexpr auto selector_230 = cdna5::build_sop1(cdna5::kSMovB64Sop1, {.ssrc0 = 230, .sdst = 10}); + constexpr auto selector_231 = cdna5::build_sop1(cdna5::kSMovB64Sop1, {.ssrc0 = 231, .sdst = 10}); + const auto low = rocjitsu::test_support::decode_one(selector_230[0], ROCJITSU_CODE_ARCH_GFX1250); + const auto high = rocjitsu::test_support::decode_one(selector_231[0], ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(low, nullptr); + ASSERT_NE(high, nullptr); + EXPECT_TRUE(translator.has_instruction_rewrite(*low)); + EXPECT_TRUE(translator.has_instruction_rewrite(*high)); + EXPECT_TRUE(translator.rewrite_requires_liveness(*low)); + EXPECT_TRUE(translator.rewrite_requires_liveness(*high)); + EXPECT_FALSE(translator.residual_rewrite_applies(*low)); + EXPECT_TRUE(translator.residual_rewrite_applies(*high)); + EXPECT_FALSE(translator.residual_rewrite_needs_basic_block(*high)); + EXPECT_TRUE(translator.instruction_local_residual_rewrite_applies(*high)); +} + +TEST(SemanticTranslator, Gfx1250ResidualChecksRecognizeEveryActionableSourceRule) { + std::vector> samples; + const auto add_sample = [&](const auto &words) { + samples.emplace_back(words.begin(), words.end()); + }; + const auto add_compound_sample = [&](const auto &prefix, const auto &body) { + std::vector words(prefix.begin(), prefix.end()); + words.insert(words.end(), body.begin(), body.end()); + samples.push_back(std::move(words)); + }; + + constexpr uint16_t kModeHwreg = 1u; + add_sample(cdna5::build_sopk(cdna5::kSSetregB32Sopk, {.simm16 = kModeHwreg, .sdst = 8})); + constexpr std::array setreg_literal = {0}; + add_compound_sample(cdna5::build_sopk(cdna5::kSSetregImm32B32Sopk, {.simm16 = kModeHwreg}), + setreg_literal); + add_sample(cdna5::build_sopp(cdna5::kSClauseSopp, {.simm16 = 4})); + add_sample(cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272})); + + constexpr auto regular_scale = + cdna5::build_vop3p(0x35, {.src0 = 256 + 64, .src1 = 256 + 66, .src2 = 0}); + constexpr auto scale16 = + cdna5::build_vop3p(0x3a, {.src0 = 256 + 64, .src1 = 256 + 66, .src2 = 0}); + constexpr auto scale_body = + cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, + {.vdst = 96, .src0 = 256 + 16, .src1 = 256 + 32, .src2 = 256 + 48}); + add_compound_sample(regular_scale, scale_body); + add_compound_sample(scale16, scale_body); + + add_sample(cdna5::build_vop3p(cdna5::kVWmmaI3216x16x64Iu8Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272})); + add_sample(cdna5::build_vop3p(cdna5::kVSwmmacI3216x16x128Iu8Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272})); + + for (const uint16_t opcode : { + cdna5::kVWmmaF3216x16x128Fp8Fp8Vop3p, + cdna5::kVWmmaF3216x16x128Fp8Bf8Vop3p, + cdna5::kVWmmaF3216x16x128Bf8Fp8Vop3p, + cdna5::kVWmmaF3216x16x128Bf8Bf8Vop3p, + }) { + add_sample(cdna5::build_vop3p(opcode, {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272})); + } + for (const uint16_t opcode : { + cdna5::kVWmmaF1616x16x128Fp8Fp8Vop3p, + cdna5::kVWmmaF1616x16x128Fp8Bf8Vop3p, + cdna5::kVWmmaF1616x16x128Bf8Fp8Vop3p, + cdna5::kVWmmaF1616x16x128Bf8Bf8Vop3p, + }) { + add_sample(cdna5::build_vop3p(opcode, {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272})); + } + add_sample( + cdna5::build_vop3p(cdna5::kVWmmaF3232x16x128F4Vop3p, + {.vdst = 96, .src0 = 256 + 16, .src1 = 256 + 40, .src2 = 256 + 64})); + + add_sample( + cdna5::build_vimage(cdna5::kTensorLoadToLdsVimage, + {.vaddr4 = 124, .vaddr0 = 8, .vaddr1 = 0, .vaddr2 = 124, .vaddr3 = 124})); + add_sample(cdna5::build_vop3(cdna5::kVCvtF32Fp8Vop3, {.vdst = 30, .clamp = 1, .src0 = 256 + 22})); + add_sample(cdna5::build_vop3(cdna5::kVCvtPkFp8F32Vop3, + {.vdst = 30, .clamp = 1, .src0 = 256 + 22, .src1 = 256 + 2})); + add_sample(cdna5::build_vop3(cdna5::kVCvtSrFp8F32Vop3, + {.vdst = 30, .clamp = 1, .src0 = 256 + 22, .src1 = 256 + 2})); + + constexpr cdna5::VdsBuilderFields ds2_fields{ + .offset0 = 3, .offset1 = 5, .addr = 20, .data0 = 30, .data1 = 40, .vdst = 50}; + for (const uint16_t opcode : { + cdna5::kDsStore2addrB32Vds, + cdna5::kDsStore2addrStride64B32Vds, + cdna5::kDsStorexchg2addrRtnB32Vds, + cdna5::kDsStorexchg2addrStride64RtnB32Vds, + cdna5::kDsLoad2addrB32Vds, + cdna5::kDsLoad2addrStride64B32Vds, + cdna5::kDsStore2addrB64Vds, + cdna5::kDsStore2addrStride64B64Vds, + cdna5::kDsStorexchg2addrRtnB64Vds, + cdna5::kDsStorexchg2addrStride64RtnB64Vds, + cdna5::kDsLoad2addrB64Vds, + cdna5::kDsLoad2addrStride64B64Vds, + }) { + add_sample(cdna5::build_vds(opcode, ds2_fields)); + } + add_sample(cdna5::build_vds(cdna5::kDsStoreAddtidB32Vds, + {.offset0 = 0x34, .offset1 = 0x12, .data0 = 16})); + add_sample( + cdna5::build_vds(cdna5::kDsLoadAddtidB32Vds, {.offset0 = 0x34, .offset1 = 0x12, .vdst = 8})); + + for (const uint16_t opcode : { + cdna5::kClusterLoadB32Vglobal, + cdna5::kClusterLoadB64Vglobal, + cdna5::kClusterLoadB128Vglobal, + cdna5::kClusterLoadAsyncToLdsB8Vglobal, + cdna5::kClusterLoadAsyncToLdsB32Vglobal, + cdna5::kClusterLoadAsyncToLdsB64Vglobal, + cdna5::kClusterLoadAsyncToLdsB128Vglobal, + }) { + add_sample(cdna5::build_vglobal(opcode, {.saddr = 4, .vdst = 8, .vaddr = 12})); + } + + std::vector residual_rules; + for (const rocjitsu::TranslationRule &rule : rocjitsu::semantic_expand_rules_gfx1250_b0_to_a0()) { + if (rule.discharge.disposition == rocjitsu::RewriteDischargeDisposition::Checked) + residual_rules.push_back(&rule); + } + ASSERT_EQ(samples.size(), residual_rules.size()); + + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, + rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0); + for (size_t sample_index = 0; sample_index < samples.size(); ++sample_index) { + SCOPED_TRACE(sample_index); + std::unique_ptr inst(decoder->decode(samples[sample_index].data(), 0)); + ASSERT_NE(inst, nullptr); + EXPECT_EQ(inst->encoding_id(), residual_rules[sample_index]->src_encoding_id); + EXPECT_EQ(inst->opcode(), residual_rules[sample_index]->src_opcode); + EXPECT_TRUE(translator.residual_rewrite_applies(*inst)); + const bool needs_basic_block = residual_rules[sample_index]->discharge.context == + rocjitsu::RewriteDischargeContext::BasicBlock; + EXPECT_EQ(translator.residual_rewrite_needs_basic_block(*inst), needs_basic_block); + EXPECT_EQ(translator.instruction_local_residual_rewrite_applies(*inst), !needs_basic_block); + } +} + TEST(BinaryTranslatorE2E, Gfx1250UsesNeutralScaledK128Fp8Bf8Wmma) { struct WmmaCase { const char *name; @@ -8558,10 +8922,9 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaRejectsClamp) { "floating-point results")); } -// The f32 lowering re-encodes VDST, SRC0, SRC1, and SRC2 unchanged, so the -// operand shapes that the packed-f16 lowering cannot address must still -// translate here. Narrowing this path would reject code objects that the -// hardware accepts. +// The f32 lowering re-encodes VDST, SRC0, SRC1, and SRC2 unchanged. Preserve +// operand encodings that the packed-f16 lowering cannot address when the +// scaled f32 form can still represent them. TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaAcceptsOperandsThePackedF16PathRejects) { struct OperandCase { const char *name; @@ -8570,7 +8933,6 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaAcceptsOperandsThePackedF16PathRejec const std::array cases = { OperandCase{"odd_matrix_and_destination", {.vdst = 55, .src0 = 256 + 17, .src1 = 256 + 33, .src2 = 256 + 49}}, - OperandCase{"sgpr_accumulator", {.vdst = 54, .src0 = 256 + 16, .src1 = 256 + 32, .src2 = 8}}, OperandCase{"nonzero_inline_accumulator", {.vdst = 54, .src0 = 256 + 16, .src1 = 256 + 32, .src2 = 129}}, }; @@ -8604,6 +8966,27 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaAcceptsOperandsThePackedF16PathRejec } } +TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaRejectsScalarAccumulator) { + const auto source_wmma = + cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128Fp8Fp8Vop3p, + {.vdst = 54, .src0 = 256 + 16, .src1 = 256 + 32, .src2 = 8}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text( + {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + rocjitsu::BinaryTranslator translator( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(rocjitsu::test_support::has_error_containing( + result, rocjitsu::DiagnosticKind::ExpandFailed, + "gfx1250 K=128 f32 WMMA scalar accumulator cannot be represented by the scaled form")); +} + TEST(BinaryTranslatorE2E, Gfx1250LowersF16K128Fp8Bf8WmmaThroughF32Scratch) { constexpr std::array source_opcodes = { cdna5::kVWmmaF1616x16x128Fp8Fp8Vop3p, @@ -9357,6 +9740,50 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadFailsClosedWithoutExecIndependentCar "gfx1250 cluster load could not allocate scalar scratch for M0 preservation")); } +TEST(BinaryTranslatorE2E, Gfx1250DischargesEveryClusterLoadVariant) { + struct Case { + std::array words; + std::string_view mnemonic; + }; + constexpr std::array cases = { + Case{{0xEE19C000u, 0x00000001u, 0x00000000u}, "cluster_load_b32"}, + Case{{0xEE1A0000u, 0x00000000u, 0x00000002u}, "cluster_load_b64"}, + Case{{0xEE1A4000u, 0x00010002u, 0x00000000u}, "cluster_load_b128"}, + Case{{0xEE1A8000u, 0x00000000u, 0x00000000u}, "cluster_load_async_to_lds_b8"}, + Case{{0xEE1AC000u, 0x00000000u, 0x00000800u}, "cluster_load_async_to_lds_b32"}, + Case{{0xEE1B0000u, 0x00000004u, 0x00000004u}, "cluster_load_async_to_lds_b64"}, + Case{{0xEE1B4000u, 0x00010001u, 0x00000000u}, "cluster_load_async_to_lds_b128"}, + }; + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + + for (const Case &test_case : cases) { + SCOPED_TRACE(test_case.mnemonic); + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text( + {test_case.words[0], test_case.words[1], test_case.words[2], kGfx1250SEndpgm}); + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + rocjitsu::BinaryTranslator translator( + ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_FALSE(translated.text_sections().empty()); + const auto decoded = + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + EXPECT_EQ( + std::ranges::count_if( + decoded, [&](const auto &inst) { return inst->mnemonic() == test_case.mnemonic; }), + 1); + } +} + TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadPreservesGuestM0ClearWithoutRestore) { constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); constexpr auto cluster = @@ -11161,13 +11588,16 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadPreservesGuestMaskClearWithoutRestore {source_clear[0], source_tensor[0], source_tensor[1], source_tensor[2], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); - rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, - gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, - rocjitsu::ProcessorRevision::Gfx1250A0)); + auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0); + options.verify_rewrite_discharge = true; + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + options); auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); @@ -13607,7 +14037,9 @@ translate_gfx1250_indexed_flat_scratch_destination(uint32_t gpr_index_control) { } /// @brief Translate a single-instruction gfx1250 kernel with the B0-to-A0 profile. -[[nodiscard]] std::vector translate_gfx1250_b0_to_a0_words(std::vector words) { +[[nodiscard]] std::vector +translate_gfx1250_b0_to_a0_words(std::vector words, + rocjitsu::TranslationTraceCallback trace_callback = {}) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; words.push_back(kGfx1250SEndpgm); auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); @@ -13617,6 +14049,8 @@ translate_gfx1250_indexed_flat_scratch_destination(uint32_t gpr_index_control) { ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); + if (trace_callback) + translator.set_trace_callback(std::move(trace_callback)); auto result = translator.translate(source); EXPECT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" : result.diagnostics.front().message); @@ -13640,7 +14074,22 @@ translate_gfx1250_indexed_flat_scratch_destination(uint32_t gpr_index_control) { TEST(BinaryTranslatorE2E, Gfx1250RewritesScalarFlatScratchBase64BitSourceForA0) { const auto source = cdna5::build_sop1( cdna5::kSMovB64Sop1, {.ssrc0 = static_cast(kFlatScratchBaseHiSelector), .sdst = 10}); - const auto out = translate_gfx1250_b0_to_a0_words({source[0]}); + struct TraceClassification { + const rocjitsu::InstructionLegalization *legalization; + bool copied_original; + bool semantic_lowering; + bool changed; + }; + std::optional rewrite_trace; + const auto out = translate_gfx1250_b0_to_a0_words( + {source[0]}, [&](const rocjitsu::TranslationTraceEvent &event) { + if (event.source_words.size() != source.size() || event.source_words[0] != source[0]) + return; + rewrite_trace = {.legalization = event.legalization, + .copied_original = event.copied_original, + .semantic_lowering = event.semantic_lowering, + .changed = event.changed}; + }); ASSERT_GE(out.size(), 2u); EXPECT_EQ(out[0] & 0xffu, kFlatScratchBaseLoSelector) @@ -13648,6 +14097,12 @@ TEST(BinaryTranslatorE2E, Gfx1250RewritesScalarFlatScratchBase64BitSourceForA0) // Only the source selector changes: destination, opcode, and encoding stay. EXPECT_EQ(out[0] & ~0xffu, source[0] & ~0xffu); EXPECT_EQ(out.size(), 2u) << "a scalar rewrite must not add instructions"; + ASSERT_TRUE(rewrite_trace.has_value()); + EXPECT_EQ(rewrite_trace->legalization, nullptr) + << "registered instruction rewrites are not opcode legalizations"; + EXPECT_FALSE(rewrite_trace->copied_original); + EXPECT_TRUE(rewrite_trace->semantic_lowering); + EXPECT_TRUE(rewrite_trace->changed); } // A 64-bit read in the first scalar source position of a two-source encoding. diff --git a/emulation/rocjitsu/tests/dbt/translate_test.cpp b/emulation/rocjitsu/tests/dbt/translate_test.cpp index 93a611e0b530..1dfd038c7cf5 100644 --- a/emulation/rocjitsu/tests/dbt/translate_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_test.cpp @@ -12,9 +12,12 @@ #include "rocjitsu/code/amdgpu_code_object.h" #include "rocjitsu/code/amdgpu_elf.h" +#include "rocjitsu/code/basic_block.h" #include "rocjitsu/code/builders/instruction_builder.h" #include "rocjitsu/code/dbt/binary_translator.h" +#include "rocjitsu/code/dbt/binary_translator_internal.h" #include "rocjitsu/code/dbt/kernel_descriptor_translator.h" +#include "rocjitsu/code/dbt/legalization/gfx1250_b0_to_a0.h" #include "rocjitsu/code/dbt/semantic/rules.h" #include "rocjitsu/code/dbt/semantic_translator.h" #include "rocjitsu/code/dbt/virtual_lds.h" @@ -70,16 +73,19 @@ RJ_DIAGNOSTIC_POP #include #include #include +#include #include #include #include #include #include +#include #include namespace rocjitsu { namespace { +using test_support::append_elf_section_for_test; using test_support::decode_one; using test_support::enable_workgroup_id_x_sgpr; using test_support::find_section; @@ -87,11 +93,14 @@ using test_support::has_error_containing; using test_support::kKernelDescriptorSize; using test_support::make_large_amdgpu_elf_with_waitcnt_entry; using test_support::make_minimal_amdgpu_elf_with_descriptor_after_text; +using test_support::make_minimal_amdgpu_elf_with_two_kernel_descriptors; using test_support::read_elf_array_for_test; using test_support::read_elf_struct_for_test; using test_support::read_kernel_descriptor_entry_offset; using test_support::read_kernel_descriptor_for_test; using test_support::TestKernelDescriptor; +using test_support::TestRuntimeTextReference; +using test_support::TestRuntimeTextRelocation; using test_support::write_elf_struct_for_test; using test_support::write_kernel_descriptor_entry_offset; using test_support::write_kernel_descriptor_for_test; @@ -119,9 +128,10 @@ void write_bytes_for_test(std::vector &image, uint64_t offset, const vo constexpr uint64_t kKernargPreloadSkipBytes = 256; -std::vector make_minimal_amdgpu_elf_with_text_and_rodata() { +std::vector +make_minimal_amdgpu_elf_with_text_and_rodata(std::span text_bytes) { constexpr uint64_t text_offset = 0x100; - constexpr uint64_t text_size = 8; + const uint64_t text_size = text_bytes.size(); constexpr uint64_t rodata_size = 4; std::vector shstrtab{'\0'}; @@ -151,8 +161,8 @@ std::vector make_minimal_amdgpu_elf_with_text_and_rodata() { ehdr.e_shstrndx = 3; std::memcpy(image.data(), &ehdr, sizeof(ehdr)); - const std::array text_words = {0xBF800000u, 0xBF800000u}; - std::memcpy(image.data() + text_offset, text_words.data(), text_size); + if (!text_bytes.empty()) + std::memcpy(image.data() + text_offset, text_bytes.data(), text_size); const uint32_t rodata_word = 0xA5A55A5Au; std::memcpy(image.data() + rodata_offset, &rodata_word, sizeof(rodata_word)); @@ -183,6 +193,18 @@ std::vector make_minimal_amdgpu_elf_with_text_and_rodata() { return image; } +std::vector make_minimal_amdgpu_elf_with_text_and_rodata() { + constexpr std::array text_words = {0xBF800000u, 0xBF800000u}; + return make_minimal_amdgpu_elf_with_text_and_rodata(std::span( + reinterpret_cast(text_words.data()), sizeof(text_words))); +} + +std::vector +make_minimal_amdgpu_elf_with_text_words_and_rodata(std::span text_words) { + return make_minimal_amdgpu_elf_with_text_and_rodata(std::span( + reinterpret_cast(text_words.data()), text_words.size_bytes())); +} + std::vector make_minimal_gfx1250_elf_with_empty_text_and_rodata() { auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); auto ehdr = read_elf_struct_for_test(image, 0); @@ -327,13 +349,15 @@ std::vector make_minimal_amdgpu_elf_with_load_segments() { return image; } -// reloc_type and reloc_addend default to a bare record, which is what the +// reloc_type defaults to a representative non-inert record, which is what the // r_offset tests want. Naming R_AMDGPU_RELATIVE64 with an addend inside the // section that follows .text instead exercises the addend shift: the stored // value is load_bias + r_addend, so a .text that grows past its load alignment // moves the section and the addend has to move with it. -std::vector make_minimal_amdgpu_elf_with_relocation_after_text( - bool place_reloc_in_text = false, uint32_t reloc_type = 0, int64_t reloc_addend = 0) { +std::vector +make_minimal_amdgpu_elf_with_relocation_after_text(bool place_reloc_in_text = false, + uint32_t reloc_type = R_AMDGPU_ABS64, + int64_t reloc_addend = 0) { constexpr uint64_t text_offset = 0x100; constexpr uint64_t text_vaddr = 0x1100; constexpr uint64_t text_size = 8; @@ -446,11 +470,25 @@ std::vector make_minimal_amdgpu_elf_with_relocation_after_text( } // Build an ET_DYN object whose .data relocation resolves against a symbol of a -// chosen type, defined either in .text or .data. Ordinary zero-addend text -// symbols can follow their relocated st_value; section symbols and nonzero -// addends need relocation-specific reconstruction and remain unsupported. -std::vector make_amdgpu_elf_with_symbol_relocation(uint8_t sym_type, bool defined_in_text, - int64_t addend = 0) { +// chosen type, defined either in .text or .data. Supported zero-addend text +// symbols can follow their relocated st_value; section symbols, nonzero +// addends, and unrecognized dynamic relocation types remain unsupported. +// ROCr rejects R_AMDGPU_NONE in target-less dynamic sections, while explicit-target +// sections are skipped for supported code objects and therefore treat NONE as inert. +constexpr std::array kSupportedExplicitSymbolRelocations = { + R_AMDGPU_ABS32_LO, + R_AMDGPU_ABS32_HI, + R_AMDGPU_ABS64, + R_AMDGPU_ABS32, +}; +constexpr uint32_t kUnrecognizedAmdGpuRelocation = 12; // Unassigned in the AMDGPU ELF ABI. +constexpr uint8_t kUnsupportedRuntimeSymbolType = 15; +constexpr std::array kUnsupportedExplicitSymbolRelocations = { + kUnrecognizedAmdGpuRelocation, +}; +std::vector +make_amdgpu_elf_with_symbol_relocation(uint8_t sym_type, bool defined_in_text, int64_t addend = 0, + uint32_t relocation_type = R_AMDGPU_ABS64) { constexpr uint64_t text_offset = 0x100; constexpr uint64_t text_vaddr = 0x1100; constexpr uint64_t text_size = 8; @@ -538,7 +576,7 @@ std::vector make_amdgpu_elf_with_symbol_relocation(uint8_t sym_type, bo Elf64_Rela rela{}; rela.r_offset = data_vaddr; // place in .data, safely shifted with the section - rela.r_info = (static_cast(1) << 32) | R_AMDGPU_ABS64; + rela.r_info = (static_cast(1) << 32) | relocation_type; rela.r_addend = addend; std::memcpy(image.data() + rela_offset, &rela, sizeof(rela)); @@ -720,11 +758,14 @@ TEST(BinaryTranslatorE2E, EmptyTextSameArchIsSuccessfulNoOp) { BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); const auto result = translator.translate(source); EXPECT_TRUE(result.ok()); EXPECT_TRUE(result.dispatchable()); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); EXPECT_EQ(result.elf_bytes, image); const auto warning = std::ranges::find_if(result.diagnostics, [](const auto &diagnostic) { return diagnostic.kind == DiagnosticKind::DataOnly; @@ -861,6 +902,48 @@ TEST(BinaryTranslatorE2E, DescriptorlessExecutableTextIsSuccessfulNoOp) { EXPECT_NE(warning->message.find("no kernel descriptors"), std::string::npos); } +TEST(BinaryTranslatorE2E, RewriteDischargeCannotVerifySkippedKernelStubs) { + const auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + options.skip_failed_kernels = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_FALSE(result.dispatchable()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "cannot be combined with skip-failed-kernels")); + EXPECT_TRUE(std::ranges::none_of(result.diagnostics, [](const auto &diagnostic) { + return diagnostic.kind == DiagnosticKind::KernelSkipped; + })); +} + +TEST(BinaryTranslatorE2E, RewriteDischargeReportsUnsupportedCoreProfile) { + const auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_CDNA4, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::ResidualRewrite, + "unavailable for this translation profile")); +} + // A code relocation names a branch destination inside the text being written, so it has to be a // whole instruction there. An offset equal to the size names the byte one past the end, which // would still compute a literal and leave it pointing outside `.text`. @@ -937,201 +1020,1605 @@ TEST(CodeObjectPatcher, ResolvesAllocatedDataPayloadsAndEndpoints) { << "source text takes precedence over a data section ending at the same address"; } -TEST(CodeObjectPatcher, ReplaceTextGrowsTextAndShiftsFollowingSections) { - auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); - AmdGpuCodeObject co(image.data(), image.size()); - ASSERT_TRUE(co.is_valid()); - ASSERT_FALSE(co.text_sections().empty()); +class RewriteDischargeBoundTestInstruction final : public Instruction { +public: + explicit RewriteDischargeBoundTestInstruction(size_t word_count) + : Instruction("bounded_decode_test", nullptr) { + size_ = static_cast(word_count * sizeof(uint32_t)); + } +}; - CodeObjectPatcher patcher(co); - const std::array text_words = {0xBF800000u, 0xBF800000u, 0xDEADBEEFu, 0xCAFEBABEu}; - const auto *text_bytes = reinterpret_cast(text_words.data()); - ASSERT_TRUE(patcher.replace_text({text_bytes, text_words.size() * sizeof(uint32_t)})); +class RewriteDischargeBoundTestDecoder final : public Decoder { +public: + RewriteDischargeBoundTestDecoder(size_t max_instruction_words, size_t decoded_words) + : max_instruction_words_(max_instruction_words), decoded_words_(decoded_words) {} - auto patched_bytes = patcher.emit(); - AmdGpuCodeObject patched(patched_bytes.data(), patched_bytes.size()); - ASSERT_TRUE(patched.is_valid()); - ASSERT_FALSE(patched.text_sections().empty()); + std::size_t max_instruction_words() const override { return max_instruction_words_; } - const Section *text = patched.text_sections()[0]; - ASSERT_NE(text, nullptr); - EXPECT_EQ(text->size(), text_words.size() * sizeof(uint32_t)); - ASSERT_EQ(patched.text_sections().size(), 1u); - EXPECT_EQ(patched.text_sections()[0]->name(), ".text"); - EXPECT_EQ(find_section(patched, ".rj_translations"), nullptr); - EXPECT_EQ(std::memcmp(text->data(), text_words.data(), text->size()), 0); + Instruction *decode(const rj_code_binary_inst_t *words) override { + ++decode_calls; + observed_words.assign(words, words + max_instruction_words_); + return new RewriteDischargeBoundTestInstruction(decoded_words_); + } - const Section *rodata = find_section(patched, ".rodata"); - ASSERT_NE(rodata, nullptr); - EXPECT_EQ(rodata->sectionOffset(), text->sectionOffset() + text->size()) - << "sections following .text must be shifted after the grown text"; - uint32_t rodata_word = 0; - std::memcpy(&rodata_word, rodata->data(), sizeof(rodata_word)); - EXPECT_EQ(rodata_word, 0xA5A55A5Au); + size_t decode_calls = 0; + std::vector observed_words; + +private: + size_t max_instruction_words_; + size_t decoded_words_; +}; + +TEST(BinaryTranslatorInternal, RewriteDischargeDecodeRejectsWidthBeyondDecoderMaximum) { + RewriteDischargeBoundTestDecoder decoder(/*max_instruction_words=*/2, /*decoded_words=*/3); + internal::RewriteDischargeInstructionDecoder bounded_decoder(decoder); + constexpr std::array words = {0x11111111u, 0x22222222u, 0x33333333u}; + const auto bytes = + std::span(reinterpret_cast(words.data()), sizeof(words)); + std::unique_ptr instruction; + + EXPECT_EQ(bounded_decoder.decode(bytes, /*source_offset=*/20, instruction), + internal::RewriteDischargeDecodeStatus::TruncatedInstruction); + ASSERT_NE(instruction, nullptr); + EXPECT_EQ(instruction->src_loc(), 20u); + EXPECT_EQ(decoder.decode_calls, 1u); + EXPECT_EQ(decoder.observed_words, (std::vector{0x11111111u, 0x22222222u})); } -// COMPUTE_PGM_RSRC3 is carried over verbatim only when source and target agree on its layout. -// "GFX10 or later" is not a fine enough test: INST_PREF_SIZE is GFX11+, and IMAGE_OP is GFX11+, -// so handing a GFX11 or GFX12 word to a GFX10 target would set bits GFX10 requires to be zero. -// Equally, a GFX12 word must survive intact on a GFX12 target, including the GFX125-only -// NAMED_BAR_CNT and an INST_PREF_SIZE above the 63 that GFX11's narrower field can hold. -TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { - using namespace rocr::llvm::amdhsa; - - const auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(); - AmdGpuCodeObject probe(image.data(), image.size()); - ASSERT_TRUE(probe.is_valid()); - const Section *probe_rodata = find_section(probe, ".rodata"); - ASSERT_NE(probe_rodata, nullptr); - ASSERT_GE(probe_rodata->size(), sizeof(kernel_descriptor_t)); - - // A GFX12-shaped source word: INST_PREF_SIZE beyond GFX11's 6-bit range, plus a GFX125-only - // named-barrier allocation. - uint32_t source_rsrc3 = 0; - AMDHSA_BITS_SET(source_rsrc3, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE, 107u); - AMDHSA_BITS_SET(source_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT, 3u); - - auto patched_rsrc3 = [&](rj_code_arch_t source_arch, - rj_code_arch_t target_arch) -> std::optional { - auto local_image = image; - AmdGpuCodeObject local_co(local_image.data(), local_image.size()); - if (!local_co.is_valid()) - return std::nullopt; - const Section *rodata = find_section(local_co, ".rodata"); - if (rodata == nullptr) - return std::nullopt; - - auto descriptor = read_kernel_descriptor_for_test(rodata->data()); - descriptor.compute_pgm_rsrc3 = source_rsrc3; - write_kernel_descriptor_for_test(local_image.data() + rodata->sectionOffset(), descriptor); +TEST(BinaryTranslatorInternal, RewriteDischargeDecodeRejectsZeroBoundWithoutDecoding) { + RewriteDischargeBoundTestDecoder decoder(/*max_instruction_words=*/0, /*decoded_words=*/1); + internal::RewriteDischargeInstructionDecoder bounded_decoder(decoder); + constexpr std::array words = {0x11111111u}; + const auto bytes = + std::span(reinterpret_cast(words.data()), sizeof(words)); + std::unique_ptr instruction = + std::make_unique(1); + + EXPECT_FALSE(bounded_decoder.has_valid_lookahead_bound()); + EXPECT_EQ(bounded_decoder.decode(bytes, /*source_offset=*/0, instruction), + internal::RewriteDischargeDecodeStatus::InvalidLookaheadBound); + EXPECT_EQ(instruction, nullptr); + EXPECT_EQ(decoder.decode_calls, 0u); +} - AmdGpuCodeObject seeded(local_image.data(), local_image.size()); - if (!seeded.is_valid()) - return std::nullopt; +TEST(BinaryTranslatorInternal, RewriteDischargeDecodeClearsUnusedWordsAcrossCalls) { + RewriteDischargeBoundTestDecoder decoder(/*max_instruction_words=*/2, /*decoded_words=*/1); + internal::RewriteDischargeInstructionDecoder bounded_decoder(decoder); + constexpr std::array full_words = {0x11111111u, 0x22222222u}; + const auto full_bytes = std::span( + reinterpret_cast(full_words.data()), sizeof(full_words)); + std::unique_ptr instruction; + + ASSERT_EQ(bounded_decoder.decode(full_bytes, /*source_offset=*/0, instruction), + internal::RewriteDischargeDecodeStatus::Success); + ASSERT_EQ(decoder.observed_words, (std::vector{0x11111111u, 0x22222222u})); + + constexpr std::array short_words = {0x33333333u}; + const auto short_bytes = std::span( + reinterpret_cast(short_words.data()), sizeof(short_words)); + EXPECT_EQ(bounded_decoder.decode(short_bytes, /*source_offset=*/4, instruction), + internal::RewriteDischargeDecodeStatus::Success); + EXPECT_EQ(decoder.observed_words, (std::vector{0x33333333u, 0u})); +} - KdTranslation translation{}; - translation.descriptor_file_offset = rodata->sectionOffset(); - translation.target_wave_size = 32; - translation.source_arch = source_arch; +TEST(BinaryTranslatorE2E, RewriteDischargeRejectsIdentityOutputWithResidualTrigger) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + constexpr auto source_clause = cdna5::build_sopp(cdna5::kSClauseSopp, {.simm16 = 4}); + write_value_for_test(image, 0x100, source_clause[0]); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); - CodeObjectPatcher patcher(seeded); - if (!patcher.apply_kernel_descriptor_translation(translation, target_arch)) - return std::nullopt; - const auto patched_image = patcher.emit(); - return read_kernel_descriptor_for_test(patched_image.data() + - translation.descriptor_file_offset) - .compute_pgm_rsrc3; - }; + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); - // Matching layout: carried verbatim, both the wide INST_PREF_SIZE and NAMED_BAR_CNT. - const auto same_layout = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_TRUE(same_layout.has_value()); - EXPECT_EQ(*same_layout, source_rsrc3); - EXPECT_EQ(AMDHSA_BITS_GET(*same_layout, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE), 107u); - EXPECT_EQ(AMDHSA_BITS_GET(*same_layout, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 3u); + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + const auto residual = std::ranges::find_if(result.diagnostics, [](const auto &diagnostic) { + return diagnostic.kind == DiagnosticKind::ResidualRewrite; + }); + ASSERT_NE(residual, result.diagnostics.end()); + EXPECT_EQ(residual->severity, DiagnosticSeverity::Error); + EXPECT_EQ(residual->output_offset, std::optional(0)); + EXPECT_EQ(residual->mnemonic, "s_clause"); +} - // GFX10 targets have no INST_PREF_SIZE and no IMAGE_OP; the GFX12 word must not be inherited. - for (const rj_code_arch_t gfx10 : {ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2}) { - const auto rebuilt = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, gfx10); - ASSERT_TRUE(rebuilt.has_value()); - EXPECT_NE(*rebuilt, source_rsrc3); - EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE), 0u) - << "GFX10 reserves the INST_PREF_SIZE bits and requires them to be zero"; +TEST(BinaryTranslatorE2E, RewriteDischargeRejectsNonDwordTextTail) { + constexpr std::array text = {0x00, 0x00, 0x80, 0xbf, 0xaa, 0xbb, 0xcc}; + for (size_t tail_size = 1; tail_size <= 3; ++tail_size) { + SCOPED_TRACE(tail_size); + auto image = make_minimal_amdgpu_elf_with_text_and_rodata( + std::span(text).first(sizeof(uint32_t) + tail_size)); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE( + has_error_containing(result, DiagnosticKind::ResidualRewrite, "partial instruction word")); } +} - // A GFX9/CDNA source encodes ACCUM_OFFSET here, so it is rebuilt for a GFX12 target. - const auto from_cdna = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_TRUE(from_cdna.has_value()); - EXPECT_NE(*from_cdna, source_rsrc3); - EXPECT_EQ(AMDHSA_BITS_GET(*from_cdna, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 0u); - - // The narrow case: GFX11 -> GFX10. Both are "GFX10+" and both use SHARED_VGPR_COUNT, so a - // coarse family check treats them as interchangeable -- but GFX11's INST_PREF_SIZE at 9:4 and - // IMAGE_OP at 31 are reserved on GFX10 and must not be carried over. - uint32_t gfx11_rsrc3 = 0; - AMDHSA_BITS_SET(gfx11_rsrc3, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE, 21u); - AMDHSA_BITS_SET(gfx11_rsrc3, COMPUTE_PGM_RSRC3_GFX10_PLUS_IMAGE_OP, 1u); - source_rsrc3 = gfx11_rsrc3; - for (const rj_code_arch_t gfx10 : {ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2}) { - const auto rebuilt = patched_rsrc3(ROCJITSU_CODE_ARCH_RDNA3, gfx10); - ASSERT_TRUE(rebuilt.has_value()); - EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE), 0u) - << "GFX10 reserves INST_PREF_SIZE; a GFX11 word must not be carried over"; - EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_IMAGE_OP), 0u) - << "IMAGE_OP is GFX11+; GFX10 reserves bit 31"; +TEST(BinaryTranslatorE2E, RewriteDischargeRejectsTruncatedMultiwordInstruction) { + constexpr std::array scaled_wmma = {0xCC350000u, 0x0202954Eu, 0xCC332042u, + 0x050A01CAu}; + for (size_t word_count = 1; word_count < scaled_wmma.size(); ++word_count) { + SCOPED_TRACE(word_count); + auto image = make_minimal_amdgpu_elf_with_text_words_and_rodata( + std::span(scaled_wmma).first(word_count)); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(std::ranges::any_of(result.diagnostics, [](const auto &diagnostic) { + return diagnostic.kind == DiagnosticKind::ResidualRewrite; + })); } +} - // GFX11 -> GFX11 still round-trips, so the split does not over-rebuild. - const auto gfx11_same = patched_rsrc3(ROCJITSU_CODE_ARCH_RDNA3, ROCJITSU_CODE_ARCH_RDNA3); - ASSERT_TRUE(gfx11_same.has_value()); - EXPECT_EQ(*gfx11_same, gfx11_rsrc3); +TEST(BinaryTranslatorE2E, RewriteDischargeRejectsResidualFlatScratchBaseSelector) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + constexpr auto source = cdna5::build_sop1(cdna5::kSMovB64Sop1, {.ssrc0 = 231, .sdst = 10}); + write_value_for_test(image, 0x100, source[0]); + AmdGpuCodeObject code_object(image.data(), image.size()); + ASSERT_TRUE(code_object.is_valid()); - // GFX125 -> GFX120. Both are GFX12, and both use the same 8-bit INST_PREF_SIZE, but LLVM - // reserves bits 21:14 on GFX120 while GFX125 fills them with NAMED_BAR_CNT, - // ENABLE_DYNAMIC_VGPR, TCP_SPLIT and ENABLE_DIDT_THROTTLE. A shared "GFX12+" bucket would - // carry those straight into target-reserved bits. - uint32_t gfx125_rsrc3 = 0; - AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE, 107u); - AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT, 3u); - AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT, 5u); - AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR, 1u); - source_rsrc3 = gfx125_rsrc3; - const auto to_gfx120 = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_RDNA4); - ASSERT_TRUE(to_gfx120.has_value()); - EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 0u) - << "bits 21:14 are reserved on GFX120 and must not inherit GFX125 state"; - EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT), 0u); - EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR), 0u); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(code_object); - // GFX125 -> GFX125 keeps all of it. - const auto gfx125_same = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); - ASSERT_TRUE(gfx125_same.has_value()); - EXPECT_EQ(*gfx125_same, gfx125_rsrc3); + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + const auto residual = std::ranges::find_if(result.diagnostics, [](const auto &diagnostic) { + return diagnostic.kind == DiagnosticKind::ResidualRewrite; + }); + ASSERT_NE(residual, result.diagnostics.end()); + EXPECT_EQ(residual->severity, DiagnosticSeverity::Error); + EXPECT_EQ(residual->output_offset, std::optional(0)); + EXPECT_EQ(residual->mnemonic, "s_mov_b64"); } -// SHARED_VGPR_COUNT is the one carried field this patcher invalidates itself: it rewrites both -// the wave size and the RSRC1 VGPR allocation the field is constrained against. LLVM requires -// the count to be zero for wave32, and for wave64 requires -// (compute_pgm_rsrc1.vgprs + 1) * 4 + shared_vgpr_count * 8 <= 256. -// -// The field counts registers the unchanged kernel body uses, so a descriptor that no longer -// leaves room for them is refused rather than clamped: clamping would keep the body's demand -// while shrinking what the descriptor reserves for it. -TEST(CodeObjectPatcher, SharedVgprCountIsReconciledWithTheTargetAllocation) { - using namespace rocr::llvm::amdhsa; +TEST(BinaryTranslatorE2E, Gfx1250TranslationIgnoresUnreferencedVisibleTextSymbols) { + constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); + constexpr auto cluster = + cdna5::build_vglobal(cdna5::kClusterLoadB32Vglobal, {.saddr = 124, .vdst = 8, .vaddr = 12}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + const std::vector words = {clear_m0[0], cluster[0], cluster[1], cluster[2], + kGfx1250SEndpgm}; + + for (const uint8_t symbol_bind : {kElfSymbolBindGlobal, kElfSymbolBindWeak}) { + SCOPED_TRACE(symbol_bind == kElfSymbolBindGlobal ? "STB_GLOBAL" : "STB_WEAK"); + auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(words, words.size()); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + const auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + symbols[2].st_info = elf_symbol_info(symbol_bind, kElfSymbolTypeFunc); + symbols[2].st_shndx = static_cast(text_it - shdrs.begin()); + symbols[2].st_value = text_it->sh_addr + sizeof(uint32_t); + symbols[2].st_size = 4 * sizeof(uint32_t); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_FALSE(result.rewrite_discharge_checked) + << "ordinary translation must ignore symbol metadata without relying on the verifier"; + AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_TRUE(translated.is_valid()); + ASSERT_EQ(translated.text_sections().size(), 1u); + const Section *translated_text = translated.text_sections().front(); + ASSERT_EQ(translated_text->size() % sizeof(uint32_t), 0u); + const auto translated_words = + std::span(reinterpret_cast(translated_text->data()), + translated_text->size() / sizeof(uint32_t)); + // Ordinary text symbols are CFG split points, but visibility alone does not + // make them external entries or require their bodies to be preserved. + EXPECT_EQ(std::ranges::count(translated_words, cluster[0]), 1); + } +} - const auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(); +TEST(BinaryTranslatorE2E, Gfx1250TranslationIgnoresUnreferencedSymbolInsideInstruction) { + constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); + constexpr auto cluster = + cdna5::build_vglobal(cdna5::kClusterLoadB32Vglobal, {.saddr = 124, .vdst = 8, .vaddr = 12}); + constexpr auto source_clause = cdna5::build_sopp(cdna5::kSClauseSopp, {.simm16 = 4}); + constexpr auto target_nop = cdna5::build_sopp(cdna5::kSNopSopp, {.simm16 = 0}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + const std::vector words = {clear_m0[0], cluster[0], cluster[1], + cluster[2], source_clause[0], kGfx1250SEndpgm}; + auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(words, words.size()); - struct PatchOutcome { - bool seeded = false; ///< Fixture setup succeeded. - bool patched = false; ///< The patcher accepted the request. - uint32_t shared_count = 0; - }; + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + const auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + symbols[2].st_info = elf_symbol_info(kElfSymbolBindGlobal, kElfSymbolTypeFunc); + symbols[2].st_shndx = static_cast(text_it - shdrs.begin()); + symbols[2].st_value = text_it->sh_addr + 2 * sizeof(uint32_t); + symbols[2].st_size = sizeof(uint32_t); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); - auto patched = [&](uint32_t source_shared, uint32_t target_wave, - uint32_t vgpr_granulated) -> PatchOutcome { - auto local_image = image; - AmdGpuCodeObject probe(local_image.data(), local_image.size()); - if (!probe.is_valid()) - return {}; - const Section *rodata = find_section(probe, ".rodata"); - if (rodata == nullptr) - return {}; + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); - auto descriptor = read_kernel_descriptor_for_test(rodata->data()); - descriptor.compute_pgm_rsrc3 = 0; - AMDHSA_BITS_SET(descriptor.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, - source_shared); - write_kernel_descriptor_for_test(local_image.data() + rodata->sectionOffset(), descriptor); + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_NE(result.elf_bytes, image); + AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_TRUE(translated.is_valid()); + ASSERT_EQ(translated.text_sections().size(), 1u); + const Section *translated_text = translated.text_sections().front(); + const auto translated_words = + std::span(reinterpret_cast(translated_text->data()), + translated_text->size() / sizeof(uint32_t)); + EXPECT_EQ(std::ranges::count(translated_words, source_clause[0]), 0); + EXPECT_EQ(std::ranges::count(translated_words, target_nop[0]), 1); +} - AmdGpuCodeObject seeded(local_image.data(), local_image.size()); - if (!seeded.is_valid()) - return {}; +TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresUnreferencedLocalTextLabel) { + constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); + constexpr auto cluster = + cdna5::build_vglobal(cdna5::kClusterLoadB32Vglobal, {.saddr = 124, .vdst = 8, .vaddr = 12}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + const std::vector words = {clear_m0[0], cluster[0], cluster[1], cluster[2], + kGfx1250SEndpgm}; + auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(words, words.size()); - KdTranslation translation{}; - translation.descriptor_file_offset = rodata->sectionOffset(); - translation.target_wave_size = target_wave; - translation.target_vgpr_granulated = vgpr_granulated; + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + std::swap(symbols[1], symbols[2]); + symbols[1].st_info = elf_symbol_info(kElfSymbolBindLocal, kElfSymbolTypeFunc); + symbols[1].st_shndx = static_cast(text_it - shdrs.begin()); + symbols[1].st_value = text_it->sh_addr + sizeof(uint32_t); + symbols[1].st_size = 4 * sizeof(uint32_t); + symtab_it->sh_info = 2; + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); + ASSERT_EQ(translated.text_sections().size(), 1u); + const Section *translated_text = translated.text_sections().front(); + const auto translated_words = + std::span(reinterpret_cast(translated_text->data()), + translated_text->size() / sizeof(uint32_t)); + EXPECT_EQ(std::ranges::count(translated_words, cluster[0]), 1) + << "an unreferenced local label must not be treated as another executable body"; +} + +TEST(BinaryTranslatorE2E, RewriteDischargeHonorsRelocationBackedLocalTextEntry) { + for (const uint32_t relocation_type : kSupportedExplicitSymbolRelocations) { + SCOPED_TRACE(relocation_type); + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, true, /*addend=*/0, + relocation_type); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + constexpr auto compound = cdna5::build_vop3p( + cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272}); + static_assert(compound.size() == 2); + write_bytes_for_test(image, text_it->sh_offset, compound.data(), sizeof(compound)); + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 2u); + symbols[1].st_info = elf_symbol_info(kElfSymbolBindLocal, kElfSymbolTypeFunc); + symbols[1].st_value = text_it->sh_addr + sizeof(uint32_t); + symbols[1].st_size = sizeof(uint32_t); + symtab_it->sh_info = 2; + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + const auto diagnostic = std::ranges::find_if(result.diagnostics, [](const auto &candidate) { + return candidate.kind == DiagnosticKind::ResidualRewrite; + }); + ASSERT_NE(diagnostic, result.diagnostics.end()); + EXPECT_EQ(diagnostic->message, + "rewrite-discharge verification found an invalid final executable entry"); + } +} + +TEST(BinaryTranslatorE2E, PreservesEtRelNotypeAbs64EntryPolicy) { + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeNone, /*defined_in_text=*/true, + /*addend=*/0, R_AMDGPU_ABS64); + auto ehdr = read_elf_struct_for_test(image, 0); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto data_it = std::ranges::find_if(shdrs, [](const Elf64_Shdr §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(data_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + + ehdr.e_type = ET_REL; + ehdr.e_flags = EF_AMDGPU_MACH_AMDGCN_GFX1250; + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 2u); + symbols[1].st_value = sizeof(uint32_t); + auto rela = read_elf_struct_for_test(image, rela_it->sh_offset); + rela.r_offset = 0; + rela_it->sh_info = static_cast(data_it - shdrs.begin()); + + constexpr auto compound = cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272}); + write_bytes_for_test(image, text_it->sh_offset, compound.data(), sizeof(compound)); + write_elf_struct_for_test(image, 0, ehdr); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + write_elf_struct_for_test(image, rela_it->sh_offset, rela); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + CodeObjectPatcher patcher(source); + EXPECT_FALSE(patcher.has_unsupported_relocation_to_text()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(has_error_containing(result, DiagnosticKind::Legalization, + "unsupported relocation referencing .text")); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::ResidualRewrite, + "invalid final executable entry")); +} + +TEST(BinaryTranslatorE2E, PreservesExplicitTargetStaticRelocationPolicy) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .relocation_type = kUnrecognizedAmdGpuRelocation, + .target_text_offset = sizeof(uint32_t), + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto rodata_it = std::ranges::find_if(shdrs, [](const Elf64_Shdr §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(rodata_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + rela_it->sh_info = static_cast(rodata_it - shdrs.begin()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + CodeObjectPatcher patcher(source); + EXPECT_FALSE(patcher.has_unsupported_relocation_to_text()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); +} + +TEST(BinaryTranslatorE2E, ExplicitTargetNonAbs64FunctionReferenceCreatesTextEntry) { + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, /*defined_in_text=*/true, + /*addend=*/0, kUnrecognizedAmdGpuRelocation); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto data_it = std::ranges::find_if(shdrs, [](const Elf64_Shdr §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(data_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + + constexpr auto compound = cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272}); + static_assert(compound.size() == 2); + write_bytes_for_test(image, text_it->sh_offset, compound.data(), sizeof(compound)); + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 2u); + symbols[1].st_value = text_it->sh_addr + sizeof(uint32_t); + symbols[1].st_size = sizeof(uint32_t); + rela_it->sh_info = static_cast(data_it - shdrs.begin()); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + CodeObjectPatcher patcher(source); + EXPECT_FALSE(patcher.has_unsupported_relocation_to_text()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::ResidualRewrite, + "invalid final executable entry")); +} + +TEST(BinaryTranslatorE2E, RejectsDynamicNoneBeforeResolvingSymbolMetadata) { + constexpr auto compound = cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272}); + static_assert(compound.size() == 2); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {compound[0], compound[1], kGfx1250SEndpgm}, + TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .relocation_type = R_AMDGPU_NONE, + .target_text_offset = sizeof(uint32_t), + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto rodata_it = std::ranges::find_if(shdrs, [](const Elf64_Shdr §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(rodata_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + + // Keep the second kernel entry at the instruction following the compound. + // Offset four is then referenced only by the target-less dynamic NONE record. + // Poison both ways entry discovery could reach its symbol: record-level NONE + // rejection must win before sh_link or the symbol index is inspected. + write_kernel_descriptor_entry_offset( + image.data() + rodata_it->sh_offset + kKernelDescriptorSize, + static_cast(text_it->sh_addr + sizeof(compound)) - + static_cast(rodata_it->sh_addr + kKernelDescriptorSize)); + rela_it->sh_link = static_cast(shdrs.size()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + auto rela = read_elf_struct_for_test(image, rela_it->sh_offset); + rela.r_offset = text_it->sh_addr; + rela.r_info = (static_cast(99) << 32) | R_AMDGPU_NONE; + rela.r_addend = 17; + write_elf_struct_for_test(image, rela_it->sh_offset, rela); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + CodeObjectPatcher patcher(source); + EXPECT_FALSE(patcher.has_relocations_within_text()); + EXPECT_TRUE(patcher.has_rocr_rejected_none_relocation()); + EXPECT_FALSE(patcher.has_unsupported_relocation_to_text()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "R_AMDGPU_NONE outside a valid explicit-target")); + EXPECT_FALSE(has_error_containing(result, DiagnosticKind::ResourceLimit, + "could not recover relocation-backed executable entries")); +} + +TEST(BinaryTranslatorE2E, RejectsDynamicNoneBeforeInspectingInvalidPlace) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .relocation_type = R_AMDGPU_NONE, + .target_text_offset = 0, + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + const auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(rela_it, shdrs.end()); + auto relocation = read_elf_struct_for_test(image, rela_it->sh_offset); + relocation.r_offset = std::numeric_limits::max(); + relocation.r_info = R_AMDGPU_NONE; + write_elf_struct_for_test(image, rela_it->sh_offset, relocation); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "R_AMDGPU_NONE outside a valid explicit-target")); +} + +TEST(BinaryTranslatorE2E, IgnoresTargetlessShtRelNoneLikeRocr) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .relocation_type = R_AMDGPU_NONE, + .target_text_offset = 0, + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(rela_it, shdrs.end()); + const size_t relocation_section_index = static_cast(rela_it - shdrs.begin()); + const Elf64_Rel rel{.r_offset = std::numeric_limits::max(), .r_info = R_AMDGPU_NONE}; + write_elf_struct_for_test(image, rela_it->sh_offset, rel); + shdrs[relocation_section_index].sh_type = SHT_REL; + shdrs[relocation_section_index].sh_size = sizeof(Elf64_Rel); + shdrs[relocation_section_index].sh_entsize = sizeof(Elf64_Rel); + shdrs[relocation_section_index].sh_link = static_cast(shdrs.size()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + CodeObjectPatcher patcher(source); + EXPECT_FALSE(patcher.has_rocr_rejected_none_relocation()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); +} + +TEST(BinaryTranslatorE2E, IgnoresExplicitTargetNoneRelocationToTextSymbol) { + constexpr auto compound = cdna5::build_vop3p(cdna5::kVWmmaF3216x16x128F8f6f4Vop3p, + {.vdst = 8, .src0 = 256, .src1 = 264, .src2 = 272}); + static_assert(compound.size() == 2); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {compound[0], compound[1], kGfx1250SEndpgm}, + TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .relocation_type = R_AMDGPU_NONE, + .target_text_offset = sizeof(uint32_t), + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto rodata_it = std::ranges::find_if(shdrs, [](const Elf64_Shdr §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(rodata_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + + // ROCr skips explicit-target/static relocation sections for supported code objects. + // Point this record at allocated data and make its symbol-table link unusable. NONE must be + // ignored before entry recovery resolves that metadata, so it neither creates the otherwise + // invalid entry at the compound instruction's second dword nor requires symbol remapping. + rela_it->sh_info = static_cast(rodata_it - shdrs.begin()); + rela_it->sh_link = static_cast(shdrs.size()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + write_kernel_descriptor_entry_offset( + image.data() + rodata_it->sh_offset + kKernelDescriptorSize, + static_cast(text_it->sh_addr + sizeof(compound)) - + static_cast(rodata_it->sh_addr + kKernelDescriptorSize)); + auto rela = read_elf_struct_for_test(image, rela_it->sh_offset); + rela.r_offset = text_it->sh_addr; + rela.r_addend = 17; + write_elf_struct_for_test(image, rela_it->sh_offset, rela); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + CodeObjectPatcher patcher(source); + EXPECT_FALSE(patcher.has_relocations_within_text()); + EXPECT_FALSE(patcher.has_rocr_rejected_none_relocation()); + EXPECT_FALSE(patcher.has_unsupported_relocation_to_text()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); +} + +TEST(BinaryTranslatorE2E, RejectsUnsupportedSymbolRelocationsToText) { + for (const uint32_t relocation_type : kUnsupportedExplicitSymbolRelocations) { + SCOPED_TRACE(relocation_type); + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, true, /*addend=*/0, + relocation_type); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "unsupported relocation referencing .text")); + } +} + +TEST(BinaryTranslatorE2E, RejectsUnsupportedRelocationBackedTextSymbolTypes) { + for (const uint8_t symbol_type : {kElfSymbolTypeNone, kUnsupportedRuntimeSymbolType}) { + SCOPED_TRACE(static_cast(symbol_type)); + auto image = make_amdgpu_elf_with_symbol_relocation(symbol_type, /*defined_in_text=*/true); + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "unsupported relocation referencing .text")); + } +} + +TEST(BinaryTranslatorE2E, RewriteDischargeDoesNotPromoteRelocationBackedNonEntrySymbol) { + for (const uint8_t symbol_type : {kElfSymbolTypeObject, kElfSymbolTypeAmdGpuHsaKernel}) { + SCOPED_TRACE(static_cast(symbol_type)); + auto image = make_amdgpu_elf_with_symbol_relocation( + symbol_type, true, /*addend=*/0, kSupportedExplicitSymbolRelocations.front()); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + constexpr auto compound = + cdna5::build_vop3(cdna5::kVAddF32Vop3, {.vdst = 8, .src0 = 256, .src1 = 257, .src2 = 0}); + static_assert(compound.size() == 2); + write_bytes_for_test(image, text_it->sh_offset, compound.data(), sizeof(compound)); + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 2u); + symbols[1].st_value = text_it->sh_addr + sizeof(uint32_t); + symbols[1].st_size = sizeof(uint32_t); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_TRUE(result.ok()); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + } +} + +TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresExplicitNonAllocatedRelocation) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .target_text_offset = 2, + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto strtab_it = std::ranges::find_if(shdrs, [&](const Elf64_Shdr §ion) { + return section.sh_type == SHT_STRTAB && + static_cast(§ion - shdrs.data()) != ehdr.e_shstrndx; + }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(strtab_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + + rela_it->sh_info = static_cast(strtab_it - shdrs.begin()); + rela_it->sh_entsize = 0; + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); +} + +TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresMalformedUnreferencedSymbolTable) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + constexpr std::array unused_symbols{}; + + for (const uint64_t entry_size : {uint64_t{0}, uint64_t{sizeof(unused_symbols)}}) { + SCOPED_TRACE(entry_size); + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Relative64, + .target_text_offset = 0, + }); + const auto header = read_elf_struct_for_test(image, 0); + const auto sections = + read_elf_array_for_test(image, header.e_shoff, header.e_shnum); + const auto valid_symtab = std::ranges::find_if( + sections, [](const Elf64_Shdr &candidate) { return candidate.sh_type == SHT_SYMTAB; }); + ASSERT_NE(valid_symtab, sections.end()); + + Elf64_Shdr irrelevant_symtab{}; + irrelevant_symtab.sh_name = valid_symtab->sh_name; + irrelevant_symtab.sh_type = SHT_SYMTAB; + irrelevant_symtab.sh_link = valid_symtab->sh_link; + irrelevant_symtab.sh_addralign = alignof(Elf64_Sym); + irrelevant_symtab.sh_entsize = entry_size; + append_elf_section_for_test(image, irrelevant_symtab, unused_symbols); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + } +} + +TEST(BinaryTranslatorE2E, RejectsAllocatedExecutableNobitsSections) { + for (const bool replace_text : {false, true}) { + SCOPED_TRACE(replace_text); + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + const auto header = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto sections = read_elf_array_for_test(image, header.e_shoff, header.e_shnum); + Elf64_Shdr &nobits = sections[replace_text ? 1 : 2]; + nobits.sh_type = SHT_NOBITS; + nobits.sh_flags = SHF_ALLOC | SHF_EXECINSTR; + nobits.sh_offset = image.size() + 0x1000; + write_bytes_for_test(image, header.e_shoff, sections.data(), + sections.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + EXPECT_EQ(source.allocated_executable_sections().size(), replace_text ? 1u : 2u); + EXPECT_EQ(source.text_sections().size(), replace_text ? 0u : 1u); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "exactly one allocated executable section named .text")); + } +} + +TEST(BinaryTranslatorE2E, UsesActualTextSectionIndexForRelocationBackedEntries) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .target_text_offset = 2, + }); + const auto header = read_elf_struct_for_test(image, 0); + auto sections = read_elf_array_for_test(image, header.e_shoff, header.e_shnum); + const auto text = std::ranges::find_if(sections, [](const Elf64_Shdr &candidate) { + return (candidate.sh_flags & SHF_EXECINSTR) != 0; + }); + ASSERT_NE(text, sections.end()); + ASSERT_GT(text - sections.begin(), 0); + + // A preceding NOBITS header may legally reuse the text section's file offset. + // Section identity, not the non-unique (offset, size) pair, must decide which + // symbol-table section index denotes executable code. + Elf64_Shdr &collision = sections[static_cast(text - sections.begin() - 1)]; + collision.sh_type = SHT_NOBITS; + collision.sh_offset = text->sh_offset; + collision.sh_size = text->sh_size; + write_bytes_for_test(image, header.e_shoff, sections.data(), + sections.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + ASSERT_EQ(source.text_sections().size(), 1u); + ASSERT_EQ(source.text_sections().front()->sectionHeaderIndex(), + std::optional(static_cast(text - sections.begin()))); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "translation found an invalid executable entry")); +} + +TEST(BinaryTranslatorE2E, TranslationFailsClosedOnMalformedAllocatedRelocation) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm}, TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Abs64, + .target_text_offset = 0, + }); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(rela_it, shdrs.end()); + rela_it->sh_link = static_cast(shdrs.size()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + const auto diagnostic = std::ranges::find_if(result.diagnostics, [](const auto &candidate) { + return candidate.kind == DiagnosticKind::Legalization; + }); + ASSERT_NE(diagnostic, result.diagnostics.end()); + EXPECT_EQ(diagnostic->message, + "translation could not recover relocation-backed executable entries"); +} + +TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresUnreferencedVisibleSymbolMetadata) { + constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); + constexpr auto cluster = + cdna5::build_vglobal(cdna5::kClusterLoadB32Vglobal, {.saddr = 124, .vdst = 8, .vaddr = 12}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + constexpr std::array target_deltas = { + static_cast(sizeof(uint32_t)), + -static_cast(sizeof(uint32_t)), + }; + + for (const int64_t target_delta : target_deltas) { + SCOPED_TRACE(target_delta); + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {clear_m0[0], cluster[0], cluster[1], cluster[2], kGfx1250SEndpgm}); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + const auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + symbols[1].st_info = elf_symbol_info(kElfSymbolBindGlobal, kElfSymbolTypeFunc); + symbols[1].st_shndx = static_cast(text_it - shdrs.begin()); + symbols[1].st_value = text_it->sh_addr; + symbols[1].st_size = sizeof(uint32_t); + symbols[2].st_info = elf_symbol_info(kElfSymbolBindGlobal, kElfSymbolTypeFunc); + symbols[2].st_shndx = static_cast(text_it - shdrs.begin()); + symbols[2].st_value = + static_cast(static_cast(text_it->sh_addr) + target_delta); + symbols[2].st_size = sizeof(uint32_t); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + } +} + +TEST(BinaryTranslatorE2E, TranslationFailsClosedOnMultipleExecutableSections) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + ASSERT_GE(shdrs.size(), 3u); + shdrs[2].sh_flags |= SHF_EXECINSTR; + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + ASSERT_EQ(source.text_sections().size(), 1u); + ASSERT_EQ(source.allocated_executable_sections().size(), 2u); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + const auto diagnostic = std::ranges::find_if(result.diagnostics, [](const auto &candidate) { + return candidate.kind == DiagnosticKind::Legalization; + }); + ASSERT_NE(diagnostic, result.diagnostics.end()); + EXPECT_EQ(diagnostic->severity, DiagnosticSeverity::Error); + EXPECT_EQ(diagnostic->guest_offset, std::nullopt); + EXPECT_EQ(diagnostic->output_offset, std::nullopt); + EXPECT_TRUE(diagnostic->mnemonic.empty()); + EXPECT_EQ(diagnostic->message, + "translation requires exactly one allocated executable section named .text"); +} + +TEST(BinaryTranslatorE2E, TranslationRejectsSoleExecutableSectionNotNamedText) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + ASSERT_GE(shdrs.size(), 3u); + shdrs[1].sh_name = shdrs[2].sh_name; + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + ASSERT_TRUE(source.text_sections().empty()); + ASSERT_EQ(source.allocated_executable_sections().size(), 1u); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(has_error_containing( + result, DiagnosticKind::Legalization, + "translation requires exactly one allocated executable section named .text")); +} + +TEST(BinaryTranslatorE2E, TranslationRejectsMalformedNameOnAdditionalExecutableSection) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + ASSERT_GE(shdrs.size(), 3u); + shdrs[2].sh_flags |= SHF_EXECINSTR; + shdrs[2].sh_name = std::numeric_limits::max(); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_FALSE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::ResourceLimit, + "translation could not parse input code object")); +} + +TEST(BinaryTranslatorE2E, TranslationRejectsMalformedNameOnSoleExecutableSection) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + ASSERT_GE(shdrs.size(), 3u); + shdrs[1].sh_name = std::numeric_limits::max(); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_FALSE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::ResourceLimit, + "translation could not parse input code object")); +} + +TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresUnreferencedVisibleTextSymbolEntry) { + constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); + constexpr auto cluster = + cdna5::build_vglobal(cdna5::kClusterLoadB32Vglobal, {.saddr = 124, .vdst = 8, .vaddr = 12}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + + for (const uint8_t symbol_type : {kElfSymbolTypeFunc, kElfSymbolTypeNone}) { + SCOPED_TRACE(symbol_type == kElfSymbolTypeFunc ? "STT_FUNC" : "STT_NOTYPE"); + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {clear_m0[0], cluster[0], cluster[1], cluster[2], kGfx1250SEndpgm}); + + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + const auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(symtab_it, shdrs.end()); + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + symbols[1].st_info = elf_symbol_info(kElfSymbolBindGlobal, symbol_type); + symbols[1].st_shndx = 1; + symbols[1].st_value = 0x1100; + symbols[1].st_size = sizeof(uint32_t); + symbols[2].st_info = elf_symbol_info(kElfSymbolBindGlobal, symbol_type); + symbols[2].st_shndx = 1; + symbols[2].st_value = 0x1100 + sizeof(uint32_t); + symbols[2].st_size = 4 * sizeof(uint32_t); + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" + : result.diagnostics.front().message); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_TRUE(result.rewrite_discharge_verified); + } +} + +TEST(BinaryTranslatorE2E, RewriteDischargeDoesNotCreditPredecessorAcrossRelativeEntry) { + constexpr auto clear_m0 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); + constexpr auto cluster = + cdna5::build_vglobal(cdna5::kClusterLoadB32Vglobal, {.saddr = 124, .vdst = 8, .vaddr = 12}); + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {clear_m0[0], cluster[0], cluster[1], cluster[2], kGfx1250SEndpgm}); + + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto data_it = std::ranges::find_if(shdrs, [](const Elf64_Shdr §ion) { + return section.sh_type == SHT_PROGBITS && (section.sh_flags & SHF_ALLOC) != 0 && + (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(data_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + for (size_t symbol_index = 1; symbol_index < symbols.size(); ++symbol_index) { + symbols[symbol_index].st_shndx = SHN_UNDEF; + symbols[symbol_index].st_value = 0; + symbols[symbol_index].st_size = 0; + } + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + + Elf64_Rela relocation{}; + relocation.r_offset = data_it->sh_addr; + relocation.r_info = R_AMDGPU_RELATIVE64; + relocation.r_addend = + static_cast(text_it->sh_addr + static_cast(sizeof(uint32_t))); + write_bytes_for_test(image, data_it->sh_offset, &relocation, sizeof(relocation)); + + data_it->sh_type = SHT_RELA; + data_it->sh_size = sizeof(Elf64_Rela); + data_it->sh_link = static_cast(symtab_it - shdrs.begin()); + data_it->sh_info = 0; + data_it->sh_addralign = alignof(Elf64_Rela); + data_it->sh_entsize = sizeof(Elf64_Rela); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(result.rewrite_discharge_checked); + EXPECT_FALSE(result.rewrite_discharge_verified); + const auto residual = std::ranges::find_if(result.diagnostics, [](const auto &diagnostic) { + return diagnostic.kind == DiagnosticKind::ResidualRewrite; + }); + ASSERT_NE(residual, result.diagnostics.end()); + EXPECT_EQ(residual->severity, DiagnosticSeverity::Error); + EXPECT_EQ(residual->output_offset, std::optional(sizeof(uint32_t))); + EXPECT_EQ(residual->mnemonic, "cluster_load_b32"); +} + +TEST(BinaryTranslatorE2E, RejectsRelocationBackedEntryOutsideKernelTranslationScopes) { + constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; + constexpr uint32_t kGfx1250SNop = 0xBF800000u; + auto image = make_minimal_amdgpu_elf_with_two_kernel_descriptors( + {kGfx1250SEndpgm, kGfx1250SEndpgm, kGfx1250SNop}, + TestRuntimeTextReference{ + .relocation = TestRuntimeTextRelocation::Relative64, + .target_text_offset = 2 * sizeof(uint32_t), + }); + + const auto ehdr = read_elf_struct_for_test(image, 0); + write_value_for_test(image, offsetof(Elf64_Ehdr, e_flags), + EF_AMDGPU_MACH_AMDGCN_GFX1250); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto text_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return (section.sh_flags & SHF_EXECINSTR) != 0; }); + const auto symtab_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_SYMTAB; }); + ASSERT_NE(text_it, shdrs.end()); + ASSERT_NE(symtab_it, shdrs.end()); + + auto symbols = read_elf_array_for_test(image, symtab_it->sh_offset, + symtab_it->sh_size / sizeof(Elf64_Sym)); + ASSERT_EQ(symbols.size(), 3u); + symbols[1].st_shndx = SHN_UNDEF; + symbols[1].st_value = 0; + symbols[1].st_size = 0; + write_bytes_for_test(image, symtab_it->sh_offset, symbols.data(), + symbols.size() * sizeof(Elf64_Sym)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_FALSE(result.rewrite_discharge_checked) + << "required runtime entries must be enforced during ordinary translation"; + const auto diagnostic = std::ranges::find_if(result.diagnostics, [](const auto &candidate) { + return candidate.kind == DiagnosticKind::Legalization && + candidate.message == + "relocation-backed executable entry is outside every kernel translation scope"; + }); + ASSERT_NE(diagnostic, result.diagnostics.end()); + EXPECT_EQ(diagnostic->severity, DiagnosticSeverity::Error); + EXPECT_EQ(diagnostic->guest_offset, 2 * sizeof(uint32_t)); +} + +TEST(CodeObjectPatcher, ReplaceTextGrowsTextAndShiftsFollowingSections) { + auto image = make_minimal_amdgpu_elf_with_text_and_rodata(); + AmdGpuCodeObject co(image.data(), image.size()); + ASSERT_TRUE(co.is_valid()); + ASSERT_FALSE(co.text_sections().empty()); + + CodeObjectPatcher patcher(co); + const std::array text_words = {0xBF800000u, 0xBF800000u, 0xDEADBEEFu, 0xCAFEBABEu}; + const auto *text_bytes = reinterpret_cast(text_words.data()); + ASSERT_TRUE(patcher.replace_text({text_bytes, text_words.size() * sizeof(uint32_t)})); + + auto patched_bytes = patcher.emit(); + AmdGpuCodeObject patched(patched_bytes.data(), patched_bytes.size()); + ASSERT_TRUE(patched.is_valid()); + ASSERT_FALSE(patched.text_sections().empty()); + + const Section *text = patched.text_sections()[0]; + ASSERT_NE(text, nullptr); + EXPECT_EQ(text->size(), text_words.size() * sizeof(uint32_t)); + ASSERT_EQ(patched.text_sections().size(), 1u); + EXPECT_EQ(patched.text_sections()[0]->name(), ".text"); + EXPECT_EQ(find_section(patched, ".rj_translations"), nullptr); + EXPECT_EQ(std::memcmp(text->data(), text_words.data(), text->size()), 0); + + const Section *rodata = find_section(patched, ".rodata"); + ASSERT_NE(rodata, nullptr); + EXPECT_EQ(rodata->sectionOffset(), text->sectionOffset() + text->size()) + << "sections following .text must be shifted after the grown text"; + uint32_t rodata_word = 0; + std::memcpy(&rodata_word, rodata->data(), sizeof(rodata_word)); + EXPECT_EQ(rodata_word, 0xA5A55A5Au); +} + +// COMPUTE_PGM_RSRC3 is carried over verbatim only when source and target agree on its layout. +// "GFX10 or later" is not a fine enough test: INST_PREF_SIZE is GFX11+, and IMAGE_OP is GFX11+, +// so handing a GFX11 or GFX12 word to a GFX10 target would set bits GFX10 requires to be zero. +// Equally, a GFX12 word must survive intact on a GFX12 target, including the GFX125-only +// NAMED_BAR_CNT and an INST_PREF_SIZE above the 63 that GFX11's narrower field can hold. +TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { + using namespace rocr::llvm::amdhsa; + + const auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(); + AmdGpuCodeObject probe(image.data(), image.size()); + ASSERT_TRUE(probe.is_valid()); + const Section *probe_rodata = find_section(probe, ".rodata"); + ASSERT_NE(probe_rodata, nullptr); + ASSERT_GE(probe_rodata->size(), sizeof(kernel_descriptor_t)); + + // A GFX12-shaped source word: INST_PREF_SIZE beyond GFX11's 6-bit range, plus a GFX125-only + // named-barrier allocation. + uint32_t source_rsrc3 = 0; + AMDHSA_BITS_SET(source_rsrc3, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE, 107u); + AMDHSA_BITS_SET(source_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT, 3u); + + auto patched_rsrc3 = [&](rj_code_arch_t source_arch, + rj_code_arch_t target_arch) -> std::optional { + auto local_image = image; + AmdGpuCodeObject local_co(local_image.data(), local_image.size()); + if (!local_co.is_valid()) + return std::nullopt; + const Section *rodata = find_section(local_co, ".rodata"); + if (rodata == nullptr) + return std::nullopt; + + auto descriptor = read_kernel_descriptor_for_test(rodata->data()); + descriptor.compute_pgm_rsrc3 = source_rsrc3; + write_kernel_descriptor_for_test(local_image.data() + rodata->sectionOffset(), descriptor); + + AmdGpuCodeObject seeded(local_image.data(), local_image.size()); + if (!seeded.is_valid()) + return std::nullopt; + + KdTranslation translation{}; + translation.descriptor_file_offset = rodata->sectionOffset(); + translation.target_wave_size = 32; + translation.source_arch = source_arch; + + CodeObjectPatcher patcher(seeded); + if (!patcher.apply_kernel_descriptor_translation(translation, target_arch)) + return std::nullopt; + const auto patched_image = patcher.emit(); + return read_kernel_descriptor_for_test(patched_image.data() + + translation.descriptor_file_offset) + .compute_pgm_rsrc3; + }; + + // Matching layout: carried verbatim, both the wide INST_PREF_SIZE and NAMED_BAR_CNT. + const auto same_layout = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_TRUE(same_layout.has_value()); + EXPECT_EQ(*same_layout, source_rsrc3); + EXPECT_EQ(AMDHSA_BITS_GET(*same_layout, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE), 107u); + EXPECT_EQ(AMDHSA_BITS_GET(*same_layout, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 3u); + + // GFX10 targets have no INST_PREF_SIZE and no IMAGE_OP; the GFX12 word must not be inherited. + for (const rj_code_arch_t gfx10 : {ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2}) { + const auto rebuilt = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, gfx10); + ASSERT_TRUE(rebuilt.has_value()); + EXPECT_NE(*rebuilt, source_rsrc3); + EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE), 0u) + << "GFX10 reserves the INST_PREF_SIZE bits and requires them to be zero"; + } + + // A GFX9/CDNA source encodes ACCUM_OFFSET here, so it is rebuilt for a GFX12 target. + const auto from_cdna = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_TRUE(from_cdna.has_value()); + EXPECT_NE(*from_cdna, source_rsrc3); + EXPECT_EQ(AMDHSA_BITS_GET(*from_cdna, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 0u); + + // The narrow case: GFX11 -> GFX10. Both are "GFX10+" and both use SHARED_VGPR_COUNT, so a + // coarse family check treats them as interchangeable -- but GFX11's INST_PREF_SIZE at 9:4 and + // IMAGE_OP at 31 are reserved on GFX10 and must not be carried over. + uint32_t gfx11_rsrc3 = 0; + AMDHSA_BITS_SET(gfx11_rsrc3, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE, 21u); + AMDHSA_BITS_SET(gfx11_rsrc3, COMPUTE_PGM_RSRC3_GFX10_PLUS_IMAGE_OP, 1u); + source_rsrc3 = gfx11_rsrc3; + for (const rj_code_arch_t gfx10 : {ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2}) { + const auto rebuilt = patched_rsrc3(ROCJITSU_CODE_ARCH_RDNA3, gfx10); + ASSERT_TRUE(rebuilt.has_value()); + EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE), 0u) + << "GFX10 reserves INST_PREF_SIZE; a GFX11 word must not be carried over"; + EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_IMAGE_OP), 0u) + << "IMAGE_OP is GFX11+; GFX10 reserves bit 31"; + } + + // GFX11 -> GFX11 still round-trips, so the split does not over-rebuild. + const auto gfx11_same = patched_rsrc3(ROCJITSU_CODE_ARCH_RDNA3, ROCJITSU_CODE_ARCH_RDNA3); + ASSERT_TRUE(gfx11_same.has_value()); + EXPECT_EQ(*gfx11_same, gfx11_rsrc3); + + // GFX125 -> GFX120. Both are GFX12, and both use the same 8-bit INST_PREF_SIZE, but LLVM + // reserves bits 21:14 on GFX120 while GFX125 fills them with NAMED_BAR_CNT, + // ENABLE_DYNAMIC_VGPR, TCP_SPLIT and ENABLE_DIDT_THROTTLE. A shared "GFX12+" bucket would + // carry those straight into target-reserved bits. + uint32_t gfx125_rsrc3 = 0; + AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE, 107u); + AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT, 3u); + AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT, 5u); + AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR, 1u); + source_rsrc3 = gfx125_rsrc3; + const auto to_gfx120 = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_RDNA4); + ASSERT_TRUE(to_gfx120.has_value()); + EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 0u) + << "bits 21:14 are reserved on GFX120 and must not inherit GFX125 state"; + EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT), 0u); + EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR), 0u); + + // GFX125 -> GFX125 keeps all of it. + const auto gfx125_same = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_TRUE(gfx125_same.has_value()); + EXPECT_EQ(*gfx125_same, gfx125_rsrc3); +} + +// SHARED_VGPR_COUNT is the one carried field this patcher invalidates itself: it rewrites both +// the wave size and the RSRC1 VGPR allocation the field is constrained against. LLVM requires +// the count to be zero for wave32, and for wave64 requires +// (compute_pgm_rsrc1.vgprs + 1) * 4 + shared_vgpr_count * 8 <= 256. +// +// The field counts registers the unchanged kernel body uses, so a descriptor that no longer +// leaves room for them is refused rather than clamped: clamping would keep the body's demand +// while shrinking what the descriptor reserves for it. +TEST(CodeObjectPatcher, SharedVgprCountIsReconciledWithTheTargetAllocation) { + using namespace rocr::llvm::amdhsa; + + const auto image = make_minimal_amdgpu_elf_with_descriptor_after_text(); + + struct PatchOutcome { + bool seeded = false; ///< Fixture setup succeeded. + bool patched = false; ///< The patcher accepted the request. + uint32_t shared_count = 0; + }; + + auto patched = [&](uint32_t source_shared, uint32_t target_wave, + uint32_t vgpr_granulated) -> PatchOutcome { + auto local_image = image; + AmdGpuCodeObject probe(local_image.data(), local_image.size()); + if (!probe.is_valid()) + return {}; + const Section *rodata = find_section(probe, ".rodata"); + if (rodata == nullptr) + return {}; + + auto descriptor = read_kernel_descriptor_for_test(rodata->data()); + descriptor.compute_pgm_rsrc3 = 0; + AMDHSA_BITS_SET(descriptor.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, + source_shared); + write_kernel_descriptor_for_test(local_image.data() + rodata->sectionOffset(), descriptor); + + AmdGpuCodeObject seeded(local_image.data(), local_image.size()); + if (!seeded.is_valid()) + return {}; + + KdTranslation translation{}; + translation.descriptor_file_offset = rodata->sectionOffset(); + translation.target_wave_size = target_wave; + translation.target_vgpr_granulated = vgpr_granulated; translation.source_arch = ROCJITSU_CODE_ARCH_RDNA3; PatchOutcome outcome; @@ -1541,6 +3028,153 @@ TEST(CodeObjectPatcher, DetectsRelocationsWithinText) { EXPECT_TRUE(text_patcher.has_relocations_within_text()); } +TEST(AmdGpuElf, ClassifiesRocrRelocationSectionModesAndActions) { + Elf64_Ehdr dynamic_header{}; + dynamic_header.e_type = ET_DYN; + std::array sections{}; + sections[1].sh_type = SHT_PROGBITS; + sections[1].sh_flags = SHF_ALLOC; + sections[2].sh_type = SHT_NULL; + Elf64_Shdr relocations{}; + relocations.sh_type = SHT_RELA; + Elf64_Sym function{}; + function.st_info = elf_symbol_info(kElfSymbolBindGlobal, kElfSymbolTypeFunc); + constexpr uint64_t abs64_info = (uint64_t{1} << 32) | R_AMDGPU_ABS64; + + const auto expect_actions = [&](RocrRelocationSectionMode expected_mode, + RocrNoneRelocationAction expected_none, + TextSymbolRelocationAction expected_abs64) { + const auto mode = classify_rocr_relocation_section(dynamic_header, sections, relocations); + EXPECT_EQ(mode, expected_mode); + EXPECT_EQ(classify_rocr_none_relocation(mode, R_AMDGPU_NONE), expected_none); + EXPECT_EQ(classify_text_symbol_relocation(mode, abs64_info, + /*has_explicit_addend=*/true, /*addend=*/0, function), + expected_abs64); + }; + + relocations.sh_info = SHN_UNDEF; + expect_actions(RocrRelocationSectionMode::Dynamic, RocrNoneRelocationAction::Rejected, + TextSymbolRelocationAction::RequiresExecutableEntry); + + relocations.sh_info = 1; + expect_actions(RocrRelocationSectionMode::ExplicitTarget, RocrNoneRelocationAction::Ignored, + TextSymbolRelocationAction::RequiresExecutableEntry); + + relocations.sh_info = 2; + expect_actions(RocrRelocationSectionMode::Malformed, RocrNoneRelocationAction::Rejected, + TextSymbolRelocationAction::Unsupported); + + relocations.sh_info = static_cast(sections.size()); + expect_actions(RocrRelocationSectionMode::Malformed, RocrNoneRelocationAction::Rejected, + TextSymbolRelocationAction::Unsupported); + + dynamic_header.e_type = ET_REL; + relocations.sh_info = SHN_UNDEF; + expect_actions(RocrRelocationSectionMode::NotApplicable, RocrNoneRelocationAction::Ignored, + TextSymbolRelocationAction::RequiresExecutableEntry); +} + +TEST(CodeObjectPatcher, RejectsDynamicNoneBeforeInspectingPlaceOrSymbolMetadata) { + const auto mutate_relocation = [](std::vector image, auto mutate) { + const auto ehdr = read_elf_struct_for_test(image, 0); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + EXPECT_NE(rela_it, shdrs.end()); + if (rela_it == shdrs.end()) + return image; + const size_t rela_index = static_cast(rela_it - shdrs.begin()); + auto relocation = read_elf_struct_for_test(image, rela_it->sh_offset); + mutate(shdrs, rela_index, relocation); + write_elf_struct_for_test(image, rela_it->sh_offset, relocation); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + return image; + }; + const auto expect_rejected = [](std::string_view name, const std::vector &image) { + SCOPED_TRACE(name); + AmdGpuCodeObject object(image.data(), image.size()); + ASSERT_TRUE(object.is_valid()); + CodeObjectPatcher patcher(object); + EXPECT_TRUE(patcher.has_rocr_rejected_none_relocation()); + }; + const auto expect_malformed = [](std::string_view name, const std::vector &image) { + SCOPED_TRACE(name); + AmdGpuCodeObject object(image.data(), image.size()); + ASSERT_TRUE(object.is_valid()); + CodeObjectPatcher patcher(object); + EXPECT_TRUE(patcher.has_malformed_rocr_relocation_section()); + EXPECT_FALSE(patcher.has_rocr_rejected_none_relocation()) + << "malformed section metadata owns the loader rejection before record dispatch"; + }; + + expect_rejected("text symbol", make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, + /*addend=*/0, R_AMDGPU_NONE)); + expect_rejected("data symbol", make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeObject, /*defined_in_text=*/false, + /*addend=*/0, R_AMDGPU_NONE)); + + const auto base = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, R_AMDGPU_NONE); + expect_rejected("symbol zero", mutate_relocation(base, [](auto &, size_t, auto &relocation) { + relocation.r_info = R_AMDGPU_NONE; + })); + expect_rejected("out-of-range symbol", + mutate_relocation(base, [](auto &, size_t, auto &relocation) { + relocation.r_info = (static_cast(99) << 32) | R_AMDGPU_NONE; + })); + expect_rejected("invalid symbol table link", + mutate_relocation(base, [](auto &shdrs, size_t rela_index, auto &) { + shdrs[rela_index].sh_link = static_cast(shdrs.size()); + })); + expect_rejected("place inside text", + mutate_relocation(base, [](auto &, size_t, auto &relocation) { + relocation.r_offset = 0x1100; + })); + expect_rejected("place outside allocated storage", + mutate_relocation(base, [](auto &, size_t, auto &relocation) { + relocation.r_offset = std::numeric_limits::max(); + relocation.r_info = R_AMDGPU_NONE; + relocation.r_addend = 91; + })); + expect_malformed("out-of-range explicit target", + mutate_relocation(base, [](auto &shdrs, size_t rela_index, auto &) { + shdrs[rela_index].sh_info = static_cast(shdrs.size()); + })); + expect_malformed("explicit target naming SHT_NULL", + mutate_relocation(base, [](auto &shdrs, size_t rela_index, auto &) { + constexpr uint32_t target_index = 2; + shdrs[target_index].sh_type = SHT_NULL; + shdrs[rela_index].sh_info = target_index; + })); + + auto rel_image = mutate_relocation(base, [](auto &shdrs, size_t rela_index, auto &relocation) { + const Elf64_Rel rel{.r_offset = relocation.r_offset, .r_info = relocation.r_info}; + relocation = {}; + std::memcpy(&relocation, &rel, sizeof(rel)); + shdrs[rela_index].sh_type = SHT_REL; + shdrs[rela_index].sh_size = sizeof(Elf64_Rel); + shdrs[rela_index].sh_entsize = sizeof(Elf64_Rel); + }); + AmdGpuCodeObject rel_object(rel_image.data(), rel_image.size()); + ASSERT_TRUE(rel_object.is_valid()); + CodeObjectPatcher rel_patcher(rel_object); + EXPECT_FALSE(rel_patcher.has_rocr_rejected_none_relocation()) + << "ROCr does not materialize SHT_REL as a relocation section"; + EXPECT_FALSE(rel_patcher.has_unsupported_relocation_to_text()); + + AmdGpuCodeObject direct_object(base.data(), base.size()); + ASSERT_TRUE(direct_object.is_valid()); + CodeObjectPatcher direct_patcher(direct_object); + constexpr std::array replacement = {0xBF800000u, 0xBF800000u}; + constexpr std::array placements = { + TextOffsetRelocation{.source_offset = 0, .target_offset = 0}, + }; + const auto replacement_bytes = std::span( + reinterpret_cast(replacement.data()), sizeof(replacement)); + EXPECT_FALSE(direct_patcher.replace_text(replacement_bytes, placements)); +} + TEST(BinaryTranslatorE2E, RejectsRelocationTargetingText) { // A relocation whose place is inside .text cannot be remapped after DBT // relocates instructions, so translation must fail closed and leave the code @@ -1558,30 +3192,116 @@ TEST(BinaryTranslatorE2E, RejectsRelocationTargetingText) { } TEST(CodeObjectPatcher, ClassifiesTextSymbolRelocationCompatibility) { - for (uint8_t sym_type : {kElfSymbolTypeFunc, kElfSymbolTypeNone, kElfSymbolTypeObject}) { - auto text_image = make_amdgpu_elf_with_symbol_relocation(sym_type, /*defined_in_text=*/true); - AmdGpuCodeObject text_co(text_image.data(), text_image.size()); - ASSERT_TRUE(text_co.is_valid()) << "sym_type=" << static_cast(sym_type); - CodeObjectPatcher text_patcher(text_co); - EXPECT_FALSE(text_patcher.has_unsupported_relocation_to_text()) - << "zero-addend ordinary text sym_type=" << static_cast(sym_type) - << " can follow its relocated st_value"; - - auto data_image = make_amdgpu_elf_with_symbol_relocation(sym_type, /*defined_in_text=*/false); - AmdGpuCodeObject data_co(data_image.data(), data_image.size()); - ASSERT_TRUE(data_co.is_valid()) << "sym_type=" << static_cast(sym_type); - CodeObjectPatcher data_patcher(data_co); - EXPECT_FALSE(data_patcher.has_unsupported_relocation_to_text()) - << "data-defined sym_type=" << static_cast(sym_type) << " must be accepted"; + auto dynamic_none = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, R_AMDGPU_NONE); + AmdGpuCodeObject dynamic_none_co(dynamic_none.data(), dynamic_none.size()); + ASSERT_TRUE(dynamic_none_co.is_valid()); + CodeObjectPatcher dynamic_none_patcher(dynamic_none_co); + EXPECT_TRUE(dynamic_none_patcher.has_rocr_rejected_none_relocation()) + << "ROCr rejects NONE in a target-less dynamic relocation section"; + EXPECT_FALSE(dynamic_none_patcher.has_unsupported_relocation_to_text()) + << "dynamic NONE compatibility is a record-level, not a text-target, decision"; + + auto explicit_none = dynamic_none; + const auto explicit_none_ehdr = read_elf_struct_for_test(explicit_none, 0); + auto explicit_none_shdrs = read_elf_array_for_test( + explicit_none, explicit_none_ehdr.e_shoff, explicit_none_ehdr.e_shnum); + const auto explicit_none_data = + std::ranges::find_if(explicit_none_shdrs, [](const auto §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto explicit_none_rela = std::ranges::find_if( + explicit_none_shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(explicit_none_data, explicit_none_shdrs.end()); + ASSERT_NE(explicit_none_rela, explicit_none_shdrs.end()); + explicit_none_rela->sh_info = + static_cast(explicit_none_data - explicit_none_shdrs.begin()); + write_bytes_for_test(explicit_none, explicit_none_ehdr.e_shoff, explicit_none_shdrs.data(), + explicit_none_shdrs.size() * sizeof(Elf64_Shdr)); + AmdGpuCodeObject explicit_none_co(explicit_none.data(), explicit_none.size()); + ASSERT_TRUE(explicit_none_co.is_valid()); + CodeObjectPatcher explicit_none_patcher(explicit_none_co); + EXPECT_FALSE(explicit_none_patcher.has_rocr_rejected_none_relocation()); + EXPECT_FALSE(explicit_none_patcher.has_unsupported_relocation_to_text()) + << "ROCr skips explicit-target/static relocation sections for supported code objects"; + + for (const uint32_t relocation_type : kSupportedExplicitSymbolRelocations) { + for (uint8_t sym_type : + {kElfSymbolTypeFunc, kElfSymbolTypeObject, kElfSymbolTypeAmdGpuHsaKernel}) { + SCOPED_TRACE(relocation_type); + auto text_image = make_amdgpu_elf_with_symbol_relocation(sym_type, /*defined_in_text=*/true, + /*addend=*/0, relocation_type); + AmdGpuCodeObject text_co(text_image.data(), text_image.size()); + ASSERT_TRUE(text_co.is_valid()) << "sym_type=" << static_cast(sym_type); + CodeObjectPatcher text_patcher(text_co); + EXPECT_FALSE(text_patcher.has_unsupported_relocation_to_text()) + << "zero-addend ordinary text sym_type=" << static_cast(sym_type) + << " can follow its relocated st_value"; + + auto data_image = make_amdgpu_elf_with_symbol_relocation(sym_type, /*defined_in_text=*/false, + /*addend=*/0, relocation_type); + AmdGpuCodeObject data_co(data_image.data(), data_image.size()); + ASSERT_TRUE(data_co.is_valid()) << "sym_type=" << static_cast(sym_type); + CodeObjectPatcher data_patcher(data_co); + EXPECT_FALSE(data_patcher.has_unsupported_relocation_to_text()) + << "data-defined sym_type=" << static_cast(sym_type) << " must be accepted"; + } } - auto section_image = - make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeSection, /*defined_in_text=*/true); - AmdGpuCodeObject section_co(section_image.data(), section_image.size()); - ASSERT_TRUE(section_co.is_valid()); - CodeObjectPatcher section_patcher(section_co); - EXPECT_TRUE(section_patcher.has_unsupported_relocation_to_text()) - << "STT_SECTION keeps its in-text offset in the relocation addend"; + for (const uint8_t symbol_type : + {kElfSymbolTypeNone, kElfSymbolTypeSection, kUnsupportedRuntimeSymbolType}) { + SCOPED_TRACE(static_cast(symbol_type)); + auto image = make_amdgpu_elf_with_symbol_relocation(symbol_type, /*defined_in_text=*/true); + AmdGpuCodeObject co(image.data(), image.size()); + ASSERT_TRUE(co.is_valid()); + CodeObjectPatcher patcher(co); + EXPECT_TRUE(patcher.has_unsupported_relocation_to_text()) + << "ROCr does not derive this text symbol's runtime address from st_value"; + } + + for (const uint32_t relocation_type : kUnsupportedExplicitSymbolRelocations) { + SCOPED_TRACE(relocation_type); + auto image = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, relocation_type); + AmdGpuCodeObject co(image.data(), image.size()); + ASSERT_TRUE(co.is_valid()); + CodeObjectPatcher patcher(co); + EXPECT_TRUE(patcher.has_unsupported_relocation_to_text()) + << "a relocation that does not consume the symbol value cannot follow relocated .text"; + } + + auto null_target = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, R_AMDGPU_ABS64); + const auto null_target_ehdr = read_elf_struct_for_test(null_target, 0); + auto null_target_shdrs = read_elf_array_for_test( + null_target, null_target_ehdr.e_shoff, null_target_ehdr.e_shnum); + const auto null_target_data = std::ranges::find_if(null_target_shdrs, [](const auto §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto null_target_rela = std::ranges::find_if( + null_target_shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(null_target_data, null_target_shdrs.end()); + ASSERT_NE(null_target_rela, null_target_shdrs.end()); + null_target_data->sh_type = SHT_NULL; + null_target_rela->sh_info = static_cast(null_target_data - null_target_shdrs.begin()); + write_bytes_for_test(null_target, null_target_ehdr.e_shoff, null_target_shdrs.data(), + null_target_shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject null_target_co(null_target.data(), null_target.size()); + ASSERT_TRUE(null_target_co.is_valid()); + CodeObjectPatcher null_target_patcher(null_target_co); + EXPECT_TRUE(null_target_patcher.has_malformed_rocr_relocation_section()) + << "ROCr cannot parse a nonzero SHT_NULL section before relocation dispatch"; + EXPECT_FALSE(null_target_patcher.has_unsupported_relocation_to_text()) + << "malformed section metadata is not an established .text reference"; + + auto relative_image = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, R_AMDGPU_RELATIVE64); + AmdGpuCodeObject relative_co(relative_image.data(), relative_image.size()); + ASSERT_TRUE(relative_co.is_valid()); + CodeObjectPatcher relative_patcher(relative_co); + EXPECT_FALSE(relative_patcher.has_unsupported_relocation_to_text()) + << "RELATIVE64 derives its target from the addend, not the redundant symbol value"; auto addend_image = make_amdgpu_elf_with_symbol_relocation( kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/4); @@ -1619,6 +3339,106 @@ TEST(CodeObjectPatcher, ClassifiesTextSymbolRelocationCompatibility) { << "REL keeps an implicit addend that generic text-symbol remapping cannot inspect"; } +TEST(BinaryTranslatorE2E, RejectsMalformedRelocationWithNonzeroNullTarget) { + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, /*defined_in_text=*/true, + /*addend=*/0, R_AMDGPU_ABS64); + const auto ehdr = read_elf_struct_for_test(image, 0); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto data_it = std::ranges::find_if(shdrs, [](const auto §ion) { + return (section.sh_flags & SHF_ALLOC) != 0 && (section.sh_flags & SHF_EXECINSTR) == 0; + }); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(data_it, shdrs.end()); + ASSERT_NE(rela_it, shdrs.end()); + data_it->sh_type = SHT_NULL; + rela_it->sh_info = static_cast(data_it - shdrs.begin()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + BinaryTranslatorOptions options; + options.input_revision = ProcessorRevision::Gfx1250B0; + options.output_revision = ProcessorRevision::Gfx1250A0; + options.verify_rewrite_discharge = true; + BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + const auto result = translator.translate(source); + + EXPECT_FALSE(result.ok()); + EXPECT_EQ(result.elf_bytes, image); + EXPECT_TRUE(has_error_containing(result, DiagnosticKind::Legalization, + "malformed ROCr relocation-section metadata")); +} + +TEST(CodeObjectPatcher, RejectsLoaderInvalidRocrRelocationsWithoutTextMap) { + const auto expect_rejected = [](std::string_view name, auto mutate_sections) { + SCOPED_TRACE(name); + auto image = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, R_AMDGPU_ABS64); + const auto ehdr = read_elf_struct_for_test(image, 0); + auto shdrs = read_elf_array_for_test(image, ehdr.e_shoff, ehdr.e_shnum); + const auto rela_it = std::ranges::find_if( + shdrs, [](const Elf64_Shdr §ion) { return section.sh_type == SHT_RELA; }); + ASSERT_NE(rela_it, shdrs.end()); + mutate_sections(shdrs, *rela_it); + auto relocation = read_elf_struct_for_test(image, rela_it->sh_offset); + relocation.r_offset = std::numeric_limits::max(); + write_elf_struct_for_test(image, rela_it->sh_offset, relocation); + rela_it->sh_link = static_cast(shdrs.size()); + write_bytes_for_test(image, ehdr.e_shoff, shdrs.data(), shdrs.size() * sizeof(Elf64_Shdr)); + + AmdGpuCodeObject object(image.data(), image.size()); + ASSERT_TRUE(object.is_valid()); + CodeObjectPatcher patcher(object); + EXPECT_TRUE(patcher.has_malformed_rocr_relocation_section()); + EXPECT_FALSE(patcher.has_rocr_rejected_none_relocation()) + << "malformed section metadata owns the loader rejection before record dispatch"; + EXPECT_FALSE(patcher.has_unsupported_relocation_to_text()); + + std::vector replacement(patcher.text_bytes().begin(), patcher.text_bytes().end()); + replacement.resize(replacement.size() + sizeof(uint32_t)); + EXPECT_FALSE(patcher.replace_text(replacement)); + EXPECT_TRUE(std::ranges::equal(patcher.image_bytes(), image)); + }; + + expect_rejected("out-of-range sh_info", [](auto §ions, Elf64_Shdr &relocations) { + relocations.sh_info = static_cast(sections.size()); + }); + expect_rejected("nonzero SHT_NULL sh_info", [](auto §ions, Elf64_Shdr &relocations) { + constexpr uint32_t target_index = 2; + ASSERT_LT(target_index, sections.size()); + sections[target_index].sh_type = SHT_NULL; + relocations.sh_info = target_index; + }); + auto dynamic_none = make_amdgpu_elf_with_symbol_relocation( + kElfSymbolTypeFunc, /*defined_in_text=*/true, /*addend=*/0, R_AMDGPU_NONE); + AmdGpuCodeObject dynamic_none_object(dynamic_none.data(), dynamic_none.size()); + ASSERT_TRUE(dynamic_none_object.is_valid()); + CodeObjectPatcher dynamic_none_patcher(dynamic_none_object); + EXPECT_FALSE(dynamic_none_patcher.has_malformed_rocr_relocation_section()); + EXPECT_TRUE(dynamic_none_patcher.has_rocr_rejected_none_relocation()); + std::vector dynamic_none_replacement(dynamic_none_patcher.text_bytes().begin(), + dynamic_none_patcher.text_bytes().end()); + dynamic_none_replacement.resize(dynamic_none_replacement.size() + sizeof(uint32_t)); + EXPECT_FALSE(dynamic_none_patcher.replace_text(dynamic_none_replacement)); + EXPECT_TRUE(std::ranges::equal(dynamic_none_patcher.image_bytes(), dynamic_none)); +} + +TEST(CodeObjectPatcher, AllowsAppendOnlyGrowthWithoutTextMapForMappingIncompatibleReference) { + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, /*defined_in_text=*/true, + /*addend=*/4, R_AMDGPU_ABS64); + AmdGpuCodeObject object(image.data(), image.size()); + ASSERT_TRUE(object.is_valid()); + CodeObjectPatcher patcher(object); + ASSERT_FALSE(patcher.has_malformed_rocr_relocation_section()); + ASSERT_FALSE(patcher.has_rocr_rejected_none_relocation()); + ASSERT_TRUE(patcher.has_unsupported_relocation_to_text()); + + std::vector replacement(patcher.text_bytes().begin(), patcher.text_bytes().end()); + replacement.resize(replacement.size() + sizeof(uint32_t)); + EXPECT_TRUE(patcher.replace_text(replacement)); +} + TEST(CodeObjectPatcher, RelocatesReferencedTextSymbolWithExactOffsetMap) { auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, /*defined_in_text=*/true); AmdGpuCodeObject object(image.data(), image.size()); @@ -1663,6 +3483,24 @@ TEST(CodeObjectPatcher, RejectsReferencedTextSymbolWithoutExactOffsetMap) { EXPECT_FALSE(patcher.replace_text(bytes, incomplete_mapping)); } +TEST(CodeObjectPatcher, RejectsConflictingReferencedTextSymbolPlacements) { + auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeFunc, + /*defined_in_text=*/true); + AmdGpuCodeObject object(image.data(), image.size()); + ASSERT_TRUE(object.is_valid()); + CodeObjectPatcher patcher(object); + + const std::array expanded_text = {0xBF800000u, 0xBF800000u, 0xBF800000u, + 0xBF800000u}; + constexpr std::array conflicting = { + TextOffsetRelocation{.source_offset = 0, .target_offset = 4}, + TextOffsetRelocation{.source_offset = 0, .target_offset = 8}, + }; + const auto bytes = std::span( + reinterpret_cast(expanded_text.data()), sizeof(expanded_text)); + EXPECT_FALSE(patcher.replace_text(bytes, conflicting)); +} + TEST(BinaryTranslatorE2E, RejectsRelocationToTextSectionSymbol) { auto image = make_amdgpu_elf_with_symbol_relocation(kElfSymbolTypeSection, /*defined_in_text=*/true); @@ -1677,12 +3515,21 @@ TEST(BinaryTranslatorE2E, RejectsRelocationToTextSectionSymbol) { "unsupported relocation referencing .text")); } -// Independently pin the AMDGPU ELF ABI value so the tests below cannot mask a -// regression by constructing the same wrong relocation type the patcher checks -// for. The fixtures use the production constant (so they never drift from it), -// but this assertion anchors that constant to the authoritative ABI number. +// Independently pin the AMDGPU ELF ABI values so the tests cannot mask a +// regression by constructing the same wrong relocation types the patcher checks +// for. The fixtures use the production constants, while these assertions anchor +// those constants to the authoritative ABI numbers. +static_assert(rocjitsu::R_AMDGPU_NONE == 0, "R_AMDGPU_NONE must be the AMDGPU ELF ABI value 0"); +static_assert(rocjitsu::R_AMDGPU_ABS32_LO == 1, + "R_AMDGPU_ABS32_LO must be the AMDGPU ELF ABI value 1"); +static_assert(rocjitsu::R_AMDGPU_ABS32_HI == 2, + "R_AMDGPU_ABS32_HI must be the AMDGPU ELF ABI value 2"); +static_assert(rocjitsu::R_AMDGPU_ABS64 == 3, "R_AMDGPU_ABS64 must be the AMDGPU ELF ABI value 3"); +static_assert(rocjitsu::R_AMDGPU_ABS32 == 6, "R_AMDGPU_ABS32 must be the AMDGPU ELF ABI value 6"); static_assert(rocjitsu::R_AMDGPU_RELATIVE64 == 13, "R_AMDGPU_RELATIVE64 must be the AMDGPU ELF ABI value 13"); +static_assert(rocjitsu::kElfSymbolTypeAmdGpuHsaKernel == 10, + "STT_AMDGPU_HSA_KERNEL must be the AMDGPU ELF ABI value 10"); // R_AMDGPU_RELATIVE64 carries symbol index 0, so the target is entirely in the // explicit addend. DBT can remap an in-text addend through its exact offset map. diff --git a/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h b/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h index 7d2c51fde40a..837540daa5e5 100644 --- a/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h +++ b/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h @@ -8,6 +8,7 @@ #include "rocjitsu/isa/instruction.h" +#include #include namespace rocjitsu::test { @@ -25,6 +26,8 @@ class DownstreamIsa { public: class Decoder { public: + // Source-integrated decoders publish their maximum encoded width and raw lookahead. + static constexpr std::size_t kMaxInstructionWords = 1; static std::unique_ptr decode(const rj_code_binary_inst_t *raw) { return std::make_unique(raw); } diff --git a/emulation/rocjitsu/tests/isa_target_registry_test.cpp b/emulation/rocjitsu/tests/isa_target_registry_test.cpp index 03ed6d342a73..6e886dc0cd25 100644 --- a/emulation/rocjitsu/tests/isa_target_registry_test.cpp +++ b/emulation/rocjitsu/tests/isa_target_registry_test.cpp @@ -24,6 +24,7 @@ namespace { class FixtureDecoder final : public Decoder { public: Instruction *decode(const rj_code_binary_inst_t *) override { return nullptr; } + std::size_t max_instruction_words() const override { return 1; } }; std::unique_ptr create_fixture_decoder() { return std::make_unique(); } diff --git a/emulation/rocjitsu/tests/patch/spill_manager_test.cpp b/emulation/rocjitsu/tests/patch/spill_manager_test.cpp index f2b5492b5f5b..6f3acb291436 100644 --- a/emulation/rocjitsu/tests/patch/spill_manager_test.cpp +++ b/emulation/rocjitsu/tests/patch/spill_manager_test.cpp @@ -109,6 +109,8 @@ enum class IntegOpcode : uint32_t { class IntegDecoder : public Decoder { public: + std::size_t max_instruction_words() const override { return 1; } + Instruction *decode(const rj_code_binary_inst_t *inst) override { auto op = static_cast(*inst); switch (op) { diff --git a/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp b/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp index f4e5db15b759..f26b61f4db85 100644 --- a/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp +++ b/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp @@ -50,6 +50,24 @@ synthetic_idempotence_mismatch(const rocjitsu::tools::TranslateOptions &options) return result; } +rocjitsu::tools::ToolResult +synthetic_residual_rewrite(const rocjitsu::tools::TranslateOptions &options) { + EXPECT_TRUE(options.verify_rewrite_discharge); + + rocjitsu::tools::ToolResult result; + result.value.rewrite_discharge_checked = true; + result.value.diagnostics.push_back( + {.severity = rocjitsu::DiagnosticSeverity::Error, + .kind = rocjitsu::DiagnosticKind::ResidualRewrite, + .guest_offset = std::nullopt, + .output_offset = 4, + .mnemonic = "s_clause", + .message = "registered rewrite remains actionable in final output", + .required_work = {}}); + result.errors.push_back({.exit_code = 3, .message = "translation failed"}); + return result; +} + uint32_t add_elf_name(std::vector &names, std::string_view name) { const uint32_t offset = static_cast(names.size()); names.insert(names.end(), name.begin(), name.end()); @@ -437,6 +455,42 @@ TEST(RjDbtTranslateIdempotence, ReportsSyntheticMismatchThroughCli) { EXPECT_TRUE(contains(stderr_text, "section '.text' first differs at 0x4")) << stderr_text; } +TEST(RjDbtTranslateRewriteDischarge, ReportsSyntheticResidualThroughCli) { + std::array arguments = { + std::string("rj_dbt_translate"), + std::string("synthetic.co"), + std::string("--input-target"), + std::string("gfx1250"), + std::string("--input-revision"), + std::string("b0"), + std::string("--output-target"), + std::string("gfx1250"), + std::string("--output-revision"), + std::string("a0"), + std::string("--verify-rewrite-discharge"), + std::string("--output-mode"), + std::string("diff"), + }; + std::vector argv; + argv.reserve(arguments.size()); + for (std::string &argument : arguments) + argv.push_back(argument.data()); + + testing::internal::CaptureStdout(); + testing::internal::CaptureStderr(); + const int status = rocjitsu::tools::detail::run_dbt_translate_cli( + static_cast(argv.size()), argv.data(), synthetic_residual_rewrite); + const std::string stderr_text = testing::internal::GetCapturedStderr(); + const std::string stdout_text = testing::internal::GetCapturedStdout(); + + EXPECT_EQ(status, 3); + EXPECT_TRUE(contains(stdout_text, "rewrite_discharge: not-verified")) << stdout_text; + EXPECT_TRUE(contains(stderr_text, "residual-rewrite output:.text+0x0004 s_clause")) + << stderr_text; + EXPECT_TRUE(contains(stderr_text, "registered rewrite remains actionable in final output")) + << stderr_text; +} + TEST(RjDbtTranslate, Smoke) { const rocjitsu::test::ScopedTempDirectory temp_dir("rj_dbt_translate_smoke_"); const std::filesystem::path temp_path(temp_dir.path()); @@ -638,6 +692,85 @@ TEST(RjDbtTranslate, VerifiesGfx1250B0ToA0Idempotence) { EXPECT_TRUE(contains(stdout_text, "target: s_nop 0")) << stdout_text; } +TEST(RjDbtTranslate, VerifiesGfx1250IdempotenceAndRewriteDischarge) { + const rocjitsu::test::ScopedTempDirectory temp_dir("rj_dbt_translate_rewrite_discharge_"); + const std::filesystem::path temp_path(temp_dir.path()); + const std::filesystem::path input = temp_path / "smoke_gfx1250.co"; + const std::filesystem::path output = temp_path / "stdout.txt"; + const std::filesystem::path error = temp_path / "stderr.txt"; + + { + const std::vector image = make_gfx1250_smoke_code_object(); + std::ofstream out(input, std::ios::binary); + out.write(reinterpret_cast(image.data()), + static_cast(image.size())); + } + + const std::string command = + shell_quote(g_translate_tool.string()) + " " + shell_quote(input.string()) + + " --input-target gfx1250 --input-revision b0 --output-target gfx1250 " + "--output-revision a0 --verify-idempotence --verify-rewrite-discharge " + "--output-mode diff > " + + shell_quote(output.string()) + " 2> " + shell_quote(error.string()); + + const int status = std::system(command.c_str()); + const std::string stdout_text = read_text_file(output); + const std::string stderr_text = read_text_file(error); + + ASSERT_TRUE(command_succeeded(status)) << "stderr:\n" + << stderr_text << "\nstdout:\n" + << stdout_text; + EXPECT_TRUE(stderr_text.empty()) << stderr_text; + EXPECT_TRUE(contains(stdout_text, "idempotence: verified")) << stdout_text; + EXPECT_TRUE(contains(stdout_text, "idempotence_diagnostics: 0")) << stdout_text; + EXPECT_TRUE(contains(stdout_text, "rewrite_discharge: verified")) << stdout_text; + EXPECT_TRUE(contains(stdout_text, "changed=1")) << stdout_text; + EXPECT_TRUE(contains(stdout_text, "source: s_clause 4")) << stdout_text; + EXPECT_TRUE(contains(stdout_text, "target: s_nop 0")) << stdout_text; +} + +TEST(RjDbtTranslate, RejectsInvalidRewriteDischargeOptionCombinations) { + rocjitsu::tools::TranslateOptions options; + options.verify_rewrite_discharge = true; + auto error = rocjitsu::tools::translation_request_error(options); + ASSERT_TRUE(error.has_value()); + EXPECT_EQ(*error, "--verify-rewrite-discharge requires gfx1250 b0-to-a0 translation"); + + options.guest_arch = ROCJITSU_CODE_ARCH_GFX1250; + options.host_arch = ROCJITSU_CODE_ARCH_GFX1250; + options.input_revision = rocjitsu::ProcessorRevision::Gfx1250B0; + options.output_revision = rocjitsu::ProcessorRevision::Gfx1250A0; + options.skip_failed_kernels = true; + error = rocjitsu::tools::translation_request_error(options); + ASSERT_TRUE(error.has_value()); + EXPECT_EQ(*error, "--verify-rewrite-discharge cannot be combined with --skip-failed-kernels"); +} + +TEST(RjDbtTranslate, RejectsRewriteDischargeWithListCodeObjects) { + std::array arguments = { + std::string("rj_dbt_translate"), + std::string("unused.co"), + std::string("--list-code-objects"), + std::string("--verify-rewrite-discharge"), + }; + std::vector argv; + argv.reserve(arguments.size()); + for (std::string &argument : arguments) + argv.push_back(argument.data()); + + testing::internal::CaptureStdout(); + testing::internal::CaptureStderr(); + const int status = rocjitsu::tools::detail::run_dbt_translate_cli( + static_cast(argv.size()), argv.data(), rocjitsu::tools::translate_code_object); + const std::string stderr_text = testing::internal::GetCapturedStderr(); + const std::string stdout_text = testing::internal::GetCapturedStdout(); + + EXPECT_EQ(status, 1); + EXPECT_TRUE(stdout_text.empty()) << stdout_text; + EXPECT_TRUE(contains(stderr_text, + "--verify-rewrite-discharge cannot be combined with --list-code-objects")); +} + TEST(RjDbtTranslate, VerifiesNonGfx1250SameArchitectureTranslation) { const rocjitsu::test::ScopedTempDirectory temp_dir("rj_dbt_translate_non_gfx_idempotence_"); const std::filesystem::path temp_path(temp_dir.path()); diff --git a/emulation/rocjitsu/tools/dbt_translate.cpp b/emulation/rocjitsu/tools/dbt_translate.cpp index 5950e7995ec4..ea4e9287a25d 100644 --- a/emulation/rocjitsu/tools/dbt_translate.cpp +++ b/emulation/rocjitsu/tools/dbt_translate.cpp @@ -187,6 +187,7 @@ make_binary_translator_options(const TranslateOptions &options) { translator_options.debug_min_free_vgpr = options.debug_min_free_vgpr; translator_options.debug_continue_after_failure = options.debug_continue_after_failure; translator_options.skip_failed_kernels = options.skip_failed_kernels; + translator_options.verify_rewrite_discharge = options.verify_rewrite_discharge; translator_options.input_revision = options.input_revision; translator_options.output_revision = options.output_revision; return translator_options; @@ -449,6 +450,15 @@ std::optional translation_request_error(const TranslateOptions return "--verify-idempotence requires matching input and output architectures"; if (options.verify_idempotence && options.skip_failed_kernels) return "--verify-idempotence cannot be combined with --skip-failed-kernels"; + if (options.verify_rewrite_discharge && + !(options.guest_arch == ROCJITSU_CODE_ARCH_GFX1250 && + options.host_arch == ROCJITSU_CODE_ARCH_GFX1250 && + options.input_revision == ProcessorRevision::Gfx1250B0 && + options.output_revision == ProcessorRevision::Gfx1250A0)) { + return "--verify-rewrite-discharge requires gfx1250 b0-to-a0 translation"; + } + if (options.verify_rewrite_discharge && options.skip_failed_kernels) + return "--verify-rewrite-discharge cannot be combined with --skip-failed-kernels"; return std::nullopt; } @@ -508,6 +518,8 @@ ToolResult translate_code_object(const TranslateOptions &option output.value.target_mach = options.target_mach ? options.target_mach : elf_mach_for_arch(output.value.host_arch); output.value.diagnostics = std::move(translated.diagnostics); + output.value.rewrite_discharge_checked = translated.rewrite_discharge_checked; + output.value.rewrite_discharge_verified = translated.rewrite_discharge_verified; } catch (const std::exception &e) { add_error(output, kTranslationError, std::string("translation threw exception: ") + e.what()); return output; @@ -545,8 +557,14 @@ ToolResult translate_code_object(const TranslateOptions &option if (options.verify_idempotence) { output.value.idempotence_checked = true; try { + auto verifier_options = make_binary_translator_options(options); + // The first translation already audited the authoritative output. The + // idempotence pass only needs to prove that translating those bytes again + // does not change them; auditing its temporary output would duplicate the + // final-stream scan and raise peak memory on large code objects. + verifier_options.verify_rewrite_discharge = false; BinaryTranslator verifier(options.guest_arch, options.host_arch, options.target_mach, - make_binary_translator_options(options)); + verifier_options); TranslatedCodeObject second = verifier.translate(translated_obj); const bool second_ok = second.ok(); output.value.idempotence_diagnostics = std::move(second.diagnostics); diff --git a/emulation/rocjitsu/tools/dbt_translate.h b/emulation/rocjitsu/tools/dbt_translate.h index c9c4c9c52a8c..3ceaed103848 100644 --- a/emulation/rocjitsu/tools/dbt_translate.h +++ b/emulation/rocjitsu/tools/dbt_translate.h @@ -101,6 +101,8 @@ struct TranslateOptions { bool skip_failed_kernels = false; /// @brief Rerun a same-architecture translation and require identical ELF bytes. bool verify_idempotence = false; + /// @brief Require every audited semantic rewrite to be discharged in final output. + bool verify_rewrite_discharge = false; DisassemblyMode disassembly = DisassemblyMode::None; }; @@ -126,6 +128,10 @@ struct TranslateOutput { bool idempotence_checked = false; /// @brief True when the requested second translation matched the first output. bool idempotence_verified = false; + /// @brief True when the requested final-output applicability scan was attempted. + bool rewrite_discharge_checked = false; + /// @brief True when no registered rewrite remained actionable. + bool rewrite_discharge_verified = false; /// @brief True if translation produced no error diagnostics. [[nodiscard]] bool ok() const { return !has_error_diagnostic(diagnostics); } diff --git a/emulation/rocjitsu/tools/dbt_translate_cli.cpp b/emulation/rocjitsu/tools/dbt_translate_cli.cpp index a725cbd9cad4..fa20cbcd29a2 100644 --- a/emulation/rocjitsu/tools/dbt_translate_cli.cpp +++ b/emulation/rocjitsu/tools/dbt_translate_cli.cpp @@ -95,6 +95,7 @@ void print_help() { << " --skip-failed-kernels Preserve failed kernels and continue other kernels\n" << " --verify-idempotence Require a same-architecture second pass to be " "unchanged\n" + << " --verify-rewrite-discharge Require no registered rewrite trigger in final output\n" << " --show-all-translations Include unchanged identity mappings in diff output\n" << " --list-code-objects List extractable code objects and exit\n" << " --help Show this help\n\n" @@ -201,6 +202,10 @@ void print_help() { options.translate.verify_idempotence = true; continue; } + if (arg == "--verify-rewrite-discharge") { + options.translate.verify_rewrite_discharge = true; + continue; + } if (arg == "--input-target") { if (!require_value(argc, argv, i, arg, value)) @@ -344,6 +349,8 @@ struct ReportTotals { return "resource-limit"; case DiagnosticKind::KernelSkipped: return "kernel-skipped"; + case DiagnosticKind::ResidualRewrite: + return "residual-rewrite"; } return "unknown"; } @@ -356,6 +363,8 @@ void print_diagnostic(std::ostream &os, const TranslationDiagnostic &diagnostic, << diagnostic_kind_name(diagnostic.kind); if (diagnostic.guest_offset) os << " .text+" << hex_offset(*diagnostic.guest_offset); + if (diagnostic.output_offset) + os << " output:.text+" << hex_offset(*diagnostic.output_offset); if (!diagnostic.mnemonic.empty()) os << " " << diagnostic.mnemonic; os << ": " << diagnostic.message << "\n"; @@ -537,6 +546,12 @@ void print_text_report(std::ostream &os, const CliOptions &options, : "not-verified"; os << "idempotence: " << status << "\n"; } + if (options.translate.verify_rewrite_discharge) { + const std::string_view status = !output.rewrite_discharge_checked ? "not-checked" + : output.rewrite_discharge_verified ? "verified" + : "not-verified"; + os << "rewrite_discharge: " << status << "\n"; + } print_code_object_report(os, "source", output.source_report); print_code_object_report(os, "translated", output.translated_report); @@ -603,6 +618,10 @@ int rocjitsu::tools::detail::run_dbt_translate_cli(int argc, char **argv, std::cerr << "--verify-idempotence cannot be combined with --list-code-objects\n"; return kUsageError; } + if (options.list_code_objects && options.translate.verify_rewrite_discharge) { + std::cerr << "--verify-rewrite-discharge cannot be combined with --list-code-objects\n"; + return kUsageError; + } if (options.list_code_objects) return list_code_objects(options); From 8418901076d016a394abbf7832a28b180f7abdaa Mon Sep 17 00:00:00 2001 From: Fei Kou Date: Mon, 17 Aug 2026 17:43:57 -0700 Subject: [PATCH 09/27] [rocjitsu] Fix ds_read_b64_tr_b16 lane layout in gfx950 simulator (#10175) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Motivation `ds_read_b64_tr_b16` returns incorrect results under the gfx950 (CDNA4) simulator. The instruction performs a 4x16-lane halfword transpose: within each 16-lane group, destination lane `l` halfword `n` comes from source lane `((l & ~0xf) | ((l >> 2) & 3)) + 4 * n`, halfword `l & 3` — the layout already encoded by the DBT reference in `tests/dbt/cdna4_to_cdna3_lds_hip_test.cpp` (`LargeStaticLdsReadB64TrB16`). The pure-simulation path's `transpose_b16()` instead performed a 4x4 transpose within groups of 4 consecutive lanes (lane 0 received source lanes 0,1,2,3 halfword 0 instead of lanes 0,4,8,12), so every gfx950 kernel that loads bf16/f16 MFMA operands with `ds_read_b64_tr_b16` computed on wrong data under the simulator. ## Technical Details - `lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/ds_transpose.h`: `transpose_b16()` now handles the wave64 B64 case (4 halfwords per lane, i.e. `ds_read_b64_tr_b16`) with the 4x16-lane stride-4 layout above. This changes only that path; the B128 path used by gfx1250 `ds_load_tr16_b128` / `global_load_tr16_b128` and RDNA4 `global_load_tr_b128` is left byte-for-byte unchanged. `tr_b4` / `tr_b6` / `tr_b8` are untouched and were not hardware-verified here. - `tests/amdgpu_vm_test.cpp`: new `DsTransposeTest.ReadB64TrB16_LaneLayout` (CPU-only). Fills LDS with a per-lane halfword pattern, dispatches an encoded `ds_read_b64_tr_b16` on the `cdna4` VM fixture, and checks all 64 lanes x 4 halfwords against the same reference formula the DBT test uses. - `TransposeKind` is split into `TR16_B128` (gfx1250/RDNA4 B128 loads, unchanged) and `B64_TR_B16` (CDNA4 `ds_read_b64_tr_b16`), emitted from `InstructionSemantics`; `transpose_response()` dispatches on the kind. ## Issue Tracking No existing GitHub issue. Related: #6829 (AccVGPR `acc` bit handling for the same DS transpose reads). ## Test Plan - `ctest` / `rocjitsu_tests --gtest_filter='DsTransposeTest.*'` for the new CPU-side layout test, before and after the `transpose_b16()` change. - Existing test suite for regressions. ## Test Result - `DsTransposeTest.ReadB64TrB16_LaneLayout`: built and run locally (CPU only, GCC 13, Release): fails on the pre-change `transpose_b16()` with 128 mismatches (64 lanes x 2 dwords; e.g. lane 0 low dword 0x12111200 vs expected 0x12441200) and passes after. - Cross-checked on gfx950 hardware (ROCm 7.2.0) with an equivalent inline-asm `ds_write_b64`/`ds_read_b64_tr_b16` kernel: hardware matches the expected layout; the simulator matched only after this change (all 64 lanes differed before). - Full `ctest` shows no status changes versus `develop` other than the added `DsTransposeTest.ReadB64TrB16_LaneLayout`. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit 95b6c410bb5e9929192bdb4825f18f10fa1c9d99) --- .../lib/python/amdisa/codegen/_generator.py | 7 +- .../rocjitsu/lib/python/amdisa/semantics.py | 5 +- .../python/amdisa/tests/test_sema_derive.py | 2 +- .../arch/amdgpu/generated/cdna4/ds_exec.cpp | 2 +- .../isa/arch/amdgpu/shared/ds_transpose.h | 50 +++++++++++-- emulation/rocjitsu/tests/amdgpu_vm_test.cpp | 71 +++++++++++++++++++ 6 files changed, 124 insertions(+), 13 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 699dec4fbca1..58105c798ed2 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -6639,15 +6639,16 @@ def _gen_ds_read_tr( signal the memory pipeline to apply the cross-lane shuffle after the raw read. """ - # TR_B4=1, TR_B6=2, TR_B8=3, TR_B16=4 + # amdgpu::TransposeKind: TR_B4=1, TR_B6=2, TR_B8=3, TR16_B128=4, + # B64_TR_B16=5. Defaults describe the B64 (num_elems=2) forms. tr_map = { 'ds_read_tr_b4': (4, 2, 1), # elem_size=4, num_elems=2, transpose=1 'ds_read_tr_b6': (4, 3, 2), # elem_size=4, num_elems=3, transpose=2 'ds_read_tr_b8': (4, 2, 3), # elem_size=4, num_elems=2, transpose=3 - 'ds_read_tr_b16': (4, 2, 4), # elem_size=4, num_elems=2, transpose=4 + 'ds_read_tr_b16': (4, 2, 5), # elem_size=4, num_elems=2, transpose=5 } default_esz, default_ne, default_tr_kind = tr_map.get( - sem.semantic_class, (4, 2, 4) + sem.semantic_class, (4, 2, 5) ) esz = sem.elem_size if sem.elem_size is not None else default_esz ne = sem.num_elems if sem.num_elems is not None else default_ne diff --git a/emulation/rocjitsu/lib/python/amdisa/semantics.py b/emulation/rocjitsu/lib/python/amdisa/semantics.py index 62b62bd636fa..88297bae001f 100644 --- a/emulation/rocjitsu/lib/python/amdisa/semantics.py +++ b/emulation/rocjitsu/lib/python/amdisa/semantics.py @@ -1788,10 +1788,13 @@ def _derive_smem(name: str) -> InstructionSemantics | None: _TRANSPOSE_LOAD_MAP: dict[str, tuple[str, int, int, int]] = { # suffix -> (semantic suffix, elem_size, num_elems, transpose kind) # elem_size/num_elems describe the raw VGPR result size in dwords. + # transpose kind is amdgpu::TransposeKind: TR_B4=1, TR_B6=2, TR_B8=3, + # TR16_B128=4 (grouped 16-bit B128 layout), B64_TR_B16=5 (CDNA4 4x16-lane + # ds_read_b64_tr_b16 layout). 'B64_TR_B4': ('b4', 4, 2, 1), 'B96_TR_B6': ('b6', 4, 3, 2), 'B64_TR_B8': ('b8', 4, 2, 3), - 'B64_TR_B16': ('b16', 4, 2, 4), + 'B64_TR_B16': ('b16', 4, 2, 5), 'TR4_B64': ('b4', 4, 2, 1), 'TR6_B96': ('b6', 4, 3, 2), 'TR8_B64': ('b8', 4, 2, 3), diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py index 1f0dabf5dc3a..59a471ae390a 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py @@ -2227,7 +2227,7 @@ def test_lowers_to_lds(self): ('DS_LOAD_TR_B64', 'ds_read_tr_b8', 2, 3), ('DS_LOAD_TR16_B128', 'ds_read_tr_b16', 4, 4), ('DS_LOAD_TR_B128', 'ds_read_tr_b16', 4, 4), - ('DS_READ_B64_TR_B16', 'ds_read_tr_b16', 2, 4), + ('DS_READ_B64_TR_B16', 'ds_read_tr_b16', 2, 5), ], ) def test_gfx1250_ds_transpose_loads( diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds_exec.cpp index 7912ca18c062..0b715ae785ea 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds_exec.cpp @@ -2915,7 +2915,7 @@ void DsReadB64TrB16Ds::execute_impl(amdgpu::Wavefront &wf) { d->num_elems = 2; d->is_load = true; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; - d->transpose = 4; + d->transpose = 5; ds_calculate_addresses(inst_, wf, *d); set_data(std::move(d)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/ds_transpose.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/ds_transpose.h index 0e598b4e0c2f..c993b6223127 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/ds_transpose.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/ds_transpose.h @@ -12,7 +12,10 @@ /// matrix instructions. /// /// TR_B8 uses byte-level transpose with groups of 4 consecutive lanes. -/// TR_B16 transposes 16-bit elements within groups of 8 consecutive lanes. +/// TR16_B128 (gfx1250 ds/global_load_tr16_b128, RDNA4 global_load_tr_b128) +/// transposes 16-bit elements within groups of 8 consecutive lanes. +/// B64_TR_B16 (CDNA4 ds_read_b64_tr_b16) is a 4x16-lane halfword transpose +/// with stride-4 source lanes. #include "rocjitsu/vm/amdgpu/mem_state.h" @@ -23,7 +26,7 @@ namespace rocjitsu { namespace amdgpu { -enum class TransposeKind : uint8_t { NONE, TR_B4, TR_B6, TR_B8, TR_B16 }; +enum class TransposeKind : uint8_t { NONE, TR_B4, TR_B6, TR_B8, TR16_B128, B64_TR_B16 }; /// @brief B64 byte-level transpose (TR_B8 only). /// @@ -69,12 +72,13 @@ inline void transpose_b64(std::vector &response_data, uint32_t num_elem response_data = std::move(output); } -/// @brief TR_B16: 16-bit element transpose. +/// @brief TR16_B128: 16-bit element transpose for B128 transpose loads +/// (gfx1250 ds_load_tr16_b128 / global_load_tr16_b128, RDNA4 global_load_tr_b128). /// /// Groups of 8 source lanes, each reading 8 halfwords. Destination lane /// `group_start + halfword_index` receives that halfword from each source lane. -inline void transpose_b16(std::vector &response_data, uint32_t num_elems, - uint32_t wf_size) { +inline void transpose_tr16_b128(std::vector &response_data, uint32_t num_elems, + uint32_t wf_size) { constexpr uint32_t lanes_per_half = 32; const uint32_t bytes_per_lane_total = num_elems * 4; @@ -106,6 +110,35 @@ inline void transpose_b16(std::vector &response_data, uint32_t num_elem response_data = std::move(output); } +/// @brief B64_TR_B16: 4x16-lane halfword transpose (CDNA4 ds_read_b64_tr_b16). +/// +/// Within each 16-lane group, destination lane `l` halfword `n` comes from +/// source lane `((l & ~0xf) | ((l >> 2) & 3)) + 4 * n`, halfword `l & 3`. +inline void transpose_b64_tr_b16(std::vector &response_data, uint32_t num_elems, + uint32_t wf_size) { + constexpr uint32_t source_lane_stride = 4; + + const uint32_t bytes_per_lane_total = num_elems * 4; + const uint32_t halfwords_per_lane = bytes_per_lane_total / 2; + + std::vector output(response_data.size(), 0); + + for (uint32_t dest_lane = 0; dest_lane < wf_size; ++dest_lane) { + const uint32_t source_halfword = dest_lane & 3; + const uint32_t source_base = (dest_lane & ~0xfu) | ((dest_lane >> 2) & 3); + for (uint32_t halfword_index = 0; halfword_index < halfwords_per_lane; ++halfword_index) { + const uint32_t source_lane = source_base + source_lane_stride * halfword_index; + const uint32_t source_offset = source_lane * bytes_per_lane_total + source_halfword * 2; + const uint32_t dest_offset = dest_lane * bytes_per_lane_total + halfword_index * 2; + + if (source_offset + 2 <= response_data.size() && dest_offset + 2 <= output.size()) + std::memcpy(&output[dest_offset], &response_data[source_offset], 2); + } + } + + response_data = std::move(output); +} + /// @brief TR_B4: 4-bit element transpose for B128 family. /// /// Groups of 8 source lanes, each reading 8 bytes (64 bits). Extracts @@ -235,8 +268,11 @@ inline void transpose_response(VectorMemState &d) { case TransposeKind::TR_B8: transpose_b64(d.response_data, d.num_elems, d.wf_size); break; - case TransposeKind::TR_B16: - transpose_b16(d.response_data, d.num_elems, d.wf_size); + case TransposeKind::TR16_B128: + transpose_tr16_b128(d.response_data, d.num_elems, d.wf_size); + break; + case TransposeKind::B64_TR_B16: + transpose_b64_tr_b16(d.response_data, d.num_elems, d.wf_size); break; case TransposeKind::TR_B4: transpose_b4(d.response_data, d.num_elems, d.wf_size); diff --git a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp index 4bd69697e2b9..92b7055af7bc 100644 --- a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp +++ b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp @@ -3197,6 +3197,77 @@ TEST(DsTransposeTest, ReadB64TrB16_AccBit) { << " should contain LDS data, not the VGPR sentinel"; } +constexpr uint32_t tr_b16_halfword_value(uint32_t lane, uint32_t halfword) { + return (0x1200u + lane * 0x11u + halfword) & 0xffffu; +} + +constexpr uint32_t pack_u16_pair(uint32_t lo, uint32_t hi) { + return (lo & 0xffffu) | ((hi & 0xffffu) << 16); +} + +// Verify the ds_read_b64_tr_b16 cross-lane layout: within each 16-lane group, +// destination lane l halfword n comes from source lane +// ((l & 0x30) | ((l & 0xc) >> 2)) + 4 * n, halfword (l & 3). Expected values use +// the same reference formula as tests/dbt/cdna4_to_cdna3_lds_hip_test.cpp. +TEST(DsTransposeTest, ReadB64TrB16_LaneLayout) { + VmFixture f("cdna4", 1, 10); + auto *snap = f.capture_halts(); + + constexpr uint32_t VDST = 4; + constexpr uint32_t TID_REG = 0; + constexpr uint32_t ADDR_REG = 1; + constexpr uint32_t DS_OP = 227; // ds_read_b64_tr_b16 + constexpr uint32_t WAVE_SIZE = 64; + constexpr uint32_t BYTES_PER_LANE = 8; + + // Kernel: + // v_add_u32 v1, v0, v0 ; v1 = 2 * tid + // v_add_u32 v1, v1, v1 ; v1 = 4 * tid + // v_add_u32 v1, v1, v1 ; v1 = 8 * tid (per-lane LDS byte address) + // ds_read_b64_tr_b16 v[4:5], v1 + // s_waitcnt lgkmcnt(0) + // s_endpgm + using namespace enc; + const uint32_t code[] = { + v_add_u32(ADDR_REG, VGPR_SRC(TID_REG), TID_REG), + v_add_u32(ADDR_REG, VGPR_SRC(ADDR_REG), ADDR_REG), + v_add_u32(ADDR_REG, VGPR_SRC(ADDR_REG), ADDR_REG), + ds_lo(DS_OP), + ds_hi(VDST, /*data0=*/0, ADDR_REG), + S_WAITCNT_0, + S_ENDPGM, + }; + uint64_t ko = f.write_kernel(0x1000, code, sizeof(code)); + + auto *cu = f.cu(); + for (uint32_t lane = 0; lane < WAVE_SIZE; ++lane) { + const uint32_t source_lo = + pack_u16_pair(tr_b16_halfword_value(lane, 0), tr_b16_halfword_value(lane, 1)); + const uint32_t source_hi = + pack_u16_pair(tr_b16_halfword_value(lane, 2), tr_b16_halfword_value(lane, 3)); + cu->lds().write32(lane * BYTES_PER_LANE, source_lo); + cu->lds().write32(lane * BYTES_PER_LANE + 4, source_hi); + } + + test::AqlQueue queue(f.mem(), f.cp()); + queue.dispatch(ko, WAVE_SIZE); + f.engine->run(); + + ASSERT_EQ(snap->snapshots().size(), 1u); + const auto &wf = snap->snapshots().front(); + + for (uint32_t lane = 0; lane < WAVE_SIZE; ++lane) { + const uint32_t halfword = lane & 3; + const uint32_t source_base = (lane & 0x30) + ((lane & 0x0c) >> 2); + const uint32_t expected_lo = pack_u16_pair(tr_b16_halfword_value(source_base + 0, halfword), + tr_b16_halfword_value(source_base + 4, halfword)); + const uint32_t expected_hi = pack_u16_pair(tr_b16_halfword_value(source_base + 8, halfword), + tr_b16_halfword_value(source_base + 12, halfword)); + EXPECT_EQ(wf.vgpr(VDST, lane), expected_lo) << "lane " << lane << " v" << VDST; + EXPECT_EQ(wf.vgpr(VDST + 1, lane), expected_hi) << "lane " << lane << " v" << (VDST + 1); + } +} + // Write-through scalar stores must use the store's VMID. Two page tables map // the same GPU VA to different host pages; a store under VMID 7 followed by the // no-op writeback_all(8) must land only in VMID 7's backing. From c4eac1e1f78d3ae74e3fa0d93738423b2f9d32ec Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 18 Aug 2026 11:44:45 -0400 Subject: [PATCH 10/27] [rocjitsu][util] Add result and diagnostic utilities (#10240) Add compact Result and FailureOr types for expected failures that should not propagate exceptions. Their operations establish an explicit termination boundary if a value operation throws. Factor FailureOr storage behind a type traits-style customization point. We provide one for pointers -- `nullptr` is considered the failure state, which makes the representation more space efficient and avoids the usual confusion about double-nullable types. Add non-owning diagnostic sinks and stream-style in-flight diagnostics -- this decouples diagnostics from error handling, as an alternative to strongly typed error code enums or custom error types. Issue: https://github.com/ROCm/rocm-systems/issues/10239 (cherry picked from commit bfaebcfb5c0f4299b5ed7a6bd71e7df0bb4c3c39) --- .../lib/rocjitsu/src/rocjitsu/result.h | 13 + emulation/rocjitsu/lib/util/README.md | 2 + .../lib/util/include/util/diagnostic.h | 178 ++++++++++ .../rocjitsu/lib/util/include/util/result.h | 170 ++++++++++ emulation/rocjitsu/tests/CMakeLists.txt | 1 + emulation/rocjitsu/tests/util_result_test.cpp | 313 ++++++++++++++++++ 6 files changed, 677 insertions(+) create mode 100644 emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/result.h create mode 100644 emulation/rocjitsu/lib/util/include/util/diagnostic.h create mode 100644 emulation/rocjitsu/lib/util/include/util/result.h create mode 100644 emulation/rocjitsu/tests/util_result_test.cpp diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/result.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/result.h new file mode 100644 index 000000000000..f32b1856be92 --- /dev/null +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/result.h @@ -0,0 +1,13 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#pragma once + +#include "util/result.h" + +namespace rocjitsu { + +using util::FailureOr; +using util::Result; + +} // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/util/README.md b/emulation/rocjitsu/lib/util/README.md index 9f3e22870467..4306d98640e0 100644 --- a/emulation/rocjitsu/lib/util/README.md +++ b/emulation/rocjitsu/lib/util/README.md @@ -41,6 +41,8 @@ INTERFACE library that contributes an include path and nothing to link. | File | Description | |------|-------------| | `log.h` | Compile-time and runtime configurable logging with named groups (VM, CP). Thread-safe, supports lazy evaluation via lambda forms. Use `Logger::print()` for group-filtered output. | +| `result.h` | No-throw `Result` and `FailureOr` return types for expected failures. | +| `diagnostic.h` | Non-owning diagnostic sinks and stream-style error construction for result-returning APIs. | | `except.h` | Exception hierarchy: `Exception` (base), `InvalidInst`, `UnimplementedInst`, `ConfigError`. All derive from `std::exception`. | ### Miscellaneous diff --git a/emulation/rocjitsu/lib/util/include/util/diagnostic.h b/emulation/rocjitsu/lib/util/include/util/diagnostic.h new file mode 100644 index 000000000000..27edaca2c16a --- /dev/null +++ b/emulation/rocjitsu/lib/util/include/util/diagnostic.h @@ -0,0 +1,178 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#pragma once + +#include "util/result.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace util { + +/// A non-owning destination for one completed diagnostic message. +/// +/// The referenced callable must outlive the sink and every diagnostic created +/// from it. It must be a non-volatile object; wrap a free function in an object +/// when needed. A default-constructed sink intentionally discards messages. +/// Explicit emission propagates callback failures, while destructor-triggered +/// emission suppresses them. +class DiagnosticSink { +public: + DiagnosticSink() = default; + + template + requires(!std::same_as, DiagnosticSink> && + std::is_object_v && !std::is_volatile_v && + std::invocable) + explicit DiagnosticSink(Callable &callable) + : context_(std::addressof(callable)), + callback_([](const void *context, std::string_view message) { + using Object = std::remove_const_t; + if constexpr (std::is_const_v) + std::invoke(*static_cast(context), message); + else + std::invoke(*const_cast(static_cast(context)), message); + }) {} + + void emit(std::string_view message) const { + if (callback_ != nullptr) + callback_(context_, message); + } + + [[nodiscard]] bool ignores_messages() const { return callback_ == nullptr; } + +private: + using Callback = void (*)(const void *, std::string_view); + + const void *context_ = nullptr; + Callback callback_ = nullptr; +}; + +/// A move-only error builder that commits its message at most once. +/// Non-fatal diagnostics and structured severity are intentionally outside this API. +class InFlightDiagnostic { +public: + explicit InFlightDiagnostic(DiagnosticSink sink) : sink_(sink) { + if (!sink_.ignores_messages()) + stream_.emplace(); + } + + InFlightDiagnostic(const InFlightDiagnostic &) = delete; + InFlightDiagnostic &operator=(const InFlightDiagnostic &) = delete; + + InFlightDiagnostic(InFlightDiagnostic &&other) noexcept + : sink_(other.sink_), stream_(std::move(other.stream_)), active_(other.active_) { + other.active_ = false; + } + + InFlightDiagnostic &operator=(InFlightDiagnostic &&other) noexcept { + if (this == &other) + return *this; + emit_from_destructor(); + sink_ = other.sink_; + stream_ = std::move(other.stream_); + active_ = other.active_; + other.active_ = false; + return *this; + } + + ~InFlightDiagnostic() { emit_from_destructor(); } + + template InFlightDiagnostic &operator<<(T &&fragment) { + assert(active_ && "cannot append to an emitted diagnostic"); + if (stream_) + *stream_ << std::forward(fragment); + return *this; + } + + InFlightDiagnostic &operator<<(std::ostream &(*manipulator)(std::ostream &)) { + assert(active_ && "cannot append to an emitted diagnostic"); + if (stream_) + *stream_ << manipulator; + return *this; + } + + /// Commit the diagnostic and return failure for compact propagation. + Result emit() { + if (active_) { + active_ = false; + if (stream_) + sink_.emit(stream_->str()); + } + return Result::failure(); + } + + operator Result() { return emit(); } + + template operator FailureOr() { + (void)emit(); + return Result::failure(); + } + +private: + void emit_from_destructor() noexcept { + if (!active_) + return; + try { + (void)emit(); + } catch (...) { + // A destructor cannot safely surface diagnostic delivery failures. + active_ = false; + } + } + + DiagnosticSink sink_; + std::optional stream_; + bool active_ = true; +}; + +/// A cheap, copyable producer for in-flight diagnostics. +class DiagnosticEmitter { +public: + DiagnosticEmitter() = default; + explicit DiagnosticEmitter(DiagnosticSink sink) : sink_(sink) {} + + template + requires(!std::same_as, DiagnosticEmitter> && + std::is_object_v && !std::is_volatile_v && + std::invocable) + explicit DiagnosticEmitter(Callable &callable) : sink_(callable) {} + + [[nodiscard]] InFlightDiagnostic emit() const { return InFlightDiagnostic(sink_); } + [[nodiscard]] bool ignores_messages() const { return sink_.ignores_messages(); } + +private: + DiagnosticSink sink_; +}; + +/// Owns the latest diagnostic message and provides an emitter that writes it. +/// This single-threaded helper is pinned because its emitters borrow it. +class StringDiagnostic { +public: + StringDiagnostic() = default; + StringDiagnostic(const StringDiagnostic &) = delete; + StringDiagnostic(StringDiagnostic &&) = delete; + StringDiagnostic &operator=(const StringDiagnostic &) = delete; + StringDiagnostic &operator=(StringDiagnostic &&) = delete; + + void operator()(std::string_view message) { message_.assign(message); } + + [[nodiscard]] DiagnosticEmitter emitter() & { return DiagnosticEmitter(*this); } + DiagnosticEmitter emitter() && = delete; + [[nodiscard]] const std::string &message() const { return message_; } + +private: + std::string message_; +}; + +} // namespace util diff --git a/emulation/rocjitsu/lib/util/include/util/result.h b/emulation/rocjitsu/lib/util/include/util/result.h new file mode 100644 index 000000000000..e3fc5df99eca --- /dev/null +++ b/emulation/rocjitsu/lib/util/include/util/result.h @@ -0,0 +1,170 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include +#include +#include +#include + +namespace util { + +/// A success/failure result for operations that do not return a value. +class [[nodiscard]] Result { +public: + constexpr Result() noexcept = default; + + static constexpr Result success() noexcept { + Result result; + result.succeeded_ = true; + return result; + } + static constexpr Result failure() noexcept { return {}; } + + [[nodiscard]] constexpr bool succeeded() const noexcept { return succeeded_; } + [[nodiscard]] constexpr bool failed() const noexcept { return !succeeded_; } + +private: + bool succeeded_ = false; +}; + +/// Customization point for value types with a reserved failure representation. +/// Niche specializations provide failure_value() and is_failure(). The niche must +/// be safe to copy, move, assign, and destroy as a T. Program-defined +/// specializations must be declared with T and be visible before every use of +/// FailureOr so that all translation units select the same storage. +template struct failure_or_storage_traits { + static constexpr bool has_niche = false; +}; + +/// Null is the canonical pointer failure representation. +template struct failure_or_storage_traits { + static constexpr bool has_niche = true; + + [[nodiscard]] static constexpr T *failure_value() noexcept { return nullptr; } + + [[nodiscard]] static constexpr bool is_failure(T *value) noexcept { return value == nullptr; } +}; + +/// A unique pointer with raw-pointer storage can use the null niche while retaining value +/// references. Fancy pointers use the generic optional-backed storage. +template + requires(std::is_same_v::pointer, + typename std::unique_ptr::element_type *> && + failure_or_storage_traits::pointer>::has_niche && + std::is_constructible_v, + typename std::unique_ptr::pointer>) +struct failure_or_storage_traits> { + using Value = std::unique_ptr; + using Pointer = typename Value::pointer; + + static constexpr bool has_niche = true; + + [[nodiscard]] static constexpr Value failure_value() noexcept { return Value(Pointer{}); } + + [[nodiscard]] static constexpr bool is_failure(const Value &value) noexcept { + return failure_or_storage_traits::is_failure(value.get()); + } +}; + +/// Storage for FailureOr. Specialize failure_or_storage_traits to use a niche. +template ::has_niche> +class FailureOrStorage { +public: + constexpr FailureOrStorage() noexcept = default; + + template + requires std::is_constructible_v + constexpr FailureOrStorage(U &&value) noexcept : value_(std::in_place, std::forward(value)) {} + + FailureOrStorage(const FailureOrStorage &) noexcept = default; + FailureOrStorage(FailureOrStorage &&) noexcept = default; + FailureOrStorage &operator=(const FailureOrStorage &) noexcept = default; + FailureOrStorage &operator=(FailureOrStorage &&) noexcept = default; + constexpr ~FailureOrStorage() noexcept = default; + + [[nodiscard]] constexpr bool has_value() const noexcept { return value_.has_value(); } + + [[nodiscard]] constexpr T &value() & noexcept { return *value_; } + [[nodiscard]] constexpr const T &value() const & noexcept { return *value_; } + [[nodiscard]] constexpr T &&value() && noexcept { return std::move(*value_); } + +private: + std::optional value_; +}; + +/// Niche-backed storage that still contains a T and can therefore return references. +template class FailureOrStorage { + using Traits = failure_or_storage_traits; + +public: + constexpr FailureOrStorage() noexcept : value_(Traits::failure_value()) {} + + template + requires std::is_constructible_v + constexpr FailureOrStorage(U &&value) noexcept : value_(std::forward(value)) { + assert(!Traits::is_failure(value_) && + "cannot construct a successful FailureOr from its failure representation"); + } + + FailureOrStorage(const FailureOrStorage &) noexcept = default; + FailureOrStorage(FailureOrStorage &&) noexcept = default; + FailureOrStorage &operator=(const FailureOrStorage &) noexcept = default; + FailureOrStorage &operator=(FailureOrStorage &&) noexcept = default; + constexpr ~FailureOrStorage() noexcept = default; + + [[nodiscard]] constexpr bool has_value() const noexcept { return !Traits::is_failure(value_); } + + [[nodiscard]] constexpr T &value() & noexcept { return value_; } + [[nodiscard]] constexpr const T &value() const & noexcept { return value_; } + [[nodiscard]] constexpr T &&value() && noexcept { return std::move(value_); } + +private: + T value_; +}; + +/// A result that contains either a value or failure. A niche's failure +/// representation is not a valid success value. After a move, the source is +/// valid but whether it contains a value is unspecified. +/// Every operation is noexcept; an exception from a value operation terminates the process. +template class [[nodiscard]] FailureOr { +public: + /// Construct a failure; the supplied Result must itself represent failure. + constexpr FailureOr([[maybe_unused]] Result result) noexcept { + assert(result.failed() && "cannot construct a FailureOr from a successful Result"); + } + + template + requires(!std::is_same_v, FailureOr> && + !std::is_same_v, Result> && std::is_constructible_v) + constexpr FailureOr(U &&value) noexcept : storage_(std::forward(value)) {} + + FailureOr(const FailureOr &) noexcept = default; + FailureOr(FailureOr &&) noexcept = default; + FailureOr &operator=(const FailureOr &) noexcept = default; + FailureOr &operator=(FailureOr &&) noexcept = default; + constexpr ~FailureOr() noexcept = default; + + [[nodiscard]] constexpr bool succeeded() const noexcept { return storage_.has_value(); } + [[nodiscard]] constexpr bool failed() const noexcept { return !storage_.has_value(); } + + [[nodiscard]] constexpr T &value() & noexcept { + assert(succeeded() && "cannot access the value of a failed FailureOr"); + return storage_.value(); + } + [[nodiscard]] constexpr const T &value() const & noexcept { + assert(succeeded() && "cannot access the value of a failed FailureOr"); + return storage_.value(); + } + [[nodiscard]] constexpr T &&value() && noexcept { + assert(succeeded() && "cannot access the value of a failed FailureOr"); + return std::move(storage_).value(); + } + +private: + FailureOrStorage storage_; +}; + +} // namespace util diff --git a/emulation/rocjitsu/tests/CMakeLists.txt b/emulation/rocjitsu/tests/CMakeLists.txt index 7f212db8901a..59c431a4446b 100644 --- a/emulation/rocjitsu/tests/CMakeLists.txt +++ b/emulation/rocjitsu/tests/CMakeLists.txt @@ -457,6 +457,7 @@ add_executable( cdna3_predicate_mask_test.cpp scoped_temp_test.cpp decode_execute_benchmark.cpp + util_result_test.cpp util_unique_handle_test.cpp util_simd_test.cpp v_add_simd_benchmark.cpp diff --git a/emulation/rocjitsu/tests/util_result_test.cpp b/emulation/rocjitsu/tests/util_result_test.cpp new file mode 100644 index 000000000000..e240c1aa3412 --- /dev/null +++ b/emulation/rocjitsu/tests/util_result_test.cpp @@ -0,0 +1,313 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#include "rocjitsu/result.h" +#include "util/diagnostic.h" +#include "util/result.h" + +#include + +#include +#include +#include +#include +#include +#include +#include + +struct CustomNicheValue { + int value; +}; + +class FancyPointer { +public: + using element_type = int; + + constexpr FancyPointer() = default; + constexpr FancyPointer(std::nullptr_t) {} + explicit constexpr FancyPointer(int state) : state_(state) {} + + explicit constexpr operator bool() const { return state_ != 0; } + friend constexpr bool operator==(FancyPointer, FancyPointer) = default; + friend constexpr bool operator==(FancyPointer pointer, std::nullptr_t) { + return pointer.state_ == 0; + } + [[nodiscard]] constexpr int state() const { return state_; } + +private: + int state_ = 0; +}; + +struct FancyPointerDeleter { + using pointer = FancyPointer; + + void operator()(FancyPointer) const noexcept {} +}; + +template <> struct util::failure_or_storage_traits { + static constexpr bool has_niche = true; + + [[nodiscard]] static constexpr CustomNicheValue failure_value() noexcept { return {-1}; } + [[nodiscard]] static constexpr bool is_failure(const CustomNicheValue &value) noexcept { + return value.value == -1; + } +}; + +template <> struct util::failure_or_storage_traits { + static constexpr bool has_niche = true; + + [[nodiscard]] static constexpr FancyPointer failure_value() noexcept { return FancyPointer(1); } + [[nodiscard]] static constexpr bool is_failure(FancyPointer pointer) noexcept { + return pointer.state() == 1; + } +}; + +namespace { + +struct PotentiallyThrowingValue { + PotentiallyThrowingValue() = default; + PotentiallyThrowingValue(PotentiallyThrowingValue &&) noexcept(false) {} + PotentiallyThrowingValue &operator=(PotentiallyThrowingValue &&) noexcept(false) { return *this; } +}; + +struct CountingDeleter { + static inline int calls = 0; + + void operator()(int *value) const noexcept { + ++calls; + delete value; + } +}; + +struct FormattingProbe { + bool &formatted; +}; + +struct ConstCollector { + std::vector &messages; + + void operator()(std::string_view message) const { messages.emplace_back(message); } +}; + +using DiagnosticFunction = void(std::string_view); + +template +concept HasRvalueEmitter = requires { std::declval().emitter(); }; + +std::ostream &operator<<(std::ostream &stream, const FormattingProbe &probe) { + probe.formatted = true; + return stream; +} + +TEST(ResultTest, RepresentsSuccessAndFailure) { + constexpr util::Result default_failure; + constexpr auto success = util::Result::success(); + constexpr util::Result failure = util::Result::failure(); + static_assert(default_failure.failed()); + static_assert(success.succeeded() && !success.failed()); + static_assert(failure.failed() && !failure.succeeded()); + static_assert(noexcept(success.succeeded()) && noexcept(failure.failed())); + static_assert(std::is_same_v); + static_assert(std::is_same_v); +} + +TEST(FailureOrTest, RepresentsValueOrFailureWithoutThrowing) { + using IntResult = util::FailureOr; + constexpr IntResult value(42); + constexpr IntResult failure(util::Result::failure()); + static_assert(value.succeeded() && value.value() == 42); + static_assert(failure.failed()); + static_assert(std::is_nothrow_copy_constructible_v); + static_assert(std::is_nothrow_copy_assignable_v); + static_assert(std::is_nothrow_move_constructible_v); + static_assert(std::is_nothrow_move_assignable_v); + static_assert(std::is_nothrow_destructible_v); + static_assert(std::is_nothrow_constructible_v); + static_assert(std::is_nothrow_move_constructible_v>>); + static_assert(sizeof(util::FailureOr>) == sizeof(std::unique_ptr)); + static_assert(sizeof(util::FailureOr>) == sizeof(std::unique_ptr)); + using TerminatingResult = util::FailureOr; + static_assert(std::is_nothrow_constructible_v); + static_assert(std::is_nothrow_move_constructible_v); + static_assert(std::is_nothrow_move_assignable_v); + static_assert(noexcept(value.succeeded()) && noexcept(failure.failed()) && + noexcept(value.value())); + static_assert(std::is_same_v, IntResult>); +} + +TEST(FailureOrTest, RejectsSuccessfulResult) { + EXPECT_DEBUG_DEATH( + { [[maybe_unused]] util::FailureOr result(util::Result::success()); }, ""); +} + +TEST(FailureOrTest, UsesNullAsPointerFailure) { + constexpr util::FailureOr pointer_failure(util::Result::failure()); + constexpr util::FailureOr byte_pointer_failure(util::Result::failure()); + constexpr util::FailureOr void_pointer_failure(util::Result::failure()); + constexpr util::FailureOr function_pointer_failure(util::Result::failure()); + + static_assert(pointer_failure.failed()); + static_assert(sizeof(util::FailureOr) == sizeof(char *)); + static_assert(byte_pointer_failure.failed()); + static_assert(void_pointer_failure.failed()); + static_assert(function_pointer_failure.failed()); +} + +TEST(FailureOrTest, SupportsCustomNicheTraits) { + constexpr util::FailureOr value(CustomNicheValue{42}); + constexpr util::FailureOr failure(util::Result::failure()); + + static_assert(value.succeeded() && value.value().value == 42); + static_assert(failure.failed()); + static_assert(sizeof(util::FailureOr) == sizeof(CustomNicheValue)); +} + +TEST(FailureOrTest, UsesNullUniquePointerAsFailure) { + util::FailureOr> value(std::make_unique(42)); + util::FailureOr> failure(util::Result::failure()); + + ASSERT_TRUE(value.succeeded()); + EXPECT_EQ(*value.value(), 42); + EXPECT_TRUE(failure.failed()); +} + +TEST(FailureOrTest, FallsBackToGenericStorageForFancyUniquePointer) { + using Pointer = std::unique_ptr; + static_assert(!util::failure_or_storage_traits::has_niche); + + util::FailureOr failure(util::Result::failure()); + util::FailureOr null_value(Pointer{}); + + EXPECT_TRUE(failure.failed()); + EXPECT_TRUE(null_value.succeeded()); + EXPECT_FALSE(static_cast(null_value.value())); +} + +TEST(FailureOrTest, RejectsTheFailureRepresentationOnTheSuccessPath) { + EXPECT_DEBUG_DEATH( + { [[maybe_unused]] util::FailureOr result(static_cast(nullptr)); }, ""); + EXPECT_DEBUG_DEATH( + { [[maybe_unused]] util::FailureOr> result(std::unique_ptr{}); }, + ""); +} + +TEST(FailureOrTest, DoesNotDeleteTheNullUniquePointerFailure) { + using Pointer = std::unique_ptr; + using PointerResult = util::FailureOr; + static_assert(sizeof(PointerResult) == sizeof(Pointer)); + + CountingDeleter::calls = 0; + { + PointerResult result(util::Result::failure()); + result = PointerResult(Pointer(new int(42))); + ASSERT_TRUE(result.succeeded()); + EXPECT_EQ(*result.value(), 42); + + result = PointerResult(util::Result::failure()); + EXPECT_TRUE(result.failed()); + EXPECT_EQ(CountingDeleter::calls, 1); + } + EXPECT_EQ(CountingDeleter::calls, 1); +} + +TEST(InFlightDiagnosticTest, EmitsExactlyOnceAfterMove) { + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + util::DiagnosticEmitter emitter(collect); + + { + auto first = emitter.emit(); + first << "invalid opcode 0x" << std::hex << 42 << std::endl; + auto second = std::move(first); + EXPECT_TRUE(second.emit().failed()); + } + + ASSERT_EQ(messages.size(), 1u); + EXPECT_EQ(messages.front(), "invalid opcode 0x2a\n"); +} + +TEST(DiagnosticSinkTest, SupportsConstCallableObjects) { + std::vector messages; + const ConstCollector collect{messages}; + util::DiagnosticEmitter emitter(collect); + + EXPECT_TRUE((emitter.emit() << "const callable").emit().failed()); + ASSERT_EQ(messages.size(), 1u); + EXPECT_EQ(messages.front(), "const callable"); + static_assert(!std::is_constructible_v); +} + +TEST(InFlightDiagnosticTest, EmitsOnDestruction) { + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + util::DiagnosticEmitter emitter(collect); + + { emitter.emit() << "implicit emit"; } + + ASSERT_EQ(messages.size(), 1u); + EXPECT_EQ(messages.front(), "implicit emit"); +} + +TEST(InFlightDiagnosticTest, RejectsFragmentsAfterEmission) { + auto diagnostic = util::DiagnosticEmitter{}.emit(); + EXPECT_TRUE(diagnostic.emit().failed()); + EXPECT_DEBUG_DEATH(diagnostic << "late fragment", ""); +} + +TEST(InFlightDiagnosticTest, MoveAssignmentEmitsTheOverwrittenMessage) { + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + util::DiagnosticEmitter emitter(collect); + + { + auto first = emitter.emit(); + first << "first"; + auto second = emitter.emit(); + second << "second"; + first = std::move(second); + } + + ASSERT_EQ(messages.size(), 2u); + EXPECT_EQ(messages[0], "first"); + EXPECT_EQ(messages[1], "second"); +} + +TEST(InFlightDiagnosticTest, ConvertsToFailedValueResult) { + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + util::DiagnosticEmitter emitter(collect); + + auto fail = [&]() -> util::FailureOr> { + return emitter.emit() << "bad operand"; + }; + + auto result = fail(); + EXPECT_TRUE(result.failed()); + ASSERT_EQ(messages.size(), 1u); + EXPECT_EQ(messages.front(), "bad operand"); +} + +TEST(InFlightDiagnosticTest, NoOpEmitterStillReturnsFailure) { + util::DiagnosticEmitter emitter; + bool formatted = false; + + auto fail = [&]() -> util::Result { return emitter.emit() << FormattingProbe{formatted}; }; + + EXPECT_TRUE(fail().failed()); + EXPECT_TRUE(emitter.ignores_messages()); + EXPECT_FALSE(formatted); +} + +TEST(StringDiagnosticTest, RetainsLatestMessage) { + static_assert(!std::is_copy_constructible_v); + static_assert(!std::is_move_constructible_v); + static_assert(!HasRvalueEmitter); + + util::StringDiagnostic diagnostic; + auto emitter = diagnostic.emitter(); + + EXPECT_TRUE((emitter.emit() << "invalid operand " << 7).emit().failed()); + EXPECT_EQ(diagnostic.message(), "invalid operand 7"); +} + +} // namespace From cdd0993a5f7c6e3faa1825e700a88d532ce5880a Mon Sep 17 00:00:00 2001 From: James Newling Date: Tue, 18 Aug 2026 09:43:55 -0700 Subject: [PATCH 11/27] fix(rocjitsu): route tensor DMA through wave VMID (#9775) ## Summary This change fixes the first rocJITsu tensor-DMA memory-translation failure reached by a gfx1250 TensileLite BF16 TDM GEMM. The workload comes from: ```text Tensile/Tests/common/gemm/gfx12/tdm_gfx1250.yaml problem identifier: Contraction_l_Alik_Bljk_Cijk_Dijk generated group: Cijk_Alik_Bljk_BBS_BH_UserArgs_00 representative problem: (64, 64, 1, 512) ``` ## Failure before this fix `tensilelite-client` segfaulted while executing a gfx1250 tensor load-to-LDS operation: ```text tensor_dma_detail::copy_bytes -> tensor_dma_detail::copy_dense_tensor -> execute_tensor_load_to_lds ``` The fault was a direct host dereference of a GPU virtual address such as `0x7fff2cc00000`. ## Root cause Tensor DMA accessed `GpuMemory` without binding the issuing wavefront's process ID. The access therefore used VMID zero. In local functional mode, VMID-zero passthrough treated the user-space-looking GPU VA as a host pointer instead of resolving it through the dispatched process page table. ## Fix - Add wave-scoped block read and write methods that always bind `Wavefront::process_id()`. - Route tensor-DMA global-memory accesses through those methods. - Remove the raw `InstructionComputeUnitView::memory()` accessor so instruction code cannot accidentally omit the wave VMID. - Use one `GpuMemory::read_block` or `write_block` operation per 1-, 2-, 4-, or 8-byte tensor element instead of acquiring translation locks once per byte. - Keep VMID zero as the intentional default for host, driver, and test callers. An equivalent VMID propagation exists in the broader unmerged [`users/kuhar/dbt-sim`](https://github.com/ROCm/rocm-systems/tree/users/kuhar/dbt-sim) work at commit [`08a5c461a5`](https://github.com/ROCm/rocm-systems/commit/08a5c461a58d4ce21d911740f66652206f828afc); this PR isolates the tensor-DMA correction, strengthens the instruction-facing memory contract, and adds direct regression coverage. ## Test coverage The new unit test: - registers a nonzero process page table; - maps load and store GPU VAs to separate host arrays; - proves VMID zero resolves to different storage; - verifies tensor load-to-LDS uses the wave process page table; and - verifies tensor store-from-LDS uses the same page table. Local validation includes the complete `Gfx1250ExecutionTest.TensorDma*` test set and changed-file pre-commit checks. ## Workload status With this fix, the generated TensileLite client advances past the original VMID-zero direct-VA fault. The complete stock workload still has separate tensor-DMA tail and descriptor-contract questions tracked by #9935. This PR removes the narrow translation failure and does not claim to resolve the full workload. ## Issue Tracking Closes #9774 This is the first independently reviewable rocJITsu correction tracked by #9935. (cherry picked from commit dbb7221fa7742c2641b54cf4ee56616d130e2ea0) --- .../isa/arch/amdgpu/shared/tensor_dma.h | 26 ++++--- .../src/rocjitsu/vm/amdgpu/compute_unit.h | 1 - .../src/rocjitsu/vm/amdgpu/gpu_memory.h | 10 +-- .../vm/amdgpu/instruction_compute_unit_view.h | 2 - .../src/rocjitsu/vm/amdgpu/wavefront.cpp | 12 ++++ .../src/rocjitsu/vm/amdgpu/wavefront.h | 10 +++ .../rocjitsu/tests/cdna5_tensor_dma_test.cpp | 68 +++++++++++++++++++ 7 files changed, 112 insertions(+), 17 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h index b45a6949233f..89002a74da5d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h @@ -14,6 +14,7 @@ #include #include #include +#include namespace rocjitsu { namespace amdgpu { @@ -220,8 +221,7 @@ inline void validate_supported_descriptor(const TensorDmaDescriptor &desc, bool inline void copy_bytes(const TensorDmaDescriptor &desc, Wavefront &wf, uint64_t global_element, uint64_t lds_element, bool in_bounds, bool store_from_lds) { - auto *memory = wf.cu().memory(); - if (!memory) + if (!wf.has_gpu_memory()) throw util::UnimplementedInst("tensor DMA without GPU memory"); const uint64_t global_addr = desc.global_base + global_element * desc.elem_size; @@ -233,15 +233,21 @@ inline void copy_bytes(const TensorDmaDescriptor &desc, Wavefront &wf, uint64_t } const uint32_t lds_addr = wf.lds_base() + desc.lds_base + static_cast(lds_byte); - for (uint32_t byte = 0; byte < desc.elem_size; ++byte) { - if (store_from_lds) { - if (in_bounds) - memory->write8(global_addr + byte, wf.lds().read8(lds_addr + byte)); - } else { - const uint8_t value = in_bounds ? memory->read8(global_addr + byte) : 0; - wf.lds().write8(lds_addr + byte, value); - } + std::array bytes{}; + auto element_bytes = std::span(bytes).first(desc.elem_size); + if (store_from_lds) { + if (!in_bounds) + return; + for (uint32_t byte = 0; byte < desc.elem_size; ++byte) + element_bytes[byte] = wf.lds().read8(lds_addr + byte); + wf.write_gpu_memory(global_addr, element_bytes); + return; } + + if (in_bounds) + wf.read_gpu_memory(global_addr, element_bytes); + for (uint32_t byte = 0; byte < desc.elem_size; ++byte) + wf.lds().write8(lds_addr + byte, element_bytes[byte]); } inline void copy_gather_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h index f461e7a13de7..274a6bdf23b6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h @@ -638,7 +638,6 @@ class ComputeUnitCore : public simdojo::CompositeComponent { bool functional_yield_requested_ = false; }; -inline GpuMemory *InstructionComputeUnitView::memory() const { return raw_cu().memory(); } inline L1ScalarCache &InstructionComputeUnitView::l1_scalar() { return raw_cu().l1_scalar(); } inline L1VectorCache &InstructionComputeUnitView::l1_vector() { return raw_cu().l1_vector(); } inline L2Cache *InstructionComputeUnitView::l2() const { return raw_cu().l2(); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h index 217e466749a6..580d61008c6d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h @@ -54,10 +54,12 @@ static_assert(KfdProcess::kPageSize == simdojo::SparseMemory::PAGE_SIZE, /// @brief AMDGPU VRAM memory with VMID-based per-process page table resolution. /// /// @details Mirrors the GFXHUB's VMID register file. Each process registers its -/// page table via register_process(). Every memory access carries an explicit -/// vmid parameter that selects the page table for VA-to-host translation, -/// matching real hardware where the VMID travels with each request from the -/// issuing wave through the memory hierarchy. +/// page table via register_process(). A memory access's vmid parameter selects +/// the page table for VA-to-host translation. VMID zero remains the intentional +/// default for host, driver, and test callers. Wave-issued accesses must instead +/// bind the issuing wave's process ID through a wave-scoped memory API, matching +/// real hardware where the VMID travels with each request through the memory +/// hierarchy. class GpuMemory : public simdojo::SparseMemory { public: explicit GpuMemory(std::string name) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h index a6954ae33701..5d15599c950e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h @@ -22,7 +22,6 @@ template class AmdgpuIsaOperand; namespace amdgpu { class ComputeUnitCore; -class GpuMemory; class L1ScalarCache; class L1VectorCache; class L2Cache; @@ -39,7 +38,6 @@ class InstructionComputeUnitView { public: explicit InstructionComputeUnitView(ComputeUnitCore &cu) : cu_(&cu) {} - GpuMemory *memory() const; L1ScalarCache &l1_scalar(); L1VectorCache &l1_vector(); L2Cache *l2() const; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp index 1d17b1674e7c..1c6db2ea9d5a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp @@ -12,6 +12,18 @@ Lds &Wavefront::lds() { return lds_ ? *lds_ : cu_.lds(); } const Lds &Wavefront::lds() const { return lds_ ? *lds_ : cu_.lds(); } +bool Wavefront::has_gpu_memory() const { return cu_.memory() != nullptr; } + +void Wavefront::read_gpu_memory(uint64_t addr, std::span dst) const { + assert(has_gpu_memory()); + cu_.memory()->read_block(addr, dst, process_id_); +} + +void Wavefront::write_gpu_memory(uint64_t addr, std::span src) { + assert(has_gpu_memory()); + cu_.memory()->write_block(addr, src, process_id_); +} + void Wavefront::halt() { // s_endpgm terminates the wave, frees its resources, and notifies the CP as one // action, mirroring hardware. Order matters: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h index 51427b0ae2b6..18cd06511316 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -187,6 +188,15 @@ class Wavefront : public ThreadContext { /// Passing nullptr restores the owning CU's LDS. void set_lds(Lds *lds) { lds_ = lds; } + /// @brief Return whether this wave's compute unit has GPU memory backing. + bool has_gpu_memory() const; + + /// @brief Read GPU memory in this wave's process address space. + void read_gpu_memory(uint64_t addr, std::span dst) const; + + /// @brief Write GPU memory in this wave's process address space. + void write_gpu_memory(uint64_t addr, std::span src); + /// @brief Return this workgroup's rank within its cluster. uint32_t cluster_rank() const { return cluster_rank_; } diff --git a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp index 0d3b70b837f2..3181f9705624 100644 --- a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp @@ -17,6 +17,74 @@ void write_tensor_dma_d0(amdgpu::ComputeUnitCore &cu, amdgpu::Wavefront &wf, uin static_cast((global_addr >> 32) & 0x01ffffffu) | 0x80000000u); } +TEST(Gfx1250ExecutionTest, TensorDmaUsesWaveProcessPageTable) { + constexpr uint32_t kProcessId = 1250; + constexpr uint32_t kElements = 4; + constexpr uint64_t kLoadGlobal = 0x20000000; + constexpr uint64_t kStoreGlobal = kLoadGlobal + KfdProcess::kPageSize; + constexpr std::array kLoadValues = { + 0x11000000u, + 0x22000000u, + 0x33000000u, + 0x44000000u, + }; + constexpr std::array kStoreValues = { + 0x55000000u, + 0x66000000u, + 0x77000000u, + 0x88000000u, + }; + + KfdProcess process(kProcessId); + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_process_id(kProcessId); + wf->set_lds_base(cu->allocate_lds(256)); + + std::array load_storage = kLoadValues; + std::array store_storage{}; + process.map_pages(kLoadGlobal, load_storage.data(), sizeof(load_storage)); + process.map_pages(kStoreGlobal, store_storage.data(), sizeof(store_storage)); + sim.memory->register_process(kProcessId, &process.page_table_, &process.page_table_mutex_, + process.page_table_generation()); + + // The same GPU VA intentionally resolves to different storage for VMID zero + // and for the dispatched process. Tensor DMA must use the wave's process ID. + EXPECT_EQ(sim.memory->read32(kLoadGlobal), 0u); + EXPECT_EQ(sim.memory->read32(kLoadGlobal, kProcessId), kLoadValues[0]); + + write_tensor_dma_d0(*cu, *wf, 0, kLoadGlobal); + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, kElements << 16); // Tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 0); + write_wave_sgpr(*cu, *wf, 15, kElements << 16); // Tile dim0. + write_wave_sgpr(*cu, *wf, 16, 0); + write_wave_sgpr(*cu, *wf, 17, 0); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c7c0c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + for (uint32_t i = 0; i < kElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), kLoadValues[i]); + + for (uint32_t i = 0; i < kElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kStoreValues[i]); + + write_tensor_dma_d0(*cu, *wf, 0, kStoreGlobal); + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x7c7c0c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + EXPECT_EQ(store_storage, kStoreValues); + + sim.memory->unregister_process(kProcessId); +} + TEST(Gfx1250ExecutionTest, TensorDmaD2CopiesGlobalAndLds) { Gfx1250Sim sim; auto *cu = sim.cu(); From 7bfeba6f5db79ee8cf4da2099e231415c2113308 Mon Sep 17 00:00:00 2001 From: Austin Lu Date: Tue, 18 Aug 2026 13:15:15 -0400 Subject: [PATCH 12/27] feat(rocjitsu): Lazy vgpr allocation system (#9779) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Motivation Rocjitsu currently eagerly allocates the entire VGPR file for every simulated CU. This completely dominates RSS for most kernels: the gfx942 topology alone commits approximately 1,280 MiB (1.25 GiB) of fixed VGPR storage. This PR replaces eager allocation with demand-paged backing for VGPRs. RSS is significantly reduced on current benchmarks and workloads, while performance is also maintained or improved. ## Technical Details - Implement lazy VGPR allocation using a portable software page table with 4KiB pages, allocated and zero-initialized on first non-const access. - Contiguous VGPR range guarantee is lost: This was only ever used for checkpointing save and restore: A replacement mechanism to copy pages into the checkpoint buffer is implemented. - Add a saturation benchmark with full-output checksum validation and compiled resource-profile verification. ## Issue Tracking N/A ## Test Plan Perform benchmarking on workloads available in rocjitsu-test-coprpus/IREE. ## Test Result ### IREE e2e Softmax Test The `softmax_static_10x256x256xf32` IREE corpus workload processes 655,360 FP32 elements and writes a 2.5 MiB output. It was compiled independently for gfx942 and gfx950, executed through IREE's HIP runtime under the corresponding rocjitsu simulator, and compared bit-for-bit with the checked-in NumPy golden output. Each exact-output total combines five baseline and five lazy-storage executions. The process measurements retained for the RSS and runtime summary were: | Target | Build | Mean peak RSS (KiB) | Mean runtime | |--------|----------------|--------------------:|-------------:| | gfx942 | Baseline | 1,627,477 | 2.09 s | | gfx942 | Lazy registers | 316,328 | 0.70 s | | gfx950 | Baseline | 1,387,861 | 1.84 s | | gfx950 | Lazy registers | 338,881 | 0.72 s | ### Corpus Kernel Results | Workload | Register pressure | Baseline median | Lazy median | Baseline peak RSS | Lazy peak RSS | Result | |---------------------------|--------------------------|-----------:|------------:|------------------:|--------------:|-------------------------------| | Startup, gfx942 | Fixed topology only | 0.86 s | 0.13 s | 1,511,424 KiB | 198,656 KiB | 84.9% faster, 86.9% less RSS | | Corpus matvec set | 6–88 VGPR | 3.26 s | 1.86 s | 1,616,700 KiB | 305,864 KiB | 42.9% faster, 81.1% less RSS | | Corpus HipKittens 256^3 | 248 VGPR | 2.03 s | 0.60 s | 1,626,112 KiB | 314,368 KiB | 70.4% faster, 80.7% less RSS | | Corpus hip-matmul 128^3 | Up to 133 VGPR plus AGPR | 6.34 s | 4.91 s | 1,615,000 KiB | 302,940 KiB | 22.6% faster, 81% less RSS | All three completed corpus workloads produced their expected correctness results. The fixed-RSS reduction is 1,312,768 KiB. That closely matches the original estimate of approximately 1,281 MiB to eagerly committed VGPR files. ### Adversarial Kernel Analysis The storage cost has three distinct sections: 1. Untouched VGPR pages consume no RSS. 2. The first access during a wave dispatch commits pages, with cost (RSS and time) growing approximately linearly with the number of touched pages. 3. Subsequent operations use the same contiguous pointer path as the preexisting eager implementation and show no pressure-dependent penalty. Physical pages are returned when the wave retires. The worst case is therefore an extremely short kernel that declares and touches nearly every VGPR across many CUs but performs very little work with them. This is not a common real-world workload pattern. The observed runtime penalty is about 8–9% for that deliberately adversarial initialization-only case. Amortization from eight rounds of computation (applying one XOR-multiply-add sequence) over every live VGPR reduces the penalty below 0.7%, while retaining an 81.2% peak-RSS reduction. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit 2779247222398de832159e19c7aae4d54a9d0cb7) --- emulation/rocjitsu/CMakeLists.txt | 1 - emulation/rocjitsu/docs/simdojo.md | 89 ++++ .../src/rocjitsu/config/checkpoint.cpp | 44 +- .../src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h | 1 + .../isa/arch/amdgpu/shared/cdna_isa_base.h | 11 +- .../isa/arch/amdgpu/shared/mma_exec.h | 354 ++++++++++----- .../isa/arch/amdgpu/shared/rdna_isa_base.h | 11 +- .../rocjitsu/src/rocjitsu/isa/isa_traits.h | 4 + .../src/rocjitsu/vm/amdgpu/compute_unit.cpp | 31 +- .../src/rocjitsu/vm/amdgpu/compute_unit.h | 94 +++- .../src/rocjitsu/vm/amdgpu/register_access.h | 39 +- .../simdojo/components/register_file.h | 416 +++++++++++++++++- emulation/rocjitsu/tests/CMakeLists.txt | 3 + emulation/rocjitsu/tests/amdgpu_vm_test.cpp | 15 +- .../rocjitsu/tests/cdna5_cluster_test.cpp | 13 +- emulation/rocjitsu/tests/config_test.cpp | 33 +- .../rocjitsu/tests/register_access_test.cpp | 40 +- .../rocjitsu/tests/register_file_test.cpp | 247 +++++++++++ .../mfma_lazy_storage_test.cpp | 48 ++ .../simd_correctness/mfma_simd_exact_test.cpp | 129 +++++- .../simd_correctness/mma_exact_test_support.h | 18 +- .../rocjitsu/tests/vgpr_redispatch_test.cpp | 87 ++++ 22 files changed, 1537 insertions(+), 191 deletions(-) create mode 100644 emulation/rocjitsu/tests/register_file_test.cpp create mode 100644 emulation/rocjitsu/tests/simd_correctness/mfma_lazy_storage_test.cpp create mode 100644 emulation/rocjitsu/tests/vgpr_redispatch_test.cpp diff --git a/emulation/rocjitsu/CMakeLists.txt b/emulation/rocjitsu/CMakeLists.txt index a8ddda566eb3..b244c384e546 100644 --- a/emulation/rocjitsu/CMakeLists.txt +++ b/emulation/rocjitsu/CMakeLists.txt @@ -405,7 +405,6 @@ add_subdirectory(fuzz/decode) if(CMAKE_SYSTEM_NAME STREQUAL "Linux") add_subdirectory(tools/rocjitsu) endif() -# Tests and scaling tools. if(BUILD_TESTING) add_subdirectory(tests) endif() diff --git a/emulation/rocjitsu/docs/simdojo.md b/emulation/rocjitsu/docs/simdojo.md index 2e764811b0a4..2ea3d16681e6 100644 --- a/emulation/rocjitsu/docs/simdojo.md +++ b/emulation/rocjitsu/docs/simdojo.md @@ -209,6 +209,95 @@ controllers. indexed read/write access. **VectorReg** (`vector_reg.h`) models a SIMD-width vector register with per-element access. +### Register-file storage + +The functional GPU model provisions vector-register storage for every fixed +wavefront slot in each simulated compute unit. Slots are independent of +hardware occupancy: a wave that uses many registers still occupies one +simulator slot, and register pressure does not reduce the number of admitted +waves. For the shipped gfx942 configuration, the vector backing has the +following dimensions: + +| Quantity | Value | +|---------------------------|--------------------------------------------| +| Simulated compute units | 320 | +| Wavefront slots per CU | 32 | +| Registers per slot | 512 combined VGPR and AGPR entries | +| Register width | 64 lanes × 4 bytes | +| Complete vector backing | 1,280 MiB | + +`RegisterFile` divides the physical VGPR index space into fixed 4 KiB chunks. +An untouched chunk is represented by a null entry and reads as zero; its +storage is allocated and zero-initialized on the first mutable access. Retiring +a wave releases wholly covered chunks and clears any shared boundary chunk. +The implementation uses only portable C++ allocation and does not require +virtual-memory APIs. Mutable handles and handles into materialized registers +remain stable until their allocation retires, but the complete register file is +deliberately not contiguous. Const access to an unmaterialized register observes +its logical zero value through shared immutable backing without allocating a +chunk. That read-only handle is an ephemeral value observation, not a persistent +storage identity, and need not observe a later write through another handle. + +This is a functional storage model, not a model of a physical register file. +In particular, filling all 32 simulator slots with high-pressure waves can +represent an occupancy that hardware could not admit. That distinction is +important when interpreting memory measurements or using register pressure to +approximate hardware throughput. + +#### Representative workloads + +The fixed-topology and IREE measurements were collected on 2026-08-10 from +rocjitsu revision `49e6ddafeb9fd8cadda1c78b891466fd498ec676`. Fixed topology +reports the median of six processes; IREE reports the median of five processes, +all of which matched the checked-in output exactly. The CTS rows report the +median of three source-identical processes from rocjitsu revision +`4d5779c15beb0d9495b319dce5d906e966275e23` and test-corpus revision +`ce5da512188dd40de0bc7da298ec11b587d8fdd3`; all tests passed. Every build was +Release, pinned to CPU 8, and used an AMD EPYC 9554 host running Linux 6.8. + +| Workload | Eager runtime | Software runtime | Eager peak RSS | Software peak RSS | Effect | +|--------------------------------------|--------------:|-----------------:|---------------:|------------------:|-------------------------------------| +| Fixed topology, no kernel | 0.87 s | 0.125 s | 1,511,424 KiB | 201,728 KiB | 85.6% faster, 86.7% less RSS | +| IREE softmax, exact output | 2.50 s | 0.99 s | 1,630,208 KiB | 326,656 KiB | 60.4% faster, 80.0% less RSS | +| CTS math | 28.37 s | 27.94 s | 2,235,924 KiB | 926,788 KiB | 1.5% faster, 58.5% less RSS | +| CTS MFMA | 151.40 s | 150.78 s | 2,235,392 KiB | 926,720 KiB | 0.4% faster, 58.5% less RSS | + +Unlike fixed topology and the shorter IREE workload, the CTS suites are +dominated by simulated instruction execution and therefore amortize the fixed +initialization work that lazy storage eliminates. Across three runs, the +startup proxy (whole-process wall time minus test-body time) fell from about +1.29 seconds to 0.54 seconds. Test-body time increased by 1.2% for math and was +unchanged to measurement precision for MFMA (+0.1%). The result is a smaller +end-to-end runtime improvement even as peak RSS falls by 58.5%. + +#### Worst-case saturation validation + +The qualified gfx942 saturation workload was measured on 2026-08-10 from +rocjitsu revision `49e6ddafeb9fd8cadda1c78b891466fd498ec676`. The +representative case places eight waves on each of one XCD's 40 CUs and reports +three-launch medians. The all-slot case deliberately fills all 32 functional +simulator slots on all 320 CUs with 253-VGPR waves—an occupancy that hardware +could not admit—and reports one checksum-validated launch. + +| Saturation runtime | Eager | Software lazy | Change | +|---------------------------------------------|------------:|--------------:|-------------| +| 253-VGPR initialization-only median launch | 156.201 ms | 157.479 ms | 0.8% slower | +| 253-VGPR eight-update median launch | 1,332.955 ms | 1,335.671 ms | 0.2% slower | +| All-slot 253-VGPR eight-update timed launch | 48.127 s | 48.780 s | 1.4% slower | + +Peak RSS is a process-wide high-water measurement. The representative sweep +therefore has one result covering all 9--253-VGPR pressure points rather than +separate values for its individual launch timings. + +| Saturation peak RSS | Eager | Software lazy | Change | +|------------------------------------|---------------:|--------------:|----------------| +| Complete 9--253-VGPR sweep | 1,609,728 KiB | 318,280 KiB | 80.2% less RSS | +| All slots, 253 VGPR, eight updates | 1,622,016 KiB | 967,064 KiB | 40.4% less RSS | + +The qualified workload, complete methodology, and reproduction commands are +pinned at rocjitsu test corpus revision +[`b3f5fa8a263ee2cd83666a62bc18731b09b1166a`](https://github.com/ROCm/rocjitsu-test-corpus/tree/b3f5fa8a263ee2cd83666a62bc18731b09b1166a/corpus/kernels/benchmarks/vgpr_saturation). + --- ## Messages and Events diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp index d1fcbf3e8bce..407331b07610 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp @@ -8,7 +8,8 @@ #include "checkpoint_generated.h" #include "flatbuffers/flatbuffers.h" -#include +#include +#include #include #include #include @@ -18,6 +19,32 @@ namespace config { namespace { +flatbuffers::Offset> +serialize_vgpr_block(flatbuffers::FlatBufferBuilder &builder, const amdgpu::ComputeUnitCore &cu, + uint32_t base) { + const size_t register_bytes = static_cast(cu.wf_size()) * sizeof(uint32_t); + const size_t block_bytes = static_cast(cu.vgpr_allocation_block_size()) * register_bytes; + uint8_t *serialized = nullptr; + const auto offset = builder.CreateUninitializedVector(block_bytes, &serialized); + cu.copy_raw_vgprs_to(base, cu.vgpr_allocation_block_size(), + {reinterpret_cast(serialized), block_bytes}); + return offset; +} + +/// Restore sparse checkpoint data into a freshly allocated, zeroed VGPR block. +/// Zero source registers are skipped to preserve lazy backing; this is a full +/// restore, rather than a merge, only while the destination begins entirely +/// zeroed. +void restore_vgpr_block_into_zeroed_storage(amdgpu::ComputeUnitCore &cu, uint32_t base, + const flatbuffers::Vector &stored) { + const size_t register_bytes = static_cast(cu.wf_size()) * sizeof(uint32_t); + const size_t block_bytes = static_cast(cu.vgpr_allocation_block_size()) * register_bytes; + const size_t copy_size = std::min(stored.size(), block_bytes); + cu.restore_raw_vgprs_into_zeroed_storage( + base, cu.vgpr_allocation_block_size(), + {reinterpret_cast(stored.data()), copy_size}); +} + /// @brief Serialize the SoC configuration into a FlatBuffer SimulationConfig. flatbuffers::Offset serialize_config(flatbuffers::FlatBufferBuilder &builder, const SoC &soc, @@ -121,10 +148,7 @@ void save_checkpoint(const std::string &path, const SoC &soc, uint64_t tick, auto sgprs_vec = builder.CreateVector(cu->sgpr_data(w->sgpr_alloc().base), w->num_sgprs()); - size_t vgpr_bytes = static_cast(cu->vgpr_allocation_block_size()) * - static_cast(w->wf_size()) * sizeof(uint32_t); - auto vgprs_vec = - builder.CreateVector(cu->raw_vgpr_data(w->vgpr_alloc().base), vgpr_bytes); + auto vgprs_vec = serialize_vgpr_block(builder, *cu, w->vgpr_alloc().base); auto wfs = fb::CreateWavefrontState(builder, w->wf_id(), w->wg_id(), w->pc, w->exec_raw(), w->vcc(), w->m0(), w->is_halted(), w->status_raw(), @@ -261,12 +285,10 @@ LoadedConfig restore_checkpoint(const std::string &path) { } } - if (auto *vgprs = wf_state->vgprs()) { - size_t vgpr_bytes = static_cast(cu->vgpr_allocation_block_size()) * - static_cast(wf->wf_size()) * sizeof(uint32_t); - size_t copy_size = std::min(vgprs->size(), vgpr_bytes); - std::memcpy(cu->raw_vgpr_data(wf->vgpr_alloc().base), vgprs->data(), copy_size); - } + // dispatch_wf_at() has just allocated this block, so RegisterFile::allocate()'s + // zero-state postcondition satisfies the sparse restore helper's precondition. + if (auto *vgprs = wf_state->vgprs()) + restore_vgpr_block_into_zeroed_storage(*cu, wf->vgpr_alloc().base, *vgprs); } } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h index e0e396252bcf..d7e46239dd77 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h @@ -70,6 +70,7 @@ struct Isa : amdgpu::RdnaIsaBase { using StatusReg = rocjitsu::cdna5::StatusReg; static constexpr uint32_t WF_SIZE_MAX = 32; ///< gfx1250 is Wave32-only. + static constexpr uint32_t MAX_WF_SLOTS = 64; // gfx1250 uses the RDNA base decoder shape, but its MODE[27] enables VGPR // high-bank indexing rather than RDNA4 DISABLE_PERF. static constexpr bool MODE_HAS_GPR_IDX_EN = true; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/cdna_isa_base.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/cdna_isa_base.h index 5937732da911..77fe3602b4ae 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/cdna_isa_base.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/cdna_isa_base.h @@ -91,10 +91,13 @@ class CdnaStatusReg : public ::util::Bitfield<32> { /// `Isa` struct adds `Decoder`, `MachineInst`, `OperandType`, and `StatusReg` /// type aliases. struct CdnaIsaBase { - static constexpr uint32_t WF_SIZE = 64; ///< Lanes per wavefront (Wave64). - static constexpr uint32_t WF_SIZE_MAX = 64; ///< CDNA is Wave64-only. - static constexpr uint32_t MAX_SGPRS_PER_WF = 102; ///< SGPRs per wavefront. - static constexpr uint32_t MAX_VGPRS_PER_WF = 256; ///< VGPRs per wavefront. + static constexpr uint32_t WF_SIZE = 64; ///< Lanes per wavefront (Wave64). + static constexpr uint32_t WF_SIZE_MAX = 64; ///< CDNA is Wave64-only. + static constexpr uint32_t MAX_WF_SLOTS = 32; ///< Maximum simulated CU wave slots. + static constexpr uint32_t MAX_SGPRS_PER_WF = 102; ///< SGPRs per wavefront. + static constexpr uint32_t MAX_VGPRS_PER_WF = 256; ///< VGPRs per wavefront. + static constexpr uint32_t MAX_ADDRESSABLE_VGPRS_PER_WF = + MAX_VGPRS_PER_WF; ///< Maximum ordinary VGPR address span. static constexpr uint32_t MAX_ACC_VGPRS_PER_WF = 0; ///< AccVGPRs (0 = absent; CDNA1 default). static constexpr uint8_t WAITCNT_LGKMCNT_MASK = 0x0F; ///< lgkmcnt mask in S_WAITCNT [11:8]. static constexpr bool SRAM_ECC = false; ///< CDNA1 default: no SRAM ECC. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/mma_exec.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/mma_exec.h index 49e601cf5fbd..7c6cbae1e1f5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/mma_exec.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/mma_exec.h @@ -33,10 +33,15 @@ #include #include +#include #include +#include #include +#include #include #include +#include +#include #include namespace rocjitsu { @@ -1025,9 +1030,9 @@ inline uint32_t mfma_dense_reg_count(uint64_t element_count, uint32_t element_bi // // MFMA/WMMA specializations below read dense source regions through // RegisterAccess views. Acquiring a read view observes the whole physical VGPR -// region, then the fast path can use zero-copy lane spans/pointers for the math. -// Keep the matrix-specific size calculations here so individual specializations -// do not open-code plugin notification or raw region sizing. +// region. Logical traversal and copying remain independent of the backing-store +// layout. Keep the matrix-specific size calculations here so individual +// specializations do not open-code plugin notification or raw region sizing. // // This is still only the physical-register-region layer. The broader cleanup is // to move operand-based SIMD paths onto the same facade and then make direct raw @@ -1064,7 +1069,74 @@ inline RegisterAccess::VgprWriteRegion write_mfma_acc32_region(auto &cu, uint32_ return regs.write_vgpr_region(base, reg_count, mfma_full_lane_mask(wf_size)); } -struct MatrixReadRegions { +template +void convert_packed_matrix_region(const RegisterAccess::VgprReadRegion &source, + Destination *destination, size_t element_count, + uint32_t elements_per_word, Convert convert) { + const size_t elements_per_reg = static_cast(source.wf_size()) * elements_per_word; + size_t converted = 0; + source.for_each([&](std::span lanes) { + if (converted == element_count) + return; + const size_t count = std::min(elements_per_reg, element_count - converted); + convert(lanes.data(), destination + converted, count); + converted += count; + }); + assert(converted == element_count && "packed conversion exceeds matrix read region"); +} + +template +void copy_matrix_region_words(const RegisterAccess::VgprReadRegion &source, + uint32_t (&destination)[Capacity]) { + const size_t word_count = static_cast(source.reg_count()) * source.wf_size(); + assert(word_count <= Capacity && "matrix read region exceeds snapshot capacity"); + if (word_count > Capacity) + std::abort(); + source.copy_to({destination, word_count}); +} + +inline void convert_f16_matrix_region(const RegisterAccess::VgprReadRegion &source, + float *destination, size_t element_count) { + convert_packed_matrix_region(source, destination, element_count, /*elements_per_word=*/2, + [](const uint32_t *words, float *out, size_t count) { + util::f16_to_f32_block(reinterpret_cast(words), + out, count); + }); +} + +inline void convert_bf16_matrix_region(const RegisterAccess::VgprReadRegion &source, + float *destination, size_t element_count) { + convert_packed_matrix_region(source, destination, element_count, /*elements_per_word=*/2, + [](const uint32_t *words, float *out, size_t count) { + util::bf16_to_f32_block(reinterpret_cast(words), + out, count); + }); +} + +inline void convert_i8_matrix_region(const RegisterAccess::VgprReadRegion &source, + int32_t *destination, size_t element_count) { + convert_packed_matrix_region(source, destination, element_count, /*elements_per_word=*/4, + [](const uint32_t *words, int32_t *out, size_t count) { + util::i8_to_i32_block(reinterpret_cast(words), out, + count); + }); +} + +inline void convert_u8_matrix_region(const RegisterAccess::VgprReadRegion &source, + int32_t *destination, size_t element_count) { + convert_packed_matrix_region(source, destination, element_count, /*elements_per_word=*/4, + [](const uint32_t *words, int32_t *out, size_t count) { + util::u8_to_i32_block(reinterpret_cast(words), + out, count); + }); +} + +class MatrixReadRegions { +public: + explicit MatrixReadRegions(RegisterAccess::VgprReadRegion a, RegisterAccess::VgprReadRegion b, + std::optional acc) + : a(std::move(a)), b(std::move(b)), acc(std::move(acc)) {} + RegisterAccess::VgprReadRegion a; RegisterAccess::VgprReadRegion b; std::optional acc; @@ -1083,8 +1155,8 @@ inline MatrixReadRegions read_mfma_fast_path_regions(auto &cu, uint32_t s0, uint uint32_t acc_regs = mfma_dense_reg_count(static_cast(M) * N * B, 32, wf_size); acc_region.emplace(regs.read_vgpr_region(s2, acc_regs, lane_mask)); } - return {regs.read_vgpr_region(s0, a_regs, lane_mask), - regs.read_vgpr_region(s1, b_regs, lane_mask), acc_region}; + return MatrixReadRegions(regs.read_vgpr_region(s0, a_regs, lane_mask), + regs.read_vgpr_region(s1, b_regs, lane_mask), std::move(acc_region)); } inline void observe_mfma_fast_path_reads(auto &cu, uint32_t s0, uint32_t s1, uint32_t s2, @@ -1107,8 +1179,8 @@ inline MatrixReadRegions read_wmma_fast_path_regions(auto &cu, uint32_t s0, uint uint32_t acc_regs = mfma_dense_reg_count(static_cast(M) * N, acc_bits, wf_size); acc_region.emplace(regs.read_vgpr_region(s2, acc_regs, lane_mask)); } - return {regs.read_vgpr_region(s0, a_regs, lane_mask), - regs.read_vgpr_region(s1, b_regs, lane_mask), acc_region}; + return MatrixReadRegions(regs.read_vgpr_region(s0, a_regs, lane_mask), + regs.read_vgpr_region(s1, b_regs, lane_mask), std::move(acc_region)); } inline void observe_wmma_fast_path_reads(auto &cu, uint32_t s0, uint32_t s1, uint32_t s2, @@ -1840,13 +1912,13 @@ inline void exec_wmma_f32_16x16x32_f16(auto &cu, uint32_t dst, uint32_t s0, uint const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/32, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_wmma_output_region(cu, dst, M, N, /*output_bits=*/32, wf); alignas(64) float A_buf[M * K]; // A[row][k] alignas(64) float B_buf[K * N]; // B[k][col] alignas(64) float C_buf[M * N]; // C[row][col] + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // A and B each occupy 8 VGPRs x wf lanes = 2*8*wf packed f16 (16 f16/lane // for K=32). Bulk-convert the region to f32 once, then the hoist is a pure // f32 index-shuffle (f16 j of word w sub s -> flat (w*wf+lane)*2+s). @@ -1854,14 +1926,14 @@ inline void exec_wmma_f32_16x16x32_f16(auto &cu, uint32_t dst, uint32_t s0, uint const uint32_t n_halves = 2 * NUM_IN_REGS * wf; alignas(64) float A_f32[2 * NUM_IN_REGS * 64]; alignas(64) float B_f32[2 * NUM_IN_REGS * 64]; - util::f16_to_f32_block(reinterpret_cast(a_words), A_f32, n_halves); - util::f16_to_f32_block(reinterpret_cast(b_words), B_f32, n_halves); + convert_f16_matrix_region(reads.a, A_f32, n_halves); + convert_f16_matrix_region(reads.b, B_f32, n_halves); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_32(M, N, row, col); C_buf[row * N + col] = apply_wmma_c_modifier( (const_acc != ACC_FROM_VGPR) ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]), + : std::bit_cast(C_words[out.reg * wf + out.lane]), c_modifier); } for (uint32_t row = 0; row < M; ++row) @@ -1918,13 +1990,13 @@ inline void exec_wmma_f32_16x16x32_bf16(auto &cu, uint32_t dst, uint32_t s0, uin const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/32, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_wmma_output_region(cu, dst, M, N, /*output_bits=*/32, wf); alignas(64) float A_buf[M * K]; // A[row][k] alignas(64) float B_buf[K * N]; // B[k][col] alignas(64) float C_buf[M * N]; // C[row][col] + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // A and B each occupy 8 VGPRs x wf lanes = 2*8*wf packed bf16 (16 bf16/lane // for K=32). Bulk-convert the region to f32 once, then the hoist is a pure // f32 index-shuffle (bf16 j of word w sub s -> flat (w*wf+lane)*2+s). @@ -1932,14 +2004,14 @@ inline void exec_wmma_f32_16x16x32_bf16(auto &cu, uint32_t dst, uint32_t s0, uin const uint32_t n_halves = 2 * NUM_IN_REGS * wf; alignas(64) float A_f32[2 * NUM_IN_REGS * 64]; alignas(64) float B_f32[2 * NUM_IN_REGS * 64]; - util::bf16_to_f32_block(reinterpret_cast(a_words), A_f32, n_halves); - util::bf16_to_f32_block(reinterpret_cast(b_words), B_f32, n_halves); + convert_bf16_matrix_region(reads.a, A_f32, n_halves); + convert_bf16_matrix_region(reads.b, B_f32, n_halves); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_32(M, N, row, col); C_buf[row * N + col] = apply_wmma_c_modifier( (const_acc != ACC_FROM_VGPR) ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]), + : std::bit_cast(C_words[out.reg * wf + out.lane]), c_modifier); } for (uint32_t row = 0; row < M; ++row) @@ -2004,6 +2076,15 @@ void f8_to_f32_block(const uint32_t *words, float *dst, size_t n) { util::bf8_e5m2_ocp_to_f32_block(reinterpret_cast(words), dst, n); } +template +void convert_f8_matrix_region(const RegisterAccess::VgprReadRegion &source, float *destination, + size_t element_count) { + convert_packed_matrix_region(source, destination, element_count, /*elements_per_word=*/4, + [](const uint32_t *words, float *out, size_t count) { + f8_to_f32_block(words, out, count); + }); +} + /// Fast path for the dense f32-out fp8/bf8-input WMMA shapes /// (v_wmma_f32_16x16x{64,128}_{fp8,bf8}_{fp8,bf8}, gfx1250, wave32). Identical /// to the f16/bf16 specializations except the bulk input convert is the f8 LUT @@ -2034,25 +2115,25 @@ void exec_wmma_f32_f8_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uin const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/32, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_wmma_output_region(cu, dst, M, N, /*output_bits=*/32, wf); alignas(64) float A_buf[M * K]; // A[row][k] alignas(64) float B_buf[K * N]; // B[k][col] alignas(64) float C_buf[M * N]; // C[row][col] + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // Bulk-convert each whole packed f8 region to f32 once, then the hoist is a // pure f32 index-shuffle (byte of word w lane l sub s -> (w*wf+l)*4+s). alignas(64) float A_f32[M * K]; alignas(64) float B_f32[N * K]; - f8_to_f32_block(a_words, A_f32, M * K); - f8_to_f32_block(b_words, B_f32, N * K); + convert_f8_matrix_region(reads.a, A_f32, M * K); + convert_f8_matrix_region(reads.b, B_f32, N * K); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_32(M, N, row, col); C_buf[row * N + col] = apply_wmma_c_modifier( (const_acc != ACC_FROM_VGPR) ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]), + : std::bit_cast(C_words[out.reg * wf + out.lane]), c_modifier); } for (uint32_t row = 0; row < M; ++row) @@ -2114,30 +2195,34 @@ void exec_wmma_f32_f32_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, ui const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/32, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_wmma_output_region(cu, dst, M, N, /*output_bits=*/32, wf); alignas(64) float A_buf[M * K]; alignas(64) float B_buf[K * N]; alignas(64) float C_buf[M * N]; + alignas(64) uint32_t A_words[M * K]; + alignas(64) uint32_t B_words[N * K]; + alignas(64) uint32_t C_words[M * N]; + copy_matrix_region_words(reads.a, A_words); + copy_matrix_region_words(reads.b, B_words); + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_32(M, N, row, col); C_buf[row * N + col] = apply_wmma_c_modifier( (const_acc != ACC_FROM_VGPR) ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]), + : std::bit_cast(C_words[out.reg * wf + out.lane]), c_modifier); } for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { auto al = wmma_input_loc(M, K, row, k, in_bits); - A_buf[row * K + k] = std::bit_cast(a_words[al.vgpr_offset * wf + al.lane]); + A_buf[row * K + k] = std::bit_cast(A_words[al.vgpr_offset * wf + al.lane]); } for (uint32_t k = 0; k < K; ++k) for (uint32_t col = 0; col < N; ++col) { auto bl = wmma_input_loc(N, K, col, k, in_bits); - B_buf[k * N + col] = std::bit_cast(b_words[bl.vgpr_offset * wf + bl.lane]); + B_buf[k * N + col] = std::bit_cast(B_words[bl.vgpr_offset * wf + bl.lane]); } for (uint32_t row = 0; row < M; ++row) for (uint32_t c0 = 0; c0 < N; c0 += W) { @@ -2570,24 +2655,24 @@ void exec_wmma_f16_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uint32 const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/16, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = readwrite_wmma_output_region(cu, dst, M, N, /*output_bits=*/16, wf); alignas(64) float A_buf[M * K]; alignas(64) float B_buf[K * N]; alignas(64) float C_buf[M * N]; alignas(64) float A_f32[M * K]; alignas(64) float B_f32[N * K]; - util::f16_to_f32_block(reinterpret_cast(a_words), A_f32, M * K); - util::f16_to_f32_block(reinterpret_cast(b_words), B_f32, N * K); + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); + convert_f16_matrix_region(reads.a, A_f32, M * K); + convert_f16_matrix_region(reads.b, B_f32, N * K); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_16(M, N, row, col); if (const_acc != ACC_FROM_VGPR) { C_buf[row * N + col] = std::bit_cast(const_acc); } else { - uint32_t raw = c_words[out.reg * wf + out.lane]; + uint32_t raw = C_words[out.reg * wf + out.lane]; C_buf[row * N + col] = util::f16_to_f32(static_cast((raw >> (out.sub_element * 16)) & 0xFFFF)); } @@ -2696,24 +2781,24 @@ void exec_wmma_bf16_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uint3 const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/16, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = readwrite_wmma_output_region(cu, dst, M, N, /*output_bits=*/16, wf); alignas(64) float A_buf[M * K]; alignas(64) float B_buf[K * N]; alignas(64) float C_buf[M * N]; alignas(64) float A_f32[M * K]; alignas(64) float B_f32[N * K]; - util::bf16_to_f32_block(reinterpret_cast(a_words), A_f32, M * K); - util::bf16_to_f32_block(reinterpret_cast(b_words), B_f32, N * K); + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); + convert_bf16_matrix_region(reads.a, A_f32, M * K); + convert_bf16_matrix_region(reads.b, B_f32, N * K); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_16(M, N, row, col); if (const_acc != ACC_FROM_VGPR) { C_buf[row * N + col] = std::bit_cast(const_acc); } else { - uint32_t raw = c_words[out.reg * wf + out.lane]; + uint32_t raw = C_words[out.reg * wf + out.lane]; C_buf[row * N + col] = util::bf16_to_f32(static_cast((raw >> (out.sub_element * 16)) & 0xFFFF)); } @@ -2798,24 +2883,24 @@ void exec_wmma_f16_f8_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uin const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/16, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = readwrite_wmma_output_region(cu, dst, M, N, /*output_bits=*/16, wf); alignas(64) float A_buf[M * K]; alignas(64) float B_buf[K * N]; alignas(64) float C_buf[M * N]; alignas(64) float A_f32[M * K]; alignas(64) float B_f32[N * K]; - f8_to_f32_block(a_words, A_f32, M * K); - f8_to_f32_block(b_words, B_f32, N * K); + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); + convert_f8_matrix_region(reads.a, A_f32, M * K); + convert_f8_matrix_region(reads.b, B_f32, N * K); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = wmma_output_loc_16(M, N, row, col); if (const_acc != ACC_FROM_VGPR) { C_buf[row * N + col] = std::bit_cast(const_acc); } else { - uint32_t raw = c_words[out.reg * wf + out.lane]; + uint32_t raw = C_words[out.reg * wf + out.lane]; C_buf[row * N + col] = util::f16_to_f32(static_cast((raw >> (out.sub_element * 16)) & 0xFFFF)); } @@ -3351,26 +3436,26 @@ inline void exec_wmma_i32_16x16x64_iu8(auto &cu, uint32_t dst, uint32_t s0, uint const uint32_t wf = cu.wf_size(); auto reads = read_wmma_fast_path_regions(cu, s0, s1, s2, M, N, K, in_bits, /*acc_bits=*/32, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; // Accumulate in unsigned 32-bit (wrap is well-defined; identical mod 2^32 // to the intended signed wrap), sign-restore via int32 cast at pack time. alignas(64) uint32_t A_buf[M * K]; // A[row][k] (sign-/zero-extended bits) alignas(64) uint32_t B_buf[K * N]; // B[k][col] (sign-/zero-extended bits) alignas(64) uint32_t S_buf[M * N]; // sum-of-products, accumulator added at pack + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // Bulk-extend the packed byte regions to int32 once, then the hoist is a // pure i32 index-shuffle (byte j of word w lane l sub s -> (w*wf+l)*4+s). alignas(64) int32_t A_i32[M * K]; alignas(64) int32_t B_i32[N * K]; if (a_signed) - util::i8_to_i32_block(reinterpret_cast(a_words), A_i32, M * K); + convert_i8_matrix_region(reads.a, A_i32, M * K); else - util::u8_to_i32_block(reinterpret_cast(a_words), A_i32, M * K); + convert_u8_matrix_region(reads.a, A_i32, M * K); if (b_signed) - util::i8_to_i32_block(reinterpret_cast(b_words), B_i32, N * K); + convert_i8_matrix_region(reads.b, B_i32, N * K); else - util::u8_to_i32_block(reinterpret_cast(b_words), B_i32, N * K); + convert_u8_matrix_region(reads.b, B_i32, N * K); for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { auto al = wmma_input_loc(M, K, row, k, in_bits); @@ -3402,7 +3487,7 @@ inline void exec_wmma_i32_16x16x64_iu8(auto &cu, uint32_t dst, uint32_t s0, uint int64_t acc = (const_acc != ACC_FROM_VGPR) ? static_cast(static_cast(const_acc)) - : static_cast(static_cast(c_words[out.reg * wf + out.lane])); + : static_cast(static_cast(C_words[out.reg * wf + out.lane])); acc += static_cast(static_cast(S_buf[row * N + col])); writes.set_linear_word(out.reg * wf + out.lane, pack_i32_acc(acc, clamp)); } @@ -4035,10 +4120,12 @@ void exec_smfmac_f32_32x32x64_fp8(auto &cu, uint32_t dst, uint32_t s0, uint32_t /// the compiler fully unroll the 16-row x 32-K inner matmul into straight-line /// AVX-512 FMAs — a runtime-dimension loop is materially slower on this hot /// path. Hoists A and B into dense f32 buffers via extract_f16, runs the -/// matmul as 16 zmm-wide f32 FMA rows (512 zmm FMAs per MFMA), and scatters -/// directly back to VGPRs (no Result staging vector). VGPR access is batched -/// through observed register-access regions (one view per operand, no -/// per-element virtual read_vgpr/write_vgpr). Falls back to the generic exec_f32 when: +/// matmul as 16 zmm-wide f32 FMA rows (512 zmm FMAs per MFMA). Batched shapes +/// stage every result on the stack and publish only after all operand reads, +/// preserving destructive-overlap semantics without a heap-backed Result +/// vector. VGPR access is batched through observed register-access regions +/// (one view per operand, no per-element virtual read_vgpr/write_vgpr). Falls +/// back to the generic exec_f32 when: /// - is unavailable /// - host native_simd is not 16 lanes (i.e. no AVX-512) /// - cbsz/blgp lane permutation is non-default @@ -4070,53 +4157,62 @@ void exec_f32_mfma_f32_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, ui const uint32_t wf = cu.wf_size(); auto reads = read_mfma_fast_path_regions(cu, s0, s1, s2, M, N, K, BATCH, in_bits, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_mfma_acc32_region(cu, dst, M, N, BATCH, wf); alignas(64) float A_buf[M * K]; alignas(64) float B_buf[K * N]; - alignas(64) float C_buf[M * N]; + static_assert(M * N * BATCH * sizeof(float) <= 8 * 1024, + "specialized MFMA result staging exceeds the stack budget"); + alignas(64) float C_buf[M * N * BATCH]; + alignas(64) uint32_t A_words[M * K * BATCH]; + alignas(64) uint32_t B_words[N * K * BATCH]; + alignas(64) uint32_t C_words[M * N * BATCH]; + copy_matrix_region_words(reads.a, A_words); + copy_matrix_region_words(reads.b, B_words); + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); bool has_nan_or_inf = false; for (uint32_t b = 0; b < BATCH; ++b) { + float *C_batch = &C_buf[b * M * N]; for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - C_buf[row * N + col] = (const_acc != ACC_FROM_VGPR) - ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]); + C_batch[row * N + col] = (const_acc != ACC_FROM_VGPR) + ? std::bit_cast(const_acc) + : std::bit_cast(C_words[out.reg * wf + out.lane]); } for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { auto al = input_loc(M, K, BATCH, row, k, b, in_bits); - A_buf[row * K + k] = std::bit_cast(a_words[al.vgpr_offset * wf + al.lane]); + A_buf[row * K + k] = std::bit_cast(A_words[al.vgpr_offset * wf + al.lane]); } for (uint32_t k = 0; k < K; ++k) for (uint32_t col = 0; col < N; ++col) { auto bl = input_loc(N, K, BATCH, col, k, b, in_bits); - B_buf[k * N + col] = std::bit_cast(b_words[bl.vgpr_offset * wf + bl.lane]); + B_buf[k * N + col] = std::bit_cast(B_words[bl.vgpr_offset * wf + bl.lane]); } for (uint32_t row = 0; row < M; ++row) for (uint32_t c0 = 0; c0 < N; c0 += W) { util::native c_row; - c_row.copy_from(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_from(&C_batch[row * N + c0], util::stdx::vector_aligned); for (uint32_t k = 0; k < K; ++k) { util::native a_bcast(A_buf[row * K + k]); util::native b_row; b_row.copy_from(&B_buf[k * N + c0], util::stdx::vector_aligned); c_row = util::stdx::fma(a_bcast, b_row, c_row); } - c_row.copy_to(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_to(&C_batch[row * N + c0], util::stdx::vector_aligned); } + } + // Publish only after every batch has consumed its inputs. + for (uint32_t b = 0; b < BATCH; ++b) for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - float fv = C_buf[row * N + col]; + float fv = C_buf[(b * M + row) * N + col]; writes.set_linear_word(out.reg * wf + out.lane, std::bit_cast(fv)); if (std::isnan(fv) || std::isinf(fv)) has_nan_or_inf = true; } - } if (has_nan_or_inf) { util::Logger::vm([&](auto &os) { os << std::format("MFMA_NAN_DETECTED (simd) dst=v{} s0=v{} s1=v{} s2=v{} {}x{}x{}_f32", dst, @@ -4145,29 +4241,32 @@ void exec_f32_mfma_f16_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, ui constexpr uint32_t W = 16; // guaranteed by the native::size()==16 guard above const uint32_t wf = cu.wf_size(); auto reads = read_mfma_fast_path_regions(cu, s0, s1, s2, M, N, K, B, in_bits, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_mfma_acc32_region(cu, dst, M, N, B, wf); alignas(64) float A_buf[M * K]; // A[row][k] (one batch block) alignas(64) float B_buf[K * N]; // B[k][col] (one batch block) - alignas(64) float C_buf[M * N]; // C[row][col] (one batch block) + static_assert(M * N * B * sizeof(float) <= 8 * 1024, + "specialized MFMA result staging exceeds the stack budget"); + alignas(64) float C_buf[M * N * B]; // C[batch][row][col] + alignas(64) uint32_t C_words[M * N * B]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // A/B occupy M*K*B and N*K*B packed f16 over their VGPRs. Bulk-convert each // whole region to f32 once with F16C (one vector op per 16 halves) instead // of branchy per-element f16_to_f32, then the hoist is a pure f32 // index-shuffle (f16 of word w lane l sub s -> flat (w*wf+l)*2+s). alignas(64) float A_f32[M * K * B]; alignas(64) float B_f32[N * K * B]; - util::f16_to_f32_block(reinterpret_cast(a_words), A_f32, M * K * B); - util::f16_to_f32_block(reinterpret_cast(b_words), B_f32, N * K * B); + convert_f16_matrix_region(reads.a, A_f32, M * K * B); + convert_f16_matrix_region(reads.b, B_f32, N * K * B); bool has_nan_or_inf = false; for (uint32_t b = 0; b < B; ++b) { + float *C_batch = &C_buf[b * M * N]; for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - C_buf[row * N + col] = (const_acc != ACC_FROM_VGPR) - ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]); + C_batch[row * N + col] = (const_acc != ACC_FROM_VGPR) + ? std::bit_cast(const_acc) + : std::bit_cast(C_words[out.reg * wf + out.lane]); } for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { @@ -4183,25 +4282,28 @@ void exec_f32_mfma_f16_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, ui for (uint32_t row = 0; row < M; ++row) for (uint32_t c0 = 0; c0 < N; c0 += W) { util::native c_row; - c_row.copy_from(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_from(&C_batch[row * N + c0], util::stdx::vector_aligned); for (uint32_t k = 0; k < K; ++k) { util::native a_bcast(A_buf[row * K + k]); util::native b_row; b_row.copy_from(&B_buf[k * N + c0], util::stdx::vector_aligned); c_row = util::stdx::fma(a_bcast, b_row, c_row); } - c_row.copy_to(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_to(&C_batch[row * N + c0], util::stdx::vector_aligned); } - // Scatter directly back to VGPRs (no Result staging vector). + } + // Publish only after every batch has consumed its inputs. This preserves + // instruction-level snapshot semantics when dst overlaps a later batch's + // source or accumulator registers. + for (uint32_t b = 0; b < B; ++b) for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - float fv = C_buf[row * N + col]; + float fv = C_buf[(b * M + row) * N + col]; writes.set_linear_word(out.reg * wf + out.lane, std::bit_cast(fv)); if (std::isnan(fv) || std::isinf(fv)) has_nan_or_inf = true; } - } if (has_nan_or_inf) { util::Logger::vm([&](auto &os) { os << std::format("MFMA_NAN_DETECTED (simd) dst=v{} s0=v{} s1=v{} s2=v{} {}x{}x{}_f16", dst, @@ -4234,27 +4336,30 @@ void exec_f32_mfma_bf16_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, u constexpr uint32_t W = 16; // guaranteed by the native::size()==16 guard above const uint32_t wf = cu.wf_size(); auto reads = read_mfma_fast_path_regions(cu, s0, s1, s2, M, N, K, B, in_bits, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_mfma_acc32_region(cu, dst, M, N, B, wf); alignas(64) float A_buf[M * K]; // A[row][k] (one batch block) alignas(64) float B_buf[K * N]; // B[k][col] (one batch block) - alignas(64) float C_buf[M * N]; // C[row][col] (one batch block) + static_assert(M * N * B * sizeof(float) <= 8 * 1024, + "specialized MFMA result staging exceeds the stack budget"); + alignas(64) float C_buf[M * N * B]; // C[batch][row][col] + alignas(64) uint32_t C_words[M * N * B]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // Bulk-convert the packed bf16 regions to f32 once (zero-extend + shift), // then the hoist is a pure f32 index-shuffle. alignas(64) float A_f32[M * K * B]; alignas(64) float B_f32[N * K * B]; - util::bf16_to_f32_block(reinterpret_cast(a_words), A_f32, M * K * B); - util::bf16_to_f32_block(reinterpret_cast(b_words), B_f32, N * K * B); + convert_bf16_matrix_region(reads.a, A_f32, M * K * B); + convert_bf16_matrix_region(reads.b, B_f32, N * K * B); bool has_nan_or_inf = false; for (uint32_t b = 0; b < B; ++b) { + float *C_batch = &C_buf[b * M * N]; for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - C_buf[row * N + col] = (const_acc != ACC_FROM_VGPR) - ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]); + C_batch[row * N + col] = (const_acc != ACC_FROM_VGPR) + ? std::bit_cast(const_acc) + : std::bit_cast(C_words[out.reg * wf + out.lane]); } for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { @@ -4270,25 +4375,26 @@ void exec_f32_mfma_bf16_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, u for (uint32_t row = 0; row < M; ++row) for (uint32_t c0 = 0; c0 < N; c0 += W) { util::native c_row; - c_row.copy_from(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_from(&C_batch[row * N + c0], util::stdx::vector_aligned); for (uint32_t k = 0; k < K; ++k) { util::native a_bcast(A_buf[row * K + k]); util::native b_row; b_row.copy_from(&B_buf[k * N + c0], util::stdx::vector_aligned); c_row = util::stdx::fma(a_bcast, b_row, c_row); } - c_row.copy_to(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_to(&C_batch[row * N + c0], util::stdx::vector_aligned); } - // Scatter directly back to VGPRs (no Result staging vector). + } + // Publish only after every batch has consumed its inputs. + for (uint32_t b = 0; b < B; ++b) for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - float fv = C_buf[row * N + col]; + float fv = C_buf[(b * M + row) * N + col]; writes.set_linear_word(out.reg * wf + out.lane, std::bit_cast(fv)); if (std::isnan(fv) || std::isinf(fv)) has_nan_or_inf = true; } - } if (has_nan_or_inf) { util::Logger::vm([&](auto &os) { os << std::format("MFMA_NAN_DETECTED (simd) dst=v{} s0=v{} s1=v{} s2=v{} {}x{}x{}_bf16", @@ -4323,26 +4429,26 @@ void exec_f32_mfma_f8_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uin constexpr uint32_t W = 16; // guaranteed by the native::size()==16 guard above const uint32_t wf = cu.wf_size(); auto reads = read_mfma_fast_path_regions(cu, s0, s1, s2, M, N, K, B, in_bits, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_mfma_acc32_region(cu, dst, M, N, B, wf); alignas(64) float A_buf[M * K]; // A[row][k] alignas(64) float B_buf[K * N]; // B[k][col] alignas(64) float C_buf[M * N]; // C[row][col] + alignas(64) uint32_t C_words[M * N]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // Bulk-convert the packed f8 regions to f32 once through the LUTs, then the // hoist is a pure f32 index-shuffle (byte of word w lane l sub s -> // (w*wf+l)*4+s). alignas(64) float A_f32[M * K]; alignas(64) float B_f32[N * K]; - f8_to_f32_block(a_words, A_f32, M * K); - f8_to_f32_block(b_words, B_f32, N * K); + convert_f8_matrix_region(reads.a, A_f32, M * K); + convert_f8_matrix_region(reads.b, B_f32, N * K); for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, 0); C_buf[row * N + col] = (const_acc != ACC_FROM_VGPR) ? std::bit_cast(const_acc) - : std::bit_cast(c_words[out.reg * wf + out.lane]); + : std::bit_cast(C_words[out.reg * wf + out.lane]); } for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { @@ -4411,28 +4517,31 @@ void exec_i32_mfma_i8_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uin constexpr uint32_t W = 16; // guaranteed by the native::size()==16 guard above const uint32_t wf = cu.wf_size(); auto reads = read_mfma_fast_path_regions(cu, s0, s1, s2, M, N, K, B, in_bits, const_acc, wf); - const uint32_t *a_words = reads.a.reg_data(); - const uint32_t *b_words = reads.b.reg_data(); - const uint32_t *c_words = reads.acc ? reads.acc->reg_data() : nullptr; auto writes = write_mfma_acc32_region(cu, dst, M, N, B, wf); // Accumulate in unsigned 32-bit (wrap is well-defined and identical mod // 2^32 to the intended signed wrap), so the SIMD path has no signed- // overflow UB. alignas(64) uint32_t A_buf[M * K]; // A[row][k] (sign-extended bits, one batch block) alignas(64) uint32_t B_buf[K * N]; // B[k][col] (sign-extended bits, one batch block) - alignas(64) uint32_t C_buf[M * N]; // C[row][col] (one batch block) + static_assert(M * N * B * sizeof(uint32_t) <= 8 * 1024, + "specialized MFMA result staging exceeds the stack budget"); + alignas(64) uint32_t C_buf[M * N * B]; // C[batch][row][col] + alignas(64) uint32_t C_words[M * N * B]; + if (reads.acc) + copy_matrix_region_words(*reads.acc, C_words); // Bulk sign-extend the packed i8 regions to int32 once, then the hoist is // a pure i32 index-shuffle (byte of word w lane l sub s -> (w*wf+l)*4+s). alignas(64) int32_t A_i32[M * K * B]; alignas(64) int32_t B_i32[N * K * B]; - util::i8_to_i32_block(reinterpret_cast(a_words), A_i32, M * K * B); - util::i8_to_i32_block(reinterpret_cast(b_words), B_i32, N * K * B); + convert_i8_matrix_region(reads.a, A_i32, M * K * B); + convert_i8_matrix_region(reads.b, B_i32, N * K * B); for (uint32_t b = 0; b < B; ++b) { + uint32_t *C_batch = &C_buf[b * M * N]; for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - C_buf[row * N + col] = - (const_acc != ACC_FROM_VGPR) ? const_acc : c_words[out.reg * wf + out.lane]; + C_batch[row * N + col] = + (const_acc != ACC_FROM_VGPR) ? const_acc : C_words[out.reg * wf + out.lane]; } for (uint32_t row = 0; row < M; ++row) for (uint32_t k = 0; k < K; ++k) { @@ -4449,22 +4558,23 @@ void exec_i32_mfma_i8_spec(auto &cu, uint32_t dst, uint32_t s0, uint32_t s1, uin for (uint32_t row = 0; row < M; ++row) for (uint32_t c0 = 0; c0 < N; c0 += W) { util::native c_row; - c_row.copy_from(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_from(&C_batch[row * N + c0], util::stdx::vector_aligned); for (uint32_t k = 0; k < K; ++k) { util::native a_bcast(A_buf[row * K + k]); util::native b_row; b_row.copy_from(&B_buf[k * N + c0], util::stdx::vector_aligned); c_row += a_bcast * b_row; } - c_row.copy_to(&C_buf[row * N + c0], util::stdx::vector_aligned); + c_row.copy_to(&C_batch[row * N + c0], util::stdx::vector_aligned); } - // Scatter directly back to VGPRs (no Result staging vector). + } + // Publish only after every batch has consumed its inputs. + for (uint32_t b = 0; b < B; ++b) for (uint32_t row = 0; row < M; ++row) for (uint32_t col = 0; col < N; ++col) { auto out = output_loc_32(M, N, row, col, b); - writes.set_linear_word(out.reg * wf + out.lane, C_buf[row * N + col]); + writes.set_linear_word(out.reg * wf + out.lane, C_buf[(b * M + row) * N + col]); } - } } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/rdna_isa_base.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/rdna_isa_base.h index c40bd2b358d7..08ccee84d729 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/rdna_isa_base.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/rdna_isa_base.h @@ -48,10 +48,13 @@ class Wavefront; /// Each per-ISA `Isa` struct adds `Decoder`, `MachineInst`, `OperandType`, and /// `StatusReg` type aliases. struct RdnaIsaBase { - static constexpr uint32_t WF_SIZE = 32; ///< Default wave size (Wave32). - static constexpr uint32_t WF_SIZE_MAX = 64; ///< Maximum wave size (Wave64 capable). - static constexpr uint32_t MAX_SGPRS_PER_WF = 106; ///< SGPRs per wavefront. - static constexpr uint32_t MAX_VGPRS_PER_WF = 256; ///< VGPRs per wavefront. + static constexpr uint32_t WF_SIZE = 32; ///< Default wave size (Wave32). + static constexpr uint32_t WF_SIZE_MAX = 64; ///< Maximum wave size (Wave64 capable). + static constexpr uint32_t MAX_WF_SLOTS = 32; ///< Maximum simulated CU wave slots. + static constexpr uint32_t MAX_SGPRS_PER_WF = 106; ///< SGPRs per wavefront. + static constexpr uint32_t MAX_VGPRS_PER_WF = 256; ///< VGPRs per wavefront. + static constexpr uint32_t MAX_ADDRESSABLE_VGPRS_PER_WF = + MAX_VGPRS_PER_WF; ///< Maximum ordinary VGPR address span. static constexpr uint32_t MAX_ACC_VGPRS_PER_WF = 0; ///< No AccVGPR file on any RDNA ISA. static constexpr bool SRAM_ECC = false; ///< RDNA does not alter D16 for ECC. static constexpr uint8_t WAITCNT_LGKMCNT_MASK = 0; ///< 0 = no monolithic S_WAITCNT. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h index 054ca48bd258..e68108635f21 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h @@ -36,8 +36,10 @@ template struct IsaTrait; /// templates depend on: /// - `WF_SIZE` — lanes per wavefront. /// - `WF_SIZE_MAX` — largest supported wavefront size. +/// - `MAX_WF_SLOTS` — maximum simulated wavefront slots per CU. /// - `MAX_SGPRS_PER_WF` — maximum scalar GPRs. /// - `MAX_VGPRS_PER_WF` — maximum vector GPRs. +/// - `MAX_ADDRESSABLE_VGPRS_PER_WF` — maximum ordinary VGPR address span. /// - `MAX_ACC_VGPRS_PER_WF` — maximum accumulator VGPRs (0 if absent). /// - `WAITCNT_LGKMCNT_MASK` — lgkmcnt field mask in S_WAITCNT (0 if no /// monolithic S_WAITCNT — RDNA4 only). @@ -49,8 +51,10 @@ template concept GpuIsa = requires { { Isa::WF_SIZE } -> std::convertible_to; { Isa::WF_SIZE_MAX } -> std::convertible_to; + { Isa::MAX_WF_SLOTS } -> std::convertible_to; { Isa::MAX_SGPRS_PER_WF } -> std::convertible_to; { Isa::MAX_VGPRS_PER_WF } -> std::convertible_to; + { Isa::MAX_ADDRESSABLE_VGPRS_PER_WF } -> std::convertible_to; { Isa::MAX_ACC_VGPRS_PER_WF } -> std::convertible_to; { Isa::WAITCNT_LGKMCNT_MASK } -> std::convertible_to; { Isa::MODE_HAS_GPR_IDX_EN } -> std::convertible_to; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp index 9dac900253ce..aa90a06215df 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp @@ -22,13 +22,35 @@ #include #include -#include +#include #include #include namespace rocjitsu { namespace amdgpu { +template void validate_compute_unit_config(const ComputeUnitCore::Config &config) { + using Limits = IsaExecComputeUnit; + + if (config.num_wf_slots > Isa::MAX_WF_SLOTS) { + throw util::ConfigError("num_wf_slots exceeds the ISA maximum of " + + std::to_string(Isa::MAX_WF_SLOTS)); + } + + const uint32_t vgprs_per_block = + std::max(config.vgprs_per_wf, Limits::MAX_ACCVGPR_PHYSICAL_LIMIT); + if (vgprs_per_block > Limits::MAX_VGPRS_PER_BLOCK) { + throw util::ConfigError("effective VGPRs per wavefront exceeds the ISA maximum of " + + std::to_string(Limits::MAX_VGPRS_PER_BLOCK)); + } + + const uint64_t vgpr_file_registers = static_cast(config.num_wf_slots) * vgprs_per_block; + if (vgpr_file_registers > std::numeric_limits::max() || + vgpr_file_registers > Limits::MAX_VGPR_FILE_REGISTERS) { + throw util::ConfigError("configured VGPR file exceeds the ISA maximum capacity"); + } +} + ComputeUnitCore::ComputeUnitCore(std::string name, const Config &config, GpuMemory *memory, L2Cache *l2, uint32_t wf_size) : simdojo::CompositeComponent(std::move(name)), config_(config), memory_(memory), @@ -63,6 +85,7 @@ std::unique_ptr ComputeUnitCore::create(std::string name, const // Helper: instantiate the ISA-specific CU for the given execution mode. #define ROCJITSU_CU_CASE(ARCH_ENUM, ISA_TYPE) \ case ARCH_ENUM: \ + validate_compute_unit_config(config); \ switch (exec_mode) { \ case simdojo::ExecMode::FUNCTIONAL: \ return std::make_unique>( \ @@ -131,12 +154,6 @@ Wavefront *ComputeUnitCore::dispatch_wf_at(uint32_t wf_id, uint32_t wg_id, uint6 return nullptr; } - // Zero the allocated register blocks so reused slots don't inherit stale - // values from previous kernel runs. - std::fill(&sgpr_file_[sgpr_base], &sgpr_file_[sgpr_base] + config_.sgprs_per_wf, 0u); - std::memset(raw_vgpr_data(static_cast(vgpr_base)), 0, - vgpr_allocation_block_size() * wf_size_ * sizeof(uint32_t)); - // Invalidate the L1 scalar cache so this wavefront reads fresh kernel // arguments from L2/memory rather than stale lines from a prior kernel. // On real hardware, the driver issues s_dcache_inv at kernel launch. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h index 274a6bdf23b6..1fd558942e52 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h @@ -35,10 +35,13 @@ #include #include #include +#include #include #include #include +#include #include +#include #include #include #include @@ -484,25 +487,60 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// @returns Pointer to the contiguous SGPR data. const uint32_t *sgpr_data(uint32_t base) const { return &sgpr_file_[base]; } - /// @brief Return a raw pointer to a wavefront's VGPR data in the physical file. + /// @brief Return a raw pointer to one VGPR in the physical file. /// @details This bypasses plugin read hooks and should not be used directly /// by instruction emulators. It is reserved for RegisterAccess, VM storage /// code, serialization/checkpointing, diagnostics, and tightly controlled /// internals that have a separate observation contract. - /// @param base Base register index in the VGPR file. - /// @returns Const pointer to the raw VGPR data. + /// The returned pointer spans exactly one register's lanes, not a contiguous + /// multi-register region. For software-lazy storage, an unmaterialized + /// register may return shared immutable zero backing. Treat the result as an + /// ephemeral value observation: it is not a persistent storage identity and + /// need not observe a later write through another handle. + /// @param base Register index in the VGPR file. + /// @returns Const pointer to one register's raw lane data. virtual const uint8_t *raw_vgpr_data(uint32_t base) const = 0; - /// @brief Return a mutable raw pointer to a wavefront's VGPR data. + /// @brief Return a mutable raw pointer to one VGPR. /// @details This bypasses the instruction-facing RegisterAccess boundary. /// It is intended for VM storage operations such as memory completion, /// checkpoint restore, RegisterAccess view implementation, and other /// tightly controlled internals. Instruction emulators should use Operand or - /// RegisterAccess write APIs instead. - /// @param base Base register index in the VGPR file. - /// @returns Mutable pointer to the raw VGPR data. + /// RegisterAccess write APIs instead. The returned pointer spans exactly one + /// register's lanes and remains stable until the owning wave retires. + /// @param base Register index in the VGPR file. + /// @returns Mutable pointer to one register's raw lane data. virtual uint8_t *raw_vgpr_data(uint32_t base) = 0; + /// @brief Visit a logical physical-VGPR range in register order. + /// @details Each callback span contains exactly one register's lanes. Backing + /// storage boundaries are not observable through this interface. + template + void for_each_raw_vgpr(uint32_t base, uint32_t count, Function &&function) const { + using FunctionType = std::remove_reference_t; + static_assert(std::is_object_v, "VGPR visitors must be callable objects"); + static_assert(std::is_invocable_v>, + "VGPR visitor must accept a const lane span"); + for_each_raw_vgpr_impl(base, count, &function, + [](const void *context, std::span lanes) { + if constexpr (std::is_const_v) { + (*static_cast(context))(lanes); + } else { + (*static_cast(const_cast(context)))(lanes); + } + }); + } + + /// @brief Copy raw bytes from a logical physical-VGPR range. + virtual void copy_raw_vgprs_to(uint32_t base, uint32_t count, + std::span destination) const = 0; + + /// @brief Restore raw bytes into a logically zero physical-VGPR range. + /// @details Zero source runs remain unmaterialized, so this is a full restore + /// only when every destination byte is initially zero. + virtual void restore_raw_vgprs_into_zeroed_storage(uint32_t base, uint32_t count, + std::span source) = 0; + /// @brief Read a VGPR lane directly from physical storage. /// @details This deliberately bypasses plugin observation and is reserved /// for VM storage operations. Instruction code receives @@ -574,6 +612,10 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// @brief Count the number of free VGPR allocation blocks. virtual uint32_t free_vgpr_blocks() const = 0; + using RawVgprVisitor = void (*)(const void *, std::span); + virtual void for_each_raw_vgpr_impl(uint32_t base, uint32_t count, const void *context, + RawVgprVisitor visitor) const = 0; + /// @brief Update wavefront states (WAITCNT, BARRIER, ENDING transitions). void update_wf_states(); @@ -754,6 +796,14 @@ template class IsaExecComputeUnit : public ExecComputeUnit { public: using Vgpr = simdojo::VectorReg; + static constexpr uint32_t MAX_ACCVGPR_PHYSICAL_LIMIT = + Isa::MAX_ACC_VGPRS_PER_WF == 0 ? 0 : ACC_VGPR_OFFSET + Isa::MAX_ACC_VGPRS_PER_WF; + static constexpr uint32_t MAX_VGPRS_PER_BLOCK = + std::max(Isa::MAX_ADDRESSABLE_VGPRS_PER_WF, MAX_ACCVGPR_PHYSICAL_LIMIT); + static constexpr size_t MAX_VGPR_FILE_REGISTERS = + static_cast(Isa::MAX_WF_SLOTS) * MAX_VGPRS_PER_BLOCK; + using VgprFile = simdojo::RegisterFile; /// @brief Construct an ISA-parameterized compute unit. /// @param name Human-readable name (e.g., "cu0"). @@ -807,23 +857,33 @@ class IsaExecComputeUnit : public ExecComputeUnit { vgpr_file_[reg_idx][lane] = val; } - /// @returns Const pointer to the raw VGPR data. + /// @returns Const pointer to one VGPR's raw lane data. const uint8_t *raw_vgpr_data(uint32_t base) const override { return reinterpret_cast(&vgpr_file_[base]); } - /// @returns Mutable pointer to the raw VGPR data. + /// @returns Mutable pointer to one VGPR's raw lane data. uint8_t *raw_vgpr_data(uint32_t base) override { return reinterpret_cast(&vgpr_file_[base]); } + void copy_raw_vgprs_to(uint32_t base, uint32_t count, + std::span destination) const override { + vgpr_file_.copy_to(base, count, destination); + } + + void restore_raw_vgprs_into_zeroed_storage(uint32_t base, uint32_t count, + std::span source) override { + vgpr_file_.copy_nonzero_from(base, count, source); + } + /// @brief Return the VGPR register file (typed, only on concrete CU). /// @returns Const reference to the VGPR register file. - const simdojo::RegisterFile &vgpr_file() const { return vgpr_file_; } + const VgprFile &vgpr_file() const { return vgpr_file_; } /// @brief Return a mutable reference to the VGPR register file. /// @returns Mutable reference to the VGPR register file. - simdojo::RegisterFile &vgpr_file() { return vgpr_file_; } + VgprFile &vgpr_file() { return vgpr_file_; } protected: /// @returns Base index of the allocated VGPR block, or -1 on failure. @@ -834,6 +894,16 @@ class IsaExecComputeUnit : public ExecComputeUnit { uint32_t free_vgpr_blocks() const override { return vgpr_file_.free_block_count(); } + void for_each_raw_vgpr_impl(uint32_t base, uint32_t count, const void *context, + ComputeUnitCore::RawVgprVisitor visitor) const override { + static_assert(sizeof(Vgpr) == Isa::WF_SIZE * sizeof(uint32_t), + "VectorReg must be layout-compatible with raw lane storage"); + vgpr_file_.for_each(base, count, [&](const Vgpr ®) { + visitor(context, + {reinterpret_cast(®), static_cast(Isa::WF_SIZE)}); + }); + } + public: uint32_t vgpr_allocation_block_size() const override { return vgprs_per_block_; } @@ -847,7 +917,7 @@ class IsaExecComputeUnit : public ExecComputeUnit { } private: - simdojo::RegisterFile vgpr_file_{"vgpr"}; + VgprFile vgpr_file_{"vgpr"}; std::vector vgpr_to_wave_; ///< Physical VGPR → owning wavefront. uint32_t vgprs_per_block_ = 0; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/register_access.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/register_access.h index ec01be44a21f..035825d77a83 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/register_access.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/register_access.h @@ -39,6 +39,7 @@ #include #include #include +#include namespace rocjitsu::amdgpu { @@ -652,20 +653,30 @@ class RegisterAccess { [[nodiscard]] uint32_t wf_size() const { return wf_size_; } [[nodiscard]] bool empty() const { return cu_ == nullptr || reg_count_ == 0; } - [[nodiscard]] std::span lanes(uint32_t relative_reg = 0) const { + /// @brief Visit each logical VGPR as one lane span, in register order. + template void for_each(Function &&function) const { assert(cu_ && "VgprReadRegion is empty"); - assert(relative_reg < reg_count_ && "relative VGPR outside read region"); if (byte_mask_ != rocjitsu::ExecutionPlugin::kFullByteMask) throw std::logic_error("partial-byte VgprReadRegion does not expose raw lane spans"); - return {reg_data(relative_reg), wf_size_}; + cu_->for_each_raw_vgpr(base_, reg_count_, std::forward(function)); + } + + /// @brief Gather physical-layout words from this logical VGPR range. + void copy_to(std::span destination) const { + assert(cu_ && "VgprReadRegion is empty"); + assert(destination.size() <= static_cast(reg_count_) * wf_size_ && + "destination exceeds read region"); + if (byte_mask_ != rocjitsu::ExecutionPlugin::kFullByteMask) + throw std::logic_error("partial-byte VgprReadRegion cannot copy raw words"); + cu_->copy_raw_vgprs_to(base_, reg_count_, std::as_writable_bytes(destination)); } - [[nodiscard]] const uint32_t *reg_data(uint32_t relative_reg = 0) const { + [[nodiscard]] std::span lanes(uint32_t relative_reg = 0) const { assert(cu_ && "VgprReadRegion is empty"); assert(relative_reg < reg_count_ && "relative VGPR outside read region"); if (byte_mask_ != rocjitsu::ExecutionPlugin::kFullByteMask) - throw std::logic_error("partial-byte VgprReadRegion does not expose raw register data"); - return reinterpret_cast(cu_->raw_vgpr_data(base_ + relative_reg)); + throw std::logic_error("partial-byte VgprReadRegion does not expose raw lane spans"); + return {reg_data(relative_reg), wf_size_}; } [[nodiscard]] uint32_t lane(uint32_t relative_reg, uint32_t lane) const { @@ -686,6 +697,22 @@ class RegisterAccess { private: friend class RegisterAccess; + /// @brief Return the lane storage for one VGPR in this region. + /// @details The returned pointer spans exactly @c wf_size() lanes. Adjacent + /// VGPRs are not required to have contiguous backing, and this pointer must + /// not be incremented to traverse adjacent registers. For an unmaterialized + /// register, the pointer may refer to shared immutable zero backing: treat + /// it as an ephemeral value snapshot that need not observe a later write + /// through another handle. Pointers must not be retained after the owning + /// wavefront retires. + [[nodiscard]] const uint32_t *reg_data(uint32_t relative_reg) const { + assert(cu_ && "VgprReadRegion is empty"); + assert(relative_reg < reg_count_ && "relative VGPR outside read region"); + if (byte_mask_ != rocjitsu::ExecutionPlugin::kFullByteMask) + throw std::logic_error("partial-byte VgprReadRegion does not expose raw register data"); + return reinterpret_cast(cu_->raw_vgpr_data(base_ + relative_reg)); + } + VgprReadRegion(const ComputeUnitCore &cu, uint32_t base, uint32_t reg_count, uint8_t byte_mask) : cu_(&cu), base_(base), reg_count_(reg_count), wf_size_(cu.wf_size()), byte_mask_(byte_mask) {} diff --git a/emulation/rocjitsu/lib/simdojo/include/simdojo/components/register_file.h b/emulation/rocjitsu/lib/simdojo/include/simdojo/components/register_file.h index 59928b1d0a45..ebac76ce5f8c 100644 --- a/emulation/rocjitsu/lib/simdojo/include/simdojo/components/register_file.h +++ b/emulation/rocjitsu/lib/simdojo/include/simdojo/components/register_file.h @@ -8,24 +8,304 @@ #define SIMDOJO_COMPONENTS_REGISTER_FILE_H_ #include "simdojo/sim/component.h" - +#include +#include #include +#include #include +#include +#include +#include +#include #include +#include #include #include namespace simdojo { +/// @brief Backing-store layout for a physical register file. +enum class RegisterFileStorage { + CONTIGUOUS, ///< Contiguous storage used by the small scalar register file. + SOFTWARE_LAZY, ///< Portable chunk storage allocated on first mutable access. +}; + +namespace detail { + +template class ContiguousRegisterStorage { +public: + void init(uint32_t count) { data_.assign(count, RegType{}); } + + void reset(uint32_t base, uint32_t count) { + std::fill(data_.begin() + base, data_.begin() + base + count, RegType{}); + } + + RegType &operator[](uint32_t idx) { return data_[idx]; } + const RegType &operator[](uint32_t idx) const { return data_[idx]; } + + template void for_each(uint32_t base, uint32_t count, Function &&function) { + for (uint32_t idx = base; idx < base + count; ++idx) + function(data_[idx]); + } + + template + void for_each(uint32_t base, uint32_t count, Function &&function) const { + for (uint32_t idx = base; idx < base + count; ++idx) + function(data_[idx]); + } + + void copy_to(uint32_t base, std::span destination) const { + if (destination.empty()) + return; + std::memcpy(destination.data(), reinterpret_cast(data_.data() + base), + destination.size()); + } + + void copy_from(uint32_t base, std::span source) { + if (source.empty()) + return; + std::memcpy(reinterpret_cast(data_.data() + base), source.data(), source.size()); + } + + void copy_nonzero_from(uint32_t base, std::span source) { + copy_from(base, source); + } + + RegType *data() { return data_.data(); } + const RegType *data() const { return data_.data(); } + +private: + std::vector data_; +}; + +/// @brief Portable sparse register storage allocated in fixed-size chunks. +/// +/// Const access to an absent chunk observes immutable zero storage without +/// allocating. Mutable access materializes and zero-initializes the containing +/// chunk. The storage retains CU-global register indices but deliberately does +/// not expose a single contiguous pointer spanning multiple chunks. +template class SoftwareLazyRegisterStorage { +public: + static_assert(MaxRegisters > 0); + static_assert(std::is_trivially_copyable_v); + static_assert(std::is_trivially_destructible_v); + + SoftwareLazyRegisterStorage() = default; + SoftwareLazyRegisterStorage(const SoftwareLazyRegisterStorage &) = delete; + SoftwareLazyRegisterStorage &operator=(const SoftwareLazyRegisterStorage &) = delete; + SoftwareLazyRegisterStorage(SoftwareLazyRegisterStorage &&) = delete; + SoftwareLazyRegisterStorage &operator=(SoftwareLazyRegisterStorage &&) = delete; + + void init(uint32_t count) { + assert(total_regs_ == 0 && "SoftwareLazyRegisterStorage already initialized"); + assert(count <= MaxRegisters && "register count exceeds lazy storage capacity"); + if (count > MaxRegisters) + std::abort(); + total_regs_ = count; + } + + void reset(uint32_t base, uint32_t count) { + assert(base <= total_regs_ && count <= total_regs_ - base && "range exceeds storage"); + if (count == 0) + return; + + const size_t first_chunk = base / REGS_PER_CHUNK; + const size_t last_chunk = (static_cast(base) + count - 1) / REGS_PER_CHUNK; + const size_t range_end = static_cast(base) + count; + for (size_t chunk_idx = first_chunk; chunk_idx <= last_chunk; ++chunk_idx) { + auto &chunk = chunks_[chunk_idx]; + if (!chunk) + continue; + + const size_t chunk_base = chunk_idx * REGS_PER_CHUNK; + const size_t valid_chunk_end = + std::min(chunk_base + REGS_PER_CHUNK, static_cast(total_regs_)); + const size_t clear_begin = std::max(static_cast(base), chunk_base); + const size_t clear_end = std::min(range_end, valid_chunk_end); + if (clear_begin == chunk_base && clear_end == valid_chunk_end) { + chunk.reset(); + } else { + std::fill(chunk->registers.begin() + static_cast(clear_begin - chunk_base), + chunk->registers.begin() + static_cast(clear_end - chunk_base), + RegType{}); + } + } + } + + [[nodiscard]] static constexpr bool can_reclaim_independently(uint32_t count) noexcept { + return count % REGS_PER_CHUNK == 0; + } + + [[nodiscard]] static constexpr uint32_t registers_per_chunk() noexcept { return REGS_PER_CHUNK; } + + /// @brief Count chunks with materialized register storage. + /// @returns Number of currently materialized chunks. + [[nodiscard]] size_t materialized_chunk_count() const noexcept { + return static_cast(std::count_if(chunks_.begin(), chunks_.end(), + [](const auto &chunk) { return chunk != nullptr; })); + } + + RegType &operator[](uint32_t idx) { + assert(idx < total_regs_); + auto &chunk = chunks_[idx / REGS_PER_CHUNK]; + if (!chunk) + chunk = std::make_unique(); + return chunk->registers[idx % REGS_PER_CHUNK]; + } + + const RegType &operator[](uint32_t idx) const { + assert(idx < total_regs_); + const auto &chunk = chunks_[idx / REGS_PER_CHUNK]; + if (!chunk) + return zero_register_; + return chunk->registers[idx % REGS_PER_CHUNK]; + } + + template void for_each(uint32_t base, uint32_t count, Function &&function) { + size_t local_idx = base % REGS_PER_CHUNK; + size_t chunk_idx = base / REGS_PER_CHUNK; + while (count != 0) { + const size_t chunk_count = std::min(REGS_PER_CHUNK - local_idx, count); + const size_t chunk_end = local_idx + chunk_count; + + auto &chunk = chunks_[chunk_idx]; + if (!chunk) + chunk = std::make_unique(); + + for (; local_idx < chunk_end; ++local_idx) + function(chunk->registers[local_idx]); + count -= chunk_count; + ++chunk_idx; + local_idx = 0; + } + } + + template + void for_each(uint32_t base, uint32_t count, Function &&function) const { + size_t local_idx = base % REGS_PER_CHUNK; + size_t chunk_idx = base / REGS_PER_CHUNK; + while (count != 0) { + const size_t chunk_count = std::min(REGS_PER_CHUNK - local_idx, count); + const size_t chunk_end = local_idx + chunk_count; + + const auto &chunk = chunks_[chunk_idx]; + if (chunk) { + for (; local_idx < chunk_end; ++local_idx) + function(chunk->registers[local_idx]); + } else { + for (; local_idx < chunk_end; ++local_idx) + function(zero_register_); + } + count -= chunk_count; + ++chunk_idx; + local_idx = 0; + } + } + + void copy_to(uint32_t base, std::span destination) const { + visit_byte_runs( + base, destination.size(), + [&](size_t chunk_idx, size_t chunk_offset, size_t run_size, size_t destination_offset) { + const auto &chunk = chunks_[chunk_idx]; + if (!chunk) { + std::memset(destination.data() + destination_offset, 0, run_size); + return; + } + const auto *source = reinterpret_cast(chunk->registers.data()); + std::memcpy(destination.data() + destination_offset, source + chunk_offset, run_size); + }); + } + + void copy_from(uint32_t base, std::span source) { + visit_byte_runs( + base, source.size(), + [&](size_t chunk_idx, size_t chunk_offset, size_t run_size, size_t source_offset) { + auto &chunk = chunks_[chunk_idx]; + if (!chunk) + chunk = std::make_unique(); + auto *destination = reinterpret_cast(chunk->registers.data()); + std::memcpy(destination + chunk_offset, source.data() + source_offset, run_size); + }); + } + + /// Copy into storage known to be logically zero, preserving absent chunks for + /// source runs that contain only zero bytes. + void copy_nonzero_from(uint32_t base, std::span source) { + visit_byte_runs( + base, source.size(), + [&](size_t chunk_idx, size_t chunk_offset, size_t run_size, size_t source_offset) { + const auto run = source.subspan(source_offset, run_size); + if (std::all_of(run.begin(), run.end(), + [](std::byte value) { return value == std::byte{}; })) + return; + auto &chunk = chunks_[chunk_idx]; + if (!chunk) + chunk = std::make_unique(); + auto *destination = reinterpret_cast(chunk->registers.data()); + std::memcpy(destination + chunk_offset, run.data(), run.size()); + }); + } + +private: + static constexpr size_t TARGET_CHUNK_BYTES = 4096; + static constexpr uint32_t REGS_PER_CHUNK = + static_cast(std::max(1, TARGET_CHUNK_BYTES / sizeof(RegType))); + static constexpr size_t MAX_CHUNKS = (MaxRegisters + REGS_PER_CHUNK - 1) / REGS_PER_CHUNK; + + struct Chunk { + std::array registers{}; + }; + + template + static void visit_byte_runs(uint32_t base, size_t byte_count, Function &&function) { + constexpr size_t CHUNK_BYTES = REGS_PER_CHUNK * sizeof(RegType); + size_t storage_offset = static_cast(base) * sizeof(RegType); + size_t range_offset = 0; + while (range_offset < byte_count) { + const size_t chunk_idx = storage_offset / CHUNK_BYTES; + const size_t chunk_offset = storage_offset % CHUNK_BYTES; + const size_t run_size = std::min(byte_count - range_offset, CHUNK_BYTES - chunk_offset); + function(chunk_idx, chunk_offset, run_size, range_offset); + storage_offset += run_size; + range_offset += run_size; + } + } + + inline static const RegType zero_register_{}; + std::array, MAX_CHUNKS> chunks_{}; + uint32_t total_regs_ = 0; +}; + +template +using RegisterStorage = std::conditional_t, + SoftwareLazyRegisterStorage>; + +} // namespace detail + /// @brief Physical register file with block-granularity allocation tracking. /// /// @details Templated on the register type: use uint32_t for scalar files or /// VectorReg for vector files. The file is divided into /// fixed-size blocks (one per hardware context slot). Allocation finds a -/// free block and returns its base register index. +/// free block and returns its base register index. References and pointers are +/// allocation-scoped: callers must not read or write through them before +/// allocation or after freeing their block. Freeing a block invalidates every +/// handle into that block. With software-lazy storage, const access to an +/// unmaterialized register is an ephemeral observation of its logical zero +/// value and may use shared immutable backing. Such a handle is not a persistent +/// storage identity and need not observe a later write through a mutable handle. +/// Mutable handles, and const handles into already materialized storage, remain +/// stable until their allocation is freed. +/// A pointer or reference to one register addresses only that register and must +/// not be incremented to traverse adjacent registers. /// /// @tparam RegType Register element type (default: uint32_t). -template class RegisterFile : public Component { +/// @tparam Storage Backing-store layout (default: contiguous storage). +/// @tparam MaxRegisters Maximum logical register count for fixed-capacity storage. +template +class RegisterFile : public Component { public: explicit RegisterFile(std::string name) : Component(std::move(name)) {} @@ -36,14 +316,16 @@ template class RegisterFile : public Component { assert(total_regs_ == 0 && "RegisterFile already initialized"); total_regs_ = total_regs; regs_per_block_ = regs_per_block; - data_.assign(total_regs, RegType{}); + data_.init(total_regs); uint32_t num_blocks = (regs_per_block > 0) ? (total_regs / regs_per_block) : 0; free_blocks_.assign(num_blocks, true); + needs_reset_.assign(num_blocks, false); } /// @brief Try to allocate a contiguous block of registers. /// @param count Number of registers needed (must be <= regs_per_block). /// @returns Base register index, or -1 if no free block. + /// @post On success, every register in the returned allocation block is zero. int32_t allocate(uint32_t count) { if (count == 0 || regs_per_block_ == 0) return -1; @@ -52,8 +334,10 @@ template class RegisterFile : public Component { if (free_blocks_[i]) { free_blocks_[i] = false; uint32_t base = static_cast(i * regs_per_block_); - for (uint32_t r = base; r < base + regs_per_block_; ++r) - data_[r] = RegType{}; + if (needs_reset_[i]) { + data_.reset(base, regs_per_block_); + needs_reset_[i] = false; + } return static_cast(base); } } @@ -72,31 +356,111 @@ template class RegisterFile : public Component { return; assert(!free_blocks_[block] && "double-free of register block"); free_blocks_[block] = true; + if constexpr (Storage == RegisterFileStorage::SOFTWARE_LAZY) { + // Immediately restore the retired block's zero state and release wholly + // covered chunks. Layouts whose blocks share chunks receive one final + // whole-file reset so their boundary chunks can also be released. + const bool independently_reclaimable = data_.can_reclaim_independently(regs_per_block_); + const bool all_blocks_free = + !independently_reclaimable && std::all_of(free_blocks_.begin(), free_blocks_.end(), + [](bool is_free) { return is_free; }); + if (all_blocks_free) { + data_.reset(0, total_regs_); + } else { + data_.reset(base, regs_per_block_); + } + needs_reset_[block] = false; + } else { + needs_reset_[block] = true; + } } /// @brief Access a register by index. /// @param idx Register index. + /// @pre The allocation block containing @p idx is currently allocated. /// @returns Mutable reference to the register. RegType &operator[](uint32_t idx) { assert(idx < total_regs_); + assert(is_allocated(idx) && "mutable access to a free register block"); return data_[idx]; } /// @brief Access a register by index (const). /// @param idx Register index. + /// @pre The allocation block containing @p idx is currently allocated. /// @returns Const reference to the register. const RegType &operator[](uint32_t idx) const { assert(idx < total_regs_); + assert(is_allocated(idx) && "const access to a free register block"); return data_[idx]; } + /// @brief Visit each logical register in an allocated range in index order. + template void for_each(uint32_t base, uint32_t count, Function &&function) { + assert_allocated_range(base, count); + data_.for_each(base, count, std::forward(function)); + } + + /// @brief Visit each logical register in an allocated range in index order. + template + void for_each(uint32_t base, uint32_t count, Function &&function) const { + assert_allocated_range(base, count); + data_.for_each(base, count, std::forward(function)); + } + + /// @brief Copy bytes from an allocated logical register range. + /// @details The destination may end within the final register. + void copy_to(uint32_t base, uint32_t count, std::span destination) const + requires std::is_trivially_copyable_v + { + assert_allocated_range(base, count); + assert(destination.size() <= static_cast(count) * sizeof(RegType)); + data_.copy_to(base, destination); + } + + /// @brief Copy bytes into an allocated logical register range. + /// @details The source may end within the final register. + void copy_from(uint32_t base, uint32_t count, std::span source) + requires std::is_trivially_copyable_v + { + assert_allocated_range(base, count); + assert(source.size() <= static_cast(count) * sizeof(RegType)); + data_.copy_from(base, source); + } + + /// @brief Copy nonzero source runs into a logically zero allocated range. + /// @details This preserves sparse backing when restoring zero-heavy state. + void copy_nonzero_from(uint32_t base, uint32_t count, std::span source) + requires std::is_trivially_copyable_v + { + assert_allocated_range(base, count); + assert(source.size() <= static_cast(count) * sizeof(RegType)); + data_.copy_nonzero_from(base, source); + } + /// @brief Return a pointer to the underlying register storage. + /// @pre Callers may dereference the returned pointer only within currently + /// allocated blocks and must stop accessing each block when it is freed. /// @returns Mutable pointer to the first register. - RegType *data() { return data_.data(); } + RegType *data() + requires requires(detail::RegisterStorage &storage) { + storage.data(); + } + { + return data_.data(); + } /// @brief Return a pointer to the underlying register storage (const). + /// @pre Callers may dereference the returned pointer only within currently + /// allocated blocks and must stop accessing each block when it is freed. /// @returns Const pointer to the first register. - const RegType *data() const { return data_.data(); } + const RegType *data() const + requires requires(const detail::RegisterStorage &storage) { + storage.data(); + } + { + return data_.data(); + } /// @brief Return the total number of registers. /// @returns Total register count. @@ -116,11 +480,41 @@ template class RegisterFile : public Component { return count; } + /// @brief Count chunks with materialized backing storage. + /// @returns Number of currently materialized chunks. + [[nodiscard]] size_t materialized_chunk_count() const + requires requires(const detail::RegisterStorage &storage) { + storage.materialized_chunk_count(); + } + { + return data_.materialized_chunk_count(); + } + private: - std::vector data_; ///< One RegType per register. - uint32_t total_regs_ = 0; ///< Total registers. - uint32_t regs_per_block_ = 0; ///< Registers per block. + void assert_allocated_range(uint32_t base, uint32_t count) const { + assert(base <= total_regs_ && count <= total_regs_ - base && "range exceeds register file"); + if (count == 0) + return; + assert(regs_per_block_ != 0); + const size_t first_block = base / regs_per_block_; + const size_t last_block = (static_cast(base) + count - 1) / regs_per_block_; + for (size_t block = first_block; block <= last_block; ++block) + assert(block < free_blocks_.size() && !free_blocks_[block] && + "range includes a free register block"); + } + + bool is_allocated(uint32_t idx) const { + if (regs_per_block_ == 0) + return false; + const size_t block = idx / regs_per_block_; + return block < free_blocks_.size() && !free_blocks_[block]; + } + + detail::RegisterStorage data_; ///< Register backing storage. + uint32_t total_regs_ = 0; ///< Total registers. + uint32_t regs_per_block_ = 0; ///< Registers per block. std::vector free_blocks_; ///< One bit per block (true = free). + std::vector needs_reset_; ///< Blocks dirtied by prior allocation. }; } // namespace simdojo diff --git a/emulation/rocjitsu/tests/CMakeLists.txt b/emulation/rocjitsu/tests/CMakeLists.txt index 59c431a4446b..92fc48e70613 100644 --- a/emulation/rocjitsu/tests/CMakeLists.txt +++ b/emulation/rocjitsu/tests/CMakeLists.txt @@ -450,6 +450,9 @@ add_executable( kfd_ioctl_test.cpp waitcnt_counter_test.cpp register_access_test.cpp + register_file_test.cpp + simd_correctness/mfma_lazy_storage_test.cpp + vgpr_redispatch_test.cpp instruction_execution_harness_test.cpp isa_target_registry_test.cpp pseudo_scalar_exec_test.cpp diff --git a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp index 92b7055af7bc..c773c96e4c4d 100644 --- a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp +++ b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp @@ -21,6 +21,7 @@ #include "rocjitsu/vm/soc.h" #include "simdojo/sim/simulation.h" +#include "util/except.h" #include "rocjitsu/base/rj_compiler.h" RJ_DIAGNOSTIC_PUSH @@ -87,7 +88,7 @@ struct VmFixture { amdgpu::GpuMemory *gpu_mem = nullptr; VmFixture(std::string_view arch = "cdna3", uint32_t num_cus = 1, uint32_t num_wf_slots = 10, - uint32_t lds_size_kb = 64, uint32_t sgprs_per_wf = 104) { + uint32_t lds_size_kb = 64, uint32_t sgprs_per_wf = 104, uint32_t vgprs_per_wf = 256) { std::string cu_range = "cu[0:" + std::to_string(num_cus) + "]"; std::string links; for (uint32_t i = 0; i < num_cus; ++i) { @@ -116,7 +117,9 @@ struct VmFixture { R"({"key":"sgprs_per_wf","value":")" + std::to_string(sgprs_per_wf) + R"("},)" - R"({"key":"vgprs_per_wf","value":"256"},)" + R"({"key":"vgprs_per_wf","value":")" + + std::to_string(vgprs_per_wf) + + R"("},)" R"({"key":"lds_size_kb","value":")" + std::to_string(lds_size_kb) + R"("})" @@ -184,6 +187,14 @@ struct VmFixture { } }; +TEST(ComputeUnitConfigTest, RejectsWavefrontSlotsAboveIsaMaximum) { + EXPECT_THROW((void)VmFixture("cdna3", 1, 33), util::ConfigError); +} + +TEST(ComputeUnitConfigTest, RejectsVgprSpanAboveIsaMaximum) { + EXPECT_THROW((void)VmFixture("cdna3", 1, 32, 64, 104, 513), util::ConfigError); +} + // Drive the engine until the listed CUs have no resident wavefronts. A wavefront // frees itself at s_endpgm (num_wfs()/has_active_wfs() drop as it halts), so the // kernel is complete once every listed CU reports idle. Waves that need their final diff --git a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp index 33f09bfe2772..5ec5f1954f2f 100644 --- a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp @@ -54,7 +54,9 @@ std::string make_single_se_gfx1250_config(uint32_t num_cus) { R"({"name":")" + cu_range + R"(","type":"compute_unit","config":[)" - R"({"key":"num_wf_slots","value":"80"},)" + R"({"key":"num_wf_slots","value":")" + + std::to_string(kGfx1250WaveSlotsPerCu) + + R"("},)" R"({"key":"sgprs_per_wf","value":"128"},)" R"({"key":"vgprs_per_wf","value":"1024"},)" R"({"key":"lds_size_kb","value":"160"})" @@ -1459,11 +1461,10 @@ TEST(Gfx1250SimulationTest, IbSts2ClusterFieldsAreZeroForOrdinaryDispatch) { queue.dispatch(kernel_object, /*grid_size_x=*/32, /*workgroup_size_x=*/32); step_until_halted(*sim.engine, *sim.cu()); - auto *wf = sim.cu()->wf(0); - ASSERT_NE(wf, nullptr); - const uint32_t sbase = wf->sgpr_alloc().base; - EXPECT_EQ(sim.cu()->read_sgpr(sbase + 2), 0u); - EXPECT_EQ(sim.cu()->read_sgpr(sbase + 3), 0u); + ASSERT_EQ(sim.snapshot->snapshots().size(), 1u); + const auto &wf = sim.snapshot->snapshots().front(); + EXPECT_EQ(wf.sgpr(2), 0u); + EXPECT_EQ(wf.sgpr(3), 0u); } TEST(Gfx1250SimulationTest, DynamicClusterLaunchStateMatchesCompilerAbiWithAlignedOffset) { diff --git a/emulation/rocjitsu/tests/config_test.cpp b/emulation/rocjitsu/tests/config_test.cpp index 8ff6b0f9fc60..0022a5a9744a 100644 --- a/emulation/rocjitsu/tests/config_test.cpp +++ b/emulation/rocjitsu/tests/config_test.cpp @@ -1052,8 +1052,13 @@ TEST(CheckpointTest, SaveAndRestoreAccVgprs) { lower_wf->halt(); const uint32_t acc0 = wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET; const uint32_t acc_last = acc0 + cdna3::Isa::MAX_ACC_VGPRS_PER_WF - 1; + const uint32_t acc_quarter = acc0 + cdna3::Isa::MAX_ACC_VGPRS_PER_WF / 4; + const uint32_t acc_midpoint = acc0 + cdna3::Isa::MAX_ACC_VGPRS_PER_WF / 2; cu->write_vgpr(acc0, 0, 0xA55A0001u); + cu->write_vgpr(acc_quarter, 63, 0xA55A003Fu); + cu->write_vgpr(acc_midpoint, 63, 0xA55A103Fu); cu->write_vgpr(acc_last, 0, 0xDEADBEEFu); + cu->write_vgpr(acc_last, 63, 0xFEEDFACEu); test::ScopedTempFile checkpoint("rocjitsu-checkpoint-"); config::save_checkpoint(checkpoint.path(), *loaded.soc(), 42, loaded.engine_config); @@ -1073,10 +1078,22 @@ TEST(CheckpointTest, SaveAndRestoreAccVgprs) { EXPECT_EQ(restored_wf->pc, 0x2000u); EXPECT_EQ(restored_cu->read_vgpr(restored_wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET, 0), 0xA55A0001u); + EXPECT_EQ(restored_cu->read_vgpr(restored_wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET + + cdna3::Isa::MAX_ACC_VGPRS_PER_WF / 4, + 63), + 0xA55A003Fu); + EXPECT_EQ(restored_cu->read_vgpr(restored_wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET + + cdna3::Isa::MAX_ACC_VGPRS_PER_WF / 2, + 63), + 0xA55A103Fu); EXPECT_EQ(restored_cu->read_vgpr(restored_wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET + cdna3::Isa::MAX_ACC_VGPRS_PER_WF - 1, 0), 0xDEADBEEFu); + EXPECT_EQ(restored_cu->read_vgpr(restored_wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET + + cdna3::Isa::MAX_ACC_VGPRS_PER_WF - 1, + 63), + 0xFEEDFACEu); } TEST(CheckpointTest, SaveAndRestoreWave32ExecScratch) { @@ -1116,6 +1133,11 @@ TEST(CheckpointTest, SaveAndRestoreWave32ExecScratch) { ASSERT_NE(wf, nullptr); ASSERT_EQ(wf->wf_size(), 32u); wf->set_exec_raw(0xDEADBEEF0000000FULL); + const uint32_t vgpr_base = wf->vgpr_alloc().base; + const uint32_t vgpr_last = vgpr_base + cu->vgpr_allocation_block_size() - 1; + cu->write_vgpr(vgpr_base + 1, 31, 0x1234001Fu); + cu->write_vgpr(vgpr_base + cu->vgpr_allocation_block_size() / 2, 31, 0x5678001Fu); + cu->write_vgpr(vgpr_last, 31, 0x9ABC001Fu); test::ScopedTempFile checkpoint("rocjitsu-checkpoint-"); config::save_checkpoint(checkpoint.path(), *loaded.soc(), 42, loaded.engine_config); @@ -1127,10 +1149,19 @@ TEST(CheckpointTest, SaveAndRestoreWave32ExecScratch) { auto *restored_cp = restored_soc->xcd(0)->command_processor(); ASSERT_NE(restored_cp, nullptr); EXPECT_EQ(restored_cp->sdma_packet_dialect(), amdgpu::SdmaPacketDialect::Gfx11Plus); - auto *restored_wf = restored_soc->xcd(0)->shader_engine(0)->compute_unit(0)->wf(0); + auto *restored_cu = restored_soc->xcd(0)->shader_engine(0)->compute_unit(0); + ASSERT_NE(restored_cu, nullptr); + auto *restored_wf = restored_cu->wf(0); ASSERT_NE(restored_wf, nullptr); EXPECT_EQ(restored_wf->exec(), 0xFULL); EXPECT_EQ(restored_wf->exec_raw(), 0xDEADBEEF0000000FULL); + EXPECT_EQ(restored_cu->read_vgpr(restored_wf->vgpr_alloc().base + 1, 31), 0x1234001Fu); + EXPECT_EQ(restored_cu->read_vgpr( + restored_wf->vgpr_alloc().base + restored_cu->vgpr_allocation_block_size() / 2, 31), + 0x5678001Fu); + EXPECT_EQ(restored_cu->read_vgpr( + restored_wf->vgpr_alloc().base + restored_cu->vgpr_allocation_block_size() - 1, 31), + 0x9ABC001Fu); } TEST(CheckpointTest, SaveAndRestoreHwregState) { diff --git a/emulation/rocjitsu/tests/register_access_test.cpp b/emulation/rocjitsu/tests/register_access_test.cpp index 8bef8ff85f8e..c1bd3339c5f3 100644 --- a/emulation/rocjitsu/tests/register_access_test.cpp +++ b/emulation/rocjitsu/tests/register_access_test.cpp @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,11 @@ concept ExposesRawComputeUnit = requires(T &value) { value.raw_cu(); }; template concept ExposesRawVgprData = requires(T &value) { value.raw_vgpr_data(0); }; +template +concept ExposesReadRegionRegData = requires(const T &value) { value.reg_data(0); }; + +static_assert(!ExposesReadRegionRegData); + template concept ExposesUnobservedVgprWrite = requires(T &value) { value.write_vgpr_storage(0, 0, 0); }; @@ -261,6 +267,39 @@ TEST(RegisterAccessTest, ReadRegionObservesAllRegistersAndReturnsLaneSpans) { EXPECT_EQ(region.lanes(1)[5], 0x4444u); } +TEST(RegisterAccessTest, ReadRegionTraversesAndCopiesLogicalRegisterRange) { + for (const auto arch : {ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_GFX1250}) { + Fixture fx(arch); + ASSERT_NE(fx.wf, nullptr); + SCOPED_TRACE(arch); + + const uint32_t wf_size = fx.wf->wf_size(); + constexpr uint32_t reg_count = 64; + const uint32_t physical_base = fx.vgpr_base() + 7; + fx.cu->write_vgpr(physical_base, 3, 0x11112222u); + fx.cu->write_vgpr(physical_base + reg_count / 2, 3, 0x33334444u); + fx.cu->write_vgpr(physical_base + reg_count - 1, 3, 0x55556666u); + + RegisterAccess regs(*fx.cu); + auto region = regs.read_vgpr_region(physical_base, reg_count, + /*lane_mask=*/uint64_t{1} << 3); + + std::vector copied(static_cast(reg_count) * wf_size); + region.copy_to(copied); + EXPECT_EQ(copied[3], 0x11112222u); + EXPECT_EQ(copied[(reg_count / 2) * wf_size + 3], 0x33334444u); + EXPECT_EQ(copied[(reg_count - 1) * wf_size + 3], 0x55556666u); + + uint32_t relative_reg = 0; + const auto visitor = [&](std::span lanes) { + EXPECT_EQ(lanes[3], copied[static_cast(relative_reg) * wf_size + 3]); + ++relative_reg; + }; + region.for_each(visitor); + EXPECT_EQ(relative_reg, reg_count); + } +} + TEST(RegisterAccessTest, PartialByteReadRegionMasksReturnedValues) { Fixture fx; ASSERT_NE(fx.wf, nullptr); @@ -275,7 +314,6 @@ TEST(RegisterAccessTest, PartialByteReadRegionMasksReturnedValues) { EXPECT_EQ(fx.plugin->reads[0].byte_mask, 0b0110); EXPECT_EQ(region.lane(/*relative_reg=*/0, /*lane=*/3), 0x00BBCC00u); EXPECT_THROW((void)region.lanes(), std::logic_error); - EXPECT_THROW((void)region.reg_data(), std::logic_error); } TEST(RegisterAccessTest, WriteRegionObservesWritesAndHonorsLaneMask) { diff --git a/emulation/rocjitsu/tests/register_file_test.cpp b/emulation/rocjitsu/tests/register_file_test.cpp new file mode 100644 index 000000000000..aa7a5f98cd45 --- /dev/null +++ b/emulation/rocjitsu/tests/register_file_test.cpp @@ -0,0 +1,247 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#include "simdojo/components/register_file.h" +#include "simdojo/components/vector_reg.h" + +#include + +#include +#include +#include +#include +#include +#include + +namespace { + +using simdojo::RegisterFile; +using simdojo::RegisterFileStorage; + +constexpr size_t SOFTWARE_LAZY_TEST_CAPACITY = 4096; +template +using SoftwareLazyTestStorage = + simdojo::detail::SoftwareLazyRegisterStorage; +template +using SoftwareLazyTestFile = + RegisterFile; + +using SoftwareLazyUint32Storage = SoftwareLazyTestStorage; +static_assert(!std::is_copy_constructible_v); +static_assert(!std::is_copy_assignable_v); +static_assert(!std::is_move_constructible_v); +static_assert(!std::is_move_assignable_v); +template +concept HasContiguousData = requires(File &file) { file.data(); }; +using SoftwareLazyUint32File = SoftwareLazyTestFile; +static_assert(!HasContiguousData); + +TEST(RegisterFileTest, ContiguousStorageClearsReusedBlock) { + RegisterFile file("contiguous"); + file.init(/*total_regs=*/16, /*regs_per_block=*/8); + + ASSERT_EQ(file.allocate(4), 0); + for (uint32_t i = 0; i < 8; ++i) + file[i] = i + 1; + + file.free(0); + ASSERT_EQ(file.allocate(1), 0); + for (uint32_t i = 0; i < 8; ++i) + EXPECT_EQ(file[i], 0u) << "register " << i; +} + +TEST(RegisterFileTest, SoftwareLazyStorageMaterializesOnlyMutableChunks) { + using Vgpr = simdojo::VectorReg<64, uint32_t>; + using Storage = SoftwareLazyTestStorage; + Storage storage; + constexpr uint32_t regs_per_chunk = Storage::registers_per_chunk(); + static_assert(regs_per_chunk > 1); + storage.init(2 * regs_per_chunk); + + const Storage &const_storage = storage; + EXPECT_EQ(storage.materialized_chunk_count(), 0u); + EXPECT_EQ(const_storage[0][0], 0u); + EXPECT_EQ(const_storage[regs_per_chunk][63], 0u); + EXPECT_EQ(storage.materialized_chunk_count(), 0u); + + storage[0][0] = 0x11111111u; + storage[regs_per_chunk - 1][63] = 0x22222222u; + EXPECT_EQ(storage.materialized_chunk_count(), 1u); + storage[regs_per_chunk][0] = 0x33333333u; + EXPECT_EQ(storage.materialized_chunk_count(), 2u); + + storage.reset(regs_per_chunk / 2, regs_per_chunk); + EXPECT_EQ(storage.materialized_chunk_count(), 2u); + EXPECT_EQ(const_storage[0][0], 0x11111111u); + EXPECT_EQ(const_storage[regs_per_chunk - 1][63], 0u); + EXPECT_EQ(const_storage[regs_per_chunk][0], 0u); + + storage.reset(0, 2 * regs_per_chunk); + EXPECT_EQ(storage.materialized_chunk_count(), 0u); + EXPECT_EQ(const_storage[0][0], 0u); + EXPECT_EQ(const_storage[regs_per_chunk][0], 0u); +} + +TEST(RegisterFileTest, SoftwareLazyStorageSupportsFixedCapacityBoundary) { + using Vgpr = simdojo::VectorReg<64, uint32_t>; + using Storage = simdojo::detail::SoftwareLazyRegisterStorage; + static_assert(Storage::registers_per_chunk() == 16); + + Storage storage; + storage.init(32); + storage[31][63] = 0xA5A5A5A5u; + + const Storage &const_storage = storage; + EXPECT_EQ(const_storage[31][63], 0xA5A5A5A5u); + EXPECT_EQ(storage.materialized_chunk_count(), 1u); +} + +TEST(RegisterFileTest, SoftwareLazyStorageClearsReusedUnalignedBlock) { + using Vgpr = simdojo::VectorReg<64, uint32_t>; + using File = SoftwareLazyTestFile; + File file("software_lazy"); + file.init(/*total_regs=*/48, /*regs_per_block=*/24); + + ASSERT_EQ(file.allocate(24), 0); + ASSERT_EQ(file.allocate(24), 24); + file[0][0] = 0x11111111u; + file[23][63] = 0x22222222u; + file[24][0] = 0x33333333u; + file[47][63] = 0x44444444u; + ASSERT_EQ(file.materialized_chunk_count(), 3u); + + file.free(0); + EXPECT_EQ(file.materialized_chunk_count(), 2u); + ASSERT_EQ(file.allocate(1), 0); + const File &const_file = file; + EXPECT_EQ(const_file[0][0], 0u); + EXPECT_EQ(const_file[23][63], 0u); + EXPECT_EQ(const_file[24][0], 0x33333333u); + EXPECT_EQ(const_file[47][63], 0x44444444u); + + file.free(0); + file.free(24); + EXPECT_EQ(file.materialized_chunk_count(), 0u); + ASSERT_EQ(file.allocate(1), 0); + ASSERT_EQ(file.allocate(1), 24); + EXPECT_EQ(const_file[0][0], 0u); + EXPECT_EQ(const_file[23][63], 0u); + EXPECT_EQ(const_file[24][0], 0u); + EXPECT_EQ(const_file[47][63], 0u); + EXPECT_EQ(file.materialized_chunk_count(), 0u); +} + +TEST(RegisterFileTest, SoftwareLazyStorageReclaimsAlignedBlocksDuringChurn) { + using Vgpr = simdojo::VectorReg<64, uint32_t>; + using File = SoftwareLazyTestFile; + constexpr uint32_t regs_per_block = 512; + File file("software_lazy"); + file.init(/*total_regs=*/2 * regs_per_block, regs_per_block); + + ASSERT_EQ(file.allocate(regs_per_block), 0); + ASSERT_EQ(file.allocate(regs_per_block), static_cast(regs_per_block)); + file[0][0] = 0x11111111u; + file[regs_per_block - 1][63] = 0x22222222u; + file[regs_per_block][0] = 0x33333333u; + file[2 * regs_per_block - 1][63] = 0x44444444u; + ASSERT_EQ(file.materialized_chunk_count(), 4u); + + file.free(0); + EXPECT_EQ(file.materialized_chunk_count(), 2u); + const File &const_file = file; + EXPECT_EQ(const_file[regs_per_block][0], 0x33333333u); + EXPECT_EQ(const_file[2 * regs_per_block - 1][63], 0x44444444u); + + for (uint32_t value = 1; value <= 8; ++value) { + ASSERT_EQ(file.allocate(regs_per_block), 0); + file[regs_per_block / 2][17] = value; + ASSERT_EQ(file.materialized_chunk_count(), 3u); + file.free(0); + EXPECT_EQ(file.materialized_chunk_count(), 2u); + } + + file.free(regs_per_block); + EXPECT_EQ(file.materialized_chunk_count(), 0u); +} + +TEST(RegisterFileTest, SoftwareLazyLogicalRangeTraversalAndCopyCrossChunks) { + using Vgpr = simdojo::VectorReg<64, uint32_t>; + using Storage = SoftwareLazyTestStorage; + using File = SoftwareLazyTestFile; + constexpr uint32_t regs_per_chunk = Storage::registers_per_chunk(); + constexpr uint32_t reg_count = 2 * regs_per_chunk + 1; + File file("software_lazy"); + file.init(reg_count, reg_count); + ASSERT_EQ(file.allocate(reg_count), 0); + + const size_t byte_count = static_cast(reg_count) * sizeof(Vgpr) - 3; + std::vector source(byte_count); + for (size_t idx = 0; idx < source.size(); ++idx) + source[idx] = static_cast((idx * 37 + 11) & 0xFF); + file.copy_from(0, reg_count, source); + + std::vector copied(byte_count); + const File &const_file = file; + const_file.copy_to(0, reg_count, copied); + EXPECT_EQ(copied, source); + + uint32_t visited = 0; + const_file.for_each(0, reg_count, [&](const Vgpr ®) { + EXPECT_EQ(reg[0], file[visited][0]); + ++visited; + }); + EXPECT_EQ(visited, reg_count); +} + +TEST(RegisterFileTest, SoftwareLazySparseCopyPreservesAbsentZeroChunks) { + using Vgpr = simdojo::VectorReg<64, uint32_t>; + using Storage = SoftwareLazyTestStorage; + using File = SoftwareLazyTestFile; + constexpr uint32_t regs_per_chunk = Storage::registers_per_chunk(); + constexpr uint32_t reg_count = 3 * regs_per_chunk; + File file("software_lazy"); + file.init(reg_count, reg_count); + ASSERT_EQ(file.allocate(reg_count), 0); + + std::vector source(static_cast(reg_count) * sizeof(Vgpr)); + source[7] = std::byte{0x5A}; + source[2 * regs_per_chunk * sizeof(Vgpr) + 13] = std::byte{0xA5}; + file.copy_nonzero_from(0, reg_count, source); + EXPECT_EQ(file.materialized_chunk_count(), 2u); + + std::vector copied(source.size()); + const File &const_file = file; + const_file.copy_to(0, reg_count, copied); + EXPECT_EQ(copied, source); + + const_file.for_each(regs_per_chunk, regs_per_chunk, + [](const Vgpr ®) { EXPECT_EQ(reg[0], 0u); }); + EXPECT_EQ(file.materialized_chunk_count(), 2u); +} + +#if GTEST_HAS_DEATH_TEST && !defined(NDEBUG) +TEST(RegisterFileDeathTest, ConstAccessToFreedBlockAsserts) { + using File = SoftwareLazyTestFile; + File file("software_lazy"); + file.init(/*total_regs=*/16, /*regs_per_block=*/8); + + ASSERT_EQ(file.allocate(1), 0); + file.free(0); + const File &const_file = file; + + EXPECT_DEATH({ static_cast(const_file[0]); }, "const access to a free register block"); +} + +TEST(RegisterFileDeathTest, MutableAccessToFreedBlockAsserts) { + using File = SoftwareLazyTestFile; + File file("software_lazy"); + file.init(/*total_regs=*/16, /*regs_per_block=*/8); + + ASSERT_EQ(file.allocate(1), 0); + file.free(0); + + EXPECT_DEATH({ static_cast(file[0]); }, "mutable access to a free register block"); +} +#endif + +} // namespace diff --git a/emulation/rocjitsu/tests/simd_correctness/mfma_lazy_storage_test.cpp b/emulation/rocjitsu/tests/simd_correctness/mfma_lazy_storage_test.cpp new file mode 100644 index 000000000000..dd79d05a0918 --- /dev/null +++ b/emulation/rocjitsu/tests/simd_correctness/mfma_lazy_storage_test.cpp @@ -0,0 +1,48 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file mfma_lazy_storage_test.cpp +/// @brief Focused MFMA coverage for logical VGPR reads across lazy chunks. + +#include "mma_exact_test_support.h" +#include "simdojo/components/register_file.h" +#include "simdojo/components/vector_reg.h" + +namespace { + +using namespace rocjitsu; +using namespace mma_exact; + +constexpr uint32_t WF_SIZE = 64; +using MfmaVgpr = simdojo::VectorReg; +using MfmaLazyStorage = simdojo::detail::SoftwareLazyRegisterStorage; + +TEST(MfmaLazyStorageTest, F16SpecInputCrossesChunkBoundary) { + SKIP_IF_NO_SIMD(); + if (util::native::size() != 16) + GTEST_SKIP() << "test requires the 16-lane matrix fast path"; + + constexpr uint32_t regs_per_chunk = MfmaLazyStorage::registers_per_chunk(); + constexpr uint32_t source_a = regs_per_chunk - 1; + constexpr uint32_t source_b = 32; + constexpr uint32_t accumulator = 64; + constexpr uint32_t destination = 128; + constexpr uint32_t input_regs = 4; + static_assert(source_a / regs_per_chunk != (source_a + input_regs - 1) / regs_per_chunk); + + ExactFixture fixture(ROCJITSU_CODE_ARCH_CDNA4, WF_SIZE); + ASSERT_NE(fixture.wf, nullptr); + fixture.seed(source_a, input_regs, Fmt::F16, Mode::RandomInt, 88); + fixture.seed(source_b, input_regs, Fmt::F16, Mode::RandomInt, 99); + auto reseed_accumulator = [&] { fixture.seed(accumulator, 32, Fmt::F32, Mode::RandomInt, 111); }; + auto kernel = [&] { + amdgpu::exec_f32_mfma_f16_spec<32, 32, 16>( + *fixture.cu, fixture.vbase + destination, fixture.vbase + source_a, + fixture.vbase + source_b, fixture.vbase + accumulator, amdgpu::ACC_FROM_VGPR, 0, 0, 0); + }; + + expect_bit_exact("f16 cross-chunk input", Mode::RandomInt, fixture, reseed_accumulator, kernel, + destination, 32); +} + +} // namespace diff --git a/emulation/rocjitsu/tests/simd_correctness/mfma_simd_exact_test.cpp b/emulation/rocjitsu/tests/simd_correctness/mfma_simd_exact_test.cpp index 49a4d2b12251..86c05b0964b9 100644 --- a/emulation/rocjitsu/tests/simd_correctness/mfma_simd_exact_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/mfma_simd_exact_test.cpp @@ -27,7 +27,6 @@ using MfmaFloatSpecFn = void (*)(amdgpu::ComputeUnitCore &, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); using MfmaIntSpecFn = void (*)(amdgpu::ComputeUnitCore &, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); - struct MfmaFixture : ExactFixture { MfmaFixture() : ExactFixture(ROCJITSU_CODE_ARCH_CDNA4, WF) {} }; @@ -66,6 +65,30 @@ void run_i8(const char *label, uint32_t M, uint32_t N, uint32_t K, uint32_t B) { }); } +void expect_fixture_bit_exact(const char *label, const std::function &seed, + const std::function &kernel, uint32_t dst, + uint32_t dst_regs) { + ForceScalarGuard force_scalar_guard; + MfmaFixture scalar_fixture; + MfmaFixture simd_fixture; + ASSERT_NE(scalar_fixture.wf, nullptr); + ASSERT_NE(simd_fixture.wf, nullptr); + seed(scalar_fixture); + seed(simd_fixture); + + util::set_force_scalar_for_testing(true); + kernel(scalar_fixture); + util::set_force_scalar_for_testing(false); + kernel(simd_fixture); + + std::vector scalar = scalar_fixture.snapshot(dst, dst_regs); + std::vector simd = simd_fixture.snapshot(dst, dst_regs); + for (size_t word = 0; word < scalar.size(); ++word) + ASSERT_EQ(scalar[word], simd[word]) + << label << ": SIMD diverges from scalar at word " << word << " (scalar=0x" << std::hex + << scalar[word] << " simd=0x" << simd[word] << ")"; +} + } // namespace // --- exec_f32 generic, f16 inputs: every dispatched CDNA4 f16 shape --- @@ -186,6 +209,110 @@ TEST(MfmaSimdExact, F32Spec_AllShapes) { spec(amdgpu::exec_f32_mfma_f32_spec<16, 16, 1, 4>, "spec_f32_16x16x1x4"); } +TEST(MfmaSimdExact, F32SpecDestructiveSourceOverlap) { + SKIP_IF_NO_SIMD(); + if (util::native::size() != 16) + GTEST_SKIP() << "test requires the 16-lane matrix fast path"; + constexpr uint32_t source_b = 0; + constexpr uint32_t destination_and_source_a = 64; + constexpr uint32_t accumulator = 128; + + for (bool materialize_overlap : {false, true}) { + SCOPED_TRACE(materialize_overlap ? "materialized" : "logical zero"); + auto seed = [=](MfmaFixture &fx) { + fx.seed(source_b, 1, Fmt::F32, Mode::RandomInt, 11); + fx.seed(accumulator, 32, Fmt::F32, Mode::RandomInt, 22); + if (materialize_overlap) + fx.seed(destination_and_source_a, 1, Fmt::F32, Mode::RandomInt, 33); + }; + auto kernel = [](MfmaFixture &fx) { + amdgpu::exec_f32_mfma_f32_spec<32, 32, 1, 2>( + *fx.cu, fx.vbase + destination_and_source_a, fx.vbase + destination_and_source_a, + fx.vbase + source_b, fx.vbase + accumulator, amdgpu::ACC_FROM_VGPR, 0, 0, 0); + }; + expect_fixture_bit_exact("f32 source overlap", seed, kernel, destination_and_source_a, 32); + } +} + +TEST(MfmaSimdExact, F16SpecDestructiveAccumulatorOverlap) { + SKIP_IF_NO_SIMD(); + if (util::native::size() != 16) + GTEST_SKIP() << "test requires the 16-lane matrix fast path"; + constexpr uint32_t source_a = 0; + constexpr uint32_t source_b = 16; + constexpr uint32_t accumulator = 48; + constexpr uint32_t destination = 64; + + for (bool materialize_overlap : {false, true}) { + SCOPED_TRACE(materialize_overlap ? "materialized" : "logical zero"); + auto seed = [=](MfmaFixture &fx) { + fx.seed(source_a, 2, Fmt::F16, Mode::RandomInt, 44); + fx.seed(source_b, 2, Fmt::F16, Mode::RandomInt, 55); + fx.seed(accumulator, 16, Fmt::F32, Mode::RandomInt, 66); + if (materialize_overlap) + fx.seed(destination, 16, Fmt::F32, Mode::RandomInt, 77); + }; + auto kernel = [](MfmaFixture &fx) { + amdgpu::exec_f32_mfma_f16_spec<32, 32, 4, 2>( + *fx.cu, fx.vbase + destination, fx.vbase + source_a, fx.vbase + source_b, + fx.vbase + accumulator, amdgpu::ACC_FROM_VGPR, 0, 0, 0); + }; + expect_fixture_bit_exact("f16 accumulator overlap", seed, kernel, destination, 32); + } +} + +TEST(MfmaSimdExact, Bf16SpecDestructiveAccumulatorOverlap) { + SKIP_IF_NO_SIMD(); + if (util::native::size() != 16) + GTEST_SKIP() << "test requires the 16-lane matrix fast path"; + constexpr uint32_t source_a = 0; + constexpr uint32_t source_b = 16; + constexpr uint32_t accumulator = 48; + constexpr uint32_t destination = 64; + + for (bool materialize_overlap : {false, true}) { + SCOPED_TRACE(materialize_overlap ? "materialized" : "logical zero"); + auto seed = [=](MfmaFixture &fx) { + fx.seed(source_a, 2, Fmt::BF16, Mode::RandomInt, 122); + fx.seed(source_b, 2, Fmt::BF16, Mode::RandomInt, 133); + fx.seed(accumulator, 16, Fmt::F32, Mode::RandomInt, 144); + if (materialize_overlap) + fx.seed(destination, 16, Fmt::F32, Mode::RandomInt, 155); + }; + auto kernel = [](MfmaFixture &fx) { + amdgpu::exec_f32_mfma_bf16_spec<32, 32, 4, 2>( + *fx.cu, fx.vbase + destination, fx.vbase + source_a, fx.vbase + source_b, + fx.vbase + accumulator, amdgpu::ACC_FROM_VGPR, 0, 0, 0); + }; + expect_fixture_bit_exact("bf16 accumulator overlap", seed, kernel, destination, 32); + } +} + +TEST(MfmaSimdExact, I8SpecDestructiveSourceOverlap) { + SKIP_IF_NO_SIMD(); + if (util::native::size() != 16) + GTEST_SKIP() << "test requires the 16-lane matrix fast path"; + constexpr uint32_t source_b = 0; + constexpr uint32_t destination_and_source_a = 64; + constexpr uint32_t accumulator = 128; + + for (bool materialize_overlap : {false, true}) { + SCOPED_TRACE(materialize_overlap ? "materialized" : "logical zero"); + auto seed = [=](MfmaFixture &fx) { + fx.seed(source_b, 1, Fmt::I8, Mode::RandomInt, 166); + fx.seed(accumulator, 32, Fmt::I8, Mode::RandomInt, 177); + if (materialize_overlap) + fx.seed(destination_and_source_a, 1, Fmt::I8, Mode::RandomInt, 188); + }; + auto kernel = [](MfmaFixture &fx) { + amdgpu::exec_i32_mfma_i8_spec<32, 32, 4, 2>( + *fx.cu, fx.vbase + destination_and_source_a, fx.vbase + destination_and_source_a, + fx.vbase + source_b, fx.vbase + accumulator, amdgpu::ACC_FROM_VGPR); + }; + expect_fixture_bit_exact("i8 source overlap", seed, kernel, destination_and_source_a, 32); + } +} + // --- MX-scaled fp8/bf8 (per-32-block e8m0 scales: power-of-two, exact) --- TEST(MfmaSimdExact, F32Scaled) { SKIP_IF_NO_SIMD(); diff --git a/emulation/rocjitsu/tests/simd_correctness/mma_exact_test_support.h b/emulation/rocjitsu/tests/simd_correctness/mma_exact_test_support.h index 8ce399de18fb..3406a5720e15 100644 --- a/emulation/rocjitsu/tests/simd_correctness/mma_exact_test_support.h +++ b/emulation/rocjitsu/tests/simd_correctness/mma_exact_test_support.h @@ -2,8 +2,7 @@ // SPDX-License-Identifier: MIT /// @file mma_exact_test_support.h -/// @brief Shared fixture for the expensive MFMA/WMMA SIMD-vs-scalar bit-exact -/// suites (enabled by RJ_ENABLE_EXPENSIVE_CHECKS). +/// @brief Shared fixture for MFMA/WMMA SIMD-vs-scalar bit-exact tests. /// /// The fused-FMA SIMD path and the non-fused scalar path can only round apart /// when an intermediate K-sum actually rounds, so the random generators seed @@ -243,6 +242,20 @@ struct ExactFixture { } }; +// Restore the process force-scalar gate on every exit from an in-process A/B +// comparison, including assertion failures and exceptions. +class ForceScalarGuard { +public: + ForceScalarGuard() : original_(util::force_scalar()) {} + ~ForceScalarGuard() { util::set_force_scalar_for_testing(original_); } + + ForceScalarGuard(const ForceScalarGuard &) = delete; + ForceScalarGuard &operator=(const ForceScalarGuard &) = delete; + +private: + bool original_; +}; + // Run `kernel` forced-scalar then SIMD over identical pre-seeded state and // assert the dst window matches bit-for-bit. `reseed_acc` restores the // accumulator window between runs (the kernels write dst == acc in-place for @@ -251,6 +264,7 @@ inline void expect_bit_exact(const char *label, Mode mode, ExactFixture &fx, const std::function &reseed_acc, const std::function &kernel, uint32_t dst_off, uint32_t dst_regs) { + ForceScalarGuard force_scalar_guard; reseed_acc(); util::set_force_scalar_for_testing(true); kernel(); diff --git a/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp b/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp new file mode 100644 index 000000000000..479d43e5b1ec --- /dev/null +++ b/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp @@ -0,0 +1,87 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file vgpr_redispatch_test.cpp +/// @brief Integration coverage for VGPR storage recycling through compute units. + +#include "rocjitsu/code/rj_code.h" +#include "rocjitsu/vm/amdgpu/compute_unit.h" +#include "rocjitsu/vm/amdgpu/gpu_memory.h" +#include "rocjitsu/vm/amdgpu/l2_cache.h" +#include "rocjitsu/vm/plugins/execution_plugin_group.h" + +#include + +#include +#include + +namespace { + +using namespace rocjitsu; +using namespace rocjitsu::amdgpu; + +struct RedispatchCase { + rj_code_arch_t arch; + uint32_t wave_size; + uint32_t vgprs_per_wf; + const char *name; +}; + +class VgprRedispatchTest : public ::testing::TestWithParam {}; + +TEST_P(VgprRedispatchTest, RecycledAllocationStartsZero) { + const RedispatchCase test_case = GetParam(); + GpuMemory gpu_memory{"vgpr_redispatch_memory"}; + L2Cache l2{"vgpr_redispatch_l2"}; + + ComputeUnitCore::Config config{}; + config.arch = test_case.arch; + config.num_wf_slots = 1; + config.sgprs_per_wf = 106; + config.vgprs_per_wf = test_case.vgprs_per_wf; + config.lds_size_kb = 64; + + auto compute_unit = ComputeUnitCore::create("vgpr_redispatch_cu", config, &gpu_memory, &l2); + compute_unit->set_plugin_group(std::make_shared(PluginSinkConfig{})); + ASSERT_EQ(compute_unit->wf_size(), test_case.wave_size); + + Wavefront *first = compute_unit->dispatch_wf(/*wg_id=*/0, /*pc=*/0, /*num_sgprs=*/32, + /*num_vgprs=*/test_case.vgprs_per_wf); + ASSERT_NE(first, nullptr); + const uint32_t first_sgpr_base = first->sgpr_alloc().base; + const uint32_t first_base = first->vgpr_alloc().base; + const uint32_t block_size = compute_unit->vgpr_allocation_block_size(); + compute_unit->write_sgpr(first_sgpr_base, 0x12345678u); + compute_unit->write_sgpr(first_sgpr_base + 31, 0x9abcdef0u); + for (uint32_t reg = 0; reg < block_size; ++reg) { + for (uint32_t lane = 0; lane < test_case.wave_size; ++lane) + compute_unit->write_vgpr(first_base + reg, lane, 1u + reg * test_case.wave_size + lane); + } + + first->halt(); + ASSERT_EQ(compute_unit->num_wfs(), 0u); + + Wavefront *second = compute_unit->dispatch_wf(/*wg_id=*/1, /*pc=*/0, /*num_sgprs=*/32, + /*num_vgprs=*/test_case.vgprs_per_wf); + ASSERT_NE(second, nullptr); + ASSERT_EQ(second->sgpr_alloc().base, first_sgpr_base); + ASSERT_EQ(second->vgpr_alloc().base, first_base); + EXPECT_EQ(compute_unit->read_sgpr(first_sgpr_base), 0u); + EXPECT_EQ(compute_unit->read_sgpr(first_sgpr_base + 31), 0u); + for (uint32_t reg = 0; reg < block_size; ++reg) { + for (uint32_t lane = 0; lane < test_case.wave_size; ++lane) { + EXPECT_EQ(compute_unit->read_vgpr(first_base + reg, lane), 0u) + << "register " << reg << ", lane " << lane; + } + } + second->halt(); +} + +INSTANTIATE_TEST_SUITE_P( + WaveSizes, VgprRedispatchTest, + ::testing::Values(RedispatchCase{ROCJITSU_CODE_ARCH_RDNA4, 32, 256, "Wave32"}, + RedispatchCase{ROCJITSU_CODE_ARCH_CDNA4, 64, 256, "Wave64"}, + RedispatchCase{ROCJITSU_CODE_ARCH_GFX1250, 32, 1024, "Gfx1250"}), + [](const ::testing::TestParamInfo &info) { return info.param.name; }); + +} // namespace From 180cf00325f8467b80cc2d3f627ac24d655ef5bb Mon Sep 17 00:00:00 2001 From: James Newling Date: Tue, 18 Aug 2026 10:23:25 -0700 Subject: [PATCH 13/27] fix(rocjitsu): honor TDM tensor bounds across iterations (#9936) ## Summary This change fixes tensor-DMA bounds contracts exposed while reducing the stock gfx1250 TensileLite TDM tail failure tracked by #9935. It is independent of the VMID correction in #9775 at the source level. Both changes are needed to advance the original workload through the currently known rocJITsu model gaps. ## Related producer-side evidence - ROCm/rocm-libraries#7976 introduced TDM iterate mode and the `tdm_gfx1250.yaml` configuration lineage that exposed this gap. - ROCm/rocm-libraries#8406 contains the same affected configuration after iterate mode was enabled and reports passing FFM and B0 validation. This is file-level evidence rather than a published per-solution trace. - ROCm/rocm-libraries#9410 added iterate-mode edge cases with waves that have zero valid rows specifically to exercise descriptor bounds clamping, and reports passing FFM validation. ## Failure before this fix Iterate mode advanced the starting global address for each repeated tile, but rocJITsu continued to apply bounds using tile-local coordinates. A final row outside the tensor was therefore copied into LDS instead of being zero-filled. An active tensor extent of zero was treated as unbounded. The complete dense or gather tile could therefore be copied instead of being masked. ## Fixes ### Include iterate-mode address advancement in tensor bounds The model decomposes each advancing iteration's linear global-address increment into an absolute tensor-coordinate origin, then applies one bounds predicate to that origin plus the tile-local coordinate. This handles sub-row advances, row advances, and rank-3 plane advances through the same path. Overlapping-stride layouts are rejected only when multiple iterations actually advance the global origin; repeated-origin descriptors do not require inverse coordinate decomposition. ### Treat zero active tensor extents as empty For an active dense or gather tile dimension, tensor extent zero masks the complete dimension. Loads zero-fill the affected LDS elements and stores suppress the corresponding global writes. Optional null descriptor groups retain their architectural zero-filled value. A rank-3 tile with null D2 therefore has a zero third tensor extent: it masks the transfer without aborting execution, still completes an enabled barrier, and releases TENSORCNT normally. ### Avoid unnecessary origin decomposition Non-iterating descriptors use an all-zero origin directly. This avoids inverse stride decomposition, including accepted rank-5 layouts whose large default strides can wrap. ## Test coverage Focused decoded-instruction regressions verify: - partial final-row load zero-fill and corresponding store suppression; - active zero-length dense and gather extents; - null-D2 rank-3 load masking and store suppression; - completion-barrier arrival and TENSORCNT release for null D2; - sub-row, row, and rank-3 plane iteration origins; - rejection of advancing overlapping-stride layouts; - acceptance of repeated-origin overlapping-stride layouts; and - safe non-iterating rank-5 execution. The complete `Gfx1250ExecutionTest.TensorDma*` test set and changed-file pre-commit checks pass locally. ## Workload status This PR intentionally does not claim to fix the complete TensileLite reproducer. It removes independently testable descriptor-model discrepancies and gets the workload closer to the unresolved tail-loop semantic question. ## Issue tracking Progress toward #9935. (cherry picked from commit a659172a31d47862d750d1cae0a3907a45decc46) --- emulation/rocjitsu/README.md | 1 + emulation/rocjitsu/docs/tensor-dma.md | 192 +++++ .../isa/arch/amdgpu/shared/tensor_dma.h | 210 +++-- .../rocjitsu/tests/cdna5_tensor_dma_test.cpp | 782 +++++++++++++++++- 4 files changed, 1120 insertions(+), 65 deletions(-) create mode 100644 emulation/rocjitsu/docs/tensor-dma.md diff --git a/emulation/rocjitsu/README.md b/emulation/rocjitsu/README.md index 41c4bb150052..15971d4d50f2 100644 --- a/emulation/rocjitsu/README.md +++ b/emulation/rocjitsu/README.md @@ -133,6 +133,7 @@ See [docs/building.md](docs/building.md) for container setup with PyTorch. | [Simdojo Engine](docs/simdojo.md) | PDES simulation framework | | [DBT Design](docs/dbt-design.md) | Binary translator architecture | | [DBI Design](docs/dbi-design.md) | Binary instrumentation (in progress) | +| [CDNA5 Tensor DMA](docs/tensor-dma.md) | gfx1250 tensor descriptor, bounds, iteration, gather, and padding model | | [Codegen](docs/codegen.md) | ISA codegen pipeline and regen commands | | [ISA Target Providers](docs/isa-target-providers.md) | Static target registration and per-component subsets | diff --git a/emulation/rocjitsu/docs/tensor-dma.md b/emulation/rocjitsu/docs/tensor-dma.md new file mode 100644 index 000000000000..e687966a3bfd --- /dev/null +++ b/emulation/rocjitsu/docs/tensor-dma.md @@ -0,0 +1,192 @@ +# CDNA5 Tensor DMA model + +rocJITsu models the Tensor Data Mover (TDM) used by gfx1250/CDNA5 +`tensor_load_to_lds` and `tensor_store_from_lds` instructions. TDM moves a +rectangular tile between global memory and LDS without routing element data +through VGPRs. + +The primary architectural reference is the +[AMD CDNA5 ISA Reference Guide](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna5-instruction-set-architecture.pdf), +especially sections 10.11.1 through 10.11.6. The descriptor field layout is +also exposed by the ROCm HIP header +`hip/amd_detail/amd_gfx1250_TDM.h`. LLVM's AMDGPU +`make_dma_descriptor` lowering is the reference for descriptors produced from +MLIR. + +This document covers descriptor coordinates, bounds, iteration, gather, LDS +padding, and completion. Group 0 transfer enablement, process/VMID address +translation, and cache visibility are separate runtime contracts. + +## Descriptor coordinate system + +Tensor dimensions are numbered from the contiguous dimension outward. +Dimension zero has implicit element stride one. For an element coordinate +`c`, the global element offset is: + +```text +offset(c) = + c[0] + + c[1] * global_stride[0] + + c[2] * global_stride[1] + + c[3] * global_stride[2] + + c[4] * global_stride[3] +``` + +The byte address is: + +```text +global_base + element_size * offset(c) +``` + +The stride fields are consumed literally. A zero stride aliases coordinates; +it is not interpreted as an omitted dense stride. Logical dimension order and +increasing memory-stride order may differ, so a descriptor can represent +permuted or padded layouts. + +Normal descriptor rank is inferred from the highest active tile dimension. +Gather mode is architecturally always rank two: `tile_dim0` is the contiguous +row width, the descriptor's repurposed `tile_dim1` field is the number of +gather indices, and `tensor_dim1` is the row bound. A null descriptor group is +equivalent to a group whose SGPR values are zero; it does not remove an active +dimension established by an earlier group. + +## Tile traversal and bounds + +For a non-gather tile, rocJITsu enumerates tile coordinates with dimension zero +varying fastest. LDS receives or supplies one dense element stream. The global +address uses the descriptor strides while the LDS stream uses the tile +extents. + +The active tensor domain is: + +```text +0 <= c[dimension] < tensor_extent[dimension] +``` + +If any active tensor extent is zero, the domain is empty. This follows directly +from the ISA's positive-end bounds rule; zero is not an "unbounded" sentinel. + +For elements outside the active tensor domain: + +- a tensor load writes zero to the corresponding LDS element; and +- a tensor store suppresses the corresponding global-memory write. + +The transfer still completes normally. In particular, it retires TENSORcnt and +performs an enabled completion-barrier arrival even if every element is +masked. + +## Descriptor iteration + +Iteration is available for rank-two and rank-three normal tensors. For +iteration `i`, the descriptor advances the starting addresses by: + +```text +global element offset = i * global_increment +LDS element offset = i * lds_increment +``` + +The ISA describes iteration as repeated row-skipping transfers but does not +provide pseudocode for converting an arbitrary linear global increment back +into tensor coordinates for bounds checking. rocJITsu makes that conversion +explicit so that address generation and bounds use the same logical origin. + +For every active dimension whose extent is greater than one, rocJITsu +constructs an address-varying axis: + +```text +(logical dimension, tensor extent, element stride) +``` + +Extent-one dimensions remain active for rank and bounds but have only +coordinate zero, so their stride cannot create overlap and does not consume a +mixed-radix digit. + +The axes are sorted by increasing stride. A layout supports advancing +iteration when every axis starts at or beyond the complete occupied span of +all faster axes. Starting with an occupied span of one element: + +```text +stride[axis] >= occupied_span +occupied_span += stride[axis] * (extent[axis] - 1) +``` + +Saturating arithmetic is used for validation. This mixed-radix condition +supports ordinary dense layouts, padding between rows or planes, and axis +permutations while guaranteeing a unique greedy inverse. + +The iteration origin is decoded in decreasing-stride order: + +```text +origin[axis] = remaining / stride[axis] +remaining = remaining % stride[axis] +``` + +Bounds are then checked using: + +```text +origin[dimension] + tile_coordinate[dimension] + < tensor_extent[dimension] +``` + +rocJITsu rejects an advancing, non-empty iterating descriptor when its stride +layout does not satisfy the invertibility condition. No inverse is required +for: + +- a single iteration; +- repeated iterations with `global_increment == 0`; or +- an empty tensor domain. + +This rejection is a simulator support boundary, not an additional ISA +restriction. Non-iterating descriptors may use overlapping or zero strides +because their global addresses do not need to be inverted. + +## Gather and scatter + +Gather mode is a two-dimensional row operation. Each index selects a global +row and transfers `tile_dim0` contiguous elements: + +```text +global element offset = + contiguous_coordinate + gather_index * global_stride[0] +``` + +Rows are packed densely into LDS in index-list order. The same index list +performs the reverse scatter for `tensor_store_from_lds`. + +The ISA allows repeated and non-monotonic indices, but only guarantees correct +out-of-bounds behavior when the index list is nondecreasing. rocJITsu currently +applies deterministic per-index bounds checks even for other index orders. + +## LDS padding + +Padding applies only to memory-to-LDS loads. It inserts periodic gaps in the +dense LDS destination stream; skipped locations retain their previous values. + +For LDS-to-memory stores, the ISA specifies no de-padding operation. rocJITsu +therefore ignores `pad_enable`, `pad_interval`, and `pad_amount` and reads the +ordinary dense LDS source stream. + +## Completion and ordering + +Each tensor instruction increments TENSORcnt once for the complete descriptor, +not once per element or iteration. Tensor operations from one wave complete in +instruction order but are unordered with other memory-instruction classes. + +When `atomic_barrier_enable` is set, the LDS barrier arrival occurs after the +complete tensor operation. It is a completion effect and is not conditional on +the number of in-bounds elements. + +## Focused validation + +The `Gfx1250ExecutionTest.TensorDma*` tests in +`tests/cdna5_tensor_dma_test.cpp` cover: + +- dense, padded, iterating, and gather load/store addressing; +- sub-row, row, plane, padded, and permuted iteration origins; +- truly overlapping versus merely permuted stride layouts; +- aliased strides on extent-one dimensions; +- zero extents in every modeled transfer form; +- literal zero gather stride; +- null descriptor groups; +- out-of-bounds load zero-fill and store suppression; and +- TENSORcnt and completion-barrier retirement. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h index 89002a74da5d..07cce5b0ea6e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h @@ -10,10 +10,10 @@ #include "rocjitsu/vm/amdgpu/wavefront.h" #include "util/except.h" -#include #include #include #include +#include #include namespace rocjitsu { @@ -21,6 +21,8 @@ namespace amdgpu { namespace tensor_dma_detail { +// See docs/tensor-dma.md for the CDNA5 descriptor coordinate system, +// ISA-backed behavior, and rocJITsu's advancing-iteration support boundary. constexpr int kSgprNull = 124; constexpr uint32_t kGlobalHighBitsMask = (1u << 25) - 1u; @@ -73,6 +75,7 @@ struct TensorDmaDescriptor { uint32_t iteration_count = 1; uint32_t atomic_barrier_addr = 0; uint32_t valid_indices = 0; + uint32_t tensor_rank = 0; std::array gather_indices{}; bool gather = false; bool gather_indices_32bit = false; @@ -82,29 +85,9 @@ struct TensorDmaDescriptor { bool active() const { return count != 0; } - uint32_t rank() const { - if (gather) { - if (tensor_dims[1] != 0) - return 2; - if (tensor_dims[0] != 0 || tile_dims[0] != 0 || valid_indices != 0) - return 1; - return 0; - } - for (uint32_t i = static_cast(tile_dims.size()); i > 0; --i) { - if (tile_dims[i - 1] != 0) - return i; - } - return 0; - } + uint32_t rank() const { return tensor_rank; } }; -inline uint64_t default_stride(const TensorDmaDescriptor &desc, uint32_t stride_index) { - uint64_t stride = 1; - for (uint32_t dim = 0; dim <= stride_index; ++dim) - stride *= std::max(desc.tensor_dims[dim], 1u); - return stride; -} - inline TensorDmaDescriptor parse_descriptor(std::array d0, std::array d1, std::array d2, std::array d3) { @@ -162,10 +145,20 @@ inline TensorDmaDescriptor parse_descriptor(std::array d0, std::arr else desc.global_strides[2] = read_bits(d2, 64, 48); desc.global_strides[3] = read_bits(d3, 0, 48); - for (uint32_t i = 0; i < desc.global_strides.size(); ++i) { - if (desc.global_strides[i] == 0) - desc.global_strides[i] = default_stride(desc, i); + + if (desc.gather) { + // CDNA5 gather mode is always a 2D row gather/scatter. tensor_dim1 is the + // row bound even when its value is zero. + desc.tensor_rank = 2; + } else { + for (uint32_t dim = static_cast(desc.tile_dims.size()); dim > 0; --dim) { + if (desc.tile_dims[dim - 1] != 0) { + desc.tensor_rank = dim; + break; + } + } } + if (desc.gather) { if (desc.gather_indices_32bit) { for (uint32_t i = 0; i < 4; ++i) @@ -184,23 +177,117 @@ inline TensorDmaDescriptor parse_descriptor(std::array d0, std::arr return desc; } -inline void validate_supported_descriptor(const TensorDmaDescriptor &desc, bool store_from_lds) { +inline uint64_t saturating_add(uint64_t lhs, uint64_t rhs) { + return rhs > std::numeric_limits::max() - lhs ? std::numeric_limits::max() + : lhs + rhs; +} + +inline uint64_t saturating_multiply(uint64_t lhs, uint64_t rhs) { + return lhs != 0 && rhs > std::numeric_limits::max() / lhs + ? std::numeric_limits::max() + : lhs * rhs; +} + +struct TensorDmaAxis { + uint32_t dimension = 0; + uint32_t extent = 0; + uint64_t stride = 0; +}; + +class TensorDmaLayout { +public: + explicit TensorDmaLayout(const TensorDmaDescriptor &desc) : rank_(desc.rank()) { + for (uint32_t dim = 0; dim < rank_; ++dim) { + const uint32_t extent = desc.tensor_dims[dim]; + empty_ |= extent == 0; + if (extent > 1) { + axes_[axis_count_++] = {.dimension = dim, + .extent = extent, + .stride = dim == 0 ? 1 : desc.global_strides[dim - 1]}; + } + } + + // Logical dimension order and increasing memory-stride order may differ. + // Validation and inversion must use the same storage-ordered basis. + // Extent-one axes have only coordinate zero and consume no address span. + // Use a bounded insertion sort: GCC 13 can report a false-positive + // -Warray-bounds error when std::sort is optimized for this five-element array. + for (uint32_t axis_idx = 1; axis_idx < axis_count_; ++axis_idx) { + const TensorDmaAxis axis = axes_[axis_idx]; + uint32_t insertion_idx = axis_idx; + while (insertion_idx > 0) { + const auto &previous = axes_[insertion_idx - 1]; + const bool axis_precedes_previous = + axis.stride < previous.stride || + (axis.stride == previous.stride && axis.dimension < previous.dimension); + if (!axis_precedes_previous) + break; + axes_[insertion_idx] = previous; + --insertion_idx; + } + axes_[insertion_idx] = axis; + } + } + + uint32_t rank() const { return rank_; } + bool empty() const { return empty_; } + + void validate_iteration_inverse() const { + if (empty_) + return; + + uint64_t occupied_span = 1; + for (uint32_t axis_idx = 0; axis_idx < axis_count_; ++axis_idx) { + const auto &axis = axes_[axis_idx]; + // Each axis must begin beyond the complete span of all faster axes for + // greedy mixed-radix inversion to be unique. + if (axis.stride < occupied_span) + throw util::UnimplementedInst("tensor DMA iterate non-invertible strides"); + + const uint64_t additional_span = + saturating_multiply(axis.stride, static_cast(axis.extent - 1)); + occupied_span = saturating_add(occupied_span, additional_span); + } + } + + std::array origin_from_linear_offset(uint64_t linear_offset) const { + std::array origin{}; + if (linear_offset == 0) + return origin; + + for (uint32_t axis_idx = axis_count_; axis_idx > 0; --axis_idx) { + const auto &axis = axes_[axis_idx - 1]; + origin[axis.dimension] = linear_offset / axis.stride; + linear_offset %= axis.stride; + } + // Dimension zero has implicit stride one. If it was omitted because its + // extent is one, preserve any padding remainder there so bounds masking + // rejects offsets outside the tensor domain. + if (linear_offset != 0) + origin[0] = linear_offset; + return origin; + } + +private: + std::array axes_{}; + uint32_t rank_ = 0; + uint32_t axis_count_ = 0; + bool empty_ = false; +}; + +inline void validate_supported_descriptor(const TensorDmaDescriptor &desc, + const TensorDmaLayout &layout) { // The in-tree HIP descriptor API and LLVM lowering only produce the boolean // count encodings 0 (disabled) and 1 (active). if (desc.count > 1) throw util::UnimplementedInst("tensor DMA count encoding"); - // LLVM MLIR's AMDGPU dialect documents padding only for memory-to-LDS copies. - if (desc.pad && store_from_lds) - throw util::UnimplementedInst("tensor DMA padded store descriptor"); if (desc.elem_size != 1 && desc.elem_size != 2 && desc.elem_size != 4 && desc.elem_size != 8) throw util::UnimplementedInst("tensor DMA element size"); - const uint32_t rank = desc.rank(); + const uint32_t rank = layout.rank(); if (!desc.gather && desc.gather_indices_32bit) throw util::UnimplementedInst("tensor DMA gather index-size bit without gather"); if (desc.gather) { - if (rank == 0) - return; - if (rank > 2) + if (rank != 2) throw util::UnimplementedInst("tensor DMA gather rank"); if (desc.tile_dims[0] == 0) throw util::UnimplementedInst("tensor DMA gather tile dimension"); @@ -213,6 +300,8 @@ inline void validate_supported_descriptor(const TensorDmaDescriptor &desc, bool } if (desc.iterate && (rank < 2 || rank > 3)) throw util::UnimplementedInst("tensor DMA iterate rank"); + if (desc.iterate && desc.iteration_count > 1 && desc.global_increment != 0) + layout.validate_iteration_inverse(); for (uint32_t dim = 0; dim < rank; ++dim) { if (desc.tile_dims[dim] == 0) throw util::UnimplementedInst("tensor DMA sparse tile dimensions"); @@ -226,7 +315,9 @@ inline void copy_bytes(const TensorDmaDescriptor &desc, Wavefront &wf, uint64_t const uint64_t global_addr = desc.global_base + global_element * desc.elem_size; uint64_t lds_byte = lds_element * desc.elem_size; - if (desc.pad) { + // The ISA applies descriptor padding only to memory-to-LDS transfers. + // Stores read the ordinary dense LDS stream and ignore the padding fields. + if (desc.pad && !store_from_lds) { const uint32_t pad_interval_bytes = desc.pad_interval * sizeof(uint32_t); const uint32_t pad_amount_bytes = desc.pad_amount * sizeof(uint32_t); lds_byte += (lds_byte / pad_interval_bytes) * pad_amount_bytes; @@ -250,28 +341,18 @@ inline void copy_bytes(const TensorDmaDescriptor &desc, Wavefront &wf, uint64_t wf.lds().write8(lds_addr + byte, element_bytes[byte]); } -inline void copy_gather_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, - bool store_from_lds) { - const uint32_t rank = desc.rank(); - if (rank == 0) - return; - +inline void copy_gather_tensor(const TensorDmaDescriptor &desc, const TensorDmaLayout &layout, + Wavefront &wf, bool store_from_lds) { for (uint32_t idx = 0; idx < desc.valid_indices; ++idx) { const uint32_t gather_index = desc.gather_indices[idx]; for (uint32_t coord0 = 0; coord0 < desc.tile_dims[0]; ++coord0) { - bool in_bounds = true; - uint64_t global_element = coord0; - if (rank == 1) { - global_element += gather_index; - if (desc.tensor_dims[0] != 0 && global_element >= desc.tensor_dims[0]) - in_bounds = false; - } else { - global_element += static_cast(gather_index) * desc.global_strides[0]; - if (desc.tensor_dims[0] != 0 && coord0 >= desc.tensor_dims[0]) - in_bounds = false; - if (desc.tensor_dims[1] != 0 && gather_index >= desc.tensor_dims[1]) - in_bounds = false; - } + bool in_bounds = !layout.empty(); + const uint64_t global_element = + coord0 + static_cast(gather_index) * desc.global_strides[0]; + if (coord0 >= desc.tensor_dims[0]) + in_bounds = false; + if (gather_index >= desc.tensor_dims[1]) + in_bounds = false; const uint64_t lds_element = static_cast(idx) * desc.tile_dims[0] + static_cast(coord0); @@ -280,8 +361,9 @@ inline void copy_gather_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, } } -inline void copy_dense_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, bool store_from_lds) { - const uint32_t rank = desc.rank(); +inline void copy_dense_tensor(const TensorDmaDescriptor &desc, const TensorDmaLayout &layout, + Wavefront &wf, bool store_from_lds) { + const uint32_t rank = layout.rank(); if (rank == 0) return; @@ -291,18 +373,23 @@ inline void copy_dense_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, bo const uint32_t iteration_count = desc.iterate ? desc.iteration_count : 1; for (uint32_t iter = 0; iter < iteration_count; ++iter) { + const uint64_t iteration_offset = static_cast(iter) * desc.global_increment; + const auto iteration_origin = desc.iterate && !layout.empty() + ? layout.origin_from_linear_offset(iteration_offset) + : std::array{}; for (uint64_t linear = 0; linear < element_count; ++linear) { uint64_t remaining = linear; - uint64_t global_element = static_cast(iter) * desc.global_increment; + uint64_t global_element = iteration_offset; uint64_t lds_element = static_cast(iter) * desc.lds_increment; uint64_t lds_stride = 1; - bool in_bounds = true; + bool in_bounds = !layout.empty(); for (uint32_t dim = 0; dim < rank; ++dim) { const uint32_t tile_dim = desc.tile_dims[dim]; const uint32_t coord = static_cast(remaining % tile_dim); remaining /= tile_dim; - if (desc.tensor_dims[dim] != 0 && coord >= desc.tensor_dims[dim]) + const uint64_t tensor_coord = iteration_origin[dim] + coord; + if (tensor_coord >= desc.tensor_dims[dim]) in_bounds = false; global_element += coord * (dim == 0 ? 1 : desc.global_strides[dim - 1]); lds_element += coord * lds_stride; @@ -315,11 +402,12 @@ inline void copy_dense_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, bo } inline void copy_tensor(const TensorDmaDescriptor &desc, Wavefront &wf, bool store_from_lds) { - validate_supported_descriptor(desc, store_from_lds); + const TensorDmaLayout layout(desc); + validate_supported_descriptor(desc, layout); if (desc.gather) - copy_gather_tensor(desc, wf, store_from_lds); + copy_gather_tensor(desc, layout, wf, store_from_lds); else - copy_dense_tensor(desc, wf, store_from_lds); + copy_dense_tensor(desc, layout, wf, store_from_lds); } inline void arrive_atomic_barrier(const TensorDmaDescriptor &desc, Wavefront &wf) { diff --git a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp index 3181f9705624..cb3e66dbb2f2 100644 --- a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp @@ -356,14 +356,16 @@ TEST(Gfx1250ExecutionTest, TensorDmaByteLoadUsesDwordPaddingUnits) { EXPECT_EQ(cu->lds().read8(wf->lds_base() + 275), 3u); } -TEST(Gfx1250ExecutionTest, TensorDmaPaddedStoreIsRejected) { +TEST(Gfx1250ExecutionTest, TensorDmaPaddedStoreIgnoresPadding) { Gfx1250Sim sim; auto *cu = sim.cu(); auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); ASSERT_NE(wf, nullptr); wf->set_lds_base(cu->allocate_lds(256)); - write_tensor_dma_d0(*cu, *wf, 0, 0x121000); + constexpr uint64_t kGlobal = 0x122000; + constexpr uint32_t kSentinel = 0xAC1DAC1Du; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 20)); // i32, pad enabled. write_wave_sgpr(*cu, *wf, 13, 4u << 16); write_wave_sgpr(*cu, *wf, 14, 0); @@ -373,9 +375,17 @@ TEST(Gfx1250ExecutionTest, TensorDmaPaddedStoreIsRejected) { write_wave_sgpr(*cu, *wf, 18, 0); write_wave_sgpr(*cu, *wf, 19, 0); + for (uint32_t i = 0; i < 4; ++i) { + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), kSentinel); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), 0x34000000u + i); + } + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x7c7c0c00u}; cdna5::TensorStoreFromLdsVimage store_inst(store_words.data()); - EXPECT_THROW(store_inst.execute_impl(*wf), util::UnimplementedInst); + store_inst.execute_impl(*wf); + + for (uint32_t i = 0; i < 4; ++i) + EXPECT_EQ(read_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t)), 0x34000000u + i); } TEST(Gfx1250ExecutionTest, TensorDmaIterateCopiesMultipleTiles) { @@ -393,7 +403,7 @@ TEST(Gfx1250ExecutionTest, TensorDmaIterateCopiesMultipleTiles) { write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. write_wave_sgpr(*cu, *wf, 15, 2u << 16); // tile dim0. write_wave_sgpr(*cu, *wf, 16, 1u); // tile dim1. - write_wave_sgpr(*cu, *wf, 17, 0); + write_wave_sgpr(*cu, *wf, 17, 2u); // tensor dim0 stride. write_wave_sgpr(*cu, *wf, 18, 0); write_wave_sgpr(*cu, *wf, 19, 0); write_wave_sgpr(*cu, *wf, 20, 0); @@ -507,6 +517,567 @@ TEST(Gfx1250ExecutionTest, TensorDmaUnsupportedCountEncodingsAreRejected) { } } +TEST(Gfx1250ExecutionTest, TensorDmaIterateMasksRowsBeyondTensorDimension) { + // Two iterations cover four rows, but the tensor has only three. The final + // repeated row must be zero-filled instead of copied from global memory. + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x131000; + constexpr uint32_t kCols = 2; + constexpr uint32_t kRows = 3; + constexpr uint32_t kTileRows = 2; + constexpr uint32_t kIterations = 2; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, kCols << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, kRows << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, kCols << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, kTileRows); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, kCols); // tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, kCols * kTileRows); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, kCols * kTileRows); // Global increment in elements. + write_wave_sgpr(*cu, *wf, 23, (kIterations - 1) << 16); + + for (uint32_t row = 0; row < kTileRows * kIterations; ++row) { + for (uint32_t col = 0; col < kCols; ++col) + write_global_u32(*sim.memory, kGlobal + (row * kCols + col) * 4, + 0x45000000u + row * 0x100u + col); + } + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t row = 0; row < kTileRows * kIterations; ++row) { + for (uint32_t col = 0; col < kCols; ++col) { + const uint32_t actual = + cu->lds().read32(wf->lds_base() + (row * kCols + col) * sizeof(uint32_t)); + const uint32_t expected = row < kRows ? 0x45000000u + row * 0x100u + col : 0u; + EXPECT_EQ(actual, expected) << "row " << row << ", col " << col; + } + } +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateStoreSkipsRowsBeyondTensorDimension) { + // Two iterations source four LDS rows, but the tensor has only three. The + // final repeated row must not overwrite global memory. + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x136000; + constexpr uint32_t kCols = 2; + constexpr uint32_t kRows = 3; + constexpr uint32_t kTileRows = 2; + constexpr uint32_t kIterations = 2; + constexpr uint32_t kSentinel = 0xAC1DAC1Du; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, kCols << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, kRows << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, kCols << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, kTileRows); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, kCols); // tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, kCols * kTileRows); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, kCols * kTileRows); // Global increment in elements. + write_wave_sgpr(*cu, *wf, 23, (kIterations - 1) << 16); + + for (uint32_t row = 0; row < kTileRows * kIterations; ++row) { + for (uint32_t col = 0; col < kCols; ++col) { + write_global_u32(*sim.memory, kGlobal + (row * kCols + col) * 4, kSentinel); + cu->lds().write32(wf->lds_base() + (row * kCols + col) * sizeof(uint32_t), + 0x4B000000u + row * 0x100u + col); + } + } + + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x7c140c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + + for (uint32_t row = 0; row < kTileRows * kIterations; ++row) { + for (uint32_t col = 0; col < kCols; ++col) { + const uint32_t actual = + read_global_u32(*sim.memory, kGlobal + (row * kCols + col) * sizeof(uint32_t)); + const uint32_t expected = row < kRows ? 0x4B000000u + row * 0x100u + col : kSentinel; + EXPECT_EQ(actual, expected) << "row " << row << ", col " << col; + } + } +} + +TEST(Gfx1250ExecutionTest, TensorDmaZeroLengthDimensionMasksEntireTile) { + // Global memory contains data and LDS starts nonzero. A zero active tensor + // extent must actively zero-fill the tile rather than copy or do nothing. + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x132000; + constexpr uint32_t kCols = 2; + constexpr uint32_t kTileRows = 2; + constexpr uint32_t kSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, kCols << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 0); // tensor dim1 has no valid rows. + write_wave_sgpr(*cu, *wf, 15, kCols << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, kTileRows); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, kCols); // tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + + for (uint32_t row = 0; row < kTileRows; ++row) { + for (uint32_t col = 0; col < kCols; ++col) + write_global_u32(*sim.memory, kGlobal + (row * kCols + col) * 4, + 0x46000000u + row * 0x100u + col); + } + for (uint32_t i = 0; i < kCols * kTileRows; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kSentinel); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x18140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kCols * kTileRows; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), 0u) << "element " << i; +} + +TEST(Gfx1250ExecutionTest, TensorDmaRankThreeNullD2MasksTransfersAndCompletes) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x137000; + constexpr uint32_t kElements = 2; + constexpr uint32_t kBarrierLdsAddr = 64; + constexpr uint32_t kGlobalSentinel = 0xAC1DAC1Du; + constexpr uint32_t kLdsSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, + (2u << 16) | (1u << 18)); // i32 elements, atomic barrier enabled. + write_wave_sgpr(*cu, *wf, 13, + (2u << 16) | (kBarrierLdsAddr >> 3)); // tensor dim0 and barrier address. + write_wave_sgpr(*cu, *wf, 14, 1u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, kElements << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u | (1u << 16)); // tile dim1 and dim2. + write_wave_sgpr(*cu, *wf, 17, 2u); // tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 2u << 16); // tensor dim1 stride. + write_wave_sgpr(*cu, *wf, 19, 0); + + for (uint32_t i = 0; i < kElements; ++i) { + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x4C000000u + i); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kLdsSentinel); + } + cu->lds().write64(wf->lds_base() + kBarrierLdsAddr, 0); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c7c0c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), 0u) << "element " << i; + EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); + EXPECT_TRUE(wf->wait_counters().empty()); + uint64_t barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); + EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); + + for (uint32_t i = 0; i < kElements; ++i) { + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), kGlobalSentinel); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), 0x4D000000u + i); + } + cu->lds().write64(wf->lds_base() + kBarrierLdsAddr, 0); + + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x7c7c0c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + + for (uint32_t i = 0; i < kElements; ++i) + EXPECT_EQ(read_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t)), kGlobalSentinel) + << "element " << i; + EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); + EXPECT_TRUE(wf->wait_counters().empty()); + barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); + EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); +} + +TEST(Gfx1250ExecutionTest, TensorDmaNonIteratingRankFiveAvoidsOriginDecomposition) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x138000; + constexpr uint32_t kValue = 0x4C000000u; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, 0); + write_wave_sgpr(*cu, *wf, 14, 1u); // tensor dim0 = 65536. + write_wave_sgpr(*cu, *wf, 15, 1u | (1u << 16)); // tensor dim1 = 65536, tile dim0 = 1. + write_wave_sgpr(*cu, *wf, 16, 1u | (1u << 16)); // tile dim1 and dim2. + write_wave_sgpr(*cu, *wf, 17, 0); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 65536u); // tensor dim2. + write_wave_sgpr(*cu, *wf, 21, 65536u); // tensor dim3. + write_wave_sgpr(*cu, *wf, 22, 0); + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // tile dim3. + write_wave_sgpr(*cu, *wf, 24, 0); + write_wave_sgpr(*cu, *wf, 25, 1u << 16); // tensor dim4. + write_wave_sgpr(*cu, *wf, 26, 1u << 16); // tile dim4. + write_wave_sgpr(*cu, *wf, 27, 0); + + write_global_u32(*sim.memory, kGlobal, kValue); + cu->lds().write32(wf->lds_base(), 0xDEADDEADu); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x18140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base()), kValue); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateMasksSubrowOriginBeyondTensor) { + // Three one-element iterations walk a 2x1 tensor. The first two origins are + // valid dim0 coordinates; the third carries into dim1 and must zero-fill. + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x133000; + constexpr uint32_t kSentinel = 0xBAD0BAD0u; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 1u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 1u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, 2u); // tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, 1u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 1u); // Global increment in elements. + write_wave_sgpr(*cu, *wf, 23, 2u << 16); // iteration_count - 1. + + for (uint32_t i = 0; i < 3; ++i) { + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x49000000u + i); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kSentinel); + } + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 0 * 4), 0x49000000u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 1 * 4), 0x49000001u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 2 * 4), 0u); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateMasksPlanesBeyondTensorDimension) { + // The descriptor iterates across two planes of a tensor whose depth is one. + // The second plane must be zero-filled rather than copied. + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x134000; + constexpr uint32_t kSentinel = 0xFACEFACEu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 2u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u | (1u << 16)); // tile dim1 and dim2. + write_wave_sgpr(*cu, *wf, 17, 2u); // tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 4u << 16); // tensor dim1 stride. + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 1u); // tensor dim2. + write_wave_sgpr(*cu, *wf, 21, 2u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 4u); // Global increment in elements. + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // iteration_count - 1. + + for (uint32_t i = 0; i < 6; ++i) + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x4A000000u + i); + for (uint32_t i = 0; i < 4; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kSentinel); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 0 * 4), 0x4A000000u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 1 * 4), 0x4A000001u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 2 * 4), 0u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 3 * 4), 0u); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateRejectsOverlappingStrides) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + write_tensor_dma_d0(*cu, *wf, 0, 0x135000); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 1u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, 1u); // Overlaps tensor dim0. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, 1u); + write_wave_sgpr(*cu, *wf, 22, 1u); + write_wave_sgpr(*cu, *wf, 23, 1u << 16); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + EXPECT_THROW(load->execute(*load, wf), util::UnimplementedInst); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateAllowsAliasedUnitExtent) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x185000; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 1u << 16); // unit tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 1u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, 1u); // dim1 aliases dim0 but has only one coordinate. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, 1u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 1u); // advance along tensor dim0. + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // iteration_count - 1. + + write_global_u32(*sim.memory, kGlobal, 0x55000000u); + write_global_u32(*sim.memory, kGlobal + sizeof(uint32_t), 0x55000001u); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base()), 0x55000000u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + sizeof(uint32_t)), 0x55000001u); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateAllowsPermutedNonOverlappingStrides) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x183000; + constexpr uint32_t kSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 1u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u | (1u << 16)); // tile dim1 and dim2. + write_wave_sgpr(*cu, *wf, 17, 4u); // tensor dim1 stride. + write_wave_sgpr(*cu, *wf, 18, 2u << 16); // tensor dim2 stride. + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 2u); // tensor dim2. + write_wave_sgpr(*cu, *wf, 21, 1u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 2u); // advance along tensor dim2. + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // iteration_count - 1. + + for (uint32_t i = 0; i < 8; ++i) + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x52000000u + i); + cu->lds().write32(wf->lds_base(), kSentinel); + cu->lds().write32(wf->lds_base() + sizeof(uint32_t), kSentinel); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base()), 0x52000000u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + sizeof(uint32_t)), 0x52000002u); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateAllowsRepeatedOriginWithOverlappingStrides) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x139000; + constexpr uint32_t kValue = 0x4D000000u; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 1u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, 1u); // overlapping tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, 1u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 0); // Global origin does not advance. + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // iteration_count - 1. + + write_global_u32(*sim.memory, kGlobal, kValue); + cu->lds().write32(wf->lds_base() + 0 * sizeof(uint32_t), 0xDEADDEADu); + cu->lds().write32(wf->lds_base() + 1 * sizeof(uint32_t), 0xDEADDEADu); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 0 * sizeof(uint32_t)), kValue); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + 1 * sizeof(uint32_t)), kValue); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateAllowsPaddedRowPlaneStride) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x13A000; + constexpr uint32_t kSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, (2u << 16) | (1u << 19)); // i32, iterate enabled. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, 1u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u | (1u << 16)); // tile dim1 and dim2. + write_wave_sgpr(*cu, *wf, 17, 4u); // padded tensor dim0 stride. + write_wave_sgpr(*cu, *wf, 18, 6u << 16); // occupied plane span. + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 2u); // tensor dim2. + write_wave_sgpr(*cu, *wf, 21, 1u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 6u); // Global plane increment in elements. + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // iteration_count - 1. + + write_global_u32(*sim.memory, kGlobal, 0x4E000000u); + write_global_u32(*sim.memory, kGlobal + 6 * sizeof(uint32_t), 0x4E000001u); + cu->lds().write32(wf->lds_base(), kSentinel); + cu->lds().write32(wf->lds_base() + sizeof(uint32_t), kSentinel); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + EXPECT_EQ(cu->lds().read32(wf->lds_base()), 0x4E000000u); + EXPECT_EQ(cu->lds().read32(wf->lds_base() + sizeof(uint32_t)), 0x4E000001u); +} + +TEST(Gfx1250ExecutionTest, TensorDmaIterateZeroExtentSkipsLayoutValidationAndCompletes) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x13B000; + constexpr uint32_t kElements = 4; + constexpr uint32_t kBarrierLdsAddr = 64; + constexpr uint32_t kGlobalSentinel = 0xAC1DAC1Du; + constexpr uint32_t kLdsSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 12, + (2u << 16) | (1u << 18) | (1u << 19)); // i32, atomic barrier and iterate enabled. + write_wave_sgpr(*cu, *wf, 13, + (2u << 16) | (kBarrierLdsAddr >> 3)); // tensor dim0 and barrier address. + write_wave_sgpr(*cu, *wf, 14, 0); // tensor dim1 is empty. + write_wave_sgpr(*cu, *wf, 15, 2u << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 1u); // tile dim1. + write_wave_sgpr(*cu, *wf, 17, 1u); // overlaps tensor dim0. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); + write_wave_sgpr(*cu, *wf, 21, 2u); // LDS increment in elements. + write_wave_sgpr(*cu, *wf, 22, 1u); // Global increment in elements. + write_wave_sgpr(*cu, *wf, 23, 1u << 16); // iteration_count - 1. + + for (uint32_t i = 0; i < kElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kLdsSentinel); + cu->lds().write64(wf->lds_base() + kBarrierLdsAddr, 0); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x7c140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), 0u) << "element " << i; + EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); + EXPECT_TRUE(wf->wait_counters().empty()); + uint64_t barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); + EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); + + for (uint32_t i = 0; i < 3; ++i) + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), kGlobalSentinel); + for (uint32_t i = 0; i < kElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), 0x4F000000u + i); + cu->lds().write64(wf->lds_base() + kBarrierLdsAddr, 0); + + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x7c140c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + + for (uint32_t i = 0; i < 3; ++i) + EXPECT_EQ(read_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t)), kGlobalSentinel) + << "element " << i; + EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); + EXPECT_TRUE(wf->wait_counters().empty()); + barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); + EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); +} + TEST(Gfx1250ExecutionTest, TensorDmaAtomicBarrierArrivesAfterCopy) { Gfx1250Sim sim; auto *cu = sim.cu(); @@ -918,4 +1489,207 @@ TEST(Gfx1250ExecutionTest, TensorDmaGatherSupportsI16Indices) { } } +TEST(Gfx1250ExecutionTest, TensorDmaGatherZeroStrideAliasesRows) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x180800; + constexpr uint32_t kCols = 2; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 0, 1u | (1u << 31)); // gather enabled. + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, kCols << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 2u << 16); // tensor dim1. + write_wave_sgpr(*cu, *wf, 15, kCols << 16); // tile dim0. + write_wave_sgpr(*cu, *wf, 16, 2u); // two valid gather indices. + write_wave_sgpr(*cu, *wf, 17, 0); // literal zero row stride. + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0u | (1u << 16)); // gather rows 0 and 1. + write_wave_sgpr(*cu, *wf, 21, 0); + write_wave_sgpr(*cu, *wf, 22, 0); + write_wave_sgpr(*cu, *wf, 23, 0); + write_wave_sgpr(*cu, *wf, 24, 0); + write_wave_sgpr(*cu, *wf, 25, 0); + write_wave_sgpr(*cu, *wf, 26, 0); + write_wave_sgpr(*cu, *wf, 27, 0); + + for (uint32_t col = 0; col < kCols; ++col) + write_global_u32(*sim.memory, kGlobal + col * sizeof(uint32_t), 0x6B000000u + col); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x18140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t row = 0; row < 2; ++row) { + for (uint32_t col = 0; col < kCols; ++col) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + (row * kCols + col) * sizeof(uint32_t)), + 0x6B000000u + col); + } +} + +TEST(Gfx1250ExecutionTest, TensorDmaGatherZeroExtentMasksEntireTile) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x181000; + constexpr uint32_t kTileElements = 2; + constexpr uint32_t kSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 0, 1u | (1u << 31)); // gather enabled. + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, 0); // tensor dim0 is empty. + write_wave_sgpr(*cu, *wf, 14, 0); + write_wave_sgpr(*cu, *wf, 15, kTileElements << 16); + write_wave_sgpr(*cu, *wf, 16, 1u); // one valid gather index. + write_wave_sgpr(*cu, *wf, 17, 0); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 1u); // gather index. + write_wave_sgpr(*cu, *wf, 21, 0); + write_wave_sgpr(*cu, *wf, 22, 0); + write_wave_sgpr(*cu, *wf, 23, 0); + write_wave_sgpr(*cu, *wf, 24, 0); + write_wave_sgpr(*cu, *wf, 25, 0); + write_wave_sgpr(*cu, *wf, 26, 0); + write_wave_sgpr(*cu, *wf, 27, 0); + + for (uint32_t i = 0; i < 3; ++i) + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x6A000000u + i); + for (uint32_t i = 0; i < kTileElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kSentinel); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x18140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kTileElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), 0u) << "element " << i; +} + +TEST(Gfx1250ExecutionTest, TensorDmaGatherRankTwoZeroExtentMasksLoadAndStore) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x182000; + constexpr uint32_t kRows = 4; + constexpr uint32_t kTileElements = 2; + constexpr uint32_t kGlobalSentinel = 0xAC1DAC1Du; + constexpr uint32_t kLdsSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 0, 1u | (1u << 31)); // gather enabled. + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, 0); // tensor dim0 is empty. + write_wave_sgpr(*cu, *wf, 14, kRows << 16); // tensor dim1 keeps rank two. + write_wave_sgpr(*cu, *wf, 15, kTileElements << 16); + write_wave_sgpr(*cu, *wf, 16, 1u); // one valid gather index. + write_wave_sgpr(*cu, *wf, 17, kTileElements); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 1u); // gather index. + write_wave_sgpr(*cu, *wf, 21, 0); + write_wave_sgpr(*cu, *wf, 22, 0); + write_wave_sgpr(*cu, *wf, 23, 0); + write_wave_sgpr(*cu, *wf, 24, 0); + write_wave_sgpr(*cu, *wf, 25, 0); + write_wave_sgpr(*cu, *wf, 26, 0); + write_wave_sgpr(*cu, *wf, 27, 0); + + for (uint32_t i = 0; i < kRows * kTileElements; ++i) + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x50000000u + i); + for (uint32_t i = 0; i < kTileElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kLdsSentinel); + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x18140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kTileElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), 0u) << "element " << i; + + for (uint32_t i = 0; i < kRows * kTileElements; ++i) + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), kGlobalSentinel); + for (uint32_t i = 0; i < kTileElements; ++i) + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), 0x51000000u + i); + + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x18140c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + + for (uint32_t i = 0; i < kRows * kTileElements; ++i) + EXPECT_EQ(read_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t)), kGlobalSentinel) + << "element " << i; +} + +TEST(Gfx1250ExecutionTest, TensorDmaGatherRankTwoZeroOuterExtentMasksLoadAndStore) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_lds_base(cu->allocate_lds(256)); + + constexpr uint64_t kGlobal = 0x184000; + constexpr uint32_t kTileElements = 2; + constexpr uint32_t kGlobalSentinel = 0xAC1DAC1Du; + constexpr uint32_t kLdsSentinel = 0xDEADDEADu; + write_tensor_dma_d0(*cu, *wf, 0, kGlobal); + write_wave_sgpr(*cu, *wf, 0, 1u | (1u << 31)); // gather enabled. + write_wave_sgpr(*cu, *wf, 12, 2u << 16); // i32 elements. + write_wave_sgpr(*cu, *wf, 13, 2u << 16); // tensor dim0. + write_wave_sgpr(*cu, *wf, 14, 0); // tensor dim1 is empty. + write_wave_sgpr(*cu, *wf, 15, kTileElements << 16); + write_wave_sgpr(*cu, *wf, 16, 1u); // one valid gather index. + write_wave_sgpr(*cu, *wf, 17, kTileElements); + write_wave_sgpr(*cu, *wf, 18, 0); + write_wave_sgpr(*cu, *wf, 19, 0); + write_wave_sgpr(*cu, *wf, 20, 0); // gather index. + write_wave_sgpr(*cu, *wf, 21, 0); + write_wave_sgpr(*cu, *wf, 22, 0); + write_wave_sgpr(*cu, *wf, 23, 0); + write_wave_sgpr(*cu, *wf, 24, 0); + write_wave_sgpr(*cu, *wf, 25, 0); + write_wave_sgpr(*cu, *wf, 26, 0); + write_wave_sgpr(*cu, *wf, 27, 0); + + for (uint32_t i = 0; i < kTileElements; ++i) { + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), 0x53000000u + i); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), kLdsSentinel); + } + + const std::array load_words = {0xd0710001u, 0x7c000000u, 0x18140c00u}; + auto load = decode_gfx1250(load_words, "tensor_load_to_lds"); + ASSERT_NE(load, nullptr); + load->execute(*load, wf); + + for (uint32_t i = 0; i < kTileElements; ++i) + EXPECT_EQ(cu->lds().read32(wf->lds_base() + i * sizeof(uint32_t)), 0u) << "element " << i; + + for (uint32_t i = 0; i < kTileElements; ++i) { + write_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t), kGlobalSentinel); + cu->lds().write32(wf->lds_base() + i * sizeof(uint32_t), 0x54000000u + i); + } + + const std::array store_words = {0xd0714001u, 0x7c000000u, 0x18140c00u}; + auto store = decode_gfx1250(store_words, "tensor_store_from_lds"); + ASSERT_NE(store, nullptr); + store->execute(*store, wf); + + for (uint32_t i = 0; i < kTileElements; ++i) + EXPECT_EQ(read_global_u32(*sim.memory, kGlobal + i * sizeof(uint32_t)), kGlobalSentinel) + << "element " << i; +} + } // namespace From 370bfb979679e3294d319527083864ef1e2ec930 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 18 Aug 2026 13:38:00 -0400 Subject: [PATCH 14/27] [rocjitsu] Fix gfx950 decoder extension handling (#10204) These were found by the fuzzer added in https://github.com/ROCm/rocm-systems/pull/9912. - validate CDNA4 VOP3PX2 suffix pairs before constructing combined instructions - size literal and compact modifier extensions from the selected opcode and operand capabilities - render SDWA source and destination modifiers from extension words and reject invalid selector combinations (cherry picked from commit 60c29efb390392f4c9bdc8b417ae5d7b67bf6dd2) --- .../lib/python/amdisa/codegen/_generator.py | 524 ++++- .../tests/test_generator_profile_gates.py | 48 +- .../amdisa/tests/test_literal_codegen.py | 57 + .../arch/amdgpu/generated/cdna1/encodings.cpp | 847 +++++++- .../arch/amdgpu/generated/cdna1/encodings.h | 29 + .../isa/arch/amdgpu/generated/cdna1/sopc.cpp | 4 - .../isa/arch/amdgpu/generated/cdna1/vop1.cpp | 422 +++- .../isa/arch/amdgpu/generated/cdna1/vop2.cpp | 473 ++++- .../isa/arch/amdgpu/generated/cdna1/vopc.cpp | 1834 ++++++++++++++--- .../arch/amdgpu/generated/cdna2/encodings.cpp | 847 +++++++- .../arch/amdgpu/generated/cdna2/encodings.h | 29 + .../isa/arch/amdgpu/generated/cdna2/sopc.cpp | 4 - .../isa/arch/amdgpu/generated/cdna2/vop1.cpp | 430 +++- .../isa/arch/amdgpu/generated/cdna2/vop2.cpp | 463 ++++- .../isa/arch/amdgpu/generated/cdna2/vopc.cpp | 1834 ++++++++++++++--- .../arch/amdgpu/generated/cdna3/encodings.cpp | 856 +++++++- .../arch/amdgpu/generated/cdna3/encodings.h | 29 + .../isa/arch/amdgpu/generated/cdna3/sopc.cpp | 4 - .../isa/arch/amdgpu/generated/cdna3/vop1.cpp | 469 ++++- .../isa/arch/amdgpu/generated/cdna3/vop2.cpp | 463 ++++- .../isa/arch/amdgpu/generated/cdna3/vopc.cpp | 1834 ++++++++++++++--- .../arch/amdgpu/generated/cdna4/decoder.cpp | 34 +- .../arch/amdgpu/generated/cdna4/encodings.cpp | 865 +++++++- .../arch/amdgpu/generated/cdna4/encodings.h | 29 + .../isa/arch/amdgpu/generated/cdna4/sopc.cpp | 4 - .../isa/arch/amdgpu/generated/cdna4/vop1.cpp | 500 ++++- .../isa/arch/amdgpu/generated/cdna4/vop2.cpp | 463 ++++- .../isa/arch/amdgpu/generated/cdna4/vopc.cpp | 1834 ++++++++++++++--- .../arch/amdgpu/generated/cdna5/encodings.cpp | 1781 +++++++++++++++- .../arch/amdgpu/generated/cdna5/encodings.h | 15 + .../arch/amdgpu/generated/rdna1/encodings.cpp | 1313 +++++++++++- .../arch/amdgpu/generated/rdna1/encodings.h | 34 +- .../isa/arch/amdgpu/generated/rdna1/vop1.cpp | 383 +++- .../isa/arch/amdgpu/generated/rdna1/vop2.cpp | 314 ++- .../isa/arch/amdgpu/generated/rdna1/vopc.cpp | 1726 +++++++++++++--- .../arch/amdgpu/generated/rdna2/encodings.cpp | 1306 +++++++++++- .../arch/amdgpu/generated/rdna2/encodings.h | 34 +- .../isa/arch/amdgpu/generated/rdna2/vop1.cpp | 383 +++- .../isa/arch/amdgpu/generated/rdna2/vop2.cpp | 314 ++- .../isa/arch/amdgpu/generated/rdna2/vopc.cpp | 1726 +++++++++++++--- .../arch/amdgpu/generated/rdna3/encodings.cpp | 1009 ++++++++- .../arch/amdgpu/generated/rdna3/encodings.h | 9 + .../amdgpu/generated/rdna3_5/encodings.cpp | 1067 +++++++++- .../arch/amdgpu/generated/rdna3_5/encodings.h | 9 + .../arch/amdgpu/generated/rdna4/encodings.cpp | 1064 +++++++++- .../arch/amdgpu/generated/rdna4/encodings.h | 9 + .../isa/arch/amdgpu/shared/dpp_sdwa_ops.h | 83 +- .../arch/amdgpu/shared/instruction_encoding.h | 12 + .../rocjitsu/src/rocjitsu/isa/instruction.h | 19 +- .../rocjitsu/tests/decode_smoke_test.cpp | 36 + .../rocjitsu/tests/execution_plugin_test.cpp | 2 +- .../rocjitsu/tests/shared_infra_test.cpp | 153 ++ 52 files changed, 25528 insertions(+), 2502 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 58105c798ed2..1c94bb8f976b 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -154,6 +154,31 @@ class _Literal32Widening(Enum): ), } +# Immediate operands carry their value directly in the instruction encoding. +_IMMEDIATE_OPERAND_TYPES = ( + 'OPR_SIMM4', + 'OPR_SIMM8', + 'OPR_SIMM16', + 'OPR_SIMM32', + 'OPR_SIMM64', + 'OPR_LABEL', + 'OPR_WAITCNT', +) + +# Only operand selector families that define SRC_LITERAL may consume a literal +# extension word. Keeping this as an allowlist makes new selector types fail +# closed until their literal capability is explicitly established. +_LITERAL_CAPABLE_OPERAND_TYPES = frozenset( + { + 'OPR_SRC', + 'OPR_SRC_NOINLINE', + 'OPR_SRC_NOLDS', + 'OPR_SREG_LITERAL', + 'OPR_SSRC', + 'OPR_SSRC_NOLDS', + } +) + def _exec_mask_flag_stmts(sem) -> list[str]: """Return ``flags_ |= ...;`` statements for EXEC instruction metadata. @@ -896,6 +921,81 @@ def _literal_encoding_info( lit_enc = enc if inst.is_implied_literal_enc else (inst_enc_obj or enc) return _LITERAL_ENCODING_OPERANDS.get(lit_enc.enc_name.upper()) + @staticmethod + def _encoded_literal_field_masks( + inst_enc: InstEncoding, literal_fields: tuple[str, ...] + ) -> dict[int, tuple[str, ...]]: + """Return the active literal-selector fields for each opcode. + + Encoding formats describe every possible source field, but individual + opcodes may use only a subset of them or reinterpret one as inline + immediate data. Extension sizing must follow the selected opcode's + operands rather than every field present in the format. + """ + fields_by_opcode: dict[int, set[str]] = {} + for inst in inst_enc.insts: + active = fields_by_opcode.setdefault(inst.opcode, set()) + active.update( + opnd.name + for opnd in inst.operands + if opnd.name in literal_fields + and opnd.operand_type in _LITERAL_CAPABLE_OPERAND_TYPES + ) + return { + opcode: tuple(field for field in literal_fields if field in active) + for opcode, active in fields_by_opcode.items() + } + + @classmethod + def _encoded_literal_helper_impl( + cls, + inst_enc: InstEncoding, + literal_fields: tuple[str, ...], + selector: int, + ) -> str: + """Render an opcode-aware encoded-literal predicate.""" + grouped_opcodes: dict[tuple[str, ...], list[int]] = {} + for opcode, fields in cls._encoded_literal_field_masks( + inst_enc, literal_fields + ).items(): + grouped_opcodes.setdefault(fields, []).append(opcode) + + name = f'has_encoded_literal{64 if selector == 254 else 32}' + lines = [ + f'bool {inst_enc.fmt_enc_name}::{name}() const {{', + ' switch (inst_.op) {', + ] + for fields, opcodes in sorted( + grouped_opcodes.items(), key=lambda item: (item[0], item[1]) + ): + if not fields: + continue + lines.extend(f' case {opcode}:' for opcode in sorted(opcodes)) + condition = ' || '.join(f'inst_.{field} == {selector}' for field in fields) + lines.append(f' return {condition};') + lines.extend((' default:', ' return false;', ' }', '}')) + return '\n'.join(lines) + + @staticmethod + def _opcode_predicate_helper_impl( + inst_enc: InstEncoding, + name: str, + opcodes: list[int], + selector_condition: str | None = None, + ) -> str: + """Render an opcode membership predicate for an encoding feature.""" + lines = [ + f'bool {inst_enc.fmt_enc_name}::{name}() const {{', + ] + if selector_condition: + lines.extend((f' if (!({selector_condition}))', ' return false;')) + lines.append(' switch (inst_.op) {') + lines.extend(f' case {opcode}:' for opcode in sorted(opcodes)) + lines.extend( + (' return true;', ' default:', ' return false;', ' }', '}') + ) + return '\n'.join(lines) + @staticmethod def _literal_operand_from_expr_stmt( opnd: Operand, @@ -1126,6 +1226,18 @@ def _supports_vop_dpp_encoding(self, enc_name: str) -> bool: dpp_struct is not None and self._supports_dpp_for_encoding(enc_name) ) or dpp8_struct is not None + def _supports_sdwa_for_encoding(self, enc_name: str) -> bool: + """Whether any instruction in an encoding has an SDWA alternate.""" + enc_upper = enc_name.upper() + if enc_upper not in ('ENC_VOP1', 'ENC_VOP2', 'ENC_VOPC'): + return False + return any( + self._instruction_supports_sdwa(inst, enc_name) + for inst_enc in self.isa_spec.inst_encodings + if inst_enc.enc_name.upper() == enc_upper + for inst in inst_enc.insts + ) + def _supports_dpp_for_encoding(self, enc_name: str) -> bool: enc_upper = enc_name.upper() if enc_upper != 'ENC_VOPC': @@ -2572,6 +2684,7 @@ def gen_encodings(self) -> None: for inst_enc in self.isa_spec.inst_encodings: if not inst_enc.insts: continue + enc_upper = inst_enc.enc_name.upper() enc_field_names = {f.name for f in inst_enc.ucode_fields} literal_fields = _LITERAL_ENCODING_OPERANDS.get( inst_enc.enc_name.upper(), ('', ()) @@ -2588,6 +2701,9 @@ def gen_encodings(self) -> None: unsupported_literal64_fields = self._unsupported_literal64_selector_fields( inst_enc ) + supports_sdwa_extension = self._supports_sdwa_for_encoding( + inst_enc.enc_name + ) supports_fixed_size_embedding = ( self._supports_gfx1250_scaled_wmma_vop3px2() and inst_enc.fmt_enc_name == 'Vop3p' @@ -2723,6 +2839,24 @@ def gen_encodings(self) -> None: if has_op: size_line += '\n opcode_ = inst_.op;' literal64_conds = self._literal64_condition_names(inst_enc) + explicit_literal64_conds = [ + name for name, _ in inst_enc.enc_conds if name.startswith('has_lit64') + ] + if explicit_literal64_conds and encoded_literal_fields: + public_members.append(cgen.Line('bool has_encoded_literal64() const;')) + class_func_impls.append( + cgen.Line( + self._encoded_literal_helper_impl( + inst_enc, encoded_literal_fields, 254 + ) + ) + ) + literal64_conds = [ + name + for name in literal64_conds + if name not in explicit_literal64_conds + ] + literal64_conds.append('has_encoded_literal64') implied_literal64_ops = [ str(inst.opcode) for inst in inst_enc.insts @@ -2735,6 +2869,16 @@ def gen_encodings(self) -> None: for name, _ in inst_enc.enc_conds if name.startswith('has_lit') and not name.startswith('has_lit64') ] + if literal32_conds and encoded_literal_fields: + public_members.append(cgen.Line('bool has_encoded_literal32() const;')) + class_func_impls.append( + cgen.Line( + self._encoded_literal_helper_impl( + inst_enc, encoded_literal_fields, 255 + ) + ) + ) + literal32_conds = ['has_encoded_literal32'] literal32_condition = ' || '.join(f'{name}()' for name in literal32_conds) if supports_fixed_size_embedding: size_line += ' if (extension_policy == ExtensionDecodePolicy::Decode) {' @@ -2769,22 +2913,9 @@ def gen_encodings(self) -> None: ' throw util::InvalidInst(' f'std::string(mnemonic) + " does not support {width}-bit literals", "");' ) - non_literal_selector_ops = sorted( - { - inst.opcode - for inst in inst_enc.insts - if any( - opnd.name in literal_fields - and opnd.operand_type in ('OPR_SENDMSG', 'OPR_SENDMSG_RTN') - for opnd in inst.operands - ) - } - ) if needs_explicit_dpp_size and encoded_literal_fields: dpp_extension_condition = ' || '.join(dpp_extension_conditions) - literal_selector_condition = ' || '.join( - f'inst_.{field} == 255' for field in encoded_literal_fields - ) + literal_selector_condition = literal32_condition or 'false' size_line += ( f' if (({dpp_extension_condition}) && ' f'({literal_selector_condition}))' @@ -2796,13 +2927,63 @@ def gen_encodings(self) -> None: # not the architecture-wide operand selector table. For example, # gfx1250 defines selector 254 for 64-bit literals, but the 64-bit # VOP3 and VOP3P encodings only support a 32-bit literal extension. + encoded_sdwa_opcodes = ( + [ + inst.opcode + for inst in inst_enc.insts + if self._instruction_supports_sdwa(inst, inst_enc.enc_name) + ] + if supports_sdwa_extension + else [] + ) + encoded_sdwa_condition = '' + if encoded_sdwa_opcodes: + encoded_sdwa_condition = 'has_encoded_sdwa()' + public_members.append(cgen.Line('bool has_encoded_sdwa() const;')) + class_func_impls.append( + cgen.Line( + self._opcode_predicate_helper_impl( + inst_enc, + 'has_encoded_sdwa', + encoded_sdwa_opcodes, + 'inst_.src0 == amdgpu::SRC_SDWA', + ) + ) + ) extension_word_capacity = self._encoding_extension_word_capacity(inst_enc) owns_extension_words = extension_word_capacity > 0 + literal32_size_condition = size_condition + compact_modifier_encoding = has_real_default_check and ( + owns_dpp_extension or supports_sdwa_extension + ) + if compact_modifier_encoding: + compact_extension_conditions = [ + *dpp_extension_conditions, + *([encoded_sdwa_condition] if encoded_sdwa_condition else []), + *([literal32_condition] if literal32_condition else []), + ] + if ( + inst_enc.has_implied_literal_ops + and not inst_enc.has_variable_implied_literal_size + ): + compact_extension_conditions.append('hasImpliedLiteral()') + literal32_size_condition = ( + ' || '.join(compact_extension_conditions) or None + ) + elif not owns_dpp_extension and literal32_condition: + literal32_size_condition = literal32_condition + if ( + inst_enc.has_implied_literal_ops + and not inst_enc.has_variable_implied_literal_size + ): + literal32_size_condition += ' || hasImpliedLiteral()' + elif literal32_size_condition is None: + literal32_size_condition = literal32_condition or None extension_size_line = '' - if literal64_condition and size_condition is not None: + if literal64_condition and literal32_size_condition is not None: extension_size_line = ( f' if ({literal64_condition}) size_ += 2 * sizeof(MachineInst);' - f' else if ({size_condition}) size_ += sizeof(MachineInst);' + f' else if ({literal32_size_condition}) size_ += sizeof(MachineInst);' ) elif literal64_condition and literal32_condition: extension_size_line = ( @@ -2813,21 +2994,14 @@ def gen_encodings(self) -> None: extension_size_line = ( f' if ({literal64_condition}) size_ += 2 * sizeof(MachineInst);' ) - elif size_condition is not None: + elif literal32_size_condition is not None: extension_size_line = ( - f' if ({size_condition}) size_ += sizeof(MachineInst);' + f' if ({literal32_size_condition}) size_ += sizeof(MachineInst);' ) elif literal32_condition: extension_size_line = ( f' if ({literal32_condition}) size_ += sizeof(MachineInst);' ) - if extension_size_line and non_literal_selector_ops: - extension_guard = ' && '.join( - f'inst_.op != {opcode}' for opcode in non_literal_selector_ops - ) - extension_size_line = ( - f' if ({extension_guard}) {{' + extension_size_line + ' }' - ) if inst_enc.has_variable_implied_literal_size: size_line += ( ' if (hasImpliedLiteral()) size_ += impliedLiteralWordCount()' @@ -2887,25 +3061,30 @@ def gen_encodings(self) -> None: # that have modifier flags (memory instructions). This is # called lazily by disassemble() instead of eagerly in the # constructor, avoiding string allocation on the hot path. - if modifier_lines or dpp8_modifier_line: + # The modifier_lines were written for the constructor where + # they appended to modifiers_ and accessed inst->field. + # Rewrite to append to 'out' and access via local pointer. + modifier_impl = ( + modifier_lines.replace('modifiers_', 'out') + dpp8_modifier_line + ) + modifier_prologue = ( + ' auto *inst = &inst_;\n (void)inst;\n' + if 'inst->' in modifier_impl + else '' + ) + modifier_tail = ( + f'{modifier_prologue} {modifier_impl}\n' if modifier_impl else '' + ) + if modifier_impl and not supports_sdwa_extension: public_members.append( cgen.Line('void build_modifiers(std::string &out) const override;'), ) - # The modifier_lines were written for the constructor where - # they appended to modifiers_ and accessed inst->field. - # Rewrite to append to 'out' and access via local pointer. - mod_impl = ( - modifier_lines.replace('modifiers_', 'out') + dpp8_modifier_line - ) - mod_prologue = ( - ' auto *inst = &inst_;(void)inst;' if modifier_lines else '' - ) class_func_impls.append( cgen.Line( f'void {inst_enc.fmt_enc_name}::build_modifiers' f'(std::string &out) const ' - f'{{{mod_prologue}' - f'{mod_impl}}}' + f'{{{modifier_prologue}' + f'{modifier_impl}}}' ) ) fmt_enc_name = inst_enc.fmt_enc_name @@ -2948,6 +3127,59 @@ def gen_encodings(self) -> None: ) ) + if supports_sdwa_extension: + public_members.append( + cgen.Line( + 'void append_src_operand(std::string &out, ' + 'uint8_t operand_index) const override;' + ) + ) + public_members.append( + cgen.Line('void build_modifiers(std::string &out) const override;') + ) + class_func_impls.append( + cgen.Line( + f'void {fmt_enc_name}::append_src_operand(' + 'std::string &out, uint8_t operand_index) const {\n' + ' const Operand *operand = src_operands_[operand_index];\n' + ' if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) {\n' + ' amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_,\n' + ' sdwa_src0_sext_, sdwa_src0_neg_, sdwa_src0_abs_);\n' + ' return;\n' + ' }\n' + ' if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) {\n' + ' amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_,\n' + ' sdwa_src1_sext_, sdwa_src1_neg_, sdwa_src1_abs_);\n' + ' return;\n' + ' }\n' + ' Instruction::append_src_operand(out, operand_index);\n' + '}' + ) + ) + if enc_upper == 'ENC_VOPC': + class_func_impls.append( + cgen.Line( + f'void {fmt_enc_name}::build_modifiers(std::string &out) const {{\n' + ' if (inst_.src0 == amdgpu::SRC_SDWA)\n' + ' amdgpu::sdwa::append_source_attributes(\n' + ' out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_);\n' + f'{modifier_tail}' + '}' + ) + ) + else: + class_func_impls.append( + cgen.Line( + f'void {fmt_enc_name}::build_modifiers(std::string &out) const {{\n' + ' if (inst_.src0 == amdgpu::SRC_SDWA)\n' + ' amdgpu::sdwa::append_destination_attributes(\n' + ' out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, sdwa_dst_unused_,\n' + ' sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_);\n' + f'{modifier_tail}' + '}' + ) + ) + if fmt_enc_name not in cond_emitted: cond_emitted.add(fmt_enc_name) seen_conds: set[str] = set() @@ -3089,6 +3321,25 @@ def gen_encodings(self) -> None: class_members.append(cgen.Statement('bool sdwa_src1_sext_ = false')) class_members.append(cgen.Statement('bool sdwa_src1_neg_ = false')) class_members.append(cgen.Statement('bool sdwa_src1_abs_ = false')) + if supports_sdwa_extension: + class_members.append( + cgen.Statement('const Operand *sdwa_src0_operand_ = nullptr') + ) + class_members.append( + cgen.Statement('const Operand *sdwa_src1_operand_ = nullptr') + ) + class_members.append( + cgen.Statement( + 'amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = ' + 'amdgpu::sdwa::SourceModifierFormat::NONE' + ) + ) + class_members.append( + cgen.Statement( + 'amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = ' + 'amdgpu::sdwa::SourceModifierFormat::NONE' + ) + ) if inst_enc.enc_name.upper() != 'ENC_VOPC': class_members.append( cgen.Statement('uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD') @@ -3097,6 +3348,8 @@ def gen_encodings(self) -> None: cgen.Statement('uint32_t sdwa_dst_unused_ = 0') ) class_members.append(cgen.Statement('bool sdwa_clamp_ = false')) + if supports_sdwa_extension: + class_members.append(cgen.Statement('uint32_t sdwa_omod_ = 0')) else: class_members.append(cgen.Statement('uint32_t sdwa_sdst_ = 106')) class_members.append(cgen.Statement('bool sdwa_sd_ = false')) @@ -3188,6 +3441,13 @@ def gen_encodings(self) -> None: ('cstring', True), ('string', True), ] + if any( + self._supports_sdwa_for_encoding(enc.enc_name) + for enc in self.isa_spec.inst_encodings + ): + _enc_cpp_includes.insert( + 1, ('rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h', False) + ) if needs_invalid_inst_include or ( self._supports_simm64_literal_operands() and any( @@ -3648,26 +3908,6 @@ def _is_cdna_mfma_f8f6f4_vop3px2_suffix(self, inst: Instruction) -> bool: and inst.name in self.isa_spec.profile.inst_size_overrides ) - @staticmethod - def _emit_cdna_mfma_f8f6f4_vop3px2_decoder_helpers() -> str: - return textwrap.dedent('''\ - namespace { - - bool isMfmaScaleF8f6f4Vop3px2(const MachineInst *opcode) { - constexpr uint32_t VOP3P_MFMA_ENC = 423; - constexpr uint32_t PREFIX_OP = 44; - auto enc0 = (opcode[0] >> 23) & 0x1FFu; - auto op0 = (opcode[0] >> 16) & 0x7Fu; - if (enc0 != VOP3P_MFMA_ENC || op0 != PREFIX_OP) - return false; - auto enc2 = (opcode[2] >> 23) & 0x1FFu; - auto op2 = (opcode[2] >> 16) & 0x7Fu; - return enc2 == VOP3P_MFMA_ENC && (op2 == 45 || op2 == 46); - } - - } // namespace - ''') - def _gfx1250_f8f6f4_wmma_shape( self, inst: Instruction ) -> tuple[int, int, int] | None: @@ -7406,6 +7646,7 @@ def gen_insts(self) -> None: if all_insts and not profile.is_alt_encoding(enc.enc_name): enc_field_names = {f.name for f in enc.ucode_fields} is_smem = enc.enc_name.upper() == 'ENC_SMEM' + supports_sdwa_extension = self._supports_sdwa_for_encoding(enc.enc_name) has_sem = self._enc_has_semantics(enc) # Check child encodings for semantics too. for child in child_encs.get(enc.enc_name, []): @@ -7901,6 +8142,19 @@ def gen_insts(self) -> None: 'reinterpret_cast(inst)->src0) ? ' f'"{dpp8_mnemonic}" : "{full_mnemonic}"' ) + if supports_sdwa_extension and self._instruction_supports_sdwa( + inst, enc.enc_name + ): + assert full_mnemonic.endswith('_e32'), ( + f'{inst.name}: compact SDWA mnemonic does not end in _e32: ' + f'{full_mnemonic}' + ) + sdwa_mnemonic = full_mnemonic[:-4] + '_sdwa' + mnemonic_expr = ( + 'reinterpret_cast(inst)->src0 ' + '== amdgpu::SRC_SDWA ? ' + f'"{sdwa_mnemonic}" : {mnemonic_expr}' + ) exec_fn_expr = f'make_exec_fn<{inst.fmt_name}>()' if profile.split_execution_sources: exec_fn_expr = self._split_execute_expr(inst.fmt_name) @@ -7981,6 +8235,7 @@ def gen_insts(self) -> None: } ) ctor_body_parts = list(opnd_body) + fieldless_caps_guards: dict[str, str] = {} # Guard fieldless def/use operands (pushed positionally) from # silently writing past the fixed-size operand arrays. The # capacities mirror instruction.h (see the class constants). @@ -8102,8 +8357,7 @@ def gen_insts(self) -> None: for opnd in inst.operands if opnd.name in _lit_fields and opnd.name in enc_field_names - and opnd.operand_type - not in ('OPR_SENDMSG', 'OPR_SENDMSG_RTN') + and opnd.operand_type in _LITERAL_CAPABLE_OPERAND_TYPES ] if ( _supports_simm32_literals @@ -8139,9 +8393,9 @@ def gen_insts(self) -> None: opnd.name in _lit_fields and opnd.name in enc_field_names ): - if opnd.operand_type in ( - 'OPR_SENDMSG', - 'OPR_SENDMSG_RTN', + if ( + opnd.operand_type + not in _LITERAL_CAPABLE_OPERAND_TYPES ): continue literal_operand_type = self._constructor_operand_type( @@ -8377,6 +8631,34 @@ def gen_insts(self) -> None: _sdwa_struct = 'VopcVopSdwaSdstEncMachineInst' else: _sdwa_struct = f'{_enc_base}VopSdwaMachineInst' + _sdwa_src0_format = ( + self._sdwa_source_modifier_format( + inst_sem, 0, opnd + ) + if inst_sem + else 'amdgpu::sdwa::SourceModifierFormat::NONE' + ) + _sdwa_src1_opnd = next( + ( + candidate + for candidate in inst.operands + if candidate.name == 'vsrc1' + ), + None, + ) + _sdwa_src1_binding = '' + if _sdwa_src1_opnd is not None: + _sdwa_src1_format = ( + self._sdwa_source_modifier_format( + inst_sem, 1, _sdwa_src1_opnd + ) + if inst_sem + else 'amdgpu::sdwa::SourceModifierFormat::NONE' + ) + _sdwa_src1_binding = ( + f' sdwa_src1_operand_ = &{_sdwa_src1_opnd.name};' + f' sdwa_src1_format_ = {_sdwa_src1_format};' + ) _sdwa_s1_code = '' if enc.enc_name.upper() in ( 'ENC_VOP2', @@ -8387,6 +8669,31 @@ def gen_insts(self) -> None: f' vsrc1 = Operand({opnd.size}, OperandType::OPR_SRC,' f' reinterpret_cast(inst)->vsrc1);' ) + _sdwa_dst_binding = '' + if enc.enc_name.upper() == 'ENC_VOPC': + _sdwa_dst_opnd = next( + ( + candidate + for candidate in inst.operands + if candidate.is_output + and candidate.fieldless + ), + None, + ) + if _sdwa_dst_opnd is None: + raise ValueError( + f'{inst.name}: SDWA VOPC lacks a ' + 'fieldless destination' + ) + _sdwa_dst_binding = ( + f' if (sw->sd) {_sdwa_dst_opnd.name} = ' + f'Operand({_sdwa_dst_opnd.size}, ' + 'OperandType::OPR_SREG, sw->sdst);' + ) + fieldless_caps_guards[_sdwa_dst_opnd.name] = ( + 'reinterpret_cast' + '(inst)->src0 == amdgpu::SRC_SDWA' + ) ctor_body_parts.append( f'if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) {{' f' auto *sw = reinterpret_cast(inst);' @@ -8399,13 +8706,18 @@ def gen_insts(self) -> None: f' sdwa_src1_sext_ = sw->src1_sext;' f' sdwa_src1_neg_ = sw->src1_neg;' f' sdwa_src1_abs_ = sw->src1_abs;' + f' sdwa_src0_operand_ = &{opnd.name};' + f' sdwa_src0_format_ = {_sdwa_src0_format};' + f'{_sdwa_src1_binding}' + ( f' sdwa_sdst_ = sw->sdst;' f' sdwa_sd_ = sw->sd;' + f'{_sdwa_dst_binding}' if enc.enc_name.upper() == 'ENC_VOPC' else f' sdwa_dst_sel_ = sw->dst_sel;' f' sdwa_dst_unused_ = sw->dst_unused;' f' sdwa_clamp_ = sw->clamp;' + f' sdwa_omod_ = sw->omod;' ) + f'{_sdwa_s1_code}}}' ) @@ -8430,9 +8742,13 @@ def gen_insts(self) -> None: # call per fieldless operand regardless of any reassignment. for opnd in inst.operands: if opnd.fieldless: - ctor_body_parts.append( - self._fieldless_caps_stmt(opnd.name, opnd.operand_type) + caps_stmt = self._fieldless_caps_stmt( + opnd.name, opnd.operand_type ) + guard = fieldless_caps_guards.get(opnd.name) + if guard: + caps_stmt = f'if (!({guard})) {caps_stmt}' + ctor_body_parts.append(caps_stmt) ctor_body_parts.extend(vgpr_msb_role_body) @@ -10574,17 +10890,9 @@ def gen_operand_types(self) -> None: # in a generated .cpp anonymous namespace) so both the model operand.cpp # (Operand::const_value) and the execution operand.cpp can use it. imm_types = [ - t - for t in ( - 'OPR_SIMM4', - 'OPR_SIMM8', - 'OPR_SIMM16', - 'OPR_SIMM32', - 'OPR_SIMM64', - 'OPR_LABEL', - 'OPR_WAITCNT', - ) - if t in self.isa_spec.operand_types + operand_type + for operand_type in _IMMEDIATE_OPERAND_TYPES + if operand_type in self.isa_spec.operand_types ] if imm_types: fn = '[[nodiscard]] constexpr bool is_immediate_type(OperandType t) {' @@ -12222,20 +12530,6 @@ def gen_decoder(self) -> None: class_impl.append( cgen.Line(self._emit_gfx1250_scaled_wmma_vop3px2_decoder_helpers()) ) - if self._supports_cdna_mfma_f8f6f4_vop3px2(): - class_impl.append( - cgen.Line(self._emit_cdna_mfma_f8f6f4_vop3px2_decoder_helpers()) - ) - decode_body.append( - cgen.Line( - ' if (isMfmaScaleF8f6f4Vop3px2(opcode)) {\n' - ' auto op2 = (opcode[2] >> 16) & 0x7Fu;\n' - ' if (op2 == 45)\n' - ' return std::make_unique(opcode + 2, true);\n' - ' return std::make_unique(opcode + 2, true);\n' - ' }\n' - ) - ) decode_body.extend( [ cgen.Statement( @@ -12375,16 +12669,38 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: ) ): _dte.sub_decode_funcs[inst.opcode] = 'decodeInvalid' - _custom_decode_bodies[_pfx] = cgen.Block( - [ - cgen.Statement( - f'auto op = *reinterpret_cast(opcode + 2)' - ), - cgen.Statement( - f'return {_dte.sub_decode_table}[op.op](opcode + 2)' - ), - ] - ) + if self._supports_cdna_mfma_f8f6f4_vop3px2(): + _custom_decode_bodies[_pfx] = cgen.Block( + [ + cgen.Line( + ' const uint32_t suffix_encoding = ' + '(opcode[2] >> 23) & 0x1FFu;\n' + ' const uint32_t suffix_opcode = ' + '(opcode[2] >> 16) & 0x7Fu;\n' + ' if (suffix_encoding != encoding::kVop3pMfma ||\n' + ' (suffix_opcode != ' + 'kVMfmaF3216x16x128F8f6f4Vop3pMfma &&\n' + ' suffix_opcode != ' + 'kVMfmaF3232x32x64F8f6f4Vop3pMfma))\n' + ' return decodeInvalid(opcode);\n' + ' if (suffix_opcode == ' + 'kVMfmaF3216x16x128F8f6f4Vop3pMfma)\n' + ' return std::make_unique(opcode + 2, true);\n' + ' return std::make_unique(opcode + 2, true);\n' + ) + ] + ) + else: + _custom_decode_bodies[_pfx] = cgen.Block( + [ + cgen.Statement( + f'auto op = *reinterpret_cast(opcode + 2)' + ), + cgen.Statement( + f'return {_dte.sub_decode_table}[op.op](opcode + 2)' + ), + ] + ) break for _fn, _body in _custom_primary_decode_bodies.items(): _decl = cgen.FunctionDeclaration( @@ -12616,6 +12932,16 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: False, ), ] + if self._supports_cdna_mfma_f8f6f4_vop3px2(): + decoder_impl_includes.append( + ( + self.config.generated_include( + self.generated_dir_name, + 'opcodes.h', + ), + False, + ) + ) if self._supports_generated_vopd(): decoder_impl_includes.append( ( diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index 392002bbb62d..2272a4a06794 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -249,6 +249,12 @@ def _generated_constructor_body(cpp: str, class_name: str) -> str: return cpp[start:end] +def _generated_bool_method_body(cpp: str, class_name: str, method: str) -> str: + start = cpp.index(f'bool {class_name}::{method}() const') + end = cpp.index('\n\n', start) + return cpp[start:end] + + def _execution_source_path(path: Path, profile) -> Path: """Return the source containing execution bodies for a generated file.""" if not profile.split_execution_sources: @@ -2415,7 +2421,12 @@ def test_gfx1250_generated_literal_validation(gfx1250_generated_root: Path): vopd = (gfx1250_generated_root / 'vopd.cpp').read_text() sop1_encoding_ctor = _generated_constructor_body(encodings, 'Sop1') - assert 'inst_.op != 76 && inst_.op != 77' in sop1_encoding_ctor + assert 'has_encoded_literal32()' in sop1_encoding_ctor + sop1_literal_helper = _generated_bool_method_body( + encodings, 'Sop1', 'has_encoded_literal32' + ) + assert 'case 76:' not in sop1_literal_helper + assert 'case 77:' not in sop1_literal_helper barrier_ctor = _generated_constructor_body(sop1, 'SBarrierSignalSop1') assert 'LiteralSupport::None' in barrier_ctor @@ -2439,7 +2450,12 @@ def test_generated_sendmsg_return_selectors_are_not_literals( sop1 = (generated_root / 'sop1.cpp').read_text() sop1_encoding_ctor = _generated_constructor_body(encodings, 'Sop1') - assert 'inst_.op != 76 && inst_.op != 77' in sop1_encoding_ctor + assert 'has_encoded_literal32()' in sop1_encoding_ctor + sop1_literal_helper = _generated_bool_method_body( + encodings, 'Sop1', 'has_encoded_literal32' + ) + assert 'case 76:' not in sop1_literal_helper + assert 'case 77:' not in sop1_literal_helper for class_name in ('SSendmsgRtnB32Sop1', 'SSendmsgRtnB64Sop1'): sendmsg_ctor = _generated_constructor_body(sop1, class_name) @@ -2464,7 +2480,7 @@ def test_gfx1250_compact_literal_policy_precedes_extension_sizing( body = _generated_constructor_body(encodings_cpp, class_name) assert 'supports_literal(literal_support, LiteralSupport::Literal32)' in body assert 'supports_literal(literal_support, LiteralSupport::Literal64)' in body - assert body.index('supports_literal(') < body.index('if (has_lit64()') + assert body.index('supports_literal(') < body.index('has_encoded_literal64()') readfirstlane = _generated_constructor_body(vop1, 'VReadfirstlaneB32Vop1') assert 'LiteralSupport::None' in readfirstlane @@ -2492,6 +2508,8 @@ def test_generated_sdwa_uses_shared_source_staging( assert 'amdgpu::sdwa::stage_source(' in generated assert 'sdwa_src_select(' not in generated assert 'std::make_unique' not in generated + encodings = (amdgpu_generated_root / arch / 'encodings.cpp').read_text() + assert '#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h"' in encodings assert checked_sdwa_files > 0 @@ -2750,11 +2768,17 @@ def test_cdna4_generated_vop1_sdwa_availability_is_instruction_specific( amdgpu_generated_root: Path, ): vop1 = (amdgpu_generated_root / 'cdna4' / 'vop1.cpp').read_text() + encodings_h = (amdgpu_generated_root / 'cdna4' / 'encodings.h').read_text() supported = _generated_constructor_body(vop1, 'VMovB32Vop1') unsupported = _generated_constructor_body(vop1, 'VCvtF64I32Vop1') assert 'reinterpret_cast' in supported + assert 'sdwa_mnemonic' not in vop1 + assert re.search(r'\? "v_floor_f32_sdwa"\s*: "v_floor_f32_e32"', vop1) + vop1_class = re.search(r'class Vop1\b.*?\n};', encodings_h, flags=re.DOTALL) + assert vop1_class is not None + assert 'owned_mnemonic_' not in vop1_class.group() assert 'V_MOV_B32 does not support SDWA' not in supported assert ( 'throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", "");' @@ -3498,6 +3522,22 @@ def generator_for( ) +def test_cdna4_vop3px2_prefix_decoder_validates_suffix(cdna4_generated_root: Path): + decoder = (cdna4_generated_root / 'decoder.cpp').read_text() + decode_body = decoder.split( + 'std::unique_ptr Decoder::decode(const MachineInst *opcode) {' + )[1].split('std::unique_ptr Decoder::decodeInvalid', 1)[0] + + assert 'isMfmaScaleF8f6f4Vop3px2' not in decode_body + assert 'suffix_encoding != encoding::kVop3pMfma' in decoder + assert 'kVMfmaF3216x16x128F8f6f4Vop3pMfma' in decoder + assert 'kVMfmaF3232x32x64F8f6f4Vop3pMfma' in decoder + assert 'return decodeInvalid(opcode);' in decoder + assert 'VMfmaF3216x16x128F8f6f4Vop3pMfma>(opcode + 2, true)' in decoder + assert 'VMfmaF3232x32x64F8f6f4Vop3pMfma>(opcode + 2, true)' in decoder + assert '#include "rocjitsu/isa/arch/amdgpu/generated/cdna4/opcodes.h"' in decoder + + @pytest.mark.parametrize( ('arch_name', 'expected_vopd_indices'), [ @@ -3581,7 +3621,7 @@ def test_gfx1250_scaled_wmma_skips_vop3p_extension_decode( assert not constructor_suffix.strip() for extension_step in ( 'throw util::InvalidInst("Vop3p does not support Literal64", "")', - 'has_lit_0()', + 'has_encoded_literal32()', 'inst_.src0 == amdgpu::SRC_DPP', 'amdgpu::dpp::is_src_dpp8(inst_.src0)', 'std::memcpy(raw_words_.data(), inst, size_)', diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py index 3d32e3b1f5a1..48392e06e613 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py @@ -175,6 +175,63 @@ def test_literal_fixups_require_generated_machine_inst_struct(): assert not codegen._has_machine_inst_struct(info[0]) +def test_literal_extension_fields_follow_each_opcodes_operands(): + enc = _enc('ENC_VOP3P') + enc.insts = [ + Instruction( + 'V_PK_ADD_I16', + 'ENC_VOP3P', + opcode=2, + operands=[ + _operand('src0', 'OPR_SRC'), + _operand('src1', 'OPR_SRC'), + ], + ), + Instruction('V_NOP', 'ENC_VOP3P', opcode=384, operands=[]), + ] + + masks = CodeGenerator._encoded_literal_field_masks(enc, ('src0', 'src1', 'src2')) + + assert masks == {2: ('src0', 'src1'), 384: ()} + + +def test_only_literal_capable_operand_fields_select_extension_words(): + enc = _enc('ENC_SOPC') + enc.insts = [ + Instruction( + 'S_SET_GPR_IDX_ON', + 'ENC_SOPC', + opcode=17, + operands=[ + _operand('ssrc0', 'OPR_SSRC'), + _operand('ssrc1', 'OPR_SIMM4'), + ], + ), + Instruction( + 'S_CBRANCH_G_FORK', + 'ENC_SOPC', + opcode=18, + operands=[ + _operand('ssrc0', 'OPR_SSRC_NOLIT'), + _operand('ssrc1', 'OPR_SRC_NOLIT'), + ], + ), + Instruction( + 'V_READFIRSTLANE_B32', + 'ENC_SOPC', + opcode=19, + operands=[_operand('ssrc0', 'OPR_VGPR')], + ), + ] + + masks = CodeGenerator._encoded_literal_field_masks(enc, ('ssrc0', 'ssrc1')) + helper = CodeGenerator._encoded_literal_helper_impl(enc, ('ssrc0', 'ssrc1'), 255) + + assert masks == {17: ('ssrc0',), 18: (), 19: ()} + assert 'inst_.ssrc0 == 255' in helper + assert 'inst_.ssrc1 == 255' not in helper + + def test_simm32_literal_operand_is_initialized_from_extension_word(): stmt = CodeGenerator._literal_operand_fixup_stmt( _literal_operand(32, 'OPR_SIMM32'), 'Sop2InstLiteralMachineInst' diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.cpp index e0d180a01a06..b0194f3eb61b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include #include @@ -22,13 +23,68 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 44: + case 45: + case 48: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -38,13 +94,42 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 17: + return inst_.ssrc0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 18: + case 19: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -88,13 +173,73 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 20; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -127,13 +272,160 @@ void Smem::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 55: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 77: + case 78: + case 79: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop1::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 39: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 51: + case 52: + case 55: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 77: + case 78: + case 79: + return true; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -153,6 +445,28 @@ void Vop1::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop1::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop1::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop1::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -163,18 +477,386 @@ bool Vop1::has_dpp() { return inst_.src0 == 250; } bool Vop1::has_sdwa() { return inst_.src0 == 249; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + case 112: + case 113: + case 114: + case 115: + case 116: + case 117: + case 118: + case 119: + case 120: + case 121: + case 122: + case 123: + case 124: + case 125: + case 126: + case 127: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vopc::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 16: + case 17: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + return true; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } +void Vopc::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vopc::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_source_attributes(out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vopc::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -183,13 +865,144 @@ bool Vopc::has_lit() { return inst_.src0 == 255; } bool Vopc::has_sdwa() { return inst_.src0 == 249; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop2::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 61: + return true; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32() || + hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -211,6 +1024,28 @@ void Vop2::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop2::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop2::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop2::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h index f44533895827..4145a044fea6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h @@ -419,6 +419,7 @@ inline constexpr uint16_t kVop3pMfma = 423; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -429,6 +430,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -460,6 +462,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -480,7 +483,11 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -503,14 +510,23 @@ class Vop1 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_sdwa(); @@ -532,6 +548,10 @@ class Vopc : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_sdst_ = 106; bool sdwa_sd_ = false; }; @@ -539,7 +559,11 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -564,9 +588,14 @@ class Vop2 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vintrp : public IsaInstruction { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp index 8f54fbcf42d0..8ff4eac337d3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp @@ -503,10 +503,6 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->ssrc1 == 255) - ssrc1 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); m0.apply_fieldless_caps(false, false, false); m0_in.apply_fieldless_caps(false, false, false); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp index 33d641e3c8be..a86069d40195 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace cdna1 { VNopVop1::VNopVop1(const MachineInst *inst) - : Vop1("v_nop_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNopVop1)) { num_src_ = 0; num_dst_ = 0; @@ -27,7 +29,9 @@ std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { } // namespace detail VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) - : Vop1("v_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMovB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -58,9 +62,12 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -143,7 +150,10 @@ std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32I32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -174,9 +184,12 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -187,7 +200,10 @@ std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32U32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -218,9 +234,12 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -231,7 +250,10 @@ std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { } // namespace detail VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_u32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -262,9 +284,12 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -275,7 +300,10 @@ std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -306,9 +334,12 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -319,7 +350,10 @@ std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16F32Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -350,9 +384,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -369,7 +406,10 @@ void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32F16Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -401,9 +441,12 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -414,7 +457,10 @@ std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { } // namespace detail VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_rpi_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtRpiI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -445,9 +491,12 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -458,7 +507,10 @@ std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_flr_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtFlrI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -489,9 +541,12 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -502,7 +557,10 @@ std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) - : Vop1("v_cvt_off_f32_i4_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtOffF32I4Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -533,9 +591,12 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -597,7 +658,10 @@ std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte0_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte0Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -628,9 +692,12 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -641,7 +708,10 @@ std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte1_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte1Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -672,9 +742,12 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -685,7 +758,10 @@ std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte2_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte2Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -716,9 +792,12 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -729,7 +808,10 @@ std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte3_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte3Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -760,9 +842,12 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -928,7 +1013,9 @@ std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { } // namespace detail VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) - : Vop1("v_fract_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -959,9 +1046,12 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -972,7 +1062,9 @@ std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { } // namespace detail VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) - : Vop1("v_trunc_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1003,9 +1095,12 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1016,7 +1111,9 @@ std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { } // namespace detail VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) - : Vop1("v_ceil_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1047,9 +1144,12 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1060,7 +1160,9 @@ std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { } // namespace detail VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) - : Vop1("v_rndne_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1091,9 +1193,12 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1104,7 +1209,9 @@ std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { } // namespace detail VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) - : Vop1("v_floor_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1135,9 +1242,12 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1148,7 +1258,9 @@ std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { } // namespace detail VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) - : Vop1("v_exp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1179,9 +1291,12 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1192,7 +1307,9 @@ std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { } // namespace detail VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) - : Vop1("v_log_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1223,9 +1340,12 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1236,7 +1356,9 @@ std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1267,9 +1389,12 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1280,7 +1405,10 @@ std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_iflag_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpIflagF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1311,9 +1439,12 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1324,7 +1455,9 @@ std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { } // namespace detail VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) - : Vop1("v_rsq_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1355,9 +1488,12 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1420,7 +1556,9 @@ std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { } // namespace detail VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1451,9 +1589,12 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1490,7 +1631,9 @@ std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { } // namespace detail VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) - : Vop1("v_sin_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1521,9 +1664,12 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1534,7 +1680,9 @@ std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { } // namespace detail VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) - : Vop1("v_cos_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1565,9 +1713,12 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1578,7 +1729,9 @@ std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { } // namespace detail VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) - : Vop1("v_not_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNotB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1609,9 +1762,12 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1622,7 +1778,9 @@ std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { } // namespace detail VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) - : Vop1("v_bfrev_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VBfrevB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1653,9 +1811,12 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1666,7 +1827,9 @@ std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhU32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1697,9 +1860,12 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1710,7 +1876,9 @@ std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { } // namespace detail VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) - : Vop1("v_ffbl_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfblB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1741,9 +1909,12 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1754,7 +1925,9 @@ std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhI32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1785,9 +1958,12 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1876,7 +2052,10 @@ std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { } // namespace detail VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1907,9 +2086,12 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1920,7 +2102,10 @@ std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode } // namespace detail VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1951,9 +2136,12 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1977,7 +2165,10 @@ std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { } // namespace detail VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) - : Vop1("v_screen_partition_4se_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VScreenPartition4seB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2008,9 +2199,12 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2021,7 +2215,10 @@ std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst } // namespace detail VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_u16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16U16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2053,9 +2250,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2072,7 +2272,10 @@ void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2104,9 +2307,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2123,7 +2329,10 @@ void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2155,9 +2364,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2174,7 +2386,10 @@ void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2206,9 +2421,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2225,7 +2443,9 @@ void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) - : Vop1("v_rcp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2257,9 +2477,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2276,7 +2499,9 @@ void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { } VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2308,9 +2533,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2327,7 +2555,9 @@ void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { } VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) - : Vop1("v_rsq_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2359,9 +2589,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2378,7 +2611,9 @@ void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { } VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) - : Vop1("v_log_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2410,9 +2645,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2429,7 +2667,9 @@ void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) - : Vop1("v_exp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2461,9 +2701,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2480,7 +2723,10 @@ void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2512,9 +2758,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2531,7 +2780,10 @@ void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2563,9 +2815,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2582,7 +2837,9 @@ void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) - : Vop1("v_floor_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2614,9 +2871,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2633,7 +2893,9 @@ void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { } VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) - : Vop1("v_ceil_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2665,9 +2927,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2684,7 +2949,9 @@ void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { } VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) - : Vop1("v_trunc_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2716,9 +2983,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2735,7 +3005,9 @@ void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { } VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) - : Vop1("v_rndne_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2767,9 +3039,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2786,7 +3061,9 @@ void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { } VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) - : Vop1("v_fract_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2818,9 +3095,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2837,7 +3117,9 @@ void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { } VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) - : Vop1("v_sin_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2869,9 +3151,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2888,7 +3173,9 @@ void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { } VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) - : Vop1("v_cos_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2920,9 +3207,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2939,7 +3229,10 @@ void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2971,9 +3264,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2990,7 +3286,10 @@ void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3022,9 +3321,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3041,7 +3343,10 @@ void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) - : Vop1("v_sat_pk_u8_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSatPkU8I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3072,9 +3377,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp index e3c8f843b7d1..c336319fe86e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna1 { VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) - : Vop2("v_cndmask_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCndmaskB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -49,9 +52,14 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -65,7 +73,9 @@ std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { } // namespace detail VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) - : Vop2("v_add_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -98,9 +108,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -113,7 +128,9 @@ std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { } // namespace detail VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) - : Vop2("v_sub_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -146,9 +163,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -161,7 +183,10 @@ std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) - : Vop2("v_subrev_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -194,9 +219,14 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -209,7 +239,10 @@ std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { } // namespace detail VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) - : Vop2("v_mul_legacy_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_legacy_f32_sdwa" + : "v_mul_legacy_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulLegacyF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -242,9 +275,14 @@ VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -257,7 +295,9 @@ std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode) } // namespace detail VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) - : Vop2("v_mul_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -290,9 +330,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -305,7 +350,10 @@ std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { } // namespace detail VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -338,9 +386,14 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -353,7 +406,10 @@ std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -386,9 +442,14 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -401,7 +462,10 @@ std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -434,9 +498,14 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -449,7 +518,10 @@ std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -482,9 +554,14 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -497,7 +574,9 @@ std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) - : Vop2("v_min_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -530,9 +609,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -545,7 +629,9 @@ std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { } // namespace detail VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) - : Vop2("v_max_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -578,9 +664,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -593,7 +684,9 @@ std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { } // namespace detail VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) - : Vop2("v_min_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -626,9 +719,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -641,7 +739,9 @@ std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { } // namespace detail VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) - : Vop2("v_max_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -674,9 +774,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -689,7 +794,9 @@ std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { } // namespace detail VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) - : Vop2("v_min_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -722,9 +829,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -737,7 +849,9 @@ std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { } // namespace detail VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) - : Vop2("v_max_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -770,9 +884,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -785,7 +904,10 @@ std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { } // namespace detail VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -818,9 +940,14 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -833,7 +960,10 @@ std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -866,9 +996,14 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -881,7 +1016,10 @@ std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { } // namespace detail VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -914,9 +1052,14 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -929,7 +1072,9 @@ std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) - : Vop2("v_and_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAndB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -962,9 +1107,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -977,7 +1127,9 @@ std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { } // namespace detail VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) - : Vop2("v_or_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VOrB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1010,9 +1162,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1025,7 +1182,9 @@ std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { } // namespace detail VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) - : Vop2("v_xor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1058,9 +1217,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1171,7 +1335,10 @@ std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode) { } // namespace detail VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) - : Vop2("v_add_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1206,9 +1373,14 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1222,7 +1394,10 @@ std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) - : Vop2("v_sub_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1257,9 +1432,14 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1273,7 +1453,10 @@ std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1308,9 +1491,14 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1324,7 +1512,10 @@ std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { } // namespace detail VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) - : Vop2("v_addc_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddcCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1361,9 +1552,14 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1378,7 +1574,10 @@ std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) - : Vop2("v_subb_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1415,9 +1614,14 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1432,7 +1636,10 @@ std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subbrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1469,9 +1676,14 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1486,7 +1698,9 @@ std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) } // namespace detail VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) - : Vop2("v_add_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1520,9 +1734,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1541,7 +1760,9 @@ void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) - : Vop2("v_sub_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1575,9 +1796,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1596,7 +1822,10 @@ void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) - : Vop2("v_subrev_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1630,9 +1859,14 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1651,7 +1885,9 @@ void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { } VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) - : Vop2("v_mul_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1685,9 +1921,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1827,7 +2068,9 @@ void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) - : Vop2("v_add_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1861,9 +2104,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1882,7 +2130,9 @@ void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) - : Vop2("v_sub_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1916,9 +2166,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1937,7 +2192,10 @@ void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) - : Vop2("v_subrev_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1971,9 +2229,14 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1992,7 +2255,10 @@ void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { } VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) - : Vop2("v_mul_lo_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulLoU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2026,9 +2292,14 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2047,7 +2318,10 @@ void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { } VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2081,9 +2355,14 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2102,7 +2381,10 @@ void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2136,9 +2418,14 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2157,7 +2444,10 @@ void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2191,9 +2481,14 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2212,7 +2507,9 @@ void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) - : Vop2("v_max_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2246,9 +2543,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2267,7 +2569,9 @@ void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { } VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) - : Vop2("v_min_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2301,9 +2605,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2322,7 +2631,9 @@ void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) - : Vop2("v_max_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2356,9 +2667,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2377,7 +2693,9 @@ void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) - : Vop2("v_max_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2411,9 +2729,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2432,7 +2755,9 @@ void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { } VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) - : Vop2("v_min_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2466,9 +2791,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2487,7 +2817,9 @@ void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { } VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) - : Vop2("v_min_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2521,9 +2853,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2542,7 +2879,9 @@ void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { } VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) - : Vop2("v_ldexp_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLdexpF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2576,9 +2915,14 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2597,7 +2941,9 @@ void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) - : Vop2("v_add_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2630,9 +2976,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2645,7 +2996,9 @@ std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { } // namespace detail VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) - : Vop2("v_sub_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2678,9 +3031,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2693,7 +3051,10 @@ std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2726,9 +3087,14 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2945,7 +3311,9 @@ std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { } // namespace detail VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) - : Vop2("v_xnor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXnorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2978,9 +3346,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp index 1a14ca028c9d..e756ef009eea 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna1 { VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -41,12 +44,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -56,7 +66,10 @@ std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -85,12 +98,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -164,7 +184,10 @@ std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) } // namespace detail VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -192,12 +215,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -207,7 +237,10 @@ std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -237,12 +270,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -254,7 +294,9 @@ std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) } // namespace detail VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -282,12 +324,19 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -297,7 +346,10 @@ std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,12 +377,19 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -340,7 +399,10 @@ std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -368,12 +430,19 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -383,7 +452,10 @@ std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -411,12 +483,19 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -426,7 +505,10 @@ std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -454,12 +536,19 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -469,7 +558,10 @@ std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -497,12 +589,19 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -512,7 +611,10 @@ std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -540,12 +642,19 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -555,7 +664,9 @@ std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -583,12 +694,19 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -598,7 +716,9 @@ std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -626,12 +746,19 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -641,7 +768,10 @@ std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -669,12 +799,19 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -684,7 +821,10 @@ std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -712,12 +852,19 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -727,7 +874,10 @@ std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -755,12 +905,19 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -770,7 +927,10 @@ std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -798,12 +958,19 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -813,7 +980,10 @@ std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -841,12 +1011,19 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -856,7 +1033,10 @@ std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -884,12 +1064,19 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -899,7 +1086,10 @@ std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -927,12 +1117,19 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -942,7 +1139,10 @@ std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -972,12 +1172,19 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -989,7 +1196,10 @@ std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1019,12 +1229,19 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1036,7 +1253,10 @@ std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1066,12 +1286,19 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1083,7 +1310,10 @@ std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1113,12 +1343,19 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1130,7 +1367,10 @@ std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1160,12 +1400,19 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1177,7 +1424,10 @@ std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1207,12 +1457,19 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1224,7 +1481,10 @@ std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1254,12 +1514,19 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1271,7 +1538,10 @@ std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1301,12 +1571,19 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1318,7 +1595,10 @@ std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1348,12 +1628,19 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1365,7 +1652,10 @@ std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1395,12 +1685,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1412,7 +1709,10 @@ std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1442,12 +1742,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1459,7 +1766,10 @@ std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1489,12 +1799,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1506,7 +1823,10 @@ std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1536,12 +1856,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1553,7 +1880,10 @@ std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1583,12 +1913,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1600,7 +1937,10 @@ std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1630,12 +1970,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1647,7 +1994,10 @@ std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1677,12 +2027,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1694,7 +2051,9 @@ std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1721,12 +2080,19 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1736,7 +2102,10 @@ std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1763,12 +2132,19 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1778,7 +2154,10 @@ std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1805,12 +2184,19 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1820,7 +2206,10 @@ std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1847,12 +2236,19 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1862,7 +2258,10 @@ std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1889,12 +2288,19 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1904,7 +2310,10 @@ std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1931,12 +2340,19 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1946,7 +2362,10 @@ std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1973,12 +2392,19 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1988,7 +2414,9 @@ std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2015,12 +2443,19 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2030,7 +2465,9 @@ std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2057,12 +2494,19 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2072,7 +2516,10 @@ std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2099,12 +2546,19 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2114,7 +2568,10 @@ std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2141,12 +2598,19 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2156,7 +2620,10 @@ std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2183,12 +2650,19 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2198,7 +2672,10 @@ std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2225,12 +2702,19 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2240,7 +2724,10 @@ std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2267,12 +2754,19 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2282,7 +2776,10 @@ std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2309,12 +2806,19 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2324,7 +2828,10 @@ std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2351,12 +2858,19 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2366,7 +2880,10 @@ std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2395,12 +2912,19 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2412,7 +2936,10 @@ std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2441,12 +2968,19 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2458,7 +2992,10 @@ std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2487,12 +3024,19 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2504,7 +3048,10 @@ std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2533,12 +3080,19 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2550,7 +3104,10 @@ std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2579,12 +3136,19 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2596,7 +3160,10 @@ std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2625,12 +3192,19 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2642,7 +3216,10 @@ std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2671,12 +3248,19 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2688,7 +3272,10 @@ std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2717,12 +3304,19 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2734,7 +3328,10 @@ std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2763,12 +3360,19 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2780,7 +3384,10 @@ std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2809,12 +3416,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2826,7 +3440,10 @@ std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2855,12 +3472,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2872,7 +3496,10 @@ std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2901,12 +3528,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2918,7 +3552,10 @@ std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2947,12 +3584,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2964,7 +3608,10 @@ std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2993,12 +3640,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3010,7 +3664,10 @@ std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3039,12 +3696,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3056,7 +3720,10 @@ std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3085,12 +3752,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4094,7 +4768,9 @@ std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4122,12 +4798,19 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4137,7 +4820,10 @@ std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4165,12 +4851,19 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4180,7 +4873,10 @@ std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4208,12 +4904,19 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4223,7 +4926,10 @@ std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4251,12 +4957,19 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4266,7 +4979,10 @@ std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4294,12 +5010,19 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4309,7 +5032,10 @@ std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4337,12 +5063,19 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4352,7 +5085,10 @@ std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4380,12 +5116,19 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4395,7 +5138,9 @@ std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4423,12 +5168,19 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4438,7 +5190,9 @@ std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4466,12 +5220,19 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4481,7 +5242,10 @@ std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4509,12 +5273,19 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4524,7 +5295,10 @@ std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4552,12 +5326,19 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4567,7 +5348,10 @@ std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4595,12 +5379,19 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4610,7 +5401,10 @@ std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4638,12 +5432,19 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4653,7 +5454,10 @@ std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4681,12 +5485,19 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4696,7 +5507,10 @@ std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4724,12 +5538,19 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4739,7 +5560,9 @@ std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4767,12 +5590,19 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4782,7 +5612,10 @@ std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4812,12 +5645,19 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4829,7 +5669,10 @@ std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4859,12 +5702,19 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4876,7 +5726,10 @@ std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4906,12 +5759,19 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4923,7 +5783,10 @@ std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4953,12 +5816,19 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4970,7 +5840,10 @@ std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5000,12 +5873,19 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5017,7 +5897,10 @@ std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5047,12 +5930,19 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5064,7 +5954,10 @@ std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5094,12 +5987,19 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5111,7 +6011,10 @@ std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5141,12 +6044,19 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5158,7 +6068,10 @@ std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5188,12 +6101,19 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5205,7 +6125,10 @@ std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5235,12 +6158,19 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5252,7 +6182,10 @@ std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5282,12 +6215,19 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5299,7 +6239,10 @@ std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5329,12 +6272,19 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5346,7 +6296,10 @@ std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5376,12 +6329,19 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5393,7 +6353,10 @@ std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5423,12 +6386,19 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5440,7 +6410,10 @@ std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5470,12 +6443,19 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5487,7 +6467,10 @@ std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5517,12 +6500,19 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5534,7 +6524,9 @@ std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5561,12 +6553,19 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5576,7 +6575,10 @@ std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5603,12 +6605,19 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5618,7 +6627,10 @@ std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5645,12 +6657,19 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5660,7 +6679,10 @@ std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5687,12 +6709,19 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5702,7 +6731,10 @@ std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5729,12 +6761,19 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5744,7 +6783,10 @@ std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5771,12 +6813,19 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5786,7 +6835,10 @@ std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5813,12 +6865,19 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5828,7 +6887,9 @@ std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5855,12 +6916,19 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5870,7 +6938,9 @@ std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5897,12 +6967,19 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5912,7 +6989,10 @@ std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5939,12 +7019,19 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5954,7 +7041,10 @@ std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5981,12 +7071,19 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5996,7 +7093,10 @@ std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6023,12 +7123,19 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6038,7 +7145,10 @@ std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6065,12 +7175,19 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6080,7 +7197,10 @@ std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6107,12 +7227,19 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6122,7 +7249,10 @@ std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6149,12 +7279,19 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6164,7 +7301,9 @@ std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6191,12 +7330,19 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6206,7 +7352,10 @@ std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6235,12 +7384,19 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6252,7 +7408,10 @@ std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6281,12 +7440,19 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6298,7 +7464,10 @@ std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6327,12 +7496,19 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6344,7 +7520,10 @@ std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6373,12 +7552,19 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6390,7 +7576,10 @@ std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6419,12 +7608,19 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6436,7 +7632,10 @@ std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6465,12 +7664,19 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6482,7 +7688,10 @@ std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6511,12 +7720,19 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6528,7 +7744,10 @@ std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6557,12 +7776,19 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6574,7 +7800,10 @@ std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6603,12 +7832,19 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6620,7 +7856,10 @@ std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6649,12 +7888,19 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6666,7 +7912,10 @@ std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6695,12 +7944,19 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6712,7 +7968,10 @@ std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6741,12 +8000,19 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6758,7 +8024,10 @@ std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6787,12 +8056,19 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6804,7 +8080,10 @@ std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6833,12 +8112,19 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6850,7 +8136,10 @@ std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6879,12 +8168,19 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6896,7 +8192,10 @@ std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6925,12 +8224,19 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.cpp index 3e788d2514a4..f8b42a78f7a0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include #include @@ -22,13 +23,68 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 44: + case 45: + case 48: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -38,13 +94,42 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 17: + return inst_.ssrc0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 18: + case 19: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -88,13 +173,73 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 20; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -127,13 +272,161 @@ void Smem::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 55: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 77: + case 78: + case 79: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop1::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 39: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 51: + case 52: + case 55: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 77: + case 78: + case 79: + case 82: + return true; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -153,6 +446,28 @@ void Vop1::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop1::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop1::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop1::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -163,18 +478,386 @@ bool Vop1::has_dpp() { return inst_.src0 == 250; } bool Vop1::has_sdwa() { return inst_.src0 == 249; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + case 112: + case 113: + case 114: + case 115: + case 116: + case 117: + case 118: + case 119: + case 120: + case 121: + case 122: + case 123: + case 124: + case 125: + case 126: + case 127: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vopc::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 16: + case 17: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + return true; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } +void Vopc::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vopc::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_source_attributes(out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vopc::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -183,13 +866,143 @@ bool Vopc::has_lit() { return inst_.src0 == 255; } bool Vopc::has_sdwa() { return inst_.src0 == 249; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop2::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 61: + return true; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32() || + hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -211,6 +1024,28 @@ void Vop2::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop2::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop2::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop2::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h index ed7a5e3524e9..74abb93c8848 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h @@ -403,6 +403,7 @@ inline constexpr uint16_t kVop3pMfma = 423; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -413,6 +414,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -444,6 +446,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -464,7 +467,11 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -487,14 +494,23 @@ class Vop1 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_sdwa(); @@ -516,6 +532,10 @@ class Vopc : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_sdst_ = 106; bool sdwa_sd_ = false; }; @@ -523,7 +543,11 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -548,9 +572,14 @@ class Vop2 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vop3p : public IsaInstruction { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp index e94781c9edb7..01d9ab1b7243 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp @@ -503,10 +503,6 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->ssrc1 == 255) - ssrc1 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); m0.apply_fieldless_caps(false, false, false); m0_in.apply_fieldless_caps(false, false, false); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp index 9a5bc0ebb9d1..b170c2d495d3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace cdna2 { VNopVop1::VNopVop1(const MachineInst *inst) - : Vop1("v_nop_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNopVop1)) { num_src_ = 0; num_dst_ = 0; @@ -27,7 +29,9 @@ std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { } // namespace detail VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) - : Vop1("v_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMovB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -58,9 +62,12 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -155,7 +162,10 @@ std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32I32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -186,9 +196,12 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -199,7 +212,10 @@ std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32U32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -230,9 +246,12 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -243,7 +262,10 @@ std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { } // namespace detail VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_u32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -274,9 +296,12 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -287,7 +312,10 @@ std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -318,9 +346,12 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -331,7 +362,10 @@ std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16F32Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -362,9 +396,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -381,7 +418,10 @@ void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32F16Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -413,9 +453,12 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -426,7 +469,10 @@ std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { } // namespace detail VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_rpi_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtRpiI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -457,9 +503,12 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -470,7 +519,10 @@ std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_flr_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtFlrI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -501,9 +553,12 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -514,7 +569,10 @@ std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) - : Vop1("v_cvt_off_f32_i4_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtOffF32I4Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -545,9 +603,12 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -615,7 +676,10 @@ std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte0_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte0Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -646,9 +710,12 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -659,7 +726,10 @@ std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte1_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte1Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -690,9 +760,12 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -703,7 +776,10 @@ std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte2_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte2Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -734,9 +810,12 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -747,7 +826,10 @@ std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte3_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte3Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -778,9 +860,12 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -976,7 +1061,9 @@ std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { } // namespace detail VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) - : Vop1("v_fract_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1007,9 +1094,12 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1020,7 +1110,9 @@ std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { } // namespace detail VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) - : Vop1("v_trunc_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1051,9 +1143,12 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1064,7 +1159,9 @@ std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { } // namespace detail VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) - : Vop1("v_ceil_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1095,9 +1192,12 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1108,7 +1208,9 @@ std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { } // namespace detail VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) - : Vop1("v_rndne_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1139,9 +1241,12 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1152,7 +1257,9 @@ std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { } // namespace detail VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) - : Vop1("v_floor_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1183,9 +1290,12 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1196,7 +1306,9 @@ std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { } // namespace detail VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) - : Vop1("v_exp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1227,9 +1339,12 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1240,7 +1355,9 @@ std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { } // namespace detail VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) - : Vop1("v_log_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1271,9 +1388,12 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1284,7 +1404,9 @@ std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1315,9 +1437,12 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1328,7 +1453,10 @@ std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_iflag_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpIflagF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1359,9 +1487,12 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1372,7 +1503,9 @@ std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { } // namespace detail VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) - : Vop1("v_rsq_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1403,9 +1536,12 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1468,7 +1604,9 @@ std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { } // namespace detail VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1499,9 +1637,12 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1538,7 +1679,9 @@ std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { } // namespace detail VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) - : Vop1("v_sin_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1569,9 +1712,12 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1582,7 +1728,9 @@ std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { } // namespace detail VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) - : Vop1("v_cos_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1613,9 +1761,12 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1626,7 +1777,9 @@ std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { } // namespace detail VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) - : Vop1("v_not_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNotB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1657,9 +1810,12 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1670,7 +1826,9 @@ std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { } // namespace detail VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) - : Vop1("v_bfrev_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VBfrevB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1701,9 +1859,12 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1714,7 +1875,9 @@ std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhU32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1745,9 +1908,12 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1758,7 +1924,9 @@ std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { } // namespace detail VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) - : Vop1("v_ffbl_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfblB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1789,9 +1957,12 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1802,7 +1973,9 @@ std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhI32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1833,9 +2006,12 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1942,7 +2118,10 @@ std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { } // namespace detail VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1973,9 +2152,12 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1986,7 +2168,10 @@ std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode } // namespace detail VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2017,9 +2202,12 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2043,7 +2231,10 @@ std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { } // namespace detail VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) - : Vop1("v_screen_partition_4se_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VScreenPartition4seB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2074,9 +2265,12 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2087,7 +2281,10 @@ std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst } // namespace detail VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_u16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16U16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2119,9 +2316,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2138,7 +2338,10 @@ void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2170,9 +2373,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2189,7 +2395,10 @@ void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2221,9 +2430,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2240,7 +2452,10 @@ void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2272,9 +2487,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2291,7 +2509,9 @@ void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) - : Vop1("v_rcp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2323,9 +2543,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2342,7 +2565,9 @@ void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { } VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2374,9 +2599,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2393,7 +2621,9 @@ void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { } VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) - : Vop1("v_rsq_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2425,9 +2655,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2444,7 +2677,9 @@ void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { } VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) - : Vop1("v_log_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2476,9 +2711,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2495,7 +2733,9 @@ void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) - : Vop1("v_exp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2527,9 +2767,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2546,7 +2789,10 @@ void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2578,9 +2824,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2597,7 +2846,10 @@ void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2629,9 +2881,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2648,7 +2903,9 @@ void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) - : Vop1("v_floor_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2680,9 +2937,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2699,7 +2959,9 @@ void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { } VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) - : Vop1("v_ceil_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2731,9 +2993,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2750,7 +3015,9 @@ void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { } VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) - : Vop1("v_trunc_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2782,9 +3049,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2801,7 +3071,9 @@ void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { } VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) - : Vop1("v_rndne_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2833,9 +3105,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2852,7 +3127,9 @@ void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { } VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) - : Vop1("v_fract_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2884,9 +3161,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2903,7 +3183,9 @@ void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { } VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) - : Vop1("v_sin_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2935,9 +3217,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2954,7 +3239,9 @@ void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { } VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) - : Vop1("v_cos_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2986,9 +3273,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3005,7 +3295,10 @@ void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3037,9 +3330,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3056,7 +3352,10 @@ void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3088,9 +3387,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3107,7 +3409,10 @@ void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) - : Vop1("v_sat_pk_u8_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSatPkU8I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3138,9 +3443,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3180,7 +3488,10 @@ std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { } // namespace detail VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) - : Vop1("v_accvgpr_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_accvgpr_mov_b32_sdwa" + : "v_accvgpr_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAccvgprMovB32Vop1)), vdst(32, OperandType::OPR_ACCVGPR, (reinterpret_cast(inst)->vdst + OpSelAccvgpr::OPR_ACCVGPR_ACC_MIN)), @@ -3212,9 +3523,12 @@ VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } flags_ |= ACCVGPR; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp index c24de0051482..56b68001a52b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna2 { VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) - : Vop2("v_cndmask_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCndmaskB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -49,9 +52,14 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -65,7 +73,9 @@ std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { } // namespace detail VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) - : Vop2("v_add_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -98,9 +108,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -113,7 +128,9 @@ std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { } // namespace detail VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) - : Vop2("v_sub_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -146,9 +163,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -161,7 +183,10 @@ std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) - : Vop2("v_subrev_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -194,9 +219,14 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -244,7 +274,9 @@ std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { } // namespace detail VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) - : Vop2("v_mul_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -277,9 +309,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -292,7 +329,10 @@ std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { } // namespace detail VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,9 +365,14 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -340,7 +385,10 @@ std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -373,9 +421,14 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -388,7 +441,10 @@ std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -421,9 +477,14 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -436,7 +497,10 @@ std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -469,9 +533,14 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -484,7 +553,9 @@ std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) - : Vop2("v_min_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -517,9 +588,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -532,7 +608,9 @@ std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { } // namespace detail VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) - : Vop2("v_max_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -565,9 +643,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -580,7 +663,9 @@ std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { } // namespace detail VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) - : Vop2("v_min_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -613,9 +698,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -628,7 +718,9 @@ std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { } // namespace detail VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) - : Vop2("v_max_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -661,9 +753,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -676,7 +773,9 @@ std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { } // namespace detail VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) - : Vop2("v_min_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -709,9 +808,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -724,7 +828,9 @@ std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { } // namespace detail VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) - : Vop2("v_max_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -757,9 +863,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -772,7 +883,10 @@ std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { } // namespace detail VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -805,9 +919,14 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -820,7 +939,10 @@ std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -853,9 +975,14 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -868,7 +995,10 @@ std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { } // namespace detail VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -901,9 +1031,14 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -916,7 +1051,9 @@ std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) - : Vop2("v_and_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAndB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -949,9 +1086,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -964,7 +1106,9 @@ std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { } // namespace detail VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) - : Vop2("v_or_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VOrB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -997,9 +1141,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1012,7 +1161,9 @@ std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { } // namespace detail VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) - : Vop2("v_xor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1045,9 +1196,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1158,7 +1314,10 @@ std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode) { } // namespace detail VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) - : Vop2("v_add_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1193,9 +1352,14 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1209,7 +1373,10 @@ std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) - : Vop2("v_sub_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1244,9 +1411,14 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1260,7 +1432,10 @@ std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1295,9 +1470,14 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1311,7 +1491,10 @@ std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { } // namespace detail VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) - : Vop2("v_addc_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddcCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1348,9 +1531,14 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1365,7 +1553,10 @@ std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) - : Vop2("v_subb_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1402,9 +1593,14 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1419,7 +1615,10 @@ std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subbrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1456,9 +1655,14 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1473,7 +1677,9 @@ std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) } // namespace detail VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) - : Vop2("v_add_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1507,9 +1713,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1528,7 +1739,9 @@ void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) - : Vop2("v_sub_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1562,9 +1775,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1583,7 +1801,10 @@ void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) - : Vop2("v_subrev_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1617,9 +1838,14 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1638,7 +1864,9 @@ void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { } VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) - : Vop2("v_mul_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1672,9 +1900,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1814,7 +2047,9 @@ void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) - : Vop2("v_add_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1848,9 +2083,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1869,7 +2109,9 @@ void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) - : Vop2("v_sub_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1903,9 +2145,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1924,7 +2171,10 @@ void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) - : Vop2("v_subrev_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1958,9 +2208,14 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1979,7 +2234,10 @@ void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { } VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) - : Vop2("v_mul_lo_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulLoU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2013,9 +2271,14 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2034,7 +2297,10 @@ void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { } VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2068,9 +2334,14 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2089,7 +2360,10 @@ void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2123,9 +2397,14 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2144,7 +2423,10 @@ void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2178,9 +2460,14 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2199,7 +2486,9 @@ void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) - : Vop2("v_max_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2233,9 +2522,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2254,7 +2548,9 @@ void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { } VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) - : Vop2("v_min_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2288,9 +2584,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2309,7 +2610,9 @@ void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) - : Vop2("v_max_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2343,9 +2646,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2364,7 +2672,9 @@ void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) - : Vop2("v_max_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2398,9 +2708,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2419,7 +2734,9 @@ void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { } VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) - : Vop2("v_min_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2453,9 +2770,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2474,7 +2796,9 @@ void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { } VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) - : Vop2("v_min_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2508,9 +2832,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2529,7 +2858,9 @@ void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { } VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) - : Vop2("v_ldexp_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLdexpF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2563,9 +2894,14 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2584,7 +2920,9 @@ void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) - : Vop2("v_add_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2617,9 +2955,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2632,7 +2975,9 @@ std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { } // namespace detail VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) - : Vop2("v_sub_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2665,9 +3010,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2680,7 +3030,10 @@ std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2713,9 +3066,14 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2932,7 +3290,9 @@ std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { } // namespace detail VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) - : Vop2("v_xnor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXnorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2965,9 +3325,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp index 69754a6cb7bf..6b74cf86424c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna2 { VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -41,12 +44,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -56,7 +66,10 @@ std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -85,12 +98,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -164,7 +184,10 @@ std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) } // namespace detail VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -192,12 +215,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -207,7 +237,10 @@ std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -237,12 +270,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -254,7 +294,9 @@ std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) } // namespace detail VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -282,12 +324,19 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -297,7 +346,10 @@ std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,12 +377,19 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -340,7 +399,10 @@ std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -368,12 +430,19 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -383,7 +452,10 @@ std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -411,12 +483,19 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -426,7 +505,10 @@ std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -454,12 +536,19 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -469,7 +558,10 @@ std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -497,12 +589,19 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -512,7 +611,10 @@ std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -540,12 +642,19 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -555,7 +664,9 @@ std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -583,12 +694,19 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -598,7 +716,9 @@ std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -626,12 +746,19 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -641,7 +768,10 @@ std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -669,12 +799,19 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -684,7 +821,10 @@ std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -712,12 +852,19 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -727,7 +874,10 @@ std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -755,12 +905,19 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -770,7 +927,10 @@ std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -798,12 +958,19 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -813,7 +980,10 @@ std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -841,12 +1011,19 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -856,7 +1033,10 @@ std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -884,12 +1064,19 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -899,7 +1086,10 @@ std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -927,12 +1117,19 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -942,7 +1139,10 @@ std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -972,12 +1172,19 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -989,7 +1196,10 @@ std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1019,12 +1229,19 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1036,7 +1253,10 @@ std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1066,12 +1286,19 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1083,7 +1310,10 @@ std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1113,12 +1343,19 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1130,7 +1367,10 @@ std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1160,12 +1400,19 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1177,7 +1424,10 @@ std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1207,12 +1457,19 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1224,7 +1481,10 @@ std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1254,12 +1514,19 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1271,7 +1538,10 @@ std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1301,12 +1571,19 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1318,7 +1595,10 @@ std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1348,12 +1628,19 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1365,7 +1652,10 @@ std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1395,12 +1685,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1412,7 +1709,10 @@ std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1442,12 +1742,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1459,7 +1766,10 @@ std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1489,12 +1799,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1506,7 +1823,10 @@ std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1536,12 +1856,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1553,7 +1880,10 @@ std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1583,12 +1913,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1600,7 +1937,10 @@ std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1630,12 +1970,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1647,7 +1994,10 @@ std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1677,12 +2027,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1694,7 +2051,9 @@ std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1721,12 +2080,19 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1736,7 +2102,10 @@ std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1763,12 +2132,19 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1778,7 +2154,10 @@ std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1805,12 +2184,19 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1820,7 +2206,10 @@ std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1847,12 +2236,19 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1862,7 +2258,10 @@ std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1889,12 +2288,19 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1904,7 +2310,10 @@ std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1931,12 +2340,19 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1946,7 +2362,10 @@ std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1973,12 +2392,19 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1988,7 +2414,9 @@ std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2015,12 +2443,19 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2030,7 +2465,9 @@ std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2057,12 +2494,19 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2072,7 +2516,10 @@ std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2099,12 +2546,19 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2114,7 +2568,10 @@ std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2141,12 +2598,19 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2156,7 +2620,10 @@ std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2183,12 +2650,19 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2198,7 +2672,10 @@ std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2225,12 +2702,19 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2240,7 +2724,10 @@ std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2267,12 +2754,19 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2282,7 +2776,10 @@ std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2309,12 +2806,19 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2324,7 +2828,10 @@ std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2351,12 +2858,19 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2366,7 +2880,10 @@ std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2395,12 +2912,19 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2412,7 +2936,10 @@ std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2441,12 +2968,19 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2458,7 +2992,10 @@ std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2487,12 +3024,19 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2504,7 +3048,10 @@ std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2533,12 +3080,19 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2550,7 +3104,10 @@ std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2579,12 +3136,19 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2596,7 +3160,10 @@ std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2625,12 +3192,19 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2642,7 +3216,10 @@ std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2671,12 +3248,19 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2688,7 +3272,10 @@ std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2717,12 +3304,19 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2734,7 +3328,10 @@ std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2763,12 +3360,19 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2780,7 +3384,10 @@ std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2809,12 +3416,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2826,7 +3440,10 @@ std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2855,12 +3472,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2872,7 +3496,10 @@ std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2901,12 +3528,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2918,7 +3552,10 @@ std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2947,12 +3584,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2964,7 +3608,10 @@ std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2993,12 +3640,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3010,7 +3664,10 @@ std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3039,12 +3696,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3056,7 +3720,10 @@ std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3085,12 +3752,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4094,7 +4768,9 @@ std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4122,12 +4798,19 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4137,7 +4820,10 @@ std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4165,12 +4851,19 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4180,7 +4873,10 @@ std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4208,12 +4904,19 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4223,7 +4926,10 @@ std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4251,12 +4957,19 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4266,7 +4979,10 @@ std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4294,12 +5010,19 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4309,7 +5032,10 @@ std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4337,12 +5063,19 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4352,7 +5085,10 @@ std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4380,12 +5116,19 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4395,7 +5138,9 @@ std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4423,12 +5168,19 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4438,7 +5190,9 @@ std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4466,12 +5220,19 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4481,7 +5242,10 @@ std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4509,12 +5273,19 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4524,7 +5295,10 @@ std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4552,12 +5326,19 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4567,7 +5348,10 @@ std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4595,12 +5379,19 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4610,7 +5401,10 @@ std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4638,12 +5432,19 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4653,7 +5454,10 @@ std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4681,12 +5485,19 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4696,7 +5507,10 @@ std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4724,12 +5538,19 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4739,7 +5560,9 @@ std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4767,12 +5590,19 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4782,7 +5612,10 @@ std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4812,12 +5645,19 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4829,7 +5669,10 @@ std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4859,12 +5702,19 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4876,7 +5726,10 @@ std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4906,12 +5759,19 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4923,7 +5783,10 @@ std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4953,12 +5816,19 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4970,7 +5840,10 @@ std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5000,12 +5873,19 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5017,7 +5897,10 @@ std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5047,12 +5930,19 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5064,7 +5954,10 @@ std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5094,12 +5987,19 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5111,7 +6011,10 @@ std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5141,12 +6044,19 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5158,7 +6068,10 @@ std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5188,12 +6101,19 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5205,7 +6125,10 @@ std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5235,12 +6158,19 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5252,7 +6182,10 @@ std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5282,12 +6215,19 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5299,7 +6239,10 @@ std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5329,12 +6272,19 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5346,7 +6296,10 @@ std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5376,12 +6329,19 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5393,7 +6353,10 @@ std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5423,12 +6386,19 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5440,7 +6410,10 @@ std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5470,12 +6443,19 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5487,7 +6467,10 @@ std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5517,12 +6500,19 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5534,7 +6524,9 @@ std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5561,12 +6553,19 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5576,7 +6575,10 @@ std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5603,12 +6605,19 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5618,7 +6627,10 @@ std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5645,12 +6657,19 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5660,7 +6679,10 @@ std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5687,12 +6709,19 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5702,7 +6731,10 @@ std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5729,12 +6761,19 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5744,7 +6783,10 @@ std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5771,12 +6813,19 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5786,7 +6835,10 @@ std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5813,12 +6865,19 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5828,7 +6887,9 @@ std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5855,12 +6916,19 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5870,7 +6938,9 @@ std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5897,12 +6967,19 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5912,7 +6989,10 @@ std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5939,12 +7019,19 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5954,7 +7041,10 @@ std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5981,12 +7071,19 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5996,7 +7093,10 @@ std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6023,12 +7123,19 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6038,7 +7145,10 @@ std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6065,12 +7175,19 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6080,7 +7197,10 @@ std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6107,12 +7227,19 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6122,7 +7249,10 @@ std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6149,12 +7279,19 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6164,7 +7301,9 @@ std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6191,12 +7330,19 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6206,7 +7352,10 @@ std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6235,12 +7384,19 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6252,7 +7408,10 @@ std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6281,12 +7440,19 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6298,7 +7464,10 @@ std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6327,12 +7496,19 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6344,7 +7520,10 @@ std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6373,12 +7552,19 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6390,7 +7576,10 @@ std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6419,12 +7608,19 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6436,7 +7632,10 @@ std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6465,12 +7664,19 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6482,7 +7688,10 @@ std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6511,12 +7720,19 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6528,7 +7744,10 @@ std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6557,12 +7776,19 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6574,7 +7800,10 @@ std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6603,12 +7832,19 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6620,7 +7856,10 @@ std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6649,12 +7888,19 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6666,7 +7912,10 @@ std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6695,12 +7944,19 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6712,7 +7968,10 @@ std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6741,12 +8000,19 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6758,7 +8024,10 @@ std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6787,12 +8056,19 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6804,7 +8080,10 @@ std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6833,12 +8112,19 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6850,7 +8136,10 @@ std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6879,12 +8168,19 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6896,7 +8192,10 @@ std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6925,12 +8224,19 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.cpp index 7daed7db3a86..a67c7d28031c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include #include @@ -22,13 +23,68 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 44: + case 45: + case 48: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -38,13 +94,42 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 17: + return inst_.ssrc0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 18: + case 19: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -88,13 +173,73 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 20; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -127,13 +272,171 @@ void Smem::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 77: + case 78: + case 79: + case 84: + case 85: + case 86: + case 87: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop1::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 39: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 51: + case 52: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 77: + case 78: + case 79: + case 82: + case 84: + case 85: + case 86: + case 87: + return true; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -153,6 +456,28 @@ void Vop1::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop1::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop1::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop1::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -163,18 +488,386 @@ bool Vop1::has_dpp() { return inst_.src0 == 250; } bool Vop1::has_sdwa() { return inst_.src0 == 249; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + case 112: + case 113: + case 114: + case 115: + case 116: + case 117: + case 118: + case 119: + case 120: + case 121: + case 122: + case 123: + case 124: + case 125: + case 126: + case 127: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vopc::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 16: + case 17: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + return true; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } +void Vopc::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vopc::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_source_attributes(out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vopc::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -183,13 +876,142 @@ bool Vopc::has_lit() { return inst_.src0 == 255; } bool Vopc::has_sdwa() { return inst_.src0 == 249; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop2::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 61: + return true; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32() || + hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -211,6 +1033,28 @@ void Vop2::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop2::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop2::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop2::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h index a0c86c68c051..938dfb245d7e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h @@ -391,6 +391,7 @@ inline constexpr uint16_t kVop3pMfma = 423; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -401,6 +402,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -432,6 +434,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -452,7 +455,11 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -475,14 +482,23 @@ class Vop1 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_sdwa(); @@ -504,6 +520,10 @@ class Vopc : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_sdst_ = 106; bool sdwa_sd_ = false; }; @@ -511,7 +531,11 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -536,9 +560,14 @@ class Vop2 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vop3p : public IsaInstruction { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp index 0cdce1742b80..947171d10598 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp @@ -503,10 +503,6 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->ssrc1 == 255) - ssrc1 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); m0.apply_fieldless_caps(false, false, false); m0_in.apply_fieldless_caps(false, false, false); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp index 87f8481c78e7..93d108120d45 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace cdna3 { VNopVop1::VNopVop1(const MachineInst *inst) - : Vop1("v_nop_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNopVop1)) { num_src_ = 0; num_dst_ = 0; @@ -27,7 +29,9 @@ std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { } // namespace detail VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) - : Vop1("v_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMovB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -58,9 +62,12 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -155,7 +162,10 @@ std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32I32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -186,9 +196,12 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -199,7 +212,10 @@ std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32U32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -230,9 +246,12 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -243,7 +262,10 @@ std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { } // namespace detail VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_u32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -274,9 +296,12 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -287,7 +312,10 @@ std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -318,9 +346,12 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -331,7 +362,10 @@ std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16F32Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -362,9 +396,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -381,7 +418,10 @@ void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32F16Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -413,9 +453,12 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -426,7 +469,10 @@ std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { } // namespace detail VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_rpi_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtRpiI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -457,9 +503,12 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -470,7 +519,10 @@ std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_flr_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtFlrI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -501,9 +553,12 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -514,7 +569,10 @@ std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) - : Vop1("v_cvt_off_f32_i4_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtOffF32I4Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -545,9 +603,12 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -615,7 +676,10 @@ std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte0_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte0Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -646,9 +710,12 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -659,7 +726,10 @@ std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte1_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte1Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -690,9 +760,12 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -703,7 +776,10 @@ std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte2_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte2Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -734,9 +810,12 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -747,7 +826,10 @@ std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte3_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte3Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -778,9 +860,12 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -976,7 +1061,9 @@ std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { } // namespace detail VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) - : Vop1("v_fract_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1007,9 +1094,12 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1020,7 +1110,9 @@ std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { } // namespace detail VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) - : Vop1("v_trunc_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1051,9 +1143,12 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1064,7 +1159,9 @@ std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { } // namespace detail VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) - : Vop1("v_ceil_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1095,9 +1192,12 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1108,7 +1208,9 @@ std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { } // namespace detail VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) - : Vop1("v_rndne_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1139,9 +1241,12 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1152,7 +1257,9 @@ std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { } // namespace detail VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) - : Vop1("v_floor_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1183,9 +1290,12 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1196,7 +1306,9 @@ std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { } // namespace detail VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) - : Vop1("v_exp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1227,9 +1339,12 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1240,7 +1355,9 @@ std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { } // namespace detail VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) - : Vop1("v_log_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1271,9 +1388,12 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1284,7 +1404,9 @@ std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1315,9 +1437,12 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1328,7 +1453,10 @@ std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_iflag_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpIflagF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1359,9 +1487,12 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1372,7 +1503,9 @@ std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { } // namespace detail VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) - : Vop1("v_rsq_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1403,9 +1536,12 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1468,7 +1604,9 @@ std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { } // namespace detail VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1499,9 +1637,12 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1538,7 +1679,9 @@ std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { } // namespace detail VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) - : Vop1("v_sin_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1569,9 +1712,12 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1582,7 +1728,9 @@ std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { } // namespace detail VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) - : Vop1("v_cos_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1613,9 +1761,12 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1626,7 +1777,9 @@ std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { } // namespace detail VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) - : Vop1("v_not_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNotB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1657,9 +1810,12 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1670,7 +1826,9 @@ std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { } // namespace detail VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) - : Vop1("v_bfrev_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VBfrevB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1701,9 +1859,12 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1714,7 +1875,9 @@ std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhU32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1745,9 +1908,12 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1758,7 +1924,9 @@ std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { } // namespace detail VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) - : Vop1("v_ffbl_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfblB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1789,9 +1957,12 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1802,7 +1973,9 @@ std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhI32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1833,9 +2006,12 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1942,7 +2118,10 @@ std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { } // namespace detail VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1973,9 +2152,12 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1986,7 +2168,10 @@ std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode } // namespace detail VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2017,9 +2202,12 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2043,7 +2231,10 @@ std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { } // namespace detail VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) - : Vop1("v_screen_partition_4se_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VScreenPartition4seB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2074,9 +2265,12 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2087,7 +2281,9 @@ std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst } // namespace detail VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) - : Vop1("v_mov_b64_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b64_sdwa" + : "v_mov_b64_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMovB64Vop1)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2119,9 +2315,12 @@ VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2132,7 +2331,10 @@ std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_u16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16U16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2164,9 +2366,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2183,7 +2388,10 @@ void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2215,9 +2423,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2234,7 +2445,10 @@ void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2266,9 +2480,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2285,7 +2502,10 @@ void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2317,9 +2537,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2336,7 +2559,9 @@ void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) - : Vop1("v_rcp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2368,9 +2593,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2387,7 +2615,9 @@ void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { } VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2419,9 +2649,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2438,7 +2671,9 @@ void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { } VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) - : Vop1("v_rsq_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2470,9 +2705,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2489,7 +2727,9 @@ void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { } VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) - : Vop1("v_log_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2521,9 +2761,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2540,7 +2783,9 @@ void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) - : Vop1("v_exp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2572,9 +2817,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2591,7 +2839,10 @@ void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2623,9 +2874,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2642,7 +2896,10 @@ void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2674,9 +2931,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2693,7 +2953,9 @@ void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) - : Vop1("v_floor_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2725,9 +2987,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2744,7 +3009,9 @@ void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { } VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) - : Vop1("v_ceil_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2776,9 +3043,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2795,7 +3065,9 @@ void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { } VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) - : Vop1("v_trunc_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2827,9 +3099,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2846,7 +3121,9 @@ void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { } VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) - : Vop1("v_rndne_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2878,9 +3155,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2897,7 +3177,9 @@ void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { } VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) - : Vop1("v_fract_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2929,9 +3211,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2948,7 +3233,9 @@ void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { } VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) - : Vop1("v_sin_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2980,9 +3267,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2999,7 +3289,9 @@ void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { } VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) - : Vop1("v_cos_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3031,9 +3323,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3050,7 +3345,10 @@ void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3082,9 +3380,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3101,7 +3402,10 @@ void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3133,9 +3437,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3152,7 +3459,10 @@ void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) - : Vop1("v_sat_pk_u8_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSatPkU8I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3183,9 +3493,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3225,7 +3538,10 @@ std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { } // namespace detail VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) - : Vop1("v_accvgpr_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_accvgpr_mov_b32_sdwa" + : "v_accvgpr_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAccvgprMovB32Vop1)), vdst(32, OperandType::OPR_ACCVGPR, (reinterpret_cast(inst)->vdst + OpSelAccvgpr::OPR_ACCVGPR_ACC_MIN)), @@ -3257,9 +3573,12 @@ VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } flags_ |= ACCVGPR; } @@ -3271,7 +3590,10 @@ std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_fp8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_fp8_sdwa" + : "v_cvt_f32_fp8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Fp8Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3302,9 +3624,12 @@ VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3315,7 +3640,10 @@ std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_bf8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_bf8_sdwa" + : "v_cvt_f32_bf8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Bf8Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3346,9 +3674,12 @@ VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3359,7 +3690,10 @@ std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode) { } // namespace detail VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) - : Vop1("v_cvt_pk_f32_fp8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_fp8_sdwa" + : "v_cvt_pk_f32_fp8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtPkF32Fp8Vop1)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3391,9 +3725,12 @@ VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3404,7 +3741,10 @@ std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode) { } // namespace detail VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) - : Vop1("v_cvt_pk_f32_bf8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_bf8_sdwa" + : "v_cvt_pk_f32_bf8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtPkF32Bf8Vop1)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3436,9 +3776,12 @@ VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp index 8f7d90740f61..cd10bc7eb8cf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna3 { VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) - : Vop2("v_cndmask_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCndmaskB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -49,9 +52,14 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -65,7 +73,9 @@ std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { } // namespace detail VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) - : Vop2("v_add_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -98,9 +108,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -113,7 +128,9 @@ std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { } // namespace detail VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) - : Vop2("v_sub_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -146,9 +163,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -161,7 +183,10 @@ std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) - : Vop2("v_subrev_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -194,9 +219,14 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -244,7 +274,9 @@ std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { } // namespace detail VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) - : Vop2("v_mul_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -277,9 +309,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -292,7 +329,10 @@ std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { } // namespace detail VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,9 +365,14 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -340,7 +385,10 @@ std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -373,9 +421,14 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -388,7 +441,10 @@ std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -421,9 +477,14 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -436,7 +497,10 @@ std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -469,9 +533,14 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -484,7 +553,9 @@ std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) - : Vop2("v_min_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -517,9 +588,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -532,7 +608,9 @@ std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { } // namespace detail VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) - : Vop2("v_max_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -565,9 +643,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -580,7 +663,9 @@ std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { } // namespace detail VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) - : Vop2("v_min_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -613,9 +698,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -628,7 +718,9 @@ std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { } // namespace detail VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) - : Vop2("v_max_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -661,9 +753,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -676,7 +773,9 @@ std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { } // namespace detail VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) - : Vop2("v_min_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -709,9 +808,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -724,7 +828,9 @@ std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { } // namespace detail VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) - : Vop2("v_max_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -757,9 +863,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -772,7 +883,10 @@ std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { } // namespace detail VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -805,9 +919,14 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -820,7 +939,10 @@ std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -853,9 +975,14 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -868,7 +995,10 @@ std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { } // namespace detail VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -901,9 +1031,14 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -916,7 +1051,9 @@ std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) - : Vop2("v_and_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAndB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -949,9 +1086,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -964,7 +1106,9 @@ std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { } // namespace detail VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) - : Vop2("v_or_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VOrB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -997,9 +1141,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1012,7 +1161,9 @@ std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { } // namespace detail VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) - : Vop2("v_xor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1045,9 +1196,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1124,7 +1280,10 @@ std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { } // namespace detail VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) - : Vop2("v_add_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1159,9 +1318,14 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1175,7 +1339,10 @@ std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) - : Vop2("v_sub_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1210,9 +1377,14 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1226,7 +1398,10 @@ std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1261,9 +1436,14 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1277,7 +1457,10 @@ std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { } // namespace detail VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) - : Vop2("v_addc_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddcCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1314,9 +1497,14 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1331,7 +1519,10 @@ std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) - : Vop2("v_subb_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1368,9 +1559,14 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1385,7 +1581,10 @@ std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subbrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1422,9 +1621,14 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1439,7 +1643,9 @@ std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) } // namespace detail VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) - : Vop2("v_add_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1473,9 +1679,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1494,7 +1705,9 @@ void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) - : Vop2("v_sub_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1528,9 +1741,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1549,7 +1767,10 @@ void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) - : Vop2("v_subrev_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1583,9 +1804,14 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1604,7 +1830,9 @@ void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { } VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) - : Vop2("v_mul_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1638,9 +1866,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1780,7 +2013,9 @@ void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) - : Vop2("v_add_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1814,9 +2049,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1835,7 +2075,9 @@ void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) - : Vop2("v_sub_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1869,9 +2111,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1890,7 +2137,10 @@ void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) - : Vop2("v_subrev_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1924,9 +2174,14 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1945,7 +2200,10 @@ void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { } VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) - : Vop2("v_mul_lo_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulLoU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1979,9 +2237,14 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2000,7 +2263,10 @@ void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { } VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2034,9 +2300,14 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2055,7 +2326,10 @@ void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2089,9 +2363,14 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2110,7 +2389,10 @@ void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2144,9 +2426,14 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2165,7 +2452,9 @@ void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) - : Vop2("v_max_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2199,9 +2488,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2220,7 +2514,9 @@ void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { } VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) - : Vop2("v_min_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2254,9 +2550,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2275,7 +2576,9 @@ void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) - : Vop2("v_max_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2309,9 +2612,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2330,7 +2638,9 @@ void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) - : Vop2("v_max_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2364,9 +2674,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2385,7 +2700,9 @@ void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { } VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) - : Vop2("v_min_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2419,9 +2736,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2440,7 +2762,9 @@ void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { } VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) - : Vop2("v_min_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2474,9 +2798,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2495,7 +2824,9 @@ void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { } VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) - : Vop2("v_ldexp_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLdexpF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2529,9 +2860,14 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2550,7 +2886,9 @@ void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) - : Vop2("v_add_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2583,9 +2921,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2598,7 +2941,9 @@ std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { } // namespace detail VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) - : Vop2("v_sub_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2631,9 +2976,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2646,7 +2996,10 @@ std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2679,9 +3032,14 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2898,7 +3256,9 @@ std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { } // namespace detail VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) - : Vop2("v_xnor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXnorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2931,9 +3291,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp index 1c91bfd0714c..8d45e331e987 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna3 { VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -41,12 +44,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -56,7 +66,10 @@ std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -85,12 +98,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -164,7 +184,10 @@ std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) } // namespace detail VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -192,12 +215,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -207,7 +237,10 @@ std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -237,12 +270,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -254,7 +294,9 @@ std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) } // namespace detail VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -282,12 +324,19 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -297,7 +346,10 @@ std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,12 +377,19 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -340,7 +399,10 @@ std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -368,12 +430,19 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -383,7 +452,10 @@ std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -411,12 +483,19 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -426,7 +505,10 @@ std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -454,12 +536,19 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -469,7 +558,10 @@ std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -497,12 +589,19 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -512,7 +611,10 @@ std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -540,12 +642,19 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -555,7 +664,9 @@ std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -583,12 +694,19 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -598,7 +716,9 @@ std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -626,12 +746,19 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -641,7 +768,10 @@ std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -669,12 +799,19 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -684,7 +821,10 @@ std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -712,12 +852,19 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -727,7 +874,10 @@ std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -755,12 +905,19 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -770,7 +927,10 @@ std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -798,12 +958,19 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -813,7 +980,10 @@ std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -841,12 +1011,19 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -856,7 +1033,10 @@ std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -884,12 +1064,19 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -899,7 +1086,10 @@ std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -927,12 +1117,19 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -942,7 +1139,10 @@ std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -972,12 +1172,19 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -989,7 +1196,10 @@ std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1019,12 +1229,19 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1036,7 +1253,10 @@ std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1066,12 +1286,19 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1083,7 +1310,10 @@ std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1113,12 +1343,19 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1130,7 +1367,10 @@ std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1160,12 +1400,19 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1177,7 +1424,10 @@ std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1207,12 +1457,19 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1224,7 +1481,10 @@ std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1254,12 +1514,19 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1271,7 +1538,10 @@ std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1301,12 +1571,19 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1318,7 +1595,10 @@ std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1348,12 +1628,19 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1365,7 +1652,10 @@ std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1395,12 +1685,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1412,7 +1709,10 @@ std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1442,12 +1742,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1459,7 +1766,10 @@ std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1489,12 +1799,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1506,7 +1823,10 @@ std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1536,12 +1856,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1553,7 +1880,10 @@ std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1583,12 +1913,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1600,7 +1937,10 @@ std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1630,12 +1970,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1647,7 +1994,10 @@ std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1677,12 +2027,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1694,7 +2051,9 @@ std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1721,12 +2080,19 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1736,7 +2102,10 @@ std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1763,12 +2132,19 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1778,7 +2154,10 @@ std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1805,12 +2184,19 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1820,7 +2206,10 @@ std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1847,12 +2236,19 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1862,7 +2258,10 @@ std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1889,12 +2288,19 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1904,7 +2310,10 @@ std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1931,12 +2340,19 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1946,7 +2362,10 @@ std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1973,12 +2392,19 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1988,7 +2414,9 @@ std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2015,12 +2443,19 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2030,7 +2465,9 @@ std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2057,12 +2494,19 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2072,7 +2516,10 @@ std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2099,12 +2546,19 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2114,7 +2568,10 @@ std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2141,12 +2598,19 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2156,7 +2620,10 @@ std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2183,12 +2650,19 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2198,7 +2672,10 @@ std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2225,12 +2702,19 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2240,7 +2724,10 @@ std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2267,12 +2754,19 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2282,7 +2776,10 @@ std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2309,12 +2806,19 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2324,7 +2828,10 @@ std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2351,12 +2858,19 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2366,7 +2880,10 @@ std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2395,12 +2912,19 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2412,7 +2936,10 @@ std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2441,12 +2968,19 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2458,7 +2992,10 @@ std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2487,12 +3024,19 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2504,7 +3048,10 @@ std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2533,12 +3080,19 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2550,7 +3104,10 @@ std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2579,12 +3136,19 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2596,7 +3160,10 @@ std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2625,12 +3192,19 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2642,7 +3216,10 @@ std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2671,12 +3248,19 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2688,7 +3272,10 @@ std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2717,12 +3304,19 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2734,7 +3328,10 @@ std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2763,12 +3360,19 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2780,7 +3384,10 @@ std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2809,12 +3416,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2826,7 +3440,10 @@ std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2855,12 +3472,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2872,7 +3496,10 @@ std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2901,12 +3528,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2918,7 +3552,10 @@ std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2947,12 +3584,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2964,7 +3608,10 @@ std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2993,12 +3640,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3010,7 +3664,10 @@ std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3039,12 +3696,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3056,7 +3720,10 @@ std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3085,12 +3752,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4094,7 +4768,9 @@ std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4122,12 +4798,19 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4137,7 +4820,10 @@ std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4165,12 +4851,19 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4180,7 +4873,10 @@ std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4208,12 +4904,19 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4223,7 +4926,10 @@ std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4251,12 +4957,19 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4266,7 +4979,10 @@ std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4294,12 +5010,19 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4309,7 +5032,10 @@ std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4337,12 +5063,19 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4352,7 +5085,10 @@ std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4380,12 +5116,19 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4395,7 +5138,9 @@ std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4423,12 +5168,19 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4438,7 +5190,9 @@ std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4466,12 +5220,19 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4481,7 +5242,10 @@ std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4509,12 +5273,19 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4524,7 +5295,10 @@ std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4552,12 +5326,19 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4567,7 +5348,10 @@ std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4595,12 +5379,19 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4610,7 +5401,10 @@ std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4638,12 +5432,19 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4653,7 +5454,10 @@ std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4681,12 +5485,19 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4696,7 +5507,10 @@ std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4724,12 +5538,19 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4739,7 +5560,9 @@ std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4767,12 +5590,19 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4782,7 +5612,10 @@ std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4812,12 +5645,19 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4829,7 +5669,10 @@ std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4859,12 +5702,19 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4876,7 +5726,10 @@ std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4906,12 +5759,19 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4923,7 +5783,10 @@ std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4953,12 +5816,19 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4970,7 +5840,10 @@ std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5000,12 +5873,19 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5017,7 +5897,10 @@ std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5047,12 +5930,19 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5064,7 +5954,10 @@ std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5094,12 +5987,19 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5111,7 +6011,10 @@ std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5141,12 +6044,19 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5158,7 +6068,10 @@ std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5188,12 +6101,19 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5205,7 +6125,10 @@ std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5235,12 +6158,19 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5252,7 +6182,10 @@ std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5282,12 +6215,19 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5299,7 +6239,10 @@ std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5329,12 +6272,19 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5346,7 +6296,10 @@ std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5376,12 +6329,19 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5393,7 +6353,10 @@ std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5423,12 +6386,19 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5440,7 +6410,10 @@ std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5470,12 +6443,19 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5487,7 +6467,10 @@ std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5517,12 +6500,19 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5534,7 +6524,9 @@ std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5561,12 +6553,19 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5576,7 +6575,10 @@ std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5603,12 +6605,19 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5618,7 +6627,10 @@ std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5645,12 +6657,19 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5660,7 +6679,10 @@ std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5687,12 +6709,19 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5702,7 +6731,10 @@ std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5729,12 +6761,19 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5744,7 +6783,10 @@ std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5771,12 +6813,19 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5786,7 +6835,10 @@ std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5813,12 +6865,19 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5828,7 +6887,9 @@ std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5855,12 +6916,19 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5870,7 +6938,9 @@ std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5897,12 +6967,19 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5912,7 +6989,10 @@ std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5939,12 +7019,19 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5954,7 +7041,10 @@ std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5981,12 +7071,19 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5996,7 +7093,10 @@ std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6023,12 +7123,19 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6038,7 +7145,10 @@ std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6065,12 +7175,19 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6080,7 +7197,10 @@ std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6107,12 +7227,19 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6122,7 +7249,10 @@ std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6149,12 +7279,19 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6164,7 +7301,9 @@ std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6191,12 +7330,19 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6206,7 +7352,10 @@ std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6235,12 +7384,19 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6252,7 +7408,10 @@ std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6281,12 +7440,19 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6298,7 +7464,10 @@ std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6327,12 +7496,19 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6344,7 +7520,10 @@ std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6373,12 +7552,19 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6390,7 +7576,10 @@ std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6419,12 +7608,19 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6436,7 +7632,10 @@ std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6465,12 +7664,19 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6482,7 +7688,10 @@ std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6511,12 +7720,19 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6528,7 +7744,10 @@ std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6557,12 +7776,19 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6574,7 +7800,10 @@ std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6603,12 +7832,19 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6620,7 +7856,10 @@ std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6649,12 +7888,19 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6666,7 +7912,10 @@ std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6695,12 +7944,19 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6712,7 +7968,10 @@ std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6741,12 +8000,19 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6758,7 +8024,10 @@ std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6787,12 +8056,19 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6804,7 +8080,10 @@ std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6833,12 +8112,19 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6850,7 +8136,10 @@ std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6879,12 +8168,19 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6896,7 +8192,10 @@ std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6925,12 +8224,19 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp index 27c9bfadbe04..c44920db6dd1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna4/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.h" #include "util/except.h" #include @@ -1548,33 +1549,11 @@ struct DecoderImpl { static const std::array sub_decode_mtbuf; }; -namespace { - -bool isMfmaScaleF8f6f4Vop3px2(const MachineInst *opcode) { - constexpr uint32_t VOP3P_MFMA_ENC = 423; - constexpr uint32_t PREFIX_OP = 44; - auto enc0 = (opcode[0] >> 23) & 0x1FFu; - auto op0 = (opcode[0] >> 16) & 0x7Fu; - if (enc0 != VOP3P_MFMA_ENC || op0 != PREFIX_OP) - return false; - auto enc2 = (opcode[2] >> 23) & 0x1FFu; - auto op2 = (opcode[2] >> 16) & 0x7Fu; - return enc2 == VOP3P_MFMA_ENC && (op2 == 45 || op2 == 46); -} - -} // namespace - std::unique_ptr Decoder::decode(const MachineInst *opcode) { return DecoderImpl::decode(opcode); } std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { - if (isMfmaScaleF8f6f4Vop3px2(opcode)) { - auto op2 = (opcode[2] >> 16) & 0x7Fu; - if (op2 == 45) - return std::make_unique(opcode + 2, true); - return std::make_unique(opcode + 2, true); - } Sop1MachineInst op = std::bit_cast(*opcode); return primary_decode_table[op.encoding](opcode); } @@ -1625,8 +1604,15 @@ std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opco } std::unique_ptr DecoderImpl::decodeVop3pX2Prefix(const MachineInst *opcode) { - auto op = *reinterpret_cast(opcode + 2); - return sub_decode_vop3p[op.op](opcode + 2); + const uint32_t suffix_encoding = (opcode[2] >> 23) & 0x1FFu; + const uint32_t suffix_opcode = (opcode[2] >> 16) & 0x7Fu; + if (suffix_encoding != encoding::kVop3pMfma || + (suffix_opcode != kVMfmaF3216x16x128F8f6f4Vop3pMfma && + suffix_opcode != kVMfmaF3232x32x64F8f6f4Vop3pMfma)) + return decodeInvalid(opcode); + if (suffix_opcode == kVMfmaF3216x16x128F8f6f4Vop3pMfma) + return std::make_unique(opcode + 2, true); + return std::make_unique(opcode + 2, true); } std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.cpp index e183476d717a..4abececc8473 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include #include @@ -22,13 +23,68 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 44: + case 45: + case 48: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -38,13 +94,42 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 17: + return inst_.ssrc0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 18: + case 19: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -82,13 +167,73 @@ Sopk::Sopk(std::string_view mnemonic, const SopkMachineInst *inst, ExecuteFn exe bool Sopk::hasImpliedLiteral() { return inst_.op == 20; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -121,13 +266,179 @@ void Smem::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 84: + case 85: + case 86: + case 87: + case 88: + case 91: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop1::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 39: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 51: + case 52: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 82: + case 84: + case 85: + case 86: + case 87: + case 88: + case 91: + return true; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -147,6 +458,28 @@ void Vop1::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop1::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop1::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop1::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -157,18 +490,386 @@ bool Vop1::has_dpp() { return inst_.src0 == 250; } bool Vop1::has_sdwa() { return inst_.src0 == 249; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + case 112: + case 113: + case 114: + case 115: + case 116: + case 117: + case 118: + case 119: + case 120: + case 121: + case 122: + case 123: + case 124: + case 125: + case 126: + case 127: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vopc::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 16: + case 17: + case 20: + case 21: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 191: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + return true; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } +void Vopc::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vopc::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_source_attributes(out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vopc::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } @@ -177,13 +878,143 @@ bool Vopc::has_lit() { return inst_.src0 == 255; } bool Vopc::has_sdwa() { return inst_.src0 == 249; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop2::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 61: + return true; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || has_encoded_sdwa() || has_encoded_literal32() || + hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -205,6 +1036,28 @@ void Vop2::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop2::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop2::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vop2::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 255 && inst_.src0 != 249; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h index 7e567d711e8c..cd2f07fd9483 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h @@ -395,6 +395,7 @@ inline constexpr uint16_t kVop3pMfma = 423; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -405,6 +406,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -434,6 +436,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -454,7 +457,11 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -477,14 +484,23 @@ class Vop1 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_sdwa(); @@ -506,6 +522,10 @@ class Vopc : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_sdst_ = 106; bool sdwa_sd_ = false; }; @@ -513,7 +533,11 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool has_dpp(); @@ -538,9 +562,14 @@ class Vop2 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vop3p : public IsaInstruction { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp index 86a5e2d9588c..9233c83e4ee3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp @@ -503,10 +503,6 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->ssrc1 == 255) - ssrc1 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); m0.apply_fieldless_caps(false, false, false); m0_in.apply_fieldless_caps(false, false, false); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp index dfd4e8a47772..21020572e4f2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace cdna4 { VNopVop1::VNopVop1(const MachineInst *inst) - : Vop1("v_nop_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNopVop1)) { num_src_ = 0; num_dst_ = 0; @@ -27,7 +29,9 @@ std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { } // namespace detail VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) - : Vop1("v_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMovB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -58,9 +62,12 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -155,7 +162,10 @@ std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32I32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -186,9 +196,12 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -199,7 +212,10 @@ std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32U32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -230,9 +246,12 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -243,7 +262,10 @@ std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { } // namespace detail VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_u32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -274,9 +296,12 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -287,7 +312,10 @@ std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -318,9 +346,12 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -331,7 +362,10 @@ std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16F32Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -362,9 +396,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -381,7 +418,10 @@ void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32F16Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -413,9 +453,12 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -426,7 +469,10 @@ std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { } // namespace detail VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_rpi_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtRpiI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -457,9 +503,12 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -470,7 +519,10 @@ std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) - : Vop1("v_cvt_flr_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtFlrI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -501,9 +553,12 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -514,7 +569,10 @@ std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) - : Vop1("v_cvt_off_f32_i4_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtOffF32I4Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -545,9 +603,12 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -615,7 +676,10 @@ std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte0_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte0Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -646,9 +710,12 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -659,7 +726,10 @@ std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte1_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte1Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -690,9 +760,12 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -703,7 +776,10 @@ std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte2_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte2Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -734,9 +810,12 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -747,7 +826,10 @@ std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_ubyte3_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte3Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -778,9 +860,12 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -976,7 +1061,9 @@ std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { } // namespace detail VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) - : Vop1("v_fract_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1007,9 +1094,12 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1020,7 +1110,9 @@ std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { } // namespace detail VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) - : Vop1("v_trunc_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1051,9 +1143,12 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1064,7 +1159,9 @@ std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { } // namespace detail VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) - : Vop1("v_ceil_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1095,9 +1192,12 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1108,7 +1208,9 @@ std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { } // namespace detail VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) - : Vop1("v_rndne_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1139,9 +1241,12 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1152,7 +1257,9 @@ std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { } // namespace detail VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) - : Vop1("v_floor_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1183,9 +1290,12 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1196,7 +1306,9 @@ std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { } // namespace detail VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) - : Vop1("v_exp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1227,9 +1339,12 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1240,7 +1355,9 @@ std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { } // namespace detail VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) - : Vop1("v_log_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1271,9 +1388,12 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1284,7 +1404,9 @@ std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1315,9 +1437,12 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1328,7 +1453,10 @@ std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) - : Vop1("v_rcp_iflag_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpIflagF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1359,9 +1487,12 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1372,7 +1503,9 @@ std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { } // namespace detail VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) - : Vop1("v_rsq_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1403,9 +1536,12 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1468,7 +1604,9 @@ std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { } // namespace detail VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1499,9 +1637,12 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1538,7 +1679,9 @@ std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { } // namespace detail VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) - : Vop1("v_sin_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1569,9 +1712,12 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1582,7 +1728,9 @@ std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { } // namespace detail VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) - : Vop1("v_cos_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1613,9 +1761,12 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1626,7 +1777,9 @@ std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { } // namespace detail VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) - : Vop1("v_not_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VNotB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1657,9 +1810,12 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1670,7 +1826,9 @@ std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { } // namespace detail VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) - : Vop1("v_bfrev_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VBfrevB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1701,9 +1859,12 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1714,7 +1875,9 @@ std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_u32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhU32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1745,9 +1908,12 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1758,7 +1924,9 @@ std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { } // namespace detail VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) - : Vop1("v_ffbl_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfblB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1789,9 +1957,12 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1802,7 +1973,9 @@ std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) - : Vop1("v_ffbh_i32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFfbhI32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1833,9 +2006,12 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1942,7 +2118,10 @@ std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { } // namespace detail VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i32_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI32F32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -1973,9 +2152,12 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1986,7 +2168,10 @@ std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode } // namespace detail VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2017,9 +2202,12 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2043,7 +2231,10 @@ std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { } // namespace detail VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) - : Vop1("v_screen_partition_4se_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VScreenPartition4seB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2074,9 +2265,12 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2087,7 +2281,9 @@ std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst } // namespace detail VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) - : Vop1("v_mov_b64_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b64_sdwa" + : "v_mov_b64_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMovB64Vop1)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2119,9 +2315,12 @@ VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2132,7 +2331,10 @@ std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_u16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16U16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2164,9 +2366,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2183,7 +2388,10 @@ void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f16_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF16I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2215,9 +2423,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2234,7 +2445,10 @@ void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2266,9 +2480,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2285,7 +2502,10 @@ void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2317,9 +2537,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2336,7 +2559,9 @@ void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) - : Vop1("v_rcp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRcpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2368,9 +2593,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2387,7 +2615,9 @@ void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { } VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) - : Vop1("v_sqrt_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSqrtF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2419,9 +2649,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2438,7 +2671,9 @@ void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { } VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) - : Vop1("v_rsq_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRsqF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2470,9 +2705,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2489,7 +2727,9 @@ void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { } VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) - : Vop1("v_log_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2521,9 +2761,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2540,7 +2783,9 @@ void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) - : Vop1("v_exp_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2572,9 +2817,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2591,7 +2839,10 @@ void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) - : Vop1("v_frexp_mant_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpMantF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2623,9 +2874,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2642,7 +2896,10 @@ void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) - : Vop1("v_frexp_exp_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFrexpExpI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2674,9 +2931,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2693,7 +2953,9 @@ void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) - : Vop1("v_floor_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFloorF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2725,9 +2987,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2744,7 +3009,9 @@ void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { } VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) - : Vop1("v_ceil_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCeilF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2776,9 +3043,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2795,7 +3065,9 @@ void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { } VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) - : Vop1("v_trunc_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VTruncF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2827,9 +3099,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2846,7 +3121,9 @@ void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { } VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) - : Vop1("v_rndne_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VRndneF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2878,9 +3155,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2897,7 +3177,9 @@ void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { } VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) - : Vop1("v_fract_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VFractF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2929,9 +3211,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2948,7 +3233,9 @@ void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { } VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) - : Vop1("v_sin_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSinF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -2980,9 +3267,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2999,7 +3289,9 @@ void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { } VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) - : Vop1("v_cos_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCosF16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3031,9 +3323,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3050,7 +3345,10 @@ void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpLegacyF32Vop1::VExpLegacyF32Vop1(const MachineInst *inst) - : Vop1("v_exp_legacy_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_exp_legacy_f32_sdwa" + : "v_exp_legacy_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VExpLegacyF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3081,9 +3379,12 @@ VExpLegacyF32Vop1::VExpLegacyF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3094,7 +3395,10 @@ std::unique_ptr decodeVExpLegacyF32Vop1(const MachineInst *opcode) } // namespace detail VLogLegacyF32Vop1::VLogLegacyF32Vop1(const MachineInst *inst) - : Vop1("v_log_legacy_f32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_log_legacy_f32_sdwa" + : "v_log_legacy_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLogLegacyF32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3125,9 +3429,12 @@ VLogLegacyF32Vop1::VLogLegacyF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3138,7 +3445,10 @@ std::unique_ptr decodeVLogLegacyF32Vop1(const MachineInst *opcode) } // namespace detail VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_i16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormI16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3170,9 +3480,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3189,7 +3502,10 @@ void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) - : Vop1("v_cvt_norm_u16_f16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtNormU16F16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3221,9 +3537,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3240,7 +3559,10 @@ void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) - : Vop1("v_sat_pk_u8_i16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSatPkU8I16Vop1)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3271,9 +3593,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3313,7 +3638,10 @@ std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { } // namespace detail VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) - : Vop1("v_accvgpr_mov_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_accvgpr_mov_b32_sdwa" + : "v_accvgpr_mov_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAccvgprMovB32Vop1)), vdst(32, OperandType::OPR_ACCVGPR, (reinterpret_cast(inst)->vdst + OpSelAccvgpr::OPR_ACCVGPR_ACC_MIN)), @@ -3345,9 +3673,12 @@ VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } flags_ |= ACCVGPR; } @@ -3359,7 +3690,10 @@ std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_fp8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_fp8_sdwa" + : "v_cvt_f32_fp8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Fp8Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3390,9 +3724,12 @@ VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3403,7 +3740,10 @@ std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_bf8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_bf8_sdwa" + : "v_cvt_f32_bf8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Bf8Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3434,9 +3774,12 @@ VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3447,7 +3790,10 @@ std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode) { } // namespace detail VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) - : Vop1("v_cvt_pk_f32_fp8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_fp8_sdwa" + : "v_cvt_pk_f32_fp8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtPkF32Fp8Vop1)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3479,9 +3825,12 @@ VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3492,7 +3841,10 @@ std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode) { } // namespace detail VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) - : Vop1("v_cvt_pk_f32_bf8_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_bf8_sdwa" + : "v_cvt_pk_f32_bf8_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtPkF32Bf8Vop1)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3524,9 +3876,12 @@ VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3537,7 +3892,9 @@ std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode) { } // namespace detail VPrngB32Vop1::VPrngB32Vop1(const MachineInst *inst) - : Vop1("v_prng_b32_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_prng_b32_sdwa" + : "v_prng_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VPrngB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3568,9 +3925,12 @@ VPrngB32Vop1::VPrngB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3627,7 +3987,10 @@ std::unique_ptr decodeVPermlane32SwapB32Vop1(const MachineInst *opc } // namespace detail VCvtF32Bf16Vop1::VCvtF32Bf16Vop1(const MachineInst *inst) - : Vop1("v_cvt_f32_bf16_e32", reinterpret_cast(inst), + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_bf16_sdwa" + : "v_cvt_f32_bf16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCvtF32Bf16Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { @@ -3659,9 +4022,12 @@ VCvtF32Bf16Vop1::VCvtF32Bf16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::BF16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp index c1d1bf594e55..883a0f88f760 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna4 { VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) - : Vop2("v_cndmask_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCndmaskB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -49,9 +52,14 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -65,7 +73,9 @@ std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { } // namespace detail VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) - : Vop2("v_add_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -98,9 +108,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -113,7 +128,9 @@ std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { } // namespace detail VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) - : Vop2("v_sub_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -146,9 +163,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -161,7 +183,10 @@ std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) - : Vop2("v_subrev_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -194,9 +219,14 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -244,7 +274,9 @@ std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { } // namespace detail VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) - : Vop2("v_mul_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -277,9 +309,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -292,7 +329,10 @@ std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { } // namespace detail VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,9 +365,14 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -340,7 +385,10 @@ std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_i32_i24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiI32I24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -373,9 +421,14 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -388,7 +441,10 @@ std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -421,9 +477,14 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -436,7 +497,10 @@ std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) - : Vop2("v_mul_hi_u32_u24_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulHiU32U24Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -469,9 +533,14 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -484,7 +553,9 @@ std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) - : Vop2("v_min_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -517,9 +588,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -532,7 +608,9 @@ std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { } // namespace detail VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) - : Vop2("v_max_f32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -565,9 +643,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -580,7 +663,9 @@ std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { } // namespace detail VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) - : Vop2("v_min_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -613,9 +698,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -628,7 +718,9 @@ std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { } // namespace detail VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) - : Vop2("v_max_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -661,9 +753,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -676,7 +773,9 @@ std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { } // namespace detail VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) - : Vop2("v_min_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -709,9 +808,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -724,7 +828,9 @@ std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { } // namespace detail VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) - : Vop2("v_max_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -757,9 +863,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -772,7 +883,10 @@ std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { } // namespace detail VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -805,9 +919,14 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -820,7 +939,10 @@ std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -853,9 +975,14 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -868,7 +995,10 @@ std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { } // namespace detail VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -901,9 +1031,14 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -916,7 +1051,9 @@ std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) - : Vop2("v_and_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAndB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -949,9 +1086,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -964,7 +1106,9 @@ std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { } // namespace detail VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) - : Vop2("v_or_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VOrB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -997,9 +1141,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1012,7 +1161,9 @@ std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { } // namespace detail VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) - : Vop2("v_xor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1045,9 +1196,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1160,7 +1316,10 @@ std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { } // namespace detail VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) - : Vop2("v_add_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1195,9 +1354,14 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1211,7 +1375,10 @@ std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) - : Vop2("v_sub_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1246,9 +1413,14 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1262,7 +1434,10 @@ std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1297,9 +1472,14 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1313,7 +1493,10 @@ std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { } // namespace detail VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) - : Vop2("v_addc_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddcCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1350,9 +1533,14 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1367,7 +1555,10 @@ std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) - : Vop2("v_subb_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1404,9 +1595,14 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1421,7 +1617,10 @@ std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { } // namespace detail VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) - : Vop2("v_subbrev_co_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubbrevCoU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), vcc(64, OperandType::OPR_VCC, 0), @@ -1458,9 +1657,14 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1475,7 +1679,9 @@ std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) } // namespace detail VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) - : Vop2("v_add_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1509,9 +1715,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1530,7 +1741,9 @@ void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) - : Vop2("v_sub_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1564,9 +1777,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1585,7 +1803,10 @@ void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) - : Vop2("v_subrev_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1619,9 +1840,14 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1640,7 +1866,9 @@ void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { } VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) - : Vop2("v_mul_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1674,9 +1902,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1818,7 +2051,9 @@ void VMadakF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) - : Vop2("v_add_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1852,9 +2087,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1873,7 +2113,9 @@ void VAddU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) - : Vop2("v_sub_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1907,9 +2149,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1928,7 +2175,10 @@ void VSubU16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) - : Vop2("v_subrev_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -1962,9 +2212,14 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1983,7 +2238,10 @@ void VSubrevU16Vop2::implicit_uses(RegisterSet &uses) const { } VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) - : Vop2("v_mul_lo_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMulLoU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2017,9 +2275,14 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2038,7 +2301,10 @@ void VMulLoU16Vop2::implicit_uses(RegisterSet &uses) const { } VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshlrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshlrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2072,9 +2338,14 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2093,7 +2364,10 @@ void VLshlrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) - : Vop2("v_lshrrev_b16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLshrrevB16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2127,9 +2401,14 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2148,7 +2427,10 @@ void VLshrrevB16Vop2::implicit_uses(RegisterSet &uses) const { } VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) - : Vop2("v_ashrrev_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAshrrevI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2182,9 +2464,14 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2203,7 +2490,9 @@ void VAshrrevI16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) - : Vop2("v_max_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2237,9 +2526,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2258,7 +2552,9 @@ void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { } VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) - : Vop2("v_min_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2292,9 +2588,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2313,7 +2614,9 @@ void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) - : Vop2("v_max_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2347,9 +2650,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2368,7 +2676,9 @@ void VMaxU16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) - : Vop2("v_max_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMaxI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2402,9 +2712,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2423,7 +2738,9 @@ void VMaxI16Vop2::implicit_uses(RegisterSet &uses) const { } VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) - : Vop2("v_min_u16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinU16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2457,9 +2774,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2478,7 +2800,9 @@ void VMinU16Vop2::implicit_uses(RegisterSet &uses) const { } VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) - : Vop2("v_min_i16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VMinI16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2512,9 +2836,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2533,7 +2862,9 @@ void VMinI16Vop2::implicit_uses(RegisterSet &uses) const { } VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) - : Vop2("v_ldexp_f16_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VLdexpF16Vop2)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2567,9 +2898,14 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2588,7 +2924,9 @@ void VLdexpF16Vop2::implicit_uses(RegisterSet &uses) const { } VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) - : Vop2("v_add_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VAddU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2621,9 +2959,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2636,7 +2979,9 @@ std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { } // namespace detail VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) - : Vop2("v_sub_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2669,9 +3014,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2684,7 +3034,10 @@ std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) - : Vop2("v_subrev_u32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VSubrevU32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOLDS, reinterpret_cast(inst)->src0), @@ -2717,9 +3070,14 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2936,7 +3294,9 @@ std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { } // namespace detail VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) - : Vop2("v_xnor_b32_e32", reinterpret_cast(inst), + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VXnorB32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2969,9 +3329,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp index d28f01b90ec9..35859f8f9cbe 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp @@ -14,7 +14,10 @@ namespace rocjitsu { namespace cdna4 { VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -41,12 +44,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -56,7 +66,10 @@ std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -85,12 +98,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -164,7 +184,10 @@ std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) } // namespace detail VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -192,12 +215,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -207,7 +237,10 @@ std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -237,12 +270,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -254,7 +294,9 @@ std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) } // namespace detail VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -282,12 +324,19 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -297,7 +346,10 @@ std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -325,12 +377,19 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -340,7 +399,10 @@ std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -368,12 +430,19 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -383,7 +452,10 @@ std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -411,12 +483,19 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -426,7 +505,10 @@ std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -454,12 +536,19 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -469,7 +558,10 @@ std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -497,12 +589,19 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -512,7 +611,10 @@ std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -540,12 +642,19 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -555,7 +664,9 @@ std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -583,12 +694,19 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -598,7 +716,9 @@ std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -626,12 +746,19 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -641,7 +768,10 @@ std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -669,12 +799,19 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -684,7 +821,10 @@ std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -712,12 +852,19 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -727,7 +874,10 @@ std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -755,12 +905,19 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -770,7 +927,10 @@ std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -798,12 +958,19 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -813,7 +980,10 @@ std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -841,12 +1011,19 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -856,7 +1033,10 @@ std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -884,12 +1064,19 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -899,7 +1086,10 @@ std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -927,12 +1117,19 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -942,7 +1139,10 @@ std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -972,12 +1172,19 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -989,7 +1196,10 @@ std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1019,12 +1229,19 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1036,7 +1253,10 @@ std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1066,12 +1286,19 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1083,7 +1310,10 @@ std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1113,12 +1343,19 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1130,7 +1367,10 @@ std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1160,12 +1400,19 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1177,7 +1424,10 @@ std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1207,12 +1457,19 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1224,7 +1481,10 @@ std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1254,12 +1514,19 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1271,7 +1538,10 @@ std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1301,12 +1571,19 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1318,7 +1595,10 @@ std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1348,12 +1628,19 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1365,7 +1652,10 @@ std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1395,12 +1685,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1412,7 +1709,10 @@ std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1442,12 +1742,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1459,7 +1766,10 @@ std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1489,12 +1799,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1506,7 +1823,10 @@ std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1536,12 +1856,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1553,7 +1880,10 @@ std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1583,12 +1913,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1600,7 +1937,10 @@ std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1630,12 +1970,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1647,7 +1994,10 @@ std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1677,12 +2027,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1694,7 +2051,9 @@ std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1721,12 +2080,19 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1736,7 +2102,10 @@ std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1763,12 +2132,19 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1778,7 +2154,10 @@ std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1805,12 +2184,19 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1820,7 +2206,10 @@ std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1847,12 +2236,19 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1862,7 +2258,10 @@ std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1889,12 +2288,19 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1904,7 +2310,10 @@ std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1931,12 +2340,19 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1946,7 +2362,10 @@ std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1973,12 +2392,19 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -1988,7 +2414,9 @@ std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2015,12 +2443,19 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2030,7 +2465,9 @@ std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2057,12 +2494,19 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2072,7 +2516,10 @@ std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2099,12 +2546,19 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2114,7 +2568,10 @@ std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2141,12 +2598,19 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2156,7 +2620,10 @@ std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2183,12 +2650,19 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2198,7 +2672,10 @@ std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2225,12 +2702,19 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2240,7 +2724,10 @@ std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2267,12 +2754,19 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2282,7 +2776,10 @@ std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2309,12 +2806,19 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2324,7 +2828,10 @@ std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2351,12 +2858,19 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2366,7 +2880,10 @@ std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2395,12 +2912,19 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2412,7 +2936,10 @@ std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2441,12 +2968,19 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2458,7 +2992,10 @@ std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2487,12 +3024,19 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2504,7 +3048,10 @@ std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2533,12 +3080,19 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2550,7 +3104,10 @@ std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2579,12 +3136,19 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2596,7 +3160,10 @@ std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2625,12 +3192,19 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2642,7 +3216,10 @@ std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2671,12 +3248,19 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2688,7 +3272,10 @@ std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2717,12 +3304,19 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2734,7 +3328,10 @@ std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2763,12 +3360,19 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2780,7 +3384,10 @@ std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2809,12 +3416,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2826,7 +3440,10 @@ std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2855,12 +3472,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2872,7 +3496,10 @@ std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2901,12 +3528,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2918,7 +3552,10 @@ std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2947,12 +3584,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2964,7 +3608,10 @@ std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2993,12 +3640,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3010,7 +3664,10 @@ std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3039,12 +3696,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3056,7 +3720,10 @@ std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3085,12 +3752,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4094,7 +4768,9 @@ std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4122,12 +4798,19 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4137,7 +4820,10 @@ std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4165,12 +4851,19 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4180,7 +4873,10 @@ std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4208,12 +4904,19 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4223,7 +4926,10 @@ std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4251,12 +4957,19 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4266,7 +4979,10 @@ std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4294,12 +5010,19 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4309,7 +5032,10 @@ std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4337,12 +5063,19 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4352,7 +5085,10 @@ std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4380,12 +5116,19 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4395,7 +5138,9 @@ std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4423,12 +5168,19 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4438,7 +5190,9 @@ std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4466,12 +5220,19 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4481,7 +5242,10 @@ std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4509,12 +5273,19 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4524,7 +5295,10 @@ std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4552,12 +5326,19 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4567,7 +5348,10 @@ std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4595,12 +5379,19 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4610,7 +5401,10 @@ std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4638,12 +5432,19 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4653,7 +5454,10 @@ std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4681,12 +5485,19 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4696,7 +5507,10 @@ std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4724,12 +5538,19 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4739,7 +5560,9 @@ std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4767,12 +5590,19 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4782,7 +5612,10 @@ std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4812,12 +5645,19 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4829,7 +5669,10 @@ std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4859,12 +5702,19 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4876,7 +5726,10 @@ std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4906,12 +5759,19 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4923,7 +5783,10 @@ std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4953,12 +5816,19 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4970,7 +5840,10 @@ std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5000,12 +5873,19 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5017,7 +5897,10 @@ std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5047,12 +5930,19 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5064,7 +5954,10 @@ std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5094,12 +5987,19 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5111,7 +6011,10 @@ std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5141,12 +6044,19 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5158,7 +6068,10 @@ std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5188,12 +6101,19 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5205,7 +6125,10 @@ std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5235,12 +6158,19 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5252,7 +6182,10 @@ std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5282,12 +6215,19 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5299,7 +6239,10 @@ std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5329,12 +6272,19 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5346,7 +6296,10 @@ std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5376,12 +6329,19 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5393,7 +6353,10 @@ std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5423,12 +6386,19 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5440,7 +6410,10 @@ std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5470,12 +6443,19 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5487,7 +6467,10 @@ std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU16Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5517,12 +6500,19 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5534,7 +6524,9 @@ std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5561,12 +6553,19 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5576,7 +6575,10 @@ std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5603,12 +6605,19 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5618,7 +6627,10 @@ std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5645,12 +6657,19 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5660,7 +6679,10 @@ std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5687,12 +6709,19 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5702,7 +6731,10 @@ std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5729,12 +6761,19 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5744,7 +6783,10 @@ std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5771,12 +6813,19 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5786,7 +6835,10 @@ std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5813,12 +6865,19 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5828,7 +6887,9 @@ std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5855,12 +6916,19 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5870,7 +6938,9 @@ std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5897,12 +6967,19 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5912,7 +6989,10 @@ std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5939,12 +7019,19 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5954,7 +7041,10 @@ std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5981,12 +7071,19 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5996,7 +7093,10 @@ std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6023,12 +7123,19 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6038,7 +7145,10 @@ std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6065,12 +7175,19 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6080,7 +7197,10 @@ std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6107,12 +7227,19 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6122,7 +7249,10 @@ std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6149,12 +7279,19 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6164,7 +7301,9 @@ std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6191,12 +7330,19 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6206,7 +7352,10 @@ std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6235,12 +7384,19 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6252,7 +7408,10 @@ std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6281,12 +7440,19 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6298,7 +7464,10 @@ std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6327,12 +7496,19 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6344,7 +7520,10 @@ std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6373,12 +7552,19 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6390,7 +7576,10 @@ std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6419,12 +7608,19 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6436,7 +7632,10 @@ std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6465,12 +7664,19 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6482,7 +7688,10 @@ std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6511,12 +7720,19 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6528,7 +7744,10 @@ std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6557,12 +7776,19 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6574,7 +7800,10 @@ std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6603,12 +7832,19 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6620,7 +7856,10 @@ std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6649,12 +7888,19 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6666,7 +7912,10 @@ std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6695,12 +7944,19 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6712,7 +7968,10 @@ std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6741,12 +8000,19 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6758,7 +8024,10 @@ std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6787,12 +8056,19 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6804,7 +8080,10 @@ std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6833,12 +8112,19 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6850,7 +8136,10 @@ std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6879,12 +8168,19 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6896,7 +8192,10 @@ std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU32Vopc)), vcc(64, OperandType::OPR_VCC, 0), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6925,12 +8224,19 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp index 6cb7d6d294d3..eb7033bdca4d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp @@ -12,6 +12,170 @@ namespace rocjitsu { namespace cdna5 { +bool Sop1::has_encoded_literal64() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 66: + case 67: + case 75: + case 83: + case 88: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + return inst_.ssrc0 == 254; + default: + return false; + } +} + +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 66: + case 67: + case 75: + case 83: + case 88: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -25,12 +189,10 @@ Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exe if (!supports_literal(literal_support, LiteralSupport::Literal64) && ((num_encoded_sources > 0 && inst_.ssrc0 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if (inst_.op != 76 && inst_.op != 77) { - if (has_lit64_0()) - size_ += 2 * sizeof(MachineInst); - else if (!default_encoding()) - size_ += sizeof(MachineInst); - } + if (has_encoded_literal64()) + size_ += 2 * sizeof(MachineInst); + else if (has_encoded_literal32()) + size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } @@ -41,6 +203,114 @@ bool Sop1::has_lit_0() { return (inst_.ssrc0 == 255); } bool Sop1::has_lit64_0() { return (inst_.ssrc0 == 254); } +bool Sopc::has_encoded_literal64() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + return inst_.ssrc0 == 254 || inst_.ssrc1 == 254; + default: + return false; + } +} + +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -56,9 +326,9 @@ Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exe ((num_encoded_sources > 0 && inst_.ssrc0 == 254) || (num_encoded_sources > 1 && inst_.ssrc1 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if (has_lit64_0() || has_lit64_1() || has_lit64_0_and_has_lit64_1()) + if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); - else if (!default_encoding()) + else if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -124,6 +394,170 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 19; } +bool Sop2::has_encoded_literal64() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + return inst_.ssrc0 == 254 || inst_.ssrc1 == 254; + default: + return false; + } +} + +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -139,9 +573,9 @@ Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exe ((num_encoded_sources > 0 && inst_.ssrc0 == 254) || (num_encoded_sources > 1 && inst_.ssrc1 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if (has_lit64_0() || has_lit64_1() || has_lit64_0_and_has_lit64_1()) + if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); - else if (!default_encoding() || hasImpliedLiteral()) + else if (has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -196,6 +630,220 @@ void Smem::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop1::has_encoded_literal64() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 74: + case 75: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + case 114: + case 115: + case 116: + case 117: + case 118: + case 119: + case 120: + case 121: + case 122: + case 123: + case 124: + case 125: + case 126: + case 127: + return inst_.src0 == 254; + default: + return false; + } +} + +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 74: + case 75: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + case 114: + case 115: + case 116: + case 117: + case 118: + case 119: + case 120: + case 121: + case 122: + case 123: + case 124: + case 125: + case 126: + case 127: + return inst_.src0 == 255; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -209,9 +857,10 @@ Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exe if (!supports_literal(literal_support, LiteralSupport::Literal64) && ((num_encoded_sources > 0 && inst_.src0 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if (has_lit64()) + if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); - else if (!default_encoding()) + else if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -263,6 +912,346 @@ bool Vop1::has_dpp8() { return (inst_.src0 == 233 || inst_.src0 == 234); } bool Vop1::has_dpp16() { return (inst_.src0 == 250); } +bool Vopc::has_encoded_literal64() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 125: + case 126: + case 127: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 253: + case 254: + case 255: + return inst_.src0 == 254; + default: + return false; + } +} + +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 125: + case 126: + case 127: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -276,9 +1265,10 @@ Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exe if (!supports_literal(literal_support, LiteralSupport::Literal64) && ((num_encoded_sources > 0 && inst_.src0 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if (has_lit64()) + if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); - else if (!default_encoding()) + else if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -302,6 +1292,132 @@ bool Vopc::has_dpp8() { return (inst_.src0 == 233 || inst_.src0 == 234); } bool Vopc::has_dpp16() { return (inst_.src0 == 250); } +bool Vop2::has_encoded_literal64() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 59: + case 60: + return inst_.src0 == 254; + default: + return false; + } +} + +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 59: + case 60: + return inst_.src0 == 255; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -317,9 +1433,10 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (hasImpliedLiteral()) size_ += impliedLiteralWordCount() * sizeof(MachineInst); - else if (has_lit64() || hasImpliedLiteral64()) + else if (hasImpliedLiteral64() || has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); - else if (!default_encoding()) + else if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -390,6 +1507,541 @@ uint32_t Vop2::impliedLiteralWordCount() { : 0; } +bool Vop3::has_encoded_literal32() const { + switch (inst_.op) { + case 385: + case 387: + case 388: + case 389: + case 390: + case 391: + case 392: + case 394: + case 395: + case 396: + case 397: + case 398: + case 399: + case 400: + case 401: + case 402: + case 403: + case 404: + case 405: + case 406: + case 407: + case 408: + case 409: + case 410: + case 412: + case 413: + case 414: + case 415: + case 416: + case 417: + case 418: + case 419: + case 420: + case 421: + case 423: + case 426: + case 427: + case 430: + case 431: + case 433: + case 435: + case 436: + case 437: + case 438: + case 439: + case 440: + case 441: + case 442: + case 443: + case 444: + case 445: + case 446: + case 447: + case 448: + case 450: + case 458: + case 459: + case 464: + case 465: + case 466: + case 467: + case 468: + case 469: + case 470: + case 471: + case 472: + case 473: + case 474: + case 475: + case 476: + case 477: + case 478: + case 479: + case 480: + case 481: + case 482: + case 483: + case 484: + case 489: + case 490: + case 491: + case 492: + case 493: + case 494: + case 495: + case 498: + case 499: + case 500: + case 501: + case 502: + case 503: + case 504: + case 505: + case 506: + case 507: + case 508: + case 509: + case 510: + case 511: + case 640: + case 641: + case 642: + case 643: + case 644: + case 645: + case 646: + case 647: + case 648: + case 649: + case 865: + case 882: + case 883: + return inst_.src0 == 255; + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 125: + case 126: + case 127: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 253: + case 254: + case 255: + case 257: + case 258: + case 259: + case 260: + case 261: + case 262: + case 263: + case 264: + case 265: + case 266: + case 267: + case 268: + case 269: + case 270: + case 273: + case 274: + case 275: + case 276: + case 277: + case 278: + case 279: + case 280: + case 281: + case 282: + case 283: + case 284: + case 285: + case 286: + case 287: + case 293: + case 294: + case 295: + case 296: + case 297: + case 298: + case 299: + case 303: + case 304: + case 305: + case 306: + case 307: + case 308: + case 309: + case 310: + case 315: + case 573: + case 605: + case 771: + case 772: + case 773: + case 774: + case 775: + case 777: + case 778: + case 779: + case 780: + case 781: + case 782: + case 785: + case 786: + case 787: + case 792: + case 793: + case 794: + case 795: + case 796: + case 797: + case 798: + case 799: + case 800: + case 801: + case 802: + case 803: + case 804: + case 805: + case 806: + case 811: + case 812: + case 813: + case 814: + case 815: + case 824: + case 825: + case 826: + case 829: + case 830: + case 833: + case 834: + case 866: + case 867: + case 868: + case 869: + case 870: + case 871: + case 872: + case 873: + case 874: + case 875: + case 876: + case 877: + case 879: + case 884: + case 885: + return inst_.src0 == 255 || inst_.src1 == 255; + case 521: + case 522: + case 523: + case 524: + case 525: + case 526: + case 527: + case 528: + case 529: + case 530: + case 531: + case 532: + case 533: + case 534: + case 535: + case 536: + case 538: + case 539: + case 541: + case 542: + case 544: + case 545: + case 546: + case 547: + case 548: + case 549: + case 550: + case 551: + case 552: + case 553: + case 554: + case 555: + case 556: + case 557: + case 558: + case 559: + case 560: + case 561: + case 562: + case 563: + case 564: + case 565: + case 567: + case 568: + case 569: + case 570: + case 571: + case 575: + case 576: + case 577: + case 578: + case 579: + case 580: + case 581: + case 582: + case 583: + case 584: + case 586: + case 587: + case 589: + case 590: + case 592: + case 593: + case 594: + case 595: + case 596: + case 597: + case 598: + case 599: + case 600: + case 601: + case 602: + case 606: + case 607: + case 608: + case 609: + case 610: + case 611: + case 612: + case 613: + case 616: + case 617: + case 618: + case 619: + case 620: + case 621: + case 622: + case 623: + case 656: + case 657: + case 762: + case 763: + case 878: + case 880: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + case 671: + case 672: + case 673: + case 680: + case 681: + case 682: + case 683: + case 684: + case 685: + case 688: + case 691: + case 692: + case 693: + case 696: + case 707: + case 708: + case 709: + case 710: + case 711: + case 712: + case 713: + case 714: + case 715: + case 716: + case 717: + case 718: + case 719: + case 720: + case 721: + case 722: + case 788: + return inst_.src1 == 255; + case 603: + case 604: + case 624: + case 625: + case 626: + case 627: + case 663: + case 664: + case 665: + case 697: + case 700: + case 703: + case 704: + case 705: + case 706: + case 723: + case 724: + case 725: + case 726: + case 727: + case 728: + return inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -408,11 +2060,9 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe (num_encoded_sources > 2 && inst_.src2 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_and_has_lit_1() || has_lit_2() || - has_lit_0_and_has_lit_2() || has_lit_1_and_has_lit_2() || - has_lit_0_and_has_lit_1_and_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -491,6 +2141,66 @@ bool Vop3::has_dpp16() { return (((inst_.src0 == 250) && (inst_.src1 != 255)) && (inst_.src2 != 255)); } +bool Vop3p::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 27: + case 28: + case 29: + case 30: + case 35: + case 40: + case 41: + case 42: + case 43: + case 44: + return inst_.src0 == 255 || inst_.src1 == 255; + case 0: + case 9: + case 14: + case 17: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 31: + case 32: + case 33: + case 34: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 54: + case 55: + case 56: + case 57: + case 61: + case 62: + case 63: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources, ExtensionDecodePolicy extension_policy) @@ -515,11 +2225,9 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn (num_encoded_sources > 2 && inst_.src2 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_and_has_lit_1() || has_lit_2() || - has_lit_0_and_has_lit_2() || has_lit_1_and_has_lit_2() || - has_lit_0_and_has_lit_1_and_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -681,6 +2389,25 @@ void Vglobal::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop3SdstEnc::has_encoded_literal32() const { + switch (inst_.op) { + case 288: + case 289: + case 290: + case 768: + case 769: + case 770: + return inst_.src0 == 255 || inst_.src1 == 255; + case 764: + case 765: + case 766: + case 767: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -699,11 +2426,9 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst (num_encoded_sources > 2 && inst_.src2 == 254))) throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_and_has_lit_1() || has_lit_2() || - has_lit_0_and_has_lit_2() || has_lit_1_and_has_lit_2() || - has_lit_0_and_has_lit_1_and_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h index b1eb33d346de..72a758545e66 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h @@ -380,6 +380,8 @@ class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + bool has_encoded_literal64() const; + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit64_0(); @@ -392,6 +394,8 @@ class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 2); + bool has_encoded_literal64() const; + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -427,6 +431,8 @@ class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 2); + bool has_encoded_literal64() const; + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -453,6 +459,8 @@ class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + bool has_encoded_literal64() const; + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -489,6 +497,8 @@ class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + bool has_encoded_literal64() const; + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); @@ -522,6 +532,8 @@ class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + bool has_encoded_literal64() const; + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -562,6 +574,7 @@ class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 3); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -593,6 +606,7 @@ class Vop3p : public IsaInstruction { Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 3, ExtensionDecodePolicy extension_policy = ExtensionDecodePolicy::Decode); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -668,6 +682,7 @@ class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn, LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 3); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.cpp index 9727dbcc24cc..d7db90e1f586 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include #include @@ -22,13 +23,79 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 48: + case 49: + case 52: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -38,13 +105,39 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 18: + case 19: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -88,13 +181,72 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 21; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 44: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -125,23 +277,168 @@ void Smem::build_modifiers(std::string &out) const { out += " dlc"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop1::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 1: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 51: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 63: + case 64: + case 66: + case 67: + case 68: + case 72: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + return true; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || has_encoded_sdwa() || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } -void Vop1::build_modifiers(std::string &out) const { - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); -} - void Vop1::implicit_uses(RegisterSet &uses) const { bool sdwa_preserve = sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE; @@ -156,6 +453,30 @@ void Vop1::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop1::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop1::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); +} + bool Vop1::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 && inst_.src0 != 249; @@ -163,18 +484,370 @@ bool Vop1::default_encoding() { bool Vop1::has_lit() { return inst_.src0 == 255; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vopc::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return true; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } +void Vopc::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vopc::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_source_attributes(out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vopc::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 && inst_.src0 != 249; @@ -182,13 +855,119 @@ bool Vopc::default_encoding() { bool Vopc::has_lit() { return inst_.src0 == 255; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 22: + case 24: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 47: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop2::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 22: + case 24: + case 26: + case 27: + case 28: + case 29: + case 30: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 47: + case 50: + case 51: + case 52: + case 53: + case 57: + case 58: + case 59: + return true; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || has_encoded_sdwa() || + has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -196,11 +975,6 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe raw_encoding_ = raw_words_.data(); } -void Vop2::build_modifiers(std::string &out) const { - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); -} - void Vop2::implicit_uses(RegisterSet &uses) const { bool sdwa_preserve = sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE; @@ -215,6 +989,30 @@ void Vop2::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop2::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop2::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); +} + bool Vop2::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 && inst_.src0 != 249; @@ -239,14 +1037,430 @@ Vintrp::Vintrp(std::string_view mnemonic, const VintrpMachineInst *inst, Execute bool Vintrp::default_encoding() { return true; } +bool Vop3::has_encoded_literal32() const { + switch (inst_.op) { + case 385: + case 387: + case 388: + case 389: + case 390: + case 391: + case 392: + case 394: + case 395: + case 396: + case 397: + case 398: + case 399: + case 400: + case 401: + case 402: + case 403: + case 404: + case 405: + case 406: + case 407: + case 408: + case 409: + case 410: + case 416: + case 417: + case 418: + case 419: + case 420: + case 421: + case 423: + case 426: + case 427: + case 430: + case 431: + case 433: + case 435: + case 436: + case 437: + case 438: + case 439: + case 440: + case 441: + case 442: + case 443: + case 444: + case 445: + case 446: + case 447: + case 448: + case 450: + case 464: + case 465: + case 466: + case 467: + case 468: + case 469: + case 470: + case 471: + case 472: + case 473: + case 474: + case 475: + case 476: + case 477: + case 478: + case 479: + case 480: + case 481: + case 482: + case 483: + case 484: + case 865: + return inst_.src0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + case 257: + case 258: + case 259: + case 260: + case 261: + case 262: + case 263: + case 264: + case 265: + case 266: + case 267: + case 268: + case 269: + case 271: + case 272: + case 273: + case 274: + case 275: + case 276: + case 278: + case 280: + case 282: + case 283: + case 284: + case 285: + case 286: + case 287: + case 293: + case 294: + case 295: + case 299: + case 303: + case 306: + case 307: + case 308: + case 309: + case 310: + case 313: + case 314: + case 315: + case 356: + case 357: + case 358: + case 359: + case 360: + case 361: + case 362: + case 364: + case 372: + case 373: + case 767: + case 768: + case 769: + case 771: + case 772: + case 773: + case 775: + case 776: + case 777: + case 778: + case 779: + case 780: + case 781: + case 782: + case 785: + case 786: + case 787: + case 788: + case 866: + case 867: + case 868: + case 869: + case 870: + case 872: + case 873: + case 874: + case 875: + case 886: + case 895: + return inst_.src0 == 255 || inst_.src1 == 255; + case 320: + case 321: + case 322: + case 323: + case 324: + case 325: + case 326: + case 327: + case 328: + case 329: + case 330: + case 331: + case 332: + case 333: + case 334: + case 335: + case 336: + case 337: + case 338: + case 339: + case 340: + case 341: + case 342: + case 343: + case 344: + case 345: + case 346: + case 347: + case 348: + case 349: + case 350: + case 351: + case 352: + case 367: + case 368: + case 369: + case 370: + case 371: + case 376: + case 832: + case 836: + case 837: + case 838: + case 839: + case 843: + case 849: + case 850: + case 851: + case 852: + case 853: + case 854: + case 855: + case 856: + case 857: + case 862: + case 863: + case 877: + case 879: + case 881: + case 882: + case 883: + case 885: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + case 887: + case 888: + return inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -274,14 +1488,51 @@ bool Vop3::has_lit_0_has_lit_1_has_lit_2() { return inst_.src0 == 255 && inst_.src1 == 255 && inst_.src2 == 255; } +bool Vop3p::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 17: + case 18: + return inst_.src0 == 255 || inst_.src1 == 255; + case 0: + case 9: + case 14: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 32: + case 33: + case 34: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -421,6 +1672,25 @@ void Flat::implicit_uses(RegisterSet &uses) const { } } +bool Vop3SdstEnc::has_encoded_literal32() const { + switch (inst_.op) { + case 296: + case 297: + case 298: + case 783: + case 784: + case 793: + return inst_.src0 == 255 || inst_.src1 == 255; + case 365: + case 366: + case 374: + case 375: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -428,8 +1698,7 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h index fbfd05c33af5..bac9b161e9dc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h @@ -368,6 +368,7 @@ inline constexpr uint16_t kVop3SdstEncOpHi4 = 430; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -378,6 +379,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -409,6 +411,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -429,8 +432,11 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); - void build_modifiers(std::string &out) const override; + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); using OpEncoding = Vop1MachineInst; @@ -452,14 +458,23 @@ class Vop1 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); using OpEncoding = VopcMachineInst; @@ -480,6 +495,10 @@ class Vopc : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_sdst_ = 106; bool sdwa_sd_ = false; }; @@ -487,8 +506,11 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); - void build_modifiers(std::string &out) const override; + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool hasImpliedLiteral(); @@ -512,9 +534,14 @@ class Vop2 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vintrp : public IsaInstruction { @@ -528,6 +555,7 @@ class Vintrp : public IsaInstruction { class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool has_lit_0(); bool has_lit_1(); bool has_lit_0_has_lit_1(); @@ -543,6 +571,7 @@ class Vop3 : public IsaInstruction { class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool has_lit_0(); bool has_lit_1(); bool has_lit_0_has_lit_1(); @@ -608,6 +637,7 @@ class Flat : public IsaInstruction { class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool has_lit_0(); bool has_lit_1(); bool has_lit_0_has_lit_1(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp index 1e89adc5cc3a..7ba174a19384 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp @@ -29,7 +29,8 @@ std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { } // namespace detail VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mov_b32_dpp" : "v_mov_b32_e32", reinterpret_cast(inst), @@ -72,9 +73,12 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -169,7 +173,9 @@ std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_i32_dpp" : "v_cvt_f32_i32_e32", reinterpret_cast(inst), @@ -212,9 +218,12 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -225,7 +234,9 @@ std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_u32_dpp" : "v_cvt_f32_u32_e32", reinterpret_cast(inst), @@ -268,9 +279,12 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -281,7 +295,9 @@ std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { } // namespace detail VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_u32_f32_dpp" : "v_cvt_u32_f32_e32", reinterpret_cast(inst), @@ -324,9 +340,12 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -337,7 +356,9 @@ std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_i32_f32_dpp" : "v_cvt_i32_f32_e32", reinterpret_cast(inst), @@ -380,9 +401,12 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -393,7 +417,9 @@ std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f16_f32_dpp" : "v_cvt_f16_f32_e32", reinterpret_cast(inst), @@ -436,9 +462,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -455,7 +484,9 @@ void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_f16_dpp" : "v_cvt_f32_f16_e32", reinterpret_cast(inst), @@ -499,9 +530,12 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -512,7 +546,9 @@ std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { } // namespace detail VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_rpi_i32_f32_dpp" : "v_cvt_rpi_i32_f32_e32", reinterpret_cast(inst), @@ -555,9 +591,12 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -568,7 +607,9 @@ std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_flr_i32_f32_dpp" : "v_cvt_flr_i32_f32_e32", reinterpret_cast(inst), @@ -611,9 +652,12 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -624,7 +668,9 @@ std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_off_f32_i4_dpp" : "v_cvt_off_f32_i4_e32", reinterpret_cast(inst), @@ -667,9 +713,12 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -739,7 +788,9 @@ std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte0_dpp" : "v_cvt_f32_ubyte0_e32", reinterpret_cast(inst), @@ -782,9 +833,12 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -795,7 +849,9 @@ std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte1_dpp" : "v_cvt_f32_ubyte1_e32", reinterpret_cast(inst), @@ -838,9 +894,12 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -851,7 +910,9 @@ std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte2_dpp" : "v_cvt_f32_ubyte2_e32", reinterpret_cast(inst), @@ -894,9 +955,12 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -907,7 +971,9 @@ std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte3_dpp" : "v_cvt_f32_ubyte3_e32", reinterpret_cast(inst), @@ -950,9 +1016,12 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1158,7 +1227,8 @@ std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { } // namespace detail VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_fract_f32_dpp" : "v_fract_f32_e32", reinterpret_cast(inst), @@ -1201,9 +1271,12 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1214,7 +1287,8 @@ std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { } // namespace detail VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_trunc_f32_dpp" : "v_trunc_f32_e32", reinterpret_cast(inst), @@ -1257,9 +1331,12 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1270,7 +1347,8 @@ std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { } // namespace detail VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ceil_f32_dpp" : "v_ceil_f32_e32", reinterpret_cast(inst), @@ -1313,9 +1391,12 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1326,7 +1407,8 @@ std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { } // namespace detail VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rndne_f32_dpp" : "v_rndne_f32_e32", reinterpret_cast(inst), @@ -1369,9 +1451,12 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1382,7 +1467,8 @@ std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { } // namespace detail VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_floor_f32_dpp" : "v_floor_f32_e32", reinterpret_cast(inst), @@ -1425,9 +1511,12 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1438,7 +1527,8 @@ std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { } // namespace detail VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_exp_f32_dpp" : "v_exp_f32_e32", reinterpret_cast(inst), @@ -1481,9 +1571,12 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1494,7 +1587,8 @@ std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { } // namespace detail VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_log_f32_dpp" : "v_log_f32_e32", reinterpret_cast(inst), @@ -1537,9 +1631,12 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1550,7 +1647,8 @@ std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rcp_f32_dpp" : "v_rcp_f32_e32", reinterpret_cast(inst), @@ -1593,9 +1691,12 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1606,7 +1707,9 @@ std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rcp_iflag_f32_dpp" : "v_rcp_iflag_f32_e32", reinterpret_cast(inst), @@ -1649,9 +1752,12 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1662,7 +1768,8 @@ std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { } // namespace detail VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rsq_f32_dpp" : "v_rsq_f32_e32", reinterpret_cast(inst), @@ -1705,9 +1812,12 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1778,7 +1888,8 @@ std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { } // namespace detail VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sqrt_f32_dpp" : "v_sqrt_f32_e32", reinterpret_cast(inst), @@ -1821,9 +1932,12 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1864,7 +1978,8 @@ std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { } // namespace detail VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sin_f32_dpp" : "v_sin_f32_e32", reinterpret_cast(inst), @@ -1907,9 +2022,12 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1920,7 +2038,8 @@ std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { } // namespace detail VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cos_f32_dpp" : "v_cos_f32_e32", reinterpret_cast(inst), @@ -1963,9 +2082,12 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1976,7 +2098,8 @@ std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { } // namespace detail VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_not_b32_dpp" : "v_not_b32_e32", reinterpret_cast(inst), @@ -2019,9 +2142,12 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2032,7 +2158,8 @@ std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { } // namespace detail VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_bfrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_bfrev_b32_dpp" : "v_bfrev_b32_e32", reinterpret_cast(inst), @@ -2075,9 +2202,12 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2088,7 +2218,8 @@ std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ffbh_u32_dpp" : "v_ffbh_u32_e32", reinterpret_cast(inst), @@ -2131,9 +2262,12 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2144,7 +2278,8 @@ std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { } // namespace detail VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ffbl_b32_dpp" : "v_ffbl_b32_e32", reinterpret_cast(inst), @@ -2187,9 +2322,12 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2200,7 +2338,8 @@ std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ffbh_i32_dpp" : "v_ffbh_i32_e32", reinterpret_cast(inst), @@ -2243,9 +2382,12 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2346,7 +2488,9 @@ std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { } // namespace detail VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_exp_i32_f32_dpp" : "v_frexp_exp_i32_f32_e32", reinterpret_cast(inst), @@ -2389,9 +2533,12 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2402,7 +2549,9 @@ std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode } // namespace detail VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_mant_f32_dpp" : "v_frexp_mant_f32_e32", reinterpret_cast(inst), @@ -2445,9 +2594,12 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2474,7 +2626,9 @@ std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { } // namespace detail VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movreld_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movreld_b32_dpp" : "v_movreld_b32_e32", reinterpret_cast(inst), @@ -2519,9 +2673,12 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2533,7 +2690,9 @@ std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { } // namespace detail VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrels_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movrels_b32_dpp" : "v_movrels_b32_e32", reinterpret_cast(inst), @@ -2574,9 +2733,12 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2588,7 +2750,9 @@ std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { } // namespace detail VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movrelsd_b32_dpp" : "v_movrelsd_b32_e32", reinterpret_cast(inst), @@ -2629,9 +2793,12 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2643,7 +2810,9 @@ std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { } // namespace detail VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_2_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movrelsd_2_b32_dpp" : "v_movrelsd_2_b32_e32", reinterpret_cast(inst), @@ -2684,9 +2853,12 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2698,7 +2870,9 @@ std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) } // namespace detail VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f16_u16_dpp" : "v_cvt_f16_u16_e32", reinterpret_cast(inst), @@ -2742,9 +2916,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2761,7 +2938,9 @@ void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f16_i16_dpp" : "v_cvt_f16_i16_e32", reinterpret_cast(inst), @@ -2805,9 +2984,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2824,7 +3006,9 @@ void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_u16_f16_dpp" : "v_cvt_u16_f16_e32", reinterpret_cast(inst), @@ -2868,9 +3052,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2887,7 +3074,9 @@ void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_i16_f16_dpp" : "v_cvt_i16_f16_e32", reinterpret_cast(inst), @@ -2931,9 +3120,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2950,7 +3142,8 @@ void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rcp_f16_dpp" : "v_rcp_f16_e32", reinterpret_cast(inst), @@ -2994,9 +3187,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3013,7 +3209,8 @@ void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { } VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sqrt_f16_dpp" : "v_sqrt_f16_e32", reinterpret_cast(inst), @@ -3057,9 +3254,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3076,7 +3276,8 @@ void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { } VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rsq_f16_dpp" : "v_rsq_f16_e32", reinterpret_cast(inst), @@ -3120,9 +3321,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3139,7 +3343,8 @@ void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { } VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_log_f16_dpp" : "v_log_f16_e32", reinterpret_cast(inst), @@ -3183,9 +3388,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3202,7 +3410,8 @@ void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_exp_f16_dpp" : "v_exp_f16_e32", reinterpret_cast(inst), @@ -3246,9 +3455,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3265,7 +3477,9 @@ void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_mant_f16_dpp" : "v_frexp_mant_f16_e32", reinterpret_cast(inst), @@ -3309,9 +3523,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3328,7 +3545,9 @@ void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_exp_i16_f16_dpp" : "v_frexp_exp_i16_f16_e32", reinterpret_cast(inst), @@ -3372,9 +3591,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3391,7 +3613,8 @@ void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_floor_f16_dpp" : "v_floor_f16_e32", reinterpret_cast(inst), @@ -3435,9 +3658,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3454,7 +3680,8 @@ void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { } VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ceil_f16_dpp" : "v_ceil_f16_e32", reinterpret_cast(inst), @@ -3498,9 +3725,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3517,7 +3747,8 @@ void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { } VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_trunc_f16_dpp" : "v_trunc_f16_e32", reinterpret_cast(inst), @@ -3561,9 +3792,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3580,7 +3814,8 @@ void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { } VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rndne_f16_dpp" : "v_rndne_f16_e32", reinterpret_cast(inst), @@ -3624,9 +3859,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3643,7 +3881,8 @@ void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { } VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_fract_f16_dpp" : "v_fract_f16_e32", reinterpret_cast(inst), @@ -3687,9 +3926,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3706,7 +3948,8 @@ void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { } VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sin_f16_dpp" : "v_sin_f16_e32", reinterpret_cast(inst), @@ -3750,9 +3993,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3769,7 +4015,8 @@ void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { } VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cos_f16_dpp" : "v_cos_f16_e32", reinterpret_cast(inst), @@ -3813,9 +4060,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3832,7 +4082,9 @@ void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { } VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sat_pk_u8_i16_dpp" : "v_sat_pk_u8_i16_e32", reinterpret_cast(inst), @@ -3875,9 +4127,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3888,7 +4143,9 @@ std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { } // namespace detail VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_norm_i16_f16_dpp" : "v_cvt_norm_i16_f16_e32", reinterpret_cast(inst), @@ -3932,9 +4189,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3951,7 +4211,9 @@ void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_norm_u16_f16_dpp" : "v_cvt_norm_u16_f16_e32", reinterpret_cast(inst), @@ -3995,9 +4257,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp index b0add1f7f77c..3913a0d2f21f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace rdna1 { VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cndmask_b32_dpp" : "v_cndmask_b32_e32", reinterpret_cast(inst), @@ -61,9 +63,14 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -123,7 +130,8 @@ std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { } // namespace detail VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_f32_dpp" : "v_add_f32_e32", reinterpret_cast(inst), @@ -168,9 +176,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -183,7 +196,8 @@ std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { } // namespace detail VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_f32_dpp" : "v_sub_f32_e32", reinterpret_cast(inst), @@ -228,9 +242,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -243,7 +262,9 @@ std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_f32_dpp" : "v_subrev_f32_e32", reinterpret_cast(inst), @@ -288,9 +309,14 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -335,7 +361,9 @@ std::unique_ptr decodeVMacLegacyF32Vop2(const MachineInst *opcode) } // namespace detail VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_legacy_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_legacy_f32_dpp" : "v_mul_legacy_f32_e32", reinterpret_cast(inst), @@ -380,9 +408,14 @@ VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -395,7 +428,8 @@ std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode) } // namespace detail VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_f32_dpp" : "v_mul_f32_e32", reinterpret_cast(inst), @@ -440,9 +474,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -455,7 +494,9 @@ std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { } // namespace detail VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_i32_i24_dpp" : "v_mul_i32_i24_e32", reinterpret_cast(inst), @@ -500,9 +541,14 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -515,7 +561,9 @@ std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_hi_i32_i24_dpp" : "v_mul_hi_i32_i24_e32", reinterpret_cast(inst), @@ -560,9 +608,14 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -575,7 +628,9 @@ std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_u32_u24_dpp" : "v_mul_u32_u24_e32", reinterpret_cast(inst), @@ -620,9 +675,14 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -635,7 +695,9 @@ std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_hi_u32_u24_dpp" : "v_mul_hi_u32_u24_e32", reinterpret_cast(inst), @@ -680,9 +742,14 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -741,7 +808,8 @@ std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { } // namespace detail VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_f32_dpp" : "v_min_f32_e32", reinterpret_cast(inst), @@ -786,9 +854,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -801,7 +874,8 @@ std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { } // namespace detail VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_f32_dpp" : "v_max_f32_e32", reinterpret_cast(inst), @@ -846,9 +920,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -861,7 +940,8 @@ std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { } // namespace detail VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_i32_dpp" : "v_min_i32_e32", reinterpret_cast(inst), @@ -906,9 +986,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -921,7 +1006,8 @@ std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { } // namespace detail VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_i32_dpp" : "v_max_i32_e32", reinterpret_cast(inst), @@ -966,9 +1052,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -981,7 +1072,8 @@ std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { } // namespace detail VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_u32_dpp" : "v_min_u32_e32", reinterpret_cast(inst), @@ -1026,9 +1118,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1041,7 +1138,8 @@ std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { } // namespace detail VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_u32_dpp" : "v_max_u32_e32", reinterpret_cast(inst), @@ -1086,9 +1184,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1101,7 +1204,9 @@ std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { } // namespace detail VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_lshrrev_b32_dpp" : "v_lshrrev_b32_e32", reinterpret_cast(inst), @@ -1146,9 +1251,14 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1161,7 +1271,9 @@ std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ashrrev_i32_dpp" : "v_ashrrev_i32_e32", reinterpret_cast(inst), @@ -1206,9 +1318,14 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1221,7 +1338,9 @@ std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { } // namespace detail VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_lshlrev_b32_dpp" : "v_lshlrev_b32_e32", reinterpret_cast(inst), @@ -1266,9 +1385,14 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1281,7 +1405,8 @@ std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_and_b32_dpp" : "v_and_b32_e32", reinterpret_cast(inst), @@ -1326,9 +1451,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1341,7 +1471,8 @@ std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { } // namespace detail VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_or_b32_dpp" : "v_or_b32_e32", reinterpret_cast(inst), @@ -1386,9 +1517,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1401,7 +1537,8 @@ std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { } // namespace detail VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_xor_b32_dpp" : "v_xor_b32_e32", reinterpret_cast(inst), @@ -1446,9 +1583,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1461,7 +1603,8 @@ std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { } // namespace detail VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_xnor_b32_dpp" : "v_xnor_b32_e32", reinterpret_cast(inst), @@ -1506,9 +1649,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1641,7 +1789,9 @@ std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode) { } // namespace detail VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_nc_u32_dpp" : "v_add_nc_u32_e32", reinterpret_cast(inst), @@ -1686,9 +1836,14 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1701,7 +1856,9 @@ std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { } // namespace detail VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_nc_u32_dpp" : "v_sub_nc_u32_e32", reinterpret_cast(inst), @@ -1746,9 +1903,14 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1761,7 +1923,9 @@ std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_nc_u32_dpp" : "v_subrev_nc_u32_e32", reinterpret_cast(inst), @@ -1806,9 +1970,14 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1821,7 +1990,9 @@ std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { } // namespace detail VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_co_ci_u32_dpp" : "v_add_co_ci_u32_e32", reinterpret_cast(inst), @@ -1870,9 +2041,14 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1887,7 +2063,9 @@ std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { } // namespace detail VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_co_ci_u32_dpp" : "v_sub_co_ci_u32_e32", reinterpret_cast(inst), @@ -1936,9 +2114,14 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1953,7 +2136,9 @@ std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_co_ci_u32_dpp" : "v_subrev_co_ci_u32_e32", reinterpret_cast(inst), @@ -2002,9 +2187,14 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2139,7 +2329,9 @@ std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { } // namespace detail VCvtPkrtzF16F32Vop2::VCvtPkrtzF16F32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pkrtz_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_pkrtz_f16_f32_dpp" : "v_cvt_pkrtz_f16_f32_e32", reinterpret_cast(inst), @@ -2184,9 +2376,14 @@ VCvtPkrtzF16F32Vop2::VCvtPkrtzF16F32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2199,7 +2396,8 @@ std::unique_ptr decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode } // namespace detail VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_f16_dpp" : "v_add_f16_e32", reinterpret_cast(inst), @@ -2245,9 +2443,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2266,7 +2469,8 @@ void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_f16_dpp" : "v_sub_f16_e32", reinterpret_cast(inst), @@ -2312,9 +2516,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2333,7 +2542,9 @@ void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_f16_dpp" : "v_subrev_f16_e32", reinterpret_cast(inst), @@ -2379,9 +2590,14 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2400,7 +2616,8 @@ void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { } VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_f16_dpp" : "v_mul_f16_e32", reinterpret_cast(inst), @@ -2446,9 +2663,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2610,7 +2832,8 @@ void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_f16_dpp" : "v_max_f16_e32", reinterpret_cast(inst), @@ -2656,9 +2879,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2677,7 +2905,8 @@ void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { } VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_f16_dpp" : "v_min_f16_e32", reinterpret_cast(inst), @@ -2723,9 +2952,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2744,7 +2978,8 @@ void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { } VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ldexp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ldexp_f16_dpp" : "v_ldexp_f16_e32", reinterpret_cast(inst), @@ -2790,9 +3025,14 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp index 63b1d3b4104d..dd47ddaf752e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace rdna1 { VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -42,12 +44,19 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -57,7 +66,10 @@ std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -85,12 +97,19 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -100,7 +119,10 @@ std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -128,12 +150,19 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -143,7 +172,10 @@ std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -171,12 +203,19 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -186,7 +225,10 @@ std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -214,12 +256,19 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -229,7 +278,10 @@ std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -257,12 +309,19 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -272,7 +331,10 @@ std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -300,12 +362,19 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -315,7 +384,9 @@ std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -343,12 +414,19 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -358,7 +436,9 @@ std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -386,12 +466,19 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -401,7 +488,10 @@ std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -429,12 +519,19 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -444,7 +541,10 @@ std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -472,12 +572,19 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -487,7 +594,10 @@ std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -515,12 +625,19 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -530,7 +647,10 @@ std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -558,12 +678,19 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -573,7 +700,10 @@ std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -601,12 +731,19 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -616,7 +753,10 @@ std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -644,12 +784,19 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -659,7 +806,10 @@ std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -687,12 +837,19 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -702,7 +859,10 @@ std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -732,12 +892,19 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -749,7 +916,10 @@ std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -779,12 +949,19 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -796,7 +973,10 @@ std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -826,12 +1006,19 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -843,7 +1030,10 @@ std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -873,12 +1063,19 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -890,7 +1087,10 @@ std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -920,12 +1120,19 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -937,7 +1144,10 @@ std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -967,12 +1177,19 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -984,7 +1201,10 @@ std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1014,12 +1234,19 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1031,7 +1258,10 @@ std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1061,12 +1291,19 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1078,7 +1315,10 @@ std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1108,12 +1348,19 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1125,7 +1372,10 @@ std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1155,12 +1405,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1172,7 +1429,10 @@ std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1202,12 +1462,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1219,7 +1486,10 @@ std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1249,12 +1519,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1266,7 +1543,10 @@ std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1296,12 +1576,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1313,7 +1600,10 @@ std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1343,12 +1633,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1360,7 +1657,10 @@ std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1390,12 +1690,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1407,7 +1714,10 @@ std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1437,12 +1747,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2478,7 +2795,9 @@ std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2506,12 +2825,19 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2521,7 +2847,10 @@ std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2549,12 +2878,19 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2564,7 +2900,10 @@ std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2592,12 +2931,19 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2607,7 +2953,10 @@ std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2635,12 +2984,19 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2650,7 +3006,10 @@ std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2678,12 +3037,19 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2693,7 +3059,10 @@ std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2721,12 +3090,19 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2736,7 +3112,10 @@ std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2764,12 +3143,19 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2779,7 +3165,9 @@ std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2807,12 +3195,19 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2822,7 +3217,10 @@ std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2850,12 +3248,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2865,7 +3270,10 @@ std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2894,12 +3302,19 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2909,7 +3324,10 @@ std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2938,12 +3356,19 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2953,7 +3378,10 @@ std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2982,12 +3410,19 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2997,7 +3432,10 @@ std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3026,12 +3464,19 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3041,7 +3486,10 @@ std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3070,12 +3518,19 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3085,7 +3540,10 @@ std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3114,12 +3572,19 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3129,7 +3594,10 @@ std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3158,12 +3626,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3173,7 +3648,10 @@ std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3203,12 +3681,19 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3220,7 +3705,10 @@ std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3250,12 +3738,19 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3267,7 +3762,10 @@ std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3297,12 +3795,19 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3314,7 +3819,10 @@ std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3344,12 +3852,19 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3361,7 +3876,10 @@ std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3391,12 +3909,19 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3408,7 +3933,10 @@ std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3438,12 +3966,19 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3455,7 +3990,10 @@ std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3485,12 +4023,19 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3502,7 +4047,10 @@ std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3532,12 +4080,19 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3549,7 +4104,10 @@ std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3579,12 +4137,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3596,7 +4161,10 @@ std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) } // namespace detail VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3627,12 +4195,19 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3644,7 +4219,10 @@ std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3675,12 +4253,19 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3692,7 +4277,10 @@ std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3723,12 +4311,19 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3740,7 +4335,10 @@ std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3771,12 +4369,19 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3788,7 +4393,10 @@ std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3819,12 +4427,19 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3836,7 +4451,10 @@ std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3867,12 +4485,19 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3884,7 +4509,10 @@ std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3915,12 +4543,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4202,7 +4837,10 @@ std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4231,12 +4869,19 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4246,7 +4891,10 @@ std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4275,12 +4923,19 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4290,7 +4945,10 @@ std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4319,12 +4977,19 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4334,7 +4999,10 @@ std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4363,12 +5031,19 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4378,7 +5053,10 @@ std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4407,12 +5085,19 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4422,7 +5107,10 @@ std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4451,12 +5139,19 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4772,7 +5467,10 @@ std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) } // namespace detail VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4803,12 +5501,19 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4820,7 +5525,10 @@ std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4851,12 +5559,19 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4868,7 +5583,10 @@ std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4899,12 +5617,19 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4916,7 +5641,10 @@ std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4947,12 +5675,19 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4964,7 +5699,10 @@ std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4995,12 +5733,19 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5012,7 +5757,10 @@ std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5043,12 +5791,19 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5060,7 +5815,9 @@ std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5088,12 +5845,19 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5103,7 +5867,10 @@ std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5131,12 +5898,19 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5146,7 +5920,10 @@ std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5174,12 +5951,19 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5189,7 +5973,10 @@ std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5217,12 +6004,19 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5232,7 +6026,10 @@ std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5260,12 +6057,19 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5275,7 +6079,10 @@ std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5303,12 +6110,19 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5318,7 +6132,10 @@ std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5346,12 +6163,19 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5361,7 +6185,9 @@ std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5389,12 +6215,19 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5404,7 +6237,9 @@ std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5433,12 +6268,19 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5448,7 +6290,10 @@ std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5477,12 +6322,19 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5492,7 +6344,10 @@ std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5521,12 +6376,19 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5536,7 +6398,10 @@ std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5565,12 +6430,19 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5580,7 +6452,10 @@ std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5609,12 +6484,19 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5624,7 +6506,10 @@ std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5653,12 +6538,19 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5668,7 +6560,10 @@ std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5697,12 +6592,19 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5712,7 +6614,9 @@ std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5741,12 +6645,19 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5756,7 +6667,10 @@ std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5786,12 +6700,19 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5803,7 +6724,10 @@ std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5833,12 +6757,19 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5850,7 +6781,10 @@ std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5880,12 +6814,19 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5897,7 +6838,10 @@ std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5927,12 +6871,19 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5944,7 +6895,10 @@ std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5974,12 +6928,19 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5991,7 +6952,10 @@ std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6021,12 +6985,19 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6038,7 +7009,10 @@ std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6068,12 +7042,19 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6085,7 +7066,10 @@ std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6115,12 +7099,19 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6132,7 +7123,10 @@ std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6163,12 +7157,19 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6180,7 +7181,10 @@ std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6211,12 +7215,19 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6228,7 +7239,10 @@ std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6259,12 +7273,19 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6276,7 +7297,10 @@ std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6307,12 +7331,19 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6324,7 +7355,10 @@ std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6355,12 +7389,19 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6372,7 +7413,10 @@ std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6403,12 +7447,19 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6420,7 +7471,10 @@ std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6451,12 +7505,19 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6468,7 +7529,10 @@ std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6499,12 +7563,19 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6756,7 +7827,9 @@ std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6785,12 +7858,19 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6800,7 +7880,10 @@ std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6829,12 +7912,19 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6844,7 +7934,10 @@ std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6873,12 +7966,19 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6888,7 +7988,10 @@ std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6917,12 +8020,19 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6932,7 +8042,10 @@ std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6961,12 +8074,19 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6976,7 +8096,10 @@ std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7005,12 +8128,19 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -7020,7 +8150,10 @@ std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7049,12 +8182,19 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -7064,7 +8204,10 @@ std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7093,12 +8236,19 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -7380,7 +8530,10 @@ std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7411,12 +8564,19 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7428,7 +8588,10 @@ std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7459,12 +8622,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7476,7 +8646,10 @@ std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7507,12 +8680,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7524,7 +8704,10 @@ std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7555,12 +8738,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7572,7 +8762,10 @@ std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7603,12 +8796,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7620,7 +8820,10 @@ std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7651,12 +8854,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7668,7 +8878,10 @@ std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7699,12 +8912,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7716,7 +8936,10 @@ std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7747,12 +8970,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.cpp index 1ddf7e7c3b86..c5259c7ff8a4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.cpp @@ -5,6 +5,7 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include #include @@ -22,13 +23,79 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 48: + case 49: + case 52: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -38,13 +105,39 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 18: + case 19: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -88,13 +181,72 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 21; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 44: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -125,23 +277,168 @@ void Smem::build_modifiers(std::string &out) const { out += " dlc"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop1::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 1: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 51: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 63: + case 64: + case 66: + case 67: + case 68: + case 72: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + return true; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || has_encoded_sdwa() || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } -void Vop1::build_modifiers(std::string &out) const { - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); -} - void Vop1::implicit_uses(RegisterSet &uses) const { bool sdwa_preserve = sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE; @@ -156,6 +453,30 @@ void Vop1::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop1::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop1::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); +} + bool Vop1::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 && inst_.src0 != 249; @@ -163,18 +484,370 @@ bool Vop1::default_encoding() { bool Vop1::has_lit() { return inst_.src0 == 255; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vopc::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + return true; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_sdwa() || has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } +void Vopc::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vopc::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_source_attributes(out, sdwa_src0_sel_, sdwa_src1_operand_, sdwa_src1_sel_); +} + bool Vopc::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 && inst_.src0 != 249; @@ -182,13 +855,116 @@ bool Vopc::default_encoding() { bool Vopc::has_lit() { return inst_.src0 == 255; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 22: + case 24: + case 26: + case 27: + case 28: + case 29: + case 30: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 47: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + return inst_.src0 == 255; + default: + return false; + } +} + +bool Vop2::has_encoded_sdwa() const { + if (!(inst_.src0 == amdgpu::SRC_SDWA)) + return false; + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 22: + case 24: + case 26: + case 27: + case 28: + case 29: + case 30: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 47: + case 50: + case 51: + case 52: + case 53: + case 57: + case 58: + case 59: + return true; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || has_encoded_sdwa() || + has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -196,11 +972,6 @@ Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exe raw_encoding_ = raw_words_.data(); } -void Vop2::build_modifiers(std::string &out) const { - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); -} - void Vop2::implicit_uses(RegisterSet &uses) const { bool sdwa_preserve = sdwa_dst_sel_ != amdgpu::sdwa::DWORD && sdwa_dst_unused_ == amdgpu::sdwa::UNUSED_PRESERVE; @@ -215,6 +986,30 @@ void Vop2::implicit_uses(RegisterSet &uses) const { uses.expand(*ref); } +void Vop2::append_src_operand(std::string &out, uint8_t operand_index) const { + const Operand *operand = src_operands_[operand_index]; + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src0_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src0_format_, sdwa_src0_sext_, sdwa_src0_neg_, + sdwa_src0_abs_); + return; + } + if (inst_.src0 == amdgpu::SRC_SDWA && operand == sdwa_src1_operand_) { + amdgpu::sdwa::append_source(out, *operand, sdwa_src1_format_, sdwa_src1_sext_, sdwa_src1_neg_, + sdwa_src1_abs_); + return; + } + Instruction::append_src_operand(out, operand_index); +} + +void Vop2::build_modifiers(std::string &out) const { + if (inst_.src0 == amdgpu::SRC_SDWA) + amdgpu::sdwa::append_destination_attributes(out, sdwa_clamp_, sdwa_omod_, sdwa_dst_sel_, + sdwa_dst_unused_, sdwa_src0_sel_, + sdwa_src1_operand_, sdwa_src1_sel_); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::append_dpp8_disassembly(out, dpp8_lane_sel_, dpp_fi_); +} + bool Vop2::default_encoding() { return inst_.src0 != 250 && inst_.src0 != 233 && inst_.src0 != 234 && inst_.src0 != 255 && inst_.src0 != 249; @@ -238,14 +1033,426 @@ Vintrp::Vintrp(std::string_view mnemonic, const VintrpMachineInst *inst, Execute bool Vintrp::default_encoding() { return true; } +bool Vop3::has_encoded_literal32() const { + switch (inst_.op) { + case 385: + case 387: + case 388: + case 389: + case 390: + case 391: + case 392: + case 394: + case 395: + case 396: + case 397: + case 398: + case 399: + case 400: + case 401: + case 402: + case 403: + case 404: + case 405: + case 406: + case 407: + case 408: + case 409: + case 410: + case 416: + case 417: + case 418: + case 419: + case 420: + case 421: + case 423: + case 426: + case 427: + case 430: + case 431: + case 433: + case 435: + case 436: + case 437: + case 438: + case 439: + case 440: + case 441: + case 442: + case 443: + case 444: + case 445: + case 446: + case 447: + case 448: + case 450: + case 464: + case 465: + case 466: + case 467: + case 468: + case 469: + case 470: + case 471: + case 472: + case 473: + case 474: + case 475: + case 476: + case 477: + case 478: + case 479: + case 480: + case 481: + case 482: + case 483: + case 484: + case 865: + return inst_.src0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 176: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 183: + case 184: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 224: + case 225: + case 226: + case 227: + case 228: + case 229: + case 230: + case 231: + case 232: + case 233: + case 234: + case 235: + case 236: + case 237: + case 238: + case 239: + case 240: + case 241: + case 242: + case 243: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: + case 250: + case 251: + case 252: + case 253: + case 254: + case 255: + case 257: + case 259: + case 260: + case 261: + case 262: + case 263: + case 264: + case 265: + case 266: + case 267: + case 268: + case 271: + case 272: + case 273: + case 274: + case 275: + case 276: + case 278: + case 280: + case 282: + case 283: + case 284: + case 285: + case 286: + case 293: + case 294: + case 295: + case 299: + case 303: + case 306: + case 307: + case 308: + case 309: + case 310: + case 313: + case 314: + case 315: + case 356: + case 357: + case 358: + case 359: + case 360: + case 361: + case 362: + case 364: + case 372: + case 373: + case 767: + case 768: + case 769: + case 771: + case 772: + case 773: + case 775: + case 776: + case 777: + case 778: + case 779: + case 780: + case 781: + case 782: + case 785: + case 786: + case 787: + case 788: + case 866: + case 867: + case 868: + case 869: + case 870: + case 872: + case 873: + case 874: + case 875: + case 886: + case 895: + return inst_.src0 == 255 || inst_.src1 == 255; + case 320: + case 322: + case 323: + case 324: + case 325: + case 326: + case 327: + case 328: + case 329: + case 330: + case 331: + case 332: + case 333: + case 334: + case 335: + case 336: + case 337: + case 338: + case 339: + case 340: + case 341: + case 342: + case 343: + case 344: + case 345: + case 346: + case 347: + case 348: + case 349: + case 350: + case 351: + case 352: + case 367: + case 368: + case 369: + case 370: + case 371: + case 376: + case 832: + case 836: + case 837: + case 838: + case 839: + case 843: + case 849: + case 850: + case 851: + case 852: + case 853: + case 854: + case 855: + case 856: + case 857: + case 862: + case 863: + case 877: + case 879: + case 881: + case 882: + case 883: + case 885: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + case 887: + case 888: + return inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -273,14 +1480,51 @@ bool Vop3::has_lit_0_has_lit_1_has_lit_2() { return inst_.src0 == 255 && inst_.src1 == 255 && inst_.src2 == 255; } +bool Vop3p::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 17: + case 18: + return inst_.src0 == 255 || inst_.src1 == 255; + case 0: + case 9: + case 14: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 32: + case 33: + case 34: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -420,6 +1664,25 @@ void Flat::implicit_uses(RegisterSet &uses) const { } } +bool Vop3SdstEnc::has_encoded_literal32() const { + switch (inst_.op) { + case 296: + case 297: + case 298: + case 783: + case 784: + case 793: + return inst_.src0 == 255 || inst_.src1 == 255; + case 365: + case 366: + case 374: + case 375: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -427,8 +1690,7 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h index f65ee729ded5..0e60f5d4701a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h @@ -364,6 +364,7 @@ inline constexpr uint16_t kVop3SdstEncOpHi4 = 430; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -374,6 +375,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -405,6 +407,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -425,8 +428,11 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); - void build_modifiers(std::string &out) const override; + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); using OpEncoding = Vop1MachineInst; @@ -448,14 +454,23 @@ class Vop1 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); using OpEncoding = VopcMachineInst; @@ -476,6 +491,10 @@ class Vopc : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_sdst_ = 106; bool sdwa_sd_ = false; }; @@ -483,8 +502,11 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); - void build_modifiers(std::string &out) const override; + bool has_encoded_literal32() const; + bool has_encoded_sdwa() const; void implicit_uses(RegisterSet &uses) const override; + void append_src_operand(std::string &out, uint8_t operand_index) const override; + void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); bool hasImpliedLiteral(); @@ -508,9 +530,14 @@ class Vop2 : public IsaInstruction { bool sdwa_src1_sext_ = false; bool sdwa_src1_neg_ = false; bool sdwa_src1_abs_ = false; + const Operand *sdwa_src0_operand_ = nullptr; + const Operand *sdwa_src1_operand_ = nullptr; + amdgpu::sdwa::SourceModifierFormat sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + amdgpu::sdwa::SourceModifierFormat sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; uint32_t sdwa_dst_sel_ = amdgpu::sdwa::DWORD; uint32_t sdwa_dst_unused_ = 0; bool sdwa_clamp_ = false; + uint32_t sdwa_omod_ = 0; }; class Vintrp : public IsaInstruction { @@ -524,6 +551,7 @@ class Vintrp : public IsaInstruction { class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool has_lit_0(); bool has_lit_1(); bool has_lit_0_has_lit_1(); @@ -539,6 +567,7 @@ class Vop3 : public IsaInstruction { class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool has_lit_0(); bool has_lit_1(); bool has_lit_0_has_lit_1(); @@ -604,6 +633,7 @@ class Flat : public IsaInstruction { class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool has_lit_0(); bool has_lit_1(); bool has_lit_0_has_lit_1(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp index cf42d7f82cd5..34a79a8aa5d7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp @@ -29,7 +29,8 @@ std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { } // namespace detail VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mov_b32_dpp" : "v_mov_b32_e32", reinterpret_cast(inst), @@ -72,9 +73,12 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -169,7 +173,9 @@ std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_i32_dpp" : "v_cvt_f32_i32_e32", reinterpret_cast(inst), @@ -212,9 +218,12 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -225,7 +234,9 @@ std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_u32_dpp" : "v_cvt_f32_u32_e32", reinterpret_cast(inst), @@ -268,9 +279,12 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -281,7 +295,9 @@ std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { } // namespace detail VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_u32_f32_dpp" : "v_cvt_u32_f32_e32", reinterpret_cast(inst), @@ -324,9 +340,12 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -337,7 +356,9 @@ std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_i32_f32_dpp" : "v_cvt_i32_f32_e32", reinterpret_cast(inst), @@ -380,9 +401,12 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -393,7 +417,9 @@ std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f16_f32_dpp" : "v_cvt_f16_f32_e32", reinterpret_cast(inst), @@ -436,9 +462,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -455,7 +484,9 @@ void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_f16_dpp" : "v_cvt_f32_f16_e32", reinterpret_cast(inst), @@ -499,9 +530,12 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -512,7 +546,9 @@ std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { } // namespace detail VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_rpi_i32_f32_dpp" : "v_cvt_rpi_i32_f32_e32", reinterpret_cast(inst), @@ -555,9 +591,12 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -568,7 +607,9 @@ std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_flr_i32_f32_dpp" : "v_cvt_flr_i32_f32_e32", reinterpret_cast(inst), @@ -611,9 +652,12 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -624,7 +668,9 @@ std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) } // namespace detail VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_off_f32_i4_dpp" : "v_cvt_off_f32_i4_e32", reinterpret_cast(inst), @@ -667,9 +713,12 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -739,7 +788,9 @@ std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { } // namespace detail VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte0_dpp" : "v_cvt_f32_ubyte0_e32", reinterpret_cast(inst), @@ -782,9 +833,12 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -795,7 +849,9 @@ std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte1_dpp" : "v_cvt_f32_ubyte1_e32", reinterpret_cast(inst), @@ -838,9 +894,12 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -851,7 +910,9 @@ std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte2_dpp" : "v_cvt_f32_ubyte2_e32", reinterpret_cast(inst), @@ -894,9 +955,12 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -907,7 +971,9 @@ std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) } // namespace detail VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f32_ubyte3_dpp" : "v_cvt_f32_ubyte3_e32", reinterpret_cast(inst), @@ -950,9 +1016,12 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1158,7 +1227,8 @@ std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { } // namespace detail VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_fract_f32_dpp" : "v_fract_f32_e32", reinterpret_cast(inst), @@ -1201,9 +1271,12 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1214,7 +1287,8 @@ std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { } // namespace detail VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_trunc_f32_dpp" : "v_trunc_f32_e32", reinterpret_cast(inst), @@ -1257,9 +1331,12 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1270,7 +1347,8 @@ std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { } // namespace detail VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ceil_f32_dpp" : "v_ceil_f32_e32", reinterpret_cast(inst), @@ -1313,9 +1391,12 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1326,7 +1407,8 @@ std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { } // namespace detail VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rndne_f32_dpp" : "v_rndne_f32_e32", reinterpret_cast(inst), @@ -1369,9 +1451,12 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1382,7 +1467,8 @@ std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { } // namespace detail VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_floor_f32_dpp" : "v_floor_f32_e32", reinterpret_cast(inst), @@ -1425,9 +1511,12 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1438,7 +1527,8 @@ std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { } // namespace detail VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_exp_f32_dpp" : "v_exp_f32_e32", reinterpret_cast(inst), @@ -1481,9 +1571,12 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1494,7 +1587,8 @@ std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { } // namespace detail VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_log_f32_dpp" : "v_log_f32_e32", reinterpret_cast(inst), @@ -1537,9 +1631,12 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1550,7 +1647,8 @@ std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rcp_f32_dpp" : "v_rcp_f32_e32", reinterpret_cast(inst), @@ -1593,9 +1691,12 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1606,7 +1707,9 @@ std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { } // namespace detail VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rcp_iflag_f32_dpp" : "v_rcp_iflag_f32_e32", reinterpret_cast(inst), @@ -1649,9 +1752,12 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1662,7 +1768,8 @@ std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { } // namespace detail VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rsq_f32_dpp" : "v_rsq_f32_e32", reinterpret_cast(inst), @@ -1705,9 +1812,12 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1778,7 +1888,8 @@ std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { } // namespace detail VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sqrt_f32_dpp" : "v_sqrt_f32_e32", reinterpret_cast(inst), @@ -1821,9 +1932,12 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1864,7 +1978,8 @@ std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { } // namespace detail VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sin_f32_dpp" : "v_sin_f32_e32", reinterpret_cast(inst), @@ -1907,9 +2022,12 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1920,7 +2038,8 @@ std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { } // namespace detail VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cos_f32_dpp" : "v_cos_f32_e32", reinterpret_cast(inst), @@ -1963,9 +2082,12 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -1976,7 +2098,8 @@ std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { } // namespace detail VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_not_b32_dpp" : "v_not_b32_e32", reinterpret_cast(inst), @@ -2019,9 +2142,12 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2032,7 +2158,8 @@ std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { } // namespace detail VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_bfrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_bfrev_b32_dpp" : "v_bfrev_b32_e32", reinterpret_cast(inst), @@ -2075,9 +2202,12 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2088,7 +2218,8 @@ std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ffbh_u32_dpp" : "v_ffbh_u32_e32", reinterpret_cast(inst), @@ -2131,9 +2262,12 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2144,7 +2278,8 @@ std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { } // namespace detail VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ffbl_b32_dpp" : "v_ffbl_b32_e32", reinterpret_cast(inst), @@ -2187,9 +2322,12 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2200,7 +2338,8 @@ std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { } // namespace detail VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ffbh_i32_dpp" : "v_ffbh_i32_e32", reinterpret_cast(inst), @@ -2243,9 +2382,12 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2346,7 +2488,9 @@ std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { } // namespace detail VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_exp_i32_f32_dpp" : "v_frexp_exp_i32_f32_e32", reinterpret_cast(inst), @@ -2389,9 +2533,12 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2402,7 +2549,9 @@ std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode } // namespace detail VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_mant_f32_dpp" : "v_frexp_mant_f32_e32", reinterpret_cast(inst), @@ -2445,9 +2594,12 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2474,7 +2626,9 @@ std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { } // namespace detail VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movreld_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movreld_b32_dpp" : "v_movreld_b32_e32", reinterpret_cast(inst), @@ -2519,9 +2673,12 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2533,7 +2690,9 @@ std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { } // namespace detail VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrels_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movrels_b32_dpp" : "v_movrels_b32_e32", reinterpret_cast(inst), @@ -2574,9 +2733,12 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2588,7 +2750,9 @@ std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { } // namespace detail VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movrelsd_b32_dpp" : "v_movrelsd_b32_e32", reinterpret_cast(inst), @@ -2629,9 +2793,12 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2643,7 +2810,9 @@ std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { } // namespace detail VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_2_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_movrelsd_2_b32_dpp" : "v_movrelsd_2_b32_e32", reinterpret_cast(inst), @@ -2684,9 +2853,12 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } m0.apply_fieldless_caps(false, false, false); } @@ -2698,7 +2870,9 @@ std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) } // namespace detail VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f16_u16_dpp" : "v_cvt_f16_u16_e32", reinterpret_cast(inst), @@ -2742,9 +2916,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2761,7 +2938,9 @@ void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_f16_i16_dpp" : "v_cvt_f16_i16_e32", reinterpret_cast(inst), @@ -2805,9 +2984,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2824,7 +3006,9 @@ void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_u16_f16_dpp" : "v_cvt_u16_f16_e32", reinterpret_cast(inst), @@ -2868,9 +3052,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2887,7 +3074,9 @@ void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_i16_f16_dpp" : "v_cvt_i16_f16_e32", reinterpret_cast(inst), @@ -2931,9 +3120,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -2950,7 +3142,8 @@ void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rcp_f16_dpp" : "v_rcp_f16_e32", reinterpret_cast(inst), @@ -2994,9 +3187,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3013,7 +3209,8 @@ void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const { } VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sqrt_f16_dpp" : "v_sqrt_f16_e32", reinterpret_cast(inst), @@ -3057,9 +3254,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3076,7 +3276,8 @@ void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const { } VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rsq_f16_dpp" : "v_rsq_f16_e32", reinterpret_cast(inst), @@ -3120,9 +3321,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3139,7 +3343,8 @@ void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const { } VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_log_f16_dpp" : "v_log_f16_e32", reinterpret_cast(inst), @@ -3183,9 +3388,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3202,7 +3410,8 @@ void VLogF16Vop1::implicit_uses(RegisterSet &uses) const { } VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_exp_f16_dpp" : "v_exp_f16_e32", reinterpret_cast(inst), @@ -3246,9 +3455,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3265,7 +3477,9 @@ void VExpF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_mant_f16_dpp" : "v_frexp_mant_f16_e32", reinterpret_cast(inst), @@ -3309,9 +3523,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3328,7 +3545,9 @@ void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const { } VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_frexp_exp_i16_f16_dpp" : "v_frexp_exp_i16_f16_e32", reinterpret_cast(inst), @@ -3372,9 +3591,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3391,7 +3613,8 @@ void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_floor_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_floor_f16_dpp" : "v_floor_f16_e32", reinterpret_cast(inst), @@ -3435,9 +3658,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3454,7 +3680,8 @@ void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const { } VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ceil_f16_dpp" : "v_ceil_f16_e32", reinterpret_cast(inst), @@ -3498,9 +3725,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3517,7 +3747,8 @@ void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const { } VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_trunc_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_trunc_f16_dpp" : "v_trunc_f16_e32", reinterpret_cast(inst), @@ -3561,9 +3792,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3580,7 +3814,8 @@ void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const { } VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rndne_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_rndne_f16_dpp" : "v_rndne_f16_e32", reinterpret_cast(inst), @@ -3624,9 +3859,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3643,7 +3881,8 @@ void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const { } VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_fract_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_fract_f16_dpp" : "v_fract_f16_e32", reinterpret_cast(inst), @@ -3687,9 +3926,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3706,7 +3948,8 @@ void VFractF16Vop1::implicit_uses(RegisterSet &uses) const { } VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sin_f16_dpp" : "v_sin_f16_e32", reinterpret_cast(inst), @@ -3750,9 +3993,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3769,7 +4015,8 @@ void VSinF16Vop1::implicit_uses(RegisterSet &uses) const { } VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cos_f16_dpp" : "v_cos_f16_e32", reinterpret_cast(inst), @@ -3813,9 +4060,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3832,7 +4082,9 @@ void VCosF16Vop1::implicit_uses(RegisterSet &uses) const { } VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sat_pk_u8_i16_dpp" : "v_sat_pk_u8_i16_e32", reinterpret_cast(inst), @@ -3875,9 +4127,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3888,7 +4143,9 @@ std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { } // namespace detail VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_norm_i16_f16_dpp" : "v_cvt_norm_i16_f16_e32", reinterpret_cast(inst), @@ -3932,9 +4189,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } @@ -3951,7 +4211,9 @@ void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const { } VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) - : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop1(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_norm_u16_f16_dpp" : "v_cvt_norm_u16_f16_e32", reinterpret_cast(inst), @@ -3995,9 +4257,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp index 9a2e4a043f2e..ff63955e646c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace rdna2 { VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cndmask_b32_dpp" : "v_cndmask_b32_e32", reinterpret_cast(inst), @@ -61,9 +63,14 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -123,7 +130,8 @@ std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { } // namespace detail VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_f32_dpp" : "v_add_f32_e32", reinterpret_cast(inst), @@ -168,9 +176,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -183,7 +196,8 @@ std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { } // namespace detail VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_f32_dpp" : "v_sub_f32_e32", reinterpret_cast(inst), @@ -228,9 +242,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -243,7 +262,9 @@ std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_f32_dpp" : "v_subrev_f32_e32", reinterpret_cast(inst), @@ -288,9 +309,14 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -335,7 +361,9 @@ std::unique_ptr decodeVFmacLegacyF32Vop2(const MachineInst *opcode) } // namespace detail VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_legacy_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_legacy_f32_dpp" : "v_mul_legacy_f32_e32", reinterpret_cast(inst), @@ -380,9 +408,14 @@ VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -395,7 +428,8 @@ std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode) } // namespace detail VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_f32_dpp" : "v_mul_f32_e32", reinterpret_cast(inst), @@ -440,9 +474,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -455,7 +494,9 @@ std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { } // namespace detail VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_i32_i24_dpp" : "v_mul_i32_i24_e32", reinterpret_cast(inst), @@ -500,9 +541,14 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -515,7 +561,9 @@ std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_hi_i32_i24_dpp" : "v_mul_hi_i32_i24_e32", reinterpret_cast(inst), @@ -560,9 +608,14 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -575,7 +628,9 @@ std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { } // namespace detail VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_u32_u24_dpp" : "v_mul_u32_u24_e32", reinterpret_cast(inst), @@ -620,9 +675,14 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -635,7 +695,9 @@ std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { } // namespace detail VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_hi_u32_u24_dpp" : "v_mul_hi_u32_u24_e32", reinterpret_cast(inst), @@ -680,9 +742,14 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -741,7 +808,8 @@ std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { } // namespace detail VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_f32_dpp" : "v_min_f32_e32", reinterpret_cast(inst), @@ -786,9 +854,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -801,7 +874,8 @@ std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { } // namespace detail VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_f32_dpp" : "v_max_f32_e32", reinterpret_cast(inst), @@ -846,9 +920,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -861,7 +940,8 @@ std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { } // namespace detail VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_i32_dpp" : "v_min_i32_e32", reinterpret_cast(inst), @@ -906,9 +986,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -921,7 +1006,8 @@ std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { } // namespace detail VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_i32_dpp" : "v_max_i32_e32", reinterpret_cast(inst), @@ -966,9 +1052,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -981,7 +1072,8 @@ std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { } // namespace detail VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_u32_dpp" : "v_min_u32_e32", reinterpret_cast(inst), @@ -1026,9 +1118,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1041,7 +1138,8 @@ std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { } // namespace detail VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_u32_dpp" : "v_max_u32_e32", reinterpret_cast(inst), @@ -1086,9 +1184,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1101,7 +1204,9 @@ std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { } // namespace detail VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_lshrrev_b32_dpp" : "v_lshrrev_b32_e32", reinterpret_cast(inst), @@ -1146,9 +1251,14 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1161,7 +1271,9 @@ std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ashrrev_i32_dpp" : "v_ashrrev_i32_e32", reinterpret_cast(inst), @@ -1206,9 +1318,14 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1221,7 +1338,9 @@ std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { } // namespace detail VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_lshlrev_b32_dpp" : "v_lshlrev_b32_e32", reinterpret_cast(inst), @@ -1266,9 +1385,14 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1281,7 +1405,8 @@ std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { } // namespace detail VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_and_b32_dpp" : "v_and_b32_e32", reinterpret_cast(inst), @@ -1326,9 +1451,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1341,7 +1471,8 @@ std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { } // namespace detail VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_or_b32_dpp" : "v_or_b32_e32", reinterpret_cast(inst), @@ -1386,9 +1517,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1401,7 +1537,8 @@ std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { } // namespace detail VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_xor_b32_dpp" : "v_xor_b32_e32", reinterpret_cast(inst), @@ -1446,9 +1583,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1461,7 +1603,8 @@ std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { } // namespace detail VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_xnor_b32_dpp" : "v_xnor_b32_e32", reinterpret_cast(inst), @@ -1506,9 +1649,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1521,7 +1669,9 @@ std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { } // namespace detail VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_nc_u32_dpp" : "v_add_nc_u32_e32", reinterpret_cast(inst), @@ -1566,9 +1716,14 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1581,7 +1736,9 @@ std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { } // namespace detail VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_nc_u32_dpp" : "v_sub_nc_u32_e32", reinterpret_cast(inst), @@ -1626,9 +1783,14 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1641,7 +1803,9 @@ std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_nc_u32_dpp" : "v_subrev_nc_u32_e32", reinterpret_cast(inst), @@ -1686,9 +1850,14 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1701,7 +1870,9 @@ std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { } // namespace detail VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_co_ci_u32_dpp" : "v_add_co_ci_u32_e32", reinterpret_cast(inst), @@ -1750,9 +1921,14 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1767,7 +1943,9 @@ std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { } // namespace detail VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_co_ci_u32_dpp" : "v_sub_co_ci_u32_e32", reinterpret_cast(inst), @@ -1816,9 +1994,14 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -1833,7 +2016,9 @@ std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { } // namespace detail VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_co_ci_u32_dpp" : "v_subrev_co_ci_u32_e32", reinterpret_cast(inst), @@ -1882,9 +2067,14 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2019,7 +2209,9 @@ std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { } // namespace detail VCvtPkrtzF16F32Vop2::VCvtPkrtzF16F32Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pkrtz_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_cvt_pkrtz_f16_f32_dpp" : "v_cvt_pkrtz_f16_f32_e32", reinterpret_cast(inst), @@ -2064,9 +2256,14 @@ VCvtPkrtzF16F32Vop2::VCvtPkrtzF16F32Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2079,7 +2276,8 @@ std::unique_ptr decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode } // namespace detail VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_add_f16_dpp" : "v_add_f16_e32", reinterpret_cast(inst), @@ -2125,9 +2323,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2146,7 +2349,8 @@ void VAddF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_sub_f16_dpp" : "v_sub_f16_e32", reinterpret_cast(inst), @@ -2192,9 +2396,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2213,7 +2422,9 @@ void VSubF16Vop2::implicit_uses(RegisterSet &uses) const { } VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_subrev_f16_dpp" : "v_subrev_f16_e32", reinterpret_cast(inst), @@ -2259,9 +2470,14 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2280,7 +2496,8 @@ void VSubrevF16Vop2::implicit_uses(RegisterSet &uses) const { } VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mul_f16_dpp" : "v_mul_f16_e32", reinterpret_cast(inst), @@ -2326,9 +2543,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2490,7 +2712,8 @@ void VFmaakF16Vop2::implicit_uses(RegisterSet &uses) const { } VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_max_f16_dpp" : "v_max_f16_e32", reinterpret_cast(inst), @@ -2536,9 +2759,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2557,7 +2785,8 @@ void VMaxF16Vop2::implicit_uses(RegisterSet &uses) const { } VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_min_f16_dpp" : "v_min_f16_e32", reinterpret_cast(inst), @@ -2603,9 +2832,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } @@ -2624,7 +2858,8 @@ void VMinF16Vop2::implicit_uses(RegisterSet &uses) const { } VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) - : Vop2(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + : Vop2(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ldexp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_ldexp_f16_dpp" : "v_ldexp_f16_e32", reinterpret_cast(inst), @@ -2670,9 +2905,14 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_dst_sel_ = sw->dst_sel; sdwa_dst_unused_ = sw->dst_unused; sdwa_clamp_ = sw->clamp; + sdwa_omod_ = sw->omod; if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp index 2aee4bb8d624..b18060d6c0cf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp @@ -14,7 +14,9 @@ namespace rocjitsu { namespace rdna2 { VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -42,12 +44,19 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -57,7 +66,10 @@ std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -85,12 +97,19 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -100,7 +119,10 @@ std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -128,12 +150,19 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -143,7 +172,10 @@ std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -171,12 +203,19 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -186,7 +225,10 @@ std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -214,12 +256,19 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -229,7 +278,10 @@ std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -257,12 +309,19 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -272,7 +331,10 @@ std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -300,12 +362,19 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -315,7 +384,9 @@ std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -343,12 +414,19 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -358,7 +436,9 @@ std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -386,12 +466,19 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -401,7 +488,10 @@ std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -429,12 +519,19 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -444,7 +541,10 @@ std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -472,12 +572,19 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -487,7 +594,10 @@ std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -515,12 +625,19 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -530,7 +647,10 @@ std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -558,12 +678,19 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -573,7 +700,10 @@ std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -601,12 +731,19 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -616,7 +753,10 @@ std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -644,12 +784,19 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -659,7 +806,10 @@ std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -687,12 +837,19 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -702,7 +859,10 @@ std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -732,12 +892,19 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -749,7 +916,10 @@ std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -779,12 +949,19 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -796,7 +973,10 @@ std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -826,12 +1006,19 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -843,7 +1030,10 @@ std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -873,12 +1063,19 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -890,7 +1087,10 @@ std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -920,12 +1120,19 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -937,7 +1144,10 @@ std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -967,12 +1177,19 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -984,7 +1201,10 @@ std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1014,12 +1234,19 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1031,7 +1258,10 @@ std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1061,12 +1291,19 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1078,7 +1315,10 @@ std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1108,12 +1348,19 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1125,7 +1372,10 @@ std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1155,12 +1405,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1172,7 +1429,10 @@ std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1202,12 +1462,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1219,7 +1486,10 @@ std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1249,12 +1519,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1266,7 +1543,10 @@ std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1296,12 +1576,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1313,7 +1600,10 @@ std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1343,12 +1633,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1360,7 +1657,10 @@ std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1390,12 +1690,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -1407,7 +1714,10 @@ std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -1437,12 +1747,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F32; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -2478,7 +2795,9 @@ std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2506,12 +2825,19 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2521,7 +2847,10 @@ std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2549,12 +2878,19 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2564,7 +2900,10 @@ std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2592,12 +2931,19 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2607,7 +2953,10 @@ std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2635,12 +2984,19 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2650,7 +3006,10 @@ std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2678,12 +3037,19 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2693,7 +3059,10 @@ std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2721,12 +3090,19 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2736,7 +3112,10 @@ std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2764,12 +3143,19 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2779,7 +3165,9 @@ std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTI32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2807,12 +3195,19 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2822,7 +3217,10 @@ std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2850,12 +3248,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2865,7 +3270,10 @@ std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2894,12 +3302,19 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2909,7 +3324,10 @@ std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2938,12 +3356,19 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2953,7 +3378,10 @@ std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -2982,12 +3410,19 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -2997,7 +3432,10 @@ std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3026,12 +3464,19 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3041,7 +3486,10 @@ std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3070,12 +3518,19 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3085,7 +3540,10 @@ std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeI16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3114,12 +3572,19 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3129,7 +3594,10 @@ std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpClassF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3158,12 +3626,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -3173,7 +3648,10 @@ std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3203,12 +3681,19 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3220,7 +3705,10 @@ std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3250,12 +3738,19 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3267,7 +3762,10 @@ std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3297,12 +3795,19 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3314,7 +3819,10 @@ std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3344,12 +3852,19 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3361,7 +3876,10 @@ std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3391,12 +3909,19 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3408,7 +3933,10 @@ std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3438,12 +3966,19 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3455,7 +3990,10 @@ std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3485,12 +4023,19 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3502,7 +4047,10 @@ std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_i32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTI32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3532,12 +4080,19 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3549,7 +4104,10 @@ std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3579,12 +4137,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F32; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3596,7 +4161,10 @@ std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) } // namespace detail VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3627,12 +4195,19 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3644,7 +4219,10 @@ std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3675,12 +4253,19 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3692,7 +4277,10 @@ std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3723,12 +4311,19 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3740,7 +4335,10 @@ std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3771,12 +4369,19 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3788,7 +4393,10 @@ std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3819,12 +4427,19 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3836,7 +4451,10 @@ std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_i16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3867,12 +4485,19 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -3884,7 +4509,10 @@ std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_class_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -3915,12 +4543,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4202,7 +4837,10 @@ std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4231,12 +4869,19 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4246,7 +4891,10 @@ std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4275,12 +4923,19 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4290,7 +4945,10 @@ std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4319,12 +4977,19 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4334,7 +4999,10 @@ std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4363,12 +5031,19 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4378,7 +5053,10 @@ std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4407,12 +5085,19 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4422,7 +5107,10 @@ std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4451,12 +5139,19 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -4772,7 +5467,10 @@ std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) } // namespace detail VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4803,12 +5501,19 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4820,7 +5525,10 @@ std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4851,12 +5559,19 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4868,7 +5583,10 @@ std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4899,12 +5617,19 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4916,7 +5641,10 @@ std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4947,12 +5675,19 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -4964,7 +5699,10 @@ std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -4995,12 +5733,19 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5012,7 +5757,10 @@ std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5043,12 +5791,19 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5060,7 +5815,9 @@ std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { } // namespace detail VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5088,12 +5845,19 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5103,7 +5867,10 @@ std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5131,12 +5898,19 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5146,7 +5920,10 @@ std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5174,12 +5951,19 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5189,7 +5973,10 @@ std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5217,12 +6004,19 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5232,7 +6026,10 @@ std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5260,12 +6057,19 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5275,7 +6079,10 @@ std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5303,12 +6110,19 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5318,7 +6132,10 @@ std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5346,12 +6163,19 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5361,7 +6185,9 @@ std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) - : Vopc("v_cmp_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTU32Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5389,12 +6215,19 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5404,7 +6237,9 @@ std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpFF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5433,12 +6268,19 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5448,7 +6290,10 @@ std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLtF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5477,12 +6322,19 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5492,7 +6344,10 @@ std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpEqF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5521,12 +6376,19 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5536,7 +6398,10 @@ std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLeF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5565,12 +6430,19 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5580,7 +6452,10 @@ std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGtF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5609,12 +6484,19 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5624,7 +6506,10 @@ std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpLgF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5653,12 +6538,19 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5668,7 +6560,10 @@ std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpGeF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5697,12 +6592,19 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5712,7 +6614,9 @@ std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpOF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5741,12 +6645,19 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -5756,7 +6667,10 @@ std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5786,12 +6700,19 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5803,7 +6724,10 @@ std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5833,12 +6757,19 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5850,7 +6781,10 @@ std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5880,12 +6814,19 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5897,7 +6838,10 @@ std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5927,12 +6871,19 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5944,7 +6895,10 @@ std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -5974,12 +6928,19 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -5991,7 +6952,10 @@ std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ne_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6021,12 +6985,19 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6038,7 +7009,10 @@ std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6068,12 +7042,19 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6085,7 +7066,10 @@ std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) - : Vopc("v_cmpx_t_u32_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTU32Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6115,12 +7099,19 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::NONE; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(32, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6132,7 +7123,10 @@ std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { } // namespace detail VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_f_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxFF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6163,12 +7157,19 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6180,7 +7181,10 @@ std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6211,12 +7215,19 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6228,7 +7239,10 @@ std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_eq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6259,12 +7273,19 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6276,7 +7297,10 @@ std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_le_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6307,12 +7331,19 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6324,7 +7355,10 @@ std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_gt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6355,12 +7389,19 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6372,7 +7413,10 @@ std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_lg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6403,12 +7447,19 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6420,7 +7471,10 @@ std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6451,12 +7505,19 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6468,7 +7529,10 @@ std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_o_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxOF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6499,12 +7563,19 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -6756,7 +7827,9 @@ std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { } // namespace detail VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpUF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6785,12 +7858,19 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6800,7 +7880,10 @@ std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6829,12 +7912,19 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6844,7 +7934,10 @@ std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6873,12 +7966,19 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6888,7 +7988,10 @@ std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6917,12 +8020,19 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6932,7 +8042,10 @@ std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNleF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -6961,12 +8074,19 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -6976,7 +8096,10 @@ std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7005,12 +8128,19 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -7020,7 +8150,10 @@ std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpNltF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7049,12 +8182,19 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -7064,7 +8204,10 @@ std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmp_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpTruF16Vopc)), vcc(64, OperandType::OPR_VCC, 106), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7093,12 +8236,19 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + vcc = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - vcc.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + vcc.apply_fieldless_caps(false, false, false); } namespace detail { @@ -7380,7 +8530,10 @@ std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { } // namespace detail VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_u_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxUF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7411,12 +8564,19 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7428,7 +8588,10 @@ std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nge_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7459,12 +8622,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7476,7 +8646,10 @@ std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlg_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7507,12 +8680,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7524,7 +8704,10 @@ std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_ngt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7555,12 +8738,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7572,7 +8762,10 @@ std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nle_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7603,12 +8796,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7620,7 +8820,10 @@ std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_neq_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7651,12 +8854,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7668,7 +8878,10 @@ std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_nlt_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7699,12 +8912,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } @@ -7716,7 +8936,10 @@ std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { } // namespace detail VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) - : Vopc("v_cmpx_tru_f16_e32", reinterpret_cast(inst), + : Vopc(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VCmpxTruF16Vopc)), exec(64, OperandType::OPR_EXEC, 126), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7747,12 +8970,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) sdwa_src1_sext_ = sw->src1_sext; sdwa_src1_neg_ = sw->src1_neg; sdwa_src1_abs_ = sw->src1_abs; + sdwa_src0_operand_ = &src0; + sdwa_src0_format_ = amdgpu::sdwa::SourceModifierFormat::F16; + sdwa_src1_operand_ = &vsrc1; + sdwa_src1_format_ = amdgpu::sdwa::SourceModifierFormat::F16; sdwa_sdst_ = sw->sdst; sdwa_sd_ = sw->sd; + if (sw->sd) + exec = Operand(64, OperandType::OPR_SREG, sw->sdst); if (sw->s1) vsrc1 = Operand(16, OperandType::OPR_SRC, reinterpret_cast(inst)->vsrc1); } - exec.apply_fieldless_caps(false, false, false); + if (!(reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA)) + exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp index c8867923e0a3..033c560753fe 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp @@ -23,16 +23,78 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 66: + case 67: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (inst_.op != 76 && inst_.op != 77) { - if (!default_encoding()) - size_ += sizeof(MachineInst); - } + if (has_encoded_literal32()) + size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } @@ -41,13 +103,39 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -91,13 +179,73 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 19; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -128,13 +276,98 @@ void Smem::build_modifiers(std::string &out) const { out += " dlc"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 28: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 105: + case 106: + case 107: + return inst_.src0 == 255; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -165,13 +398,212 @@ bool Vop1::default_encoding() { bool Vop1::has_lit() { return inst_.src0 == 255; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 125: + case 126: + case 127: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -188,13 +620,68 @@ bool Vopc::default_encoding() { bool Vopc::has_lit() { return inst_.src0 == 255; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 32: + case 33: + case 34: + case 37: + case 38: + case 39: + case 43: + case 44: + case 45: + case 47: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + return inst_.src0 == 255; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -231,6 +718,439 @@ bool Vop2::hasImpliedLiteral() { return inst_.op == 44 || inst_.op == 45 || inst_.op == 55 || inst_.op == 56; } +bool Vop3::has_encoded_literal32() const { + switch (inst_.op) { + case 385: + case 387: + case 388: + case 389: + case 390: + case 391: + case 392: + case 394: + case 395: + case 396: + case 397: + case 398: + case 399: + case 400: + case 401: + case 402: + case 403: + case 404: + case 405: + case 406: + case 407: + case 408: + case 409: + case 410: + case 412: + case 416: + case 417: + case 418: + case 419: + case 420: + case 421: + case 423: + case 426: + case 427: + case 430: + case 431: + case 433: + case 435: + case 436: + case 437: + case 438: + case 439: + case 440: + case 441: + case 442: + case 443: + case 444: + case 445: + case 446: + case 447: + case 448: + case 450: + case 464: + case 465: + case 466: + case 467: + case 468: + case 469: + case 470: + case 471: + case 472: + case 473: + case 474: + case 475: + case 476: + case 477: + case 478: + case 479: + case 480: + case 481: + case 482: + case 483: + case 484: + case 489: + case 490: + case 491: + case 865: + return inst_.src0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 125: + case 126: + case 127: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 253: + case 254: + case 255: + case 257: + case 259: + case 260: + case 261: + case 262: + case 263: + case 264: + case 265: + case 266: + case 267: + case 268: + case 271: + case 272: + case 273: + case 274: + case 275: + case 276: + case 280: + case 281: + case 282: + case 283: + case 284: + case 285: + case 286: + case 293: + case 294: + case 295: + case 299: + case 303: + case 306: + case 307: + case 308: + case 309: + case 310: + case 313: + case 314: + case 315: + case 573: + case 605: + case 771: + case 772: + case 773: + case 774: + case 775: + case 777: + case 778: + case 779: + case 780: + case 781: + case 782: + case 785: + case 786: + case 787: + case 796: + case 797: + case 798: + case 799: + case 800: + case 801: + case 802: + case 803: + case 804: + case 805: + case 806: + case 807: + case 808: + case 809: + case 810: + case 811: + case 812: + case 813: + case 814: + case 815: + case 824: + case 825: + case 826: + case 828: + case 829: + case 830: + case 866: + case 867: + case 868: + return inst_.src0 == 255 || inst_.src1 == 255; + case 521: + case 522: + case 523: + case 524: + case 525: + case 526: + case 527: + case 528: + case 529: + case 530: + case 531: + case 532: + case 533: + case 534: + case 535: + case 536: + case 537: + case 538: + case 539: + case 540: + case 541: + case 542: + case 543: + case 544: + case 545: + case 546: + case 547: + case 548: + case 549: + case 550: + case 551: + case 552: + case 567: + case 568: + case 569: + case 570: + case 571: + case 576: + case 577: + case 580: + case 581: + case 582: + case 583: + case 584: + case 585: + case 586: + case 587: + case 588: + case 589: + case 590: + case 591: + case 592: + case 593: + case 595: + case 596: + case 597: + case 598: + case 599: + case 600: + case 601: + case 602: + case 606: + case 607: + case 608: + case 609: + case 610: + case 611: + case 612: + case 613: + case 614: + case 615: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + case 603: + case 604: + return inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -238,10 +1158,9 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -295,6 +1214,43 @@ bool Vop3::has_lit_0_has_lit_1_has_lit_2() { return inst_.src0 == 255 && inst_.src1 == 255 && inst_.src2 == 255; } +bool Vop3p::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 17: + case 18: + return inst_.src0 == 255 || inst_.src1 == 255; + case 0: + case 9: + case 14: + case 19: + case 22: + case 23: + case 24: + case 25: + case 26: + case 32: + case 33: + case 34: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -302,10 +1258,9 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -485,6 +1440,25 @@ void Flat::implicit_uses(RegisterSet &uses) const { } } +bool Vop3SdstEnc::has_encoded_literal32() const { + switch (inst_.op) { + case 288: + case 289: + case 290: + case 768: + case 769: + case 770: + return inst_.src0 == 255 || inst_.src1 == 255; + case 764: + case 765: + case 766: + case 767: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -493,10 +1467,9 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h index 69f563138e2b..6cf1495e5c70 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h @@ -342,6 +342,7 @@ inline constexpr uint16_t kVop3SdstEncOpHi4 = 430; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -352,6 +353,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -383,6 +385,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -403,6 +406,7 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool default_encoding(); @@ -434,6 +438,7 @@ class Vop1 : public IsaInstruction { class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); @@ -463,6 +468,7 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool default_encoding(); @@ -496,6 +502,7 @@ class Vop2 : public IsaInstruction { class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -521,6 +528,7 @@ class Vop3 : public IsaInstruction { class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -609,6 +617,7 @@ class Flat : public IsaInstruction { class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp index 8337fc5732f3..d672d80b6c6c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp @@ -23,16 +23,93 @@ std::string flat_mnemonic(std::string_view mnemonic, int seg) { } } // namespace +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 66: + case 67: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (inst_.op != 76 && inst_.op != 77) { - if (!default_encoding()) - size_ += sizeof(MachineInst); - } + if (has_encoded_literal32()) + size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } @@ -41,13 +118,67 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -91,13 +222,88 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 19; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -132,13 +338,98 @@ void Smem::build_modifiers(std::string &out) const { out += " dlc"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 28: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 105: + case 106: + case 107: + return inst_.src0 == 255; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -169,13 +460,212 @@ bool Vop1::default_encoding() { bool Vop1::has_lit() { return inst_.src0 == 255; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 125: + case 126: + case 127: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -192,13 +682,68 @@ bool Vopc::default_encoding() { bool Vopc::has_lit() { return inst_.src0 == 255; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 32: + case 33: + case 34: + case 37: + case 38: + case 39: + case 43: + case 44: + case 45: + case 47: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + return inst_.src0 == 255; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -235,6 +780,439 @@ bool Vop2::hasImpliedLiteral() { return inst_.op == 44 || inst_.op == 45 || inst_.op == 55 || inst_.op == 56; } +bool Vop3::has_encoded_literal32() const { + switch (inst_.op) { + case 385: + case 387: + case 388: + case 389: + case 390: + case 391: + case 392: + case 394: + case 395: + case 396: + case 397: + case 398: + case 399: + case 400: + case 401: + case 402: + case 403: + case 404: + case 405: + case 406: + case 407: + case 408: + case 409: + case 410: + case 412: + case 416: + case 417: + case 418: + case 419: + case 420: + case 421: + case 423: + case 426: + case 427: + case 430: + case 431: + case 433: + case 435: + case 436: + case 437: + case 438: + case 439: + case 440: + case 441: + case 442: + case 443: + case 444: + case 445: + case 446: + case 447: + case 448: + case 450: + case 464: + case 465: + case 466: + case 467: + case 468: + case 469: + case 470: + case 471: + case 472: + case 473: + case 474: + case 475: + case 476: + case 477: + case 478: + case 479: + case 480: + case 481: + case 482: + case 483: + case 484: + case 489: + case 490: + case 491: + case 865: + return inst_.src0 == 255; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 125: + case 126: + case 127: + case 128: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 143: + case 144: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 159: + case 160: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 175: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 192: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 199: + case 200: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 207: + case 208: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 215: + case 216: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 223: + case 253: + case 254: + case 255: + case 257: + case 259: + case 260: + case 261: + case 262: + case 263: + case 264: + case 265: + case 266: + case 267: + case 268: + case 271: + case 272: + case 273: + case 274: + case 275: + case 276: + case 280: + case 281: + case 282: + case 283: + case 284: + case 285: + case 286: + case 293: + case 294: + case 295: + case 299: + case 303: + case 306: + case 307: + case 308: + case 309: + case 310: + case 313: + case 314: + case 315: + case 573: + case 605: + case 771: + case 772: + case 773: + case 774: + case 775: + case 777: + case 778: + case 779: + case 780: + case 781: + case 782: + case 785: + case 786: + case 787: + case 796: + case 797: + case 798: + case 799: + case 800: + case 801: + case 802: + case 803: + case 804: + case 805: + case 806: + case 807: + case 808: + case 809: + case 810: + case 811: + case 812: + case 813: + case 814: + case 815: + case 824: + case 825: + case 826: + case 828: + case 829: + case 830: + case 866: + case 867: + case 868: + return inst_.src0 == 255 || inst_.src1 == 255; + case 521: + case 522: + case 523: + case 524: + case 525: + case 526: + case 527: + case 528: + case 529: + case 530: + case 531: + case 532: + case 533: + case 534: + case 535: + case 536: + case 537: + case 538: + case 539: + case 540: + case 541: + case 542: + case 543: + case 544: + case 545: + case 546: + case 547: + case 548: + case 549: + case 550: + case 551: + case 552: + case 567: + case 568: + case 569: + case 570: + case 571: + case 576: + case 577: + case 580: + case 581: + case 582: + case 583: + case 584: + case 585: + case 586: + case 587: + case 588: + case 589: + case 590: + case 591: + case 592: + case 593: + case 595: + case 596: + case 597: + case 598: + case 599: + case 600: + case 601: + case 602: + case 606: + case 607: + case 608: + case 609: + case 610: + case 611: + case 612: + case 613: + case 614: + case 615: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + case 603: + case 604: + return inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -242,10 +1220,9 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -299,6 +1276,43 @@ bool Vop3::has_lit_0_has_lit_1_has_lit_2() { return inst_.src0 == 255 && inst_.src1 == 255 && inst_.src2 == 255; } +bool Vop3p::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 17: + case 18: + return inst_.src0 == 255 || inst_.src1 == 255; + case 0: + case 9: + case 14: + case 19: + case 22: + case 23: + case 24: + case 25: + case 26: + case 32: + case 33: + case 34: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -306,10 +1320,9 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -489,6 +1502,25 @@ void Flat::implicit_uses(RegisterSet &uses) const { } } +bool Vop3SdstEnc::has_encoded_literal32() const { + switch (inst_.op) { + case 288: + case 289: + case 290: + case 768: + case 769: + case 770: + return inst_.src0 == 255 || inst_.src1 == 255; + case 764: + case 765: + case 766: + case 767: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -497,10 +1529,9 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h index 117e4ec85286..f545ed267776 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h @@ -355,6 +355,7 @@ inline constexpr uint16_t kVop3SdstEncOpHi4 = 430; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -365,6 +366,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -396,6 +398,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -418,6 +421,7 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool default_encoding(); @@ -449,6 +453,7 @@ class Vop1 : public IsaInstruction { class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); @@ -478,6 +483,7 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool default_encoding(); @@ -511,6 +517,7 @@ class Vop2 : public IsaInstruction { class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -536,6 +543,7 @@ class Vop3 : public IsaInstruction { class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -624,6 +632,7 @@ class Flat : public IsaInstruction { class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp index 53b516eb7846..53274ac419bf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp @@ -12,16 +12,95 @@ namespace rocjitsu { namespace rdna4 { +bool Sop1::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 66: + case 67: + case 83: + case 88: + case 96: + case 97: + case 98: + case 99: + case 100: + case 101: + case 102: + case 103: + case 104: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + return inst_.ssrc0 == 255; + default: + return false; + } +} + Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (inst_.op != 76 && inst_.op != 77) { - if (!default_encoding()) - size_ += sizeof(MachineInst); - } + if (has_encoded_literal32()) + size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); } @@ -30,13 +109,67 @@ bool Sop1::default_encoding() { return inst_.ssrc0 != 255; } bool Sop1::has_lit_0() { return inst_.ssrc0 == 255; } +bool Sopc::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -80,13 +213,95 @@ bool Sopk::default_encoding() { return true; } bool Sopk::hasImpliedLiteral() { return inst_.op == 19; } +bool Sop2::has_encoded_literal32() const { + switch (inst_.op) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 64: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 71: + case 72: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 79: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + return inst_.ssrc0 == 255 || inst_.ssrc1 == 255; + default: + return false; + } +} + Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -119,13 +334,102 @@ void Smem::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop1::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 28: + case 32: + case 33: + case 34: + case 35: + case 36: + case 37: + case 39: + case 42: + case 43: + case 46: + case 47: + case 49: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 63: + case 64: + case 66: + case 80: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 87: + case 88: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 95: + case 96: + case 97: + case 98: + case 99: + case 100: + case 105: + case 106: + case 107: + case 108: + case 109: + case 110: + case 111: + return inst_.src0 == 255; + default: + return false; + } +} + Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -156,13 +460,184 @@ bool Vop1::default_encoding() { bool Vop1::has_lit() { return inst_.src0 == 255; } +bool Vopc::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 125: + case 126: + case 127: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 253: + case 254: + case 255: + return inst_.src0 == 255; + default: + return false; + } +} + Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32()) size_ += sizeof(MachineInst); std::memcpy(raw_words_.data(), inst, size_); raw_encoding_ = raw_words_.data(); @@ -179,13 +654,71 @@ bool Vopc::default_encoding() { bool Vopc::has_lit() { return inst_.src0 == 255; } +bool Vop2::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 31: + case 32: + case 33: + case 34: + case 37: + case 38: + case 39: + case 43: + case 44: + case 45: + case 47: + case 48: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 55: + case 56: + case 59: + case 60: + return inst_.src0 == 255; + default: + return false; + } +} + Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!default_encoding() || hasImpliedLiteral()) + if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || + has_encoded_literal32() || hasImpliedLiteral()) size_ += sizeof(MachineInst); if (hasImpliedLiteral()) literal_ = reinterpret_cast(inst)[1]; @@ -222,6 +755,442 @@ bool Vop2::hasImpliedLiteral() { return inst_.op == 44 || inst_.op == 45 || inst_.op == 55 || inst_.op == 56; } +bool Vop3::has_encoded_literal32() const { + switch (inst_.op) { + case 385: + case 387: + case 388: + case 389: + case 390: + case 391: + case 392: + case 394: + case 395: + case 396: + case 397: + case 398: + case 399: + case 400: + case 401: + case 402: + case 403: + case 404: + case 405: + case 406: + case 407: + case 408: + case 409: + case 410: + case 412: + case 416: + case 417: + case 418: + case 419: + case 420: + case 421: + case 423: + case 426: + case 427: + case 430: + case 431: + case 433: + case 435: + case 436: + case 437: + case 438: + case 439: + case 440: + case 441: + case 442: + case 443: + case 444: + case 445: + case 446: + case 447: + case 448: + case 450: + case 464: + case 465: + case 466: + case 467: + case 468: + case 469: + case 470: + case 471: + case 472: + case 473: + case 474: + case 475: + case 476: + case 477: + case 478: + case 479: + case 480: + case 481: + case 482: + case 483: + case 484: + case 489: + case 490: + case 491: + case 492: + case 493: + case 494: + case 495: + case 640: + case 641: + case 642: + case 643: + case 644: + case 645: + case 646: + case 647: + case 648: + case 649: + case 865: + return inst_.src0 == 255; + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + case 17: + case 18: + case 19: + case 20: + case 21: + case 22: + case 23: + case 24: + case 25: + case 26: + case 27: + case 28: + case 29: + case 30: + case 33: + case 34: + case 35: + case 36: + case 37: + case 38: + case 39: + case 40: + case 41: + case 42: + case 43: + case 44: + case 45: + case 46: + case 49: + case 50: + case 51: + case 52: + case 53: + case 54: + case 57: + case 58: + case 59: + case 60: + case 61: + case 62: + case 65: + case 66: + case 67: + case 68: + case 69: + case 70: + case 73: + case 74: + case 75: + case 76: + case 77: + case 78: + case 81: + case 82: + case 83: + case 84: + case 85: + case 86: + case 89: + case 90: + case 91: + case 92: + case 93: + case 94: + case 125: + case 126: + case 127: + case 129: + case 130: + case 131: + case 132: + case 133: + case 134: + case 135: + case 136: + case 137: + case 138: + case 139: + case 140: + case 141: + case 142: + case 145: + case 146: + case 147: + case 148: + case 149: + case 150: + case 151: + case 152: + case 153: + case 154: + case 155: + case 156: + case 157: + case 158: + case 161: + case 162: + case 163: + case 164: + case 165: + case 166: + case 167: + case 168: + case 169: + case 170: + case 171: + case 172: + case 173: + case 174: + case 177: + case 178: + case 179: + case 180: + case 181: + case 182: + case 185: + case 186: + case 187: + case 188: + case 189: + case 190: + case 193: + case 194: + case 195: + case 196: + case 197: + case 198: + case 201: + case 202: + case 203: + case 204: + case 205: + case 206: + case 209: + case 210: + case 211: + case 212: + case 213: + case 214: + case 217: + case 218: + case 219: + case 220: + case 221: + case 222: + case 253: + case 254: + case 255: + case 257: + case 258: + case 259: + case 260: + case 261: + case 262: + case 263: + case 264: + case 265: + case 266: + case 267: + case 268: + case 269: + case 270: + case 273: + case 274: + case 275: + case 276: + case 277: + case 278: + case 280: + case 281: + case 282: + case 283: + case 284: + case 285: + case 286: + case 287: + case 293: + case 294: + case 295: + case 299: + case 303: + case 304: + case 305: + case 306: + case 307: + case 308: + case 309: + case 310: + case 315: + case 573: + case 605: + case 771: + case 772: + case 773: + case 774: + case 775: + case 777: + case 778: + case 779: + case 780: + case 781: + case 782: + case 785: + case 786: + case 787: + case 796: + case 797: + case 798: + case 799: + case 800: + case 801: + case 802: + case 803: + case 804: + case 805: + case 806: + case 811: + case 812: + case 813: + case 814: + case 815: + case 824: + case 825: + case 826: + case 829: + case 830: + case 833: + case 834: + case 866: + case 867: + case 868: + case 869: + case 870: + case 871: + case 872: + case 873: + case 874: + case 875: + case 876: + return inst_.src0 == 255 || inst_.src1 == 255; + case 521: + case 522: + case 523: + case 524: + case 525: + case 526: + case 527: + case 528: + case 529: + case 530: + case 531: + case 532: + case 533: + case 534: + case 535: + case 536: + case 538: + case 539: + case 541: + case 542: + case 544: + case 545: + case 546: + case 547: + case 548: + case 549: + case 550: + case 551: + case 552: + case 553: + case 554: + case 555: + case 556: + case 557: + case 558: + case 559: + case 560: + case 561: + case 562: + case 567: + case 568: + case 569: + case 570: + case 571: + case 576: + case 577: + case 580: + case 581: + case 582: + case 583: + case 584: + case 586: + case 587: + case 589: + case 590: + case 592: + case 593: + case 595: + case 596: + case 597: + case 598: + case 599: + case 600: + case 601: + case 602: + case 610: + case 611: + case 612: + case 613: + case 614: + case 615: + case 616: + case 617: + case 618: + case 619: + case 620: + case 621: + case 622: + case 623: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + case 603: + case 604: + return inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -229,10 +1198,9 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -286,6 +1254,49 @@ bool Vop3::has_lit_0_has_lit_1_has_lit_2() { return inst_.src0 == 255 && inst_.src1 == 255 && inst_.src2 == 255; } +bool Vop3p::has_encoded_literal32() const { + switch (inst_.op) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + case 10: + case 11: + case 12: + case 13: + case 15: + case 16: + case 27: + case 28: + case 29: + case 30: + return inst_.src0 == 255 || inst_.src1 == 255; + case 0: + case 9: + case 14: + case 19: + case 22: + case 23: + case 24: + case 25: + case 26: + case 32: + case 33: + case 34: + case 36: + case 37: + case 38: + case 39: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -293,10 +1304,9 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); @@ -467,6 +1477,25 @@ void Vglobal::build_modifiers(std::string &out) const { out += " nv"; } +bool Vop3SdstEnc::has_encoded_literal32() const { + switch (inst_.op) { + case 288: + case 289: + case 290: + case 768: + case 769: + case 770: + return inst_.src0 == 255 || inst_.src1 == 255; + case 764: + case 765: + case 766: + case 767: + return inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255; + default: + return false; + } +} + Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { @@ -475,10 +1504,9 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) + (has_encoded_literal32())) throw util::InvalidInst("DPP and literal operands cannot be combined", ""); - if (has_lit_0() || has_lit_1() || has_lit_0_has_lit_1() || has_lit_2() || has_lit_0_has_lit_2() || - has_lit_1_has_lit_2() || has_lit_0_has_lit_1_has_lit_2()) + if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) size_ += sizeof(MachineInst); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h index 7c0ff3926033..76c34b62aef6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h @@ -372,6 +372,7 @@ inline constexpr uint16_t kVop3SdstEncOpHi4 = 430; class Sop1 : public IsaInstruction { public: Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); using OpEncoding = Sop1MachineInst; @@ -382,6 +383,7 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -413,6 +415,7 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -435,6 +438,7 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool default_encoding(); @@ -466,6 +470,7 @@ class Vop1 : public IsaInstruction { class Vopc : public IsaInstruction { public: Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); @@ -495,6 +500,7 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool default_encoding(); @@ -528,6 +534,7 @@ class Vop2 : public IsaInstruction { class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -553,6 +560,7 @@ class Vop3 : public IsaInstruction { class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -653,6 +661,7 @@ class Vglobal : public IsaInstruction { class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); + bool has_encoded_literal32() const; void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h index 5ab6a5ff1827..d45ceb6fa8f8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h @@ -25,6 +25,8 @@ #include #include #include +#include +#include namespace rocjitsu { namespace amdgpu { @@ -393,17 +395,76 @@ inline uint32_t sdwa_src_select(uint32_t val, uint32_t sel, bool sign_ext) { return word_val; } -/// @brief Floating-point representation used by SDWA source modifiers. -/// -/// SDWA selection and sign extension apply to every source. Absolute-value and -/// negate fields apply only to floating-point sources, and their sign bit -/// depends on the semantic source type rather than the selector width. -enum class SourceModifierFormat { - NONE, - F16, - BF16, - F32, -}; +/// @brief Append an SDWA source, including modifiers encoded in the extension word. +/// The semantic source format selects which modifier family is meaningful: +/// integer-like sources use sign extension, while floating-point sources use +/// negate and absolute-value modifiers. +inline void append_source(std::string &out, const Operand &source, SourceModifierFormat format, + bool sign_extend, bool negate, bool absolute) { + if (format == SourceModifierFormat::NONE && sign_extend) + out += "sext("; + if (format != SourceModifierFormat::NONE && negate) + out += '-'; + if (format != SourceModifierFormat::NONE && absolute) + out += '|'; + out += source.name(); + if (format != SourceModifierFormat::NONE && absolute) + out += '|'; + if (format == SourceModifierFormat::NONE && sign_extend) + out += ')'; +} + +inline std::string selection_name(uint32_t selection) { + constexpr std::array names = {"BYTE_0", "BYTE_1", "BYTE_2", "BYTE_3", + "WORD_0", "WORD_1", "DWORD"}; + if (selection < names.size()) + return std::string(names[selection]); + return "invalid(" + std::to_string(selection) + ")"; +} + +inline std::string destination_unused_name(uint32_t unused) { + constexpr std::array names = {"UNUSED_PAD", "UNUSED_SEXT", + "UNUSED_PRESERVE"}; + if (unused < names.size()) + return std::string(names[unused]); + return "invalid(" + std::to_string(unused) + ")"; +} + +inline void append_source_attributes(std::string &out, uint32_t src0_selection, const Operand *src1, + uint32_t src1_selection) { + out += " src0_sel:"; + out += selection_name(src0_selection); + if (src1) { + out += " src1_sel:"; + out += selection_name(src1_selection); + } +} + +inline void append_destination_attributes(std::string &out, bool clamp, uint32_t omod, + uint32_t destination_selection, + uint32_t destination_unused, uint32_t src0_selection, + const Operand *src1, uint32_t src1_selection) { + if (clamp) + out += " clamp"; + switch (omod) { + case 1: + out += " mul:2"; + break; + case 2: + out += " mul:4"; + break; + case 3: + out += " div:2"; + break; + default: + break; + } + out += " dst_sel:"; + out += selection_name(destination_selection); + out += " dst_unused:"; + out += destination_unused_name(destination_unused); + append_source_attributes(out, src0_selection, src1, src1_selection); +} inline uint32_t apply_source_modifiers(uint32_t value, SourceModifierFormat format, bool negate, bool absolute) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h index 1af91bdcf62a..76032a459417 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h @@ -96,6 +96,18 @@ enum SdwaUnused : uint32_t { UNUSED_PRESERVE = 2, }; +/// @brief Floating-point representation used by SDWA source modifiers. +/// +/// SDWA selection and sign extension apply to every source. Absolute-value and +/// negate fields apply only to floating-point sources, and their sign bit +/// depends on the semantic source type rather than the selector width. +enum class SourceModifierFormat { + NONE, + F16, + BF16, + F32, +}; + } // namespace sdwa /// @brief Return the VOP3 output-select field across MRISA spelling variants. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h index c04367dc8f7c..6cc5d4ea4521 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h @@ -339,21 +339,22 @@ class Instruction : public util::IListNodeis_fieldless()) + for (uint8_t operand_index = 0; operand_index < num_dst_; ++operand_index) { + if (dst_operands_[operand_index]->is_fieldless()) continue; disassembly_ += (first ? " " : ", "); - disassembly_ += dst_operands_[i]->name(); + disassembly_ += dst_operands_[operand_index]->name(); first = false; } - for (uint8_t i = 0; i < num_src_; ++i) { - if (src_operands_[i]->size_bits() == 0 || src_operands_[i]->is_fieldless()) + for (uint8_t operand_index = 0; operand_index < num_src_; ++operand_index) { + if (src_operands_[operand_index]->size_bits() == 0 || + src_operands_[operand_index]->is_fieldless()) continue; disassembly_ += (first ? " " : ", "); - disassembly_ += src_operands_[i]->name(); + append_src_operand(disassembly_, operand_index); first = false; } build_modifiers(disassembly_); @@ -379,6 +380,10 @@ class Instruction : public util::IListNodename(); + } /// @brief Cached disassembly string. mutable std::string disassembly_; /// @brief Instruction property flags bitmask. diff --git a/emulation/rocjitsu/tests/decode_smoke_test.cpp b/emulation/rocjitsu/tests/decode_smoke_test.cpp index d57bbb84f611..77956361b1ea 100644 --- a/emulation/rocjitsu/tests/decode_smoke_test.cpp +++ b/emulation/rocjitsu/tests/decode_smoke_test.cpp @@ -1776,4 +1776,40 @@ TEST(AccVgprSrcCanonicalizationTest, LegalRawSrcResolvesToUnifiedAccIndex) { } } +TEST(Cdna4DecodeTest, RejectsVop3px2PrefixWithoutMfmaSuffix) { + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + + const uint32_t unrelated_opcode[] = { + 0xD3AC0000u, + 0x00000000u, + 0xD3AC0000u, + 0x00000000u, + }; + EXPECT_THROW(static_cast(decoder->decode(unrelated_opcode)), util::InvalidInst); + + const uint32_t wrong_encoding[] = { + 0xD3AC0000u, + 0x00000000u, + 0xD32D0000u, + 0x00000000u, + }; + EXPECT_THROW(static_cast(decoder->decode(wrong_encoding)), util::InvalidInst); +} + +TEST(Cdna4DecodeTest, MfmaScaleF8f6f4AcceptsSecondVop3px2Suffix) { + const uint32_t words[] = { + 0xD3AC0000u, + 0x00000000u, + 0xD3AE0000u, + 0x04020100u, + }; + + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + std::unique_ptr inst(decoder->decode(words)); + ASSERT_NE(inst, nullptr); + EXPECT_EQ(inst->mnemonic(), "v_mfma_f32_32x32x64_f8f6f4"); + EXPECT_EQ(inst->size(), sizeof(words)); +} } // namespace diff --git a/emulation/rocjitsu/tests/execution_plugin_test.cpp b/emulation/rocjitsu/tests/execution_plugin_test.cpp index b860dd2eb775..10f661968e98 100644 --- a/emulation/rocjitsu/tests/execution_plugin_test.cpp +++ b/emulation/rocjitsu/tests/execution_plugin_test.cpp @@ -1692,7 +1692,7 @@ TEST(ExecutionPluginTest, SdwaFloatingModifiersUseSemanticSourceWidth) { std::unique_ptr bf16_inst( decoder->decode(reinterpret_cast(&cvt_bf16))); ASSERT_NE(bf16_inst, nullptr); - ASSERT_EQ(std::string_view(bf16_inst->mnemonic()), "v_cvt_f32_bf16_e32"); + ASSERT_EQ(std::string_view(bf16_inst->mnemonic()), "v_cvt_f32_bf16_sdwa"); cu->write_vgpr(vb + kSrc0, 0, 0xCAFE'C000u); cu->execute_instruction(bf16_inst.get(), *wf); EXPECT_EQ(cu->read_vgpr_storage(vb + kDst, 0), std::bit_cast(2.0f)); diff --git a/emulation/rocjitsu/tests/shared_infra_test.cpp b/emulation/rocjitsu/tests/shared_infra_test.cpp index 66bb2edad244..aabb0efcc9db 100644 --- a/emulation/rocjitsu/tests/shared_infra_test.cpp +++ b/emulation/rocjitsu/tests/shared_infra_test.cpp @@ -3191,6 +3191,159 @@ void cdna4_vop1_sdwa_availability_is_instruction_specific() { util::InvalidInst); } +TEST(SdwaTest, Cdna4DisassemblesDestinationAndSourceAttributes) { + cdna4::Vop1VopSdwaMachineInst raw{}; + raw.src0 = amdgpu::SRC_SDWA; + raw.op = cdna4::kVFloorF32Vop1; + raw.vdst = 0; + raw.encoding = cdna4::encoding::kVop1 >> 2; + raw.vsrc0 = 92; + raw.dst_sel = amdgpu::sdwa::BYTE_0; + raw.dst_unused = amdgpu::sdwa::UNUSED_PAD; + raw.clamp = 1; + raw.omod = 3; + raw.src0_sel = amdgpu::sdwa::BYTE_0; + + const auto words = std::bit_cast>(raw); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + std::unique_ptr inst(decoder->decode(words.data())); + ASSERT_NE(inst, nullptr); + EXPECT_EQ(inst->disassemble(), "v_floor_f32_sdwa v0, v92 clamp div:2 dst_sel:BYTE_0 " + "dst_unused:UNUSED_PAD src0_sel:BYTE_0"); +} + +TEST(SdwaTest, Cdna4DisassemblesCompareDestinationAndSourceModifiers) { + cdna4::VopcVopSdwaSdstEncMachineInst raw{}; + raw.src0 = amdgpu::SRC_SDWA; + raw.vsrc1 = 1; + raw.op = cdna4::kVCmpEqF32Vopc; + raw.encoding = cdna4::encoding::kVopc >> 2; + raw.vsrc0 = 0; + raw.sdst = 4; + raw.sd = 1; + raw.src0_sel = amdgpu::sdwa::BYTE_0; + raw.src0_neg = 1; + raw.src0_abs = 1; + raw.src1_sel = amdgpu::sdwa::DWORD; + raw.src1_neg = 1; + + const auto words = std::bit_cast>(raw); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + std::unique_ptr inst(decoder->decode(words.data())); + ASSERT_NE(inst, nullptr); + EXPECT_EQ(inst->disassemble(), + "v_cmp_eq_f32_sdwa s[4:5], -|v0|, -v1 src0_sel:BYTE_0 src1_sel:DWORD"); + ASSERT_EQ(inst->num_dst_operands(), 1); + EXPECT_EQ(inst->dst_operand(0)->to_register_ref(), (RegisterRef{RegClass::SGPR, 4, 2})); +} + +TEST(SdwaTest, Cdna4DisassemblesImplicitCompareDestination) { + cdna4::VopcVopSdwaSdstEncMachineInst raw{}; + raw.src0 = amdgpu::SRC_SDWA; + raw.vsrc1 = 1; + raw.op = cdna4::kVCmpEqF32Vopc; + raw.encoding = cdna4::encoding::kVopc >> 2; + raw.vsrc0 = 0; + raw.sd = 0; + raw.src0_sel = amdgpu::sdwa::DWORD; + raw.src1_sel = amdgpu::sdwa::DWORD; + + const auto words = std::bit_cast>(raw); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + std::unique_ptr inst(decoder->decode(words.data())); + ASSERT_NE(inst, nullptr); + EXPECT_EQ(inst->disassemble(), "v_cmp_eq_f32_sdwa vcc, v0, v1 src0_sel:DWORD src1_sel:DWORD"); +} + +TEST(SdwaTest, Cdna4DisassemblesBothVop2Sources) { + cdna4::Vop2VopSdwaMachineInst raw{}; + raw.src0 = amdgpu::SRC_SDWA; + raw.vsrc1 = 3; + raw.vdst = 5; + raw.op = cdna4::kVAddF32Vop2; + raw.encoding = cdna4::encoding::kVop2; + raw.vsrc0 = 2; + raw.dst_sel = amdgpu::sdwa::DWORD; + raw.dst_unused = amdgpu::sdwa::UNUSED_PAD; + raw.src0_sel = amdgpu::sdwa::DWORD; + raw.src0_neg = 1; + raw.src0_abs = 1; + raw.src1_sel = amdgpu::sdwa::BYTE_2; + raw.src1_neg = 1; + + const auto words = std::bit_cast>(raw); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + std::unique_ptr inst(decoder->decode(words.data())); + ASSERT_NE(inst, nullptr); + EXPECT_EQ(inst->disassemble(), + "v_add_f32_sdwa v5, -|v2|, -v3 dst_sel:DWORD dst_unused:UNUSED_PAD " + "src0_sel:DWORD src1_sel:BYTE_2"); +} + +TEST(SdwaTest, InvalidAttributeValuesAreExplicit) { + EXPECT_EQ(amdgpu::sdwa::selection_name(7), "invalid(7)"); + EXPECT_EQ(amdgpu::sdwa::destination_unused_name(3), "invalid(3)"); +} + +TEST(DecodeSizeTest, Cdna4UsesOpcodeOperandCapabilitiesForLiteralSelectors) { + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + + cdna4::SopcMachineInst set_gpr_idx{}; + set_gpr_idx.ssrc0 = 0; + set_gpr_idx.ssrc1 = 255; + set_gpr_idx.op = cdna4::kSSetGprIdxOnSopc; + set_gpr_idx.encoding = cdna4::encoding::kSopc; + const auto set_gpr_idx_words = std::bit_cast>(set_gpr_idx); + std::unique_ptr set_gpr_idx_inst(decoder->decode(set_gpr_idx_words.data())); + ASSERT_NE(set_gpr_idx_inst, nullptr); + EXPECT_EQ(set_gpr_idx_inst->size(), sizeof(uint32_t)); + + cdna4::Sop1MachineInst get_pc{}; + get_pc.ssrc0 = 255; + get_pc.op = cdna4::kSGetPcB64Sop1; + get_pc.sdst = 0; + get_pc.encoding = cdna4::encoding::kSop1; + const auto get_pc_words = std::bit_cast>(get_pc); + std::unique_ptr get_pc_inst(decoder->decode(get_pc_words.data())); + ASSERT_NE(get_pc_inst, nullptr); + EXPECT_EQ(get_pc_inst->size(), sizeof(uint32_t)); + + cdna4::Sop2MachineInst fork{}; + fork.ssrc0 = 255; + fork.ssrc1 = 255; + fork.op = cdna4::kSCbranchGForkSop2; + fork.encoding = cdna4::encoding::kSop2 >> 7; + const auto fork_words = std::bit_cast>(fork); + EXPECT_THROW( + { std::unique_ptr fork_inst(decoder->decode(fork_words.data())); }, + util::InvalidInst); + + cdna4::Vop1MachineInst v_nop{}; + v_nop.src0 = 255; + v_nop.op = cdna4::kVNopVop1; + v_nop.encoding = cdna4::encoding::kVop1 >> 2; + const auto v_nop_words = std::bit_cast>(v_nop); + std::unique_ptr v_nop_inst(decoder->decode(v_nop_words.data())); + ASSERT_NE(v_nop_inst, nullptr); + EXPECT_EQ(v_nop_inst->size(), sizeof(uint32_t)); + + cdna4::Sop1MachineInst scalar_literal{}; + scalar_literal.ssrc0 = 255; + scalar_literal.op = cdna4::kSNotB32Sop1; + scalar_literal.sdst = 0; + scalar_literal.encoding = cdna4::encoding::kSop1; + const std::array scalar_literal_words = {std::bit_cast(scalar_literal), + 0x12345678u}; + std::unique_ptr scalar_literal_inst(decoder->decode(scalar_literal_words.data())); + ASSERT_NE(scalar_literal_inst, nullptr); + EXPECT_EQ(scalar_literal_inst->size(), sizeof(scalar_literal_words)); +} + void cdna4_unsupported_sdwa_decode_halts_wave() { cdna4::Vop1VopSdwaMachineInst raw{}; raw.src0 = amdgpu::SRC_SDWA; From 536110a083d90100bd4b919d497cb032195618f5 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 18 Aug 2026 19:19:25 -0400 Subject: [PATCH 15/27] [rocjitsu] Model gfx1250 wave ABI state (#10345) Model the architectural wave state that gfx1250 compiler-generated kernels and debugger paths consume instead of relying on legacy scalar register conventions. Treat scalar selectors 102 and 103 as ordinary SGPRs on GFX10+ targets, preserve Wave32 VCC_HI scratch across vector predicate and carry writes, and expose explicit masked VCC access for VCCZ. Keep the flat-scratch encoding policy architecture-explicit so unknown future targets do not inherit the legacy alias. Populate the gfx1250 TTMP launch payload from the AQL dispatch: encode the queue packet index, wave-in-workgroup position, and Y/Z validity in TTMP8, while retaining the architected workgroup and cluster coordinates in TTMP6, TTMP7, and TTMP9. Extend execution and dispatch tests across every scalar resolver direction, both VCC execution paths, one- and two-dimensional TTMP layouts, and nonzero queue slots. (cherry picked from commit c1dba564e7e3a9158ce56bd0d314c7769ca0a073) --- .../amdisa/codegen/execute/sema_lower.py | 4 +- .../amdisa/codegen/execute/vector_cmp.py | 10 +- .../amdisa/codegen/execute/vector_special.py | 2 +- .../amdisa/tests/test_gen_vector_cmpx.py | 10 +- .../arch/amdgpu/generated/cdna1/vop3_exec.cpp | 6 +- .../arch/amdgpu/generated/cdna1/vopc_exec.cpp | 198 ++++++++-------- .../arch/amdgpu/generated/cdna2/vop3_exec.cpp | 6 +- .../arch/amdgpu/generated/cdna2/vopc_exec.cpp | 198 ++++++++-------- .../arch/amdgpu/generated/cdna3/vop3_exec.cpp | 6 +- .../arch/amdgpu/generated/cdna3/vopc_exec.cpp | 198 ++++++++-------- .../arch/amdgpu/generated/cdna4/vop3_exec.cpp | 6 +- .../arch/amdgpu/generated/cdna4/vopc_exec.cpp | 198 ++++++++-------- .../amdgpu/generated/shared/execute_shared.h | 222 +++++++++--------- .../amdgpu/shared/scalar_operand_resolve.h | 22 +- .../isa/arch/amdgpu/shared/simd_glue.h | 8 +- .../rocjitsu/src/rocjitsu/isa/isa_traits.h | 23 ++ .../rocjitsu/vm/amdgpu/command_processor.cpp | 22 +- .../rocjitsu/vm/amdgpu/command_processor.h | 2 +- .../src/rocjitsu/vm/amdgpu/dispatch_entry.h | 2 + .../src/rocjitsu/vm/amdgpu/wavefront.h | 22 +- .../tests/cdna5_dispatch_memory_test.cpp | 38 +++ .../rocjitsu/tests/cdna5_execution_test.cpp | 114 +++++++++ 22 files changed, 759 insertions(+), 558 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/sema_lower.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/sema_lower.py index 4e3609737074..684cd8eeacb2 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/sema_lower.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/sema_lower.py @@ -272,12 +272,12 @@ def _vcc_write_stmt(ctx: LoweringContext) -> str: if ctx.vcc_dst and ctx.vcc_dst != '__vcc__': return _write_vcc_mask_to_explicit_dst(ctx.vcc_dst) if ctx.vcc_dst == '__vcc__': - return 'wf.set_vcc(vcc);' + return 'wf.set_vcc_mask(vcc);' if ctx.operand_map: dst = ctx.operand_map.dst(0) if dst: return _write_vcc_mask_to_explicit_dst(dst.name) - return 'wf.set_vcc(vcc);' + return 'wf.set_vcc_mask(vcc);' def _indent(ctx: LoweringContext) -> str: diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_cmp.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_cmp.py index 44d4dd557983..a090cdc4fac1 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_cmp.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_cmp.py @@ -163,12 +163,12 @@ def gen_vector_cmp_class( L.append(' }') if is_cmpx: if cmpx_writes_vcc: - L.append(' wf.set_vcc(result);') + L.append(' wf.set_vcc_mask(result);') L.append(' wf.set_exec(result);') elif dst: L.extend(_write_explicit_lane_mask(dst[0], 'vcc')) else: - L.append(' wf.set_vcc(vcc);') + L.append(' wf.set_vcc_mask(vcc);') return '\n'.join(L) @@ -372,7 +372,7 @@ def gen_vector_cmp( L.extend(_write_explicit_lane_mask(dst[0], 'vcc')) else: # VOPC: write to VCC. - L.append(' wf.set_vcc(vcc);') + L.append(' wf.set_vcc_mask(vcc);') return '\n'.join(L) @@ -412,7 +412,7 @@ def gen_vector_cmpx( if dst and is_vop3: L.extend(_write_explicit_lane_mask(dst[0], 'result')) else: - L.append(' wf.set_vcc(result);') + L.append(' wf.set_vcc_mask(result);') L.append(' wf.set_exec(result);') return '\n'.join(L) @@ -498,5 +498,5 @@ def gen_vector_add_co( # VOP3_SDST_ENC: carry-out goes to sdst (any SGPR pair). L.extend(_write_explicit_lane_mask(dst[1], 'vcc')) else: - L.append(' wf.set_vcc(vcc);') + L.append(' wf.set_vcc_mask(vcc);') return '\n'.join(L) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py index e73534b3a6fe..44eccdbbb637 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py @@ -586,7 +586,7 @@ def gen_vector_div_scale( if len(dst) > 1: L.append(f' amdgpu::write_wave_mask_scalar({dst[1]}, wf, vcc);') else: - L.append(' wf.set_vcc(vcc);') + L.append(' wf.set_vcc_mask(vcc);') return '\n'.join(L) diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_gen_vector_cmpx.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_gen_vector_cmpx.py index e6fbf960909d..d724fd40ebfd 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_gen_vector_cmpx.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_gen_vector_cmpx.py @@ -101,7 +101,7 @@ def _make_codegen(profile) -> CodeGenerator: # Regex tolerant to whitespace and identifier choice. We anchor on the # stable parts of the contract — the wave-mask helper calls -# ``set_vcc``, ``set_exec``) and the dst identifier — not on the exact +# ``set_vcc_mask``, ``set_exec``) and the dst identifier — not on the exact # variable name of the result-mask local. def _re_write_wave_mask(dst_ident: str) -> re.Pattern[str]: return re.compile( @@ -110,7 +110,7 @@ def _re_write_wave_mask(dst_ident: str) -> re.Pattern[str]: ) -_RE_SET_VCC = re.compile(r'\bwf\s*\.\s*set_vcc\s*\(\s*\w+\s*\)\s*;') +_RE_SET_VCC = re.compile(r'\bwf\s*\.\s*set_vcc_mask\s*\(\s*\w+\s*\)\s*;') _RE_SET_EXEC = re.compile(r'\bwf\s*\.\s*set_exec\s*\(\s*\w+\s*\)\s*;') _RE_ANY_WRITE_WAVE_MASK = re.compile(r'\bamdgpu::write_wave_mask_scalar\s*\(') @@ -147,7 +147,7 @@ class TestGenVectorCmpxWriteBacks: * ``set_exec`` is emitted unconditionally. * a wave-size-width-aware write on the SDST is emitted iff ``profile.cmpx_writes_vcc and is_vop3 and dst``. - * ``set_vcc`` is emitted iff + * ``set_vcc_mask`` is emitted iff ``profile.cmpx_writes_vcc and not (is_vop3 and dst)``. The ``op='t'`` shortcut is intentional: it bypasses ``_cmp_condition`` @@ -200,11 +200,11 @@ def test_writeback_invariants( # VCC write: must appear iff expected. vcc_match = _RE_SET_VCC.search(body) if expect_vcc_write: - assert vcc_match, f'Expected wf.set_vcc(...) call; body was:\n{body}' + assert vcc_match, f'Expected wf.set_vcc_mask(...) call; body was:\n{body}' else: assert ( not vcc_match - ), f'Did not expect wf.set_vcc(...) call; body was:\n{body}' + ), f'Did not expect wf.set_vcc_mask(...) call; body was:\n{body}' # Mutual exclusion: a single V_CMPX never writes both VCC and SDST. assert not ( diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3_exec.cpp index d752308db9d3..14a51048ac77 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3_exec.cpp @@ -2903,7 +2903,7 @@ void VCmpxClassF32Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2951,7 +2951,7 @@ void VCmpxClassF64Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3076,7 +3076,7 @@ void VCmpxClassF16Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc_exec.cpp index 0849539180be..3e48731ff760 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc_exec.cpp @@ -95,7 +95,7 @@ void VCmpxClassF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -147,7 +147,7 @@ void VCmpxClassF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -231,7 +231,7 @@ void VCmpxClassF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -681,7 +681,7 @@ void VCmpxFF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -720,7 +720,7 @@ void VCmpxLtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -759,7 +759,7 @@ void VCmpxEqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -798,7 +798,7 @@ void VCmpxLeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -837,7 +837,7 @@ void VCmpxGtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -876,7 +876,7 @@ void VCmpxLgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -915,7 +915,7 @@ void VCmpxGeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -954,7 +954,7 @@ void VCmpxOF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -993,7 +993,7 @@ void VCmpxUF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1032,7 +1032,7 @@ void VCmpxNgeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1071,7 +1071,7 @@ void VCmpxNlgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1110,7 +1110,7 @@ void VCmpxNgtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1149,7 +1149,7 @@ void VCmpxNleF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1188,7 +1188,7 @@ void VCmpxNeqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1227,7 +1227,7 @@ void VCmpxNltF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1261,7 +1261,7 @@ void VCmpxTruF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1711,7 +1711,7 @@ void VCmpxFF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1748,7 +1748,7 @@ void VCmpxLtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1785,7 +1785,7 @@ void VCmpxEqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1822,7 +1822,7 @@ void VCmpxLeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1859,7 +1859,7 @@ void VCmpxGtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1896,7 +1896,7 @@ void VCmpxLgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1933,7 +1933,7 @@ void VCmpxGeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1970,7 +1970,7 @@ void VCmpxOF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2007,7 +2007,7 @@ void VCmpxUF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2044,7 +2044,7 @@ void VCmpxNgeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2081,7 +2081,7 @@ void VCmpxNlgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2118,7 +2118,7 @@ void VCmpxNgtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2155,7 +2155,7 @@ void VCmpxNleF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2192,7 +2192,7 @@ void VCmpxNeqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2229,7 +2229,7 @@ void VCmpxNltF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2263,7 +2263,7 @@ void VCmpxTruF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2347,7 +2347,7 @@ void VCmpxFF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2362,7 +2362,7 @@ void VCmpxLtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2377,7 +2377,7 @@ void VCmpxEqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2392,7 +2392,7 @@ void VCmpxLeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2407,7 +2407,7 @@ void VCmpxGtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2422,7 +2422,7 @@ void VCmpxLgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2437,7 +2437,7 @@ void VCmpxGeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2452,7 +2452,7 @@ void VCmpxOF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2467,7 +2467,7 @@ void VCmpxUF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2482,7 +2482,7 @@ void VCmpxNgeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2497,7 +2497,7 @@ void VCmpxNlgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2512,7 +2512,7 @@ void VCmpxNgtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2527,7 +2527,7 @@ void VCmpxNleF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2542,7 +2542,7 @@ void VCmpxNeqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2557,7 +2557,7 @@ void VCmpxNltF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2569,7 +2569,7 @@ void VCmpxTruF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3011,7 +3011,7 @@ void VCmpxFI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3048,7 +3048,7 @@ void VCmpxLtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3085,7 +3085,7 @@ void VCmpxEqI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3122,7 +3122,7 @@ void VCmpxLeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3159,7 +3159,7 @@ void VCmpxGtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3196,7 +3196,7 @@ void VCmpxNeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3233,7 +3233,7 @@ void VCmpxGeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3267,7 +3267,7 @@ void VCmpxTI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3301,7 +3301,7 @@ void VCmpxFU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3338,7 +3338,7 @@ void VCmpxLtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3375,7 +3375,7 @@ void VCmpxEqU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3412,7 +3412,7 @@ void VCmpxLeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3449,7 +3449,7 @@ void VCmpxGtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3486,7 +3486,7 @@ void VCmpxNeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3523,7 +3523,7 @@ void VCmpxGeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3557,7 +3557,7 @@ void VCmpxTU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4007,7 +4007,7 @@ void VCmpxFI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4044,7 +4044,7 @@ void VCmpxLtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4081,7 +4081,7 @@ void VCmpxEqI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4118,7 +4118,7 @@ void VCmpxLeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4155,7 +4155,7 @@ void VCmpxGtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4192,7 +4192,7 @@ void VCmpxNeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4229,7 +4229,7 @@ void VCmpxGeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4263,7 +4263,7 @@ void VCmpxTI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4297,7 +4297,7 @@ void VCmpxFU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4334,7 +4334,7 @@ void VCmpxLtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4371,7 +4371,7 @@ void VCmpxEqU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4408,7 +4408,7 @@ void VCmpxLeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4445,7 +4445,7 @@ void VCmpxGtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4482,7 +4482,7 @@ void VCmpxNeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4519,7 +4519,7 @@ void VCmpxGeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4553,7 +4553,7 @@ void VCmpxTU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4637,7 +4637,7 @@ void VCmpxFI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4652,7 +4652,7 @@ void VCmpxLtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4667,7 +4667,7 @@ void VCmpxEqI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4682,7 +4682,7 @@ void VCmpxLeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4697,7 +4697,7 @@ void VCmpxGtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4712,7 +4712,7 @@ void VCmpxNeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4727,7 +4727,7 @@ void VCmpxGeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4739,7 +4739,7 @@ void VCmpxTI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4751,7 +4751,7 @@ void VCmpxFU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4766,7 +4766,7 @@ void VCmpxLtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4781,7 +4781,7 @@ void VCmpxEqU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4796,7 +4796,7 @@ void VCmpxLeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4811,7 +4811,7 @@ void VCmpxGtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4826,7 +4826,7 @@ void VCmpxNeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4841,7 +4841,7 @@ void VCmpxGeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4853,7 +4853,7 @@ void VCmpxTU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3_exec.cpp index eadb4fa976b8..b4a815165456 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3_exec.cpp @@ -2879,7 +2879,7 @@ void VCmpxClassF32Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2927,7 +2927,7 @@ void VCmpxClassF64Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3052,7 +3052,7 @@ void VCmpxClassF16Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc_exec.cpp index a31cf19ddf77..e9bc56ab7b23 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc_exec.cpp @@ -95,7 +95,7 @@ void VCmpxClassF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -147,7 +147,7 @@ void VCmpxClassF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -231,7 +231,7 @@ void VCmpxClassF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -681,7 +681,7 @@ void VCmpxFF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -720,7 +720,7 @@ void VCmpxLtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -759,7 +759,7 @@ void VCmpxEqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -798,7 +798,7 @@ void VCmpxLeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -837,7 +837,7 @@ void VCmpxGtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -876,7 +876,7 @@ void VCmpxLgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -915,7 +915,7 @@ void VCmpxGeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -954,7 +954,7 @@ void VCmpxOF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -993,7 +993,7 @@ void VCmpxUF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1032,7 +1032,7 @@ void VCmpxNgeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1071,7 +1071,7 @@ void VCmpxNlgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1110,7 +1110,7 @@ void VCmpxNgtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1149,7 +1149,7 @@ void VCmpxNleF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1188,7 +1188,7 @@ void VCmpxNeqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1227,7 +1227,7 @@ void VCmpxNltF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1261,7 +1261,7 @@ void VCmpxTruF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1711,7 +1711,7 @@ void VCmpxFF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1748,7 +1748,7 @@ void VCmpxLtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1785,7 +1785,7 @@ void VCmpxEqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1822,7 +1822,7 @@ void VCmpxLeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1859,7 +1859,7 @@ void VCmpxGtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1896,7 +1896,7 @@ void VCmpxLgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1933,7 +1933,7 @@ void VCmpxGeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1970,7 +1970,7 @@ void VCmpxOF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2007,7 +2007,7 @@ void VCmpxUF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2044,7 +2044,7 @@ void VCmpxNgeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2081,7 +2081,7 @@ void VCmpxNlgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2118,7 +2118,7 @@ void VCmpxNgtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2155,7 +2155,7 @@ void VCmpxNleF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2192,7 +2192,7 @@ void VCmpxNeqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2229,7 +2229,7 @@ void VCmpxNltF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2263,7 +2263,7 @@ void VCmpxTruF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2347,7 +2347,7 @@ void VCmpxFF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2362,7 +2362,7 @@ void VCmpxLtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2377,7 +2377,7 @@ void VCmpxEqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2392,7 +2392,7 @@ void VCmpxLeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2407,7 +2407,7 @@ void VCmpxGtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2422,7 +2422,7 @@ void VCmpxLgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2437,7 +2437,7 @@ void VCmpxGeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2452,7 +2452,7 @@ void VCmpxOF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2467,7 +2467,7 @@ void VCmpxUF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2482,7 +2482,7 @@ void VCmpxNgeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2497,7 +2497,7 @@ void VCmpxNlgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2512,7 +2512,7 @@ void VCmpxNgtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2527,7 +2527,7 @@ void VCmpxNleF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2542,7 +2542,7 @@ void VCmpxNeqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2557,7 +2557,7 @@ void VCmpxNltF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2569,7 +2569,7 @@ void VCmpxTruF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3011,7 +3011,7 @@ void VCmpxFI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3048,7 +3048,7 @@ void VCmpxLtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3085,7 +3085,7 @@ void VCmpxEqI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3122,7 +3122,7 @@ void VCmpxLeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3159,7 +3159,7 @@ void VCmpxGtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3196,7 +3196,7 @@ void VCmpxNeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3233,7 +3233,7 @@ void VCmpxGeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3267,7 +3267,7 @@ void VCmpxTI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3301,7 +3301,7 @@ void VCmpxFU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3338,7 +3338,7 @@ void VCmpxLtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3375,7 +3375,7 @@ void VCmpxEqU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3412,7 +3412,7 @@ void VCmpxLeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3449,7 +3449,7 @@ void VCmpxGtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3486,7 +3486,7 @@ void VCmpxNeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3523,7 +3523,7 @@ void VCmpxGeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3557,7 +3557,7 @@ void VCmpxTU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4007,7 +4007,7 @@ void VCmpxFI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4044,7 +4044,7 @@ void VCmpxLtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4081,7 +4081,7 @@ void VCmpxEqI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4118,7 +4118,7 @@ void VCmpxLeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4155,7 +4155,7 @@ void VCmpxGtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4192,7 +4192,7 @@ void VCmpxNeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4229,7 +4229,7 @@ void VCmpxGeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4263,7 +4263,7 @@ void VCmpxTI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4297,7 +4297,7 @@ void VCmpxFU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4334,7 +4334,7 @@ void VCmpxLtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4371,7 +4371,7 @@ void VCmpxEqU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4408,7 +4408,7 @@ void VCmpxLeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4445,7 +4445,7 @@ void VCmpxGtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4482,7 +4482,7 @@ void VCmpxNeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4519,7 +4519,7 @@ void VCmpxGeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4553,7 +4553,7 @@ void VCmpxTU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4637,7 +4637,7 @@ void VCmpxFI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4652,7 +4652,7 @@ void VCmpxLtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4667,7 +4667,7 @@ void VCmpxEqI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4682,7 +4682,7 @@ void VCmpxLeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4697,7 +4697,7 @@ void VCmpxGtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4712,7 +4712,7 @@ void VCmpxNeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4727,7 +4727,7 @@ void VCmpxGeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4739,7 +4739,7 @@ void VCmpxTI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4751,7 +4751,7 @@ void VCmpxFU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4766,7 +4766,7 @@ void VCmpxLtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4781,7 +4781,7 @@ void VCmpxEqU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4796,7 +4796,7 @@ void VCmpxLeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4811,7 +4811,7 @@ void VCmpxGtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4826,7 +4826,7 @@ void VCmpxNeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4841,7 +4841,7 @@ void VCmpxGeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4853,7 +4853,7 @@ void VCmpxTU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3_exec.cpp index 134d43a621e5..681b33228af7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3_exec.cpp @@ -3014,7 +3014,7 @@ void VCmpxClassF32Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3062,7 +3062,7 @@ void VCmpxClassF64Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3187,7 +3187,7 @@ void VCmpxClassF16Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc_exec.cpp index 99656d78965b..401c21b16a1b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc_exec.cpp @@ -95,7 +95,7 @@ void VCmpxClassF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -147,7 +147,7 @@ void VCmpxClassF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -231,7 +231,7 @@ void VCmpxClassF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -681,7 +681,7 @@ void VCmpxFF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -720,7 +720,7 @@ void VCmpxLtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -759,7 +759,7 @@ void VCmpxEqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -798,7 +798,7 @@ void VCmpxLeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -837,7 +837,7 @@ void VCmpxGtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -876,7 +876,7 @@ void VCmpxLgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -915,7 +915,7 @@ void VCmpxGeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -954,7 +954,7 @@ void VCmpxOF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -993,7 +993,7 @@ void VCmpxUF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1032,7 +1032,7 @@ void VCmpxNgeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1071,7 +1071,7 @@ void VCmpxNlgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1110,7 +1110,7 @@ void VCmpxNgtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1149,7 +1149,7 @@ void VCmpxNleF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1188,7 +1188,7 @@ void VCmpxNeqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1227,7 +1227,7 @@ void VCmpxNltF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1261,7 +1261,7 @@ void VCmpxTruF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1711,7 +1711,7 @@ void VCmpxFF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1748,7 +1748,7 @@ void VCmpxLtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1785,7 +1785,7 @@ void VCmpxEqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1822,7 +1822,7 @@ void VCmpxLeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1859,7 +1859,7 @@ void VCmpxGtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1896,7 +1896,7 @@ void VCmpxLgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1933,7 +1933,7 @@ void VCmpxGeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1970,7 +1970,7 @@ void VCmpxOF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2007,7 +2007,7 @@ void VCmpxUF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2044,7 +2044,7 @@ void VCmpxNgeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2081,7 +2081,7 @@ void VCmpxNlgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2118,7 +2118,7 @@ void VCmpxNgtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2155,7 +2155,7 @@ void VCmpxNleF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2192,7 +2192,7 @@ void VCmpxNeqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2229,7 +2229,7 @@ void VCmpxNltF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2263,7 +2263,7 @@ void VCmpxTruF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2347,7 +2347,7 @@ void VCmpxFF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2362,7 +2362,7 @@ void VCmpxLtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2377,7 +2377,7 @@ void VCmpxEqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2392,7 +2392,7 @@ void VCmpxLeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2407,7 +2407,7 @@ void VCmpxGtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2422,7 +2422,7 @@ void VCmpxLgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2437,7 +2437,7 @@ void VCmpxGeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2452,7 +2452,7 @@ void VCmpxOF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2467,7 +2467,7 @@ void VCmpxUF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2482,7 +2482,7 @@ void VCmpxNgeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2497,7 +2497,7 @@ void VCmpxNlgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2512,7 +2512,7 @@ void VCmpxNgtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2527,7 +2527,7 @@ void VCmpxNleF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2542,7 +2542,7 @@ void VCmpxNeqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2557,7 +2557,7 @@ void VCmpxNltF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2569,7 +2569,7 @@ void VCmpxTruF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3011,7 +3011,7 @@ void VCmpxFI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3048,7 +3048,7 @@ void VCmpxLtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3085,7 +3085,7 @@ void VCmpxEqI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3122,7 +3122,7 @@ void VCmpxLeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3159,7 +3159,7 @@ void VCmpxGtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3196,7 +3196,7 @@ void VCmpxNeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3233,7 +3233,7 @@ void VCmpxGeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3267,7 +3267,7 @@ void VCmpxTI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3301,7 +3301,7 @@ void VCmpxFU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3338,7 +3338,7 @@ void VCmpxLtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3375,7 +3375,7 @@ void VCmpxEqU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3412,7 +3412,7 @@ void VCmpxLeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3449,7 +3449,7 @@ void VCmpxGtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3486,7 +3486,7 @@ void VCmpxNeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3523,7 +3523,7 @@ void VCmpxGeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3557,7 +3557,7 @@ void VCmpxTU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4007,7 +4007,7 @@ void VCmpxFI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4044,7 +4044,7 @@ void VCmpxLtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4081,7 +4081,7 @@ void VCmpxEqI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4118,7 +4118,7 @@ void VCmpxLeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4155,7 +4155,7 @@ void VCmpxGtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4192,7 +4192,7 @@ void VCmpxNeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4229,7 +4229,7 @@ void VCmpxGeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4263,7 +4263,7 @@ void VCmpxTI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4297,7 +4297,7 @@ void VCmpxFU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4334,7 +4334,7 @@ void VCmpxLtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4371,7 +4371,7 @@ void VCmpxEqU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4408,7 +4408,7 @@ void VCmpxLeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4445,7 +4445,7 @@ void VCmpxGtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4482,7 +4482,7 @@ void VCmpxNeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4519,7 +4519,7 @@ void VCmpxGeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4553,7 +4553,7 @@ void VCmpxTU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4637,7 +4637,7 @@ void VCmpxFI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4652,7 +4652,7 @@ void VCmpxLtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4667,7 +4667,7 @@ void VCmpxEqI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4682,7 +4682,7 @@ void VCmpxLeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4697,7 +4697,7 @@ void VCmpxGtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4712,7 +4712,7 @@ void VCmpxNeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4727,7 +4727,7 @@ void VCmpxGeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4739,7 +4739,7 @@ void VCmpxTI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4751,7 +4751,7 @@ void VCmpxFU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4766,7 +4766,7 @@ void VCmpxLtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4781,7 +4781,7 @@ void VCmpxEqU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4796,7 +4796,7 @@ void VCmpxLeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4811,7 +4811,7 @@ void VCmpxGtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4826,7 +4826,7 @@ void VCmpxNeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4841,7 +4841,7 @@ void VCmpxGeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4853,7 +4853,7 @@ void VCmpxTU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3_exec.cpp index fc83d395e62d..cdc15dd744d9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3_exec.cpp @@ -7331,7 +7331,7 @@ void VCmpxClassF32Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -7379,7 +7379,7 @@ void VCmpxClassF64Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -7504,7 +7504,7 @@ void VCmpxClassF16Vop3::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc_exec.cpp index 64ded9defde8..4061f3040268 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc_exec.cpp @@ -95,7 +95,7 @@ void VCmpxClassF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -147,7 +147,7 @@ void VCmpxClassF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -231,7 +231,7 @@ void VCmpxClassF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (match) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -681,7 +681,7 @@ void VCmpxFF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -720,7 +720,7 @@ void VCmpxLtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -759,7 +759,7 @@ void VCmpxEqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -798,7 +798,7 @@ void VCmpxLeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -837,7 +837,7 @@ void VCmpxGtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -876,7 +876,7 @@ void VCmpxLgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -915,7 +915,7 @@ void VCmpxGeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -954,7 +954,7 @@ void VCmpxOF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -993,7 +993,7 @@ void VCmpxUF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1032,7 +1032,7 @@ void VCmpxNgeF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1071,7 +1071,7 @@ void VCmpxNlgF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1110,7 +1110,7 @@ void VCmpxNgtF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1149,7 +1149,7 @@ void VCmpxNleF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1188,7 +1188,7 @@ void VCmpxNeqF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1227,7 +1227,7 @@ void VCmpxNltF16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1261,7 +1261,7 @@ void VCmpxTruF16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1711,7 +1711,7 @@ void VCmpxFF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1748,7 +1748,7 @@ void VCmpxLtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1785,7 +1785,7 @@ void VCmpxEqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1822,7 +1822,7 @@ void VCmpxLeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1859,7 +1859,7 @@ void VCmpxGtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1896,7 +1896,7 @@ void VCmpxLgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1933,7 +1933,7 @@ void VCmpxGeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -1970,7 +1970,7 @@ void VCmpxOF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2007,7 +2007,7 @@ void VCmpxUF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2044,7 +2044,7 @@ void VCmpxNgeF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2081,7 +2081,7 @@ void VCmpxNlgF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2118,7 +2118,7 @@ void VCmpxNgtF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2155,7 +2155,7 @@ void VCmpxNleF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2192,7 +2192,7 @@ void VCmpxNeqF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2229,7 +2229,7 @@ void VCmpxNltF32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2263,7 +2263,7 @@ void VCmpxTruF32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -2347,7 +2347,7 @@ void VCmpxFF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2362,7 +2362,7 @@ void VCmpxLtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2377,7 +2377,7 @@ void VCmpxEqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2392,7 +2392,7 @@ void VCmpxLeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2407,7 +2407,7 @@ void VCmpxGtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2422,7 +2422,7 @@ void VCmpxLgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1 || s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2437,7 +2437,7 @@ void VCmpxGeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2452,7 +2452,7 @@ void VCmpxOF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!std::isnan(s0) && !std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2467,7 +2467,7 @@ void VCmpxUF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2482,7 +2482,7 @@ void VCmpxNgeF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 >= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2497,7 +2497,7 @@ void VCmpxNlgF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1 || s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2512,7 +2512,7 @@ void VCmpxNgtF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 > s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2527,7 +2527,7 @@ void VCmpxNleF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 <= s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2542,7 +2542,7 @@ void VCmpxNeqF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1 || std::isnan(s0) || std::isnan(s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2557,7 +2557,7 @@ void VCmpxNltF64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (!(s0 < s1)) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -2569,7 +2569,7 @@ void VCmpxTruF64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -3011,7 +3011,7 @@ void VCmpxFI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3048,7 +3048,7 @@ void VCmpxLtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3085,7 +3085,7 @@ void VCmpxEqI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3122,7 +3122,7 @@ void VCmpxLeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3159,7 +3159,7 @@ void VCmpxGtI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3196,7 +3196,7 @@ void VCmpxNeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3233,7 +3233,7 @@ void VCmpxGeI16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3267,7 +3267,7 @@ void VCmpxTI16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3301,7 +3301,7 @@ void VCmpxFU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3338,7 +3338,7 @@ void VCmpxLtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3375,7 +3375,7 @@ void VCmpxEqU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3412,7 +3412,7 @@ void VCmpxLeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3449,7 +3449,7 @@ void VCmpxGtU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3486,7 +3486,7 @@ void VCmpxNeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3523,7 +3523,7 @@ void VCmpxGeU16Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -3557,7 +3557,7 @@ void VCmpxTU16Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4007,7 +4007,7 @@ void VCmpxFI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4044,7 +4044,7 @@ void VCmpxLtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4081,7 +4081,7 @@ void VCmpxEqI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4118,7 +4118,7 @@ void VCmpxLeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4155,7 +4155,7 @@ void VCmpxGtI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4192,7 +4192,7 @@ void VCmpxNeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4229,7 +4229,7 @@ void VCmpxGeI32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4263,7 +4263,7 @@ void VCmpxTI32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4297,7 +4297,7 @@ void VCmpxFU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4334,7 +4334,7 @@ void VCmpxLtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4371,7 +4371,7 @@ void VCmpxEqU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4408,7 +4408,7 @@ void VCmpxLeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4445,7 +4445,7 @@ void VCmpxGtU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4482,7 +4482,7 @@ void VCmpxNeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4519,7 +4519,7 @@ void VCmpxGeU32Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4553,7 +4553,7 @@ void VCmpxTU32Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); if (inst_.src0 == amdgpu::SRC_SDWA && sdwa_sd_) { uint64_t cmp_result = wf.vcc(); @@ -4637,7 +4637,7 @@ void VCmpxFI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4652,7 +4652,7 @@ void VCmpxLtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4667,7 +4667,7 @@ void VCmpxEqI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4682,7 +4682,7 @@ void VCmpxLeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4697,7 +4697,7 @@ void VCmpxGtI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4712,7 +4712,7 @@ void VCmpxNeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4727,7 +4727,7 @@ void VCmpxGeI64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4739,7 +4739,7 @@ void VCmpxTI64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4751,7 +4751,7 @@ void VCmpxFU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; (void)lane; } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4766,7 +4766,7 @@ void VCmpxLtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 < s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4781,7 +4781,7 @@ void VCmpxEqU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 == s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4796,7 +4796,7 @@ void VCmpxLeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 <= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4811,7 +4811,7 @@ void VCmpxGtU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 > s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4826,7 +4826,7 @@ void VCmpxNeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 != s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4841,7 +4841,7 @@ void VCmpxGeU64Vopc::execute_impl(amdgpu::Wavefront &wf) { if (s0 >= s1) result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } @@ -4853,7 +4853,7 @@ void VCmpxTU64Vopc::execute_impl(amdgpu::Wavefront &wf) { continue; result |= (1ULL << lane); } - wf.set_vcc(result); + wf.set_vcc_mask(result); wf.set_exec(result); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h index 5f0f71fb1edd..7c563c3fffcb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h @@ -2836,7 +2836,7 @@ inline void execute_v_add_co_ci_u32_vop2([[maybe_unused]] Inst &inst, return static_cast(w); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -2890,7 +2890,7 @@ inline void execute_v_add_co_u32_vop2([[maybe_unused]] Inst &inst, [[maybe_unuse return static_cast(w); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -3275,7 +3275,7 @@ inline void execute_v_addc_co_u32_vop2([[maybe_unused]] Inst &inst, return static_cast(w); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4020,7 +4020,7 @@ inline void execute_v_cmp_class_f16_vopc([[maybe_unused]] Inst &inst, if (match) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4150,7 +4150,7 @@ inline void execute_v_cmp_class_f32_vopc([[maybe_unused]] Inst &inst, if (match) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4288,7 +4288,7 @@ inline void execute_v_cmp_class_f64_vopc([[maybe_unused]] Inst &inst, if (match) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4338,7 +4338,7 @@ inline void execute_v_cmp_eq_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4382,7 +4382,7 @@ inline void execute_v_cmp_eq_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4428,7 +4428,7 @@ inline void execute_v_cmp_eq_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4460,7 +4460,7 @@ inline void execute_v_cmp_eq_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4490,7 +4490,7 @@ inline void execute_v_cmp_eq_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4520,7 +4520,7 @@ inline void execute_v_cmp_eq_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4549,7 +4549,7 @@ inline void execute_v_cmp_eq_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4579,7 +4579,7 @@ inline void execute_v_cmp_eq_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4609,7 +4609,7 @@ inline void execute_v_cmp_eq_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4639,7 +4639,7 @@ inline void execute_v_cmp_f_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4667,7 +4667,7 @@ inline void execute_v_cmp_f_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4695,7 +4695,7 @@ inline void execute_v_cmp_f_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4712,7 +4712,7 @@ inline void execute_v_cmp_f_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4740,7 +4740,7 @@ inline void execute_v_cmp_f_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4769,7 +4769,7 @@ inline void execute_v_cmp_f_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4784,7 +4784,7 @@ inline void execute_v_cmp_f_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4812,7 +4812,7 @@ inline void execute_v_cmp_f_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4841,7 +4841,7 @@ inline void execute_v_cmp_f_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (0) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4891,7 +4891,7 @@ inline void execute_v_cmp_ge_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4935,7 +4935,7 @@ inline void execute_v_cmp_ge_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -4981,7 +4981,7 @@ inline void execute_v_cmp_ge_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5013,7 +5013,7 @@ inline void execute_v_cmp_ge_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5043,7 +5043,7 @@ inline void execute_v_cmp_ge_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5073,7 +5073,7 @@ inline void execute_v_cmp_ge_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5102,7 +5102,7 @@ inline void execute_v_cmp_ge_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5132,7 +5132,7 @@ inline void execute_v_cmp_ge_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5162,7 +5162,7 @@ inline void execute_v_cmp_ge_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5211,7 +5211,7 @@ inline void execute_v_cmp_gt_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5255,7 +5255,7 @@ inline void execute_v_cmp_gt_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5301,7 +5301,7 @@ inline void execute_v_cmp_gt_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5333,7 +5333,7 @@ inline void execute_v_cmp_gt_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5363,7 +5363,7 @@ inline void execute_v_cmp_gt_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5393,7 +5393,7 @@ inline void execute_v_cmp_gt_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5422,7 +5422,7 @@ inline void execute_v_cmp_gt_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5452,7 +5452,7 @@ inline void execute_v_cmp_gt_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5482,7 +5482,7 @@ inline void execute_v_cmp_gt_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5532,7 +5532,7 @@ inline void execute_v_cmp_le_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5576,7 +5576,7 @@ inline void execute_v_cmp_le_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5622,7 +5622,7 @@ inline void execute_v_cmp_le_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5654,7 +5654,7 @@ inline void execute_v_cmp_le_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5684,7 +5684,7 @@ inline void execute_v_cmp_le_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5714,7 +5714,7 @@ inline void execute_v_cmp_le_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5743,7 +5743,7 @@ inline void execute_v_cmp_le_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5773,7 +5773,7 @@ inline void execute_v_cmp_le_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5803,7 +5803,7 @@ inline void execute_v_cmp_le_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5860,7 +5860,7 @@ inline void execute_v_cmp_lg_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse }())) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5910,7 +5910,7 @@ inline void execute_v_cmp_lg_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse }())) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -5962,7 +5962,7 @@ inline void execute_v_cmp_lg_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse }())) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6011,7 +6011,7 @@ inline void execute_v_cmp_lt_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6055,7 +6055,7 @@ inline void execute_v_cmp_lt_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6101,7 +6101,7 @@ inline void execute_v_cmp_lt_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6133,7 +6133,7 @@ inline void execute_v_cmp_lt_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6163,7 +6163,7 @@ inline void execute_v_cmp_lt_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6193,7 +6193,7 @@ inline void execute_v_cmp_lt_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6222,7 +6222,7 @@ inline void execute_v_cmp_lt_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6252,7 +6252,7 @@ inline void execute_v_cmp_lt_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6282,7 +6282,7 @@ inline void execute_v_cmp_lt_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6314,7 +6314,7 @@ inline void execute_v_cmp_ne_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6344,7 +6344,7 @@ inline void execute_v_cmp_ne_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6374,7 +6374,7 @@ inline void execute_v_cmp_ne_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6403,7 +6403,7 @@ inline void execute_v_cmp_ne_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6433,7 +6433,7 @@ inline void execute_v_cmp_ne_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6463,7 +6463,7 @@ inline void execute_v_cmp_ne_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unuse static_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6515,7 +6515,7 @@ inline void execute_v_cmp_neq_f16_vopc([[maybe_unused]] Inst &inst, static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6561,7 +6561,7 @@ inline void execute_v_cmp_neq_f32_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6609,7 +6609,7 @@ inline void execute_v_cmp_neq_f64_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane)))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6661,7 +6661,7 @@ inline void execute_v_cmp_nge_f16_vopc([[maybe_unused]] Inst &inst, static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6707,7 +6707,7 @@ inline void execute_v_cmp_nge_f32_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6755,7 +6755,7 @@ inline void execute_v_cmp_nge_f64_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6807,7 +6807,7 @@ inline void execute_v_cmp_ngt_f16_vopc([[maybe_unused]] Inst &inst, static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6853,7 +6853,7 @@ inline void execute_v_cmp_ngt_f32_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6901,7 +6901,7 @@ inline void execute_v_cmp_ngt_f64_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6953,7 +6953,7 @@ inline void execute_v_cmp_nle_f16_vopc([[maybe_unused]] Inst &inst, static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -6999,7 +6999,7 @@ inline void execute_v_cmp_nle_f32_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7047,7 +7047,7 @@ inline void execute_v_cmp_nle_f64_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7106,7 +7106,7 @@ inline void execute_v_cmp_nlg_f16_vopc([[maybe_unused]] Inst &inst, }()))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7158,7 +7158,7 @@ inline void execute_v_cmp_nlg_f32_vopc([[maybe_unused]] Inst &inst, }()))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7212,7 +7212,7 @@ inline void execute_v_cmp_nlg_f64_vopc([[maybe_unused]] Inst &inst, }()))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7264,7 +7264,7 @@ inline void execute_v_cmp_nlt_f16_vopc([[maybe_unused]] Inst &inst, static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7310,7 +7310,7 @@ inline void execute_v_cmp_nlt_f32_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7358,7 +7358,7 @@ inline void execute_v_cmp_nlt_f64_vopc([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7410,7 +7410,7 @@ inline void execute_v_cmp_o_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7456,7 +7456,7 @@ inline void execute_v_cmp_o_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused !std::isnan(std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7506,7 +7506,7 @@ inline void execute_v_cmp_o_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7519,7 +7519,7 @@ inline void execute_v_cmp_t_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7546,7 +7546,7 @@ inline void execute_v_cmp_t_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7573,7 +7573,7 @@ inline void execute_v_cmp_t_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7590,7 +7590,7 @@ inline void execute_v_cmp_t_i16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7618,7 +7618,7 @@ inline void execute_v_cmp_t_i32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7646,7 +7646,7 @@ inline void execute_v_cmp_t_i64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7661,7 +7661,7 @@ inline void execute_v_cmp_t_u16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7689,7 +7689,7 @@ inline void execute_v_cmp_t_u32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7718,7 +7718,7 @@ inline void execute_v_cmp_t_u64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7750,7 +7750,7 @@ inline void execute_v_cmp_tru_f16_vopc([[maybe_unused]] Inst &inst, if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7780,7 +7780,7 @@ inline void execute_v_cmp_tru_f32_vopc([[maybe_unused]] Inst &inst, if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7810,7 +7810,7 @@ inline void execute_v_cmp_tru_f64_vopc([[maybe_unused]] Inst &inst, if (1) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7862,7 +7862,7 @@ inline void execute_v_cmp_u_f16_vopc([[maybe_unused]] Inst &inst, [[maybe_unused static_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane)))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7908,7 +7908,7 @@ inline void execute_v_cmp_u_f32_vopc([[maybe_unused]] Inst &inst, [[maybe_unused std::isnan(std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -7958,7 +7958,7 @@ inline void execute_v_cmp_u_f64_vopc([[maybe_unused]] Inst &inst, [[maybe_unused std::bit_cast(amdgpu::RegisterAccess(wf).read_lane64(inst.vsrc1, lane))))) vcc |= (1ULL << lane); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -18330,7 +18330,7 @@ inline void execute_v_sub_co_ci_u32_vop2([[maybe_unused]] Inst &inst, return static_cast(a - b - c); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -18381,7 +18381,7 @@ inline void execute_v_sub_co_u32_vop2([[maybe_unused]] Inst &inst, [[maybe_unuse return a - b; }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -18688,7 +18688,7 @@ inline void execute_v_subb_co_u32_vop2([[maybe_unused]] Inst &inst, return static_cast(a - b - c); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -18747,7 +18747,7 @@ inline void execute_v_subbrev_co_u32_vop2([[maybe_unused]] Inst &inst, return static_cast(a - b - c); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -18799,7 +18799,7 @@ inline void execute_v_subrev_co_ci_u32_vop2([[maybe_unused]] Inst &inst, return static_cast(a - b - c); }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template @@ -18851,7 +18851,7 @@ inline void execute_v_subrev_co_u32_vop2([[maybe_unused]] Inst &inst, return a - b; }()); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); } template diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h index d1aba9f13a47..426ec1e6e048 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h @@ -26,9 +26,9 @@ namespace amdgpu { // value for this arch (124 on most arches; 125 on RDNA 3 / RDNA 3.5 / RDNA4 // / GFX1250, where 124 is the NULL slot). inline uint32_t resolve_src_scalar(const Wavefront &wf, int ev, int m0_ev) { - if (ev == 102) + if (arch_uses_legacy_flat_scratch_sgprs(wf.cu().arch()) && ev == 102) return static_cast(wf.scratch_base()); - if (ev == 103) + if (arch_uses_legacy_flat_scratch_sgprs(wf.cu().arch()) && ev == 103) return static_cast(wf.scratch_base() >> 32); if (ev <= 105) return RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + static_cast(ev)); @@ -85,13 +85,9 @@ inline uint32_t resolve_src_scalar(const Wavefront &wf, int ev, int m0_ev) { if (ev == 250) return 0u; // NULL if (ev == 251) - return (wf.vcc() & (wf.wf_size() >= 64 ? ~0ULL : ((1ULL << wf.wf_size()) - 1ULL))) == 0 - ? 1u - : 0u; // VCCZ - if (ev == 252) { - uint64_t active = wf.wf_size() >= 64 ? ~0ULL : ((1ULL << wf.wf_size()) - 1ULL); - return (wf.exec() & active) == 0 ? 1u : 0u; // EXECZ - } + return wf.vcc_mask() == 0 ? 1u : 0u; // VCCZ + if (ev == 252) + return wf.exec() == 0 ? 1u : 0u; // EXECZ if (ev == 253) return wf.read_scc() ? 1u : 0u; // SCC throw std::logic_error("Unsupported encoding value for scalar read: " + std::to_string(ev)); @@ -139,7 +135,7 @@ inline bool can_resolve_src_scalar(int ev, int m0_ev) { } inline uint64_t resolve_src_scalar64(const Wavefront &wf, int ev, int m0_ev) { - if (ev == 102) + if (arch_uses_legacy_flat_scratch_sgprs(wf.cu().arch()) && ev == 102) return wf.scratch_base(); if (ev <= 105) { uint32_t lo = RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + static_cast(ev)); @@ -197,12 +193,12 @@ inline uint64_t resolve_src_scalar64(const Wavefront &wf, int ev, int m0_ev) { } inline void resolve_dst_write(Wavefront &wf, int ev, uint32_t val, int m0_ev) { - if (ev == 102) { + if (arch_uses_legacy_flat_scratch_sgprs(wf.cu().arch()) && ev == 102) { uint64_t sb = wf.scratch_base(); wf.set_scratch_base((sb & 0xFFFFFFFF00000000ULL) | val); return; } - if (ev == 103) { + if (arch_uses_legacy_flat_scratch_sgprs(wf.cu().arch()) && ev == 103) { uint64_t sb = wf.scratch_base(); wf.set_scratch_base((sb & 0x00000000FFFFFFFFULL) | (static_cast(val) << 32)); return; @@ -241,7 +237,7 @@ inline void resolve_dst_write(Wavefront &wf, int ev, uint32_t val, int m0_ev) { } inline void resolve_dst_write64(Wavefront &wf, int ev, uint64_t val) { - if (ev == 102) { + if (arch_uses_legacy_flat_scratch_sgprs(wf.cu().arch()) && ev == 102) { wf.set_scratch_base(val); return; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/simd_glue.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/simd_glue.h index 38f121b11601..c117303eb633 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/simd_glue.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/simd_glue.h @@ -628,7 +628,7 @@ template carry_bits |= (1ULL << i); vcc_out = (vcc_out & ~(chunk << base)) | ((carry_bits & chunk) << base); } - wf.set_vcc(vcc_out); + wf.set_vcc_mask(vcc_out); return true; } @@ -1182,7 +1182,7 @@ template cmp_bits |= (1ULL << i); vcc = (vcc & ~(chunk << base)) | ((cmp_bits & chunk) << base); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); return true; } @@ -1218,7 +1218,7 @@ template const uint64_t cmp_bits = cmp_bits64(a, b, cmp_op); vcc = (vcc & ~(chunk << base)) | ((cmp_bits & chunk) << base); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); return true; } @@ -1259,7 +1259,7 @@ template const uint64_t cmp_bits = cmp_class_f64_bits(s, mask, cmp_op); vcc = (vcc & ~(chunk << base)) | ((cmp_bits & chunk) << base); } - wf.set_vcc(vcc); + wf.set_vcc_mask(vcc); return true; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h index e68108635f21..de30b049a31f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h @@ -99,6 +99,29 @@ template inline constexpr bool supports_wave_size(uint32_t wf) { arch == ROCJITSU_CODE_ARCH_RDNA4; } +/// @brief Return true when scalar selectors 102 and 103 name FLAT_SCRATCH. +/// +/// @details GFX10+ makes those selectors ordinary SGPRs. Keep both the legacy +/// and modern architecture sets explicit so an unclassified future target does +/// not silently inherit the legacy register alias. +[[nodiscard]] inline constexpr bool arch_uses_legacy_flat_scratch_sgprs(rj_code_arch_t arch) { + switch (arch) { + case ROCJITSU_CODE_ARCH_CDNA1: + case ROCJITSU_CODE_ARCH_CDNA2: + case ROCJITSU_CODE_ARCH_CDNA3: + case ROCJITSU_CODE_ARCH_CDNA4: + return true; + case ROCJITSU_CODE_ARCH_RDNA1: + case ROCJITSU_CODE_ARCH_RDNA2: + case ROCJITSU_CODE_ARCH_RDNA3: + case ROCJITSU_CODE_ARCH_RDNA3_5: + case ROCJITSU_CODE_ARCH_RDNA4: + case ROCJITSU_CODE_ARCH_GFX1250: + default: + return false; + } +} + /// @brief Maximum SGPR allocation encodable in an AMDHSA descriptor for @p arch. /// /// @details CDNA descriptors account for reserved architectural SGPRs such as diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp index 7ac10722dfc6..23d5ce0ed981 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp @@ -71,11 +71,14 @@ static_assert(kMaxClusterWorkgroups <= 16, // and cluster identity sequences. constexpr uint32_t kGfx12Ttmp6 = 114; constexpr uint32_t kGfx12Ttmp7 = 115; +constexpr uint32_t kGfx12Ttmp8 = 116; constexpr uint32_t kGfx12Ttmp9 = 117; // LLVM's gfx1250 architected-SGPR ABI maps TTMP6 as seven 4-bit fields: // cluster-local XYZ, cluster-max XYZ, and max-flat-ID from low to high bits. -// TTMP7 holds 16-bit cluster-grid Y/Z IDs, while TTMP9 holds cluster-grid X. +// TTMP7 holds 16-bit cluster-grid Y/Z IDs. TTMP8 holds queue-packet ID +// [24:0], wave-in-workgroup [29:25], grid-Y/Z-valid [30], and debug-mark +// [31]. TTMP9 holds cluster-grid X. constexpr uint32_t kGfx12Ttmp6ClusterLocalXShift = 0; constexpr uint32_t kGfx12Ttmp6ClusterLocalYShift = 4; constexpr uint32_t kGfx12Ttmp6ClusterLocalZShift = 8; @@ -84,6 +87,9 @@ constexpr uint32_t kGfx12Ttmp6ClusterMaxYShift = 16; constexpr uint32_t kGfx12Ttmp6ClusterMaxZShift = 20; constexpr uint32_t kGfx12Ttmp6ClusterMaxFlatIdShift = 24; constexpr uint32_t kGfx12Ttmp7ClusterGridDimensionMask = 0xFFFFu; +constexpr uint32_t kGfx12Ttmp8QueuePacketIdMask = 0x1FFFFFFu; +constexpr uint32_t kGfx12Ttmp8WaveIdInGroupShift = 25; +constexpr uint32_t kGfx12Ttmp8GridYzValidShift = 30; struct PlannedWorkgroup { uint32_t local_wg_id = 0; @@ -397,6 +403,10 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, uint32_t ttmp6 = 0; uint32_t ttmp7 = ((wg_id_z & kGfx12Ttmp7ClusterGridDimensionMask) << 16) | (wg_id_y & kGfx12Ttmp7ClusterGridDimensionMask); + uint32_t ttmp8 = pkt.queue_packet_id & kGfx12Ttmp8QueuePacketIdMask; + ttmp8 |= wf_index_in_wg << kGfx12Ttmp8WaveIdInGroupShift; + if (pkt.grid_yz_valid) + ttmp8 |= 1u << kGfx12Ttmp8GridYzValidShift; uint32_t ttmp9 = grid_wg_id_x; if (properties.uses_cluster_ttmp_workgroup_ids) { const uint32_t cluster_size_x = nonzero_or_one(pkt.cluster_size_x); @@ -424,6 +434,7 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, } cu->write_sgpr(sbase + kGfx12Ttmp6, ttmp6); cu->write_sgpr(sbase + kGfx12Ttmp7, ttmp7); + cu->write_sgpr(sbase + kGfx12Ttmp8, ttmp8); cu->write_sgpr(sbase + kGfx12Ttmp9, ttmp9); } @@ -1286,7 +1297,8 @@ static const uint8_t *find_elf_base(const uint8_t *ptr, const uint8_t *limit) { } void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pkt, - const HwQueue &queue, uint64_t pkt_addr, HwQueueState &qs, + const HwQueue &queue, uint64_t pkt_addr, + uint32_t queue_packet_id, HwQueueState &qs, ClusterDispatchShape cluster_shape) { bool host_accessible = queue.host_accessible; using namespace rocr::llvm::amdhsa; @@ -1320,6 +1332,7 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.dispatch_id = next_dispatch_id_++; dp.profiling_start_timestamp = hsa_system_timestamp(); dp.queue_id = queue.queue_id; + dp.queue_packet_id = queue_packet_id; dp.process_id = queue.process_id; dp.kernel_entry_pc = entry_pc; dp.total_wgs = total_wgs; @@ -1386,6 +1399,7 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.grid_wgs_x = (num_dims <= 1) ? total_wgs : grid_wgs_x; dp.grid_wgs_y = (num_dims >= 2) ? grid_wgs_y : 1; dp.grid_wgs_z = (num_dims >= 3) ? grid_wgs_z : 1; + dp.grid_yz_valid = num_dims >= 2; dp.cluster_size_x = nonzero_or_one(cluster_shape.size_x); dp.cluster_size_y = nonzero_or_one(cluster_shape.size_y); dp.cluster_size_z = nonzero_or_one(cluster_shape.size_z); @@ -1612,7 +1626,7 @@ void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdoj } if (pkt_type == HSA_PACKET_TYPE_KERNEL_DISPATCH) { - process_aql_packet(pkt, queue, pkt_addr, qs); + process_aql_packet(pkt, queue, pkt_addr, slot, qs); } else if (pkt_type == HSA_PACKET_TYPE_BARRIER_AND || pkt_type == HSA_PACKET_TYPE_BARRIER_OR) { constexpr uint32_t DEP_OFF = 8; constexpr uint32_t SIG_OFF = 56; @@ -1772,7 +1786,7 @@ void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdoj cluster_shape.size_x = ext.cluster_size_x; cluster_shape.size_y = ext.cluster_size_y; cluster_shape.size_z = ext.cluster_size_z; - process_aql_packet(dispatch, queue, pkt_addr, qs, cluster_shape); + process_aql_packet(dispatch, queue, pkt_addr, slot, qs, cluster_shape); } else if (ext.amd_format == kAmdAqlFormatPm4Ib) { constexpr uint32_t SIG_OFF = 56; const uint64_t sig = read_gpu_u64(pkt_addr + SIG_OFF, queue.process_id); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h index 5a34ea784ae5..75a87d76f166 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h @@ -241,7 +241,7 @@ class CommandProcessor : public simdojo::Component { /// @brief Parse an AQL dispatch packet, read its kernel descriptor, and create a DispatchEntry. void process_aql_packet(const hsa_kernel_dispatch_packet_t &pkt, const HwQueue &queue, - uint64_t pkt_addr, HwQueueState &qs, + uint64_t pkt_addr, uint32_t queue_packet_id, HwQueueState &qs, ClusterDispatchShape cluster_shape = {}); rocr::llvm::amdhsa::kernel_descriptor_t diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h index 8f9f829bc6cc..d020870b9754 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h @@ -44,6 +44,7 @@ struct ClusterDispatchShape { struct DispatchEntry { uint32_t dispatch_id = 0; uint32_t queue_id = 0; + uint32_t queue_packet_id = 0; uint32_t process_id = 0; uint64_t kernel_entry_pc = 0; @@ -66,6 +67,7 @@ struct DispatchEntry { uint32_t grid_wgs_x = 0; uint32_t grid_wgs_y = 1; uint32_t grid_wgs_z = 1; + bool grid_yz_valid = false; uint32_t cluster_count_x = 0; uint32_t cluster_count_y = 0; uint32_t cluster_count_z = 0; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h index 18cd06511316..576f42ff8e6e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h @@ -245,14 +245,28 @@ class Wavefront : public ThreadContext { /// @brief Set the raw architectural EXEC register pair. void set_exec_raw(uint64_t val) { exec_ = val; } - /// @brief Return the VCC scalar register pair. - /// @returns Raw VCC register value. + /// @brief Return the raw architectural VCC register pair. + /// @returns Raw VCC register value, including non-lane bits in wave32 mode. uint64_t vcc() const { return vcc_; } - /// @brief Set the VCC scalar register pair. - /// @param val New VCC value. + /// @brief Return the active-lane portion of the VCC register pair. + /// @returns VCC mask with non-lane bits cleared. + uint64_t vcc_mask() const { return vcc_ & lane_mask(); } + + /// @brief Set the raw architectural VCC register pair. + /// @param val New raw VCC value. + /// + /// Scalar operand writes may update either half directly. Vector predicate + /// and carry producers must use set_vcc_mask() to preserve wave32 VCC_HI. void set_vcc(uint64_t val) { vcc_ = val; } + /// @brief Set the active-lane portion of the VCC register pair. + /// @param val New lane-mask value. + /// + /// Wave32 leaves VCC_HI available as scalar scratch. Vector instructions + /// that produce a predicate or carry mask must preserve those non-lane bits. + void set_vcc_mask(uint64_t val) { vcc_ = (vcc_ & ~lane_mask()) | (val & lane_mask()); } + /// @brief Return the M0 special register. /// @returns M0 register value. uint32_t m0() const { return m0_; } diff --git a/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp b/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp index 1d53ac4a1a8b..c9abd168147f 100644 --- a/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp @@ -334,6 +334,44 @@ TEST(Gfx1250SimulationTest, TtmpWorkgroupIdsUseGridCoordinatesFor2DDispatch) { // TTMP9 (s117) holds grid_wg_id_x; TTMP7 (s115) packs wg_id_y/z. EXPECT_EQ(target->sgpr(117), 1u); EXPECT_EQ(target->sgpr(115), 1u); + EXPECT_NE(target->sgpr(116) & (1u << 30), 0u); +} + +TEST(Gfx1250SimulationTest, Ttmp8EncodesWaveIdWithinWorkgroup) { + Gfx1250Sim sim; + const uint32_t code[] = {S_ENDPGM_GFX12}; + uint64_t kernel_object = sim.write_kernel(0x10000, code, std::size(code)); + + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch(kernel_object, 64, 64); + step_until_xcd_halted(sim); + + ASSERT_EQ(sim.snapshot->snapshots().size(), 2u); + std::vector ttmp8_values; + for (const auto &wf : sim.snapshot->snapshots()) + ttmp8_values.push_back(wf.sgpr(116)); + std::sort(ttmp8_values.begin(), ttmp8_values.end()); + EXPECT_EQ(ttmp8_values, (std::vector{0, 1u << 25})); +} + +TEST(Gfx1250SimulationTest, Ttmp8EncodesQueuePacketId) { + Gfx1250Sim sim; + const uint32_t code[] = {S_ENDPGM_GFX12}; + uint64_t kernel_object = sim.write_kernel(0x10000, code, std::size(code)); + + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch(kernel_object, 32, 32); + queue.dispatch(kernel_object, 32, 32); + step_until_xcd_halted(sim); + + ASSERT_EQ(sim.snapshot->snapshots().size(), 2u); + std::array queue_packet_ids{}; + for (const auto &wf : sim.snapshot->snapshots()) { + ASSERT_GE(wf.dispatch_id, 1u); + ASSERT_LE(wf.dispatch_id, 2u); + queue_packet_ids[wf.dispatch_id - 1] = wf.sgpr(116) & 0x1FFFFFFu; + } + EXPECT_EQ(queue_packet_ids, (std::array{0, 1})); } TEST(Gfx1250SimulationTest, GlobalStoreWritesVisibleMemory) { diff --git a/emulation/rocjitsu/tests/cdna5_execution_test.cpp b/emulation/rocjitsu/tests/cdna5_execution_test.cpp index 32f5fc209c3b..d53db192eac7 100644 --- a/emulation/rocjitsu/tests/cdna5_execution_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_execution_test.cpp @@ -24,6 +24,120 @@ TEST(Gfx1250ExecutionTest, TargetProvidesImmutableExecutionBackend) { EXPECT_TRUE(cdna5::Operand::full_execution_backend_complete()); } +TEST(Gfx1250ExecutionTest, ScalarMovesTreatS102AndS103AsOrdinarySgprs) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + + constexpr uint64_t kScratchBase = 0xabcde00012345000ull; + wf->set_scratch_base(kScratchBase); + write_wave_sgpr(*cu, *wf, 90, 0x11223344u); + write_wave_sgpr(*cu, *wf, 91, 0x55667788u); + write_wave_sgpr(*cu, *wf, 92, 0xaabbccddu); + write_wave_sgpr(*cu, *wf, 93, 0xeeff0011u); + write_wave_sgpr(*cu, *wf, 102, 0); + write_wave_sgpr(*cu, *wf, 103, 0); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + + constexpr std::array kMove64 = { + 0xbee6015au, // s_mov_b64 s[102:103], s[90:91] + 0, + 0, + }; + std::unique_ptr move64(decoder->decode(kMove64.data())); + ASSERT_NE(move64, nullptr); + EXPECT_EQ(move64->mnemonic(), "s_mov_b64"); + EXPECT_EQ(move64->size(), 4); + move64->execute(*move64, wf); + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 102), 0x11223344u); + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 103), 0x55667788u); + EXPECT_EQ(wf->scratch_base(), kScratchBase); + + constexpr std::array kWriteS102 = { + 0xbee6005cu, // s_mov_b32 s102, s92 + 0, + 0, + }; + constexpr std::array kWriteS103 = { + 0xbee7005du, // s_mov_b32 s103, s93 + 0, + 0, + }; + for (const auto *words : {kWriteS102.data(), kWriteS103.data()}) { + std::unique_ptr move32(decoder->decode(words)); + ASSERT_NE(move32, nullptr); + EXPECT_EQ(move32->mnemonic(), "s_mov_b32"); + EXPECT_EQ(move32->size(), 4); + move32->execute(*move32, wf); + } + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 102), 0xaabbccddu); + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 103), 0xeeff0011u); + + constexpr std::array kReadS102 = { + 0xbed20066u, // s_mov_b32 s82, s102 + 0, + 0, + }; + constexpr std::array kReadS103 = { + 0xbed30067u, // s_mov_b32 s83, s103 + 0, + 0, + }; + for (const auto *words : {kReadS102.data(), kReadS103.data()}) { + std::unique_ptr move32(decoder->decode(words)); + ASSERT_NE(move32, nullptr); + EXPECT_EQ(move32->mnemonic(), "s_mov_b32"); + EXPECT_EQ(move32->size(), 4); + move32->execute(*move32, wf); + } + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 82), 0xaabbccddu); + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 83), 0xeeff0011u); + + constexpr std::array kReadS102S103 = { + 0xbed00166u, // s_mov_b64 s[80:81], s[102:103] + 0, + 0, + }; + std::unique_ptr read64(decoder->decode(kReadS102S103.data())); + ASSERT_NE(read64, nullptr); + EXPECT_EQ(read64->mnemonic(), "s_mov_b64"); + EXPECT_EQ(read64->size(), 4); + read64->execute(*read64, wf); + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 80), 0xaabbccddu); + EXPECT_EQ(read_wave_sgpr(*cu, *wf, 81), 0xeeff0011u); + EXPECT_EQ(wf->scratch_base(), kScratchBase); +} + +TEST(Gfx1250ExecutionTest, Wave32VectorComparePreservesVccHiScratch) { + ForceScalarGuard force_scalar_guard; + for (const bool force_scalar : {false, true}) { + SCOPED_TRACE(force_scalar ? "scalar" : "simd"); + util::set_force_scalar_for_testing(force_scalar); + + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_exec(0x3u); + wf->set_vcc(0x000001c0ffffffffull); + write_wave_sgpr(*cu, *wf, 28, 7u); + const uint32_t vgpr_base = wf->vgpr_alloc().base; + cu->write_vgpr(vgpr_base + 18, 0, 6u); + cu->write_vgpr(vgpr_base + 18, 1, 8u); + + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + constexpr auto kCompare = cdna5::build_vopc(cdna5::kVCmpGtI32Vopc, {.src0 = 28, .vsrc1 = 18}); + std::unique_ptr decoded(decoder->decode(kCompare.data())); + ASSERT_NE(decoded, nullptr); + EXPECT_EQ(decoded->mnemonic(), "v_cmp_gt_i32_e32"); + decoded->execute(*decoded, wf); + EXPECT_EQ(wf->vcc(), 0x000001c000000001ull); + } +} + TEST(Gfx1250ExecutionTest, DivScaleWritesExplicitSdstMask) { Gfx1250Sim sim; auto *cu = sim.cu(); From 3f922ad5f2ece8759d045a2a3bf0a74e2f569964 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 18 Aug 2026 20:37:32 -0400 Subject: [PATCH 16/27] [rocjitsu] Model gfx1250 barrier synchronization (#10346) Implement the CDNA5 split-barrier model used by compiler-generated gfx1250 kernels. Derive the signal, wait, init, join, leave, and state operations for the gfx1250 profile while retaining the RDNA4 behavior inherited by other targets. Track independent completion state for named, workgroup, trap, cluster, and cluster-trap barriers. Carry workgroup counters in the compute unit and coordinate per-workgroup cluster arrivals across compute units under a dedicated execution-state lock. Shrink membership when waves or clustered workgroups terminate, honor privilege and single-wave rules, and notify execution plugins outside internal locks with the complete synchronized domain. Decode named-barrier allocation from the AQL kernel descriptor, use the generated M0 operand selector, and align LDS tensor-barrier phase expectations with the architectural layout. Add instruction and dispatch coverage for named membership, negative barrier IDs, independent domains, early termination, cross-CU cluster synchronization, packed state, and barrier transitions. (cherry picked from commit 7f71be9f32e5ba18f45bbe1935068a5a07cf6e16) --- .../lib/python/amdisa/codegen/_generator.py | 77 +++- .../rocjitsu/lib/python/amdisa/isa_profile.py | 19 + .../rocjitsu/lib/python/amdisa/semantics.py | 21 +- .../tests/test_generator_profile_gates.py | 20 +- .../python/amdisa/tests/test_sema_derive.py | 31 +- .../arch/amdgpu/generated/cdna5/sop1_exec.cpp | 45 ++- .../arch/amdgpu/generated/cdna5/sopp_exec.cpp | 5 +- .../arch/amdgpu/generated/rdna4/sop1_exec.cpp | 8 +- .../arch/amdgpu/generated/rdna4/sopp_exec.cpp | 2 +- .../amdgpu/generated/shared/execute_shared.h | 14 - .../rocjitsu/vm/amdgpu/command_processor.cpp | 254 ++++++++++--- .../rocjitsu/vm/amdgpu/command_processor.h | 25 ++ .../src/rocjitsu/vm/amdgpu/compute_unit.cpp | 240 +++++++++++- .../src/rocjitsu/vm/amdgpu/compute_unit.h | 51 ++- .../src/rocjitsu/vm/amdgpu/dispatch_entry.h | 1 + .../src/rocjitsu/vm/amdgpu/lds_barrier_cell.h | 15 +- .../lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h | 3 +- .../src/rocjitsu/vm/amdgpu/wavefront.cpp | 18 + .../src/rocjitsu/vm/amdgpu/wavefront.h | 30 +- .../rocjitsu/vm/plugins/execution_plugin.h | 2 +- .../rocjitsu/tests/cdna5_instruction_test.cpp | 357 ++++++++++++++++++ .../rocjitsu/tests/cdna5_sim_test_common.h | 5 +- .../rocjitsu/tests/cdna5_tensor_dma_test.cpp | 49 +-- 23 files changed, 1146 insertions(+), 146 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 1c94bb8f976b..0b1c4fe3467f 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -4946,6 +4946,16 @@ def _semantic_reg_class(opnd: Operand) -> RegClass: L.append(' wf.set_state(amdgpu::WfState::BARRIER);') return '\n'.join(L) + if cls == 'scalar_barrier_wait': + L.append( + f' int32_t barrier_id = static_cast({src_ops[0]}.encoding_value_);' + ) + L.append(' wf.barrier_wait(barrier_id);') + return '\n'.join(L) + + if cls == 'scalar_barrier_leave': + return ' wf.write_scc(wf.barrier_leave());' + if cls == 'branch': L.append( f' int16_t offset = static_cast({src_ops[0]}.encoding_value_);' @@ -5094,7 +5104,69 @@ def _semantic_reg_class(opnd: Operand) -> RegClass: return '\n'.join(L) if cls == 'scalar_barrier_state': - L.append(f' amdgpu::RegisterAccess(wf).write_scalar({dst_ops[0]}, 0);') + L.append( + f' uint32_t source = amdgpu::RegisterAccess(wf).read_scalar({src_ops[0]});' + ) + L.append( + f' bool source_is_m0 = ' + f'{src_ops[0]}.encoding_value() == ' + f'OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0;' + ) + L.append( + ' int32_t barrier_id = source_is_m0 ? static_cast(source & 0x1fu) ' + ': static_cast(source);' + ) + L.append( + f' amdgpu::RegisterAccess(wf).write_scalar({dst_ops[0]}, wf.barrier_state(barrier_id));' + ) + return '\n'.join(L) + + if cls in ( + 'scalar_barrier_signal', + 'scalar_barrier_init', + 'scalar_barrier_join', + ): + L.append( + f' uint32_t source = amdgpu::RegisterAccess(wf).read_scalar({src_ops[0]});' + ) + L.append( + f' bool source_is_m0 = ' + f'{src_ops[0]}.encoding_value() == ' + f'OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0;' + ) + L.append( + ' int32_t barrier_id = source_is_m0 ? static_cast(source & 0x1fu) ' + ': static_cast(source);' + ) + if cls == 'scalar_barrier_signal': + L.append( + ' uint32_t member_count = source_is_m0 ? ((source >> 16) & 0x7fu) : 0;' + ) + if op == 'signal_isfirst': + L.append( + ' bool barrier_valid = (wf.barrier_state(barrier_id) & 1u) != 0;' + ) + L.append( + ' bool is_first = wf.barrier_signal(barrier_id, member_count);' + ) + L.append(' if (barrier_valid) wf.write_scc(is_first);') + else: + L.append(' wf.barrier_signal(barrier_id, member_count);') + elif cls == 'scalar_barrier_init': + has_implicit_m0 = any( + operand.name == 'm0' and operand.is_input + for operand in inst.operands + ) + member_source = ( + 'wf.m0()' + if has_implicit_m0 + else f'amdgpu::RegisterAccess(wf).read_scalar({src_ops[0]})' + ) + L.append(f' uint32_t member_source = {member_source};') + L.append(' uint32_t member_count = (member_source >> 16) & 0x7fu;') + L.append(' wf.barrier_init(barrier_id, member_count);') + else: + L.append(' wf.barrier_join(barrier_id);') return '\n'.join(L) if cls == 'scalar_movrel': @@ -12057,7 +12129,8 @@ def _inert_guard(ret_expr: str = '', cond: str = _inert_cond) -> str: resolve_code = cgen.Line( 'namespace {\n' '\n' - f'constexpr int kM0EncodingValue = {125 if scalar_null_precedes_m0 else 124};\n' + f'constexpr int kM0EncodingValue = ' + f'{125 if scalar_null_precedes_m0 else 124};\n' '\n' + _is_vgpr_only_body + '\n\n' diff --git a/emulation/rocjitsu/lib/python/amdisa/isa_profile.py b/emulation/rocjitsu/lib/python/amdisa/isa_profile.py index ab1d19229009..a1c631e3ad18 100644 --- a/emulation/rocjitsu/lib/python/amdisa/isa_profile.py +++ b/emulation/rocjitsu/lib/python/amdisa/isa_profile.py @@ -1657,6 +1657,14 @@ def scalar_null_precedes_m0(self) -> bool: def uses_true16_vop3_opsel(self) -> bool: return True + @property + def semantic_overrides(self) -> dict[str, tuple[str, ...]]: + return { + 'S_BARRIER_SIGNAL': ('true_nop', '', ''), + 'S_BARRIER_SIGNAL_ISFIRST': ('true_nop', '', ''), + 'S_BARRIER_WAIT': ('barrier', '', ''), + } + def mnemonic_rule(self, enc_name: str) -> MnemonicRule: """RDNA4 mnemonic rules. @@ -1728,6 +1736,17 @@ def generated_dir_name(self) -> str | None: def cpp_namespace(self) -> str | None: return 'cdna5' + @property + def semantic_overrides(self) -> dict[str, tuple[str, ...]]: + overrides = dict(super().semantic_overrides) + for mnemonic in ( + 'S_BARRIER_SIGNAL', + 'S_BARRIER_SIGNAL_ISFIRST', + 'S_BARRIER_WAIT', + ): + overrides.pop(mnemonic, None) + return overrides + @property def semantic_class_overrides(self) -> dict[str, str]: return { diff --git a/emulation/rocjitsu/lib/python/amdisa/semantics.py b/emulation/rocjitsu/lib/python/amdisa/semantics.py index 88297bae001f..f20fb388b247 100644 --- a/emulation/rocjitsu/lib/python/amdisa/semantics.py +++ b/emulation/rocjitsu/lib/python/amdisa/semantics.py @@ -352,13 +352,12 @@ def _derive_sopp(name: str) -> InstructionSemantics | None: } if name in _SPLIT_WAIT: return InstructionSemantics(name, 'wait_counter', operation=name[2:].lower()) - # S_BARRIER_WAIT uses the existing whole-workgroup barrier model for the - # common split form where S_BARRIER_SIGNAL is immediately followed by - # S_BARRIER_WAIT. Arrival accounting and named-barrier ids are not modeled - # yet: signal stays a no-op, wait parks the wavefront, and CU release logic - # keys only on all non-halted sibling waves in the same workgroup. - if name in ('S_BARRIER', 'S_BARRIER_WAIT'): + if name == 'S_BARRIER': return InstructionSemantics(name, 'barrier') + if name == 'S_BARRIER_WAIT': + return InstructionSemantics(name, 'scalar_barrier_wait') + if name == 'S_BARRIER_LEAVE': + return InstructionSemantics(name, 'scalar_barrier_leave', sets_scc='nonzero') if name == 'S_SET_GPR_IDX_OFF': return InstructionSemantics(name, 'gpr_idx', operation='off') @@ -419,11 +418,11 @@ def _derive_sopp(name: str) -> InstructionSemantics | None: 'S_MOVRELSD_2': ('scalar_movrel', 'srcdst2'), 'S_MOVRELSD_2_B32': ('scalar_movrel', 'srcdst2'), 'S_SENDMSG_RTN': ('scalar_sendmsg_rtn', None), - 'S_BARRIER_SIGNAL': ('true_nop', None), - 'S_BARRIER_SIGNAL_ISFIRST': ('true_nop', None), + 'S_BARRIER_SIGNAL_ISFIRST': ('scalar_barrier_signal', 'signal_isfirst'), + 'S_BARRIER_SIGNAL': ('scalar_barrier_signal', 'signal'), 'S_GET_BARRIER_STATE': ('scalar_barrier_state', None, 'b32'), - 'S_BARRIER_INIT': ('true_nop', None), - 'S_BARRIER_JOIN': ('true_nop', None), + 'S_BARRIER_INIT': ('scalar_barrier_init', None), + 'S_BARRIER_JOIN': ('scalar_barrier_join', None), 'S_WAKEUP_BARRIER': ('true_nop', None), 'S_ALLOC_VGPR': ('true_nop', None), 'S_SLEEP_VAR': ('true_nop', None), @@ -523,6 +522,8 @@ def _derive_sop1(name: str) -> InstructionSemantics | None: scc = 'none' else: scc = 'nonzero' + elif cls == 'scalar_barrier_signal' and op == 'signal_isfirst': + scc = 'nonzero' return InstructionSemantics( name, cls, operation=op, data_type=dtype, sets_scc=scc ) diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index 2272a4a06794..73a04f802a48 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -412,14 +412,9 @@ def test_generated_scc_accesses_match_mrisa(isa_name, profile_type): } assert set(mrisa_scc_accesses) == active_keys mismatches = [] - excluded = { - 'S_ALLOC_VGPR', - 'S_BARRIER_LEAVE', - 'S_BARRIER_SIGNAL_ISFIRST', - } expected_exclusions = { 'rdna4': {'S_ALLOC_VGPR', 'S_BARRIER_SIGNAL_ISFIRST'}, - 'gfx1250': excluded, + 'gfx1250': {'S_ALLOC_VGPR'}, } checked_exclusions = set() checked = 0 @@ -434,7 +429,7 @@ def test_generated_scc_accesses_match_mrisa(isa_name, profile_type): mrisa_reads_scc, mrisa_writes_scc = mrisa_scc_accesses[key] sem = semantics.instructions.get(inst.name) - if inst.name in excluded: + if inst.name in expected_exclusions.get(isa_name, set()): assert ( mrisa_writes_scc ), f'{isa_name}: stale SCC exclusion for {inst.name}' @@ -2243,6 +2238,17 @@ def test_generated_operand_validates_barrier_id_selectors( assert '"s_get_barrier_state", {0xBE805080U' in gfx1250_test_encodings +def test_gfx1250_barrier_init_reads_member_count_from_implicit_m0( + gfx1250_generated_root: Path, +): + sop1_exec = (gfx1250_generated_root / 'sop1_exec.cpp').read_text() + body = _generated_method_body(sop1_exec, 'SBarrierInitSop1', 'SBarrierJoinSop1') + + assert 'read_scalar(ssrc0)' in body + assert 'uint32_t member_source = wf.m0();' in body + assert 'member_count = (member_source >> 16) & 0x7fu' in body + + def test_generated_operand_validates_direct_selector_namespaces( amdgpu_generated_root: Path, gfx1250_generated_root: Path ): diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py index 59a471ae390a..a2f6e762e368 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py @@ -720,10 +720,10 @@ def test_scalar_movrel_derives_indexed_register_semantics( class TestDeriveScalarSplitBarrier: - def test_barrier_wait_derives_current_workgroup_barrier_model(self): + def test_barrier_wait_derives_barrier_wait_model(self): sem = derive_semantics('S_BARRIER_WAIT', 'ENC_SOPP') assert sem is not None - assert sem.semantic_class == 'barrier' + assert sem.semantic_class == 'scalar_barrier_wait' assert sem.sets_scc is None def test_get_barrier_state_derives_idle_state_read(self): @@ -734,19 +734,30 @@ def test_get_barrier_state_derives_idle_state_read(self): assert sem.sets_scc is None @pytest.mark.parametrize( - 'name', + ('name', 'semantic_class', 'operation'), [ - 'S_BARRIER_SIGNAL', - 'S_BARRIER_SIGNAL_ISFIRST', - 'S_BARRIER_INIT', - 'S_BARRIER_JOIN', - 'S_WAKEUP_BARRIER', + ('S_BARRIER_SIGNAL', 'scalar_barrier_signal', 'signal'), + ('S_BARRIER_SIGNAL_ISFIRST', 'scalar_barrier_signal', 'signal_isfirst'), + ('S_BARRIER_INIT', 'scalar_barrier_init', None), + ('S_BARRIER_JOIN', 'scalar_barrier_join', None), + ('S_WAKEUP_BARRIER', 'true_nop', None), ], ) - def test_named_barrier_ops_derive_current_noop_model(self, name): + def test_named_barrier_ops_derive_execution_model( + self, name, semantic_class, operation + ): sem = derive_semantics(name, 'ENC_SOP1') assert sem is not None - assert sem.semantic_class == 'true_nop' + assert sem.semantic_class == semantic_class + assert sem.operation == operation + if name == 'S_BARRIER_SIGNAL_ISFIRST': + assert sem.sets_scc == 'nonzero' + + def test_barrier_leave_derives_execution_model(self): + sem = derive_semantics('S_BARRIER_LEAVE', 'ENC_SOPP') + assert sem is not None + assert sem.semantic_class == 'scalar_barrier_leave' + assert sem.sets_scc == 'nonzero' class TestDeriveVectorUnary: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp index fd3b843fac31..67d7c4f7c52b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp @@ -324,21 +324,52 @@ void SSendmsgRtnB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SBarrierSignalSop1::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::execute_s_barrier_signal_sop1(*this, wf); + uint32_t source = amdgpu::RegisterAccess(wf).read_scalar(ssrc0); + bool source_is_m0 = ssrc0.encoding_value() == OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0; + int32_t barrier_id = + source_is_m0 ? static_cast(source & 0x1fu) : static_cast(source); + uint32_t member_count = source_is_m0 ? ((source >> 16) & 0x7fu) : 0; + wf.barrier_signal(barrier_id, member_count); } void SBarrierSignalIsfirstSop1::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::execute_s_barrier_signal_isfirst_sop1(*this, wf); + uint32_t source = amdgpu::RegisterAccess(wf).read_scalar(ssrc0); + bool source_is_m0 = ssrc0.encoding_value() == OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0; + int32_t barrier_id = + source_is_m0 ? static_cast(source & 0x1fu) : static_cast(source); + uint32_t member_count = source_is_m0 ? ((source >> 16) & 0x7fu) : 0; + bool barrier_valid = (wf.barrier_state(barrier_id) & 1u) != 0; + bool is_first = wf.barrier_signal(barrier_id, member_count); + if (barrier_valid) + wf.write_scc(is_first); } void SGetBarrierStateSop1::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::RegisterAccess(wf).write_scalar(sdst, 0); + uint32_t source = amdgpu::RegisterAccess(wf).read_scalar(ssrc0); + bool source_is_m0 = ssrc0.encoding_value() == OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0; + int32_t barrier_id = + source_is_m0 ? static_cast(source & 0x1fu) : static_cast(source); + amdgpu::RegisterAccess(wf).write_scalar(sdst, wf.barrier_state(barrier_id)); +} + +void SBarrierInitSop1::execute_impl(amdgpu::Wavefront &wf) { + uint32_t source = amdgpu::RegisterAccess(wf).read_scalar(ssrc0); + bool source_is_m0 = ssrc0.encoding_value() == OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0; + int32_t barrier_id = + source_is_m0 ? static_cast(source & 0x1fu) : static_cast(source); + uint32_t member_source = wf.m0(); + uint32_t member_count = (member_source >> 16) & 0x7fu; + wf.barrier_init(barrier_id, member_count); +} + +void SBarrierJoinSop1::execute_impl(amdgpu::Wavefront &wf) { + uint32_t source = amdgpu::RegisterAccess(wf).read_scalar(ssrc0); + bool source_is_m0 = ssrc0.encoding_value() == OpSelSsrcBarrierId::OPR_SSRC_BARRIER_ID_M0; + int32_t barrier_id = + source_is_m0 ? static_cast(source & 0x1fu) : static_cast(source); + wf.barrier_join(barrier_id); } -void SBarrierInitSop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; } - -void SBarrierJoinSop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; } - void SAllocVgprSop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_alloc_vgpr_sop1(*this, wf); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp_exec.cpp index 1263c6e11daf..e1aff12664e5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp_exec.cpp @@ -57,10 +57,11 @@ void SDenormModeSopp::execute_impl(amdgpu::Wavefront &wf) { } void SBarrierWaitSopp::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::execute_s_barrier_wait_sopp(*this, wf); + int32_t barrier_id = static_cast(simm16.encoding_value_); + wf.barrier_wait(barrier_id); } -void SBarrierLeaveSopp::execute_impl(amdgpu::Wavefront &wf) { (void)wf; } +void SBarrierLeaveSopp::execute_impl(amdgpu::Wavefront &wf) { wf.write_scc(wf.barrier_leave()); } void SCodeEndSopp::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_code_end_sopp(*this, wf); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp index 98212f3ff708..680c76f2bb6b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp @@ -313,13 +313,9 @@ void SSendmsgRtnB64Sop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_sendmsg_rtn_b64_sop1(*this, wf); } -void SBarrierSignalSop1::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::execute_s_barrier_signal_sop1(*this, wf); -} +void SBarrierSignalSop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; } -void SBarrierSignalIsfirstSop1::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::execute_s_barrier_signal_isfirst_sop1(*this, wf); -} +void SBarrierSignalIsfirstSop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; } void SAllocVgprSop1::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_s_alloc_vgpr_sop1(*this, wf); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp_exec.cpp index 317a27b7d1b1..d02416204288 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp_exec.cpp @@ -67,7 +67,7 @@ void SDenormModeSopp::execute_impl(amdgpu::Wavefront &wf) { } void SBarrierWaitSopp::execute_impl(amdgpu::Wavefront &wf) { - amdgpu::execute_s_barrier_wait_sopp(*this, wf); + wf.set_state(amdgpu::WfState::BARRIER); } void SCodeEndSopp::execute_impl(amdgpu::Wavefront &wf) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h index 7c563c3fffcb..0514779bc56a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h @@ -712,20 +712,6 @@ inline void execute_s_barrier_sopp([[maybe_unused]] Inst &inst, [[maybe_unused]] wf.set_state(amdgpu::WfState::BARRIER); } -template -inline void execute_s_barrier_signal_sop1([[maybe_unused]] Inst &inst, - [[maybe_unused]] Wavefront &wf) {} - -template -inline void execute_s_barrier_signal_isfirst_sop1([[maybe_unused]] Inst &inst, - [[maybe_unused]] Wavefront &wf) {} - -template -inline void execute_s_barrier_wait_sopp([[maybe_unused]] Inst &inst, - [[maybe_unused]] Wavefront &wf) { - wf.set_state(amdgpu::WfState::BARRIER); -} - template inline void execute_s_bcnt0_i32_b32_sop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp index 23d5ce0ed981..b8bbfaf39ef2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp @@ -866,7 +866,7 @@ void CommandProcessor::register_cluster_workgroup(const DispatchEntry &entry, ui uint32_t lds_base) { if (!entry.has_workgroup_clusters()) return; - std::lock_guard lock(hw_queue_mutex_); + std::lock_guard lock(cluster_barrier_mutex_); uint32_t cluster_base_wg_id = entry.cluster_base_local_wg_id(local_wg_id) + entry.workgroup_id_offset; uint64_t cluster_key = wg_key(entry.dispatch_id, cluster_base_wg_id); @@ -883,65 +883,218 @@ void CommandProcessor::register_cluster_workgroup(const DispatchEntry &entry, ui placement.peer_wg_ids.push_back(peer_local_wg_id + entry.workgroup_id_offset); } cluster_wg_placements_[wg_key(entry.dispatch_id, global_wg_id)] = std::move(placement); + auto &barriers = cluster_barriers_[cluster_key]; + if (barriers.expected_member_count == 0) { + barriers.expected_member_count = entry.cluster_size(); + barriers.member_count = entry.cluster_size(); + } + barriers.registered_workgroups.insert(global_wg_id); } -void CommandProcessor::mark_cluster_workgroup_complete(uint32_t dispatch_id, uint32_t wg_id) { - auto it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); - if (it == cluster_wg_placements_.end()) - return; +bool CommandProcessor::find_valid_cluster_barrier_locked(const Wavefront &wf, int32_t barrier_id, + ClusterWorkgroupPlacement *&placement, + ClusterBarrierState *&barriers) { + if (barrier_id != kClusterBarrierId && barrier_id != kClusterTrapBarrierId) + return false; + auto placement_it = cluster_wg_placements_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + if (placement_it == cluster_wg_placements_.end()) + return false; + auto barriers_it = cluster_barriers_.find(placement_it->second.cluster_key); + if (barriers_it == cluster_barriers_.end() || barriers_it->second.member_count == 0 || + barriers_it->second.registered_workgroups.size() != barriers_it->second.expected_member_count) + return false; + placement = &placement_it->second; + barriers = &barriers_it->second; + return true; +} - it->second.completed = true; - uint64_t cluster_key = it->second.cluster_key; - auto peer_wg_ids = it->second.peer_wg_ids; - for (uint32_t peer_wg_id : peer_wg_ids) { - auto peer_it = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); - if (peer_it == cluster_wg_placements_.end() || !peer_it->second.completed) +bool CommandProcessor::find_valid_cluster_barrier_locked( + const Wavefront &wf, int32_t barrier_id, const ClusterWorkgroupPlacement *&placement, + const ClusterBarrierState *&barriers) const { + if (barrier_id != kClusterBarrierId && barrier_id != kClusterTrapBarrierId) + return false; + auto placement_it = cluster_wg_placements_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + if (placement_it == cluster_wg_placements_.end()) + return false; + auto barriers_it = cluster_barriers_.find(placement_it->second.cluster_key); + if (barriers_it == cluster_barriers_.end() || barriers_it->second.member_count == 0 || + barriers_it->second.registered_workgroups.size() != barriers_it->second.expected_member_count) + return false; + placement = &placement_it->second; + barriers = &barriers_it->second; + return true; +} + +bool CommandProcessor::cluster_barrier_valid(const Wavefront &wf, int32_t barrier_id) const { + std::lock_guard lock(cluster_barrier_mutex_); + const ClusterWorkgroupPlacement *placement = nullptr; + const ClusterBarrierState *barriers = nullptr; + return find_valid_cluster_barrier_locked(wf, barrier_id, placement, barriers); +} + +uint32_t CommandProcessor::cluster_barrier_state(const Wavefront &wf, int32_t barrier_id, + uint32_t allocation_blocks) const { + std::lock_guard lock(cluster_barrier_mutex_); + const ClusterWorkgroupPlacement *placement = nullptr; + const ClusterBarrierState *barriers = nullptr; + if (!find_valid_cluster_barrier_locked(wf, barrier_id, placement, barriers)) + return 0; + const uint32_t index = static_cast(-barrier_id - kClusterBarrierBit); + return 1u | ((barriers->member_count & 0x7fu) << 4) | + ((barriers->signaled_workgroups[index].size() & 0x7fu) << 16) | + ((allocation_blocks & 0x7u) << 24); +} + +bool CommandProcessor::cluster_barrier_signal(Wavefront &wf, int32_t barrier_id) { + bool is_first = false; + std::vector> peers; + const uint8_t completion_bit = static_cast(-barrier_id); + { + std::lock_guard lock(cluster_barrier_mutex_); + ClusterWorkgroupPlacement *placement = nullptr; + ClusterBarrierState *barriers = nullptr; + if (!find_valid_cluster_barrier_locked(wf, barrier_id, placement, barriers)) + return false; + + const uint32_t index = static_cast(completion_bit - kClusterBarrierBit); + auto [_, inserted] = barriers->signaled_workgroups[index].insert(wf.wg_id()); + if (!inserted) + return false; + is_first = barriers->signaled_workgroups[index].size() == 1; + if (barriers->signaled_workgroups[index].size() < barriers->member_count) + return is_first; + + barriers->signaled_workgroups[index].clear(); + peers.reserve(placement->peer_wg_ids.size()); + for (uint32_t peer_wg_id : placement->peer_wg_ids) { + auto peer = cluster_wg_placements_.find(wg_key(wf.dispatch_id(), peer_wg_id)); + if (peer != cluster_wg_placements_.end() && peer->second.cu) + peers.emplace_back(peer->second.cu, peer_wg_id); + } + } + + std::vector members; + for (auto [cu, peer_wg_id] : peers) { + auto peer_members = cu->complete_barrier(wf.dispatch_id(), peer_wg_id, completion_bit); + members.insert(members.end(), peer_members.begin(), peer_members.end()); + } + if (!members.empty()) + plugin_group_->onAmdgpuBarrierResolved(std::span(members)); + return is_first; +} + +void CommandProcessor::mark_cluster_workgroup_complete(uint32_t dispatch_id, uint32_t wg_id) { + std::array>, 2> resolved_peers; + std::vector retired_cus; + uint64_t cluster_key = 0; + { + std::lock_guard lock(cluster_barrier_mutex_); + auto it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); + if (it == cluster_wg_placements_.end() || it->second.completed) return; + + it->second.completed = true; + cluster_key = it->second.cluster_key; + const auto peer_wg_ids = it->second.peer_wg_ids; + auto barrier_it = cluster_barriers_.find(cluster_key); + if (barrier_it != cluster_barriers_.end() && barrier_it->second.member_count != 0) { + auto &barriers = barrier_it->second; + --barriers.member_count; + for (uint32_t index = 0; index < barriers.signaled_workgroups.size(); ++index) { + barriers.signaled_workgroups[index].erase(wg_id); + if (barriers.member_count == 0 || + barriers.signaled_workgroups[index].size() < barriers.member_count) + continue; + barriers.signaled_workgroups[index].clear(); + for (uint32_t peer_wg_id : peer_wg_ids) { + auto peer = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); + if (peer != cluster_wg_placements_.end() && !peer->second.completed && peer->second.cu) + resolved_peers[index].emplace_back(peer->second.cu, peer_wg_id); + } + } + } + + const bool all_completed = std::ranges::all_of(peer_wg_ids, [&](uint32_t peer_wg_id) { + auto peer = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); + return peer != cluster_wg_placements_.end() && peer->second.completed; + }); + if (!all_completed) + cluster_key = 0; + else { + for (uint32_t peer_wg_id : peer_wg_ids) { + auto peer = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); + if (peer != cluster_wg_placements_.end() && peer->second.cu) + retired_cus.push_back(peer->second.cu); + cluster_wg_placements_.erase(wg_key(dispatch_id, peer_wg_id)); + } + cluster_barriers_.erase(cluster_key); + } } - for (uint32_t peer_wg_id : peer_wg_ids) { - auto peer_it = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); - if (peer_it != cluster_wg_placements_.end() && peer_it->second.cu) { - peer_it->second.cu->unpin_lds_for_cluster(cluster_key); - // The waves halted (and freed) before the pin was released, so reclaim each - // peer CU's LDS now that the whole cluster is done. - peer_it->second.cu->maybe_reset_lds_alloc(); + for (uint32_t index = 0; index < resolved_peers.size(); ++index) { + std::vector members; + const uint8_t completion_bit = static_cast(kClusterBarrierBit + index); + for (auto [cu, peer_wg_id] : resolved_peers[index]) { + auto peer_members = cu->complete_barrier(dispatch_id, peer_wg_id, completion_bit); + members.insert(members.end(), peer_members.begin(), peer_members.end()); + } + if (!members.empty()) + plugin_group_->onAmdgpuBarrierResolved(std::span(members)); + } + + if (cluster_key != 0) { + for (auto *cu : retired_cus) { + cu->unpin_lds_for_cluster(cluster_key); + // The waves halted before the pin was released, so reclaim LDS after + // every workgroup in the cluster has retired. + cu->maybe_reset_lds_alloc(); } } - for (uint32_t peer_wg_id : peer_wg_ids) - cluster_wg_placements_.erase(wg_key(dispatch_id, peer_wg_id)); } void CommandProcessor::erase_cluster_workgroup(uint32_t dispatch_id, uint32_t wg_id) { - std::lock_guard lock(hw_queue_mutex_); - auto it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); - if (it == cluster_wg_placements_.end()) - return; - if (it->second.cu) { - it->second.cu->unpin_lds_for_cluster(it->second.cluster_key); - it->second.cu->maybe_reset_lds_alloc(); + ComputeUnitCore *cu = nullptr; + uint64_t cluster_key = 0; + { + std::lock_guard lock(cluster_barrier_mutex_); + auto it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); + if (it == cluster_wg_placements_.end()) + return; + cu = it->second.cu; + cluster_key = it->second.cluster_key; + cluster_barriers_.erase(cluster_key); + cluster_wg_placements_.erase(it); + } + if (cu) { + cu->unpin_lds_for_cluster(cluster_key); + cu->maybe_reset_lds_alloc(); } - cluster_wg_placements_.erase(it); } void CommandProcessor::erase_cluster_workgroups(uint32_t dispatch_id) { - std::lock_guard lock(hw_queue_mutex_); - for (auto it = cluster_wg_placements_.begin(); it != cluster_wg_placements_.end();) { - if ((it->first >> 32) == dispatch_id) { - if (it->second.cu) { - it->second.cu->unpin_lds_for_cluster(it->second.cluster_key); - it->second.cu->maybe_reset_lds_alloc(); + std::vector> retired; + { + std::lock_guard lock(cluster_barrier_mutex_); + for (auto it = cluster_wg_placements_.begin(); it != cluster_wg_placements_.end();) { + if ((it->first >> 32) == dispatch_id) { + cluster_barriers_.erase(it->second.cluster_key); + if (it->second.cu) + retired.emplace_back(it->second.cu, it->second.cluster_key); + it = cluster_wg_placements_.erase(it); + } else { + ++it; } - it = cluster_wg_placements_.erase(it); - } else { - ++it; } } + for (auto [cu, cluster_key] : retired) { + cu->unpin_lds_for_cluster(cluster_key); + cu->maybe_reset_lds_alloc(); + } } std::vector CommandProcessor::cluster_lds_targets(uint32_t dispatch_id, uint32_t wg_id, uint32_t mcast_mask) { - std::lock_guard lock(hw_queue_mutex_); + std::lock_guard lock(cluster_barrier_mutex_); std::vector targets; auto src_it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); if (src_it == cluster_wg_placements_.end()) @@ -1067,7 +1220,8 @@ uint32_t CommandProcessor::dispatch_workgroups(DispatchEntry &entry) { } // All fallible per-wave work succeeded: commit WG bookkeeping and the cluster pin. - cu->begin_workgroup(entry.dispatch_id, global_wg_id, entry.wfs_per_workgroup); + cu->begin_workgroup(entry.dispatch_id, global_wg_id, entry.wfs_per_workgroup, + entry.num_named_barriers); register_cluster_workgroup(entry, local_wg_id, global_wg_id, cu, lds_base); plugin_group_->onAmdgpuWorkgroupDispatched(entry.dispatch_id, global_wg_id, @@ -1184,13 +1338,18 @@ uint32_t CommandProcessor::dispatch_workgroups(DispatchEntry &entry) { void CommandProcessor::notify_wg_complete(uint32_t dispatch_id, uint32_t wg_id) { util::Logger::cp( [&](auto &os) { os << std::format("WG_COMPLETE d={} wg={}", dispatch_id, wg_id); }); - std::lock_guard lock(hw_queue_mutex_); - for (auto *spi : spis_) - if (spi->release_wgp_workgroup(dispatch_id, wg_id)) - break; + { + std::lock_guard lock(hw_queue_mutex_); + for (auto *spi : spis_) + if (spi->release_wgp_workgroup(dispatch_id, wg_id)) + break; + } mark_cluster_workgroup_complete(dispatch_id, wg_id); - if (completion_) - completion_->notify_wg_complete(dispatch_id, wg_id, new_queue_states_); + { + std::lock_guard lock(hw_queue_mutex_); + if (completion_) + completion_->notify_wg_complete(dispatch_id, wg_id, new_queue_states_); + } } // INVARIANT: on_cu_idle() runs on the owning partition's engine thread — it is @@ -1347,6 +1506,11 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.kernarg_size = kd.kernarg_size; dp.num_user_sgprs = user_sgprs; dp.kernel_code_properties = kd.kernel_code_properties; + if (arch == ROCJITSU_CODE_ARCH_GFX1250) { + const uint32_t named_barrier_blocks = + AMDHSA_BITS_GET(kd.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT); + dp.num_named_barriers = std::min(named_barrier_blocks * 4u, ComputeUnitCore::kMaxNamedBarriers); + } dp.kernarg_preload = kd.kernarg_preload; dp.initial_mode_raw = initial_mode_from_compute_pgm_rsrc1(kd.compute_pgm_rsrc1, arch); dp.private_segment_fixed_size = std::max(kd.private_segment_fixed_size, pkt.private_segment_size); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h index 75a87d76f166..68b216910ffe 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h @@ -32,6 +32,7 @@ #include "simdojo/sim/component.h" #include +#include #include #include #include @@ -40,6 +41,7 @@ #include #include #include +#include #include #include @@ -195,6 +197,9 @@ class CommandProcessor : public simdojo::Component { } private: + struct ClusterWorkgroupPlacement; + struct ClusterBarrierState; + /// @brief Initialize a wavefront's registers per the AMDHSA ABI. void init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, const DispatchEntry &entry, uint32_t global_wg_id, uint32_t wf_index_in_wg); @@ -251,6 +256,16 @@ class CommandProcessor : public simdojo::Component { void register_cluster_workgroup(const DispatchEntry &entry, uint32_t local_wg_id, uint32_t global_wg_id, ComputeUnitCore *cu, uint32_t lds_base); + bool cluster_barrier_signal(Wavefront &wf, int32_t barrier_id); + uint32_t cluster_barrier_state(const Wavefront &wf, int32_t barrier_id, + uint32_t allocation_blocks) const; + bool cluster_barrier_valid(const Wavefront &wf, int32_t barrier_id) const; + bool find_valid_cluster_barrier_locked(const Wavefront &wf, int32_t barrier_id, + ClusterWorkgroupPlacement *&placement, + ClusterBarrierState *&barriers); + bool find_valid_cluster_barrier_locked(const Wavefront &wf, int32_t barrier_id, + const ClusterWorkgroupPlacement *&placement, + const ClusterBarrierState *&barriers) const; void mark_cluster_workgroup_complete(uint32_t dispatch_id, uint32_t wg_id); void erase_cluster_workgroup(uint32_t dispatch_id, uint32_t wg_id); void erase_cluster_workgroups(uint32_t dispatch_id); @@ -333,12 +348,22 @@ class CommandProcessor : public simdojo::Component { std::vector peer_wg_ids; }; std::unordered_map cluster_wg_placements_; + struct ClusterBarrierState { + uint32_t expected_member_count = 0; + uint32_t member_count = 0; + std::unordered_set registered_workgroups; + std::array, 2> signaled_workgroups; + }; + std::unordered_map cluster_barriers_; + mutable std::recursive_mutex cluster_barrier_mutex_; simdojo::Event doorbell_event_{this, simdojo::EventType::TIMER_CALLBACK}; std::recursive_mutex hw_queue_mutex_; std::shared_ptr plugin_group_ = ExecutionPluginGroup::empty_group(); + friend class ComputeUnitCore; + /// @brief Read a uint64 from GPU virtual address space via GpuMemory translation. uint64_t read_gpu_u64(uint64_t va, uint32_t vmid) const; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp index aa90a06215df..fb0df2892df7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp @@ -29,6 +29,18 @@ namespace rocjitsu { namespace amdgpu { +namespace { +constexpr uint32_t kPrivilegedStatusBit = 1u << 5; + +bool is_privileged(const Wavefront &wf) { return (wf.status_raw() & kPrivilegedStatusBit) != 0; } + +uint32_t pack_barrier_state(uint32_t member_count, uint32_t signal_count, + uint32_t allocation_blocks = 0) { + return 1u | ((member_count & 0x7fu) << 4) | ((signal_count & 0x7fu) << 16) | + ((allocation_blocks & 0x7u) << 24); +} +} // namespace + template void validate_compute_unit_config(const ComputeUnitCore::Config &config) { using Limits = IsaExecComputeUnit; @@ -207,12 +219,231 @@ void ComputeUnitCore::maybe_reset_lds_alloc() { reset_lds_alloc(); } +void ComputeUnitCore::begin_workgroup(uint32_t dispatch_id, uint32_t wg_id, uint32_t wf_count, + uint32_t num_named_barriers) { + const uint64_t key = wg_key(dispatch_id, wg_id); + active_wgs_[key] = wf_count; + if (wf_count <= 1) { + // Single-wave workgroups are not allocated workgroup or named barriers. + barrier_wgs_.erase(key); + return; + } + + auto &group = barrier_wgs_[key]; + group = {}; + group.allocated_count = std::min(num_named_barriers, kMaxNamedBarriers); + for (auto &barrier : group.workgroup) + barrier.member_count = wf_count; +} + +void ComputeUnitCore::named_barrier_init(Wavefront &wf, int32_t barrier_id, uint32_t member_count) { + auto group = barrier_wgs_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + if (group == barrier_wgs_.end() || barrier_id <= 0 || + static_cast(barrier_id) > group->second.allocated_count) + return; + + auto &barrier = group->second.named[static_cast(barrier_id)]; + if (member_count != 0) + barrier.member_count = member_count & 0x7fu; + barrier.signal_count = 0; +} + +void ComputeUnitCore::named_barrier_join(Wavefront &wf, int32_t barrier_id) { + auto group = barrier_wgs_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + if (group == barrier_wgs_.end()) + return; + if (barrier_id == 0) { + wf.named_barrier_id_ = 0; + wf.barrier_complete_[kNamedBarrierBit] = false; + if (wf.waiting_barrier_bit_ == kNamedBarrierBit) + wf.waiting_barrier_bit_ = Wavefront::kNoBarrierWait; + return; + } + if (barrier_id < 0 || static_cast(barrier_id) > group->second.allocated_count) + return; + wf.named_barrier_id_ = static_cast(barrier_id); + wf.barrier_complete_[kNamedBarrierBit] = false; + if (wf.waiting_barrier_bit_ == kNamedBarrierBit) + wf.waiting_barrier_bit_ = Wavefront::kNoBarrierWait; +} + +bool ComputeUnitCore::barrier_signal(Wavefront &wf, int32_t barrier_id, uint32_t member_count) { + if (barrier_id == kClusterBarrierId || barrier_id == kClusterTrapBarrierId) { + if (barrier_id == kClusterTrapBarrierId && !is_privileged(wf)) + return false; + return cp_ ? cp_->cluster_barrier_signal(wf, barrier_id) : false; + } + + auto group = barrier_wgs_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + if (group == barrier_wgs_.end() || barrier_id == 0 || barrier_id < kWorkgroupTrapBarrierId) + return false; + + BarrierCounter *barrier = nullptr; + uint8_t completion_bit = kNamedBarrierBit; + uint32_t named_id = 0; + if (barrier_id > 0) { + named_id = static_cast(barrier_id); + if (named_id > group->second.allocated_count) + return false; + barrier = &group->second.named[named_id]; + if (member_count != 0) + barrier->member_count = member_count & 0x7fu; + } else { + if (barrier_id == kWorkgroupTrapBarrierId && !is_privileged(wf)) + return false; + completion_bit = static_cast(-barrier_id); + barrier = &group->second.workgroup[completion_bit - kWorkgroupBarrierBit]; + } + + if (barrier->member_count == 0) + return false; + const bool is_first = barrier->signal_count == 0; + barrier->signal_count = std::min(barrier->signal_count + 1, 0x7fu); + if (barrier->signal_count < barrier->member_count) + return is_first; + + barrier->signal_count = 0; + auto members = complete_barrier(wf.dispatch_id(), wf.wg_id(), completion_bit, named_id); + notify_barrier_complete(members); + return is_first; +} + +std::vector ComputeUnitCore::complete_barrier(uint32_t dispatch_id, uint32_t wg_id, + uint8_t completion_bit, + uint32_t named_barrier_id) { + std::vector members; + for (const auto &candidate : wfs_) { + if (candidate->is_halted() || candidate->dispatch_id() != dispatch_id || + candidate->wg_id() != wg_id) + continue; + if (completion_bit == kNamedBarrierBit && candidate->named_barrier_id_ != named_barrier_id) + continue; + candidate->barrier_complete_[completion_bit] = true; + members.push_back(candidate.get()); + } + for (auto *member : members) { + if (member->state() == WfState::BARRIER && member->waiting_barrier_bit_ == completion_bit) { + member->barrier_complete_[completion_bit] = false; + member->waiting_barrier_bit_ = Wavefront::kNoBarrierWait; + member->set_state(WfState::RUNNING); + member->set_ready_cycle(cycle_counter_); + } + } + return members; +} + +void ComputeUnitCore::notify_barrier_complete(std::span members) { + if (!members.empty()) + plugin_group_->onAmdgpuBarrierResolved(members); +} + +uint32_t ComputeUnitCore::barrier_state(const Wavefront &wf, int32_t barrier_id) const { + auto group = barrier_wgs_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + const uint32_t allocation_blocks = + group == barrier_wgs_.end() ? 0 : (group->second.allocated_count + 3) / 4; + + if (barrier_id == kClusterBarrierId || barrier_id == kClusterTrapBarrierId) { + if (barrier_id == kClusterTrapBarrierId && !is_privileged(wf)) + return 0; + return cp_ ? cp_->cluster_barrier_state(wf, barrier_id, allocation_blocks) : 0; + } + + if (group == barrier_wgs_.end() || barrier_id == 0 || barrier_id < kWorkgroupTrapBarrierId) + return 0; + + if (barrier_id < 0) { + if (barrier_id == kWorkgroupTrapBarrierId && !is_privileged(wf)) + return 0; + const auto &barrier = group->second.workgroup[static_cast(-barrier_id - 1)]; + return pack_barrier_state(barrier.member_count, barrier.signal_count, allocation_blocks); + } + + const uint32_t id = static_cast(barrier_id); + if (id > group->second.allocated_count) + return 0; + const auto &barrier = group->second.named[id]; + return pack_barrier_state(barrier.member_count, barrier.signal_count, allocation_blocks); +} + +void ComputeUnitCore::barrier_wait(Wavefront &wf, int32_t barrier_id) { + uint8_t completion_bit = kNamedBarrierBit; + if (barrier_id >= 0) { + auto group = barrier_wgs_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + if (group == barrier_wgs_.end() || wf.named_barrier_id_ == 0 || + wf.named_barrier_id_ > group->second.allocated_count) + return; + } else { + if (barrier_id < kClusterTrapBarrierId || + ((barrier_id == kWorkgroupTrapBarrierId || barrier_id == kClusterTrapBarrierId) && + !is_privileged(wf))) + return; + completion_bit = static_cast(-barrier_id); + if (completion_bit <= kWorkgroupTrapBarrierBit) { + if (!barrier_wgs_.contains(wg_key(wf.dispatch_id(), wf.wg_id()))) + return; + } else if (!cp_ || !cp_->cluster_barrier_valid(wf, barrier_id)) { + return; + } + } + + if (wf.barrier_complete_[completion_bit]) { + wf.barrier_complete_[completion_bit] = false; + return; + } + wf.waiting_barrier_bit_ = completion_bit; + wf.set_state(WfState::BARRIER); +} + +bool ComputeUnitCore::named_barrier_leave(Wavefront &wf) { + auto group = barrier_wgs_.find(wg_key(wf.dispatch_id(), wf.wg_id())); + const uint32_t id = wf.named_barrier_id_; + if (group == barrier_wgs_.end()) + return false; + if (id == 0) + return true; + if (id > group->second.allocated_count) + return false; + + wf.named_barrier_id_ = 0; + wf.barrier_complete_[kNamedBarrierBit] = false; + if (wf.waiting_barrier_bit_ == kNamedBarrierBit) + wf.waiting_barrier_bit_ = Wavefront::kNoBarrierWait; + auto &barrier = group->second.named[id]; + if (barrier.member_count != 0) + --barrier.member_count; + if (barrier.signal_count >= barrier.member_count) { + barrier.signal_count = 0; + auto members = complete_barrier(wf.dispatch_id(), wf.wg_id(), kNamedBarrierBit, id); + notify_barrier_complete(members); + } + return barrier.member_count == 0; +} + void ComputeUnitCore::release_wf(uint32_t dispatch_id, uint32_t wg_id) { auto key = wg_key(dispatch_id, wg_id); + auto group = barrier_wgs_.find(key); + if (group != barrier_wgs_.end()) { + const auto retire_member = [&](BarrierCounter &barrier, uint8_t completion_bit, + uint32_t joined_id = 0) { + if (barrier.member_count == 0) + return; + --barrier.member_count; + if (barrier.member_count == 0 || barrier.signal_count < barrier.member_count) + return; + barrier.signal_count = 0; + auto members = complete_barrier(dispatch_id, wg_id, completion_bit, joined_id); + notify_barrier_complete(members); + }; + + retire_member(group->second.workgroup[0], kWorkgroupBarrierBit); + retire_member(group->second.workgroup[1], kWorkgroupTrapBarrierBit); + } + auto it = active_wgs_.find(key); if (it != active_wgs_.end() && --it->second == 0) { plugin_group_->onAmdgpuWorkgroupCompleted(dispatch_id, wg_id); active_wgs_.erase(it); + barrier_wgs_.erase(key); if (cp_) cp_->notify_wg_complete(dispatch_id, wg_id); } @@ -233,6 +464,7 @@ void ComputeUnitCore::abort_workgroup(uint32_t dispatch_id, uint32_t wg_id) { free_wavefront_resources(*w); } active_wgs_.erase(wg_key(dispatch_id, wg_id)); + barrier_wgs_.erase(wg_key(dispatch_id, wg_id)); maybe_reset_lds_alloc(); } @@ -335,14 +567,15 @@ void ComputeUnitCore::update_wf_states() { } for (auto &w : wfs_) { - if (w->state() != WfState::BARRIER) + if (w->state() != WfState::BARRIER || w->waiting_barrier_bit_ != Wavefront::kNoBarrierWait) continue; uint32_t did = w->dispatch_id(); uint32_t wg = w->wg_id(); bool all_at_barrier = true; for (auto &w2 : wfs_) { if (w2->dispatch_id() == did && w2->wg_id() == wg && w2->state() != WfState::HALTED && - w2->state() != WfState::BARRIER) { + (w2->state() != WfState::BARRIER || + w2->waiting_barrier_bit_ != Wavefront::kNoBarrierWait)) { all_at_barrier = false; break; } @@ -350,7 +583,8 @@ void ComputeUnitCore::update_wf_states() { if (all_at_barrier) { std::vector barrier_wfs; for (auto &w2 : wfs_) - if (w2->dispatch_id() == did && w2->wg_id() == wg && w2->state() == WfState::BARRIER) + if (w2->dispatch_id() == did && w2->wg_id() == wg && w2->state() == WfState::BARRIER && + w2->waiting_barrier_bit_ == Wavefront::kNoBarrierWait) barrier_wfs.push_back(w2.get()); plugin_group_->onAmdgpuBarrierResolved(std::span(barrier_wfs)); for (auto *bwf : barrier_wfs) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h index 1fd558942e52..d8abd097fe57 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h @@ -52,6 +52,17 @@ namespace amdgpu { class CommandProcessor; +inline constexpr int32_t kWorkgroupBarrierId = -1; +inline constexpr int32_t kWorkgroupTrapBarrierId = -2; +inline constexpr int32_t kClusterBarrierId = -3; +inline constexpr int32_t kClusterTrapBarrierId = -4; + +inline constexpr uint8_t kNamedBarrierBit = 0; +inline constexpr uint8_t kWorkgroupBarrierBit = 1; +inline constexpr uint8_t kWorkgroupTrapBarrierBit = 2; +inline constexpr uint8_t kClusterBarrierBit = 3; +inline constexpr uint8_t kClusterTrapBarrierBit = 4; + /// @brief Base AMDGPU compute unit that owns wavefront slots and register files. /// /// @details Owns the physical SGPR and VGPR register files and a fixed array of @@ -75,6 +86,7 @@ class CommandProcessor; class ComputeUnitCore : public simdojo::CompositeComponent { public: static constexpr uint32_t kFunctionalQuantum = 1024; + static constexpr uint32_t kMaxNamedBarriers = 16; /// @brief Configuration for a compute unit. struct Config { @@ -198,9 +210,26 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// @brief Register a new workgroup with its expected WF count. /// @details Called by the DispatchController when assigning a WG to this CU. /// Initializes the refcount so release_wf() can detect WG completion. - void begin_workgroup(uint32_t dispatch_id, uint32_t wg_id, uint32_t wf_count) { - active_wgs_[wg_key(dispatch_id, wg_id)] = wf_count; - } + void begin_workgroup(uint32_t dispatch_id, uint32_t wg_id, uint32_t wf_count, + uint32_t num_named_barriers = 0); + + /// @brief Initialize a named barrier's member count and clear its signals. + void named_barrier_init(Wavefront &wf, int32_t barrier_id, uint32_t member_count); + + /// @brief Associate a wave with one named barrier. + void named_barrier_join(Wavefront &wf, int32_t barrier_id); + + /// @brief Signal a split-barrier domain and return whether this was its first signal. + bool barrier_signal(Wavefront &wf, int32_t barrier_id, uint32_t member_count); + + /// @brief Return the packed architectural state of a split-barrier domain. + uint32_t barrier_state(const Wavefront &wf, int32_t barrier_id) const; + + /// @brief Wait on the completion bit selected by a split-barrier ID. + void barrier_wait(Wavefront &wf, int32_t barrier_id); + + /// @brief Leave the wave's currently joined named barrier. + bool named_barrier_leave(Wavefront &wf); /// @brief Called by Wavefront::halt() to decrement the WG refcount. /// @details When the refcount reaches zero, all WFs in the WG have halted @@ -662,6 +691,20 @@ class ComputeUnitCore : public simdojo::CompositeComponent { std::unordered_map active_wgs_; + struct BarrierCounter { + uint32_t member_count = 0; + uint32_t signal_count = 0; + }; + struct WorkgroupBarriers { + uint32_t allocated_count = 0; + std::array named{}; + std::array workgroup{}; + }; + std::vector complete_barrier(uint32_t dispatch_id, uint32_t wg_id, + uint8_t completion_bit, uint32_t named_barrier_id = 0); + void notify_barrier_complete(std::span members); + std::unordered_map barrier_wgs_; + uint64_t shared_aperture_base_ = 0; uint64_t shared_aperture_limit_ = 0; uint64_t private_aperture_base_ = 0; @@ -678,6 +721,8 @@ class ComputeUnitCore : public simdojo::CompositeComponent { simdojo::Port *req_ = nullptr; ///< Requester port: L2 cache request (structural). uint64_t step_count_ = 0; bool functional_yield_requested_ = false; + + friend class CommandProcessor; }; inline L1ScalarCache &InstructionComputeUnitView::l1_scalar() { return raw_cu().l1_scalar(); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h index d020870b9754..06b18d12ba7f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h @@ -55,6 +55,7 @@ struct DispatchEntry { uint32_t kernarg_size = 0; uint32_t num_user_sgprs = 2; uint32_t kernel_code_properties = 0; + uint32_t num_named_barriers = 0; uint16_t kernarg_preload = 0; uint32_t initial_mode_raw = 0; uint64_t dispatch_ptr = 0; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds_barrier_cell.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds_barrier_cell.h index a1a5171fbe32..467f1c2102c3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds_barrier_cell.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/lds_barrier_cell.h @@ -11,14 +11,13 @@ namespace amdgpu { /// Raw LDS barrier cell used by the gfx1250 DS barrier-arrive instructions. /// -/// The AMDGCN ISA raw async-barrier object uses [15:0] pending, [31:16] -/// phase, and [47:32] init count. This is intentionally distinct from MLIR's -/// ds_barrier_state helper; kernels that poll the raw cell directly test bit -/// 16 for phase parity. -constexpr uint64_t kLdsBarrierCellPendingMask = 0xffffull; -constexpr uint64_t kLdsBarrierCellPhaseMask = 0xffffull; +/// RocJITsu uses the CDNA5 WIDTH=29 form described by the architectural LDS +/// barrier layout: [28:0] pending, [31:29] phase, and [47:32] init count. +/// Polling kernels test bit 29 for phase parity. +constexpr uint64_t kLdsBarrierCellPendingMask = (1ull << 29) - 1; +constexpr uint64_t kLdsBarrierCellPhaseMask = 0x7ull; constexpr uint64_t kLdsBarrierCellInitCountMask = 0xffffull; -constexpr uint32_t kLdsBarrierCellPhaseShift = 16; +constexpr uint32_t kLdsBarrierCellPhaseShift = 29; constexpr uint32_t kLdsBarrierCellInitCountShift = 32; constexpr uint64_t kLdsBarrierCellReservedMask = 0xffff000000000000ull; @@ -27,7 +26,7 @@ inline uint64_t lds_barrier_cell_pending_count(uint64_t state) { return state & kLdsBarrierCellPendingMask; } -/// Return the raw 16-bit phase counter. +/// Return the raw three-bit phase counter. inline uint64_t lds_barrier_cell_phase(uint64_t state) { return (state >> kLdsBarrierCellPhaseShift) & kLdsBarrierCellPhaseMask; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h index a20af86c4ca2..8a7b6ce35762 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h @@ -103,7 +103,8 @@ class ShaderProcessorInput { ComputeUnitCore *cu = placement->cu; uint32_t lds_base = placement->lds_base; - cu->begin_workgroup(wg.entry->dispatch_id, wg.global_wg_id, wg.entry->wfs_per_workgroup); + cu->begin_workgroup(wg.entry->dispatch_id, wg.global_wg_id, wg.entry->wfs_per_workgroup, + wg.entry->num_named_barriers); std::vector wg_wfs; wg_wfs.reserve(wg.entry->wfs_per_workgroup); for (uint32_t w = 0; w < wg.entry->wfs_per_workgroup; ++w) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp index 1c6db2ea9d5a..9af1a1b52145 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp @@ -24,6 +24,24 @@ void Wavefront::write_gpu_memory(uint64_t addr, std::span src) { cu_.memory()->write_block(addr, src, process_id_); } +void Wavefront::barrier_init(int32_t barrier_id, uint32_t member_count) { + cu_.named_barrier_init(*this, barrier_id, member_count); +} + +void Wavefront::barrier_join(int32_t barrier_id) { cu_.named_barrier_join(*this, barrier_id); } + +bool Wavefront::barrier_signal(int32_t barrier_id, uint32_t member_count) { + return cu_.barrier_signal(*this, barrier_id, member_count); +} + +uint32_t Wavefront::barrier_state(int32_t barrier_id) const { + return cu_.barrier_state(*this, barrier_id); +} + +void Wavefront::barrier_wait(int32_t barrier_id) { cu_.barrier_wait(*this, barrier_id); } + +bool Wavefront::barrier_leave() { return cu_.named_barrier_leave(*this); } + void Wavefront::halt() { // s_endpgm terminates the wave, frees its resources, and notifies the CP as one // action, mirroring hardware. Order matters: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h index 576f42ff8e6e..408dbd6c496e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h @@ -171,6 +171,24 @@ class Wavefront : public ThreadContext { /// @brief Set the per-WG LDS base offset. void set_lds_base(uint32_t base) { lds_base_ = base; } + /// @brief Initialize a workgroup named barrier from an ISA barrier operand. + void barrier_init(int32_t barrier_id, uint32_t member_count); + + /// @brief Join one workgroup named barrier. + void barrier_join(int32_t barrier_id); + + /// @brief Signal a barrier and report whether this is its first signal. + bool barrier_signal(int32_t barrier_id, uint32_t member_count); + + /// @brief Read the packed architectural state of a barrier. + uint32_t barrier_state(int32_t barrier_id) const; + + /// @brief Wait on a named, workgroup, trap, or cluster barrier. + void barrier_wait(int32_t barrier_id); + + /// @brief Leave the currently joined named barrier. + bool barrier_leave(); + /// @brief Return the aligned LDS allocation size for this workgroup. uint32_t lds_size() const { return lds_size_; } @@ -525,6 +543,9 @@ class Wavefront : public ThreadContext { shared_aperture_limit_ = 0; private_aperture_base_ = 0; private_aperture_limit_ = 0; + named_barrier_id_ = 0; + barrier_complete_.fill(false); + waiting_barrier_bit_ = kNoBarrierWait; wait_counters_ = {}; wait_target_ = {}; ready_cycle_ = 0; @@ -584,8 +605,13 @@ class Wavefront : public ThreadContext { uint64_t shared_aperture_limit_ = 0; uint64_t private_aperture_base_ = 0; uint64_t private_aperture_limit_ = 0; - WfState state_ = WfState::HALTED; ///< Current execution state. - WaitCounters wait_counters_; ///< Outstanding memory operation counters. + static constexpr uint8_t kNoBarrierWait = 0xff; + uint32_t named_barrier_id_ = 0; ///< Currently joined named barrier. + /// Completion bits: named, workgroup, workgroup trap, cluster, cluster trap. + std::array barrier_complete_{}; + uint8_t waiting_barrier_bit_ = kNoBarrierWait; ///< Completion bit awaited by split wait. + WfState state_ = WfState::HALTED; ///< Current execution state. + WaitCounters wait_counters_; ///< Outstanding memory operation counters. public: uint32_t trace_inst_count_ = 0; ///< Debug: instruction count for trace. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/execution_plugin.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/execution_plugin.h index bca848950e7d..6355521d6d30 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/execution_plugin.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/execution_plugin.h @@ -171,7 +171,7 @@ class ExecutionPlugin { /// requires_serial_hot_hooks() returns true. virtual void onAmdgpuReadSgpr(const amdgpu::Wavefront * /*wf*/, uint32_t /*physical_reg*/) {} - /// Called when all waves in a workgroup have reached s_barrier. + /// Called with the waves synchronized by a completed barrier domain. /// Infrequent hook; see the concurrency contract on requires_serial_hot_hooks(). virtual void onAmdgpuBarrierResolved(std::span /*wavefronts*/) {} diff --git a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp index 06bf97c8db61..fd4d1e6c6388 100644 --- a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp @@ -8,6 +8,24 @@ namespace { using namespace rocjitsu; using namespace rocjitsu::test::cdna5; +class BarrierSpanPlugin final : public ExecutionPlugin { +public: + BarrierSpanPlugin() : ExecutionPlugin("barrier_span") {} + + void onAmdgpuBarrierResolved(std::span wavefronts) override { + span_sizes.push_back(wavefronts.size()); + std::vector workgroups; + for (const auto *wf : wavefronts) + workgroups.push_back(wf->wg_id()); + std::ranges::sort(workgroups); + workgroups.erase(std::unique(workgroups.begin(), workgroups.end()), workgroups.end()); + workgroup_ids.push_back(std::move(workgroups)); + } + + std::vector span_sizes; + std::vector> workgroup_ids; +}; + TEST(Gfx1250SimulationTest, SGetPcI64ReturnsNextInstructionAddress) { constexpr uint64_t kKernelAddr = 0x10000; const uint32_t code[] = { @@ -259,6 +277,345 @@ TEST(Gfx1250SimulationTest, SplitNamedBarrierOpsReportIdleState) { EXPECT_EQ(wf->sgpr(4), 0u); } +TEST(Gfx1250SimulationTest, NamedBarrierSignalIsfirstPreservesSccWithoutAllocation) { + Gfx1250Sim sim; + auto *wf = sim.dispatch_scratch_wf(); + ASSERT_NE(wf, nullptr); + + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + const std::array signal_words = {0xBE804F7Du}; + std::unique_ptr signal(decoder->decode(signal_words.data())); + ASSERT_NE(signal, nullptr); + + wf->set_m0((2u << 16) | 1u); + wf->write_scc(true); + sim.cu()->execute_instruction(signal.get(), *wf); + EXPECT_TRUE(wf->read_scc()); +} + +void expect_barrier_init_reads_implicit_m0(uint32_t init_encoding, uint32_t init_m0) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf0 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *wf1 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf0, nullptr); + ASSERT_NE(wf1, nullptr); + cu->begin_workgroup(0, 0, 2, 4); + + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + const std::array init_words = {init_encoding}; + const std::array join_words = {0xBE805281u}; // s_barrier_join 1 + const std::array signal_words = {0xBE804F81u}; // s_barrier_signal_isfirst 1 + const std::array state_words = {0xBE845081u}; // s_get_barrier_state s4, 1 + std::unique_ptr init(decoder->decode(init_words.data())); + std::unique_ptr join(decoder->decode(join_words.data())); + std::unique_ptr signal(decoder->decode(signal_words.data())); + std::unique_ptr state(decoder->decode(state_words.data())); + ASSERT_NE(init, nullptr); + ASSERT_NE(join, nullptr); + ASSERT_NE(signal, nullptr); + ASSERT_NE(state, nullptr); + + wf0->set_m0(init_m0); + cu->execute_instruction(init.get(), *wf0); + for (auto *wf : {wf0, wf1}) + cu->execute_instruction(join.get(), *wf); + + cu->execute_instruction(signal.get(), *wf0); + EXPECT_TRUE(wf0->read_scc()); + cu->execute_instruction(state.get(), *wf0); + EXPECT_EQ(read_wave_sgpr(*cu, *wf0, 4), 0x01010021u); + wf0->barrier_wait(1); + EXPECT_EQ(wf0->state(), amdgpu::WfState::BARRIER); + + cu->execute_instruction(signal.get(), *wf1); + EXPECT_FALSE(wf1->read_scc()); + EXPECT_EQ(wf0->state(), amdgpu::WfState::RUNNING); + cu->execute_instruction(state.get(), *wf1); + EXPECT_EQ(read_wave_sgpr(*cu, *wf1, 4), 0x01000021u); +} + +TEST(Gfx1250SimulationTest, NamedBarrierInitImmediateReadsMemberCountFromImplicitM0) { + expect_barrier_init_reads_implicit_m0(0xBE805181u, 2u << 16); // s_barrier_init 1 +} + +TEST(Gfx1250SimulationTest, NamedBarrierInitM0ReadsMemberCountFromImplicitM0) { + expect_barrier_init_reads_implicit_m0(0xBE80517Du, (2u << 16) | 1u); // s_barrier_init m0 +} + +TEST(Gfx1250SimulationTest, NamedBarrierSynchronizesJoinedWavesAcrossPhases) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf0 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *wf1 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf0, nullptr); + ASSERT_NE(wf1, nullptr); + cu->begin_workgroup(0, 0, 2, 4); + + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + const std::array join_words = {0xBE80527Du}; + const std::array signal_words = {0xBE804F7Du}; + const std::array wait_words = {0xBF940001u}; + const std::array state_words = {0xBE84507Du}; + std::unique_ptr join(decoder->decode(join_words.data())); + std::unique_ptr signal(decoder->decode(signal_words.data())); + std::unique_ptr wait(decoder->decode(wait_words.data())); + std::unique_ptr state(decoder->decode(state_words.data())); + ASSERT_NE(join, nullptr); + ASSERT_NE(signal, nullptr); + ASSERT_NE(wait, nullptr); + ASSERT_NE(state, nullptr); + ASSERT_EQ(std::string_view(join->mnemonic()), "s_barrier_join"); + ASSERT_EQ(std::string_view(signal->mnemonic()), "s_barrier_signal_isfirst"); + ASSERT_EQ(std::string_view(wait->mnemonic()), "s_barrier_wait"); + ASSERT_EQ(std::string_view(state->mnemonic()), "s_get_barrier_state"); + + for (auto *wf : {wf0, wf1}) { + wf->set_m0(1); + cu->execute_instruction(join.get(), *wf); + wf->set_m0((2u << 16) | 1u); + } + + cu->execute_instruction(signal.get(), *wf0); + EXPECT_TRUE(wf0->read_scc()); + cu->execute_instruction(wait.get(), *wf0); + EXPECT_EQ(wf0->state(), amdgpu::WfState::BARRIER); + + cu->execute_instruction(signal.get(), *wf1); + EXPECT_FALSE(wf1->read_scc()); + EXPECT_EQ(wf0->state(), amdgpu::WfState::RUNNING); + cu->execute_instruction(wait.get(), *wf1); + EXPECT_EQ(wf1->state(), amdgpu::WfState::RUNNING); + + cu->execute_instruction(state.get(), *wf0); + EXPECT_EQ(read_wave_sgpr(*cu, *wf0, 4), 0x01000021u); + + cu->execute_instruction(signal.get(), *wf1); + EXPECT_TRUE(wf1->read_scc()); + cu->execute_instruction(wait.get(), *wf1); + EXPECT_EQ(wf1->state(), amdgpu::WfState::BARRIER); + + cu->execute_instruction(signal.get(), *wf0); + EXPECT_FALSE(wf0->read_scc()); + EXPECT_EQ(wf1->state(), amdgpu::WfState::RUNNING); + cu->execute_instruction(wait.get(), *wf0); + EXPECT_EQ(wf0->state(), amdgpu::WfState::RUNNING); +} + +TEST(Gfx1250SimulationTest, WorkgroupBarrierSignalAndWaitUseDedicatedCompletionState) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf0 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *wf1 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf0, nullptr); + ASSERT_NE(wf1, nullptr); + cu->begin_workgroup(0, 0, 2, 4); + + EXPECT_TRUE(wf0->barrier_signal(-1, 0)); + EXPECT_EQ(wf0->barrier_state(-1), 0x01010021u); + wf0->barrier_wait(-1); + EXPECT_EQ(wf0->state(), amdgpu::WfState::BARRIER); + + EXPECT_FALSE(wf1->barrier_signal(-1, 0)); + EXPECT_EQ(wf0->state(), amdgpu::WfState::RUNNING); + EXPECT_EQ(wf1->barrier_state(-1), 0x01000021u); + wf1->barrier_wait(-1); + EXPECT_EQ(wf1->state(), amdgpu::WfState::RUNNING); +} + +TEST(Gfx1250SimulationTest, WorkgroupBarrierCompletesAfterUnsignaledWaveTerminates) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *waiting = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *terminating = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(waiting, nullptr); + ASSERT_NE(terminating, nullptr); + cu->begin_workgroup(0, 0, 2); + + EXPECT_TRUE(waiting->barrier_signal(-1, 0)); + waiting->barrier_wait(-1); + EXPECT_EQ(waiting->state(), amdgpu::WfState::BARRIER); + + terminating->halt(); + EXPECT_EQ(waiting->state(), amdgpu::WfState::RUNNING); + EXPECT_EQ(waiting->barrier_state(-1), 0x00000011u); +} + +TEST(Gfx1250SimulationTest, NamedBarrierMembershipPersistsAfterJoinedWaveTerminates) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *waiting = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *terminating = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(waiting, nullptr); + ASSERT_NE(terminating, nullptr); + cu->begin_workgroup(0, 0, 2, 4); + + waiting->barrier_init(1, 2); + waiting->barrier_join(1); + terminating->barrier_join(1); + EXPECT_TRUE(waiting->barrier_signal(1, 0)); + waiting->barrier_wait(1); + EXPECT_EQ(waiting->state(), amdgpu::WfState::BARRIER); + + terminating->halt(); + EXPECT_EQ(waiting->state(), amdgpu::WfState::BARRIER); + EXPECT_EQ(waiting->barrier_state(1), 0x01010021u); +} + +TEST(Gfx1250SimulationTest, WorkgroupAndTrapBarriersKeepIndependentSignalCounts) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf0 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *wf1 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf0, nullptr); + ASSERT_NE(wf1, nullptr); + cu->begin_workgroup(0, 0, 2); + + EXPECT_TRUE(wf0->barrier_signal(-1, 0)); + EXPECT_EQ(wf0->barrier_state(-1), 0x00010021u); + EXPECT_EQ(wf0->barrier_state(-2), 0u); + + wf0->set_status_raw(wf0->status_raw() | (1u << 5)); + EXPECT_TRUE(wf0->barrier_signal(-2, 0)); + EXPECT_EQ(wf0->barrier_state(-2), 0x00010021u); + EXPECT_EQ(wf0->barrier_state(-1), 0x00010021u); +} + +TEST(Gfx1250SimulationTest, WorkgroupSignalIsfirstAcceptsNegativeInlineBarrierId) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf0 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *wf1 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf0, nullptr); + ASSERT_NE(wf1, nullptr); + cu->begin_workgroup(0, 0, 2); + + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + const std::array signal_words = {0xBE804FC1u}; // s_barrier_signal_isfirst -1 + std::unique_ptr signal(decoder->decode(signal_words.data())); + ASSERT_NE(signal, nullptr); + + cu->execute_instruction(signal.get(), *wf0); + EXPECT_TRUE(wf0->read_scc()); + cu->execute_instruction(signal.get(), *wf1); + EXPECT_FALSE(wf1->read_scc()); +} + +TEST(Gfx1250SimulationTest, NamedBarrierLeaveCompletesReducedMembership) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf0 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + auto *wf1 = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf0, nullptr); + ASSERT_NE(wf1, nullptr); + cu->begin_workgroup(0, 0, 2, 4); + + wf0->barrier_init(1, 2); + EXPECT_EQ(wf0->barrier_state(1), 0x01000021u); + wf0->barrier_join(1); + wf1->barrier_join(1); + EXPECT_TRUE(wf0->barrier_signal(1, 0)); + wf0->barrier_wait(7); // Any nonnegative immediate waits on the joined named barrier. + EXPECT_EQ(wf0->state(), amdgpu::WfState::BARRIER); + + EXPECT_FALSE(wf1->barrier_leave()); + EXPECT_EQ(wf0->state(), amdgpu::WfState::RUNNING); + EXPECT_EQ(wf0->barrier_state(1), 0x01000011u); + EXPECT_TRUE(wf0->barrier_leave()); + EXPECT_EQ(wf0->barrier_state(1), 0x01000001u); +} + +TEST(Gfx1250SimulationTest, AqlDescriptorAllocatesNamedBarriersForTwoWaveKernel) { + constexpr uint64_t kKernelAddr = 0x10000; + const uint32_t code[] = { + 0xBEFD0081u, // s_mov_b32 m0, 1 + 0xBE80527Du, // s_barrier_join m0 + 0xBEFD00FFu, + 0x00020001u, // s_mov_b32 m0, (2 << 16) | 1 + 0xBE804E7Du, // s_barrier_signal m0 + 0xBF940007u, // s_barrier_wait 7 (the joined named barrier) + 0xBE84507Du, // s_get_barrier_state s4, m0 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + uint64_t kernel_object = sim.write_kernel(kKernelAddr, code, std::size(code), 104, 32, 2, false, + false, false, 0, 0, 0, 0, 0, 1); + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch(kernel_object, 64, 64); + step_until_halted(*sim.engine, *sim.cu()); + + ASSERT_EQ(sim.snapshot->snapshots().size(), 2u); + for (const auto &wf : sim.snapshot->snapshots()) + EXPECT_EQ(wf.sgpr(4), 0x01000021u); +} + +TEST(Gfx1250SimulationTest, ClusterBarrierSynchronizesWorkgroupsAcrossComputeUnits) { + constexpr auto read_first_workitem = + cdna5::build_vop1(cdna5::kVReadfirstlaneB32Vop1, {.src0 = 256, .vdst = 4}); + constexpr auto is_first_wave = + cdna5::build_sopc(cdna5::kSCmpEqU32Sopc, {.ssrc0 = 4, .ssrc1 = 128}); + constexpr auto skip_signal = cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 1}); + const uint32_t code[] = { + read_first_workitem[0], // v_readfirstlane_b32 s4, v0 + is_first_wave[0], // s_cmp_eq_u32 s4, 0 + skip_signal[0], // s_cbranch_scc0 wait + 0xBE804EC3u, // s_barrier_signal -3 + 0xBF94FFFDu, // s_barrier_wait -3 + 0xBE8450C3u, // s_get_barrier_state s4, -3 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + auto plugin = std::make_unique(); + auto *barrier_span = plugin.get(); + ASSERT_TRUE(sim.plugin_group->add(std::move(plugin))); + uint64_t kernel_object = sim.write_kernel(0x10000, code, std::size(code), 104, 32, 2, false, + false, false, 0, 0, 0, 0, 0, 1); + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch_clustered(kernel_object, /*cluster_count_x=*/1, /*cluster_size_x=*/2, + /*workgroup_size_x=*/64); + step_until_xcd_halted(sim); + + ASSERT_EQ(sim.snapshot->snapshots().size(), 4u); + for (const auto &wf : sim.snapshot->snapshots()) { + const uint32_t state = wf.sgpr(4); + const uint32_t member_count = (state >> 4) & 0x7fu; + EXPECT_EQ(state & 0x07000001u, 0x01000001u); + EXPECT_EQ((state >> 16) & 0x7fu, 0u); + EXPECT_TRUE(member_count == 1 || member_count == 2); + } + ASSERT_EQ(barrier_span->span_sizes.size(), 1u); + EXPECT_EQ(barrier_span->span_sizes[0], 4u); + EXPECT_EQ(barrier_span->workgroup_ids[0], (std::vector{0, 1})); +} + +TEST(Gfx1250SimulationTest, ClusterBarrierCompletesAfterWorkgroupTerminatesEarly) { + constexpr auto is_first_workgroup = + cdna5::build_sopc(cdna5::kSCmpEqU32Sopc, {.ssrc0 = 2, .ssrc1 = 128}); + constexpr auto exit_first_workgroup = cdna5::build_sopp(cdna5::kSCbranchScc1Sopp, {.simm16 = 2}); + const uint32_t code[] = { + is_first_workgroup[0], // s_cmp_eq_u32 s2, 0 + exit_first_workgroup[0], // s_cbranch_scc1 end + 0xBE804EC3u, // s_barrier_signal -3 + 0xBF94FFFDu, // s_barrier_wait -3 + S_ENDPGM_GFX12, + }; + + Gfx1250Sim sim; + uint64_t kernel_object = sim.write_kernel(0x10000, code, std::size(code)); + test::AqlQueue queue(sim.memory, sim.cp()); + queue.dispatch_clustered(kernel_object, /*cluster_count_x=*/1, /*cluster_size_x=*/2, + /*workgroup_size_x=*/32); + step_until_xcd_halted(sim); + + ASSERT_EQ(sim.snapshot->snapshots().size(), 2u); +} + TEST(Gfx1250SimulationTest, VgprMsbModeTracksModeRegisterLayout) { Gfx1250Sim sim; // Resident wave: this test mutates and reads live wavefront MODE state. diff --git a/emulation/rocjitsu/tests/cdna5_sim_test_common.h b/emulation/rocjitsu/tests/cdna5_sim_test_common.h index 6c51e329b1a6..5277fe3f3b07 100644 --- a/emulation/rocjitsu/tests/cdna5_sim_test_common.h +++ b/emulation/rocjitsu/tests/cdna5_sim_test_common.h @@ -156,7 +156,8 @@ struct Gfx1250Sim { bool enable_wg_id_x = false, bool enable_wg_id_y = false, bool enable_wg_id_z = false, uint32_t kernel_code_properties = 0, uint32_t kernarg_size = 0, uint32_t kernarg_preload_length = 0, - uint32_t kernarg_preload_offset = 0, uint32_t enable_vgpr_workitem_id = 0) { + uint32_t kernarg_preload_offset = 0, uint32_t enable_vgpr_workitem_id = 0, + uint32_t named_barrier_blocks = 0) { using namespace rocr::llvm::amdhsa; kernel_descriptor_t kd{}; kd.kernel_code_entry_byte_offset = sizeof(kernel_descriptor_t); @@ -174,6 +175,8 @@ struct Gfx1250Sim { enable_wg_id_z); AMDHSA_BITS_SET(kd.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, enable_vgpr_workitem_id); + AMDHSA_BITS_SET(kd.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT, + named_barrier_blocks); kd.kernel_code_properties = kernel_code_properties; AMDHSA_BITS_SET(kd.kernarg_preload, KERNARG_PRELOAD_SPEC_LENGTH, kernarg_preload_length); AMDHSA_BITS_SET(kd.kernarg_preload, KERNARG_PRELOAD_SPEC_OFFSET, kernarg_preload_offset); diff --git a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp index cb3e66dbb2f2..02e860ab7691 100644 --- a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp @@ -698,7 +698,7 @@ TEST(Gfx1250ExecutionTest, TensorDmaRankThreeNullD2MasksTransfersAndCompletes) { EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); EXPECT_TRUE(wf->wait_counters().empty()); uint64_t barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); - EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_EQ(barrier_state, amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); for (uint32_t i = 0; i < kElements; ++i) { @@ -718,7 +718,7 @@ TEST(Gfx1250ExecutionTest, TensorDmaRankThreeNullD2MasksTransfersAndCompletes) { EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); EXPECT_TRUE(wf->wait_counters().empty()); barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); - EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_EQ(barrier_state, amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); } @@ -1054,7 +1054,7 @@ TEST(Gfx1250ExecutionTest, TensorDmaIterateZeroExtentSkipsLayoutValidationAndCom EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); EXPECT_TRUE(wf->wait_counters().empty()); uint64_t barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); - EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_EQ(barrier_state, amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); for (uint32_t i = 0; i < 3; ++i) @@ -1074,7 +1074,7 @@ TEST(Gfx1250ExecutionTest, TensorDmaIterateZeroExtentSkipsLayoutValidationAndCom EXPECT_EQ(wf->wait_counters().tensorcnt, 0u); EXPECT_TRUE(wf->wait_counters().empty()); barrier_state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); - EXPECT_EQ(barrier_state, 0xffffull << 16); + EXPECT_EQ(barrier_state, amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(barrier_state)); } @@ -1110,11 +1110,11 @@ TEST(Gfx1250ExecutionTest, TensorDmaAtomicBarrierArrivesAfterCopy) { EXPECT_EQ(cu->lds().read32(wf->lds_base() + 0 * 4), 0x55000000u); EXPECT_EQ(cu->lds().read32(wf->lds_base() + 1 * 4), 0x55000001u); const uint64_t state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); - EXPECT_EQ(state, 0xffffull << 16); + EXPECT_EQ(state, amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(state)); } -TEST(Gfx1250ExecutionTest, SBarrierWaitEntersBarrierState) { +TEST(Gfx1250ExecutionTest, SBarrierWaitIsNoOpForSingleWaveWorkgroup) { Gfx1250Sim sim; auto *cu = sim.cu(); auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); @@ -1124,17 +1124,17 @@ TEST(Gfx1250ExecutionTest, SBarrierWaitEntersBarrierState) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - const std::array wait_words = {0xBF940000u, 0u}; + const std::array wait_words = {0xBF94FFFFu, 0u}; std::unique_ptr wait_inst(decoder->decode(wait_words.data())); ASSERT_NE(wait_inst, nullptr); ASSERT_EQ(std::string_view(wait_inst->mnemonic()), "s_barrier_wait"); cu->execute_instruction(wait_inst.get(), *wf); - EXPECT_EQ(wf->state(), amdgpu::WfState::BARRIER); + EXPECT_EQ(wf->state(), amdgpu::WfState::RUNNING); } -TEST(Gfx1250ExecutionTest, SBarrierWaitReleasesOnlyAfterAllSiblingsWait) { +TEST(Gfx1250ExecutionTest, SBarrierWaitReleasesOnlyAfterSignalQuorum) { Gfx1250Sim sim; auto *cu = sim.cu(); constexpr uint64_t kEndPgmPc = 0x150000; @@ -1151,25 +1151,23 @@ TEST(Gfx1250ExecutionTest, SBarrierWaitReleasesOnlyAfterAllSiblingsWait) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - const std::array wait_words = {0xBF940000u, 0u}; + const std::array wait_words = {0xBF94FFFFu, 0u}; std::unique_ptr wait_inst(decoder->decode(wait_words.data())); ASSERT_NE(wait_inst, nullptr); ASSERT_EQ(std::string_view(wait_inst->mnemonic()), "s_barrier_wait"); cu->execute_instruction(wait_inst.get(), *wf0); - wf1->wait_counters().increment(amdgpu::WaitCounterType::TENSORCNT); - wf1->set_wait_target_tensorcnt(0); - wf1->set_state(amdgpu::WfState::WAITCNT); - - ASSERT_TRUE(cu->step()); EXPECT_EQ(wf0->state(), amdgpu::WfState::BARRIER); - EXPECT_EQ(wf1->state(), amdgpu::WfState::WAITCNT); - - wf1->release_wait_counter(amdgpu::WaitCounterType::TENSORCNT); - ASSERT_EQ(wf1->state(), amdgpu::WfState::RUNNING); cu->execute_instruction(wait_inst.get(), *wf1); ASSERT_EQ(wf1->state(), amdgpu::WfState::BARRIER); + EXPECT_TRUE(wf0->barrier_signal(-1, 0)); + EXPECT_EQ(wf0->state(), amdgpu::WfState::BARRIER); + EXPECT_EQ(wf1->state(), amdgpu::WfState::BARRIER); + EXPECT_FALSE(wf1->barrier_signal(-1, 0)); + EXPECT_EQ(wf0->state(), amdgpu::WfState::RUNNING); + EXPECT_EQ(wf1->state(), amdgpu::WfState::RUNNING); + EXPECT_FALSE(cu->step()); EXPECT_TRUE(wf0->is_halted()); EXPECT_TRUE(wf1->is_halted()); @@ -1226,7 +1224,7 @@ TEST(Gfx1250ExecutionTest, DsAtomicAsyncBarrierArriveFlipsRawBarrierPhase) { local_pipeline.issue(arrive_inst, *wf); const uint64_t state = cu->lds().read64(wf->lds_base() + kBarrierLdsAddr); - EXPECT_EQ(state, 0xffffull << 16); + EXPECT_EQ(state, amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(state)); EXPECT_TRUE(wf->wait_counters().empty()); } @@ -1258,7 +1256,9 @@ TEST(Gfx1250ExecutionTest, LocalMemPipelineUsesInjectedBarrierDecrementPayload) const uint64_t expected = amdgpu::lds_barrier_cell_update_arrive(amdgpu::lds_barrier_cell_init_state(2), decrement); EXPECT_EQ(cu->lds().read64(wf->lds_base() + kBarrierLdsAddr), expected); - EXPECT_EQ(expected, (1ull << 32) | (0xffffull << 16) | 1ull); + EXPECT_EQ(expected, (1ull << 32) | + (amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift) | + 1ull); EXPECT_TRUE(wf->wait_counters().empty()); } @@ -1271,7 +1271,9 @@ TEST(Gfx1250ExecutionTest, LdsBarrierCellHandlesSingleAndBatchedArrivals) { EXPECT_FALSE(amdgpu::lds_barrier_cell_phase_parity(state)); state = amdgpu::lds_barrier_cell_update_arrive(state); - EXPECT_EQ(state, (1ull << 32) | (0xffffull << 16) | 1ull); + EXPECT_EQ(state, (1ull << 32) | + (amdgpu::kLdsBarrierCellPhaseMask << amdgpu::kLdsBarrierCellPhaseShift) | + 1ull); EXPECT_TRUE(amdgpu::lds_barrier_cell_phase_parity(state)); const uint64_t drained = @@ -1287,7 +1289,8 @@ TEST(Gfx1250ExecutionTest, LdsBarrierCellHandlesSingleAndBatchedArrivals) { const uint64_t batched = amdgpu::lds_barrier_cell_update_arrive(amdgpu::lds_barrier_cell_init_state(2), 5); EXPECT_EQ(batched, iterated); - EXPECT_EQ(batched, (1ull << 32) | (0xfffeull << 16)); + EXPECT_EQ(batched, (1ull << 32) | (0x6ull << amdgpu::kLdsBarrierCellPhaseShift)); + EXPECT_FALSE(amdgpu::lds_barrier_cell_phase_parity(batched)); for (uint32_t arrivals_per_phase : {0u, 1u}) { state = amdgpu::lds_barrier_cell_init_state(arrivals_per_phase); From 7b5ecf6c7ba3dccdb1440b21f91ecffdf0d1b4ae Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 18 Aug 2026 22:10:02 -0400 Subject: [PATCH 17/27] [rocjitsu] Replace decoder exceptions with results (#10368) Instruction rejection is normal decoder control flow, so represent it explicitly instead of throwing. Generated decoders now return DecodeResult, diagnostics travel through the failure path, and decoder, operand, translation, patching, fuzz, test, and tool callers handle the result directly. The generator remains the source of truth and all architecture outputs are regenerated. Build on the prerequisite Result and diagnostic utilities. Keep validation call sites uniform without emitting empty per-format methods: IsaInstruction supplies a static constexpr success fallback, while formats hide it only when they have real checks. Generated validation temporaries spell out Result, with no virtual dispatch. Add a valid-dominated large-object decode benchmark. Against the exception-based baseline, the final niche-backed implementation is 4.1% faster on successful decodes and 34.0x faster when rejecting invalid encodings, based on medians from nine interleaved CPU-pinned runs with identical checksums and no unexpected accepts or rejects. (cherry picked from commit bea7ac8937c5e39ba8c703d787a74658485db8ee) --- emulation/rocjitsu/CONTRIBUTING.md | 24 +- emulation/rocjitsu/docs/style.md | 9 +- emulation/rocjitsu/fuzz/decode/README.md | 2 +- .../rocjitsu/fuzz/decode/decode_fuzz_core.cpp | 14 +- .../lib/python/amdisa/codegen/_generator.py | 367 +- .../tests/test_generator_profile_gates.py | 207 +- .../src/rocjitsu/code/basic_block.cpp | 23 +- .../rocjitsu/src/rocjitsu/code/basic_block.h | 9 +- .../rocjitsu/code/dbt/binary_translator.cpp | 61 +- .../code/dbt/binary_translator_internal.h | 6 +- .../src/rocjitsu/code/patch/instrumentor.cpp | 8 +- .../rocjitsu/code/patch/probe_callable.cpp | 12 +- .../src/rocjitsu/code/patch/probe_clobber.cpp | 10 +- .../rocjitsu/src/rocjitsu/code/rj_code.cpp | 23 +- .../arch/amdgpu/generated/cdna1/decoder.cpp | 3521 ++++++----- .../isa/arch/amdgpu/generated/cdna1/decoder.h | 3 +- .../isa/arch/amdgpu/generated/cdna1/ds.cpp | 766 ++- .../arch/amdgpu/generated/cdna1/encodings.h | 1 + .../isa/arch/amdgpu/generated/cdna1/exp.cpp | 7 +- .../isa/arch/amdgpu/generated/cdna1/flat.cpp | 337 +- .../isa/arch/amdgpu/generated/cdna1/mimg.cpp | 643 +- .../isa/arch/amdgpu/generated/cdna1/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/cdna1/mubuf.cpp | 505 +- .../arch/amdgpu/generated/cdna1/operand.cpp | 1 - .../isa/arch/amdgpu/generated/cdna1/smem.cpp | 577 +- .../isa/arch/amdgpu/generated/cdna1/sop1.cpp | 358 +- .../isa/arch/amdgpu/generated/cdna1/sop2.cpp | 331 +- .../isa/arch/amdgpu/generated/cdna1/sopc.cpp | 126 +- .../isa/arch/amdgpu/generated/cdna1/sopk.cpp | 129 +- .../isa/arch/amdgpu/generated/cdna1/sopp.cpp | 205 +- .../arch/amdgpu/generated/cdna1/vintrp.cpp | 22 +- .../isa/arch/amdgpu/generated/cdna1/vop1.cpp | 844 ++- .../isa/arch/amdgpu/generated/cdna1/vop2.cpp | 639 +- .../isa/arch/amdgpu/generated/cdna1/vop3.cpp | 2767 +++++++-- .../isa/arch/amdgpu/generated/cdna1/vop3p.cpp | 348 +- .../isa/arch/amdgpu/generated/cdna1/vopc.cpp | 2866 ++++++--- .../arch/amdgpu/generated/cdna2/decoder.cpp | 3341 ++++++----- .../isa/arch/amdgpu/generated/cdna2/decoder.h | 3 +- .../isa/arch/amdgpu/generated/cdna2/ds.cpp | 771 ++- .../arch/amdgpu/generated/cdna2/encodings.h | 1 + .../isa/arch/amdgpu/generated/cdna2/flat.cpp | 358 +- .../isa/arch/amdgpu/generated/cdna2/mimg.cpp | 174 +- .../isa/arch/amdgpu/generated/cdna2/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/cdna2/mubuf.cpp | 540 +- .../arch/amdgpu/generated/cdna2/operand.cpp | 1 - .../isa/arch/amdgpu/generated/cdna2/smem.cpp | 577 +- .../isa/arch/amdgpu/generated/cdna2/sop1.cpp | 358 +- .../isa/arch/amdgpu/generated/cdna2/sop2.cpp | 331 +- .../isa/arch/amdgpu/generated/cdna2/sopc.cpp | 126 +- .../isa/arch/amdgpu/generated/cdna2/sopk.cpp | 129 +- .../isa/arch/amdgpu/generated/cdna2/sopp.cpp | 205 +- .../isa/arch/amdgpu/generated/cdna2/vop1.cpp | 811 ++- .../isa/arch/amdgpu/generated/cdna2/vop2.cpp | 639 +- .../isa/arch/amdgpu/generated/cdna2/vop3.cpp | 2731 +++++++-- .../isa/arch/amdgpu/generated/cdna2/vop3p.cpp | 426 +- .../isa/arch/amdgpu/generated/cdna2/vopc.cpp | 2866 ++++++--- .../arch/amdgpu/generated/cdna3/decoder.cpp | 3358 ++++++----- .../isa/arch/amdgpu/generated/cdna3/decoder.h | 3 +- .../isa/arch/amdgpu/generated/cdna3/ds.cpp | 797 ++- .../arch/amdgpu/generated/cdna3/encodings.h | 1 + .../isa/arch/amdgpu/generated/cdna3/flat.cpp | 379 +- .../isa/arch/amdgpu/generated/cdna3/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/cdna3/mubuf.cpp | 518 +- .../arch/amdgpu/generated/cdna3/operand.cpp | 1 - .../isa/arch/amdgpu/generated/cdna3/smem.cpp | 577 +- .../isa/arch/amdgpu/generated/cdna3/sop1.cpp | 358 +- .../isa/arch/amdgpu/generated/cdna3/sop2.cpp | 331 +- .../isa/arch/amdgpu/generated/cdna3/sopc.cpp | 126 +- .../isa/arch/amdgpu/generated/cdna3/sopk.cpp | 129 +- .../isa/arch/amdgpu/generated/cdna3/sopp.cpp | 212 +- .../isa/arch/amdgpu/generated/cdna3/vop1.cpp | 862 ++- .../isa/arch/amdgpu/generated/cdna3/vop2.cpp | 628 +- .../isa/arch/amdgpu/generated/cdna3/vop3.cpp | 2779 +++++++-- .../isa/arch/amdgpu/generated/cdna3/vop3p.cpp | 595 +- .../isa/arch/amdgpu/generated/cdna3/vopc.cpp | 2866 ++++++--- .../arch/amdgpu/generated/cdna4/decoder.cpp | 3647 ++++++----- .../isa/arch/amdgpu/generated/cdna4/decoder.h | 3 +- .../isa/arch/amdgpu/generated/cdna4/ds.cpp | 788 ++- .../arch/amdgpu/generated/cdna4/encodings.h | 1 + .../isa/arch/amdgpu/generated/cdna4/flat.cpp | 379 +- .../isa/arch/amdgpu/generated/cdna4/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/cdna4/mubuf.cpp | 525 +- .../arch/amdgpu/generated/cdna4/operand.cpp | 1 - .../isa/arch/amdgpu/generated/cdna4/smem.cpp | 577 +- .../isa/arch/amdgpu/generated/cdna4/sop1.cpp | 358 +- .../isa/arch/amdgpu/generated/cdna4/sop2.cpp | 331 +- .../isa/arch/amdgpu/generated/cdna4/sopc.cpp | 126 +- .../isa/arch/amdgpu/generated/cdna4/sopk.cpp | 129 +- .../isa/arch/amdgpu/generated/cdna4/sopp.cpp | 212 +- .../isa/arch/amdgpu/generated/cdna4/vop1.cpp | 936 ++- .../isa/arch/amdgpu/generated/cdna4/vop2.cpp | 640 +- .../isa/arch/amdgpu/generated/cdna4/vop3.cpp | 3259 ++++++++-- .../isa/arch/amdgpu/generated/cdna4/vop3p.cpp | 776 ++- .../isa/arch/amdgpu/generated/cdna4/vopc.cpp | 2866 ++++++--- .../arch/amdgpu/generated/cdna5/decoder.cpp | 3984 ++++++------ .../isa/arch/amdgpu/generated/cdna5/decoder.h | 3 +- .../arch/amdgpu/generated/cdna5/encodings.cpp | 108 +- .../arch/amdgpu/generated/cdna5/encodings.h | 184 +- .../arch/amdgpu/generated/cdna5/operand.cpp | 1 - .../isa/arch/amdgpu/generated/cdna5/smem.cpp | 185 +- .../isa/arch/amdgpu/generated/cdna5/sop1.cpp | 642 +- .../isa/arch/amdgpu/generated/cdna5/sop2.cpp | 1263 ++-- .../isa/arch/amdgpu/generated/cdna5/sopc.cpp | 787 ++- .../isa/arch/amdgpu/generated/cdna5/sopk.cpp | 56 +- .../isa/arch/amdgpu/generated/cdna5/sopp.cpp | 283 +- .../arch/amdgpu/generated/cdna5/vbuffer.cpp | 417 +- .../isa/arch/amdgpu/generated/cdna5/vds.cpp | 824 ++- .../isa/arch/amdgpu/generated/cdna5/vflat.cpp | 435 +- .../arch/amdgpu/generated/cdna5/vglobal.cpp | 640 +- .../arch/amdgpu/generated/cdna5/vimage.cpp | 15 +- .../isa/arch/amdgpu/generated/cdna5/vop1.cpp | 1259 +++- .../isa/arch/amdgpu/generated/cdna5/vop2.cpp | 656 +- .../arch/amdgpu/generated/cdna5/vop3_alu.cpp | 2226 +++++-- .../arch/amdgpu/generated/cdna5/vop3_cmp.cpp | 2299 +++++-- .../arch/amdgpu/generated/cdna5/vop3_cvt.cpp | 1807 ++++-- .../arch/amdgpu/generated/cdna5/vop3_data.cpp | 467 +- .../arch/amdgpu/generated/cdna5/vop3_misc.cpp | 191 +- .../amdgpu/generated/cdna5/vop3_ternary.cpp | 929 ++- .../isa/arch/amdgpu/generated/cdna5/vop3p.cpp | 1971 ++++-- .../arch/amdgpu/generated/cdna5/vopc_cmp.cpp | 976 ++- .../arch/amdgpu/generated/cdna5/vopc_cmpx.cpp | 994 ++- .../isa/arch/amdgpu/generated/cdna5/vopd.cpp | 53 +- .../isa/arch/amdgpu/generated/cdna5/vopd.h | 3 + .../arch/amdgpu/generated/cdna5/vscratch.cpp | 172 +- .../arch/amdgpu/generated/rdna1/decoder.cpp | 3409 ++++++----- .../isa/arch/amdgpu/generated/rdna1/decoder.h | 3 +- .../isa/arch/amdgpu/generated/rdna1/ds.cpp | 766 ++- .../arch/amdgpu/generated/rdna1/encodings.h | 1 + .../isa/arch/amdgpu/generated/rdna1/exp.cpp | 7 +- .../isa/arch/amdgpu/generated/rdna1/flat.cpp | 379 +- .../isa/arch/amdgpu/generated/rdna1/mimg.cpp | 895 ++- .../isa/arch/amdgpu/generated/rdna1/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/rdna1/mubuf.cpp | 526 +- .../arch/amdgpu/generated/rdna1/operand.cpp | 1 - .../isa/arch/amdgpu/generated/rdna1/smem.cpp | 136 +- .../isa/arch/amdgpu/generated/rdna1/sop1.cpp | 435 +- .../isa/arch/amdgpu/generated/rdna1/sop2.cpp | 317 +- .../isa/arch/amdgpu/generated/rdna1/sopc.cpp | 113 +- .../isa/arch/amdgpu/generated/rdna1/sopk.cpp | 170 +- .../isa/arch/amdgpu/generated/rdna1/sopp.cpp | 243 +- .../arch/amdgpu/generated/rdna1/vintrp.cpp | 22 +- .../isa/arch/amdgpu/generated/rdna1/vop1.cpp | 1121 +++- .../isa/arch/amdgpu/generated/rdna1/vop2.cpp | 666 ++- .../isa/arch/amdgpu/generated/rdna1/vop3.cpp | 2693 +++++++-- .../isa/arch/amdgpu/generated/rdna1/vop3p.cpp | 189 +- .../isa/arch/amdgpu/generated/rdna1/vopc.cpp | 3134 +++++++--- .../arch/amdgpu/generated/rdna2/decoder.cpp | 3384 ++++++----- .../isa/arch/amdgpu/generated/rdna2/decoder.h | 3 +- .../isa/arch/amdgpu/generated/rdna2/ds.cpp | 766 ++- .../arch/amdgpu/generated/rdna2/encodings.h | 1 + .../isa/arch/amdgpu/generated/rdna2/exp.cpp | 7 +- .../isa/arch/amdgpu/generated/rdna2/flat.cpp | 379 +- .../isa/arch/amdgpu/generated/rdna2/mimg.cpp | 909 ++- .../isa/arch/amdgpu/generated/rdna2/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/rdna2/mubuf.cpp | 533 +- .../arch/amdgpu/generated/rdna2/operand.cpp | 1 - .../isa/arch/amdgpu/generated/rdna2/smem.cpp | 95 +- .../isa/arch/amdgpu/generated/rdna2/sop1.cpp | 435 +- .../isa/arch/amdgpu/generated/rdna2/sop2.cpp | 317 +- .../isa/arch/amdgpu/generated/rdna2/sopc.cpp | 113 +- .../isa/arch/amdgpu/generated/rdna2/sopk.cpp | 170 +- .../isa/arch/amdgpu/generated/rdna2/sopp.cpp | 237 +- .../arch/amdgpu/generated/rdna2/vintrp.cpp | 22 +- .../isa/arch/amdgpu/generated/rdna2/vop1.cpp | 1121 +++- .../isa/arch/amdgpu/generated/rdna2/vop2.cpp | 612 +- .../isa/arch/amdgpu/generated/rdna2/vop3.cpp | 2667 +++++++-- .../isa/arch/amdgpu/generated/rdna2/vop3p.cpp | 189 +- .../isa/arch/amdgpu/generated/rdna2/vopc.cpp | 3134 +++++++--- .../arch/amdgpu/generated/rdna3/decoder.cpp | 3314 +++++----- .../isa/arch/amdgpu/generated/rdna3/decoder.h | 3 +- .../isa/arch/amdgpu/generated/rdna3/ds.cpp | 797 ++- .../arch/amdgpu/generated/rdna3/encodings.cpp | 10 - .../arch/amdgpu/generated/rdna3/encodings.h | 28 + .../isa/arch/amdgpu/generated/rdna3/exp.cpp | 7 +- .../isa/arch/amdgpu/generated/rdna3/flat.cpp | 363 +- .../arch/amdgpu/generated/rdna3/ldsdir.cpp | 15 +- .../isa/arch/amdgpu/generated/rdna3/mimg.cpp | 587 +- .../isa/arch/amdgpu/generated/rdna3/mtbuf.cpp | 120 +- .../isa/arch/amdgpu/generated/rdna3/mubuf.cpp | 519 +- .../arch/amdgpu/generated/rdna3/operand.cpp | 1 - .../isa/arch/amdgpu/generated/rdna3/smem.cpp | 78 +- .../isa/arch/amdgpu/generated/rdna3/sop1.cpp | 434 +- .../isa/arch/amdgpu/generated/rdna3/sop2.cpp | 326 +- .../isa/arch/amdgpu/generated/rdna3/sopc.cpp | 113 +- .../isa/arch/amdgpu/generated/rdna3/sopk.cpp | 156 +- .../isa/arch/amdgpu/generated/rdna3/sopp.cpp | 256 +- .../arch/amdgpu/generated/rdna3/vinterp.cpp | 44 +- .../isa/arch/amdgpu/generated/rdna3/vop1.cpp | 1011 +++- .../isa/arch/amdgpu/generated/rdna3/vop2.cpp | 511 +- .../isa/arch/amdgpu/generated/rdna3/vop3.cpp | 5173 +++++++++++++--- .../isa/arch/amdgpu/generated/rdna3/vop3p.cpp | 563 +- .../isa/arch/amdgpu/generated/rdna3/vopc.cpp | 2321 +++++-- .../isa/arch/amdgpu/generated/rdna3/vopd.cpp | 24 +- .../isa/arch/amdgpu/generated/rdna3/vopd.h | 3 + .../arch/amdgpu/generated/rdna3_5/decoder.cpp | 3455 ++++++----- .../arch/amdgpu/generated/rdna3_5/decoder.h | 3 +- .../isa/arch/amdgpu/generated/rdna3_5/ds.cpp | 797 ++- .../amdgpu/generated/rdna3_5/encodings.cpp | 10 - .../arch/amdgpu/generated/rdna3_5/encodings.h | 28 + .../isa/arch/amdgpu/generated/rdna3_5/exp.cpp | 7 +- .../arch/amdgpu/generated/rdna3_5/flat.cpp | 363 +- .../arch/amdgpu/generated/rdna3_5/ldsdir.cpp | 15 +- .../arch/amdgpu/generated/rdna3_5/mimg.cpp | 587 +- .../arch/amdgpu/generated/rdna3_5/mtbuf.cpp | 120 +- .../arch/amdgpu/generated/rdna3_5/mubuf.cpp | 561 +- .../arch/amdgpu/generated/rdna3_5/operand.cpp | 1 - .../arch/amdgpu/generated/rdna3_5/smem.cpp | 91 +- .../arch/amdgpu/generated/rdna3_5/sop1.cpp | 525 +- .../arch/amdgpu/generated/rdna3_5/sop2.cpp | 417 +- .../arch/amdgpu/generated/rdna3_5/sopc.cpp | 281 +- .../arch/amdgpu/generated/rdna3_5/sopk.cpp | 156 +- .../arch/amdgpu/generated/rdna3_5/sopp.cpp | 256 +- .../arch/amdgpu/generated/rdna3_5/vinterp.cpp | 44 +- .../arch/amdgpu/generated/rdna3_5/vop1.cpp | 1011 +++- .../arch/amdgpu/generated/rdna3_5/vop2.cpp | 511 +- .../arch/amdgpu/generated/rdna3_5/vop3.cpp | 5173 +++++++++++++--- .../arch/amdgpu/generated/rdna3_5/vop3p.cpp | 563 +- .../arch/amdgpu/generated/rdna3_5/vopc.cpp | 2321 +++++-- .../arch/amdgpu/generated/rdna3_5/vopd.cpp | 24 +- .../isa/arch/amdgpu/generated/rdna3_5/vopd.h | 3 + .../arch/amdgpu/generated/rdna4/decoder.cpp | 3853 +++++++----- .../isa/arch/amdgpu/generated/rdna4/decoder.h | 3 +- .../arch/amdgpu/generated/rdna4/encodings.cpp | 10 - .../arch/amdgpu/generated/rdna4/encodings.h | 28 + .../arch/amdgpu/generated/rdna4/operand.cpp | 1 - .../isa/arch/amdgpu/generated/rdna4/smem.cpp | 185 +- .../isa/arch/amdgpu/generated/rdna4/sop1.cpp | 551 +- .../isa/arch/amdgpu/generated/rdna4/sop2.cpp | 465 +- .../isa/arch/amdgpu/generated/rdna4/sopc.cpp | 281 +- .../isa/arch/amdgpu/generated/rdna4/sopk.cpp | 56 +- .../isa/arch/amdgpu/generated/rdna4/sopp.cpp | 274 +- .../arch/amdgpu/generated/rdna4/vbuffer.cpp | 654 +- .../isa/arch/amdgpu/generated/rdna4/vds.cpp | 792 ++- .../arch/amdgpu/generated/rdna4/vdsdir.cpp | 15 +- .../arch/amdgpu/generated/rdna4/vexport.cpp | 7 +- .../isa/arch/amdgpu/generated/rdna4/vflat.cpp | 386 +- .../arch/amdgpu/generated/rdna4/vglobal.cpp | 465 +- .../arch/amdgpu/generated/rdna4/vimage.cpp | 234 +- .../arch/amdgpu/generated/rdna4/vinterp.cpp | 44 +- .../isa/arch/amdgpu/generated/rdna4/vop1.cpp | 1065 +++- .../isa/arch/amdgpu/generated/rdna4/vop2.cpp | 564 +- .../isa/arch/amdgpu/generated/rdna4/vop3.cpp | 5322 ++++++++++++++--- .../isa/arch/amdgpu/generated/rdna4/vop3p.cpp | 961 ++- .../isa/arch/amdgpu/generated/rdna4/vopc.cpp | 1969 +++++- .../isa/arch/amdgpu/generated/rdna4/vopd.cpp | 24 +- .../isa/arch/amdgpu/generated/rdna4/vopd.h | 3 + .../arch/amdgpu/generated/rdna4/vsample.cpp | 408 +- .../arch/amdgpu/generated/rdna4/vscratch.cpp | 172 +- .../src/rocjitsu/isa/arch/risc_v/decoder.h | 10 +- .../rocjitsu/src/rocjitsu/isa/decode_result.h | 18 + .../lib/rocjitsu/src/rocjitsu/isa/decoder.cpp | 35 +- .../lib/rocjitsu/src/rocjitsu/isa/decoder.h | 34 +- .../rocjitsu/src/rocjitsu/isa/instruction.h | 7 + .../lib/rocjitsu/src/rocjitsu/isa/operand.cpp | 20 +- .../lib/rocjitsu/src/rocjitsu/isa/operand.h | 10 +- .../rocjitsu/src/rocjitsu/isa/rj_decode.cpp | 6 +- .../src/rocjitsu/vm/amdgpu/compute_unit.cpp | 19 +- .../rocjitsu/lib/util/include/util/result.h | 2 + .../rocjitsu/tests/analysis/liveness_test.cpp | 227 +- .../rocjitsu/tests/buffer_operand_test.cpp | 5 +- .../tests/cdna3_predicate_mask_test.cpp | 3 +- .../tests/cdna5_architecture_test.cpp | 87 +- .../rocjitsu/tests/cdna5_execution_test.cpp | 45 +- .../rocjitsu/tests/cdna5_instruction_test.cpp | 35 +- .../rocjitsu/tests/cdna5_sim_test_common.h | 3 +- .../rocjitsu/tests/cdna5_tensor_dma_test.cpp | 5 +- .../tests/check_model_only_symbols.cmake | 2 +- .../tests/check_narrow_registry_symbols.cmake | 2 +- .../code/relocation_function_table_test.cpp | 9 +- .../tests/dbi/hsa_dbi_nop_asm_test.cpp | 8 +- .../tests/dbi/hsa_dbi_nop_probe_test.cpp | 13 +- .../rocjitsu/tests/dbi/probe_fixture_test.cpp | 4 +- .../dbt/device_kernels_translate_tests.cpp | 34 +- .../dbt/multikernel_indirect_branch_test.cpp | 9 +- .../relocation_function_table_hip_test.cpp | 3 +- .../tests/dbt/semantic_scratch_test.cpp | 5 +- .../dbt/support/translate_test_support.cpp | 3 +- .../tests/dbt/translate_gfx1250_test.cpp | 28 +- .../rocjitsu/tests/dbt/translate_test.cpp | 30 +- .../tests/decode_execute_benchmark.cpp | 7 +- .../rocjitsu/tests/decode_smoke_test.cpp | 160 +- emulation/rocjitsu/tests/decode_test_util.h | 58 + .../rocjitsu/tests/decoder_c_api_test.cpp | 3 +- .../rocjitsu/tests/execution_plugin_test.cpp | 41 +- .../tests/fixtures/downstream_isa_fixture.h | 3 +- .../instruction_execution_harness_test.cpp | 281 +- .../tests/isa_registry_composition_test.cpp | 3 +- .../tests/isa_target_registry_test.cpp | 14 +- emulation/rocjitsu/tests/matmul_test.cpp | 3 +- .../rocjitsu/tests/model_only_isa_test.cpp | 5 +- .../tests/patch/instrumentor_test.cpp | 5 +- .../tests/patch/probe_callable_test.cpp | 12 + .../tests/patch/probe_clobber_test.cpp | 8 + .../tests/patch/spill_manager_test.cpp | 5 +- .../tests/pseudo_scalar_exec_test.cpp | 23 +- emulation/rocjitsu/tests/scalar_scc_test.cpp | 7 +- .../rocjitsu/tests/shared_infra_test.cpp | 118 +- .../vop1_cvt_f64_scalar_correctness_test.cpp | 3 +- .../vop1_cvt_f64_simd_correctness_test.cpp | 3 +- .../vop1_cvt_f8_simd_correctness_test.cpp | 3 +- .../vop1_f64_simd_correctness_test.cpp | 3 +- .../vop1_simd_correctness_test.cpp | 3 +- .../vop2_carry_simd_correctness_test.cpp | 3 +- .../vop2_cndmask_simd_correctness_test.cpp | 3 +- ...op2_fma_f16_rdna_simd_correctness_test.cpp | 3 +- .../vop2_fma_f64_simd_correctness_test.cpp | 5 +- .../vop2_fma_simd_correctness_test.cpp | 3 +- .../vop2_minmax_simd_correctness_test.cpp | 3 +- .../vop2_simd_correctness_test.cpp | 3 +- .../vop3_b16_rdna_simd_correctness_test.cpp | 9 +- .../vop3_binary_simd_correctness_test.cpp | 5 +- .../vop3_carry_simd_correctness_test.cpp | 5 +- ...op3_cndmask_pack_simd_correctness_test.cpp | 7 +- .../vop3_cvt_f64_simd_correctness_test.cpp | 3 +- .../vop3_cvt_pk_f32_rdna_correctness_test.cpp | 9 +- ...vop3_div_helpers_simd_correctness_test.cpp | 15 +- .../vop3_fmac_simd_correctness_test.cpp | 5 +- ...6_transcendental_simd_correctness_test.cpp | 3 +- .../vop3_fp16_unary_simd_correctness_test.cpp | 3 +- .../vop3_fp64_simd_correctness_test.cpp | 3 +- ...int_binary_extra_simd_correctness_test.cpp | 3 +- ...widening_ternary_simd_correctness_test.cpp | 5 +- .../vop3_ldexp_simd_correctness_test.cpp | 3 +- .../vop3_shift64_scalar_correctness_test.cpp | 3 +- .../vop3_shift64_simd_correctness_test.cpp | 7 +- .../vop3_ternary_fp_simd_correctness_test.cpp | 3 +- ...vop3_ternary_int_simd_correctness_test.cpp | 3 +- .../vop3_unary_simd_correctness_test.cpp | 5 +- .../vop3p_dot_simd_correctness_test.cpp | 5 +- .../vop3p_fma_mix_simd_correctness_test.cpp | 3 +- .../vop3p_mov_b32_simd_correctness_test.cpp | 7 +- ...p_pk_binary_fp16_simd_correctness_test.cpp | 3 +- ...3p_pk_binary_int_simd_correctness_test.cpp | 3 +- .../vop_alias_rdna_simd_correctness_test.cpp | 3 +- ...vopc_cmp_class_scalar_correctness_test.cpp | 3 +- .../vopc_cmp_class_simd_correctness_test.cpp | 5 +- .../vopc_simd_correctness_test.cpp | 3 +- .../vopc_vop3_fp16_simd_correctness_test.cpp | 3 +- .../vopc_vop3_fp32_simd_correctness_test.cpp | 3 +- .../vopc_vop3_fp64_simd_correctness_test.cpp | 3 +- .../vopc_vop3_int_simd_correctness_test.cpp | 3 +- .../tests/smem_sbase_operand_test.cpp | 3 +- emulation/rocjitsu/tests/util_result_test.cpp | 11 + .../rocjitsu/tests/v_add_simd_benchmark.cpp | 3 +- emulation/rocjitsu/tests/vector_add_test.cpp | 3 +- emulation/rocjitsu/tools/CMakeLists.txt | 7 + emulation/rocjitsu/tools/dbt_translate.cpp | 46 +- .../rocjitsu/tools/rj_decode_benchmark.cpp | 310 + 348 files changed, 130303 insertions(+), 39737 deletions(-) create mode 100644 emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decode_result.h create mode 100644 emulation/rocjitsu/tests/decode_test_util.h create mode 100644 emulation/rocjitsu/tools/rj_decode_benchmark.cpp diff --git a/emulation/rocjitsu/CONTRIBUTING.md b/emulation/rocjitsu/CONTRIBUTING.md index 1f4d481d06b1..e6487611f87c 100644 --- a/emulation/rocjitsu/CONTRIBUTING.md +++ b/emulation/rocjitsu/CONTRIBUTING.md @@ -49,8 +49,11 @@ Before writing new infrastructure, check these existing libraries: - **Intrusive list** — `util/intrusive_list.h` for linked data structures that need O(1) insert/erase without heap allocation per node. - **Arena allocator** — `util/arena_alloc.h` for fixed-size block pools. -- **Exceptions** — `util/except.h` for `InvalidInst`, `UnimplementedInst`, - `ConfigError`. +- **Expected failures** — Return `Result` or `FailureOr` and accept a + `DiagnosticEmitter` when the caller needs a reason. Its sink is non-owning + and must not outlive its callable. +- **Exceptions** — `util/except.h` for unrecoverable initialization, + configuration, and execution failures. - **Register sets** — `isa/register_set.h` for ISA-independent register file modeling (SGPR/VGPR/AccVGPR bitsets). - **Spill manager** — `code/patch/spill_manager.h` for scratch layout @@ -88,16 +91,13 @@ Before writing new infrastructure, check these existing libraries: `stderr` — it runs inside another runtime's `OnLoad`, its messages must survive a log-groups-OFF build, and its signal-backtrace path must stay async-signal-safe (`rj_hsa_dbt_hooks.cpp` uses raw `::write`). -- **Exceptions.** Exceptions are used only for unrecoverable errors - during initialization and configuration (`ConfigError`) or when - encountering invalid/unimplemented instructions during code object - parsing (`InvalidInst`, `UnimplementedInst`). All exception types - live in `util/except.h`. Do not throw exceptions in simulation hot - paths (event handlers, instruction execution, cache lookups). Do not - add `try`/`catch` blocks unless you are at a boundary that must - translate an error (e.g., the C API layer). There is no general - exception safety guarantee — assume code is not exception-safe - unless explicitly documented. +- **Errors.** Expected failures such as a rejected instruction encoding return + `Result` or `FailureOr` and optionally emit a diagnostic. Exceptions are + reserved for unrecoverable initialization, configuration, or execution + failures. Do not throw exceptions in simulation hot paths (event handlers, + instruction execution, cache lookups). Do not add `try`/`catch` blocks unless + you are at a boundary that must translate an error (e.g., the C API layer). + There is no general exception safety guarantee unless explicitly documented. ## ISA codegen workflow diff --git a/emulation/rocjitsu/docs/style.md b/emulation/rocjitsu/docs/style.md index 62582918a63d..729164718650 100644 --- a/emulation/rocjitsu/docs/style.md +++ b/emulation/rocjitsu/docs/style.md @@ -148,10 +148,11 @@ Foo foo = static_cast(bar); // OK but could use auto instead to avoid repet ## Error Handling -- Exceptions are only for unrecoverable errors: initialization/configuration - failures (`ConfigError`) and invalid or unimplemented instructions during - code-object parsing (`InvalidInst`, `UnimplementedInst`). All exception types - live in `util/except.h`. +- Expected failures such as a rejected instruction encoding return `Result` or + `FailureOr`. Accept a `DiagnosticEmitter` when the caller needs the reason; + its sink is non-owning and must not outlive its callable. +- Exceptions are only for unrecoverable initialization, configuration, or + execution failures. Exception types live in `util/except.h`. - Do not throw in simulation hot paths (event handlers, instruction execution, cache lookups). - Do not add `try`/`catch` except at a boundary that must translate an error diff --git a/emulation/rocjitsu/fuzz/decode/README.md b/emulation/rocjitsu/fuzz/decode/README.md index ae0845ff2c25..22c46e1e11ca 100644 --- a/emulation/rocjitsu/fuzz/decode/README.md +++ b/emulation/rocjitsu/fuzz/decode/README.md @@ -77,7 +77,7 @@ ninja -C build-decode-afl rj_decode_fuzz build-decode-afl/fuzz/decode/rj_decode_fuzz --afl --target gfx1250 ``` -`InvalidInst` is an ordinary rejection. Other exceptions, signals, sanitizer +Decoder failure is an ordinary rejection. Exceptions from unrelated failures, signals, sanitizer findings, and decoder invariant failures remain crashes for AFL++ to retain. ## Offline LLVM comparison diff --git a/emulation/rocjitsu/fuzz/decode/decode_fuzz_core.cpp b/emulation/rocjitsu/fuzz/decode/decode_fuzz_core.cpp index 5e4b7530f5a6..9e49cc73d9ca 100644 --- a/emulation/rocjitsu/fuzz/decode/decode_fuzz_core.cpp +++ b/emulation/rocjitsu/fuzz/decode/decode_fuzz_core.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/instruction.h" #include "rocjitsu/isa/operand.h" #include "rocjitsu/isa/target_registry.h" -#include "util/except.h" #include #include @@ -91,17 +90,14 @@ DecodeRecord decode_window(Decoder &decoder, std::span bytes) { words[word] |= static_cast(bytes[word * sizeof(uint32_t) + byte]) << (byte * 8); } - std::unique_ptr inst; - try { - inst.reset(decoder.decode(words.data())); - } catch (const util::InvalidInst &error) { + util::StringDiagnostic rejection; + DecodeResult decoded = decoder.decode(words.data(), rejection.emitter()); + if (decoded.failed()) { DecodeRecord record; - record.rejection = error.what(); + record.rejection = rejection.message(); return record; } - - if (!inst) - fail_invariant("a successful decode returned null"); + std::unique_ptr inst = std::move(decoded).value(); const int size = inst->size(); if (size != 4 && size != 8 && size != 12 && size != 16) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 0b1c4fe3467f..16a7c6c6c9bb 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -1942,6 +1942,7 @@ def opcode_mask(name: str, opcodes: frozenset[int]) -> str: vopd3_execute_slot_cases = '' vopd3_constructor_branch = '' vopd3_constructor_close = '' + vopd3_validation_branch = '' vopd3_init_operands_prefix = '' vopd3_init_operands_suffix = '' vopdxy_bits_decl = cpp_block(''' @@ -2038,14 +2039,8 @@ def opcode_mask(name: str, opcodes: frozenset[int]) -> str: word2_ = words[2]; opx_ = static_cast((word0_ >> 18) & 0x3F); opy_ = static_cast((word0_ >> 12) & 0x3F); - if (!is_valid_opcode(opx_, kVopd3XOpcodeMask)) - throw util::InvalidInst("invalid VOPD3 X opcode", ""); - if (!is_valid_opcode(opy_, kVopd3YOpcodeMask)) - throw util::InvalidInst("invalid VOPD3 Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); - if (srcx0 == 254 || srcx0 == 255 || srcy0 == 254 || srcy0 == 255) - throw util::InvalidInst("VOPD3 does not support literal selectors", ""); negx_ = static_cast((word1_ >> 9) & 0x7); negy_ = static_cast((word1_ >> 12) & 0x7); uint16_t vsrcx1 = static_cast((word1_ >> 16) & 0xFF); @@ -2057,10 +2052,6 @@ def opcode_mask(name: str, opcodes: frozenset[int]) -> str: uint32_t x_bits = is_float64_op(opx_) ? 64 : 32; uint32_t y_bits = is_float64_op(opy_) ? 64 : 32; - const uint32_t x_end = vdstx + x_bits / 32; - const uint32_t y_end = vdsty + y_bits / 32; - if (vdstx < y_end && vdsty < x_end) - throw util::InvalidInst("VOPD3 destination ranges overlap", ""); dstx_ = Operand(x_bits, OperandType::OPR_VGPR, vdstx); dsty_ = Operand(y_bits, OperandType::OPR_VGPR, vdsty); srcx0_ = make_src0(x_bits, true, false, 0, srcx0); @@ -2076,6 +2067,31 @@ def opcode_mask(name: str, opcodes: frozenset[int]) -> str: vopd3_constructor_branch = vopd3_constructor_branch.replace( '@VOPD3_PREFIX_SHIFT@', str(32 - vopd3_prefix.prefix_bits) ).replace('@VOPD3_PREFIX@', f'0x{vopd3_prefix.prefix:X}') + vopd3_validation_branch = cpp_block(''' + if ((word0 >> @VOPD3_PREFIX_SHIFT@) == @VOPD3_PREFIX@) { + const uint16_t opx = static_cast((word0 >> 18) & 0x3F); + const uint16_t opy = static_cast((word0 >> 12) & 0x3F); + if (!is_valid_opcode(opx, kVopd3XOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD3 X opcode"; + if (!is_valid_opcode(opy, kVopd3YOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD3 Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcx0 == 255 || srcy0 == 254 || srcy0 == 255) [[unlikely]] + return emit_error.emit() << "VOPD3 does not support literal selectors"; + const uint32_t word2 = words[2]; + const uint16_t vdstx = static_cast(word2 & 0xFF); + const uint16_t vdsty = static_cast((word2 >> 24) & 0xFF); + const uint32_t x_end = vdstx + (is_float64_op(opx) ? 2 : 1); + const uint32_t y_end = vdsty + (is_float64_op(opy) ? 2 : 1); + if (vdstx < y_end && vdsty < x_end) [[unlikely]] + return emit_error.emit() << "VOPD3 destination ranges overlap"; + return Result::success(); + } + ''') + vopd3_validation_branch = vopd3_validation_branch.replace( + '@VOPD3_PREFIX_SHIFT@', str(32 - vopd3_prefix.prefix_bits) + ).replace('@VOPD3_PREFIX@', f'0x{vopd3_prefix.prefix:X}') vopd3_constructor_close = ' }' vopd3_init_operands_prefix = cpp_block(''' const bool vopd3 = format_ == Format::Vopd3; @@ -2165,6 +2181,7 @@ def opcode_mask(name: str, opcodes: frozenset[int]) -> str: #include "@GENERATED_ARCH@/encodings.h" #include "@GENERATED_ARCH@/operand.h" + #include "rocjitsu/isa/decode_result.h" #include #include @@ -2175,6 +2192,8 @@ class Vopd : public IsaInstruction { public: explicit Vopd(const MachineInst *inst); + static Result validate_encoding(const MachineInst *inst, + const util::DiagnosticEmitter &emit_error); void execute_impl(amdgpu::Wavefront &wf); private: @@ -2345,6 +2364,26 @@ class Vopd : public IsaInstruction @INLINE_EXECUTION_HELPERS@ + Result + Vopd::validate_encoding(const MachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto *words = reinterpret_cast(inst); + const uint32_t word0 = words[0]; + const uint32_t word1 = words[1]; + @VOPD3_VALIDATION_BRANCH@ + const uint16_t opx = static_cast((word0 >> 22) & 0xF); + const uint16_t opy = static_cast((word0 >> 17) & 0x1F); + if (!is_valid_opcode(opx, kVopdXOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD X opcode"; + if (!is_valid_opcode(opy, kVopdYOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcy0 == 254) [[unlikely]] + return emit_error.emit() << "VOPD does not support 64-bit literals"; + return Result::success(); + } + Vopd::Vopd(const MachineInst *inst) : IsaInstruction("vopd", @VOPD_EXEC_FN@), dstx_(32, OperandType::OPR_VGPR, 0), @@ -2365,16 +2404,10 @@ class Vopd : public IsaInstruction encoding_id_ = @VOPD_PREFIX@; opx_ = static_cast((word0_ >> 22) & 0xF); opy_ = static_cast((word0_ >> 17) & 0x1F); - if (!is_valid_opcode(opx_, kVopdXOpcodeMask)) - throw util::InvalidInst("invalid VOPD X opcode", ""); - if (!is_valid_opcode(opy_, kVopdYOpcodeMask)) - throw util::InvalidInst("invalid VOPD Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t vsrcx1 = static_cast((word0_ >> 9) & 0xFF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); uint16_t vsrcy1 = static_cast((word1_ >> 9) & 0xFF); - if (srcx0 == 254 || srcy0 == 254) - throw util::InvalidInst("VOPD does not support 64-bit literals", ""); uint16_t vdstx = static_cast((word1_ >> 24) & 0xFF); uint16_t vdsty_hi = static_cast((word1_ >> 17) & 0x7F); uint16_t vdsty = static_cast((vdsty_hi << 1) | ((~vdstx) & 1u)); @@ -2503,6 +2536,7 @@ class Vopd : public IsaInstruction .replace('@VOPD3_UNUSED_ATTR@', vopd3_unused_attr) .replace('@VOPD_OP_NAME_CASES@', vopd_op_name_cases) .replace('@VOPD3_MODEL_HELPERS@', vopd3_model_helpers) + .replace('@VOPD3_VALIDATION_BRANCH@', vopd3_validation_branch) .replace('@VOPD3_CONSTRUCTOR_BRANCH@', vopd3_constructor_branch) .replace('@VOPD3_CONSTRUCTOR_CLOSE@', vopd3_constructor_close) .replace('@VOPD_PREFIX@', f'0x{vopd_prefix.prefix:X}') @@ -2680,7 +2714,6 @@ def gen_encodings(self) -> None: enc_classes = [] class_func_impls = [] cond_emitted: set[str] = set() - needs_invalid_inst_include = False for inst_enc in self.isa_spec.inst_encodings: if not inst_enc.insts: continue @@ -2696,8 +2729,6 @@ def gen_encodings(self) -> None: self._supports_simm64_literal_operands() and bool(encoded_literal_fields) ) - if uses_instruction_literal_policy: - needs_invalid_inst_include = True unsupported_literal64_fields = self._unsupported_literal64_selector_fields( inst_enc ) @@ -2730,21 +2761,6 @@ def gen_encodings(self) -> None: ), cgen.Value('ExecuteFn', 'exec_fn'), ] - if uses_instruction_literal_policy: - constructor_args.extend( - [ - cgen.Value( - 'LiteralSupport', - 'literal_support = LiteralSupport::Both', - ), - cgen.Value( - 'int', - 'num_encoded_sources = ' f'{len(encoded_literal_fields)}', - ), - ] - ) - elif unsupported_literal64_fields: - constructor_args.append(cgen.Value('int', 'num_encoded_sources = 3')) if supports_fixed_size_embedding: constructor_args.append( cgen.Value( @@ -2763,6 +2779,25 @@ def gen_encodings(self) -> None: constructor_args, ) ) + validation_args = [ + '[[maybe_unused]] std::string_view mnemonic', + f'const {inst_enc.fmt_enc_name}MachineInst *inst', + 'const util::DiagnosticEmitter &emit_error', + ] + if uses_instruction_literal_policy: + validation_args.extend( + [ + 'LiteralSupport literal_support = LiteralSupport::Both', + f'int num_encoded_sources = {len(encoded_literal_fields)}', + ] + ) + elif unsupported_literal64_fields: + validation_args.append('int num_encoded_sources = 3') + if supports_fixed_size_embedding: + validation_args.append( + 'ExtensionDecodePolicy extension_policy = ' + 'ExtensionDecodePolicy::Decode' + ) # Determine whether the constructor needs a runtime size # check for an extension DWORD beyond the base encoding. # @@ -2836,6 +2871,8 @@ def gen_encodings(self) -> None: ' raw_encoding_ = reinterpret_cast(&inst_);\n' ' encoding_id_ = raw_encoding_[0] >> 23;' ) + validation_body = ' const auto &inst_ = *inst;' + has_encoding_validation = False if has_op: size_line += '\n opcode_ = inst_.op;' literal64_conds = self._literal64_condition_names(inst_enc) @@ -2882,6 +2919,9 @@ def gen_encodings(self) -> None: literal32_condition = ' || '.join(f'{name}()' for name in literal32_conds) if supports_fixed_size_embedding: size_line += ' if (extension_policy == ExtensionDecodePolicy::Decode) {' + validation_body += ( + ' if (extension_policy == ExtensionDecodePolicy::Decode) {' + ) # Some profiles expose SRC_LITERAL64 in their global operand # selector table even when a particular encoding has no 64-bit # literal extension form. Derive the affected source fields from @@ -2891,38 +2931,41 @@ def gen_encodings(self) -> None: # constructor reads two extension DWORDs that the encoding does # not own. if unsupported_literal64_fields: + has_encoding_validation = True reject_condition = ' || '.join( f'(num_encoded_sources > {source_idx} && inst_.{field} == 254)' for source_idx, field in enumerate(unsupported_literal64_fields) ) - size_line += ( + validation_body += ( f'\n if ({reject_condition})' - f' throw util::InvalidInst("{inst_enc.fmt_enc_name} does not support ' - 'Literal64", "");' + f' [[unlikely]] return emit_error.emit() << "{inst_enc.fmt_enc_name} does not support ' + 'Literal64";' ) if uses_instruction_literal_policy: + has_encoding_validation = True for width, selector in ((32, 255), (64, 254)): reject_condition = ' || '.join( f'(num_encoded_sources > {source_idx} && ' f'inst_.{field} == {selector})' for source_idx, field in enumerate(encoded_literal_fields) ) - size_line += ( + validation_body += ( f'\n if (!supports_literal(literal_support, ' f'LiteralSupport::Literal{width}) && ({reject_condition}))' - ' throw util::InvalidInst(' - f'std::string(mnemonic) + " does not support {width}-bit literals", "");' + f' [[unlikely]] return emit_error.emit() << mnemonic << " does not support {width}-bit literals";' ) if needs_explicit_dpp_size and encoded_literal_fields: + has_encoding_validation = True dpp_extension_condition = ' || '.join(dpp_extension_conditions) - literal_selector_condition = literal32_condition or 'false' - size_line += ( + literal_selector_condition = ' || '.join( + f'inst_.{field} == 255' for field in encoded_literal_fields + ) + validation_body += ( f' if (({dpp_extension_condition}) && ' f'({literal_selector_condition}))' - ' throw util::InvalidInst(' - '"DPP and literal operands cannot be combined", "");' + ' [[unlikely]] return emit_error.emit() << ' + '"DPP and literal operands cannot be combined";' ) - needs_invalid_inst_include = True # Size owned storage from this encoding's declared extension forms, # not the architecture-wide operand selector table. For example, # gfx1250 defines selector 254 for 64-bit literals, but the 64-bit @@ -3026,13 +3069,17 @@ def gen_encodings(self) -> None: ) if supports_fixed_size_embedding: size_line += ' }' - constructor_extra_params = '' - if uses_instruction_literal_policy: - constructor_extra_params += ( - ', LiteralSupport literal_support, int num_encoded_sources' + validation_body += ' }' + validation_body += ' return Result::success();' + if has_encoding_validation: + public_members.append( + cgen.Line( + 'static Result validate_encoding(' + + ', '.join(validation_args) + + f') {{{validation_body}}}' + ) ) - elif unsupported_literal64_fields: - constructor_extra_params += ', int num_encoded_sources' + constructor_extra_params = '' if supports_fixed_size_embedding: constructor_extra_params += ', ExtensionDecodePolicy extension_policy' if rule.use_flat_mnemonic: @@ -3056,7 +3103,6 @@ def gen_encodings(self) -> None: f'{{{size_line}}}' ) class_func_impls.append(cgen.Line(class_ctor_impl)) - # Generate build_modifiers() override for encoding bases # that have modifier flags (memory instructions). This is # called lazily by disassemble() instead of eagerly in the @@ -3402,6 +3448,7 @@ def gen_encodings(self) -> None: False, ), ('rocjitsu/isa/instruction.h', False), + ('rocjitsu/isa/decode_result.h', False), (encoding_helper_header, False), ('array', True), ('cstdint', True), @@ -3448,14 +3495,6 @@ def gen_encodings(self) -> None: _enc_cpp_includes.insert( 1, ('rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h', False) ) - if needs_invalid_inst_include or ( - self._supports_simm64_literal_operands() - and any( - self._rejects_unencoded_vop3p_literal64(enc) - for enc in self.isa_spec.inst_encodings - ) - ): - _enc_cpp_includes.insert(1, ('util/except.h', False)) class_impl_file = CppFile( 'encodings', self.out_path, @@ -4250,8 +4289,7 @@ def _emit_gfx1250_scaled_wmma_vop3px2_impls(self) -> _ImplOutputs: model = textwrap.dedent('''\ VWmmaScaleF32Vop3px2::VWmmaScaleF32Vop3px2(const MachineInst *inst) : Vop3p(gfx1250_scaled_wmma_mnemonic(inst), reinterpret_cast(inst + 2), - @EXEC_FN@, LiteralSupport::Both, 3, - Vop3p::ExtensionDecodePolicy::Skip), + @EXEC_FN@, Vop3p::ExtensionDecodePolicy::Skip), vdst(gfx1250_scaled_wmma_dst_size_bits(inst), OperandType::OPR_VGPR, reinterpret_cast(inst + 2)->vdst), src0(gfx1250_scaled_wmma_src0_size_bits(inst), OperandType::OPR_SRC_VGPR, @@ -8266,7 +8304,7 @@ def gen_insts(self) -> None: init_list_parts = [ f'{inst.fmt_true_enc_name}({mnemonic_expr}, ' f'reinterpret_cast(inst), ' - f'{exec_fn_expr}{literal_policy_args})' + f'{exec_fn_expr})' ] + opnd_ctor_init init_list = ', '.join(init_list_parts) # Check if this is a memory instruction to set MEMORY_OP flag @@ -8308,6 +8346,8 @@ def gen_insts(self) -> None: ) ctor_body_parts = list(opnd_body) fieldless_caps_guards: dict[str, str] = {} + factory_validation_parts: list[str] = [] + factory_op_encoding = f'{inst.fmt_true_enc_name}::OpEncoding' # Guard fieldless def/use operands (pushed positionally) from # silently writing past the fixed-size operand arrays. The # capacities mirror instruction.h (see the class constants). @@ -8335,16 +8375,17 @@ def gen_insts(self) -> None: opnd.operand_type ) raw_value = ( - f'reinterpret_cast(inst)->{opnd.name}' + f'reinterpret_cast(inst)' + f'->{opnd.name}' ) valid_expr = ' || '.join( f'({raw_value} >= {lo} && {raw_value} <= {hi})' for lo, hi in intervals ) - ctor_body_parts.append( + factory_validation_parts.append( f'if (!({valid_expr})) ' - f'throw util::InvalidInst("{inst.name} has an invalid ' - 'accumulator selector", "");' + f'[[unlikely]] return emit_error.emit() << "{inst.name} has an invalid ' + 'accumulator selector";' ) # LLVM models pseudo-scalar V_S_* destinations as @@ -8358,11 +8399,11 @@ def gen_insts(self) -> None: inst_sem is not None and inst_sem.semantic_class == 'pseudo_scalar_unary' ): - ctor_body_parts.append( - 'if (reinterpret_cast(inst)->vdst >= ' + factory_validation_parts.append( + f'if (reinterpret_cast(inst)->vdst >= ' 'OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) ' - f'throw util::InvalidInst("{inst.name} has an invalid ' - 'SReg_32_XEXEC destination", "");' + f'[[unlikely]] return emit_error.emit() << "{inst.name} has an invalid ' + 'SReg_32_XEXEC destination";' ) # Flat segment-aware operands: adjust addr width and add @@ -8437,20 +8478,20 @@ def gen_insts(self) -> None: and len(_encoded_literal_fields) > 1 ): literal32_selector = ' || '.join( - 'reinterpret_cast(inst)->' + f'reinterpret_cast(inst)->' f'{field} == 255' for field in _encoded_literal_fields ) literal64_selector = ' || '.join( - 'reinterpret_cast(inst)->' + f'reinterpret_cast(inst)->' f'{field} == 254' for field in _encoded_literal_fields ) - ctor_body_parts.append( + factory_validation_parts.append( f'if (({literal32_selector}) && ' f'({literal64_selector})) ' - f'throw util::InvalidInst("{inst.name} may not mix ' - '32-bit and 64-bit literals", "");' + f'[[unlikely]] return emit_error.emit() << "{inst.name} may not mix ' + '32-bit and 64-bit literals";' ) for opnd in inst.operands: # The only fieldless operand that needs a fixup @@ -8676,10 +8717,16 @@ def gen_insts(self) -> None: if len(unsupported_dpp_markers) == 1 else 'DPP' ) - ctor_body_parts.append( - f'if ({" || ".join(marker for marker, _ in unsupported_dpp_markers)}) ' - f'throw util::InvalidInst("{inst.name} does not support ' - f'{unsupported_dpp_label}", "");' + qualified_dpp_markers = [ + marker.replace( + 'OpEncoding', factory_op_encoding + ) + for marker, _ in unsupported_dpp_markers + ] + factory_validation_parts.append( + f'if ({" || ".join(qualified_dpp_markers)}) ' + f'[[unlikely]] return emit_error.emit() << "{inst.name} does not support ' + f'{unsupported_dpp_label}";' ) # SDWA (src0 == amdgpu::SRC_SDWA): CDNA and RDNA1/2 only. _has_sdwa = any( @@ -8798,10 +8845,10 @@ def gen_insts(self) -> None: 'ENC_VOP2', 'ENC_VOPC', ): - ctor_body_parts.append( - 'if (reinterpret_cast(inst)->src0 == ' + factory_validation_parts.append( + f'if (reinterpret_cast(inst)->src0 == ' 'amdgpu::SRC_SDWA) ' - f'throw util::InvalidInst("{inst.name} does not support SDWA", "");' + f'[[unlikely]] return emit_error.emit() << "{inst.name} does not support SDWA";' ) # Apply the fieldless-operand capability policy once, after @@ -9424,11 +9471,31 @@ def _dpp_write_mask_lines( inst_impls = [class_ctor_impl] decoder_factory = decoder_factories.get(inst.fmt_name) if decoder_factory is not None: + factory_mnemonic_expr = mnemonic_expr.replace( + 'OpEncoding', factory_op_encoding + ) + factory_validation_body = ''.join( + f' {line}\n' for line in factory_validation_parts + ) + factory_inst_decl = ( + ' const auto *inst = opcode;\n' + if factory_validation_parts + or '(inst)' in factory_mnemonic_expr + else '' + ) inst_impls.append( cgen.Line( 'namespace detail {\n' - f'std::unique_ptr {decoder_factory}' - '(const MachineInst *opcode) {\n' + f'DecodeResult {decoder_factory}' + '(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) {\n' + f'{factory_inst_decl}' + f' Result validation = {inst.fmt_true_enc_name}::validate_encoding(' + f'{factory_mnemonic_expr}, ' + f'reinterpret_cast(opcode), ' + f'emit_error{literal_policy_args});\n' + ' if (validation.failed()) [[unlikely]]\n' + ' return Result::failure();\n' + f'{factory_validation_body}' f' return std::make_unique<{inst.fmt_name}>(opcode);\n' '}\n' '} // namespace detail' @@ -9935,7 +10002,6 @@ def _delegates_to_shared(i: Instruction) -> bool: ), False, ), - ('util/except.h', False), ] if is_mem_enc: model_cpp_includes.extend( @@ -12471,7 +12537,6 @@ def _inert_guard(ret_expr: str = '', cond: str = _inert_cond) -> str: False, ), ('rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h', False), - ('util/except.h', False), ('format', True), ('optional', True), ('stdexcept', True), @@ -12576,8 +12641,11 @@ def gen_decoder(self) -> None: f'static constexpr std::size_t kMaxInstructionWords = {self._max_instruction_word_count()}' ), cgen.FunctionDeclaration( - cgen.Value('static std::unique_ptr', 'decode'), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('static DecodeResult', 'decode'), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ), ], ) @@ -12586,16 +12654,23 @@ def gen_decoder(self) -> None: class_members = [ cgen.Line('public:'), cgen.FunctionDeclaration( - cgen.Value('static std::unique_ptr', 'decode'), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('static DecodeResult', 'decode'), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ), cgen.Line('private:'), cgen.Statement( - 'using DecodeFunc = std::unique_ptr(*)(const MachineInst *)' + 'using DecodeFunc = DecodeResult(*)(const MachineInst *, ' + 'const DecodeErrorEmitter &)' ), cgen.FunctionDeclaration( - cgen.Value('static std::unique_ptr', 'decodeInvalid'), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('static DecodeResult', 'decodeInvalid'), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ), ] decode_body = [] @@ -12608,31 +12683,39 @@ def gen_decoder(self) -> None: cgen.Statement( 'Sop1MachineInst op = std::bit_cast(*opcode)' ), - cgen.Statement('return primary_decode_table[op.encoding](opcode)'), + cgen.Statement( + 'return primary_decode_table[op.encoding](opcode, emit_error)' + ), ] ) decode_table_funcs = [ cgen.FunctionBody( cgen.FunctionDeclaration( - cgen.Value('std::unique_ptr', 'DecoderImpl::decode'), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('DecodeResult', 'DecoderImpl::decode'), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ), cgen.Block(decode_body), ), cgen.FunctionBody( cgen.FunctionDeclaration( cgen.Value( - 'std::unique_ptr', + 'DecodeResult', 'DecoderImpl::decodeInvalid', ), - [cgen.Value('const MachineInst *', 'opcode')], + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ), cgen.Block( [ cgen.Statement( - 'throw util::InvalidInst(std::format("{:X}", *opcode))' + 'return emit_error.emit() << "Invalid instruction opcode: " ' + '<< std::format("{:X}", *opcode)' ), - cgen.Statement('return nullptr'), ] ), ), @@ -12675,7 +12758,14 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: for _prefix in self.isa_spec.profile.vopd_encoding_prefixes: _reserve_primary_prefix(_prefix.prefix, _prefix.prefix_bits, _vopd_fn) _custom_primary_decode_bodies[_vopd_fn] = cgen.Block( - [cgen.Statement('return std::make_unique(opcode)')] + [ + cgen.Line( + ' Result validation = Vopd::validate_encoding(opcode, emit_error);\n' + ' if (validation.failed()) [[unlikely]]\n' + ' return Result::failure();\n' + ), + cgen.Statement('return std::make_unique(opcode)'), + ] ) if self._supports_gfx1250_scaled_wmma_vop3px2(): @@ -12702,7 +12792,7 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: cgen.Line( ' if (!isVop3pOp(opcode[2], 0x33) && ' '!isVop3pOp(opcode[2], 0x88))\n' - ' return decodeInvalid(opcode);\n' + ' return decodeInvalid(opcode, emit_error);\n' ), cgen.Statement( 'return std::make_unique(opcode)' @@ -12755,7 +12845,7 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: 'kVMfmaF3216x16x128F8f6f4Vop3pMfma &&\n' ' suffix_opcode != ' 'kVMfmaF3232x32x64F8f6f4Vop3pMfma))\n' - ' return decodeInvalid(opcode);\n' + ' return decodeInvalid(opcode, emit_error);\n' ' if (suffix_opcode == ' 'kVMfmaF3216x16x128F8f6f4Vop3pMfma)\n' ' return std::make_unique(opcode + 2, true);\n' @@ -12770,24 +12860,28 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: f'auto op = *reinterpret_cast(opcode + 2)' ), cgen.Statement( - f'return {_dte.sub_decode_table}[op.op](opcode + 2)' + f'return {_dte.sub_decode_table}[op.op](opcode + 2, emit_error)' ), ] ) break for _fn, _body in _custom_primary_decode_bodies.items(): _decl = cgen.FunctionDeclaration( - cgen.Value('static std::unique_ptr', _fn), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('static DecodeResult', _fn), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ) class_members.append(_decl) decode_table_funcs.append( cgen.FunctionBody( cgen.FunctionDeclaration( - cgen.Value( - 'std::unique_ptr', f'DecoderImpl::{_fn}' - ), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('DecodeResult', f'DecoderImpl::{_fn}'), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ), _body, ) @@ -12811,10 +12905,13 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: decode_funcs_found.add(dte.decode_func) func_decl = cgen.FunctionDeclaration( cgen.Value( - 'std::unique_ptr', + 'DecodeResult', f'DecoderImpl::{dte.decode_func}', ), - [cgen.Value('const MachineInst *', 'opcode')], + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], ) sub_decode_func_decls = [] if primary_factory_is_distributed: @@ -12843,7 +12940,7 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: 'op = *reinterpret_cast(opcode)', ), cgen.Statement( - f'return {dte.sub_decode_table}[op.op](opcode)' + f'return {dte.sub_decode_table}[op.op](opcode, emit_error)' ), ] ), @@ -12876,14 +12973,18 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: sub_decode_func_decls.append( cgen.FunctionDeclaration( cgen.Value( - 'static std::unique_ptr', + 'static DecodeResult', fn, ), [ cgen.Value( 'const MachineInst *', 'opcode', - ) + ), + cgen.Value( + 'const DecodeErrorEmitter &', + 'emit_error', + ), ], ) ) @@ -12902,14 +13003,18 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: cgen.FunctionBody( cgen.FunctionDeclaration( cgen.Value( - 'std::unique_ptr', + 'DecodeResult', f'DecoderImpl::{fn}', ), [ cgen.Value( 'const MachineInst *', 'opcode', - ) + ), + cgen.Value( + 'const DecodeErrorEmitter &', + 'emit_error', + ), ], ), _fn_body, @@ -12929,10 +13034,15 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: class_members.append( cgen.FunctionDeclaration( cgen.Value( - 'static std::unique_ptr', + 'static DecodeResult', f'{dte.decode_func}', ), - [cgen.Value('const MachineInst *', 'opcode')], + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value( + 'const DecodeErrorEmitter &', 'emit_error' + ), + ], ) ) class_members.extend(sub_decode_func_decls) @@ -12941,8 +13051,8 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: decode_table_entries = ''.join(decode_table_entries) class_members.extend(decode_tables) detail_decls = '\n'.join( - f'std::unique_ptr {factory_name}' - '(const MachineInst *opcode);' + f'DecodeResult {factory_name}' + '(const MachineInst *opcode, const DecodeErrorEmitter &emit_error);' for factory_name in sorted(distributed_factory_names) ) class_impl[0:0] = [ @@ -12955,10 +13065,15 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: 0, cgen.FunctionBody( cgen.FunctionDeclaration( - cgen.Value('std::unique_ptr', 'Decoder::decode'), - [cgen.Value('const MachineInst *', 'opcode')], + cgen.Value('DecodeResult', 'Decoder::decode'), + [ + cgen.Value('const MachineInst *', 'opcode'), + cgen.Value('const DecodeErrorEmitter &', 'emit_error'), + ], + ), + cgen.Block( + [cgen.Statement('return DecoderImpl::decode(opcode, emit_error)')] ), - cgen.Block([cgen.Statement('return DecoderImpl::decode(opcode)')]), ), ) class_impl.extend(decode_table_funcs) @@ -12981,6 +13096,7 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: ), False, ), + ('rocjitsu/isa/decode_result.h', False), ('array', True), ('cstddef', True), ('memory', True), @@ -12996,7 +13112,6 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: self.config.generated_include(self.generated_dir_name, 'decoder.h'), False, ), - ('util/except.h', False), ( self.config.generated_include( self.generated_dir_name, diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index 73a04f802a48..6bc03367d018 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -255,6 +255,12 @@ def _generated_bool_method_body(cpp: str, class_name: str, method: str) -> str: return cpp[start:end] +def _generated_decode_body(cpp: str, class_name: str) -> str: + start = cpp.index(f'DecodeResult decode{class_name}(') + end = cpp.index('\n}\n} // namespace detail', start) + return cpp[start : end + 2] + + def _execution_source_path(path: Path, profile) -> Path: """Return the source containing execution bodies for a generated file.""" if not profile.split_execution_sources: @@ -1937,15 +1943,15 @@ def test_generated_pseudo_scalar_vop3_paths_ignore_exec_and_f16_opsel( 'VSSqrtF16Vop3', ] for class_name in pseudo_scalar_constructors: - constructor = _generated_constructor_body(constructor_source, class_name) - assert '>= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO' in constructor - assert 'has an invalid SReg_32_XEXEC destination' in constructor - assert 'may not use VCC as a destination' not in constructor - assert constructor.index( + decode_body = _generated_decode_body(constructor_source, class_name) + assert 'OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO' in decode_body + assert 'has an invalid SReg_32_XEXEC destination' in decode_body + assert 'may not use VCC as a destination' not in decode_body + assert decode_body.index( 'has an invalid SReg_32_XEXEC destination' - ) < constructor.index('does not support DPP') - assert '->opsel' not in constructor - assert 'vop3_opsel' not in constructor + ) < decode_body.index('does not support DPP') + assert '->opsel' not in decode_body + assert 'vop3_opsel' not in decode_body assert constructor_source.count( 'has an invalid SReg_32_XEXEC destination' ) == len(pseudo_scalar_constructors) @@ -2298,7 +2304,10 @@ def test_generated_restricted_operands_do_not_apply_literal_fixups( assert 'src2 == 255' not in wmma assert 'src2 == 254' not in wmma assert 'OperandType::OPR_SRC' in generic_accumulator_wmma - assert 'has an invalid accumulator selector' in generic_accumulator_wmma + generic_accumulator_decode = _generated_decode_body( + vop3p, 'VWmmaF3216x16x128Fp8Fp8Vop3p' + ) + assert 'has an invalid accumulator selector' in generic_accumulator_decode assert 'src2 == 255' not in generic_accumulator_wmma assert 'src2 == 254' not in generic_accumulator_wmma assert 'OperandType::OPR_SIMM32' not in generic_accumulator_wmma @@ -2314,7 +2323,7 @@ def test_gfx1250_generated_operand_validates_lane_selectors( operand = (gfx1250_generated_root / 'operand.cpp').read_text() assert 'OPR_SSRC_LANESEL_POS_INT_MAX = 191' in operand_types - assert '#include "util/except.h"' in operand + assert '#include "util/except.h"' not in operand assert 'opr_type == OperandType::OPR_SSRC_LANESEL' in operand assert 'EncodingError::InvalidLaneSelector' in operand @@ -2323,7 +2332,7 @@ def test_gfx1250_generated_operand_rejects_invalid_exec_selector( gfx1250_generated_root: Path, ): operand = (gfx1250_generated_root / 'operand.cpp').read_text() - assert '#include "util/except.h"' in operand + assert '#include "util/except.h"' not in operand assert 'opr_type == OperandType::OPR_EXEC' in operand assert '(encoding_value >= 126 && encoding_value <= 126)' in operand assert 'EncodingError::InvalidExecSelector' in operand @@ -2348,16 +2357,19 @@ def test_gfx1250_generated_vop3_add_f16_applies_dpp( assert 'std::array raw_words_{};' in vop3_base vop3_encoding_ctor = _generated_constructor_body(encodings_cpp, 'Vop3') + vop3_validation = vop3_base assert 'inst_.src0 == amdgpu::SRC_DPP' in vop3_encoding_ctor assert 'amdgpu::dpp::is_src_dpp8(inst_.src0)' in vop3_encoding_ctor - assert 'DPP and literal operands cannot be combined' in vop3_encoding_ctor - assert vop3_encoding_ctor.index('DPP and literal operands cannot be combined') < ( - vop3_encoding_ctor.index('std::memcpy(raw_words_.data(), inst, size_);') - ) + assert 'DPP and literal operands cannot be combined' in vop3_validation assert 'size_ += sizeof(MachineInst);' in vop3_encoding_ctor assert 'std::memcpy(raw_words_.data(), inst, size_);' in vop3_encoding_ctor assert 'raw_encoding_ = raw_words_.data();' in vop3_encoding_ctor + decode = _generated_decode_body(vop3_alu, 'VAddF16Vop3') + assert 'Result validation = Vop3::validate_encoding(' in decode + assert decode.index('validate_encoding(') < decode.index('validation.failed()') + assert decode.index('validation.failed()') < decode.index('std::make_unique') + ctor = _generated_constructor_body(vop3_alu, 'VAddF16Vop3') assert 'Vop3VopDpp16MachineInst' in ctor assert 'dpp_ctrl_ = dp->dpp_ctrl;' in ctor @@ -2372,6 +2384,18 @@ def test_gfx1250_generated_vop3_add_f16_applies_dpp( assert 'src0.clear_delegate();' not in body +def test_noop_format_validation_is_inherited(amdgpu_generated_root: Path): + encodings_h = (amdgpu_generated_root / 'rdna4' / 'encodings.h').read_text() + + sopp_start = encodings_h.index('class Sopp ') + sopp = encodings_h[sopp_start : encodings_h.index('\n};', sopp_start)] + assert 'validate_encoding' not in sopp + + vop3_start = encodings_h.index('class Vop3 ') + vop3 = encodings_h[vop3_start : encodings_h.index('\n};', vop3_start)] + assert 'validate_encoding' in vop3 + + def test_generated_dpp8_disassembly_uses_encoding_state( amdgpu_generated_root: Path, ) -> None: @@ -2411,12 +2435,14 @@ def test_gfx1250_generated_vop3_rejects_literal64_selectors( assert 'src0 == 254' in vop1_ctor assert 'OperandType::OPR_SIMM64' in vop1_ctor + vop3_decode = _generated_decode_body(vop3_alu, 'VSqrtF16Vop3') + assert 'LiteralSupport::Literal32, 1' in vop3_decode vop3_ctor = _generated_constructor_body(vop3_alu, 'VSqrtF16Vop3') - assert 'LiteralSupport::Literal32, 1' in vop3_ctor assert 'OperandType::OPR_SIMM64' not in vop3_ctor + vop3p_decode = _generated_decode_body(vop3p, 'VFmaMixF32Vop3p') + assert 'LiteralSupport::Literal32' in vop3p_decode vop3p_ctor = _generated_constructor_body(vop3p, 'VFmaMixF32Vop3p') - assert 'LiteralSupport::Literal32' in vop3p_ctor assert 'OperandType::OPR_SIMM64' not in vop3p_ctor @@ -2434,13 +2460,14 @@ def test_gfx1250_generated_literal_validation(gfx1250_generated_root: Path): assert 'case 76:' not in sop1_literal_helper assert 'case 77:' not in sop1_literal_helper + barrier_decode = _generated_decode_body(sop1, 'SBarrierSignalSop1') + assert 'LiteralSupport::None' in barrier_decode barrier_ctor = _generated_constructor_body(sop1, 'SBarrierSignalSop1') - assert 'LiteralSupport::None' in barrier_ctor assert 'OperandType::OPR_SIMM32' not in barrier_ctor assert 'OperandType::OPR_SIMM64' not in barrier_ctor - sop2_ctor = _generated_constructor_body(sop2, 'SAddCoU32Sop2') - assert 'may not mix 32-bit and 64-bit literals' in sop2_ctor + sop2_decode = _generated_decode_body(sop2, 'SAddCoU32Sop2') + assert 'may not mix 32-bit and 64-bit literals' in sop2_decode assert vopd.count('VOPD does not support 64-bit literals') == 1 assert 'srcx0 == 254 || srcx0 == 255 || srcy0 == 254 || srcy0 == 255' in vopd assert 'VOPD3 does not support literal selectors' in vopd @@ -2468,14 +2495,14 @@ def test_generated_sendmsg_return_selectors_are_not_literals( assert 'OperandType::OPR_SIMM32' not in sendmsg_ctor assert 'OperandType::OPR_SIMM64' not in sendmsg_ctor if arch == 'gfx1250': - assert 'LiteralSupport::None, 0' in sendmsg_ctor + sendmsg_decode = _generated_decode_body(sop1, class_name) + assert 'LiteralSupport::None, 0' in sendmsg_decode def test_gfx1250_compact_literal_policy_precedes_extension_sizing( gfx1250_generated_root: Path, ): encodings_h = (gfx1250_generated_root / 'encodings.h').read_text() - encodings_cpp = (gfx1250_generated_root / 'encodings.cpp').read_text() vop1 = (gfx1250_generated_root / 'vop1.cpp').read_text() vop2 = (gfx1250_generated_root / 'vop2.cpp').read_text() @@ -2483,17 +2510,28 @@ def test_gfx1250_compact_literal_policy_precedes_extension_sizing( assert 'LiteralSupport::Both' in encodings_h for class_name in ('Vop1', 'Vop2', 'Vopc'): - body = _generated_constructor_body(encodings_cpp, class_name) + start = encodings_h.index(f'class {class_name} ') + body = encodings_h[start : encodings_h.index('\n};', start)] assert 'supports_literal(literal_support, LiteralSupport::Literal32)' in body assert 'supports_literal(literal_support, LiteralSupport::Literal64)' in body - assert body.index('supports_literal(') < body.index('has_encoded_literal64()') + assert 'static Result validate_encoding' in body - readfirstlane = _generated_constructor_body(vop1, 'VReadfirstlaneB32Vop1') + readfirstlane = _generated_decode_body(vop1, 'VReadfirstlaneB32Vop1') assert 'LiteralSupport::None' in readfirstlane + assert readfirstlane.index('validate_encoding(') < readfirstlane.index( + 'validation.failed()' + ) + assert readfirstlane.index('validation.failed()') < readfirstlane.index( + 'std::make_unique' + ) - fmamk_f64 = _generated_constructor_body(vop2, 'VFmamkF64Vop2') + fmamk_f64 = _generated_decode_body(vop2, 'VFmamkF64Vop2') assert 'LiteralSupport::Literal64' in fmamk_f64 - fmamk_f32 = _generated_constructor_body(vop2, 'VFmamkF32Vop2') + assert fmamk_f64.index('validate_encoding(') < fmamk_f64.index( + 'validation.failed()' + ) + assert fmamk_f64.index('validation.failed()') < fmamk_f64.index('std::make_unique') + fmamk_f32 = _generated_decode_body(vop2, 'VFmamkF32Vop2') assert 'LiteralSupport::Literal32' in fmamk_f32 @@ -2777,7 +2815,7 @@ def test_cdna4_generated_vop1_sdwa_availability_is_instruction_specific( encodings_h = (amdgpu_generated_root / 'cdna4' / 'encodings.h').read_text() supported = _generated_constructor_body(vop1, 'VMovB32Vop1') - unsupported = _generated_constructor_body(vop1, 'VCvtF64I32Vop1') + unsupported = _generated_decode_body(vop1, 'VCvtF64I32Vop1') assert 'reinterpret_cast' in supported assert 'sdwa_mnemonic' not in vop1 @@ -2786,10 +2824,7 @@ def test_cdna4_generated_vop1_sdwa_availability_is_instruction_specific( assert vop1_class is not None assert 'owned_mnemonic_' not in vop1_class.group() assert 'V_MOV_B32 does not support SDWA' not in supported - assert ( - 'throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", "");' - in unsupported - ) + assert 'emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"' in unsupported def test_gfx1250_generated_vop1_dpp8_availability_is_instruction_specific( @@ -2797,13 +2832,11 @@ def test_gfx1250_generated_vop1_dpp8_availability_is_instruction_specific( ): vop1 = (gfx1250_generated_root / 'vop1.cpp').read_text() constructor = _generated_constructor_body(vop1, 'VCvtF64I32Vop1') + decode_body = _generated_decode_body(vop1, 'VCvtF64I32Vop1') assert 'reinterpret_cast' in constructor assert 'reinterpret_cast' not in constructor - assert ( - 'throw util::InvalidInst("V_CVT_F64_I32 does not support DPP8", "");' - in constructor - ) + assert 'emit_error.emit() << "V_CVT_F64_I32 does not support DPP8"' in decode_body def test_rdna4_generated_vop3_dpp_availability_is_instruction_specific( @@ -2813,19 +2846,15 @@ def test_rdna4_generated_vop3_dpp_availability_is_instruction_specific( vop3p = (rdna4_generated_root / 'vop3p.cpp').read_text() supported = _generated_constructor_body(vop3, 'VAddF32Vop3') - unsupported_vop3 = _generated_constructor_body(vop3, 'VAddF64Vop3') - unsupported_vop3p = _generated_constructor_body(vop3p, 'VPkAddF16Vop3p') + unsupported_vop3 = _generated_decode_body(vop3, 'VAddF64Vop3') + unsupported_vop3p = _generated_decode_body(vop3p, 'VPkAddF16Vop3p') assert 'reinterpret_cast' in supported assert 'reinterpret_cast' in supported assert 'V_ADD_F32 does not support DPP' not in supported + assert 'emit_error.emit() << "V_ADD_F64 does not support DPP"' in unsupported_vop3 assert ( - 'throw util::InvalidInst("V_ADD_F64 does not support DPP", "");' - in unsupported_vop3 - ) - assert ( - 'throw util::InvalidInst("V_PK_ADD_F16 does not support DPP", "");' - in unsupported_vop3p + 'emit_error.emit() << "V_PK_ADD_F16 does not support DPP"' in unsupported_vop3p ) @@ -2852,18 +2881,15 @@ def test_gfx1250_packed_f32_execute_uses_local_simd_probe( def test_gfx1250_vop3p_rejects_unencoded_literal64_selectors( gfx1250_generated_root: Path, ): - encodings = (gfx1250_generated_root / 'encodings.cpp').read_text() + encodings_h = (gfx1250_generated_root / 'encodings.h').read_text() vop3p = (gfx1250_generated_root / 'vop3p.cpp').read_text() - ctor_start = encodings.index('Vop3p::Vop3p(') - ctor_end = encodings.index('void Vop3p::implicit_uses', ctor_start) - vop3p_ctor = encodings[ctor_start:ctor_end] + class_start = encodings_h.index('class Vop3p ') + validation = encodings_h[class_start : encodings_h.index('\n};', class_start)] - assert 'num_encoded_sources > 0 && inst_.src0 == 254' in vop3p_ctor - assert 'num_encoded_sources > 1 && inst_.src1 == 254' in vop3p_ctor - assert 'num_encoded_sources > 2 && inst_.src2 == 254' in vop3p_ctor - assert ( - 'throw util::InvalidInst("Vop3p does not support Literal64", "")' in vop3p_ctor - ) + assert 'num_encoded_sources > 0 && inst_.src0 == 254' in validation + assert 'num_encoded_sources > 1 && inst_.src1 == 254' in validation + assert 'num_encoded_sources > 2 && inst_.src2 == 254' in validation + assert 'emit_error.emit() << "Vop3p does not support Literal64"' in validation for class_name in ('VPkAddF32Vop3p', 'VPkMulF32Vop3p', 'VPkFmaF32Vop3p'): body = _generated_constructor_body(vop3p, class_name) @@ -2871,16 +2897,11 @@ def test_gfx1250_vop3p_rejects_unencoded_literal64_selectors( assert 'literal_word + 1' not in body for class_name in ('VPkAddF32Vop3p', 'VPkMulF32Vop3p'): - body = _generated_constructor_body(vop3p, class_name) - assert ( - f'selected_exec_fn(InstructionExecutionId::{class_name}), ' - 'LiteralSupport::Literal32, 2)' in body - ) - fma_body = _generated_constructor_body(vop3p, 'VPkFmaF32Vop3p') - assert ( - 'selected_exec_fn(InstructionExecutionId::VPkFmaF32Vop3p), ' - 'LiteralSupport::Literal32)' in fma_body - ) + body = _generated_decode_body(vop3p, class_name) + assert 'LiteralSupport::Literal32,' in body + assert '2);' in body + fma_body = _generated_decode_body(vop3p, 'VPkFmaF32Vop3p') + assert 'LiteralSupport::Literal32);' in fma_body def test_split_execution_ids_name_and_match_callbacks( @@ -3025,14 +3046,9 @@ def test_rdna1_2_generated_vopc_dpp_is_explicitly_unsupported( assert 'amdgpu::dpp::apply_dpp' not in vopc_exec, arch assert 'dpp_write_mask' not in vopc_exec, arch - ctor = _generated_constructor_body(vopc_model, 'VCmpEqU32Vopc') - assert ( - 'throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", "");' in ctor - ), arch - assert ( - 'amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)' - in ctor - ), arch + ctor = _generated_decode_body(vopc_model, 'VCmpEqU32Vopc') + assert 'emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"' in ctor, arch + assert 'amdgpu::dpp::is_src_dpp8(' in ctor, arch assert 'reinterpret_cast' not in ctor, arch body = _generated_method_body(vopc_exec, 'VCmpEqU32Vopc', 'VCmpLeU32Vopc') @@ -3386,7 +3402,6 @@ def test_gfx1250_helper_blocks_emit_scaled_wmma_table_decoder( assert ( 'reinterpret_cast(inst + 2), ' 'selected_exec_fn(InstructionExecutionId::VWmmaScaleF32Vop3px2), ' - 'LiteralSupport::Both, 3, ' 'Vop3p::ExtensionDecodePolicy::Skip),' ) in model_impl @@ -3396,8 +3411,9 @@ def test_gfx1250_helper_blocks_emit_scaled_wmma_table_decoder( decoder = (gfx1250_generated_root / 'decoder.cpp').read_text() decode_body = decoder.split( - 'std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) {' - )[1].split('std::unique_ptr DecoderImpl::decodeInvalid', 1)[0] + 'DecodeResult DecoderImpl::decode(const MachineInst *opcode, ' + 'const DecodeErrorEmitter &emit_error) {' + )[1].split('DecodeResult DecoderImpl::decodeInvalid', 1)[0] assert 'isWmmaScaleF32Vop3px2' not in decode_body assert decoder.count('&DecoderImpl::decodeVWmmaScaleF32Vop3px2,') == 2 assert 'if (!isVop3pOp(opcode[2], 0x33)' in decoder @@ -3531,14 +3547,15 @@ def generator_for( def test_cdna4_vop3px2_prefix_decoder_validates_suffix(cdna4_generated_root: Path): decoder = (cdna4_generated_root / 'decoder.cpp').read_text() decode_body = decoder.split( - 'std::unique_ptr Decoder::decode(const MachineInst *opcode) {' - )[1].split('std::unique_ptr Decoder::decodeInvalid', 1)[0] + 'DecodeResult DecoderImpl::decode(const MachineInst *opcode, ' + 'const DecodeErrorEmitter &emit_error) {' + )[1].split('DecodeResult DecoderImpl::decodeInvalid', 1)[0] assert 'isMfmaScaleF8f6f4Vop3px2' not in decode_body assert 'suffix_encoding != encoding::kVop3pMfma' in decoder assert 'kVMfmaF3216x16x128F8f6f4Vop3pMfma' in decoder assert 'kVMfmaF3232x32x64F8f6f4Vop3pMfma' in decoder - assert 'return decodeInvalid(opcode);' in decoder + assert 'return decodeInvalid(opcode, emit_error);' in decoder assert 'VMfmaF3216x16x128F8f6f4Vop3pMfma>(opcode + 2, true)' in decoder assert 'VMfmaF3232x32x64F8f6f4Vop3pMfma>(opcode + 2, true)' in decoder assert '#include "rocjitsu/isa/arch/amdgpu/generated/cdna4/opcodes.h"' in decoder @@ -3561,8 +3578,9 @@ def test_vopd_dispatch_uses_primary_decode_table( arch_root = amdgpu_generated_root / _generated_dir_name(arch_name) decoder = (arch_root / 'decoder.cpp').read_text() decode_body = decoder.split( - 'std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) {' - )[1].split('std::unique_ptr DecoderImpl::decodeInvalid', 1)[0] + 'DecodeResult DecoderImpl::decode(const MachineInst *opcode, ' + 'const DecodeErrorEmitter &emit_error) {' + )[1].split('DecodeResult DecoderImpl::decodeInvalid', 1)[0] assert 'Vopd::is_vopd' not in decode_body primary_table = decoder.split('DecoderImpl::primary_decode_table = {', 1)[1].split( @@ -3578,7 +3596,12 @@ def test_vopd_dispatch_uses_primary_decode_table( if entry == '&DecoderImpl::decodeVopd' } assert actual_vopd_indices == expected_vopd_indices - assert 'DecoderImpl::decodeVopd(const MachineInst *opcode)' in decoder + assert re.search( + r'DecoderImpl::decodeVopd\(const MachineInst \*opcode,\s+' + r'const DecodeErrorEmitter &emit_error\)', + decoder, + ) + assert 'Result validation = Vopd::validate_encoding(opcode, emit_error);' in decoder assert 'is_vopd' not in (arch_root / 'vopd.h').read_text() assert 'is_vopd' not in (arch_root / 'vopd.cpp').read_text() @@ -3603,7 +3626,7 @@ def test_decoder_header_keeps_dispatch_details_private( assert 'DecodeFunc' not in decoder_header assert 'decodeInvalid' not in decoder_header assert 'primary_decode_table' not in decoder_header - assert decoder_header.count('static std::unique_ptr decode(') == 1 + assert decoder_header.count('static DecodeResult decode(') == 1 def test_gfx1250_scaled_wmma_skips_vop3p_extension_decode( @@ -3626,7 +3649,6 @@ def test_gfx1250_scaled_wmma_skips_vop3p_extension_decode( guarded_body, constructor_suffix = guarded_suffix.rsplit('\n }\n}', 1) assert not constructor_suffix.strip() for extension_step in ( - 'throw util::InvalidInst("Vop3p does not support Literal64", "")', 'has_encoded_literal32()', 'inst_.src0 == amdgpu::SRC_DPP', 'amdgpu::dpp::is_src_dpp8(inst_.src0)', @@ -3635,9 +3657,14 @@ def test_gfx1250_scaled_wmma_skips_vop3p_extension_decode( ): assert extension_step in guarded_body + validation_start = encodings_h.index('class Vop3p ') + validation = encodings_h[ + validation_start : encodings_h.index('\n};', validation_start) + ] + assert 'emit_error.emit() << "Vop3p does not support Literal64"' in validation + assert ( 'selected_exec_fn(InstructionExecutionId::VWmmaScaleF32Vop3px2), ' - 'LiteralSupport::Both, 3, ' 'Vop3p::ExtensionDecodePolicy::Skip)' ) in vop3p_cpp @@ -3802,10 +3829,12 @@ def test_gfx1250_vopd_template_uses_dx9_zero_and_fma(tmp_path): assert 'make_src0(y_bits, true, false, 0, srcy0)' in cpp assert 'make_src0(x_bits, false, has_literal_, literal_, srcx0)' in cpp assert 'make_src0(y_bits, false, has_literal_, literal_, srcy0)' in cpp - assert 'if (!is_valid_opcode(opx_, kVopdXOpcodeMask))' in cpp - assert 'if (!is_valid_opcode(opy_, kVopdYOpcodeMask))' in cpp - assert 'if (!is_valid_opcode(opx_, kVopd3XOpcodeMask))' in cpp - assert 'if (!is_valid_opcode(opy_, kVopd3YOpcodeMask))' in cpp + assert 'if (!is_valid_opcode(opx, kVopdXOpcodeMask))' in cpp + assert 'if (!is_valid_opcode(opy, kVopdYOpcodeMask))' in cpp + assert 'if (!is_valid_opcode(opx, kVopd3XOpcodeMask))' in cpp + assert 'if (!is_valid_opcode(opy, kVopd3YOpcodeMask))' in cpp + assert 'return emit_error.emit() << "invalid VOPD X opcode";' in cpp + assert 'throw util::InvalidInst' not in cpp assert 'if (vdstx < y_end && vdsty < x_end)' in cpp assert 'case 3:\n case 7:' not in cpp assert 'if (lhs == 0.0f || rhs == 0.0f)' in exec_cpp @@ -4288,7 +4317,7 @@ def test_cdna4_mfma_f8f6f4_accepts_standalone_and_prefixed_encodings( source = (amdgpu_generated_root / 'cdna4' / 'vop3p.cpp').read_text() assert 'VMfmaF3216x16x128F8f6f4Vop3pMfma>(opcode + 2, true)' in decoder - assert 'decodeVMfmaF3216x16x128F8f6f4Vop3pMfma(const MachineInst *opcode)' in source + assert 'decodeVMfmaF3216x16x128F8f6f4Vop3pMfma(const MachineInst *opcode,' in source assert 'decodeVMfmaF3216x16x128F8f6f4Vop3pMfma' in decoder assert 'bool has_vop3px2_prefix = false' in header assert 'if (has_vop3px2_prefix)' in source diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp index 25eff90a63ed..fa83d4aa8dd3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp @@ -145,10 +145,10 @@ void BasicBlock::add_static_pc_address_builder(PcAddressBuilder builder) { static_pc_address_builders_.push_back(builder); } -std::vector> +FailureOr>> BasicBlock::build(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, - std::span extra_leaders, ExternalEntryPolicy entry_policy, - std::span extra_split_points) { + DecodeErrorEmitter emit_error, std::span extra_leaders, + ExternalEntryPolicy entry_policy, std::span extra_split_points) { std::vector> blocks; for (const auto *sec : co.text_sections()) { @@ -169,14 +169,15 @@ BasicBlock::build(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, continue; } - Instruction *raw_inst = nullptr; - try { - raw_inst = decoder.decode(&inst_data[pc], byte_offset); - } catch (const util::InvalidInst &error) { - throw util::InvalidInst( - std::string(error.what()) + " at .text byte offset " + std::to_string(byte_offset), ""); - } - std::unique_ptr inst(raw_inst); + auto emit_at_offset = [&](std::string_view message) { + emit_error.emit() << message << " at .text byte offset " << byte_offset; + }; + const DecodeErrorEmitter decode_error = + emit_error.ignores_messages() ? DecodeErrorEmitter{} : DecodeErrorEmitter(emit_at_offset); + DecodeResult decode_result = decoder.decode(&inst_data[pc], byte_offset, decode_error); + if (decode_result.failed()) + return Result::failure(); + std::unique_ptr inst = std::move(decode_result).value(); uint32_t inst_size_bytes = static_cast(inst->size()); uint32_t inst_words = inst_size_bytes / sizeof(uint32_t); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.h index 12e4d25f1c86..dd99dedcacb1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.h @@ -10,6 +10,7 @@ #include "rocjitsu/analysis/indirect_branch_discovery.h" #include "rocjitsu/code/instruction_list.h" #include "rocjitsu/code/rj_code.h" +#include "rocjitsu/isa/decode_result.h" #include "util/intrusive_list.h" #include @@ -153,6 +154,8 @@ class BasicBlock : public util::IListNode { /// @param[in] co Code object to analyze. /// @param[in] decoder Decoder for the target ISA. /// @param[in] arch ISA architecture used to match static PC builders. + /// @param[in] emit_error Destination for a decode diagnostic, including the + /// source `.text` byte offset. /// @param[in] extra_leaders Byte offsets that must start a basic block AND are entered from /// outside the decoded graph. Under ExplicitOnly these become the external-entry set, so an /// offset listed here has no incoming caller facts. @@ -163,10 +166,10 @@ class BasicBlock : public util::IListNode { /// entries. Function-entry symbols and stored-pointer targets belong here: they are genuine /// boundaries, yet most are ordinary helpers whose callers reach them by a decoded edge, and /// calling them external would throw those caller facts away. - /// @returns Ordered list of basic blocks with their decoded instructions. - static std::vector> + /// @returns Ordered basic blocks with their decoded instructions, or failure. + static FailureOr>> build(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, - std::span extra_leaders = {}, + DecodeErrorEmitter emit_error = {}, std::span extra_leaders = {}, ExternalEntryPolicy entry_policy = ExternalEntryPolicy::InferPredecessorless, std::span extra_split_points = {}); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp index 0d549a628cf9..94077a785f04 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp @@ -35,7 +35,6 @@ #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" #include "rocjitsu/isa/isa_traits.h" -#include "util/except.h" #include #include @@ -354,15 +353,13 @@ generated_branch_island_pool_offsets(std::span text, rj_code_arch // A malformed slot can select an extension-bearing format. Pad the // speculative decode so pool recognition never reads beyond its input. const std::array slot_words = {text_word_at(text, slot_offset), 0, 0}; - try { - std::unique_ptr slot_inst(decoder->decode(slot_words.data())); - if (slot_inst && slot_inst->size() == static_cast(sizeof(uint32_t)) && + DecodeResult decoded = decoder->decode(slot_words.data()); + if (decoded.succeeded()) { + const std::unique_ptr &slot_inst = decoded.value(); + if (slot_inst->size() == static_cast(sizeof(uint32_t)) && slot_inst->mnemonic() == "s_branch" && slot_inst->branch_offset_bytes()) { continue; } - } catch (const util::InvalidInst &) { - // A marker-shaped region containing an invalid instruction is not a - // generated pool. Normal block decoding will report the instruction. } has_canonical_slots = false; break; @@ -1938,10 +1935,9 @@ namespace internal { RewriteDischargeInstructionDecoder::RewriteDischargeInstructionDecoder(Decoder &decoder) : decoder_(decoder), lookahead_words_(decoder.max_instruction_words()) {} -RewriteDischargeDecodeStatus -RewriteDischargeInstructionDecoder::decode(std::span remaining_bytes, - uint64_t source_offset, - std::unique_ptr &instruction) { +RewriteDischargeDecodeStatus RewriteDischargeInstructionDecoder::decode( + std::span remaining_bytes, uint64_t source_offset, + std::unique_ptr &instruction, const DecodeErrorEmitter &emit_error) { instruction.reset(); if (lookahead_words_.empty()) return RewriteDischargeDecodeStatus::InvalidLookaheadBound; @@ -1950,7 +1946,10 @@ RewriteDischargeInstructionDecoder::decode(std::span remaining_by const size_t remaining_words = remaining_bytes.size() / sizeof(uint32_t); const size_t copied_words = std::min(remaining_words, lookahead_words_.size()); std::memcpy(lookahead_words_.data(), remaining_bytes.data(), copied_words * sizeof(uint32_t)); - instruction.reset(decoder_.decode(lookahead_words_.data(), source_offset)); + DecodeResult decoded = decoder_.decode(lookahead_words_.data(), source_offset, emit_error); + if (decoded.failed()) + return RewriteDischargeDecodeStatus::InvalidEncoding; + instruction = std::move(decoded).value(); if (instruction == nullptr || instruction->size() <= 0 || instruction->size() % static_cast(sizeof(uint32_t)) != 0) { return RewriteDischargeDecodeStatus::InvalidInstructionSize; @@ -2191,14 +2190,23 @@ void BinaryTranslator::verify_rewrite_discharge(TranslatedCodeObject &result) co } std::unique_ptr inst; - const auto decode_status = instruction_decoder.decode(text_bytes.subspan(instruction_offset), - instruction_offset, inst); + util::StringDiagnostic decode_error; + const auto decode_status = instruction_decoder.decode( + text_bytes.subspan(instruction_offset), instruction_offset, inst, decode_error.emitter()); if (decode_status == internal::RewriteDischargeDecodeStatus::InvalidLookaheadBound) { append_rewrite_discharge_error( result.diagnostics, "rewrite-discharge verification decoder reported an invalid lookahead bound"); return; } + if (decode_status == internal::RewriteDischargeDecodeStatus::InvalidEncoding) { + append_rewrite_discharge_error( + result.diagnostics, + "rewrite-discharge verification failed to decode final output: " + + decode_error.message(), + instruction_offset); + return; + } if (decode_status == internal::RewriteDischargeDecodeStatus::InvalidInstructionSize) { append_rewrite_discharge_error( result.diagnostics, @@ -2244,8 +2252,17 @@ void BinaryTranslator::verify_rewrite_discharge(TranslatedCodeObject &result) co return; } - const auto blocks = BasicBlock::build(output, *decoder, host_arch_, block_leaders, - ExternalEntryPolicy::ExplicitOnly); + util::StringDiagnostic decode_error; + FailureOr>> block_result = + BasicBlock::build(output, *decoder, host_arch_, decode_error.emitter(), block_leaders, + ExternalEntryPolicy::ExplicitOnly); + if (block_result.failed()) { + append_rewrite_discharge_error( + result.diagnostics, "rewrite-discharge verification failed to decode final output: " + + decode_error.message()); + return; + } + std::vector> blocks = std::move(block_result).value(); if (has_invalid_block_leader(blocks, block_leaders, text->size())) { append_rewrite_discharge_error( result.diagnostics, @@ -2496,13 +2513,15 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob // branch or call target can be resolved through the current kernel's placement // map without borrowing another kernel's return continuation. std::vector> blocks; - try { - blocks = BasicBlock::build(obj, *decoder, guest_arch_, block_leaders, - ExternalEntryPolicy::ExplicitOnly, block_split_points); - } catch (const util::InvalidInst &error) { - append_error(result.diagnostics, DiagnosticKind::Legalization, error.what()); + util::StringDiagnostic decode_error; + auto block_result = + BasicBlock::build(obj, *decoder, guest_arch_, decode_error.emitter(), block_leaders, + ExternalEntryPolicy::ExplicitOnly, block_split_points); + if (block_result.failed()) { + append_error(result.diagnostics, DiagnosticKind::Legalization, decode_error.message()); return leave_unchanged(); } + blocks = std::move(block_result).value(); if (has_invalid_block_leader(blocks, block_leaders, text.size())) { append_error(result.diagnostics, DiagnosticKind::Legalization, "translation found an invalid executable entry"); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h index 13e4856bb050..ece213636dc0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator_internal.h @@ -12,6 +12,8 @@ #pragma once +#include "rocjitsu/isa/decode_result.h" + #include #include #include @@ -29,6 +31,7 @@ namespace internal { enum class RewriteDischargeDecodeStatus : uint8_t { Success, InvalidLookaheadBound, + InvalidEncoding, InvalidInstructionSize, TruncatedInstruction, }; @@ -46,7 +49,8 @@ class RewriteDischargeInstructionDecoder { [[nodiscard]] RewriteDischargeDecodeStatus decode(std::span remaining_bytes, uint64_t source_offset, - std::unique_ptr &instruction); + std::unique_ptr &instruction, + const DecodeErrorEmitter &emit_error = {}); private: Decoder &decoder_; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp index e3b0f5b0bebb..30a01dd2ccf5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp @@ -584,7 +584,13 @@ bool Instrumentor::ensure_blocks_built(std::string *error_out) { return false; } decoder_ = std::move(decoder); - blocks_ = BasicBlock::build(obj_, *decoder_, arch_); + util::StringDiagnostic decode_error; + auto blocks = BasicBlock::build(obj_, *decoder_, arch_, decode_error.emitter()); + if (blocks.failed()) { + report(error_out, decode_error.message().c_str()); + return false; + } + blocks_ = std::move(blocks).value(); // BasicBlock::build returns blocks in .text order. Keep clause state across // block boundaries because a branch target may split the linear instruction // stream in the middle of a clause. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_callable.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_callable.cpp index 0d884bd97a3c..9cc6dc061b44 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_callable.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_callable.cpp @@ -15,6 +15,8 @@ #include #include #include +#include +#include namespace rocjitsu { @@ -172,11 +174,15 @@ std::optional build_probe_callable(const AmdGpuCodeObject &probe_ bool last_has_src0 = false; size_t w = 0; while (w < num_words) { - std::unique_ptr inst(decoder->decode(&words[w])); - if (inst == nullptr) { - report(error_out, "probe body failed to decode"); + util::StringDiagnostic decode_error; + DecodeResult decoded = decoder->decode(&words[w], decode_error.emitter()); + if (decoded.failed()) { + const std::string message = "probe body failed to decode at word " + std::to_string(w) + + ": " + decode_error.message(); + report(error_out, message.c_str()); return std::nullopt; } + std::unique_ptr inst = std::move(decoded).value(); const int size = inst->size(); if (size != 4 && size != 8) { report(error_out, "probe body has an unsupported instruction size"); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_clobber.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_clobber.cpp index de9aeea9e270..6169551e1103 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_clobber.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/probe_clobber.cpp @@ -138,11 +138,15 @@ std::optional build_probe_clobber_summary(const ProbeCallab size_t w = 0; while (w < num_words) { - std::unique_ptr inst(decoder->decode(&words[w])); - if (!inst) { - report(error_out, "failed to decode probe body while summarizing clobbers"); + util::StringDiagnostic decode_error; + DecodeResult decoded = decoder->decode(&words[w], decode_error.emitter()); + if (decoded.failed()) { + const std::string message = "failed to decode probe body at word " + std::to_string(w) + + " while summarizing clobbers: " + decode_error.message(); + report(error_out, message.c_str()); return std::nullopt; } + std::unique_ptr inst = std::move(decoded).value(); const int size = inst->size(); if (size != 4 && size != 8) { report(error_out, "probe body instruction has an unexpected size"); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp index df14f9046386..27b6b4c19cbb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/rj_code.cpp @@ -5,9 +5,9 @@ #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/target_registry.h" -#include "util/except.h" #include +#include #include using namespace rocjitsu; @@ -136,8 +136,10 @@ rj_status_t rj_code_inst_list_create(rj_code_object_t *obj, rj_code_target_id_t // at word zero for each section. std::size_t word_index = 0; while (word_index < inst_data_size) { - auto *raw_inst = decoder->decode(&inst_data[word_index]); - std::unique_ptr inst(raw_inst); + DecodeResult decoded = decoder->decode(&inst_data[word_index]); + if (decoded.failed()) + return ROCJITSU_STATUS_ERROR; + std::unique_ptr inst = std::move(decoded).value(); owned->list.push_back(*inst); word_index += static_cast(inst->size()) / sizeof(uint32_t); owned->storage.push_back(std::move(inst)); @@ -145,7 +147,9 @@ rj_status_t rj_code_inst_list_create(rj_code_object_t *obj, rj_code_target_id_t } *inst_list = owned.release(); - } catch (const util::InvalidInst &) { + } catch (const std::bad_alloc &) { + return ROCJITSU_STATUS_OUT_OF_RESOURCES; + } catch (...) { return ROCJITSU_STATUS_ERROR; } return ROCJITSU_STATUS_SUCCESS; @@ -191,12 +195,17 @@ rj_status_t rj_code_basic_block_list_create(rj_code_object_t *obj, rj_code_targe try { Instruction::ScopedHeapAllocation heap_allocation; auto owned = std::make_unique(); - owned->blocks = BasicBlock::build(*obj->co, *decoder, arch); + auto blocks = BasicBlock::build(*obj->co, *decoder, arch); + if (blocks.failed()) + return ROCJITSU_STATUS_ERROR; + owned->blocks = std::move(blocks).value(); *list = owned.release(); - } catch (const util::InvalidInst &) { + return ROCJITSU_STATUS_SUCCESS; + } catch (const std::bad_alloc &) { + return ROCJITSU_STATUS_OUT_OF_RESOURCES; + } catch (...) { return ROCJITSU_STATUS_ERROR; } - return ROCJITSU_STATUS_SUCCESS; } void rj_code_basic_block_list_retain(rj_code_basic_block_list_t *list) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.cpp index f392868421fd..249db7af23fa 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3p.h" -#include "util/except.h" #include #include #include @@ -15,1475 +14,1985 @@ namespace rocjitsu { namespace cdna1 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbinvl1Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbinvl1VolMubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeExpExp(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4COMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather8hPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode); -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpMovF32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpMovF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1F32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1llF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1lvF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2LegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbinvl1Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbinvl1VolMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4COMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather8hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpMovF32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpMovF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1llF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1lvF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2LegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeVintrp(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMimg(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1501,88 +2010,102 @@ struct DecoderImpl { static const std::array sub_decode_mimg; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVintrp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vintrp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vintrp[op.op](opcode); + return sub_decode_vintrp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMimg(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mimg::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mimg[op.op](opcode); + return sub_decode_mimg[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h index e5aa422cf3d6..1027924e2ef3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA1_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace cdna1 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 4; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace cdna1 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/ds.cpp index 6262ed270558..5966693fa603 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/ds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/ds.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +84,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +111,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +138,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +165,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +219,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +246,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +273,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +300,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +327,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -309,7 +356,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +381,11 @@ DsWriteB32Ds::DsWriteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +408,11 @@ DsWrite2B32Ds::DsWrite2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +435,12 @@ DsWrite2st64B32Ds::DsWrite2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +465,11 @@ DsCmpstB32Ds::DsCmpstB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -426,7 +494,11 @@ DsCmpstF32Ds::DsCmpstF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -449,7 +521,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +548,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +565,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +592,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -529,7 +617,12 @@ DsWriteAddtidB32Ds::DsWriteAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -550,7 +643,11 @@ DsWriteB8Ds::DsWriteB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +668,11 @@ DsWriteB16Ds::DsWriteB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -596,7 +697,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -621,7 +726,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -646,7 +755,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -671,7 +784,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -696,7 +813,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -721,7 +842,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -746,7 +871,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -771,7 +900,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -796,7 +929,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -821,7 +958,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -846,7 +987,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -871,7 +1016,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -898,7 +1047,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1077,12 @@ DsWrxchgRtnB32Ds::DsWrxchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -950,7 +1109,12 @@ DsWrxchg2RtnB32Ds::DsWrxchg2RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -977,7 +1141,12 @@ DsWrxchg2st64RtnB32Ds::DsWrxchg2st64RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1004,7 +1173,12 @@ DsCmpstRtnB32Ds::DsCmpstRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1031,7 +1205,12 @@ DsCmpstRtnF32Ds::DsCmpstRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1235,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1081,7 +1264,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1107,7 +1294,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1132,7 +1323,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1153,7 +1348,11 @@ DsReadB32Ds::DsReadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1174,7 +1373,11 @@ DsRead2B32Ds::DsRead2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1195,7 +1398,12 @@ DsRead2st64B32Ds::DsRead2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1216,7 +1424,11 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1237,7 +1449,11 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1258,7 +1474,11 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1499,11 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1296,7 +1520,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1315,7 +1543,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1334,7 +1566,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1357,7 +1594,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1380,7 +1621,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1403,7 +1648,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1426,7 +1675,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1449,7 +1702,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1472,7 +1729,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1495,7 +1756,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1783,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1810,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1564,7 +1837,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1587,7 +1864,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1610,7 +1891,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1635,7 +1920,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1656,7 +1945,11 @@ DsWriteB64Ds::DsWriteB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1679,7 +1972,11 @@ DsWrite2B64Ds::DsWrite2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1702,7 +1999,12 @@ DsWrite2st64B64Ds::DsWrite2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1727,7 +2029,11 @@ DsCmpstB64Ds::DsCmpstB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1752,7 +2058,11 @@ DsCmpstF64Ds::DsCmpstF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1775,7 +2085,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1798,7 +2112,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,7 +2137,12 @@ DsWriteB8D16HiDs::DsWriteB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1840,7 +2163,12 @@ DsWriteB16D16HiDs::DsWriteB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1861,7 +2189,11 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1888,7 +2220,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1915,7 +2252,11 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1942,7 +2283,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1969,7 +2315,11 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1996,7 +2346,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2027,7 +2382,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2052,7 +2411,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2077,7 +2440,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2102,7 +2469,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2127,7 +2498,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2152,7 +2527,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2177,7 +2556,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2202,7 +2585,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2227,7 +2614,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2252,7 +2643,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2277,7 +2672,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2302,7 +2701,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2329,7 +2732,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2354,7 +2762,12 @@ DsWrxchgRtnB64Ds::DsWrxchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2381,7 +2794,12 @@ DsWrxchg2RtnB64Ds::DsWrxchg2RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2408,7 +2826,12 @@ DsWrxchg2st64RtnB64Ds::DsWrxchg2st64RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2435,7 +2858,12 @@ DsCmpstRtnB64Ds::DsCmpstRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2462,7 +2890,12 @@ DsCmpstRtnF64Ds::DsCmpstRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2487,7 +2920,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2512,7 +2949,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2533,7 +2974,11 @@ DsReadB64Ds::DsReadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2554,7 +2999,11 @@ DsRead2B64Ds::DsRead2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2575,7 +3024,12 @@ DsRead2st64B64Ds::DsRead2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2600,7 +3054,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2613,7 +3072,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2628,7 +3092,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2641,7 +3109,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2656,7 +3128,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2669,7 +3145,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2684,7 +3164,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2705,7 +3189,12 @@ DsReadAddtidB32Ds::DsReadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2726,7 +3215,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2747,7 +3240,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2767,7 +3264,12 @@ DsOrderedCountDs::DsOrderedCountDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode) { +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_ordered_count", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2788,7 +3290,11 @@ DsWriteB96Ds::DsWriteB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2809,7 +3315,11 @@ DsWriteB128Ds::DsWriteB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2830,7 +3340,11 @@ DsReadB96Ds::DsReadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2851,7 +3365,11 @@ DsReadB128Ds::DsReadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h index 4145a044fea6..c1ddd008c19a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna1/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/exp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/exp.cpp index 28a45bb9cb04..e627465ae5ad 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/exp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/exp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/exp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -33,7 +32,11 @@ ExpExp::ExpExp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeExpExp(const MachineInst *opcode) { +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Exp::validate_encoding("exp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/flat.cpp index 108caf0a8a04..e6036d1231e6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/flat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/flat.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,12 @@ FlatLoadUbyteFlat::FlatLoadUbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +82,12 @@ FlatLoadSbyteFlat::FlatLoadSbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -113,7 +122,12 @@ FlatLoadUshortFlat::FlatLoadUshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +162,12 @@ FlatLoadSshortFlat::FlatLoadSshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -183,7 +202,12 @@ FlatLoadDwordFlat::FlatLoadDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -218,7 +242,12 @@ FlatLoadDwordx2Flat::FlatLoadDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +282,12 @@ FlatLoadDwordx3Flat::FlatLoadDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +322,12 @@ FlatLoadDwordx4Flat::FlatLoadDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +362,12 @@ FlatStoreByteFlat::FlatStoreByteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -358,7 +402,12 @@ FlatStoreByteD16HiFlat::FlatStoreByteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -393,7 +442,12 @@ FlatStoreShortFlat::FlatStoreShortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +482,12 @@ FlatStoreShortD16HiFlat::FlatStoreShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +522,12 @@ FlatStoreDwordFlat::FlatStoreDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -498,7 +562,12 @@ FlatStoreDwordx2Flat::FlatStoreDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -533,7 +602,12 @@ FlatStoreDwordx3Flat::FlatStoreDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +642,12 @@ FlatStoreDwordx4Flat::FlatStoreDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -603,7 +682,12 @@ FlatLoadUbyteD16Flat::FlatLoadUbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -645,7 +729,12 @@ FlatLoadUbyteD16HiFlat::FlatLoadUbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +776,12 @@ FlatLoadSbyteD16Flat::FlatLoadSbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -729,7 +823,12 @@ FlatLoadSbyteD16HiFlat::FlatLoadSbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -771,7 +870,12 @@ FlatLoadShortD16Flat::FlatLoadShortD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -813,7 +917,12 @@ FlatLoadShortD16HiFlat::FlatLoadShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +967,12 @@ FlatAtomicSwapFlat::FlatAtomicSwapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -896,7 +1010,12 @@ FlatAtomicCmpswapFlat::FlatAtomicCmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1053,12 @@ FlatAtomicAddFlat::FlatAtomicAddFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -972,7 +1096,12 @@ FlatAtomicSubFlat::FlatAtomicSubFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1010,7 +1139,12 @@ FlatAtomicSminFlat::FlatAtomicSminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1048,7 +1182,12 @@ FlatAtomicUminFlat::FlatAtomicUminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1086,7 +1225,12 @@ FlatAtomicSmaxFlat::FlatAtomicSmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1268,12 @@ FlatAtomicUmaxFlat::FlatAtomicUmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1162,7 +1311,12 @@ FlatAtomicAndFlat::FlatAtomicAndFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1200,7 +1354,12 @@ FlatAtomicOrFlat::FlatAtomicOrFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1397,12 @@ FlatAtomicXorFlat::FlatAtomicXorFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1276,7 +1440,12 @@ FlatAtomicIncFlat::FlatAtomicIncFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1314,7 +1483,12 @@ FlatAtomicDecFlat::FlatAtomicDecFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1526,12 @@ FlatAtomicSwapX2Flat::FlatAtomicSwapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1390,7 +1569,12 @@ FlatAtomicCmpswapX2Flat::FlatAtomicCmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1428,7 +1612,12 @@ FlatAtomicAddX2Flat::FlatAtomicAddX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1655,12 @@ FlatAtomicSubX2Flat::FlatAtomicSubX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,7 +1698,12 @@ FlatAtomicSminX2Flat::FlatAtomicSminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1542,7 +1741,12 @@ FlatAtomicUminX2Flat::FlatAtomicUminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1580,7 +1784,12 @@ FlatAtomicSmaxX2Flat::FlatAtomicSmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1618,7 +1827,12 @@ FlatAtomicUmaxX2Flat::FlatAtomicUmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1656,7 +1870,12 @@ FlatAtomicAndX2Flat::FlatAtomicAndX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1694,7 +1913,12 @@ FlatAtomicOrX2Flat::FlatAtomicOrX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1732,7 +1956,12 @@ FlatAtomicXorX2Flat::FlatAtomicXorX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1770,7 +1999,12 @@ FlatAtomicIncX2Flat::FlatAtomicIncX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1808,7 +2042,12 @@ FlatAtomicDecX2Flat::FlatAtomicDecX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mimg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mimg.cpp index 6ea91327c7e9..fe4b4119a4f5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mimg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mimg.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/mimg.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -26,7 +25,11 @@ ImageLoadMimg::ImageLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -45,7 +48,12 @@ ImageLoadMipMimg::ImageLoadMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +72,12 @@ ImageLoadPckMimg::ImageLoadPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +96,12 @@ ImageLoadPckSgnMimg::ImageLoadPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +120,12 @@ ImageLoadMipPckMimg::ImageLoadMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +144,12 @@ ImageLoadMipPckSgnMimg::ImageLoadMipPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ ImageStoreMimg::ImageStoreMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +191,12 @@ ImageStoreMipMimg::ImageStoreMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +215,12 @@ ImageStorePckMimg::ImageStorePckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +239,12 @@ ImageStoreMipPckMimg::ImageStoreMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +263,12 @@ ImageGetResinfoMimg::ImageGetResinfoMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -236,7 +288,12 @@ ImageAtomicSwapMimg::ImageAtomicSwapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +313,12 @@ ImageAtomicCmpswapMimg::ImageAtomicCmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -276,7 +338,12 @@ ImageAtomicAddMimg::ImageAtomicAddMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +363,12 @@ ImageAtomicSubMimg::ImageAtomicSubMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -316,7 +388,12 @@ ImageAtomicSminMimg::ImageAtomicSminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +413,12 @@ ImageAtomicUminMimg::ImageAtomicUminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +438,12 @@ ImageAtomicSmaxMimg::ImageAtomicSmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +463,12 @@ ImageAtomicUmaxMimg::ImageAtomicUmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -396,7 +488,12 @@ ImageAtomicAndMimg::ImageAtomicAndMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -416,7 +513,12 @@ ImageAtomicOrMimg::ImageAtomicOrMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +538,12 @@ ImageAtomicXorMimg::ImageAtomicXorMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +563,12 @@ ImageAtomicIncMimg::ImageAtomicIncMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +588,12 @@ ImageAtomicDecMimg::ImageAtomicDecMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -497,7 +614,12 @@ ImageSampleMimg::ImageSampleMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -518,7 +640,12 @@ ImageSampleClMimg::ImageSampleClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -539,7 +666,12 @@ ImageSampleDMimg::ImageSampleDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +692,12 @@ ImageSampleDClMimg::ImageSampleDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -581,7 +718,12 @@ ImageSampleLMimg::ImageSampleLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +744,12 @@ ImageSampleBMimg::ImageSampleBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +770,12 @@ ImageSampleBClMimg::ImageSampleBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -644,7 +796,12 @@ ImageSampleLzMimg::ImageSampleLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -665,7 +822,12 @@ ImageSampleCMimg::ImageSampleCMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -686,7 +848,12 @@ ImageSampleCClMimg::ImageSampleCClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +874,12 @@ ImageSampleCDMimg::ImageSampleCDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -728,7 +900,12 @@ ImageSampleCDClMimg::ImageSampleCDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +926,12 @@ ImageSampleCLMimg::ImageSampleCLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +952,12 @@ ImageSampleCBMimg::ImageSampleCBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +978,12 @@ ImageSampleCBClMimg::ImageSampleCBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -812,7 +1004,12 @@ ImageSampleCLzMimg::ImageSampleCLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -833,7 +1030,12 @@ ImageSampleOMimg::ImageSampleOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -854,7 +1056,12 @@ ImageSampleClOMimg::ImageSampleClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -875,7 +1082,12 @@ ImageSampleDOMimg::ImageSampleDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -896,7 +1108,12 @@ ImageSampleDClOMimg::ImageSampleDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -917,7 +1134,12 @@ ImageSampleLOMimg::ImageSampleLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -938,7 +1160,12 @@ ImageSampleBOMimg::ImageSampleBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -959,7 +1186,12 @@ ImageSampleBClOMimg::ImageSampleBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -980,7 +1212,12 @@ ImageSampleLzOMimg::ImageSampleLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1001,7 +1238,12 @@ ImageSampleCOMimg::ImageSampleCOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1022,7 +1264,12 @@ ImageSampleCClOMimg::ImageSampleCClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1043,7 +1290,12 @@ ImageSampleCDOMimg::ImageSampleCDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1064,7 +1316,12 @@ ImageSampleCDClOMimg::ImageSampleCDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1085,7 +1342,12 @@ ImageSampleCLOMimg::ImageSampleCLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1106,7 +1368,12 @@ ImageSampleCBOMimg::ImageSampleCBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1127,7 +1394,12 @@ ImageSampleCBClOMimg::ImageSampleCBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1148,7 +1420,12 @@ ImageSampleCLzOMimg::ImageSampleCLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1169,7 +1446,12 @@ ImageGather4Mimg::ImageGather4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1190,7 +1472,12 @@ ImageGather4ClMimg::ImageGather4ClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1211,7 +1498,12 @@ ImageGather4hMimg::ImageGather4hMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1232,7 +1524,12 @@ ImageGather4LMimg::ImageGather4LMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1253,7 +1550,12 @@ ImageGather4BMimg::ImageGather4BMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1274,7 +1576,12 @@ ImageGather4BClMimg::ImageGather4BClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1295,7 +1602,12 @@ ImageGather4LzMimg::ImageGather4LzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1316,7 +1628,12 @@ ImageGather4CMimg::ImageGather4CMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1337,7 +1654,12 @@ ImageGather4CClMimg::ImageGather4CClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1358,7 +1680,12 @@ ImageGather4hPckMimg::ImageGather4hPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1379,7 +1706,12 @@ ImageGather8hPckMimg::ImageGather8hPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather8hPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather8hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather8h_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1400,7 +1732,12 @@ ImageGather4CLMimg::ImageGather4CLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1421,7 +1758,12 @@ ImageGather4CBMimg::ImageGather4CBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1442,7 +1784,12 @@ ImageGather4CBClMimg::ImageGather4CBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1463,7 +1810,12 @@ ImageGather4CLzMimg::ImageGather4CLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1484,7 +1836,12 @@ ImageGather4OMimg::ImageGather4OMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1505,7 +1862,12 @@ ImageGather4ClOMimg::ImageGather4ClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1526,7 +1888,12 @@ ImageGather4LOMimg::ImageGather4LOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1914,12 @@ ImageGather4BOMimg::ImageGather4BOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1568,7 +1940,12 @@ ImageGather4BClOMimg::ImageGather4BClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1589,7 +1966,12 @@ ImageGather4LzOMimg::ImageGather4LzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1610,7 +1992,12 @@ ImageGather4COMimg::ImageGather4COMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4COMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4COMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1631,7 +2018,12 @@ ImageGather4CClOMimg::ImageGather4CClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1652,7 +2044,12 @@ ImageGather4CLOMimg::ImageGather4CLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +2070,12 @@ ImageGather4CBOMimg::ImageGather4CBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1694,7 +2096,12 @@ ImageGather4CBClOMimg::ImageGather4CBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1715,7 +2122,12 @@ ImageGather4CLzOMimg::ImageGather4CLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1736,7 +2148,12 @@ ImageGetLodMimg::ImageGetLodMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_lod", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1757,7 +2174,12 @@ ImageSampleCdMimg::ImageSampleCdMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1778,7 +2200,12 @@ ImageSampleCdClMimg::ImageSampleCdClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1799,7 +2226,12 @@ ImageSampleCCdMimg::ImageSampleCCdMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1820,7 +2252,12 @@ ImageSampleCCdClMimg::ImageSampleCCdClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1841,7 +2278,12 @@ ImageSampleCdOMimg::ImageSampleCdOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1862,7 +2304,12 @@ ImageSampleCdClOMimg::ImageSampleCdClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1883,7 +2330,12 @@ ImageSampleCCdOMimg::ImageSampleCCdOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1904,7 +2356,12 @@ ImageSampleCCdClOMimg::ImageSampleCCdClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mtbuf.cpp index 98333422dab4..d82a6742c8a2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mtbuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/mtbuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +70,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +128,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -138,7 +157,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +186,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +215,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -210,7 +244,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +273,12 @@ TbufferLoadFormatD16XMtbuf::TbufferLoadFormatD16XMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +308,13 @@ TbufferLoadFormatD16XyMtbuf::TbufferLoadFormatD16XyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +338,13 @@ TbufferLoadFormatD16XyzMtbuf::TbufferLoadFormatD16XyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +374,13 @@ TbufferLoadFormatD16XyzwMtbuf::TbufferLoadFormatD16XyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +404,13 @@ TbufferStoreFormatD16XMtbuf::TbufferStoreFormatD16XMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +434,13 @@ TbufferStoreFormatD16XyMtbuf::TbufferStoreFormatD16XyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +464,13 @@ TbufferStoreFormatD16XyzMtbuf::TbufferStoreFormatD16XyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -414,7 +494,13 @@ TbufferStoreFormatD16XyzwMtbuf::TbufferStoreFormatD16XyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf.cpp index 2a80d97894db..b1949e701c48 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/mubuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +70,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +128,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -138,7 +157,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +186,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +215,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -210,7 +244,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +273,12 @@ BufferLoadFormatD16XMubuf::BufferLoadFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +309,12 @@ BufferLoadFormatD16XyMubuf::BufferLoadFormatD16XyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +338,13 @@ BufferLoadFormatD16XyzMubuf::BufferLoadFormatD16XyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -320,7 +375,13 @@ BufferLoadFormatD16XyzwMubuf::BufferLoadFormatD16XyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +405,12 @@ BufferStoreFormatD16XMubuf::BufferStoreFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,7 +434,13 @@ BufferStoreFormatD16XyMubuf::BufferStoreFormatD16XyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -392,7 +464,13 @@ BufferStoreFormatD16XyzMubuf::BufferStoreFormatD16XyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -416,7 +494,13 @@ BufferStoreFormatD16XyzwMubuf::BufferStoreFormatD16XyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -440,7 +524,12 @@ BufferLoadUbyteMubuf::BufferLoadUbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -464,7 +553,12 @@ BufferLoadSbyteMubuf::BufferLoadSbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +582,12 @@ BufferLoadUshortMubuf::BufferLoadUshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +611,12 @@ BufferLoadSshortMubuf::BufferLoadSshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +640,12 @@ BufferLoadDwordMubuf::BufferLoadDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +669,12 @@ BufferLoadDwordx2Mubuf::BufferLoadDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -584,7 +698,12 @@ BufferLoadDwordx3Mubuf::BufferLoadDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -608,7 +727,12 @@ BufferLoadDwordx4Mubuf::BufferLoadDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -632,7 +756,12 @@ BufferStoreByteMubuf::BufferStoreByteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -656,7 +785,12 @@ BufferStoreByteD16HiMubuf::BufferStoreByteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -680,7 +814,12 @@ BufferStoreShortMubuf::BufferStoreShortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +843,12 @@ BufferStoreShortD16HiMubuf::BufferStoreShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -728,7 +872,12 @@ BufferStoreDwordMubuf::BufferStoreDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -752,7 +901,12 @@ BufferStoreDwordx2Mubuf::BufferStoreDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -776,7 +930,12 @@ BufferStoreDwordx3Mubuf::BufferStoreDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -800,7 +959,12 @@ BufferStoreDwordx4Mubuf::BufferStoreDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -824,7 +988,12 @@ BufferLoadUbyteD16Mubuf::BufferLoadUbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +1024,12 @@ BufferLoadUbyteD16HiMubuf::BufferLoadUbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -886,7 +1060,12 @@ BufferLoadSbyteD16Mubuf::BufferLoadSbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -917,7 +1096,12 @@ BufferLoadSbyteD16HiMubuf::BufferLoadSbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -948,7 +1132,12 @@ BufferLoadShortD16Mubuf::BufferLoadShortD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -979,7 +1168,12 @@ BufferLoadShortD16HiMubuf::BufferLoadShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1010,7 +1204,13 @@ BufferLoadFormatD16HiXMubuf::BufferLoadFormatD16HiXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1041,7 +1241,13 @@ BufferStoreFormatD16HiXMubuf::BufferStoreFormatD16HiXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1059,7 +1265,12 @@ BufferStoreLdsDwordMubuf::BufferStoreLdsDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_lds_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1283,12 @@ BufferWbinvl1Mubuf::BufferWbinvl1Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbinvl1Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbinvl1Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbinvl1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1085,7 +1301,12 @@ BufferWbinvl1VolMubuf::BufferWbinvl1VolMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbinvl1VolMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbinvl1VolMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbinvl1_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1111,7 +1332,12 @@ BufferAtomicSwapMubuf::BufferAtomicSwapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1364,12 @@ BufferAtomicCmpswapMubuf::BufferAtomicCmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1164,7 +1395,12 @@ BufferAtomicAddMubuf::BufferAtomicAddMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1190,7 +1426,12 @@ BufferAtomicSubMubuf::BufferAtomicSubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1216,7 +1457,12 @@ BufferAtomicSminMubuf::BufferAtomicSminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1242,7 +1488,12 @@ BufferAtomicUminMubuf::BufferAtomicUminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1268,7 +1519,12 @@ BufferAtomicSmaxMubuf::BufferAtomicSmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1294,7 +1550,12 @@ BufferAtomicUmaxMubuf::BufferAtomicUmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1320,7 +1581,12 @@ BufferAtomicAndMubuf::BufferAtomicAndMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1346,7 +1612,12 @@ BufferAtomicOrMubuf::BufferAtomicOrMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1372,7 +1643,12 @@ BufferAtomicXorMubuf::BufferAtomicXorMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1398,7 +1674,12 @@ BufferAtomicIncMubuf::BufferAtomicIncMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1424,7 +1705,12 @@ BufferAtomicDecMubuf::BufferAtomicDecMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1450,7 +1736,12 @@ BufferAtomicAddF32Mubuf::BufferAtomicAddF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1476,7 +1767,12 @@ BufferAtomicPkAddF16Mubuf::BufferAtomicPkAddF16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1502,7 +1798,12 @@ BufferAtomicSwapX2Mubuf::BufferAtomicSwapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1529,7 +1830,12 @@ BufferAtomicCmpswapX2Mubuf::BufferAtomicCmpswapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1555,7 +1861,12 @@ BufferAtomicAddX2Mubuf::BufferAtomicAddX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1581,7 +1892,12 @@ BufferAtomicSubX2Mubuf::BufferAtomicSubX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1607,7 +1923,12 @@ BufferAtomicSminX2Mubuf::BufferAtomicSminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1633,7 +1954,12 @@ BufferAtomicUminX2Mubuf::BufferAtomicUminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1659,7 +1985,12 @@ BufferAtomicSmaxX2Mubuf::BufferAtomicSmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1685,7 +2016,12 @@ BufferAtomicUmaxX2Mubuf::BufferAtomicUmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1711,7 +2047,12 @@ BufferAtomicAndX2Mubuf::BufferAtomicAndX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1737,7 +2078,12 @@ BufferAtomicOrX2Mubuf::BufferAtomicOrX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1763,7 +2109,12 @@ BufferAtomicXorX2Mubuf::BufferAtomicXorX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1789,7 +2140,12 @@ BufferAtomicIncX2Mubuf::BufferAtomicIncX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1815,7 +2171,12 @@ BufferAtomicDecX2Mubuf::BufferAtomicDecX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp index af9e4be4292f..abfb63d927ec 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem.cpp index 37c38b5a87d4..c9008055259f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,11 @@ SLoadDwordSmem::SLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,12 @@ SLoadDwordx2Smem::SLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +91,12 @@ SLoadDwordx4Smem::SLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -103,7 +116,12 @@ SLoadDwordx8Smem::SLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +141,12 @@ SLoadDwordx16Smem::SLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +166,12 @@ SScratchLoadDwordSmem::SScratchLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -163,7 +191,12 @@ SScratchLoadDwordx2Smem::SScratchLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -183,7 +216,12 @@ SScratchLoadDwordx4Smem::SScratchLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +241,12 @@ SBufferLoadDwordSmem::SBufferLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +266,12 @@ SBufferLoadDwordx2Smem::SBufferLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +291,12 @@ SBufferLoadDwordx4Smem::SBufferLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,7 +316,12 @@ SBufferLoadDwordx8Smem::SBufferLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +341,12 @@ SBufferLoadDwordx16Smem::SBufferLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -303,7 +366,12 @@ SStoreDwordSmem::SStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +391,12 @@ SStoreDwordx2Smem::SStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +416,12 @@ SStoreDwordx4Smem::SStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -363,7 +441,12 @@ SScratchStoreDwordSmem::SScratchStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -383,7 +466,12 @@ SScratchStoreDwordx2Smem::SScratchStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -403,7 +491,12 @@ SScratchStoreDwordx4Smem::SScratchStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -423,7 +516,12 @@ SBufferStoreDwordSmem::SBufferStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -443,7 +541,12 @@ SBufferStoreDwordx2Smem::SBufferStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +566,12 @@ SBufferStoreDwordx4Smem::SBufferStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +584,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -489,7 +601,11 @@ SDcacheWbSmem::SDcacheWbSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -502,7 +618,12 @@ SDcacheInvVolSmem::SDcacheInvVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -515,7 +636,12 @@ SDcacheWbVolSmem::SDcacheWbVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -530,7 +656,11 @@ SMemtimeSmem::SMemtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +675,12 @@ SMemrealtimeSmem::SMemrealtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memrealtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +699,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -583,7 +722,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -600,7 +744,12 @@ SDcacheDiscardSmem::SDcacheDiscardSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +766,12 @@ SDcacheDiscardX2Smem::SDcacheDiscardX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -637,7 +791,12 @@ SBufferAtomicSwapSmem::SBufferAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +816,12 @@ SBufferAtomicCmpswapSmem::SBufferAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -677,7 +841,12 @@ SBufferAtomicAddSmem::SBufferAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -697,7 +866,12 @@ SBufferAtomicSubSmem::SBufferAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +891,12 @@ SBufferAtomicSminSmem::SBufferAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -737,7 +916,12 @@ SBufferAtomicUminSmem::SBufferAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -757,7 +941,12 @@ SBufferAtomicSmaxSmem::SBufferAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -777,7 +966,12 @@ SBufferAtomicUmaxSmem::SBufferAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -797,7 +991,12 @@ SBufferAtomicAndSmem::SBufferAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -817,7 +1016,12 @@ SBufferAtomicOrSmem::SBufferAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -837,7 +1041,12 @@ SBufferAtomicXorSmem::SBufferAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -857,7 +1066,12 @@ SBufferAtomicIncSmem::SBufferAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1091,12 @@ SBufferAtomicDecSmem::SBufferAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -897,7 +1116,12 @@ SBufferAtomicSwapX2Smem::SBufferAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -917,7 +1141,12 @@ SBufferAtomicCmpswapX2Smem::SBufferAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -937,7 +1166,12 @@ SBufferAtomicAddX2Smem::SBufferAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -957,7 +1191,12 @@ SBufferAtomicSubX2Smem::SBufferAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -977,7 +1216,12 @@ SBufferAtomicSminX2Smem::SBufferAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -997,7 +1241,12 @@ SBufferAtomicUminX2Smem::SBufferAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1266,12 @@ SBufferAtomicSmaxX2Smem::SBufferAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1037,7 +1291,12 @@ SBufferAtomicUmaxX2Smem::SBufferAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1316,12 @@ SBufferAtomicAndX2Smem::SBufferAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1077,7 +1341,12 @@ SBufferAtomicOrX2Smem::SBufferAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1366,12 @@ SBufferAtomicXorX2Smem::SBufferAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1117,7 +1391,12 @@ SBufferAtomicIncX2Smem::SBufferAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1416,12 @@ SBufferAtomicDecX2Smem::SBufferAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1157,7 +1441,12 @@ SAtomicSwapSmem::SAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1177,7 +1466,12 @@ SAtomicCmpswapSmem::SAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1491,11 @@ SAtomicAddSmem::SAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1217,7 +1515,11 @@ SAtomicSubSmem::SAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1237,7 +1539,12 @@ SAtomicSminSmem::SAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1257,7 +1564,12 @@ SAtomicUminSmem::SAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1277,7 +1589,12 @@ SAtomicSmaxSmem::SAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1297,7 +1614,12 @@ SAtomicUmaxSmem::SAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1317,7 +1639,11 @@ SAtomicAndSmem::SAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1337,7 +1663,11 @@ SAtomicOrSmem::SAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1357,7 +1687,11 @@ SAtomicXorSmem::SAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1377,7 +1711,11 @@ SAtomicIncSmem::SAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1397,7 +1735,11 @@ SAtomicDecSmem::SAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1417,7 +1759,12 @@ SAtomicSwapX2Smem::SAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1437,7 +1784,12 @@ SAtomicCmpswapX2Smem::SAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1809,12 @@ SAtomicAddX2Smem::SAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1477,7 +1834,12 @@ SAtomicSubX2Smem::SAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1859,12 @@ SAtomicSminX2Smem::SAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1517,7 +1884,12 @@ SAtomicUminX2Smem::SAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1537,7 +1909,12 @@ SAtomicSmaxX2Smem::SAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1557,7 +1934,12 @@ SAtomicUmaxX2Smem::SAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1577,7 +1959,12 @@ SAtomicAndX2Smem::SAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1597,7 +1984,12 @@ SAtomicOrX2Smem::SAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1617,7 +2009,12 @@ SAtomicXorX2Smem::SAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1637,7 +2034,12 @@ SAtomicIncX2Smem::SAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1657,7 +2059,12 @@ SAtomicDecX2Smem::SAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1.cpp index b2bf8e1d3342..2cd1dd283dc8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +173,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +201,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +230,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +255,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +281,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -295,7 +339,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -319,7 +368,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +398,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +424,11 @@ SFf0I32B32Sop1::SFf0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +450,11 @@ SFf0I32B64Sop1::SFf0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +475,11 @@ SFf1I32B32Sop1::SFf1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +501,11 @@ SFf1I32B64Sop1::SFf1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +526,12 @@ SFlbitI32B32Sop1::SFlbitI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +553,12 @@ SFlbitI32B64Sop1::SFlbitI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +579,11 @@ SFlbitI32Sop1::SFlbitI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +605,12 @@ SFlbitI32I64Sop1::SFlbitI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +632,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +658,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +685,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -604,7 +712,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +739,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +766,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +789,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -685,7 +812,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +839,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +861,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +897,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +935,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -823,7 +972,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +1009,12 @@ SAndn2SaveexecB64Sop1::SAndn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -887,7 +1046,12 @@ SOrn2SaveexecB64Sop1::SOrn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -919,7 +1083,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1120,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -983,7 +1157,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1007,7 +1186,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1216,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1241,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1266,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1295,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1325,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1141,7 +1350,12 @@ SCbranchJoinSop1::SCbranchJoinSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode) { +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cbranch_join", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1379,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1189,7 +1407,12 @@ SSetGprIdxIdxSop1::SSetGprIdxIdxSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_set_gpr_idx_idx", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1444,12 @@ SAndn1SaveexecB64Sop1::SAndn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1253,7 +1481,12 @@ SOrn1SaveexecB64Sop1::SOrn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1285,7 +1518,12 @@ SAndn1WrexecB64Sop1::SAndn1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1317,7 +1555,12 @@ SAndn2WrexecB64Sop1::SAndn2WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1581,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop2.cpp index e6d9359a8de9..d10215b3d6d5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +280,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +314,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +348,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +382,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +454,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +490,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +525,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +562,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +596,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +632,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +666,11 @@ SAndn2B32Sop2::SAndn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +702,11 @@ SAndn2B64Sop2::SAndn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +736,11 @@ SOrn2B32Sop2::SOrn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +772,11 @@ SOrn2B64Sop2::SOrn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +806,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +842,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -779,7 +876,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -811,7 +912,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +946,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +982,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1016,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1051,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1085,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1120,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1154,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1189,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1220,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1251,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1282,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1316,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1350,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1385,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1420,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1444,12 @@ SCbranchGForkSop2::SCbranchGForkSop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode) { +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cbranch_g_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1479,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1513,12 @@ SRfeRestoreB64Sop2::SRfeRestoreB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_rfe_restore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1365,7 +1545,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1392,7 +1576,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,7 +1610,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1645,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1680,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1715,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1749,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1569,7 +1782,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1596,7 +1814,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp index 8ff4eac337d3..df06df0702c2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -482,7 +549,11 @@ SSetvskipSopc::SSetvskipSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode) { +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_setvskip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +579,12 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_set_gpr_idx_on", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +614,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +648,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopk.cpp index 29ad2c1587da..7db0b2e8f659 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -46,7 +49,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +73,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,7 +97,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +121,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +145,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +169,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +193,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +217,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -206,7 +241,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -226,7 +265,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +289,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +313,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -286,7 +337,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +362,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +384,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +405,12 @@ SCbranchIForkSopk::SCbranchIForkSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode) { +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cbranch_i_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +427,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +448,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -395,7 +471,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +499,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopp.cpp index a0fc333eea68..286429ae3390 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -36,7 +39,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +60,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +82,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +106,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +136,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +166,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +196,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +226,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +256,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +280,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +299,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +338,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +357,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +376,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +398,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,7 +420,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -362,7 +440,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +457,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +476,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +496,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +517,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +537,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +577,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +597,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +616,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +634,12 @@ SSetGprIdxOffSopp::SSetGprIdxOffSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_off", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -528,7 +659,12 @@ SSetGprIdxModeSopp::SSetGprIdxModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -542,7 +678,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vintrp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vintrp.cpp index c4c9d3744760..28df4a499730 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vintrp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vintrp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vintrp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,12 @@ VInterpP1F32Vintrp::VInterpP1F32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1F32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpP1F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_p1_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +56,12 @@ VInterpP2F32Vintrp::VInterpP2F32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +83,12 @@ VInterpMovF32Vintrp::VInterpMovF32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpMovF32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpMovF32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_mov_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp index a86069d40195..87e7a2920543 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,14 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +78,14 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,14 +99,20 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_readfirstlane_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -112,14 +131,19 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -137,14 +161,19 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_i32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -194,7 +223,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -244,7 +281,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -294,7 +339,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +397,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -394,7 +455,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +520,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +578,16 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -551,7 +637,16 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +696,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,14 +724,19 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -645,14 +754,19 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -702,7 +816,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -752,7 +875,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -802,7 +934,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -852,7 +993,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -871,14 +1021,19 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_U32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_u32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -896,14 +1051,19 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_U32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_u32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -922,14 +1082,19 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_TRUNC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_trunc_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -948,14 +1113,19 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CEIL_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_ceil_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -974,14 +1144,19 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RNDNE_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rndne_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1000,14 +1175,19 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FLOOR_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_floor_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1236,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1105,7 +1293,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1154,7 +1350,14 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1203,7 +1406,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1252,7 +1463,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1301,7 +1520,14 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1350,7 +1576,14 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1399,7 +1632,14 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1449,7 +1689,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1498,7 +1747,14 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1517,14 +1773,19 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RCP_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rcp_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1543,14 +1804,19 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RSQ_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rsq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1599,7 +1865,14 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1618,14 +1891,19 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SQRT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_sqrt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1674,7 +1952,14 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1723,7 +2008,14 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1772,7 +2064,14 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1821,7 +2120,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1870,7 +2177,14 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1919,7 +2233,14 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1968,7 +2289,14 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1987,14 +2315,20 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_exp_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2013,14 +2347,20 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_mant_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2039,14 +2379,19 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FRACT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_fract_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2096,7 +2441,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2146,7 +2500,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2159,7 +2522,11 @@ VClrexcpVop1::VClrexcpVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop1::validate_encoding( + "v_clrexcp_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2209,7 +2576,16 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2260,7 +2636,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2317,7 +2701,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2374,7 +2766,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2431,7 +2831,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2487,7 +2895,14 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2543,7 +2958,14 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2599,7 +3021,14 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2655,7 +3084,14 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2711,7 +3147,14 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2768,7 +3211,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2825,7 +3277,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2881,7 +3342,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2937,7 +3406,14 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2993,7 +3469,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3049,7 +3533,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3105,7 +3597,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3161,7 +3661,14 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3217,7 +3724,14 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3274,7 +3788,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3331,7 +3854,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3387,7 +3919,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3409,14 +3950,19 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_swap_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp index c336319fe86e..3032631c0961 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -67,7 +66,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +130,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +192,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +255,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +319,16 @@ VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_legacy_f32_sdwa" + : "v_mul_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +383,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +446,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +510,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +575,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +639,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +703,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +765,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -733,7 +827,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -788,7 +889,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -843,7 +951,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -898,7 +1013,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -954,7 +1076,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1010,7 +1141,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1066,7 +1206,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1270,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1176,7 +1332,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1231,7 +1394,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1260,12 +1430,17 @@ VMacF32Vop2::VMacF32Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_mac_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1290,14 +1465,19 @@ VMadmkF32Vop2::VMadmkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadmkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madmk_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1322,14 +1502,19 @@ VMadakF32Vop2::VMadakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madak_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1388,7 +1573,15 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1640,15 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1506,7 +1707,16 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1568,7 +1778,15 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1630,7 +1848,15 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1692,7 +1918,16 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1748,7 +1983,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1810,7 +2052,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1873,7 +2122,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1935,7 +2192,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1971,12 +2235,17 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_mac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2009,14 +2278,19 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADMK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madmk_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2049,14 +2323,19 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADAK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madak_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2118,7 +2397,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2180,7 +2466,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2243,7 +2536,15 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2306,7 +2607,15 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2369,7 +2678,16 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2432,7 +2750,16 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2495,7 +2822,16 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2557,7 +2893,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2619,7 +2962,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2681,7 +3031,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2743,7 +3100,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2805,7 +3169,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2867,7 +3238,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2929,7 +3307,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2990,7 +3376,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3045,7 +3438,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3101,7 +3501,15 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3130,12 +3538,18 @@ VDot2cF32F16Vop2::VDot2cF32F16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_f32_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3164,12 +3578,18 @@ VDot2cI32I16Vop2::VDot2cI32I16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_I32_I16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_i32_i16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_I32_I16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3198,12 +3618,18 @@ VDot4cI32I8Vop2::VDot4cI32I8Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT4C_I32_I8 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot4c_i32_i8_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT4C_I32_I8 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3232,12 +3658,18 @@ VDot8cI32I4Vop2::VDot8cI32I4Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT8C_I32_I4 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot8c_i32_i4_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT8C_I32_I4 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3266,12 +3698,17 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3300,12 +3737,17 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PK_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_pk_fmac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3360,7 +3802,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3.cpp index 1e36ce560a71..e1cd425f6df9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -30,7 +29,12 @@ VInterpP1F32Vop3::VInterpP1F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +57,12 @@ VInterpP2F32Vop3::VInterpP2F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +84,12 @@ VInterpMovF32Vop3::VInterpMovF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpMovF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpMovF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_mov_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -88,7 +102,11 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +123,11 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +144,12 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readfirstlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +166,11 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -156,7 +187,11 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -173,7 +208,11 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,7 +229,11 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -207,7 +250,11 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +271,11 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -241,7 +292,11 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +319,11 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +340,12 @@ VCvtRpiI32F32Vop3::VCvtRpiI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_rpi_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -298,7 +362,12 @@ VCvtFlrI32F32Vop3::VCvtFlrI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_flr_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +384,12 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_off_f32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -332,7 +406,11 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -349,7 +427,11 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +448,12 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -383,7 +470,12 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +492,12 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -417,7 +514,12 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -434,7 +536,11 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,11 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +578,11 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +599,11 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -502,7 +620,11 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -519,7 +641,11 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +662,11 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -553,7 +683,11 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -570,7 +704,11 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -587,7 +725,11 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -604,7 +746,11 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -621,7 +767,11 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +788,11 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +809,11 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -672,7 +830,12 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_iflag_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -689,7 +852,11 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -706,7 +873,11 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -723,7 +894,11 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -740,7 +915,11 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -757,7 +936,11 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -774,7 +957,11 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +978,11 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -808,7 +999,11 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -825,7 +1020,11 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -842,7 +1041,11 @@ VFfbhU32Vop3::VFfbhU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1062,11 @@ VFfblB32Vop3::VFfblB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -876,7 +1083,11 @@ VFfbhI32Vop3::VFfbhI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -893,7 +1104,12 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -910,7 +1126,12 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -927,7 +1148,11 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -944,7 +1169,12 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -961,7 +1191,12 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -974,7 +1209,11 @@ VClrexcpVop3::VClrexcpVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_clrexcp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -991,7 +1230,12 @@ VScreenPartition4seB32Vop3::VScreenPartition4seB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_screen_partition_4se_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1008,7 +1252,11 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1031,7 +1279,11 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1054,7 +1306,11 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1077,7 +1333,11 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1100,7 +1360,11 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1123,7 +1387,11 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1146,7 +1414,11 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1169,7 +1441,11 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1192,7 +1468,11 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1215,7 +1495,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1523,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1261,7 +1551,11 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1284,7 +1578,11 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1307,7 +1605,11 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1330,7 +1632,11 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1353,7 +1659,11 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1376,7 +1686,11 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1399,7 +1713,11 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,7 +1740,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1445,7 +1768,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1468,7 +1796,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sat_pk_u8_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1493,7 +1826,11 @@ VSwapB32Vop3::VSwapB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1514,7 +1851,12 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cndmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1533,7 +1875,11 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1552,7 +1898,11 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1571,7 +1921,11 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1590,7 +1944,12 @@ VMulLegacyF32Vop3::VMulLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1609,7 +1968,11 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1628,7 +1991,11 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1647,7 +2014,12 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1666,7 +2038,11 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1685,7 +2061,12 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1704,7 +2085,11 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1723,7 +2108,11 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1742,7 +2131,11 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1761,7 +2154,11 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1780,7 +2177,11 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1799,7 +2200,11 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,7 +2223,12 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1837,7 +2247,12 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1856,7 +2271,12 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1875,7 +2295,11 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1894,7 +2318,11 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1913,7 +2341,11 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1933,7 +2365,11 @@ VMacF32Vop3::VMacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1952,7 +2388,11 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1977,7 +2417,11 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2002,7 +2446,11 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2027,7 +2475,11 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2053,7 +2505,11 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2078,7 +2534,11 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2103,7 +2563,11 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2128,7 +2592,11 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2153,7 +2621,11 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2178,7 +2650,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2203,7 +2680,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2228,7 +2710,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2253,7 +2740,11 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2278,7 +2769,11 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2303,7 +2798,11 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2328,7 +2827,11 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2353,7 +2856,11 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2378,7 +2885,11 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2403,7 +2914,11 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2428,7 +2943,11 @@ VAddU32Vop3::VAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2447,7 +2966,11 @@ VSubU32Vop3::VSubU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2466,7 +2989,11 @@ VSubrevU32Vop3::VSubrevU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2486,7 +3013,12 @@ VDot2cF32F16Vop3::VDot2cF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2506,7 +3038,12 @@ VDot2cI32I16Vop3::VDot2cI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2526,7 +3063,12 @@ VDot4cI32I8Vop3::VDot4cI32I8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot4c_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2546,7 +3088,12 @@ VDot8cI32I4Vop3::VDot8cI32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot8c_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2566,7 +3113,11 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2586,7 +3137,11 @@ VPkFmacF16Vop3::VPkFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pk_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2605,7 +3160,11 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2626,7 +3185,12 @@ VMadLegacyF32Vop3::VMadLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2647,7 +3211,11 @@ VMadF32Vop3::VMadF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2668,7 +3236,11 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2689,7 +3261,11 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2710,7 +3286,11 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubeid_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2731,7 +3311,11 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubesc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2752,7 +3336,11 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubetc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2773,7 +3361,11 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubema_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2794,7 +3386,11 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2815,7 +3411,11 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2836,7 +3436,11 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2857,7 +3461,11 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2878,7 +3486,11 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2899,7 +3511,11 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lerp_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2920,7 +3536,12 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbit_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2941,7 +3562,12 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbyte_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2962,7 +3588,11 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2983,7 +3613,11 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3004,7 +3638,11 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3025,7 +3663,11 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3046,7 +3688,11 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3067,7 +3713,11 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3088,7 +3738,11 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3109,7 +3763,11 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3130,7 +3788,11 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3151,7 +3813,11 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3172,7 +3838,11 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3193,7 +3863,11 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3214,7 +3888,11 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3235,7 +3913,12 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3256,7 +3939,12 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3277,7 +3965,12 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3301,7 +3994,12 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3325,7 +4023,12 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3346,7 +4049,11 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_msad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3367,7 +4074,12 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_qsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3388,7 +4100,12 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3409,7 +4126,12 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3430,7 +4152,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3457,7 +4184,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3484,7 +4216,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3511,7 +4248,11 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_perm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3532,7 +4273,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3559,7 +4305,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3585,7 +4336,12 @@ VCvtPkaccumU8F32Vop3::VCvtPkaccumU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkaccum_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3606,7 +4362,11 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3627,7 +4387,11 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3648,7 +4412,11 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3669,7 +4437,11 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3696,7 +4468,11 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3723,7 +4499,11 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3750,7 +4530,11 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3777,7 +4561,11 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3804,7 +4592,11 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3831,7 +4623,11 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3858,7 +4654,11 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3885,7 +4685,11 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3912,7 +4716,12 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3933,7 +4742,12 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_lshl_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3954,7 +4768,11 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3975,7 +4793,11 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3996,7 +4818,11 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4017,7 +4843,11 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4038,7 +4868,11 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4065,7 +4899,11 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4092,7 +4930,11 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4119,7 +4961,11 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4146,7 +4992,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4171,7 +5022,12 @@ VInterpP1llF16Vop3::VInterpP1llF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1llF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1llF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1ll_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4192,7 +5048,12 @@ VInterpP1lvF16Vop3::VInterpP1lvF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1lvF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1lvF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1lv_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4213,7 +5074,12 @@ VInterpP2LegacyF16Vop3::VInterpP2LegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2LegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2LegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4234,7 +5100,12 @@ VInterpP2F16Vop3::VInterpP2F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4253,7 +5124,11 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4272,7 +5147,11 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4291,7 +5170,11 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4310,7 +5193,11 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4329,7 +5216,11 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4348,7 +5239,11 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4367,7 +5262,11 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4386,7 +5285,11 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4405,7 +5308,11 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4424,7 +5331,12 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4444,7 +5356,12 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_writelane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4463,7 +5380,12 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bcnt_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4482,7 +5404,12 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_lo_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4501,7 +5428,12 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_hi_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4520,7 +5452,12 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4539,7 +5476,12 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4558,7 +5500,12 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4577,7 +5524,12 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trig_preop_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4596,7 +5548,11 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4615,7 +5571,12 @@ VCvtPknormI16F32Vop3::VCvtPknormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4634,7 +5595,12 @@ VCvtPknormU16F32Vop3::VCvtPknormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4653,7 +5619,12 @@ VCvtPkrtzF16F32Vop3::VCvtPkrtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkrtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4672,7 +5643,12 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u16_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4691,7 +5667,12 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_i16_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4710,7 +5691,12 @@ VCvtPknormI16F16Vop3::VCvtPknormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4729,7 +5715,12 @@ VCvtPknormU16F16Vop3::VCvtPknormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4748,7 +5739,11 @@ VAddI32Vop3::VAddI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4767,7 +5762,11 @@ VSubI32Vop3::VSubI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4786,7 +5785,11 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4811,7 +5814,11 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4836,7 +5843,12 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pack_b32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4855,7 +5867,12 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4878,7 +5895,12 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4897,7 +5919,12 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4920,7 +5947,12 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4939,7 +5971,12 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4962,7 +5999,12 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4981,7 +6023,11 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5000,7 +6046,11 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5019,7 +6069,11 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5038,7 +6092,11 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5057,7 +6115,11 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5076,7 +6138,11 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5095,7 +6161,11 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5114,7 +6184,11 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5133,7 +6207,11 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5152,7 +6230,11 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5171,7 +6253,11 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5190,7 +6276,11 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5209,7 +6299,11 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5228,7 +6322,11 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5247,7 +6345,11 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5266,7 +6368,11 @@ VCmpTruF16Vop3::VCmpTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5289,7 +6395,11 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5312,7 +6422,11 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5335,7 +6449,11 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5358,7 +6476,11 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5381,7 +6503,11 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5404,7 +6530,11 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5427,7 +6557,11 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5450,7 +6584,11 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5473,7 +6611,11 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5496,7 +6638,12 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5519,7 +6666,12 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5542,7 +6694,12 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5565,7 +6722,12 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5588,7 +6750,12 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5611,7 +6778,12 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5634,7 +6806,12 @@ VCmpxTruF16Vop3::VCmpxTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5653,7 +6830,11 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5672,7 +6853,11 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5691,7 +6876,11 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5710,7 +6899,11 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5729,7 +6922,11 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5748,7 +6945,11 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5767,7 +6968,11 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5786,7 +6991,11 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5805,7 +7014,11 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5824,7 +7037,11 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5843,7 +7060,11 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5862,7 +7083,11 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5881,7 +7106,11 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5900,7 +7129,11 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5919,7 +7152,11 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5938,7 +7175,11 @@ VCmpTruF32Vop3::VCmpTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5961,7 +7202,11 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5984,7 +7229,11 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6007,7 +7256,11 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6030,7 +7283,11 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6053,7 +7310,11 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6076,7 +7337,11 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6099,7 +7364,11 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6122,7 +7391,11 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6145,7 +7418,11 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6168,7 +7445,12 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6191,7 +7473,12 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6214,7 +7501,12 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6237,7 +7529,12 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6260,7 +7557,12 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6283,7 +7585,12 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6306,7 +7613,12 @@ VCmpxTruF32Vop3::VCmpxTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6325,7 +7637,11 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6344,7 +7660,11 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6363,7 +7683,11 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6382,7 +7706,11 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6401,7 +7729,11 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6420,7 +7752,11 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6439,7 +7775,11 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6458,7 +7798,11 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6477,7 +7821,11 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6496,7 +7844,11 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6515,7 +7867,11 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6534,7 +7890,11 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6553,7 +7913,11 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6572,7 +7936,11 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6591,7 +7959,11 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6610,7 +7982,11 @@ VCmpTruF64Vop3::VCmpTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6633,7 +8009,11 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6656,7 +8036,11 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6679,7 +8063,11 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6702,7 +8090,11 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6725,7 +8117,11 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6748,7 +8144,11 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6771,7 +8171,11 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6794,7 +8198,11 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6817,7 +8225,11 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6840,7 +8252,12 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6863,7 +8280,12 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6886,7 +8308,12 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6909,7 +8336,12 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6932,7 +8364,12 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6955,7 +8392,12 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6978,7 +8420,12 @@ VCmpxTruF64Vop3::VCmpxTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6997,7 +8444,11 @@ VCmpFI16Vop3::VCmpFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7016,7 +8467,11 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7035,7 +8490,11 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7054,7 +8513,11 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7073,7 +8536,11 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7092,7 +8559,11 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7111,7 +8582,11 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7130,7 +8605,11 @@ VCmpTI16Vop3::VCmpTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7149,7 +8628,11 @@ VCmpFU16Vop3::VCmpFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7168,7 +8651,11 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7187,7 +8674,11 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7206,7 +8697,11 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7225,7 +8720,11 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7244,7 +8743,11 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7263,7 +8766,11 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7282,7 +8789,11 @@ VCmpTU16Vop3::VCmpTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7305,7 +8816,11 @@ VCmpxFI16Vop3::VCmpxFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7328,7 +8843,11 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7351,7 +8870,11 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7374,7 +8897,11 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7397,7 +8924,11 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7420,7 +8951,11 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7443,7 +8978,11 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7466,7 +9005,11 @@ VCmpxTI16Vop3::VCmpxTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7489,7 +9032,11 @@ VCmpxFU16Vop3::VCmpxFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7512,7 +9059,11 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7535,7 +9086,11 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7558,7 +9113,11 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7581,7 +9140,11 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7604,7 +9167,11 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7627,7 +9194,11 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7650,7 +9221,11 @@ VCmpxTU16Vop3::VCmpxTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7669,7 +9244,11 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7688,7 +9267,11 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7707,7 +9290,11 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7726,7 +9313,11 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7745,7 +9336,11 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7764,7 +9359,11 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7783,7 +9382,11 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7802,7 +9405,11 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7821,7 +9428,11 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7840,7 +9451,11 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7859,7 +9474,11 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7878,7 +9497,11 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7897,7 +9520,11 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7916,7 +9543,11 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7935,7 +9566,11 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7954,7 +9589,11 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7977,7 +9616,11 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8000,7 +9643,11 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8023,7 +9670,11 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8046,7 +9697,11 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8069,7 +9724,11 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8092,7 +9751,11 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8115,7 +9778,11 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8138,7 +9805,11 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8161,7 +9832,11 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8184,7 +9859,11 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8207,7 +9886,11 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8230,7 +9913,11 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8253,7 +9940,11 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8276,7 +9967,11 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8299,7 +9994,11 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8322,7 +10021,11 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8341,7 +10044,11 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8360,7 +10067,11 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8379,7 +10090,11 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8398,7 +10113,11 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8417,7 +10136,11 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8436,7 +10159,11 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8455,7 +10182,11 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8474,7 +10205,11 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8493,7 +10228,11 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8512,7 +10251,11 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8531,7 +10274,11 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8550,7 +10297,11 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8569,7 +10320,11 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8588,7 +10343,11 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8607,7 +10366,11 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8626,7 +10389,11 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8649,7 +10416,11 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8672,7 +10443,11 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8695,7 +10470,11 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8718,7 +10497,11 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8741,7 +10524,11 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8764,7 +10551,11 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8787,7 +10578,11 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8810,7 +10605,11 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8833,7 +10632,11 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8856,7 +10659,11 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8879,7 +10686,11 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8902,7 +10713,11 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8925,7 +10740,11 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8948,7 +10767,11 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8971,7 +10794,11 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8994,7 +10821,11 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9015,7 +10846,12 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9036,7 +10872,12 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9057,7 +10898,12 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9080,7 +10926,12 @@ VAddcCoU32Vop3SdstEnc::VAddcCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_addc_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9103,7 +10954,12 @@ VSubbCoU32Vop3SdstEnc::VSubbCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subb_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9126,7 +10982,12 @@ VSubbrevCoU32Vop3SdstEnc::VSubbrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subbrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9149,7 +11010,12 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9172,7 +11038,12 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9195,7 +11066,12 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_u64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9218,7 +11094,12 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_i64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3p.cpp index e173ba22f65a..2857372b05ee 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -48,7 +51,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +75,11 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,7 +98,11 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +121,12 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -124,7 +145,12 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +169,12 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +193,11 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -181,7 +216,11 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -202,7 +241,11 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +264,11 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -240,7 +287,11 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +310,11 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -278,7 +333,11 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +358,11 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +381,11 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +404,11 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +427,11 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +450,11 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -396,7 +475,12 @@ VMadMixF32Vop3p::VMadMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mix_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +502,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixlo_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -446,7 +535,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixhi_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +567,12 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +593,12 @@ VDot2I32I16Vop3p::VDot2I32I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -515,7 +619,12 @@ VDot2U32U16Vop3p::VDot2U32U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +645,12 @@ VDot4I32I8Vop3p::VDot4I32I8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +671,12 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -578,7 +697,12 @@ VDot8I32I4Vop3p::VDot8I32I4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -599,7 +723,12 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_u32_u4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,7 +749,12 @@ VAccvgprReadVop3p::VAccvgprReadVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_read", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +772,12 @@ VAccvgprWriteVop3p::VAccvgprWriteVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_write", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -664,7 +803,12 @@ VMfmaF3232x32x1f32Vop3pMfma::VMfmaF3232x32x1f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x1f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -690,7 +834,12 @@ VMfmaF3216x16x1f32Vop3pMfma::VMfmaF3216x16x1f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x1f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -716,7 +865,12 @@ VMfmaF324x4x1f32Vop3pMfma::VMfmaF324x4x1f32Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x1f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -742,7 +896,12 @@ VMfmaF3232x32x2f32Vop3pMfma::VMfmaF3232x32x2f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x2f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -768,7 +927,12 @@ VMfmaF3216x16x4f32Vop3pMfma::VMfmaF3216x16x4f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -794,7 +958,12 @@ VMfmaF3232x32x4f16Vop3pMfma::VMfmaF3232x32x4f16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -820,7 +989,12 @@ VMfmaF3216x16x4f16Vop3pMfma::VMfmaF3216x16x4f16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -846,7 +1020,12 @@ VMfmaF324x4x4f16Vop3pMfma::VMfmaF324x4x4f16Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -872,7 +1051,12 @@ VMfmaF3232x32x8f16Vop3pMfma::VMfmaF3232x32x8f16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -898,7 +1082,13 @@ VMfmaF3216x16x16f16Vop3pMfma::VMfmaF3216x16x16f16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1114,12 @@ VMfmaI3232x32x4i8Vop3pMfma::VMfmaI3232x32x4i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x4i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -950,7 +1145,12 @@ VMfmaI3216x16x4i8Vop3pMfma::VMfmaI3216x16x4i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x4i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -976,7 +1176,12 @@ VMfmaI324x4x4i8Vop3pMfma::VMfmaI324x4x4i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_4x4x4i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1002,7 +1207,12 @@ VMfmaI3232x32x8i8Vop3pMfma::VMfmaI3232x32x8i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x8i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1028,7 +1238,12 @@ VMfmaI3216x16x16i8Vop3pMfma::VMfmaI3216x16x16i8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x16i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1054,7 +1269,13 @@ VMfmaF3232x32x2bf16Vop3pMfma::VMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x2bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1080,7 +1301,13 @@ VMfmaF3216x16x2bf16Vop3pMfma::VMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x2bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1106,7 +1333,12 @@ VMfmaF324x4x2bf16Vop3pMfma::VMfmaF324x4x2bf16Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x2bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1132,7 +1364,13 @@ VMfmaF3232x32x4bf16Vop3pMfma::VMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1158,7 +1396,13 @@ VMfmaF3216x16x8bf16Vop3pMfma::VMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x8bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp index e756ef009eea..fb1f981a4cec 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,8 +30,6 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -60,7 +57,18 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -85,8 +93,6 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -116,7 +122,18 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,15 +154,21 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -168,17 +191,23 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -202,8 +231,6 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -231,7 +258,18 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -257,8 +295,6 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -288,7 +324,18 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -311,8 +358,6 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -340,7 +385,17 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -364,8 +419,6 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -393,7 +446,17 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -417,8 +480,6 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -446,7 +507,17 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -470,8 +541,6 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -499,7 +568,17 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -523,8 +602,6 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -552,7 +629,17 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -576,8 +663,6 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -605,7 +690,17 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -629,8 +724,6 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -658,7 +751,17 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -681,8 +784,6 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -710,7 +811,17 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -733,8 +844,6 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -762,7 +871,17 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -786,8 +905,6 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -815,7 +932,17 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -839,8 +966,6 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -868,7 +993,17 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -892,8 +1027,6 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -921,7 +1054,17 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -945,8 +1088,6 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -974,7 +1115,17 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -998,8 +1149,6 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1027,7 +1176,17 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1051,8 +1210,6 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1080,7 +1237,17 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1104,8 +1271,6 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1133,7 +1298,17 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1159,8 +1334,6 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1190,7 +1363,17 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1216,8 +1399,6 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1247,7 +1428,17 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1273,8 +1464,6 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1304,7 +1493,17 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1330,8 +1529,6 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1361,7 +1558,17 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1387,8 +1594,6 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1418,7 +1623,17 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1444,8 +1659,6 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1475,7 +1688,17 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1501,8 +1724,6 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1532,7 +1753,17 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1558,8 +1789,6 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1589,7 +1818,17 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1615,8 +1854,6 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1646,7 +1883,17 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1672,8 +1919,6 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1703,7 +1948,18 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1729,8 +1985,6 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1760,7 +2014,18 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1786,8 +2051,6 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1817,7 +2080,18 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1843,8 +2117,6 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1874,7 +2146,18 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1900,8 +2183,6 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1931,7 +2212,18 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1957,8 +2249,6 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1988,7 +2278,18 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2014,8 +2315,6 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2045,7 +2344,18 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2067,8 +2377,6 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2096,7 +2404,17 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2119,8 +2437,6 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2148,7 +2464,17 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2171,8 +2497,6 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2200,7 +2524,17 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2223,8 +2557,6 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2252,7 +2584,17 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2275,8 +2617,6 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2304,7 +2644,17 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2327,8 +2677,6 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2356,7 +2704,17 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2379,8 +2737,6 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2408,7 +2764,17 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2430,8 +2796,6 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2459,7 +2823,17 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2481,8 +2855,6 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2510,7 +2882,17 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2533,8 +2915,6 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2562,7 +2942,17 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2585,8 +2975,6 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2614,7 +3002,17 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2637,8 +3035,6 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2666,7 +3062,17 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2689,8 +3095,6 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2718,7 +3122,17 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2741,8 +3155,6 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2770,7 +3182,17 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2793,8 +3215,6 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2822,7 +3242,17 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2845,8 +3275,6 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2874,7 +3302,17 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2899,8 +3337,6 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2930,7 +3366,17 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2955,8 +3401,6 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2986,7 +3430,17 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3011,8 +3465,6 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3042,7 +3494,17 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3067,8 +3529,6 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3098,7 +3558,17 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3123,8 +3593,6 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3154,7 +3622,17 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3179,8 +3657,6 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3210,7 +3686,17 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3235,8 +3721,6 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3266,7 +3750,17 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3291,8 +3785,6 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3322,7 +3814,17 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3347,8 +3849,6 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3378,7 +3878,17 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3403,8 +3913,6 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3434,7 +3942,18 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3459,8 +3978,6 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3490,7 +4007,18 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3515,8 +4043,6 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3546,7 +4072,18 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3571,8 +4108,6 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3602,7 +4137,18 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3627,8 +4173,6 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3658,7 +4202,18 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3683,8 +4238,6 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3714,7 +4267,18 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3739,8 +4303,6 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3770,7 +4332,18 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3791,15 +4364,20 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3820,15 +4398,20 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3849,15 +4432,20 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3878,15 +4466,20 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3907,15 +4500,20 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3936,15 +4534,20 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3965,15 +4568,20 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3994,15 +4602,20 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4023,15 +4636,20 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4052,15 +4670,20 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4081,15 +4704,20 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4110,15 +4738,20 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4139,15 +4772,20 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4168,15 +4806,20 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4197,15 +4840,20 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4226,15 +4874,20 @@ VCmpTruF64Vopc::VCmpTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4257,17 +4910,22 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4290,17 +4948,22 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4323,17 +4986,22 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4356,17 +5024,22 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4389,17 +5062,22 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4422,17 +5100,22 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4455,17 +5138,22 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4488,17 +5176,22 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4521,17 +5214,22 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4554,17 +5252,23 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4587,17 +5291,23 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4620,17 +5330,23 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4653,17 +5369,23 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4686,17 +5408,23 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4719,17 +5447,23 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4752,17 +5486,23 @@ VCmpxTruF64Vopc::VCmpxTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4785,8 +5525,6 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4814,7 +5552,17 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4838,8 +5586,6 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4867,7 +5613,17 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4891,8 +5647,6 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4920,7 +5674,17 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4944,8 +5708,6 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4973,7 +5735,17 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4997,8 +5769,6 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5026,7 +5796,17 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5050,8 +5830,6 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5079,7 +5857,17 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5103,8 +5891,6 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5132,7 +5918,17 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5155,8 +5951,6 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5184,7 +5978,17 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5207,8 +6011,6 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5236,7 +6038,17 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5260,8 +6072,6 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5289,7 +6099,17 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5313,8 +6133,6 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5342,7 +6160,17 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5366,8 +6194,6 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5395,7 +6221,17 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5419,8 +6255,6 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5448,7 +6282,17 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5472,8 +6316,6 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5501,7 +6343,17 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5525,8 +6377,6 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5554,7 +6404,17 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5577,8 +6437,6 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5606,7 +6464,17 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5632,8 +6500,6 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5663,7 +6529,17 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5689,8 +6565,6 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5720,7 +6594,17 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5746,8 +6630,6 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5777,7 +6659,17 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5803,8 +6695,6 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5834,7 +6724,17 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5860,8 +6760,6 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5891,7 +6789,17 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5917,8 +6825,6 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5948,7 +6854,17 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5974,8 +6890,6 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6005,7 +6919,17 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6031,8 +6955,6 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6062,7 +6984,17 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6088,8 +7020,6 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6119,7 +7049,17 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6145,8 +7085,6 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6176,7 +7114,17 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6202,8 +7150,6 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6233,7 +7179,17 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6259,8 +7215,6 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6290,7 +7244,17 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6316,8 +7280,6 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6347,7 +7309,17 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6373,8 +7345,6 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6404,7 +7374,17 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6430,8 +7410,6 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6461,7 +7439,17 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6487,8 +7475,6 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6518,7 +7504,17 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6540,8 +7536,6 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6569,7 +7563,17 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6592,8 +7596,6 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6621,7 +7623,17 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6644,8 +7656,6 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6673,7 +7683,17 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6696,8 +7716,6 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6725,7 +7743,17 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6748,8 +7776,6 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6777,7 +7803,17 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6800,8 +7836,6 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6829,7 +7863,17 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6852,8 +7896,6 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6881,7 +7923,17 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6903,8 +7955,6 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6932,7 +7982,17 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6954,8 +8014,6 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6983,7 +8041,17 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7006,8 +8074,6 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7035,7 +8101,17 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7058,8 +8134,6 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7087,7 +8161,17 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7110,8 +8194,6 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7139,7 +8221,17 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7162,8 +8254,6 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7191,7 +8281,17 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7214,8 +8314,6 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7243,7 +8341,17 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7266,8 +8374,6 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7295,7 +8401,17 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7317,8 +8433,6 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7346,7 +8460,17 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7371,8 +8495,6 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7402,7 +8524,17 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7427,8 +8559,6 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7458,7 +8588,17 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7483,8 +8623,6 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7514,7 +8652,17 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7539,8 +8687,6 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7570,7 +8716,17 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7595,8 +8751,6 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7626,7 +8780,17 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7651,8 +8815,6 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7682,7 +8844,17 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7707,8 +8879,6 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7738,7 +8908,17 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7763,8 +8943,6 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7794,7 +8972,17 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7819,8 +9007,6 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7850,7 +9036,17 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7875,8 +9071,6 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7906,7 +9100,17 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7931,8 +9135,6 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7962,7 +9164,17 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7987,8 +9199,6 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8018,7 +9228,17 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8043,8 +9263,6 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8074,7 +9292,17 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8099,8 +9327,6 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8130,7 +9356,17 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8155,8 +9391,6 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8186,7 +9420,17 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8211,8 +9455,6 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8242,7 +9484,17 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8263,15 +9515,20 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8292,15 +9549,20 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8321,15 +9583,20 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8350,15 +9617,20 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8379,15 +9651,20 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8408,15 +9685,20 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8437,15 +9719,20 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8466,15 +9753,20 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8495,15 +9787,20 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8524,15 +9821,20 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8553,15 +9855,20 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8582,15 +9889,20 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8611,15 +9923,20 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8640,15 +9957,20 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8669,15 +9991,20 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8698,15 +10025,20 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8729,17 +10061,22 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8762,17 +10099,22 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8795,17 +10137,22 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8828,17 +10175,22 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8861,17 +10213,22 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8894,17 +10251,22 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8927,17 +10289,22 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8960,17 +10327,22 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8993,17 +10365,22 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9026,17 +10403,22 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9059,17 +10441,22 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9092,17 +10479,22 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9125,17 +10517,22 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9158,17 +10555,22 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9191,17 +10593,22 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9224,17 +10631,22 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.cpp index 680f690b9539..c75f134711bc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3p.h" -#include "util/except.h" #include #include #include @@ -15,1419 +14,1866 @@ namespace rocjitsu { namespace cdna2 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferInvl2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbinvl1Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbinvl1VolMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbl2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode); -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16bf161kVop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4bf161kVop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x4bf161kVop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8bf161kVop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x4bf161kVop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF6416x16x4f64Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF644x4x4f64Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMovB32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferInvl2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbinvl1Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbinvl1VolMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbl2Mubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprMovB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprMovB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x4bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x4bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF6416x16x4f64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF644x4x4f64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMovB32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMimg(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1444,83 +1890,96 @@ struct DecoderImpl { static const std::array sub_decode_mimg; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMimg(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mimg::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mimg[op.op](opcode); + return sub_decode_mimg[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h index f2444ea7d812..4125f3d544ff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA2_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace cdna2 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 4; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace cdna2 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/ds.cpp index 59ea67fafda6..e5a98e5bff8f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/ds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/ds.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -62,7 +65,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -89,7 +96,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +127,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +158,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -170,7 +189,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +220,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +251,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -251,7 +282,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -278,7 +313,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -305,7 +344,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -332,7 +375,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +412,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +441,11 @@ DsWriteB32Ds::DsWriteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +476,11 @@ DsWrite2B32Ds::DsWrite2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +511,12 @@ DsWrite2st64B32Ds::DsWrite2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +549,11 @@ DsCmpstB32Ds::DsCmpstB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -518,7 +586,11 @@ DsCmpstF32Ds::DsCmpstF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +617,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +648,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -585,7 +665,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -612,7 +696,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -637,7 +725,12 @@ DsWriteAddtidB32Ds::DsWriteAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +755,11 @@ DsWriteB8Ds::DsWriteB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +784,11 @@ DsWriteB16Ds::DsWriteB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -720,7 +821,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -753,7 +858,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -786,7 +895,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -819,7 +932,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -852,7 +969,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -885,7 +1006,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -918,7 +1043,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1080,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -984,7 +1117,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1154,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1191,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1228,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1122,7 +1271,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1309,12 @@ DsWrxchgRtnB32Ds::DsWrxchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1194,7 +1353,12 @@ DsWrxchg2RtnB32Ds::DsWrxchg2RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1233,7 +1397,12 @@ DsWrxchg2st64RtnB32Ds::DsWrxchg2st64RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1272,7 +1441,12 @@ DsCmpstRtnB32Ds::DsCmpstRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1311,7 +1485,12 @@ DsCmpstRtnF32Ds::DsCmpstRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1344,7 +1523,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1377,7 +1560,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1415,7 +1602,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1448,7 +1639,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1473,7 +1668,11 @@ DsReadB32Ds::DsReadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1498,7 +1697,11 @@ DsRead2B32Ds::DsRead2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1523,7 +1726,12 @@ DsRead2st64B32Ds::DsRead2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1548,7 +1756,11 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1573,7 +1785,11 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1598,7 +1814,11 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1623,7 +1843,11 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1868,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1671,7 +1899,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1698,7 +1930,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1725,7 +1962,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1752,7 +1993,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1779,7 +2024,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1806,7 +2055,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1833,7 +2086,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1860,7 +2117,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1887,7 +2148,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1914,7 +2179,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1941,7 +2210,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1968,7 +2241,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1995,7 +2272,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2022,7 +2303,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2055,7 +2340,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2080,7 +2369,11 @@ DsWriteB64Ds::DsWriteB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2111,7 +2404,11 @@ DsWrite2B64Ds::DsWrite2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2142,7 +2439,12 @@ DsWrite2st64B64Ds::DsWrite2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2175,7 +2477,11 @@ DsCmpstB64Ds::DsCmpstB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2208,7 +2514,11 @@ DsCmpstF64Ds::DsCmpstF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2235,7 +2545,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2262,7 +2576,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2287,7 +2605,12 @@ DsWriteB8D16HiDs::DsWriteB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2312,7 +2635,12 @@ DsWriteB16D16HiDs::DsWriteB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2337,7 +2665,11 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2368,7 +2700,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2399,7 +2736,11 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2430,7 +2771,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2461,7 +2807,11 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2492,7 +2842,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2525,7 +2880,11 @@ DsAddF64Ds::DsAddF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2558,7 +2917,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2591,7 +2954,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2624,7 +2991,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2657,7 +3028,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2690,7 +3065,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2723,7 +3102,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2756,7 +3139,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2789,7 +3176,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2822,7 +3213,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2855,7 +3250,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2888,7 +3287,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2921,7 +3324,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2960,7 +3367,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2993,7 +3405,12 @@ DsWrxchgRtnB64Ds::DsWrxchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3032,7 +3449,12 @@ DsWrxchg2RtnB64Ds::DsWrxchg2RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3071,7 +3493,12 @@ DsWrxchg2st64RtnB64Ds::DsWrxchg2st64RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3110,7 +3537,12 @@ DsCmpstRtnB64Ds::DsCmpstRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3149,7 +3581,12 @@ DsCmpstRtnF64Ds::DsCmpstRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3182,7 +3619,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3215,7 +3656,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3240,7 +3685,11 @@ DsReadB64Ds::DsReadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3265,7 +3714,11 @@ DsRead2B64Ds::DsRead2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3290,7 +3743,12 @@ DsRead2st64B64Ds::DsRead2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3323,7 +3781,11 @@ DsAddRtnF64Ds::DsAddRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3356,7 +3818,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3369,7 +3836,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3384,7 +3856,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3397,7 +3873,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3412,7 +3892,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3425,7 +3909,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3440,7 +3928,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3465,7 +3957,12 @@ DsReadAddtidB32Ds::DsReadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3490,7 +3987,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3515,7 +4016,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3540,7 +4045,11 @@ DsWriteB96Ds::DsWriteB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3565,7 +4074,11 @@ DsWriteB128Ds::DsWriteB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3590,7 +4103,11 @@ DsReadB96Ds::DsReadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3615,7 +4132,11 @@ DsReadB128Ds::DsReadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h index 74abb93c8848..e6d9c8335a57 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna2/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/flat.cpp index 293809cc8c41..8f5832726848 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/flat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/flat.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -47,7 +46,12 @@ FlatLoadUbyteFlat::FlatLoadUbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,7 +90,12 @@ FlatLoadSbyteFlat::FlatLoadSbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -125,7 +134,12 @@ FlatLoadUshortFlat::FlatLoadUshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -164,7 +178,12 @@ FlatLoadSshortFlat::FlatLoadSshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +222,12 @@ FlatLoadDwordFlat::FlatLoadDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -242,7 +266,12 @@ FlatLoadDwordx2Flat::FlatLoadDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +310,12 @@ FlatLoadDwordx3Flat::FlatLoadDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -320,7 +354,12 @@ FlatLoadDwordx4Flat::FlatLoadDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +398,12 @@ FlatStoreByteFlat::FlatStoreByteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +442,12 @@ FlatStoreByteD16HiFlat::FlatStoreByteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +486,12 @@ FlatStoreShortFlat::FlatStoreShortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +530,12 @@ FlatStoreShortD16HiFlat::FlatStoreShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -515,7 +574,12 @@ FlatStoreDwordFlat::FlatStoreDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +618,12 @@ FlatStoreDwordx2Flat::FlatStoreDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +662,12 @@ FlatStoreDwordx3Flat::FlatStoreDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -632,7 +706,12 @@ FlatStoreDwordx4Flat::FlatStoreDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -671,7 +750,12 @@ FlatLoadUbyteD16Flat::FlatLoadUbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +801,12 @@ FlatLoadUbyteD16HiFlat::FlatLoadUbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -763,7 +852,12 @@ FlatLoadSbyteD16Flat::FlatLoadSbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +903,12 @@ FlatLoadSbyteD16HiFlat::FlatLoadSbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +954,12 @@ FlatLoadShortD16Flat::FlatLoadShortD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -901,7 +1005,12 @@ FlatLoadShortD16HiFlat::FlatLoadShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -954,7 +1063,12 @@ FlatAtomicSwapFlat::FlatAtomicSwapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1000,7 +1114,12 @@ FlatAtomicCmpswapFlat::FlatAtomicCmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1046,7 +1165,12 @@ FlatAtomicAddFlat::FlatAtomicAddFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1092,7 +1216,12 @@ FlatAtomicSubFlat::FlatAtomicSubFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1267,12 @@ FlatAtomicSminFlat::FlatAtomicSminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1184,7 +1318,12 @@ FlatAtomicUminFlat::FlatAtomicUminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1230,7 +1369,12 @@ FlatAtomicSmaxFlat::FlatAtomicSmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1276,7 +1420,12 @@ FlatAtomicUmaxFlat::FlatAtomicUmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1322,7 +1471,12 @@ FlatAtomicAndFlat::FlatAtomicAndFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1368,7 +1522,12 @@ FlatAtomicOrFlat::FlatAtomicOrFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1414,7 +1573,12 @@ FlatAtomicXorFlat::FlatAtomicXorFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1460,7 +1624,12 @@ FlatAtomicIncFlat::FlatAtomicIncFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1506,7 +1675,12 @@ FlatAtomicDecFlat::FlatAtomicDecFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1552,7 +1726,12 @@ FlatAtomicAddF64Flat::FlatAtomicAddF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1598,7 +1777,12 @@ FlatAtomicMinF64Flat::FlatAtomicMinF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1828,12 @@ FlatAtomicMaxF64Flat::FlatAtomicMaxF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1690,7 +1879,12 @@ FlatAtomicSwapX2Flat::FlatAtomicSwapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1736,7 +1930,12 @@ FlatAtomicCmpswapX2Flat::FlatAtomicCmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1782,7 +1981,12 @@ FlatAtomicAddX2Flat::FlatAtomicAddX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1828,7 +2032,12 @@ FlatAtomicSubX2Flat::FlatAtomicSubX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1874,7 +2083,12 @@ FlatAtomicSminX2Flat::FlatAtomicSminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1920,7 +2134,12 @@ FlatAtomicUminX2Flat::FlatAtomicUminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1966,7 +2185,12 @@ FlatAtomicSmaxX2Flat::FlatAtomicSmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2012,7 +2236,12 @@ FlatAtomicUmaxX2Flat::FlatAtomicUmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2058,7 +2287,12 @@ FlatAtomicAndX2Flat::FlatAtomicAndX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2104,7 +2338,12 @@ FlatAtomicOrX2Flat::FlatAtomicOrX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2150,7 +2389,12 @@ FlatAtomicXorX2Flat::FlatAtomicXorX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2196,7 +2440,12 @@ FlatAtomicIncX2Flat::FlatAtomicIncX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2242,7 +2491,12 @@ FlatAtomicDecX2Flat::FlatAtomicDecX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mimg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mimg.cpp index 97b5f99cf9ac..60461fd33b0c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mimg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mimg.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/mimg.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -30,7 +29,11 @@ ImageLoadMimg::ImageLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +56,12 @@ ImageLoadMipMimg::ImageLoadMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -76,7 +84,12 @@ ImageLoadPckMimg::ImageLoadPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -99,7 +112,12 @@ ImageLoadPckSgnMimg::ImageLoadPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +140,12 @@ ImageLoadMipPckMimg::ImageLoadMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -145,7 +168,12 @@ ImageLoadMipPckSgnMimg::ImageLoadMipPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +196,11 @@ ImageStoreMimg::ImageStoreMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +223,12 @@ ImageStoreMipMimg::ImageStoreMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +251,12 @@ ImageStorePckMimg::ImageStorePckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -237,7 +279,12 @@ ImageStoreMipPckMimg::ImageStoreMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -260,7 +307,12 @@ ImageGetResinfoMimg::ImageGetResinfoMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +336,12 @@ ImageAtomicSwapMimg::ImageAtomicSwapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -308,7 +365,12 @@ ImageAtomicCmpswapMimg::ImageAtomicCmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -332,7 +394,12 @@ ImageAtomicAddMimg::ImageAtomicAddMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +423,12 @@ ImageAtomicSubMimg::ImageAtomicSubMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -380,7 +452,12 @@ ImageAtomicSminMimg::ImageAtomicSminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -404,7 +481,12 @@ ImageAtomicUminMimg::ImageAtomicUminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +510,12 @@ ImageAtomicSmaxMimg::ImageAtomicSmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +539,12 @@ ImageAtomicUmaxMimg::ImageAtomicUmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +568,12 @@ ImageAtomicAndMimg::ImageAtomicAndMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -500,7 +597,12 @@ ImageAtomicOrMimg::ImageAtomicOrMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -524,7 +626,12 @@ ImageAtomicXorMimg::ImageAtomicXorMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -548,7 +655,12 @@ ImageAtomicIncMimg::ImageAtomicIncMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +684,12 @@ ImageAtomicDecMimg::ImageAtomicDecMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -597,7 +714,12 @@ ImageSampleMimg::ImageSampleMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mtbuf.cpp index 6d02572e014a..7391c2cbfba1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mtbuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/mtbuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -46,7 +45,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +78,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +111,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -130,7 +144,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -158,7 +177,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +210,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +243,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -242,7 +276,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ TbufferLoadFormatD16XMtbuf::TbufferLoadFormatD16XMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -304,7 +348,13 @@ TbufferLoadFormatD16XyMtbuf::TbufferLoadFormatD16XyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -332,7 +382,13 @@ TbufferLoadFormatD16XyzMtbuf::TbufferLoadFormatD16XyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +422,13 @@ TbufferLoadFormatD16XyzwMtbuf::TbufferLoadFormatD16XyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -394,7 +456,13 @@ TbufferStoreFormatD16XMtbuf::TbufferStoreFormatD16XMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -422,7 +490,13 @@ TbufferStoreFormatD16XyMtbuf::TbufferStoreFormatD16XyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -450,7 +524,13 @@ TbufferStoreFormatD16XyzMtbuf::TbufferStoreFormatD16XyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +558,13 @@ TbufferStoreFormatD16XyzwMtbuf::TbufferStoreFormatD16XyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf.cpp index 7bed538b7da1..33c7364eaf13 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/mubuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -46,7 +45,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +78,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +111,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -130,7 +144,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -158,7 +177,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +210,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +243,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -242,7 +276,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ BufferLoadFormatD16XMubuf::BufferLoadFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -305,7 +349,12 @@ BufferLoadFormatD16XyMubuf::BufferLoadFormatD16XyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +382,13 @@ BufferLoadFormatD16XyzMubuf::BufferLoadFormatD16XyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,7 +423,13 @@ BufferLoadFormatD16XyzwMubuf::BufferLoadFormatD16XyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -396,7 +457,12 @@ BufferStoreFormatD16XMubuf::BufferStoreFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +490,13 @@ BufferStoreFormatD16XyMubuf::BufferStoreFormatD16XyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +524,13 @@ BufferStoreFormatD16XyzMubuf::BufferStoreFormatD16XyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -480,7 +558,13 @@ BufferStoreFormatD16XyzwMubuf::BufferStoreFormatD16XyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +592,12 @@ BufferLoadUbyteMubuf::BufferLoadUbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +625,12 @@ BufferLoadSbyteMubuf::BufferLoadSbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +658,12 @@ BufferLoadUshortMubuf::BufferLoadUshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -592,7 +691,12 @@ BufferLoadSshortMubuf::BufferLoadSshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,7 +724,12 @@ BufferLoadDwordMubuf::BufferLoadDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +757,12 @@ BufferLoadDwordx2Mubuf::BufferLoadDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -676,7 +790,12 @@ BufferLoadDwordx3Mubuf::BufferLoadDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +823,12 @@ BufferLoadDwordx4Mubuf::BufferLoadDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -732,7 +856,12 @@ BufferStoreByteMubuf::BufferStoreByteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -760,7 +889,12 @@ BufferStoreByteD16HiMubuf::BufferStoreByteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -788,7 +922,12 @@ BufferStoreShortMubuf::BufferStoreShortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -816,7 +955,12 @@ BufferStoreShortD16HiMubuf::BufferStoreShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -844,7 +988,12 @@ BufferStoreDwordMubuf::BufferStoreDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -872,7 +1021,12 @@ BufferStoreDwordx2Mubuf::BufferStoreDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -900,7 +1054,12 @@ BufferStoreDwordx3Mubuf::BufferStoreDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -928,7 +1087,12 @@ BufferStoreDwordx4Mubuf::BufferStoreDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -956,7 +1120,12 @@ BufferLoadUbyteD16Mubuf::BufferLoadUbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -991,7 +1160,12 @@ BufferLoadUbyteD16HiMubuf::BufferLoadUbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1026,7 +1200,12 @@ BufferLoadSbyteD16Mubuf::BufferLoadSbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1240,12 @@ BufferLoadSbyteD16HiMubuf::BufferLoadSbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1280,12 @@ BufferLoadShortD16Mubuf::BufferLoadShortD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1131,7 +1320,12 @@ BufferLoadShortD16HiMubuf::BufferLoadShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1166,7 +1360,13 @@ BufferLoadFormatD16HiXMubuf::BufferLoadFormatD16HiXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1201,7 +1401,13 @@ BufferStoreFormatD16HiXMubuf::BufferStoreFormatD16HiXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1214,7 +1420,12 @@ BufferWbl2Mubuf::BufferWbl2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbl2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbl2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbl2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1227,7 +1438,12 @@ BufferInvl2Mubuf::BufferInvl2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferInvl2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferInvl2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_invl2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1245,7 +1461,12 @@ BufferStoreLdsDwordMubuf::BufferStoreLdsDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreLdsDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_lds_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1258,7 +1479,12 @@ BufferWbinvl1Mubuf::BufferWbinvl1Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbinvl1Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbinvl1Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbinvl1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1497,12 @@ BufferWbinvl1VolMubuf::BufferWbinvl1VolMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbinvl1VolMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbinvl1VolMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbinvl1_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1301,7 +1532,12 @@ BufferAtomicSwapMubuf::BufferAtomicSwapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1336,7 +1572,12 @@ BufferAtomicCmpswapMubuf::BufferAtomicCmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1366,7 +1607,12 @@ BufferAtomicAddMubuf::BufferAtomicAddMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1396,7 +1642,12 @@ BufferAtomicSubMubuf::BufferAtomicSubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1426,7 +1677,12 @@ BufferAtomicSminMubuf::BufferAtomicSminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1456,7 +1712,12 @@ BufferAtomicUminMubuf::BufferAtomicUminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1486,7 +1747,12 @@ BufferAtomicSmaxMubuf::BufferAtomicSmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1516,7 +1782,12 @@ BufferAtomicUmaxMubuf::BufferAtomicUmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1817,12 @@ BufferAtomicAndMubuf::BufferAtomicAndMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1576,7 +1852,12 @@ BufferAtomicOrMubuf::BufferAtomicOrMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1606,7 +1887,12 @@ BufferAtomicXorMubuf::BufferAtomicXorMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1636,7 +1922,12 @@ BufferAtomicIncMubuf::BufferAtomicIncMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1666,7 +1957,12 @@ BufferAtomicDecMubuf::BufferAtomicDecMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1696,7 +1992,12 @@ BufferAtomicAddF32Mubuf::BufferAtomicAddF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1726,7 +2027,12 @@ BufferAtomicPkAddF16Mubuf::BufferAtomicPkAddF16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1756,7 +2062,12 @@ BufferAtomicAddF64Mubuf::BufferAtomicAddF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1786,7 +2097,12 @@ BufferAtomicMinF64Mubuf::BufferAtomicMinF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1816,7 +2132,12 @@ BufferAtomicMaxF64Mubuf::BufferAtomicMaxF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1846,7 +2167,12 @@ BufferAtomicSwapX2Mubuf::BufferAtomicSwapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1881,7 +2207,12 @@ BufferAtomicCmpswapX2Mubuf::BufferAtomicCmpswapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1911,7 +2242,12 @@ BufferAtomicAddX2Mubuf::BufferAtomicAddX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1941,7 +2277,12 @@ BufferAtomicSubX2Mubuf::BufferAtomicSubX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1971,7 +2312,12 @@ BufferAtomicSminX2Mubuf::BufferAtomicSminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2001,7 +2347,12 @@ BufferAtomicUminX2Mubuf::BufferAtomicUminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2031,7 +2382,12 @@ BufferAtomicSmaxX2Mubuf::BufferAtomicSmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2061,7 +2417,12 @@ BufferAtomicUmaxX2Mubuf::BufferAtomicUmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2091,7 +2452,12 @@ BufferAtomicAndX2Mubuf::BufferAtomicAndX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2121,7 +2487,12 @@ BufferAtomicOrX2Mubuf::BufferAtomicOrX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2151,7 +2522,12 @@ BufferAtomicXorX2Mubuf::BufferAtomicXorX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2181,7 +2557,12 @@ BufferAtomicIncX2Mubuf::BufferAtomicIncX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2211,7 +2592,12 @@ BufferAtomicDecX2Mubuf::BufferAtomicDecX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp index 325b95e6b2a3..fb72c2f73467 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem.cpp index 808a0332ef31..fead16afe23b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,11 @@ SLoadDwordSmem::SLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,12 @@ SLoadDwordx2Smem::SLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +91,12 @@ SLoadDwordx4Smem::SLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -103,7 +116,12 @@ SLoadDwordx8Smem::SLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +141,12 @@ SLoadDwordx16Smem::SLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +166,12 @@ SScratchLoadDwordSmem::SScratchLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -163,7 +191,12 @@ SScratchLoadDwordx2Smem::SScratchLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -183,7 +216,12 @@ SScratchLoadDwordx4Smem::SScratchLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +241,12 @@ SBufferLoadDwordSmem::SBufferLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +266,12 @@ SBufferLoadDwordx2Smem::SBufferLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +291,12 @@ SBufferLoadDwordx4Smem::SBufferLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,7 +316,12 @@ SBufferLoadDwordx8Smem::SBufferLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +341,12 @@ SBufferLoadDwordx16Smem::SBufferLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -303,7 +366,12 @@ SStoreDwordSmem::SStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +391,12 @@ SStoreDwordx2Smem::SStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +416,12 @@ SStoreDwordx4Smem::SStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -363,7 +441,12 @@ SScratchStoreDwordSmem::SScratchStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -383,7 +466,12 @@ SScratchStoreDwordx2Smem::SScratchStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -403,7 +491,12 @@ SScratchStoreDwordx4Smem::SScratchStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -423,7 +516,12 @@ SBufferStoreDwordSmem::SBufferStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -443,7 +541,12 @@ SBufferStoreDwordx2Smem::SBufferStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +566,12 @@ SBufferStoreDwordx4Smem::SBufferStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +584,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -489,7 +601,11 @@ SDcacheWbSmem::SDcacheWbSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -502,7 +618,12 @@ SDcacheInvVolSmem::SDcacheInvVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -515,7 +636,12 @@ SDcacheWbVolSmem::SDcacheWbVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -530,7 +656,11 @@ SMemtimeSmem::SMemtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +675,12 @@ SMemrealtimeSmem::SMemrealtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memrealtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +699,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -583,7 +722,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -600,7 +744,12 @@ SDcacheDiscardSmem::SDcacheDiscardSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +766,12 @@ SDcacheDiscardX2Smem::SDcacheDiscardX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -637,7 +791,12 @@ SBufferAtomicSwapSmem::SBufferAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +816,12 @@ SBufferAtomicCmpswapSmem::SBufferAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -677,7 +841,12 @@ SBufferAtomicAddSmem::SBufferAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -697,7 +866,12 @@ SBufferAtomicSubSmem::SBufferAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +891,12 @@ SBufferAtomicSminSmem::SBufferAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -737,7 +916,12 @@ SBufferAtomicUminSmem::SBufferAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -757,7 +941,12 @@ SBufferAtomicSmaxSmem::SBufferAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -777,7 +966,12 @@ SBufferAtomicUmaxSmem::SBufferAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -797,7 +991,12 @@ SBufferAtomicAndSmem::SBufferAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -817,7 +1016,12 @@ SBufferAtomicOrSmem::SBufferAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -837,7 +1041,12 @@ SBufferAtomicXorSmem::SBufferAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -857,7 +1066,12 @@ SBufferAtomicIncSmem::SBufferAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1091,12 @@ SBufferAtomicDecSmem::SBufferAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -897,7 +1116,12 @@ SBufferAtomicSwapX2Smem::SBufferAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -917,7 +1141,12 @@ SBufferAtomicCmpswapX2Smem::SBufferAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -937,7 +1166,12 @@ SBufferAtomicAddX2Smem::SBufferAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -957,7 +1191,12 @@ SBufferAtomicSubX2Smem::SBufferAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -977,7 +1216,12 @@ SBufferAtomicSminX2Smem::SBufferAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -997,7 +1241,12 @@ SBufferAtomicUminX2Smem::SBufferAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1266,12 @@ SBufferAtomicSmaxX2Smem::SBufferAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1037,7 +1291,12 @@ SBufferAtomicUmaxX2Smem::SBufferAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1316,12 @@ SBufferAtomicAndX2Smem::SBufferAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1077,7 +1341,12 @@ SBufferAtomicOrX2Smem::SBufferAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1366,12 @@ SBufferAtomicXorX2Smem::SBufferAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1117,7 +1391,12 @@ SBufferAtomicIncX2Smem::SBufferAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1416,12 @@ SBufferAtomicDecX2Smem::SBufferAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1157,7 +1441,12 @@ SAtomicSwapSmem::SAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1177,7 +1466,12 @@ SAtomicCmpswapSmem::SAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1491,11 @@ SAtomicAddSmem::SAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1217,7 +1515,11 @@ SAtomicSubSmem::SAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1237,7 +1539,12 @@ SAtomicSminSmem::SAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1257,7 +1564,12 @@ SAtomicUminSmem::SAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1277,7 +1589,12 @@ SAtomicSmaxSmem::SAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1297,7 +1614,12 @@ SAtomicUmaxSmem::SAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1317,7 +1639,11 @@ SAtomicAndSmem::SAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1337,7 +1663,11 @@ SAtomicOrSmem::SAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1357,7 +1687,11 @@ SAtomicXorSmem::SAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1377,7 +1711,11 @@ SAtomicIncSmem::SAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1397,7 +1735,11 @@ SAtomicDecSmem::SAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1417,7 +1759,12 @@ SAtomicSwapX2Smem::SAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1437,7 +1784,12 @@ SAtomicCmpswapX2Smem::SAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1809,12 @@ SAtomicAddX2Smem::SAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1477,7 +1834,12 @@ SAtomicSubX2Smem::SAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1859,12 @@ SAtomicSminX2Smem::SAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1517,7 +1884,12 @@ SAtomicUminX2Smem::SAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1537,7 +1909,12 @@ SAtomicSmaxX2Smem::SAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1557,7 +1934,12 @@ SAtomicUmaxX2Smem::SAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1577,7 +1959,12 @@ SAtomicAndX2Smem::SAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1597,7 +1984,12 @@ SAtomicOrX2Smem::SAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1617,7 +2009,12 @@ SAtomicXorX2Smem::SAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1637,7 +2034,12 @@ SAtomicIncX2Smem::SAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1657,7 +2059,12 @@ SAtomicDecX2Smem::SAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1.cpp index 86e43a43b4f1..894e69f8056e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +173,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +201,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +230,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +255,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +281,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -295,7 +339,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -319,7 +368,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +398,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +424,11 @@ SFf0I32B32Sop1::SFf0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +450,11 @@ SFf0I32B64Sop1::SFf0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +475,11 @@ SFf1I32B32Sop1::SFf1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +501,11 @@ SFf1I32B64Sop1::SFf1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +526,12 @@ SFlbitI32B32Sop1::SFlbitI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +553,12 @@ SFlbitI32B64Sop1::SFlbitI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +579,11 @@ SFlbitI32Sop1::SFlbitI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +605,12 @@ SFlbitI32I64Sop1::SFlbitI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +632,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +658,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +685,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -604,7 +712,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +739,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +766,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +789,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -685,7 +812,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +839,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +861,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +897,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +935,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -823,7 +972,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +1009,12 @@ SAndn2SaveexecB64Sop1::SAndn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -887,7 +1046,12 @@ SOrn2SaveexecB64Sop1::SOrn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -919,7 +1083,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1120,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -983,7 +1157,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1007,7 +1186,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1216,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1241,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1266,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1295,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1325,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1141,7 +1350,12 @@ SCbranchJoinSop1::SCbranchJoinSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode) { +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cbranch_join", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1379,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1189,7 +1407,12 @@ SSetGprIdxIdxSop1::SSetGprIdxIdxSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_set_gpr_idx_idx", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1444,12 @@ SAndn1SaveexecB64Sop1::SAndn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1253,7 +1481,12 @@ SOrn1SaveexecB64Sop1::SOrn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1285,7 +1518,12 @@ SAndn1WrexecB64Sop1::SAndn1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1317,7 +1555,12 @@ SAndn2WrexecB64Sop1::SAndn2WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1581,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop2.cpp index a356d5af8e41..91d10c8badab 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +280,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +314,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +348,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +382,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +454,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +490,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +525,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +562,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +596,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +632,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +666,11 @@ SAndn2B32Sop2::SAndn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +702,11 @@ SAndn2B64Sop2::SAndn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +736,11 @@ SOrn2B32Sop2::SOrn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +772,11 @@ SOrn2B64Sop2::SOrn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +806,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +842,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -779,7 +876,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -811,7 +912,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +946,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +982,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1016,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1051,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1085,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1120,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1154,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1189,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1220,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1251,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1282,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1316,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1350,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1385,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1420,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1444,12 @@ SCbranchGForkSop2::SCbranchGForkSop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode) { +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cbranch_g_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1479,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1513,12 @@ SRfeRestoreB64Sop2::SRfeRestoreB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_rfe_restore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1365,7 +1545,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1392,7 +1576,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,7 +1610,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1645,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1680,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1715,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1749,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1569,7 +1782,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1596,7 +1814,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp index 01d9ab1b7243..5f16e201fe90 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -482,7 +549,11 @@ SSetvskipSopc::SSetvskipSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode) { +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_setvskip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +579,12 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_set_gpr_idx_on", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +614,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +648,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopk.cpp index 7076439b0031..9715791f7368 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -46,7 +49,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +73,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,7 +97,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +121,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +145,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +169,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +193,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +217,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -206,7 +241,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -226,7 +265,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +289,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +313,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -286,7 +337,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +362,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +384,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +405,12 @@ SCbranchIForkSopk::SCbranchIForkSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode) { +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cbranch_i_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +427,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +448,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -395,7 +471,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +499,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopp.cpp index 833f8942e44c..13624f22c774 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -36,7 +39,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +60,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +82,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +106,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +136,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +166,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +196,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +226,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +256,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +280,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +299,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +338,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +357,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +376,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +398,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,7 +420,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -362,7 +440,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +457,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +476,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +496,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +517,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +537,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +577,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +597,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +616,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +634,12 @@ SSetGprIdxOffSopp::SSetGprIdxOffSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_off", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -528,7 +659,12 @@ SSetGprIdxModeSopp::SSetGprIdxModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -542,7 +678,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp index b170c2d495d3..bc7a87c786d0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,14 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +78,14 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,14 +99,20 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_readfirstlane_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -120,12 +139,17 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -151,12 +175,17 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_i32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -206,7 +235,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +293,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +351,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +409,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -406,7 +467,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +532,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -513,7 +590,16 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +649,16 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +708,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,12 +744,17 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -663,14 +772,19 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -720,7 +834,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +893,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -820,7 +952,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -870,7 +1011,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -897,12 +1047,17 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_U32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_u32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -928,12 +1083,17 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_U32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_u32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -960,12 +1120,17 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_TRUNC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_trunc_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -992,12 +1157,17 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CEIL_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_ceil_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1016,14 +1186,19 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RNDNE_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rndne_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1050,12 +1225,17 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FLOOR_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_floor_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1104,7 +1284,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1153,7 +1341,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1202,7 +1398,14 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1251,7 +1454,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1300,7 +1511,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1568,14 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1398,7 +1624,14 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1680,14 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1737,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1795,14 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1565,14 +1821,19 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RCP_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rcp_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1591,14 +1852,19 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RSQ_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rsq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1647,7 +1913,14 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1666,14 +1939,19 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SQRT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_sqrt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1722,7 +2000,14 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1771,7 +2056,14 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1820,7 +2112,14 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1869,7 +2168,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1918,7 +2225,14 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1967,7 +2281,14 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2016,7 +2337,14 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2043,12 +2371,18 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_exp_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2075,12 +2409,18 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_mant_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2107,12 +2447,17 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FRACT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_fract_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2162,7 +2507,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2212,7 +2566,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2225,7 +2588,11 @@ VClrexcpVop1::VClrexcpVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop1::validate_encoding( + "v_clrexcp_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2275,7 +2642,16 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2326,7 +2702,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2383,7 +2767,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2440,7 +2832,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2497,7 +2897,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2553,7 +2961,14 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2609,7 +3024,14 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2665,7 +3087,14 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2721,7 +3150,14 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2777,7 +3213,14 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2834,7 +3277,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2891,7 +3343,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2947,7 +3408,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3003,7 +3472,14 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3059,7 +3535,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3115,7 +3599,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3171,7 +3663,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3227,7 +3727,14 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3283,7 +3790,14 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3340,7 +3854,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3397,7 +3920,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3453,7 +3985,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3475,14 +4016,19 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_swap_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3534,7 +4080,16 @@ VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVAccvgprMovB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_accvgpr_mov_b32_sdwa" + : "v_accvgpr_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp index 56b68001a52b..24cf5008dc88 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -67,7 +66,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +130,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +192,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +255,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,12 +293,17 @@ VFmacF64Vop2::VFmacF64Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -323,7 +358,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -379,7 +421,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +485,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -491,7 +550,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -547,7 +614,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +678,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +740,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -712,7 +802,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -767,7 +864,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -822,7 +926,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +988,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -933,7 +1051,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -989,7 +1116,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1045,7 +1181,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1100,7 +1245,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1307,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1210,7 +1369,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1239,12 +1405,17 @@ VMacF32Vop2::VMacF32Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_mac_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1269,14 +1440,19 @@ VMadmkF32Vop2::VMadmkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadmkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madmk_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1301,14 +1477,19 @@ VMadakF32Vop2::VMadakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madak_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1367,7 +1548,15 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1426,7 +1615,15 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1485,7 +1682,16 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1753,15 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1609,7 +1823,15 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1671,7 +1893,16 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1727,7 +1958,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1789,7 +2027,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1852,7 +2097,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1914,7 +2167,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1950,12 +2210,17 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_mac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1988,14 +2253,19 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADMK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madmk_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2028,14 +2298,19 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADAK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madak_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2097,7 +2372,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2159,7 +2441,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2222,7 +2511,15 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2285,7 +2582,15 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2348,7 +2653,16 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2411,7 +2725,16 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2474,7 +2797,16 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2536,7 +2868,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2598,7 +2937,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2660,7 +3006,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2722,7 +3075,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2784,7 +3144,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2846,7 +3213,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2908,7 +3282,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2969,7 +3351,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3024,7 +3413,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3080,7 +3476,15 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3109,12 +3513,18 @@ VDot2cF32F16Vop2::VDot2cF32F16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_f32_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3143,12 +3553,18 @@ VDot2cI32I16Vop2::VDot2cI32I16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_I32_I16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_i32_i16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_I32_I16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3177,12 +3593,18 @@ VDot4cI32I8Vop2::VDot4cI32I8Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT4C_I32_I8 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot4c_i32_i8_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT4C_I32_I8 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3211,12 +3633,18 @@ VDot8cI32I4Vop2::VDot8cI32I4Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT8C_I32_I4 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot8c_i32_i4_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT8C_I32_I4 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3245,12 +3673,17 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3279,12 +3712,17 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PK_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_pk_fmac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3339,7 +3777,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3.cpp index f719e479dcc2..fbd9ece495c8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -21,7 +20,11 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -38,7 +41,11 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -55,7 +62,12 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readfirstlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +84,11 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -89,7 +105,11 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +126,11 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +147,11 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -157,7 +189,11 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +210,11 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +237,11 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +258,12 @@ VCvtRpiI32F32Vop3::VCvtRpiI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_rpi_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +280,12 @@ VCvtFlrI32F32Vop3::VCvtFlrI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_flr_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -248,7 +302,12 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_off_f32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +324,11 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -282,7 +345,11 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +366,12 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -316,7 +388,12 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +410,12 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +432,12 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -367,7 +454,11 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +475,11 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +496,11 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +517,11 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +538,11 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +559,11 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +580,11 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +601,11 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +622,11 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +643,11 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +664,11 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +685,11 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +706,11 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -588,7 +727,11 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -605,7 +748,12 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_iflag_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -622,7 +770,11 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -639,7 +791,11 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -656,7 +812,11 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -673,7 +833,11 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -690,7 +854,11 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +875,11 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -724,7 +896,11 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +917,11 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +938,11 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -775,7 +959,11 @@ VFfbhU32Vop3::VFfbhU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -792,7 +980,11 @@ VFfblB32Vop3::VFfblB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +1001,11 @@ VFfbhI32Vop3::VFfbhI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -826,7 +1022,12 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -843,7 +1044,12 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -860,7 +1066,11 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1087,12 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1109,12 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -907,7 +1127,11 @@ VClrexcpVop3::VClrexcpVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_clrexcp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1148,12 @@ VScreenPartition4seB32Vop3::VScreenPartition4seB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_screen_partition_4se_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -941,7 +1170,11 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1197,11 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -987,7 +1224,11 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1010,7 +1251,11 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1033,7 +1278,11 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1305,11 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1079,7 +1332,11 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1102,7 +1359,11 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1125,7 +1386,11 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1148,7 +1413,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1171,7 +1441,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1194,7 +1469,11 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1217,7 +1496,11 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1240,7 +1523,11 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1263,7 +1550,11 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1286,7 +1577,11 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1604,11 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1332,7 +1631,11 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1355,7 +1658,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1378,7 +1686,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1714,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sat_pk_u8_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1426,7 +1744,11 @@ VSwapB32Vop3::VSwapB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1449,7 +1771,12 @@ VAccvgprMovB32Vop3::VAccvgprMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAccvgprMovB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_accvgpr_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1470,7 +1797,12 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cndmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1489,7 +1821,11 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1508,7 +1844,11 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1527,7 +1867,11 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1891,11 @@ VFmacF64Vop3::VFmacF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1566,7 +1914,11 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1585,7 +1937,11 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1960,12 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1623,7 +1984,11 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1642,7 +2007,12 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1661,7 +2031,11 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1680,7 +2054,11 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +2077,11 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1718,7 +2100,11 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1737,7 +2123,11 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1756,7 +2146,11 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1775,7 +2169,12 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1794,7 +2193,12 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1813,7 +2217,12 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1832,7 +2241,11 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1851,7 +2264,11 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1870,7 +2287,11 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1890,7 +2311,11 @@ VMacF32Vop3::VMacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1909,7 +2334,11 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1934,7 +2363,11 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1959,7 +2392,11 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1984,7 +2421,11 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2010,7 +2451,11 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2035,7 +2480,11 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2060,7 +2509,11 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2085,7 +2538,11 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2110,7 +2567,11 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2135,7 +2596,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2160,7 +2626,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2185,7 +2656,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2210,7 +2686,11 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2235,7 +2715,11 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2260,7 +2744,11 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2285,7 +2773,11 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2310,7 +2802,11 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2335,7 +2831,11 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2360,7 +2860,11 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2385,7 +2889,11 @@ VAddU32Vop3::VAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2404,7 +2912,11 @@ VSubU32Vop3::VSubU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2423,7 +2935,11 @@ VSubrevU32Vop3::VSubrevU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2443,7 +2959,12 @@ VDot2cF32F16Vop3::VDot2cF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2463,7 +2984,12 @@ VDot2cI32I16Vop3::VDot2cI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2483,7 +3009,12 @@ VDot4cI32I8Vop3::VDot4cI32I8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot4c_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2503,7 +3034,12 @@ VDot8cI32I4Vop3::VDot8cI32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot8c_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2523,7 +3059,11 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2543,7 +3083,11 @@ VPkFmacF16Vop3::VPkFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pk_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2562,7 +3106,11 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2583,7 +3131,12 @@ VMadLegacyF32Vop3::VMadLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2604,7 +3157,11 @@ VMadF32Vop3::VMadF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2625,7 +3182,11 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2646,7 +3207,11 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2667,7 +3232,11 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubeid_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2688,7 +3257,11 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubesc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2709,7 +3282,11 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubetc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2730,7 +3307,11 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubema_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2751,7 +3332,11 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2772,7 +3357,11 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2793,7 +3382,11 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2814,7 +3407,11 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2835,7 +3432,11 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2856,7 +3457,11 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lerp_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2877,7 +3482,12 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbit_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2898,7 +3508,12 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbyte_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2919,7 +3534,11 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2940,7 +3559,11 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2961,7 +3584,11 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2982,7 +3609,11 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3003,7 +3634,11 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3024,7 +3659,11 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3045,7 +3684,11 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3066,7 +3709,11 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3087,7 +3734,11 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3108,7 +3759,11 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3129,7 +3784,11 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3150,7 +3809,11 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3171,7 +3834,11 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3192,7 +3859,12 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3213,7 +3885,12 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3234,7 +3911,12 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3258,7 +3940,12 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3282,7 +3969,12 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3303,7 +3995,11 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_msad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3324,7 +4020,12 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_qsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3345,7 +4046,12 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3366,7 +4072,12 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3387,7 +4098,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3414,7 +4130,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3441,7 +4162,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3468,7 +4194,11 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_perm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3489,7 +4219,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3516,7 +4251,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3542,7 +4282,12 @@ VCvtPkaccumU8F32Vop3::VCvtPkaccumU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkaccum_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3563,7 +4308,11 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3584,7 +4333,11 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3605,7 +4358,11 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3626,7 +4383,11 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3653,7 +4414,11 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3680,7 +4445,11 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3707,7 +4476,11 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3734,7 +4507,11 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3761,7 +4538,11 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3788,7 +4569,11 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3815,7 +4600,11 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3842,7 +4631,11 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3869,7 +4662,12 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3890,7 +4688,12 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_lshl_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3911,7 +4714,11 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3932,7 +4739,11 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3953,7 +4764,11 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3974,7 +4789,11 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3995,7 +4814,11 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4022,7 +4845,11 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4049,7 +4876,11 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4076,7 +4907,11 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4103,7 +4938,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4128,7 +4968,11 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4147,7 +4991,11 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4166,7 +5014,11 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4185,7 +5037,11 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4204,7 +5060,11 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4223,7 +5083,11 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4242,7 +5106,11 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4261,7 +5129,11 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4280,7 +5152,11 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4299,7 +5175,12 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4319,7 +5200,12 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_writelane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4338,7 +5224,12 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bcnt_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4357,7 +5248,12 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_lo_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4376,7 +5272,12 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_hi_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4395,7 +5296,12 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4414,7 +5320,12 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4433,7 +5344,12 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4452,7 +5368,12 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trig_preop_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4471,7 +5392,11 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4490,7 +5415,12 @@ VCvtPknormI16F32Vop3::VCvtPknormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4509,7 +5439,12 @@ VCvtPknormU16F32Vop3::VCvtPknormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4528,7 +5463,12 @@ VCvtPkrtzF16F32Vop3::VCvtPkrtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkrtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4547,7 +5487,12 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u16_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4566,7 +5511,12 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_i16_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4585,7 +5535,12 @@ VCvtPknormI16F16Vop3::VCvtPknormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4604,7 +5559,12 @@ VCvtPknormU16F16Vop3::VCvtPknormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4623,7 +5583,11 @@ VAddI32Vop3::VAddI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4642,7 +5606,11 @@ VSubI32Vop3::VSubI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4661,7 +5629,11 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4686,7 +5658,11 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4711,7 +5687,12 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pack_b32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4730,7 +5711,12 @@ VMulLegacyF32Vop3::VMulLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4749,7 +5735,12 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4772,7 +5763,12 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4791,7 +5787,12 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4814,7 +5815,12 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4833,7 +5839,12 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4856,7 +5867,12 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4875,7 +5891,11 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4894,7 +5914,11 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4913,7 +5937,11 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4932,7 +5960,11 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4951,7 +5983,11 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4970,7 +6006,11 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4989,7 +6029,11 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5008,7 +6052,11 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5027,7 +6075,11 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5046,7 +6098,11 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5065,7 +6121,11 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5084,7 +6144,11 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5103,7 +6167,11 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5122,7 +6190,11 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5141,7 +6213,11 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5160,7 +6236,11 @@ VCmpTruF16Vop3::VCmpTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5183,7 +6263,11 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5206,7 +6290,11 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5229,7 +6317,11 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5252,7 +6344,11 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5275,7 +6371,11 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5298,7 +6398,11 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5321,7 +6425,11 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5344,7 +6452,11 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5367,7 +6479,11 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5390,7 +6506,12 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5413,7 +6534,12 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5436,7 +6562,12 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5459,7 +6590,12 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5482,7 +6618,12 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5505,7 +6646,12 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5528,7 +6674,12 @@ VCmpxTruF16Vop3::VCmpxTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5547,7 +6698,11 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5566,7 +6721,11 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5585,7 +6744,11 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5604,7 +6767,11 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5623,7 +6790,11 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5642,7 +6813,11 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5661,7 +6836,11 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5680,7 +6859,11 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5699,7 +6882,11 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5718,7 +6905,11 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5737,7 +6928,11 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5756,7 +6951,11 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5775,7 +6974,11 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5794,7 +6997,11 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5813,7 +7020,11 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5832,7 +7043,11 @@ VCmpTruF32Vop3::VCmpTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5855,7 +7070,11 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5878,7 +7097,11 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5901,7 +7124,11 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5924,7 +7151,11 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5947,7 +7178,11 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5970,7 +7205,11 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5993,7 +7232,11 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6016,7 +7259,11 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6039,7 +7286,11 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6062,7 +7313,12 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6085,7 +7341,12 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6108,7 +7369,12 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6131,7 +7397,12 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6154,7 +7425,12 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6177,7 +7453,12 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6200,7 +7481,12 @@ VCmpxTruF32Vop3::VCmpxTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6219,7 +7505,11 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6238,7 +7528,11 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6257,7 +7551,11 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6276,7 +7574,11 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6295,7 +7597,11 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6314,7 +7620,11 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6333,7 +7643,11 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6352,7 +7666,11 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6371,7 +7689,11 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6390,7 +7712,11 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6409,7 +7735,11 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6428,7 +7758,11 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6447,7 +7781,11 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6466,7 +7804,11 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6485,7 +7827,11 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6504,7 +7850,11 @@ VCmpTruF64Vop3::VCmpTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6527,7 +7877,11 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6550,7 +7904,11 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6573,7 +7931,11 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6596,7 +7958,11 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6619,7 +7985,11 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6642,7 +8012,11 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6665,7 +8039,11 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6688,7 +8066,11 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6711,7 +8093,11 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6734,7 +8120,12 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6757,7 +8148,12 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6780,7 +8176,12 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6803,7 +8204,12 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6826,7 +8232,12 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6849,7 +8260,12 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6872,7 +8288,12 @@ VCmpxTruF64Vop3::VCmpxTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6891,7 +8312,11 @@ VCmpFI16Vop3::VCmpFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6910,7 +8335,11 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6929,7 +8358,11 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6948,7 +8381,11 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6967,7 +8404,11 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6986,7 +8427,11 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7005,7 +8450,11 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7024,7 +8473,11 @@ VCmpTI16Vop3::VCmpTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7043,7 +8496,11 @@ VCmpFU16Vop3::VCmpFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7062,7 +8519,11 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7081,7 +8542,11 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7100,7 +8565,11 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7119,7 +8588,11 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7138,7 +8611,11 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7157,7 +8634,11 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7176,7 +8657,11 @@ VCmpTU16Vop3::VCmpTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7199,7 +8684,11 @@ VCmpxFI16Vop3::VCmpxFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7222,7 +8711,11 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7245,7 +8738,11 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7268,7 +8765,11 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7291,7 +8792,11 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7314,7 +8819,11 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7337,7 +8846,11 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7360,7 +8873,11 @@ VCmpxTI16Vop3::VCmpxTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7383,7 +8900,11 @@ VCmpxFU16Vop3::VCmpxFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7406,7 +8927,11 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7429,7 +8954,11 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7452,7 +8981,11 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7475,7 +9008,11 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7498,7 +9035,11 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7521,7 +9062,11 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7544,7 +9089,11 @@ VCmpxTU16Vop3::VCmpxTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7563,7 +9112,11 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7582,7 +9135,11 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7601,7 +9158,11 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7620,7 +9181,11 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7639,7 +9204,11 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7658,7 +9227,11 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7677,7 +9250,11 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7696,7 +9273,11 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7715,7 +9296,11 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7734,7 +9319,11 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7753,7 +9342,11 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7772,7 +9365,11 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7791,7 +9388,11 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7810,7 +9411,11 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7829,7 +9434,11 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7848,7 +9457,11 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7871,7 +9484,11 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7894,7 +9511,11 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7917,7 +9538,11 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7940,7 +9565,11 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7963,7 +9592,11 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7986,7 +9619,11 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8009,7 +9646,11 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8032,7 +9673,11 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8055,7 +9700,11 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8078,7 +9727,11 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8101,7 +9754,11 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8124,7 +9781,11 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8147,7 +9808,11 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8170,7 +9835,11 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8193,7 +9862,11 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8216,7 +9889,11 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8235,7 +9912,11 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8254,7 +9935,11 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8273,7 +9958,11 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8292,7 +9981,11 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8311,7 +10004,11 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8330,7 +10027,11 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8349,7 +10050,11 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8368,7 +10073,11 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8387,7 +10096,11 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8406,7 +10119,11 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8425,7 +10142,11 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8444,7 +10165,11 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8463,7 +10188,11 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8482,7 +10211,11 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8501,7 +10234,11 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8520,7 +10257,11 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8543,7 +10284,11 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8566,7 +10311,11 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8589,7 +10338,11 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8612,7 +10365,11 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8635,7 +10392,11 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8658,7 +10419,11 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8681,7 +10446,11 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8704,7 +10473,11 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8727,7 +10500,11 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8750,7 +10527,11 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8773,7 +10554,11 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8796,7 +10581,11 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8819,7 +10608,11 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8842,7 +10635,11 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8865,7 +10662,11 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8888,7 +10689,11 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8909,7 +10714,12 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8930,7 +10740,12 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8951,7 +10766,12 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8974,7 +10794,12 @@ VAddcCoU32Vop3SdstEnc::VAddcCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_addc_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8997,7 +10822,12 @@ VSubbCoU32Vop3SdstEnc::VSubbCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subb_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9020,7 +10850,12 @@ VSubbrevCoU32Vop3SdstEnc::VSubbrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subbrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9043,7 +10878,12 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9066,7 +10906,12 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9089,7 +10934,12 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_u64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9112,7 +10962,12 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_i64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3p.cpp index dfb3012cd834..1f49b71b8713 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,7 +40,11 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +69,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +99,11 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +128,11 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +157,12 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +181,12 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -179,7 +205,12 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -198,7 +229,11 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +258,11 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +289,11 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -275,7 +318,11 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +347,11 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +376,11 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +405,11 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -377,7 +436,11 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -402,7 +465,11 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -427,7 +494,11 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +523,11 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -477,7 +552,11 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -504,7 +583,12 @@ VMadMixF32Vop3p::VMadMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mix_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -526,7 +610,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixlo_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +643,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixhi_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -581,7 +675,12 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +701,12 @@ VDot2I32I16Vop3p::VDot2I32I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +727,12 @@ VDot2U32U16Vop3p::VDot2U32U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -644,7 +753,12 @@ VDot4I32I8Vop3p::VDot4I32I8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -665,7 +779,12 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -686,7 +805,12 @@ VDot8I32I4Vop3p::VDot8I32I4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +831,12 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_u32_u4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -728,7 +857,11 @@ VPkFmaF32Vop3p::VPkFmaF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -747,7 +880,11 @@ VPkMulF32Vop3p::VPkMulF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -766,7 +903,11 @@ VPkAddF32Vop3p::VPkAddF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -785,7 +926,11 @@ VPkMovB32Vop3p::VPkMovB32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMovB32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMovB32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -806,7 +951,12 @@ VAccvgprReadVop3p::VAccvgprReadVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_read", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -824,7 +974,12 @@ VAccvgprWriteVop3p::VAccvgprWriteVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_write", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -862,7 +1017,12 @@ VMfmaF3232x32x1f32Vop3pMfma::VMfmaF3232x32x1f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x1f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -900,7 +1060,12 @@ VMfmaF3216x16x1f32Vop3pMfma::VMfmaF3216x16x1f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x1f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -938,7 +1103,12 @@ VMfmaF324x4x1f32Vop3pMfma::VMfmaF324x4x1f32Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x1f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x1f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -976,7 +1146,12 @@ VMfmaF3232x32x2f32Vop3pMfma::VMfmaF3232x32x2f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x2f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x2f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1014,7 +1189,12 @@ VMfmaF3216x16x4f32Vop3pMfma::VMfmaF3216x16x4f32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4f32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1232,12 @@ VMfmaF3232x32x4f16Vop3pMfma::VMfmaF3232x32x4f16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1090,7 +1275,12 @@ VMfmaF3216x16x4f16Vop3pMfma::VMfmaF3216x16x4f16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1128,7 +1318,12 @@ VMfmaF324x4x4f16Vop3pMfma::VMfmaF324x4x4f16Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x4f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1166,7 +1361,12 @@ VMfmaF3232x32x8f16Vop3pMfma::VMfmaF3232x32x8f16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1204,7 +1404,13 @@ VMfmaF3216x16x16f16Vop3pMfma::VMfmaF3216x16x16f16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16f16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1242,7 +1448,12 @@ VMfmaI3232x32x4i8Vop3pMfma::VMfmaI3232x32x4i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x4i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1280,7 +1491,12 @@ VMfmaI3216x16x4i8Vop3pMfma::VMfmaI3216x16x4i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x4i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1318,7 +1534,12 @@ VMfmaI324x4x4i8Vop3pMfma::VMfmaI324x4x4i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI324x4x4i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_4x4x4i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1356,7 +1577,12 @@ VMfmaI3232x32x8i8Vop3pMfma::VMfmaI3232x32x8i8Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x8i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x8i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1620,12 @@ VMfmaI3216x16x16i8Vop3pMfma::VMfmaI3216x16x16i8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x16i8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x16i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1432,7 +1663,13 @@ VMfmaF3232x32x4bf161kVop3pMfma::VMfmaF3232x32x4bf161kVop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x4bf161kVop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x4bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4bf16_1k", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1470,7 +1707,13 @@ VMfmaF3216x16x4bf161kVop3pMfma::VMfmaF3216x16x4bf161kVop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4bf161kVop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4bf16_1k", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1508,7 +1751,13 @@ VMfmaF324x4x4bf161kVop3pMfma::VMfmaF324x4x4bf161kVop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF324x4x4bf161kVop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x4bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4bf16_1k", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1795,13 @@ VMfmaF3232x32x8bf161kVop3pMfma::VMfmaF3232x32x8bf161kVop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8bf161kVop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8bf16_1k", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1839,13 @@ VMfmaF3216x16x16bf161kVop3pMfma::VMfmaF3216x16x16bf161kVop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16bf161kVop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16bf161kVop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16bf16_1k", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1622,7 +1883,13 @@ VMfmaF3232x32x2bf16Vop3pMfma::VMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x2bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1660,7 +1927,13 @@ VMfmaF3216x16x2bf16Vop3pMfma::VMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x2bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1698,7 +1971,12 @@ VMfmaF324x4x2bf16Vop3pMfma::VMfmaF324x4x2bf16Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x2bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x2bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1736,7 +2014,13 @@ VMfmaF3232x32x4bf16Vop3pMfma::VMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x4bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1774,7 +2058,13 @@ VMfmaF3216x16x8bf16Vop3pMfma::VMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x8bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x8bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1812,7 +2102,12 @@ VMfmaF6416x16x4f64Vop3pMfma::VMfmaF6416x16x4f64Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF6416x16x4f64Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF6416x16x4f64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f64_16x16x4f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1850,7 +2145,12 @@ VMfmaF644x4x4f64Vop3pMfma::VMfmaF644x4x4f64Vop3pMfma(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMfmaF644x4x4f64Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF644x4x4f64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f64_4x4x4f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp index 6b74cf86424c..c80d1266f211 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,8 +30,6 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -60,7 +57,18 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -85,8 +93,6 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -116,7 +122,18 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,15 +154,21 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -168,17 +191,23 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -202,8 +231,6 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -231,7 +258,18 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -257,8 +295,6 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -288,7 +324,18 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -311,8 +358,6 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -340,7 +385,17 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -364,8 +419,6 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -393,7 +446,17 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -417,8 +480,6 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -446,7 +507,17 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -470,8 +541,6 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -499,7 +568,17 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -523,8 +602,6 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -552,7 +629,17 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -576,8 +663,6 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -605,7 +690,17 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -629,8 +724,6 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -658,7 +751,17 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -681,8 +784,6 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -710,7 +811,17 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -733,8 +844,6 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -762,7 +871,17 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -786,8 +905,6 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -815,7 +932,17 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -839,8 +966,6 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -868,7 +993,17 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -892,8 +1027,6 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -921,7 +1054,17 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -945,8 +1088,6 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -974,7 +1115,17 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -998,8 +1149,6 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1027,7 +1176,17 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1051,8 +1210,6 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1080,7 +1237,17 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1104,8 +1271,6 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1133,7 +1298,17 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1159,8 +1334,6 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1190,7 +1363,17 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1216,8 +1399,6 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1247,7 +1428,17 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1273,8 +1464,6 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1304,7 +1493,17 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1330,8 +1529,6 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1361,7 +1558,17 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1387,8 +1594,6 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1418,7 +1623,17 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1444,8 +1659,6 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1475,7 +1688,17 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1501,8 +1724,6 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1532,7 +1753,17 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1558,8 +1789,6 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1589,7 +1818,17 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1615,8 +1854,6 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1646,7 +1883,17 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1672,8 +1919,6 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1703,7 +1948,18 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1729,8 +1985,6 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1760,7 +2014,18 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1786,8 +2051,6 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1817,7 +2080,18 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1843,8 +2117,6 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1874,7 +2146,18 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1900,8 +2183,6 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1931,7 +2212,18 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1957,8 +2249,6 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1988,7 +2278,18 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2014,8 +2315,6 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2045,7 +2344,18 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2067,8 +2377,6 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2096,7 +2404,17 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2119,8 +2437,6 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2148,7 +2464,17 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2171,8 +2497,6 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2200,7 +2524,17 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2223,8 +2557,6 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2252,7 +2584,17 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2275,8 +2617,6 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2304,7 +2644,17 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2327,8 +2677,6 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2356,7 +2704,17 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2379,8 +2737,6 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2408,7 +2764,17 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2430,8 +2796,6 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2459,7 +2823,17 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2481,8 +2855,6 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2510,7 +2882,17 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2533,8 +2915,6 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2562,7 +2942,17 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2585,8 +2975,6 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2614,7 +3002,17 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2637,8 +3035,6 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2666,7 +3062,17 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2689,8 +3095,6 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2718,7 +3122,17 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2741,8 +3155,6 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2770,7 +3182,17 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2793,8 +3215,6 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2822,7 +3242,17 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2845,8 +3275,6 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2874,7 +3302,17 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2899,8 +3337,6 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2930,7 +3366,17 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2955,8 +3401,6 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2986,7 +3430,17 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3011,8 +3465,6 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3042,7 +3494,17 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3067,8 +3529,6 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3098,7 +3558,17 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3123,8 +3593,6 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3154,7 +3622,17 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3179,8 +3657,6 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3210,7 +3686,17 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3235,8 +3721,6 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3266,7 +3750,17 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3291,8 +3785,6 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3322,7 +3814,17 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3347,8 +3849,6 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3378,7 +3878,17 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3403,8 +3913,6 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3434,7 +3942,18 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3459,8 +3978,6 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3490,7 +4007,18 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3515,8 +4043,6 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3546,7 +4072,18 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3571,8 +4108,6 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3602,7 +4137,18 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3627,8 +4173,6 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3658,7 +4202,18 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3683,8 +4238,6 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3714,7 +4267,18 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3739,8 +4303,6 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3770,7 +4332,18 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3791,15 +4364,20 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3820,15 +4398,20 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3849,15 +4432,20 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3878,15 +4466,20 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3907,15 +4500,20 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3936,15 +4534,20 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3965,15 +4568,20 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3994,15 +4602,20 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4023,15 +4636,20 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4052,15 +4670,20 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4081,15 +4704,20 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4110,15 +4738,20 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4139,15 +4772,20 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4168,15 +4806,20 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4197,15 +4840,20 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4226,15 +4874,20 @@ VCmpTruF64Vopc::VCmpTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4257,17 +4910,22 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4290,17 +4948,22 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4323,17 +4986,22 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4356,17 +5024,22 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4389,17 +5062,22 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4422,17 +5100,22 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4455,17 +5138,22 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4488,17 +5176,22 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4521,17 +5214,22 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4554,17 +5252,23 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4587,17 +5291,23 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4620,17 +5330,23 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4653,17 +5369,23 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4686,17 +5408,23 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4719,17 +5447,23 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4752,17 +5486,23 @@ VCmpxTruF64Vopc::VCmpxTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4785,8 +5525,6 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4814,7 +5552,17 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4838,8 +5586,6 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4867,7 +5613,17 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4891,8 +5647,6 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4920,7 +5674,17 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4944,8 +5708,6 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4973,7 +5735,17 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4997,8 +5769,6 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5026,7 +5796,17 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5050,8 +5830,6 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5079,7 +5857,17 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5103,8 +5891,6 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5132,7 +5918,17 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5155,8 +5951,6 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5184,7 +5978,17 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5207,8 +6011,6 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5236,7 +6038,17 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5260,8 +6072,6 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5289,7 +6099,17 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5313,8 +6133,6 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5342,7 +6160,17 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5366,8 +6194,6 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5395,7 +6221,17 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5419,8 +6255,6 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5448,7 +6282,17 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5472,8 +6316,6 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5501,7 +6343,17 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5525,8 +6377,6 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5554,7 +6404,17 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5577,8 +6437,6 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5606,7 +6464,17 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5632,8 +6500,6 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5663,7 +6529,17 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5689,8 +6565,6 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5720,7 +6594,17 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5746,8 +6630,6 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5777,7 +6659,17 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5803,8 +6695,6 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5834,7 +6724,17 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5860,8 +6760,6 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5891,7 +6789,17 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5917,8 +6825,6 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5948,7 +6854,17 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5974,8 +6890,6 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6005,7 +6919,17 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6031,8 +6955,6 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6062,7 +6984,17 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6088,8 +7020,6 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6119,7 +7049,17 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6145,8 +7085,6 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6176,7 +7114,17 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6202,8 +7150,6 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6233,7 +7179,17 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6259,8 +7215,6 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6290,7 +7244,17 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6316,8 +7280,6 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6347,7 +7309,17 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6373,8 +7345,6 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6404,7 +7374,17 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6430,8 +7410,6 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6461,7 +7439,17 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6487,8 +7475,6 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6518,7 +7504,17 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6540,8 +7536,6 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6569,7 +7563,17 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6592,8 +7596,6 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6621,7 +7623,17 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6644,8 +7656,6 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6673,7 +7683,17 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6696,8 +7716,6 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6725,7 +7743,17 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6748,8 +7776,6 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6777,7 +7803,17 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6800,8 +7836,6 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6829,7 +7863,17 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6852,8 +7896,6 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6881,7 +7923,17 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6903,8 +7955,6 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6932,7 +7982,17 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6954,8 +8014,6 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6983,7 +8041,17 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7006,8 +8074,6 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7035,7 +8101,17 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7058,8 +8134,6 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7087,7 +8161,17 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7110,8 +8194,6 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7139,7 +8221,17 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7162,8 +8254,6 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7191,7 +8281,17 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7214,8 +8314,6 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7243,7 +8341,17 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7266,8 +8374,6 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7295,7 +8401,17 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7317,8 +8433,6 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7346,7 +8460,17 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7371,8 +8495,6 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7402,7 +8524,17 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7427,8 +8559,6 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7458,7 +8588,17 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7483,8 +8623,6 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7514,7 +8652,17 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7539,8 +8687,6 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7570,7 +8716,17 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7595,8 +8751,6 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7626,7 +8780,17 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7651,8 +8815,6 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7682,7 +8844,17 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7707,8 +8879,6 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7738,7 +8908,17 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7763,8 +8943,6 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7794,7 +8972,17 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7819,8 +9007,6 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7850,7 +9036,17 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7875,8 +9071,6 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7906,7 +9100,17 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7931,8 +9135,6 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7962,7 +9164,17 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7987,8 +9199,6 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8018,7 +9228,17 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8043,8 +9263,6 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8074,7 +9292,17 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8099,8 +9327,6 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8130,7 +9356,17 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8155,8 +9391,6 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8186,7 +9420,17 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8211,8 +9455,6 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8242,7 +9484,17 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8263,15 +9515,20 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8292,15 +9549,20 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8321,15 +9583,20 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8350,15 +9617,20 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8379,15 +9651,20 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8408,15 +9685,20 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8437,15 +9719,20 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8466,15 +9753,20 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8495,15 +9787,20 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8524,15 +9821,20 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8553,15 +9855,20 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8582,15 +9889,20 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8611,15 +9923,20 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8640,15 +9957,20 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8669,15 +9991,20 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8698,15 +10025,20 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8729,17 +10061,22 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8762,17 +10099,22 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8795,17 +10137,22 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8828,17 +10175,22 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8861,17 +10213,22 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8894,17 +10251,22 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8927,17 +10289,22 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8960,17 +10327,22 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8993,17 +10365,22 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9026,17 +10403,22 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9059,17 +10441,22 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9092,17 +10479,22 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9125,17 +10517,22 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9158,17 +10555,22 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9191,17 +10593,22 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9224,17 +10631,22 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.cpp index 84c23f632487..f99e1ba21b40 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3p.h" -#include "util/except.h" #include #include #include @@ -15,1428 +14,1879 @@ namespace rocjitsu { namespace cdna3 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferInvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbl2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddBf16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddF16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnBf16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnF16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode); -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode); -std::unique_ptr decodeSSetValuCoexecModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x8Xf32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x4Xf32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMovB32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferInvMubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbl2Mubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddBf16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddF16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnBf16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnF16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetValuCoexecModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprMovB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprMovB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x8Xf32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x4Xf32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMovB32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1452,78 +1902,90 @@ struct DecoderImpl { static const std::array sub_decode_mtbuf; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h index 063fee1de4be..07d08a297b7f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA3_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace cdna3 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 4; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace cdna3 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/ds.cpp index 48c81e15ae56..878668d66020 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/ds.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -36,7 +35,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +97,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -117,7 +128,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -144,7 +159,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -171,7 +190,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -198,7 +221,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -225,7 +252,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -252,7 +283,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -279,7 +314,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +345,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +376,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +413,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -391,7 +442,11 @@ DsWriteB32Ds::DsWriteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -422,7 +477,11 @@ DsWrite2B32Ds::DsWrite2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -453,7 +512,12 @@ DsWrite2st64B32Ds::DsWrite2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +550,11 @@ DsCmpstB32Ds::DsCmpstB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -519,7 +587,11 @@ DsCmpstF32Ds::DsCmpstF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -546,7 +618,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -573,7 +649,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +666,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +697,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -635,7 +723,11 @@ DsPkAddF16Ds::DsPkAddF16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddF16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddF16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +749,11 @@ DsPkAddBf16Ds::DsPkAddBf16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddBf16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddBf16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -682,7 +778,12 @@ DsWriteAddtidB32Ds::DsWriteAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +808,11 @@ DsWriteB8Ds::DsWriteB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -732,7 +837,11 @@ DsWriteB16Ds::DsWriteB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -765,7 +874,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -798,7 +911,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -831,7 +948,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +985,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -897,7 +1022,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -930,7 +1059,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -963,7 +1096,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -996,7 +1133,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1029,7 +1170,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1062,7 +1207,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1095,7 +1244,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1128,7 +1281,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1324,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1200,7 +1362,12 @@ DsWrxchgRtnB32Ds::DsWrxchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1239,7 +1406,12 @@ DsWrxchg2RtnB32Ds::DsWrxchg2RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1278,7 +1450,12 @@ DsWrxchg2st64RtnB32Ds::DsWrxchg2st64RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1317,7 +1494,12 @@ DsCmpstRtnB32Ds::DsCmpstRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1356,7 +1538,12 @@ DsCmpstRtnF32Ds::DsCmpstRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1389,7 +1576,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,7 +1613,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1460,7 +1655,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1493,7 +1692,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1721,11 @@ DsReadB32Ds::DsReadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1543,7 +1750,11 @@ DsRead2B32Ds::DsRead2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1568,7 +1779,12 @@ DsRead2st64B32Ds::DsRead2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1593,7 +1809,11 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1618,7 +1838,11 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1643,7 +1867,11 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1668,7 +1896,11 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1689,7 +1921,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1716,7 +1952,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1743,7 +1983,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1770,7 +2015,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2046,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1824,7 +2077,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1851,7 +2108,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1878,7 +2139,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1905,7 +2170,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1932,7 +2201,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1959,7 +2232,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1986,7 +2263,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2013,7 +2294,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2040,7 +2325,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2067,7 +2356,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2100,7 +2393,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2125,7 +2422,11 @@ DsWriteB64Ds::DsWriteB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2156,7 +2457,11 @@ DsWrite2B64Ds::DsWrite2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2187,7 +2492,12 @@ DsWrite2st64B64Ds::DsWrite2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2220,7 +2530,11 @@ DsCmpstB64Ds::DsCmpstB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2253,7 +2567,11 @@ DsCmpstF64Ds::DsCmpstF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2280,7 +2598,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2307,7 +2629,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2332,7 +2658,12 @@ DsWriteB8D16HiDs::DsWriteB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2357,7 +2688,12 @@ DsWriteB16D16HiDs::DsWriteB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2382,7 +2718,11 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2413,7 +2753,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2444,7 +2789,11 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2475,7 +2824,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2506,7 +2860,11 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2537,7 +2895,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2570,7 +2933,11 @@ DsAddF64Ds::DsAddF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2603,7 +2970,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2636,7 +3007,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2669,7 +3044,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2702,7 +3081,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2735,7 +3118,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2768,7 +3155,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2801,7 +3192,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2834,7 +3229,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2867,7 +3266,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2900,7 +3303,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2933,7 +3340,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2966,7 +3377,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3005,7 +3420,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3038,7 +3458,12 @@ DsWrxchgRtnB64Ds::DsWrxchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3077,7 +3502,12 @@ DsWrxchg2RtnB64Ds::DsWrxchg2RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3116,7 +3546,12 @@ DsWrxchg2st64RtnB64Ds::DsWrxchg2st64RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3155,7 +3590,12 @@ DsCmpstRtnB64Ds::DsCmpstRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3194,7 +3634,12 @@ DsCmpstRtnF64Ds::DsCmpstRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3227,7 +3672,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3260,7 +3709,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3285,7 +3738,11 @@ DsReadB64Ds::DsReadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3310,7 +3767,11 @@ DsRead2B64Ds::DsRead2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3335,7 +3796,12 @@ DsRead2st64B64Ds::DsRead2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3368,7 +3834,11 @@ DsAddRtnF64Ds::DsAddRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3401,7 +3871,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3414,7 +3889,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3429,7 +3909,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3442,7 +3926,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3457,7 +3945,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3470,7 +3962,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3485,7 +3981,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3510,7 +4010,12 @@ DsReadAddtidB32Ds::DsReadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3538,7 +4043,12 @@ DsPkAddRtnF16Ds::DsPkAddRtnF16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnF16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnF16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_rtn_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3566,7 +4076,12 @@ DsPkAddRtnBf16Ds::DsPkAddRtnBf16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnBf16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnBf16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_rtn_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3591,7 +4106,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3616,7 +4135,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3641,7 +4164,11 @@ DsWriteB96Ds::DsWriteB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3666,7 +4193,11 @@ DsWriteB128Ds::DsWriteB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3691,7 +4222,11 @@ DsReadB96Ds::DsReadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3716,7 +4251,11 @@ DsReadB128Ds::DsReadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h index 938dfb245d7e..6cf87c92a71a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna3/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/flat.cpp index b1a01fd48f5c..aa44704e3320 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/flat.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -48,7 +47,12 @@ FlatLoadUbyteFlat::FlatLoadUbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -87,7 +91,12 @@ FlatLoadSbyteFlat::FlatLoadSbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +135,12 @@ FlatLoadUshortFlat::FlatLoadUshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -165,7 +179,12 @@ FlatLoadSshortFlat::FlatLoadSshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -204,7 +223,12 @@ FlatLoadDwordFlat::FlatLoadDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +267,12 @@ FlatLoadDwordx2Flat::FlatLoadDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -282,7 +311,12 @@ FlatLoadDwordx3Flat::FlatLoadDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -321,7 +355,12 @@ FlatLoadDwordx4Flat::FlatLoadDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +399,12 @@ FlatStoreByteFlat::FlatStoreByteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +443,12 @@ FlatStoreByteD16HiFlat::FlatStoreByteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -438,7 +487,12 @@ FlatStoreShortFlat::FlatStoreShortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -477,7 +531,12 @@ FlatStoreShortD16HiFlat::FlatStoreShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +575,12 @@ FlatStoreDwordFlat::FlatStoreDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -555,7 +619,12 @@ FlatStoreDwordx2Flat::FlatStoreDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -594,7 +663,12 @@ FlatStoreDwordx3Flat::FlatStoreDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -633,7 +707,12 @@ FlatStoreDwordx4Flat::FlatStoreDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -672,7 +751,12 @@ FlatLoadUbyteD16Flat::FlatLoadUbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -718,7 +802,12 @@ FlatLoadUbyteD16HiFlat::FlatLoadUbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -764,7 +853,12 @@ FlatLoadSbyteD16Flat::FlatLoadSbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -810,7 +904,12 @@ FlatLoadSbyteD16HiFlat::FlatLoadSbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -856,7 +955,12 @@ FlatLoadShortD16Flat::FlatLoadShortD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -902,7 +1006,12 @@ FlatLoadShortD16HiFlat::FlatLoadShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -955,7 +1064,12 @@ FlatAtomicSwapFlat::FlatAtomicSwapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1001,7 +1115,12 @@ FlatAtomicCmpswapFlat::FlatAtomicCmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1047,7 +1166,12 @@ FlatAtomicAddFlat::FlatAtomicAddFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1093,7 +1217,12 @@ FlatAtomicSubFlat::FlatAtomicSubFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1139,7 +1268,12 @@ FlatAtomicSminFlat::FlatAtomicSminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1185,7 +1319,12 @@ FlatAtomicUminFlat::FlatAtomicUminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1231,7 +1370,12 @@ FlatAtomicSmaxFlat::FlatAtomicSmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1277,7 +1421,12 @@ FlatAtomicUmaxFlat::FlatAtomicUmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1323,7 +1472,12 @@ FlatAtomicAndFlat::FlatAtomicAndFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1369,7 +1523,12 @@ FlatAtomicOrFlat::FlatAtomicOrFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1415,7 +1574,12 @@ FlatAtomicXorFlat::FlatAtomicXorFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1461,7 +1625,12 @@ FlatAtomicIncFlat::FlatAtomicIncFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1507,7 +1676,12 @@ FlatAtomicDecFlat::FlatAtomicDecFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1553,7 +1727,12 @@ FlatAtomicAddF32Flat::FlatAtomicAddF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1599,7 +1778,12 @@ FlatAtomicPkAddF16Flat::FlatAtomicPkAddF16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1645,7 +1829,12 @@ FlatAtomicAddF64Flat::FlatAtomicAddF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1691,7 +1880,12 @@ FlatAtomicMinF64Flat::FlatAtomicMinF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1737,7 +1931,12 @@ FlatAtomicMaxF64Flat::FlatAtomicMaxF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1783,7 +1982,12 @@ FlatAtomicPkAddBf16Flat::FlatAtomicPkAddBf16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1829,7 +2033,12 @@ FlatAtomicSwapX2Flat::FlatAtomicSwapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1875,7 +2084,12 @@ FlatAtomicCmpswapX2Flat::FlatAtomicCmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1921,7 +2135,12 @@ FlatAtomicAddX2Flat::FlatAtomicAddX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1967,7 +2186,12 @@ FlatAtomicSubX2Flat::FlatAtomicSubX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2013,7 +2237,12 @@ FlatAtomicSminX2Flat::FlatAtomicSminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2059,7 +2288,12 @@ FlatAtomicUminX2Flat::FlatAtomicUminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2105,7 +2339,12 @@ FlatAtomicSmaxX2Flat::FlatAtomicSmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2151,7 +2390,12 @@ FlatAtomicUmaxX2Flat::FlatAtomicUmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2197,7 +2441,12 @@ FlatAtomicAndX2Flat::FlatAtomicAndX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2243,7 +2492,12 @@ FlatAtomicOrX2Flat::FlatAtomicOrX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2289,7 +2543,12 @@ FlatAtomicXorX2Flat::FlatAtomicXorX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2335,7 +2594,12 @@ FlatAtomicIncX2Flat::FlatAtomicIncX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2381,7 +2645,12 @@ FlatAtomicDecX2Flat::FlatAtomicDecX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mtbuf.cpp index d55e8724d7bc..d74d2e8f42f4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mtbuf.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -47,7 +46,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +79,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -103,7 +112,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -131,7 +145,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +178,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -187,7 +211,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +244,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +277,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -271,7 +310,12 @@ TbufferLoadFormatD16XMtbuf::TbufferLoadFormatD16XMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -305,7 +349,13 @@ TbufferLoadFormatD16XyMtbuf::TbufferLoadFormatD16XyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +383,13 @@ TbufferLoadFormatD16XyzMtbuf::TbufferLoadFormatD16XyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -367,7 +423,13 @@ TbufferLoadFormatD16XyzwMtbuf::TbufferLoadFormatD16XyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -395,7 +457,13 @@ TbufferStoreFormatD16XMtbuf::TbufferStoreFormatD16XMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -423,7 +491,13 @@ TbufferStoreFormatD16XyMtbuf::TbufferStoreFormatD16XyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +525,13 @@ TbufferStoreFormatD16XyzMtbuf::TbufferStoreFormatD16XyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -479,7 +559,13 @@ TbufferStoreFormatD16XyzwMtbuf::TbufferStoreFormatD16XyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf.cpp index 0cd875d0abf4..d5082067abe9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/mubuf.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -47,7 +46,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +79,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -103,7 +112,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -131,7 +145,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +178,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -187,7 +211,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +244,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +277,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -271,7 +310,12 @@ BufferLoadFormatD16XMubuf::BufferLoadFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +350,12 @@ BufferLoadFormatD16XyMubuf::BufferLoadFormatD16XyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -334,7 +383,13 @@ BufferLoadFormatD16XyzMubuf::BufferLoadFormatD16XyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -369,7 +424,13 @@ BufferLoadFormatD16XyzwMubuf::BufferLoadFormatD16XyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -397,7 +458,12 @@ BufferStoreFormatD16XMubuf::BufferStoreFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -425,7 +491,13 @@ BufferStoreFormatD16XyMubuf::BufferStoreFormatD16XyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -453,7 +525,13 @@ BufferStoreFormatD16XyzMubuf::BufferStoreFormatD16XyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +559,13 @@ BufferStoreFormatD16XyzwMubuf::BufferStoreFormatD16XyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -509,7 +593,12 @@ BufferLoadUbyteMubuf::BufferLoadUbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +626,12 @@ BufferLoadSbyteMubuf::BufferLoadSbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -565,7 +659,12 @@ BufferLoadUshortMubuf::BufferLoadUshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +692,12 @@ BufferLoadSshortMubuf::BufferLoadSshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -621,7 +725,12 @@ BufferLoadDwordMubuf::BufferLoadDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -649,7 +758,12 @@ BufferLoadDwordx2Mubuf::BufferLoadDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -677,7 +791,12 @@ BufferLoadDwordx3Mubuf::BufferLoadDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -705,7 +824,12 @@ BufferLoadDwordx4Mubuf::BufferLoadDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -733,7 +857,12 @@ BufferStoreByteMubuf::BufferStoreByteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -761,7 +890,12 @@ BufferStoreByteD16HiMubuf::BufferStoreByteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -789,7 +923,12 @@ BufferStoreShortMubuf::BufferStoreShortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -817,7 +956,12 @@ BufferStoreShortD16HiMubuf::BufferStoreShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -845,7 +989,12 @@ BufferStoreDwordMubuf::BufferStoreDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +1022,12 @@ BufferStoreDwordx2Mubuf::BufferStoreDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -901,7 +1055,12 @@ BufferStoreDwordx3Mubuf::BufferStoreDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -929,7 +1088,12 @@ BufferStoreDwordx4Mubuf::BufferStoreDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -957,7 +1121,12 @@ BufferLoadUbyteD16Mubuf::BufferLoadUbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -992,7 +1161,12 @@ BufferLoadUbyteD16HiMubuf::BufferLoadUbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1027,7 +1201,12 @@ BufferLoadSbyteD16Mubuf::BufferLoadSbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1062,7 +1241,12 @@ BufferLoadSbyteD16HiMubuf::BufferLoadSbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1281,12 @@ BufferLoadShortD16Mubuf::BufferLoadShortD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1132,7 +1321,12 @@ BufferLoadShortD16HiMubuf::BufferLoadShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1361,13 @@ BufferLoadFormatD16HiXMubuf::BufferLoadFormatD16HiXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1202,7 +1402,13 @@ BufferStoreFormatD16HiXMubuf::BufferStoreFormatD16HiXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1215,7 +1421,12 @@ BufferWbl2Mubuf::BufferWbl2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbl2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbl2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbl2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1439,11 @@ BufferInvMubuf::BufferInvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferInvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferInvMubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1258,7 +1473,12 @@ BufferAtomicSwapMubuf::BufferAtomicSwapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,7 +1513,12 @@ BufferAtomicCmpswapMubuf::BufferAtomicCmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1323,7 +1548,12 @@ BufferAtomicAddMubuf::BufferAtomicAddMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1353,7 +1583,12 @@ BufferAtomicSubMubuf::BufferAtomicSubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1383,7 +1618,12 @@ BufferAtomicSminMubuf::BufferAtomicSminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1413,7 +1653,12 @@ BufferAtomicUminMubuf::BufferAtomicUminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1443,7 +1688,12 @@ BufferAtomicSmaxMubuf::BufferAtomicSmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1473,7 +1723,12 @@ BufferAtomicUmaxMubuf::BufferAtomicUmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,7 +1758,12 @@ BufferAtomicAndMubuf::BufferAtomicAndMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1533,7 +1793,12 @@ BufferAtomicOrMubuf::BufferAtomicOrMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1563,7 +1828,12 @@ BufferAtomicXorMubuf::BufferAtomicXorMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1593,7 +1863,12 @@ BufferAtomicIncMubuf::BufferAtomicIncMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1623,7 +1898,12 @@ BufferAtomicDecMubuf::BufferAtomicDecMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1653,7 +1933,12 @@ BufferAtomicAddF32Mubuf::BufferAtomicAddF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1683,7 +1968,12 @@ BufferAtomicPkAddF16Mubuf::BufferAtomicPkAddF16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1713,7 +2003,12 @@ BufferAtomicAddF64Mubuf::BufferAtomicAddF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1743,7 +2038,12 @@ BufferAtomicMinF64Mubuf::BufferAtomicMinF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1773,7 +2073,12 @@ BufferAtomicMaxF64Mubuf::BufferAtomicMaxF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1803,7 +2108,12 @@ BufferAtomicSwapX2Mubuf::BufferAtomicSwapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1838,7 +2148,12 @@ BufferAtomicCmpswapX2Mubuf::BufferAtomicCmpswapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1868,7 +2183,12 @@ BufferAtomicAddX2Mubuf::BufferAtomicAddX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1898,7 +2218,12 @@ BufferAtomicSubX2Mubuf::BufferAtomicSubX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1928,7 +2253,12 @@ BufferAtomicSminX2Mubuf::BufferAtomicSminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1958,7 +2288,12 @@ BufferAtomicUminX2Mubuf::BufferAtomicUminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1988,7 +2323,12 @@ BufferAtomicSmaxX2Mubuf::BufferAtomicSmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2018,7 +2358,12 @@ BufferAtomicUmaxX2Mubuf::BufferAtomicUmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2048,7 +2393,12 @@ BufferAtomicAndX2Mubuf::BufferAtomicAndX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2078,7 +2428,12 @@ BufferAtomicOrX2Mubuf::BufferAtomicOrX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2108,7 +2463,12 @@ BufferAtomicXorX2Mubuf::BufferAtomicXorX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2138,7 +2498,12 @@ BufferAtomicIncX2Mubuf::BufferAtomicIncX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2168,7 +2533,12 @@ BufferAtomicDecX2Mubuf::BufferAtomicDecX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp index 33555272cba0..c80a52b2cce8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem.cpp index e8d298620c00..9eab7801662f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -44,7 +43,11 @@ SLoadDwordSmem::SLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +67,12 @@ SLoadDwordx2Smem::SLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -84,7 +92,12 @@ SLoadDwordx4Smem::SLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -104,7 +117,12 @@ SLoadDwordx8Smem::SLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -124,7 +142,12 @@ SLoadDwordx16Smem::SLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -144,7 +167,12 @@ SScratchLoadDwordSmem::SScratchLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -164,7 +192,12 @@ SScratchLoadDwordx2Smem::SScratchLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -184,7 +217,12 @@ SScratchLoadDwordx4Smem::SScratchLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -204,7 +242,12 @@ SBufferLoadDwordSmem::SBufferLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +267,12 @@ SBufferLoadDwordx2Smem::SBufferLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -244,7 +292,12 @@ SBufferLoadDwordx4Smem::SBufferLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +317,12 @@ SBufferLoadDwordx8Smem::SBufferLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +342,12 @@ SBufferLoadDwordx16Smem::SBufferLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -304,7 +367,12 @@ SStoreDwordSmem::SStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -324,7 +392,12 @@ SStoreDwordx2Smem::SStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +417,12 @@ SStoreDwordx4Smem::SStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -364,7 +442,12 @@ SScratchStoreDwordSmem::SScratchStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +467,12 @@ SScratchStoreDwordx2Smem::SScratchStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -404,7 +492,12 @@ SScratchStoreDwordx4Smem::SScratchStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +517,12 @@ SBufferStoreDwordSmem::SBufferStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -444,7 +542,12 @@ SBufferStoreDwordx2Smem::SBufferStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -464,7 +567,12 @@ SBufferStoreDwordx4Smem::SBufferStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -477,7 +585,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -490,7 +602,11 @@ SDcacheWbSmem::SDcacheWbSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +619,12 @@ SDcacheInvVolSmem::SDcacheInvVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +637,12 @@ SDcacheWbVolSmem::SDcacheWbVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +657,11 @@ SMemtimeSmem::SMemtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -546,7 +676,12 @@ SMemrealtimeSmem::SMemrealtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memrealtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -565,7 +700,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -584,7 +723,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +745,12 @@ SDcacheDiscardSmem::SDcacheDiscardSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -618,7 +767,12 @@ SDcacheDiscardX2Smem::SDcacheDiscardX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +792,12 @@ SBufferAtomicSwapSmem::SBufferAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -658,7 +817,12 @@ SBufferAtomicCmpswapSmem::SBufferAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +842,12 @@ SBufferAtomicAddSmem::SBufferAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -698,7 +867,12 @@ SBufferAtomicSubSmem::SBufferAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -718,7 +892,12 @@ SBufferAtomicSminSmem::SBufferAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -738,7 +917,12 @@ SBufferAtomicUminSmem::SBufferAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +942,12 @@ SBufferAtomicSmaxSmem::SBufferAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -778,7 +967,12 @@ SBufferAtomicUmaxSmem::SBufferAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -798,7 +992,12 @@ SBufferAtomicAndSmem::SBufferAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -818,7 +1017,12 @@ SBufferAtomicOrSmem::SBufferAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -838,7 +1042,12 @@ SBufferAtomicXorSmem::SBufferAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +1067,12 @@ SBufferAtomicIncSmem::SBufferAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -878,7 +1092,12 @@ SBufferAtomicDecSmem::SBufferAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -898,7 +1117,12 @@ SBufferAtomicSwapX2Smem::SBufferAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -918,7 +1142,12 @@ SBufferAtomicCmpswapX2Smem::SBufferAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -938,7 +1167,12 @@ SBufferAtomicAddX2Smem::SBufferAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1192,12 @@ SBufferAtomicSubX2Smem::SBufferAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -978,7 +1217,12 @@ SBufferAtomicSminX2Smem::SBufferAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -998,7 +1242,12 @@ SBufferAtomicUminX2Smem::SBufferAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1018,7 +1267,12 @@ SBufferAtomicSmaxX2Smem::SBufferAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1038,7 +1292,12 @@ SBufferAtomicUmaxX2Smem::SBufferAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1058,7 +1317,12 @@ SBufferAtomicAndX2Smem::SBufferAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1078,7 +1342,12 @@ SBufferAtomicOrX2Smem::SBufferAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1367,12 @@ SBufferAtomicXorX2Smem::SBufferAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1118,7 +1392,12 @@ SBufferAtomicIncX2Smem::SBufferAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1417,12 @@ SBufferAtomicDecX2Smem::SBufferAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1158,7 +1442,12 @@ SAtomicSwapSmem::SAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1178,7 +1467,12 @@ SAtomicCmpswapSmem::SAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1198,7 +1492,11 @@ SAtomicAddSmem::SAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1218,7 +1516,11 @@ SAtomicSubSmem::SAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1540,12 @@ SAtomicSminSmem::SAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1258,7 +1565,12 @@ SAtomicUminSmem::SAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1278,7 +1590,12 @@ SAtomicSmaxSmem::SAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1298,7 +1615,12 @@ SAtomicUmaxSmem::SAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1318,7 +1640,11 @@ SAtomicAndSmem::SAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1664,11 @@ SAtomicOrSmem::SAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1358,7 +1688,11 @@ SAtomicXorSmem::SAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1378,7 +1712,11 @@ SAtomicIncSmem::SAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1398,7 +1736,11 @@ SAtomicDecSmem::SAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1418,7 +1760,12 @@ SAtomicSwapX2Smem::SAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1438,7 +1785,12 @@ SAtomicCmpswapX2Smem::SAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1458,7 +1810,12 @@ SAtomicAddX2Smem::SAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1478,7 +1835,12 @@ SAtomicSubX2Smem::SAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1498,7 +1860,12 @@ SAtomicSminX2Smem::SAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1885,12 @@ SAtomicUminX2Smem::SAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1538,7 +1910,12 @@ SAtomicSmaxX2Smem::SAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1558,7 +1935,12 @@ SAtomicUmaxX2Smem::SAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1578,7 +1960,12 @@ SAtomicAndX2Smem::SAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1598,7 +1985,12 @@ SAtomicOrX2Smem::SAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1618,7 +2010,12 @@ SAtomicXorX2Smem::SAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1638,7 +2035,12 @@ SAtomicIncX2Smem::SAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1658,7 +2060,12 @@ SAtomicDecX2Smem::SAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1.cpp index 65a71156d389..e49027b2e2ad 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +173,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +201,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +230,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +255,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +281,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -295,7 +339,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -319,7 +368,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +398,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +424,11 @@ SFf0I32B32Sop1::SFf0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +450,11 @@ SFf0I32B64Sop1::SFf0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +475,11 @@ SFf1I32B32Sop1::SFf1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +501,11 @@ SFf1I32B64Sop1::SFf1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +526,12 @@ SFlbitI32B32Sop1::SFlbitI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +553,12 @@ SFlbitI32B64Sop1::SFlbitI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +579,11 @@ SFlbitI32Sop1::SFlbitI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +605,12 @@ SFlbitI32I64Sop1::SFlbitI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +632,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +658,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +685,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -604,7 +712,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +739,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +766,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +789,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -685,7 +812,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +839,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +861,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +897,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +935,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -823,7 +972,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +1009,12 @@ SAndn2SaveexecB64Sop1::SAndn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -887,7 +1046,12 @@ SOrn2SaveexecB64Sop1::SOrn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -919,7 +1083,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1120,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -983,7 +1157,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1007,7 +1186,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1216,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1241,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1266,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1295,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1325,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1141,7 +1350,12 @@ SCbranchJoinSop1::SCbranchJoinSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode) { +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cbranch_join", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1379,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1189,7 +1407,12 @@ SSetGprIdxIdxSop1::SSetGprIdxIdxSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_set_gpr_idx_idx", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1444,12 @@ SAndn1SaveexecB64Sop1::SAndn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1253,7 +1481,12 @@ SOrn1SaveexecB64Sop1::SOrn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1285,7 +1518,12 @@ SAndn1WrexecB64Sop1::SAndn1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1317,7 +1555,12 @@ SAndn2WrexecB64Sop1::SAndn2WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1581,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop2.cpp index 0b5c5cec5fc6..7a70ba66bd4c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +280,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +314,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +348,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +382,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +454,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +490,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +525,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +562,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +596,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +632,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +666,11 @@ SAndn2B32Sop2::SAndn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +702,11 @@ SAndn2B64Sop2::SAndn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +736,11 @@ SOrn2B32Sop2::SOrn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +772,11 @@ SOrn2B64Sop2::SOrn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +806,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +842,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -779,7 +876,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -811,7 +912,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +946,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +982,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1016,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1051,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1085,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1120,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1154,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1189,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1220,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1251,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1282,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1316,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1350,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1385,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1420,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1444,12 @@ SCbranchGForkSop2::SCbranchGForkSop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode) { +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cbranch_g_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1479,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1513,12 @@ SRfeRestoreB64Sop2::SRfeRestoreB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_rfe_restore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1365,7 +1545,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1392,7 +1576,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,7 +1610,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1645,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1680,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1715,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1749,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1569,7 +1782,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1596,7 +1814,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp index 947171d10598..164aae061d92 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -482,7 +549,11 @@ SSetvskipSopc::SSetvskipSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode) { +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_setvskip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +579,12 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_set_gpr_idx_on", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +614,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +648,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopk.cpp index 56fcff3fd230..2a30a58b693f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -46,7 +49,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +73,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,7 +97,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +121,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +145,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +169,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +193,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +217,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -206,7 +241,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -226,7 +265,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +289,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +313,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -286,7 +337,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +362,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +384,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +405,12 @@ SCbranchIForkSopk::SCbranchIForkSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode) { +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cbranch_i_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +427,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +448,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -395,7 +471,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +499,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopp.cpp index 26a891e1b9ae..76a89cf044cf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -36,7 +39,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +60,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +82,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +106,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +136,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +166,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +196,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +226,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +256,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +280,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +299,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +338,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +357,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +376,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +398,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,7 +420,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -362,7 +440,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +457,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +476,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +496,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +517,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +537,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +577,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +597,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +616,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +634,12 @@ SSetGprIdxOffSopp::SSetGprIdxOffSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_off", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -528,7 +659,12 @@ SSetGprIdxModeSopp::SSetGprIdxModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -542,7 +678,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +698,12 @@ SSetValuCoexecModeSopp::SSetValuCoexecModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetValuCoexecModeSopp(const MachineInst *opcode) { +DecodeResult decodeSSetValuCoexecModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_valu_coexec_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp index 93d108120d45..8efb157c82b8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,14 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +78,14 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,14 +99,20 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_readfirstlane_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -120,12 +139,17 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -151,12 +175,17 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_i32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -206,7 +235,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +293,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +351,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +409,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -406,7 +467,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +532,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -513,7 +590,16 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +649,16 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +708,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,12 +744,17 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -663,14 +772,19 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -720,7 +834,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +893,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -820,7 +952,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -870,7 +1011,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -897,12 +1047,17 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_U32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_u32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -928,12 +1083,17 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_U32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_u32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -960,12 +1120,17 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_TRUNC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_trunc_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -992,12 +1157,17 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CEIL_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_ceil_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1016,14 +1186,19 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RNDNE_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rndne_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1050,12 +1225,17 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FLOOR_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_floor_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1104,7 +1284,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1153,7 +1341,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1202,7 +1398,14 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1251,7 +1454,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1300,7 +1511,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1568,14 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1398,7 +1624,14 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1680,14 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1737,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1795,14 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1565,14 +1821,19 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RCP_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rcp_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1591,14 +1852,19 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RSQ_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rsq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1647,7 +1913,14 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1666,14 +1939,19 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SQRT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_sqrt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1722,7 +2000,14 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1771,7 +2056,14 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1820,7 +2112,14 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1869,7 +2168,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1918,7 +2225,14 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1967,7 +2281,14 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2016,7 +2337,14 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2043,12 +2371,18 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_exp_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2075,12 +2409,18 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_mant_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2107,12 +2447,17 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FRACT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_fract_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2162,7 +2507,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2212,7 +2566,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2225,7 +2588,11 @@ VClrexcpVop1::VClrexcpVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop1::validate_encoding( + "v_clrexcp_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2275,7 +2642,16 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2701,14 @@ VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b64_sdwa" + : "v_mov_b64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2376,7 +2759,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2433,7 +2824,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2490,7 +2889,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2547,7 +2954,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2603,7 +3018,14 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2659,7 +3081,14 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2715,7 +3144,14 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2771,7 +3207,14 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2827,7 +3270,14 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2884,7 +3334,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2941,7 +3400,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2997,7 +3465,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3053,7 +3529,14 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3109,7 +3592,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3165,7 +3656,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3221,7 +3720,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3277,7 +3784,14 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3333,7 +3847,14 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3390,7 +3911,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3447,7 +3977,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3503,7 +4042,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3525,14 +4073,19 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_swap_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3584,7 +4137,16 @@ VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVAccvgprMovB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_accvgpr_mov_b32_sdwa" + : "v_accvgpr_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3634,7 +4196,15 @@ VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_fp8_sdwa" + : "v_cvt_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3684,7 +4254,15 @@ VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_bf8_sdwa" + : "v_cvt_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3735,7 +4313,16 @@ VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_fp8_sdwa" + : "v_cvt_pk_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3786,7 +4373,16 @@ VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_bf8_sdwa" + : "v_cvt_pk_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp index cd10bc7eb8cf..f5b9a37f2568 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -67,7 +66,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +130,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +192,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +255,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,12 +293,17 @@ VFmacF64Vop2::VFmacF64Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -323,7 +358,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -379,7 +421,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +485,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -491,7 +550,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -547,7 +614,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +678,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +740,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -712,7 +802,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -767,7 +864,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -822,7 +926,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +988,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -933,7 +1051,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -989,7 +1116,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1045,7 +1181,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1100,7 +1245,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1307,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1210,7 +1369,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1235,14 +1401,19 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAMK_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmamk_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1267,14 +1438,19 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAAK_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmaak_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1333,7 +1509,15 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1392,7 +1576,15 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1451,7 +1643,16 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1513,7 +1714,15 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1575,7 +1784,15 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1637,7 +1854,16 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1693,7 +1919,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +1988,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,7 +2058,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1880,7 +2128,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1916,12 +2171,17 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_mac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1954,14 +2214,19 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADMK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madmk_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1994,14 +2259,19 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADAK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madak_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2063,7 +2333,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2125,7 +2402,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2188,7 +2472,15 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2251,7 +2543,15 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2314,7 +2614,16 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2377,7 +2686,16 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2440,7 +2758,16 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2502,7 +2829,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2564,7 +2898,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2626,7 +2967,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2688,7 +3036,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2750,7 +3105,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2812,7 +3174,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2874,7 +3243,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2935,7 +3312,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2990,7 +3374,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3046,7 +3437,15 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3075,12 +3474,18 @@ VDot2cF32F16Vop2::VDot2cF32F16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_f32_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3109,12 +3514,18 @@ VDot2cI32I16Vop2::VDot2cI32I16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_I32_I16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_i32_i16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_I32_I16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3143,12 +3554,18 @@ VDot4cI32I8Vop2::VDot4cI32I8Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT4C_I32_I8 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot4c_i32_i8_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT4C_I32_I8 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3177,12 +3594,18 @@ VDot8cI32I4Vop2::VDot8cI32I4Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT8C_I32_I4 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot8c_i32_i4_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT8C_I32_I4 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3211,12 +3634,17 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3245,12 +3673,17 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PK_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_pk_fmac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3305,7 +3738,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3.cpp index d1afcb9d109b..009465e4898b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -21,7 +20,11 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -38,7 +41,11 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -55,7 +62,12 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readfirstlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +84,11 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -89,7 +105,11 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +126,11 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +147,11 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -157,7 +189,11 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +210,11 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +237,11 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +258,12 @@ VCvtRpiI32F32Vop3::VCvtRpiI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_rpi_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +280,12 @@ VCvtFlrI32F32Vop3::VCvtFlrI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_flr_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -248,7 +302,12 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_off_f32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +324,11 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -282,7 +345,11 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +366,12 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -316,7 +388,12 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +410,12 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +432,12 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -367,7 +454,11 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +475,11 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +496,11 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +517,11 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +538,11 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +559,11 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +580,11 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +601,11 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +622,11 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +643,11 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +664,11 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +685,11 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +706,11 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -588,7 +727,11 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -605,7 +748,12 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_iflag_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -622,7 +770,11 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -639,7 +791,11 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -656,7 +812,11 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -673,7 +833,11 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -690,7 +854,11 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +875,11 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -724,7 +896,11 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +917,11 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +938,11 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -775,7 +959,11 @@ VFfbhU32Vop3::VFfbhU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -792,7 +980,11 @@ VFfblB32Vop3::VFfblB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +1001,11 @@ VFfbhI32Vop3::VFfbhI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -826,7 +1022,12 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -843,7 +1044,12 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -860,7 +1066,11 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1087,12 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1109,12 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -907,7 +1127,11 @@ VClrexcpVop3::VClrexcpVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_clrexcp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1148,12 @@ VScreenPartition4seB32Vop3::VScreenPartition4seB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_screen_partition_4se_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -941,7 +1170,11 @@ VMovB64Vop3::VMovB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1191,11 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -981,7 +1218,11 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1004,7 +1245,11 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1027,7 +1272,11 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1299,11 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1073,7 +1326,11 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1353,11 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1119,7 +1380,11 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1407,11 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1434,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1188,7 +1462,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1211,7 +1490,11 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1234,7 +1517,11 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1257,7 +1544,11 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1280,7 +1571,11 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1303,7 +1598,11 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1326,7 +1625,11 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1652,11 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1372,7 +1679,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1395,7 +1707,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1418,7 +1735,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sat_pk_u8_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1443,7 +1765,11 @@ VSwapB32Vop3::VSwapB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1792,12 @@ VAccvgprMovB32Vop3::VAccvgprMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAccvgprMovB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_accvgpr_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1483,7 +1814,11 @@ VCvtF32Fp8Vop3::VCvtF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1500,7 +1835,11 @@ VCvtF32Bf8Vop3::VCvtF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1517,7 +1856,12 @@ VCvtPkF32Fp8Vop3::VCvtPkF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_f32_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1534,7 +1878,12 @@ VCvtPkF32Bf8Vop3::VCvtPkF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_f32_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1555,7 +1904,12 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cndmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1574,7 +1928,11 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1593,7 +1951,11 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1612,7 +1974,11 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1632,7 +1998,11 @@ VFmacF64Vop3::VFmacF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1651,7 +2021,11 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1670,7 +2044,11 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1689,7 +2067,12 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1708,7 +2091,11 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1727,7 +2114,12 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1746,7 +2138,11 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1765,7 +2161,11 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1784,7 +2184,11 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1803,7 +2207,11 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1822,7 +2230,11 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1841,7 +2253,11 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1860,7 +2276,12 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1879,7 +2300,12 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1898,7 +2324,12 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1917,7 +2348,11 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1936,7 +2371,11 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1955,7 +2394,11 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1974,7 +2417,11 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1999,7 +2446,11 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2024,7 +2475,11 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2049,7 +2504,11 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2075,7 +2534,11 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2100,7 +2563,11 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2125,7 +2592,11 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2150,7 +2621,11 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2175,7 +2650,11 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2200,7 +2679,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2225,7 +2709,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2250,7 +2739,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2275,7 +2769,11 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2300,7 +2798,11 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2827,11 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2350,7 +2856,11 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2375,7 +2885,11 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2400,7 +2914,11 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2425,7 +2943,11 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2450,7 +2972,11 @@ VAddU32Vop3::VAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2469,7 +2995,11 @@ VSubU32Vop3::VSubU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2488,7 +3018,11 @@ VSubrevU32Vop3::VSubrevU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2508,7 +3042,12 @@ VDot2cF32F16Vop3::VDot2cF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2528,7 +3067,12 @@ VDot2cI32I16Vop3::VDot2cI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2548,7 +3092,12 @@ VDot4cI32I8Vop3::VDot4cI32I8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot4c_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2568,7 +3117,12 @@ VDot8cI32I4Vop3::VDot8cI32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot8c_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2588,7 +3142,11 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2608,7 +3166,11 @@ VPkFmacF16Vop3::VPkFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pk_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2627,7 +3189,11 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2648,7 +3214,11 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2669,7 +3239,11 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2690,7 +3264,11 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubeid_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2711,7 +3289,11 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubesc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2732,7 +3314,11 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubetc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3339,11 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubema_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2774,7 +3364,11 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2795,7 +3389,11 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2816,7 +3414,11 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2837,7 +3439,11 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2858,7 +3464,11 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2879,7 +3489,11 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lerp_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2900,7 +3514,12 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbit_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2921,7 +3540,12 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbyte_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2942,7 +3566,11 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2963,7 +3591,11 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2984,7 +3616,11 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3005,7 +3641,11 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3026,7 +3666,11 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3047,7 +3691,11 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3068,7 +3716,11 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3089,7 +3741,11 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3110,7 +3766,11 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3131,7 +3791,11 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3152,7 +3816,11 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3173,7 +3841,11 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3194,7 +3866,11 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3215,7 +3891,12 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3236,7 +3917,12 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3257,7 +3943,12 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3281,7 +3972,12 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3305,7 +4001,12 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3326,7 +4027,11 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_msad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3347,7 +4052,12 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_qsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3368,7 +4078,12 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3389,7 +4104,12 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3410,7 +4130,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3437,7 +4162,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3464,7 +4194,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3491,7 +4226,11 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_perm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3512,7 +4251,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3539,7 +4283,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3565,7 +4314,12 @@ VCvtPkaccumU8F32Vop3::VCvtPkaccumU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkaccum_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3586,7 +4340,11 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3607,7 +4365,11 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3628,7 +4390,11 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3649,7 +4415,11 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3676,7 +4446,11 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3703,7 +4477,11 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3730,7 +4508,11 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3757,7 +4539,11 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3784,7 +4570,11 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3811,7 +4601,11 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3838,7 +4632,11 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3865,7 +4663,11 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3892,7 +4694,12 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3913,7 +4720,12 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_lshl_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3934,7 +4746,11 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3955,7 +4771,11 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3976,7 +4796,11 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3997,7 +4821,11 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4018,7 +4846,11 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4045,7 +4877,11 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4072,7 +4908,11 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4099,7 +4939,11 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4126,7 +4970,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4153,7 +5002,12 @@ VLshlAddU64Vop3::VLshlAddU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4172,7 +5026,11 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4191,7 +5049,11 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4210,7 +5072,11 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4229,7 +5095,11 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4248,7 +5118,11 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4267,7 +5141,11 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4286,7 +5164,11 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4305,7 +5187,11 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4324,7 +5210,11 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4343,7 +5233,12 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4363,7 +5258,12 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_writelane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4382,7 +5282,12 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bcnt_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4401,7 +5306,12 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_lo_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4420,7 +5330,12 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_hi_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4439,7 +5354,12 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4458,7 +5378,12 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4477,7 +5402,12 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4496,7 +5426,12 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trig_preop_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4515,7 +5450,11 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4534,7 +5473,12 @@ VCvtPknormI16F32Vop3::VCvtPknormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4553,7 +5497,12 @@ VCvtPknormU16F32Vop3::VCvtPknormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4572,7 +5521,12 @@ VCvtPkrtzF16F32Vop3::VCvtPkrtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkrtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4591,7 +5545,12 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u16_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4610,7 +5569,12 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_i16_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4629,7 +5593,12 @@ VCvtPknormI16F16Vop3::VCvtPknormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4648,7 +5617,12 @@ VCvtPknormU16F16Vop3::VCvtPknormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4667,7 +5641,11 @@ VAddI32Vop3::VAddI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4686,7 +5664,11 @@ VSubI32Vop3::VSubI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4705,7 +5687,11 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4730,7 +5716,11 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4755,7 +5745,12 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pack_b32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4774,7 +5769,12 @@ VMulLegacyF32Vop3::VMulLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4794,7 +5794,12 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_fp8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4820,7 +5825,12 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_bf8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4846,7 +5856,12 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_sr_fp8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4872,7 +5887,12 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_sr_bf8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4897,7 +5917,12 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4920,7 +5945,12 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4939,7 +5969,12 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4962,7 +5997,12 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4981,7 +6021,12 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5004,7 +6049,12 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5023,7 +6073,11 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5042,7 +6096,11 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5061,7 +6119,11 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5080,7 +6142,11 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5099,7 +6165,11 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5118,7 +6188,11 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5137,7 +6211,11 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5156,7 +6234,11 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5175,7 +6257,11 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5194,7 +6280,11 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5213,7 +6303,11 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5232,7 +6326,11 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5251,7 +6349,11 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5270,7 +6372,11 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5289,7 +6395,11 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5308,7 +6418,11 @@ VCmpTruF16Vop3::VCmpTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5331,7 +6445,11 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5354,7 +6472,11 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5377,7 +6499,11 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5400,7 +6526,11 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5423,7 +6553,11 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5446,7 +6580,11 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5469,7 +6607,11 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5492,7 +6634,11 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5515,7 +6661,11 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5538,7 +6688,12 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5561,7 +6716,12 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5584,7 +6744,12 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5607,7 +6772,12 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5630,7 +6800,12 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5653,7 +6828,12 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5676,7 +6856,12 @@ VCmpxTruF16Vop3::VCmpxTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5695,7 +6880,11 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5714,7 +6903,11 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5733,7 +6926,11 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5752,7 +6949,11 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5771,7 +6972,11 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5790,7 +6995,11 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5809,7 +7018,11 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5828,7 +7041,11 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5847,7 +7064,11 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5866,7 +7087,11 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5885,7 +7110,11 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5904,7 +7133,11 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5923,7 +7156,11 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5942,7 +7179,11 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5961,7 +7202,11 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5980,7 +7225,11 @@ VCmpTruF32Vop3::VCmpTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6003,7 +7252,11 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6026,7 +7279,11 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6049,7 +7306,11 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6072,7 +7333,11 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6095,7 +7360,11 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6118,7 +7387,11 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6141,7 +7414,11 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6164,7 +7441,11 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6187,7 +7468,11 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6210,7 +7495,12 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6233,7 +7523,12 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6256,7 +7551,12 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6279,7 +7579,12 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6302,7 +7607,12 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6325,7 +7635,12 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6348,7 +7663,12 @@ VCmpxTruF32Vop3::VCmpxTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6367,7 +7687,11 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6386,7 +7710,11 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6405,7 +7733,11 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6424,7 +7756,11 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6443,7 +7779,11 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6462,7 +7802,11 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6481,7 +7825,11 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6500,7 +7848,11 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6519,7 +7871,11 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6538,7 +7894,11 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6557,7 +7917,11 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6576,7 +7940,11 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6595,7 +7963,11 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6614,7 +7986,11 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6633,7 +8009,11 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6652,7 +8032,11 @@ VCmpTruF64Vop3::VCmpTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6675,7 +8059,11 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6698,7 +8086,11 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6721,7 +8113,11 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6744,7 +8140,11 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6767,7 +8167,11 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6790,7 +8194,11 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6813,7 +8221,11 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6836,7 +8248,11 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6859,7 +8275,11 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6882,7 +8302,12 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6905,7 +8330,12 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6928,7 +8358,12 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6951,7 +8386,12 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6974,7 +8414,12 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6997,7 +8442,12 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7020,7 +8470,12 @@ VCmpxTruF64Vop3::VCmpxTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7039,7 +8494,11 @@ VCmpFI16Vop3::VCmpFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7058,7 +8517,11 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7077,7 +8540,11 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7096,7 +8563,11 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7115,7 +8586,11 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7134,7 +8609,11 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7153,7 +8632,11 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7172,7 +8655,11 @@ VCmpTI16Vop3::VCmpTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7191,7 +8678,11 @@ VCmpFU16Vop3::VCmpFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7210,7 +8701,11 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7229,7 +8724,11 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7248,7 +8747,11 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7267,7 +8770,11 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7286,7 +8793,11 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7305,7 +8816,11 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7324,7 +8839,11 @@ VCmpTU16Vop3::VCmpTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7347,7 +8866,11 @@ VCmpxFI16Vop3::VCmpxFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7370,7 +8893,11 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7393,7 +8920,11 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7416,7 +8947,11 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7439,7 +8974,11 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7462,7 +9001,11 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7485,7 +9028,11 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7508,7 +9055,11 @@ VCmpxTI16Vop3::VCmpxTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7531,7 +9082,11 @@ VCmpxFU16Vop3::VCmpxFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7554,7 +9109,11 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7577,7 +9136,11 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7600,7 +9163,11 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7623,7 +9190,11 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7646,7 +9217,11 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7669,7 +9244,11 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7692,7 +9271,11 @@ VCmpxTU16Vop3::VCmpxTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7711,7 +9294,11 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7730,7 +9317,11 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7749,7 +9340,11 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7768,7 +9363,11 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7787,7 +9386,11 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7806,7 +9409,11 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7825,7 +9432,11 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7844,7 +9455,11 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7863,7 +9478,11 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7882,7 +9501,11 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7901,7 +9524,11 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7920,7 +9547,11 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7939,7 +9570,11 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7958,7 +9593,11 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7977,7 +9616,11 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7996,7 +9639,11 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8019,7 +9666,11 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8042,7 +9693,11 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8065,7 +9720,11 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8088,7 +9747,11 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8111,7 +9774,11 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8134,7 +9801,11 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8157,7 +9828,11 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8180,7 +9855,11 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8203,7 +9882,11 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8226,7 +9909,11 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8249,7 +9936,11 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8272,7 +9963,11 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8295,7 +9990,11 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8318,7 +10017,11 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8341,7 +10044,11 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8364,7 +10071,11 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8383,7 +10094,11 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8402,7 +10117,11 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8421,7 +10140,11 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8440,7 +10163,11 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8459,7 +10186,11 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8478,7 +10209,11 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8497,7 +10232,11 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8516,7 +10255,11 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8535,7 +10278,11 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8554,7 +10301,11 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8573,7 +10324,11 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8592,7 +10347,11 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8611,7 +10370,11 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8630,7 +10393,11 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8649,7 +10416,11 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8668,7 +10439,11 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8691,7 +10466,11 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8714,7 +10493,11 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8737,7 +10520,11 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8760,7 +10547,11 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8783,7 +10574,11 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8806,7 +10601,11 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8829,7 +10628,11 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8852,7 +10655,11 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8875,7 +10682,11 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8898,7 +10709,11 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8921,7 +10736,11 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8944,7 +10763,11 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8967,7 +10790,11 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8990,7 +10817,11 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9013,7 +10844,11 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9036,7 +10871,11 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9057,7 +10896,12 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9078,7 +10922,12 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9099,7 +10948,12 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9122,7 +10976,12 @@ VAddcCoU32Vop3SdstEnc::VAddcCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_addc_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9145,7 +11004,12 @@ VSubbCoU32Vop3SdstEnc::VSubbCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subb_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9168,7 +11032,12 @@ VSubbrevCoU32Vop3SdstEnc::VSubbrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subbrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9191,7 +11060,12 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9214,7 +11088,12 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9237,7 +11116,12 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_u64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9260,7 +11144,12 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_i64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3p.cpp index bced5e9138c1..2f8793b355d8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,7 +40,11 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +69,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +99,11 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -110,7 +122,11 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +145,12 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +169,12 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -167,7 +193,12 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +217,11 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -211,7 +246,11 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +277,11 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,7 +306,11 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -282,7 +329,11 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -301,7 +352,11 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -326,7 +381,11 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +412,11 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -372,7 +435,11 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -391,7 +458,11 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -410,7 +481,11 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +510,11 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -462,7 +541,12 @@ VMadMixF32Vop3p::VMadMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mix_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -484,7 +568,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixlo_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +601,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixhi_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -539,7 +633,12 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +659,12 @@ VDot2I32I16Vop3p::VDot2I32I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -581,7 +685,12 @@ VDot2U32U16Vop3p::VDot2U32U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +711,12 @@ VDot4I32I8Vop3p::VDot4I32I8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +737,12 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -644,7 +763,12 @@ VDot8I32I4Vop3p::VDot8I32I4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -665,7 +789,12 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_u32_u4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -686,7 +815,11 @@ VPkFmaF32Vop3p::VPkFmaF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -705,7 +838,11 @@ VPkMulF32Vop3p::VPkMulF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -724,7 +861,11 @@ VPkAddF32Vop3p::VPkAddF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -743,7 +884,11 @@ VPkMovB32Vop3p::VPkMovB32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMovB32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMovB32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -764,7 +909,12 @@ VAccvgprReadVop3p::VAccvgprReadVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_read", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -782,7 +932,12 @@ VAccvgprWriteVop3p::VAccvgprWriteVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_write", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -820,7 +975,13 @@ VMfmaF3216x16x8Xf32Vop3pMfma::VMfmaF3216x16x8Xf32Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x8Xf32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x8Xf32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x8_xf32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +1019,13 @@ VMfmaF3232x32x4Xf32Vop3pMfma::VMfmaF3232x32x4Xf32Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x4Xf32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x4Xf32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4_xf32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -896,7 +1063,13 @@ VMfmaF3232x32x12bF32Vop3pMfma::VMfmaF3232x32x12bF32Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x1_2b_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1107,13 @@ VMfmaF3216x16x14bF32Vop3pMfma::VMfmaF3216x16x14bF32Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x1_4b_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -972,7 +1151,13 @@ VMfmaF324x4x116bF32Vop3pMfma::VMfmaF324x4x116bF32Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x1_16b_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1010,7 +1195,13 @@ VMfmaF3232x32x2F32Vop3pMfma::VMfmaF3232x32x2F32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x2_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1048,7 +1239,13 @@ VMfmaF3216x16x4F32Vop3pMfma::VMfmaF3216x16x4F32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1086,7 +1283,13 @@ VMfmaF3232x32x42bF16Vop3pMfma::VMfmaF3232x32x42bF16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4_2b_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1327,13 @@ VMfmaF3216x16x44bF16Vop3pMfma::VMfmaF3216x16x44bF16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4_4b_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1162,7 +1371,13 @@ VMfmaF324x4x416bF16Vop3pMfma::VMfmaF324x4x416bF16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4_16b_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1200,7 +1415,13 @@ VMfmaF3232x32x8F16Vop3pMfma::VMfmaF3232x32x8F16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1459,13 @@ VMfmaF3216x16x16F16Vop3pMfma::VMfmaF3216x16x16F16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1276,7 +1503,13 @@ VMfmaI3232x32x42bI8Vop3pMfma::VMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x4_2b_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1314,7 +1547,13 @@ VMfmaI3216x16x44bI8Vop3pMfma::VMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x4_4b_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1591,13 @@ VMfmaI324x4x416bI8Vop3pMfma::VMfmaI324x4x416bI8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_4x4x4_16b_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1390,7 +1635,13 @@ VMfmaI3232x32x16I8Vop3pMfma::VMfmaI3232x32x16I8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x16_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1428,7 +1679,13 @@ VMfmaI3216x16x32I8Vop3pMfma::VMfmaI3216x16x32I8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x32_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1723,13 @@ VMfmaF3232x32x42bBf16Vop3pMfma::VMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4_2b_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,7 +1767,13 @@ VMfmaF3216x16x44bBf16Vop3pMfma::VMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4_4b_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1542,7 +1811,13 @@ VMfmaF324x4x416bBf16Vop3pMfma::VMfmaF324x4x416bBf16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4_16b_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1580,7 +1855,13 @@ VMfmaF3232x32x8Bf16Vop3pMfma::VMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1618,7 +1899,13 @@ VMfmaF3216x16x16Bf16Vop3pMfma::VMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1655,7 +1942,13 @@ VSmfmacF3216x16x32F16Vop3pMfma::VSmfmacF3216x16x32F16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x32_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1692,7 +1985,13 @@ VSmfmacF3232x32x16F16Vop3pMfma::VSmfmacF3232x32x16F16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x16_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1729,7 +2028,13 @@ VSmfmacF3216x16x32Bf16Vop3pMfma::VSmfmacF3216x16x32Bf16Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x32_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1766,7 +2071,13 @@ VSmfmacF3232x32x16Bf16Vop3pMfma::VSmfmacF3232x32x16Bf16Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x16_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1803,7 +2114,13 @@ VSmfmacI3216x16x64I8Vop3pMfma::VSmfmacI3216x16x64I8Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_i32_16x16x64_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1840,7 +2157,13 @@ VSmfmacI3232x32x32I8Vop3pMfma::VSmfmacI3232x32x32I8Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_i32_32x32x32_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1878,7 +2201,13 @@ VMfmaF6416x16x4F64Vop3pMfma::VMfmaF6416x16x4F64Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f64_16x16x4_f64", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1916,7 +2245,13 @@ VMfmaF644x4x44bF64Vop3pMfma::VMfmaF644x4x44bF64Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f64_4x4x4_4b_f64", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1954,7 +2289,13 @@ VMfmaF3216x16x32Bf8Bf8Vop3pMfma::VMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1992,7 +2333,13 @@ VMfmaF3216x16x32Bf8Fp8Vop3pMfma::VMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2030,7 +2377,13 @@ VMfmaF3216x16x32Fp8Bf8Vop3pMfma::VMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2068,7 +2421,13 @@ VMfmaF3216x16x32Fp8Fp8Vop3pMfma::VMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2106,7 +2465,13 @@ VMfmaF3232x32x16Bf8Bf8Vop3pMfma::VMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2144,7 +2509,13 @@ VMfmaF3232x32x16Bf8Fp8Vop3pMfma::VMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2182,7 +2553,13 @@ VMfmaF3232x32x16Fp8Bf8Vop3pMfma::VMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2220,7 +2597,13 @@ VMfmaF3232x32x16Fp8Fp8Vop3pMfma::VMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2257,7 +2640,13 @@ VSmfmacF3216x16x64Bf8Bf8Vop3pMfma::VSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2294,7 +2683,13 @@ VSmfmacF3216x16x64Bf8Fp8Vop3pMfma::VSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2331,7 +2726,13 @@ VSmfmacF3216x16x64Fp8Bf8Vop3pMfma::VSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2368,7 +2769,13 @@ VSmfmacF3216x16x64Fp8Fp8Vop3pMfma::VSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2405,7 +2812,13 @@ VSmfmacF3232x32x32Bf8Bf8Vop3pMfma::VSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2442,7 +2855,13 @@ VSmfmacF3232x32x32Bf8Fp8Vop3pMfma::VSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2479,7 +2898,13 @@ VSmfmacF3232x32x32Fp8Bf8Vop3pMfma::VSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2516,7 +2941,13 @@ VSmfmacF3232x32x32Fp8Fp8Vop3pMfma::VSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp index 8d45e331e987..98aeb13cbf46 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,8 +30,6 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -60,7 +57,18 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -85,8 +93,6 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -116,7 +122,18 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,15 +154,21 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -168,17 +191,23 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -202,8 +231,6 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -231,7 +258,18 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -257,8 +295,6 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -288,7 +324,18 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -311,8 +358,6 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -340,7 +385,17 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -364,8 +419,6 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -393,7 +446,17 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -417,8 +480,6 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -446,7 +507,17 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -470,8 +541,6 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -499,7 +568,17 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -523,8 +602,6 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -552,7 +629,17 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -576,8 +663,6 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -605,7 +690,17 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -629,8 +724,6 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -658,7 +751,17 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -681,8 +784,6 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -710,7 +811,17 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -733,8 +844,6 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -762,7 +871,17 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -786,8 +905,6 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -815,7 +932,17 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -839,8 +966,6 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -868,7 +993,17 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -892,8 +1027,6 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -921,7 +1054,17 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -945,8 +1088,6 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -974,7 +1115,17 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -998,8 +1149,6 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1027,7 +1176,17 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1051,8 +1210,6 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1080,7 +1237,17 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1104,8 +1271,6 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1133,7 +1298,17 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1159,8 +1334,6 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1190,7 +1363,17 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1216,8 +1399,6 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1247,7 +1428,17 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1273,8 +1464,6 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1304,7 +1493,17 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1330,8 +1529,6 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1361,7 +1558,17 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1387,8 +1594,6 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1418,7 +1623,17 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1444,8 +1659,6 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1475,7 +1688,17 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1501,8 +1724,6 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1532,7 +1753,17 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1558,8 +1789,6 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1589,7 +1818,17 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1615,8 +1854,6 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1646,7 +1883,17 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1672,8 +1919,6 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1703,7 +1948,18 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1729,8 +1985,6 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1760,7 +2014,18 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1786,8 +2051,6 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1817,7 +2080,18 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1843,8 +2117,6 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1874,7 +2146,18 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1900,8 +2183,6 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1931,7 +2212,18 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1957,8 +2249,6 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1988,7 +2278,18 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2014,8 +2315,6 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2045,7 +2344,18 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2067,8 +2377,6 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2096,7 +2404,17 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2119,8 +2437,6 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2148,7 +2464,17 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2171,8 +2497,6 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2200,7 +2524,17 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2223,8 +2557,6 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2252,7 +2584,17 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2275,8 +2617,6 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2304,7 +2644,17 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2327,8 +2677,6 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2356,7 +2704,17 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2379,8 +2737,6 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2408,7 +2764,17 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2430,8 +2796,6 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2459,7 +2823,17 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2481,8 +2855,6 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2510,7 +2882,17 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2533,8 +2915,6 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2562,7 +2942,17 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2585,8 +2975,6 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2614,7 +3002,17 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2637,8 +3035,6 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2666,7 +3062,17 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2689,8 +3095,6 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2718,7 +3122,17 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2741,8 +3155,6 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2770,7 +3182,17 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2793,8 +3215,6 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2822,7 +3242,17 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2845,8 +3275,6 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2874,7 +3302,17 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2899,8 +3337,6 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2930,7 +3366,17 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2955,8 +3401,6 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2986,7 +3430,17 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3011,8 +3465,6 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3042,7 +3494,17 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3067,8 +3529,6 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3098,7 +3558,17 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3123,8 +3593,6 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3154,7 +3622,17 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3179,8 +3657,6 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3210,7 +3686,17 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3235,8 +3721,6 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3266,7 +3750,17 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3291,8 +3785,6 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3322,7 +3814,17 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3347,8 +3849,6 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3378,7 +3878,17 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3403,8 +3913,6 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3434,7 +3942,18 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3459,8 +3978,6 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3490,7 +4007,18 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3515,8 +4043,6 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3546,7 +4072,18 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3571,8 +4108,6 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3602,7 +4137,18 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3627,8 +4173,6 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3658,7 +4202,18 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3683,8 +4238,6 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3714,7 +4267,18 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3739,8 +4303,6 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3770,7 +4332,18 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3791,15 +4364,20 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3820,15 +4398,20 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3849,15 +4432,20 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3878,15 +4466,20 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3907,15 +4500,20 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3936,15 +4534,20 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3965,15 +4568,20 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3994,15 +4602,20 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4023,15 +4636,20 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4052,15 +4670,20 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4081,15 +4704,20 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4110,15 +4738,20 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4139,15 +4772,20 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4168,15 +4806,20 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4197,15 +4840,20 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4226,15 +4874,20 @@ VCmpTruF64Vopc::VCmpTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4257,17 +4910,22 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4290,17 +4948,22 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4323,17 +4986,22 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4356,17 +5024,22 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4389,17 +5062,22 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4422,17 +5100,22 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4455,17 +5138,22 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4488,17 +5176,22 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4521,17 +5214,22 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4554,17 +5252,23 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4587,17 +5291,23 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4620,17 +5330,23 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4653,17 +5369,23 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4686,17 +5408,23 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4719,17 +5447,23 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4752,17 +5486,23 @@ VCmpxTruF64Vopc::VCmpxTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4785,8 +5525,6 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4814,7 +5552,17 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4838,8 +5586,6 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4867,7 +5613,17 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4891,8 +5647,6 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4920,7 +5674,17 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4944,8 +5708,6 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4973,7 +5735,17 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4997,8 +5769,6 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5026,7 +5796,17 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5050,8 +5830,6 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5079,7 +5857,17 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5103,8 +5891,6 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5132,7 +5918,17 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5155,8 +5951,6 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5184,7 +5978,17 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5207,8 +6011,6 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5236,7 +6038,17 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5260,8 +6072,6 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5289,7 +6099,17 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5313,8 +6133,6 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5342,7 +6160,17 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5366,8 +6194,6 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5395,7 +6221,17 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5419,8 +6255,6 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5448,7 +6282,17 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5472,8 +6316,6 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5501,7 +6343,17 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5525,8 +6377,6 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5554,7 +6404,17 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5577,8 +6437,6 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5606,7 +6464,17 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5632,8 +6500,6 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5663,7 +6529,17 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5689,8 +6565,6 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5720,7 +6594,17 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5746,8 +6630,6 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5777,7 +6659,17 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5803,8 +6695,6 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5834,7 +6724,17 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5860,8 +6760,6 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5891,7 +6789,17 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5917,8 +6825,6 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5948,7 +6854,17 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5974,8 +6890,6 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6005,7 +6919,17 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6031,8 +6955,6 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6062,7 +6984,17 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6088,8 +7020,6 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6119,7 +7049,17 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6145,8 +7085,6 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6176,7 +7114,17 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6202,8 +7150,6 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6233,7 +7179,17 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6259,8 +7215,6 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6290,7 +7244,17 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6316,8 +7280,6 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6347,7 +7309,17 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6373,8 +7345,6 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6404,7 +7374,17 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6430,8 +7410,6 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6461,7 +7439,17 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6487,8 +7475,6 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6518,7 +7504,17 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6540,8 +7536,6 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6569,7 +7563,17 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6592,8 +7596,6 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6621,7 +7623,17 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6644,8 +7656,6 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6673,7 +7683,17 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6696,8 +7716,6 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6725,7 +7743,17 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6748,8 +7776,6 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6777,7 +7803,17 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6800,8 +7836,6 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6829,7 +7863,17 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6852,8 +7896,6 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6881,7 +7923,17 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6903,8 +7955,6 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6932,7 +7982,17 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6954,8 +8014,6 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6983,7 +8041,17 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7006,8 +8074,6 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7035,7 +8101,17 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7058,8 +8134,6 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7087,7 +8161,17 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7110,8 +8194,6 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7139,7 +8221,17 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7162,8 +8254,6 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7191,7 +8281,17 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7214,8 +8314,6 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7243,7 +8341,17 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7266,8 +8374,6 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7295,7 +8401,17 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7317,8 +8433,6 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7346,7 +8460,17 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7371,8 +8495,6 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7402,7 +8524,17 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7427,8 +8559,6 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7458,7 +8588,17 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7483,8 +8623,6 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7514,7 +8652,17 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7539,8 +8687,6 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7570,7 +8716,17 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7595,8 +8751,6 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7626,7 +8780,17 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7651,8 +8815,6 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7682,7 +8844,17 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7707,8 +8879,6 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7738,7 +8908,17 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7763,8 +8943,6 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7794,7 +8972,17 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7819,8 +9007,6 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7850,7 +9036,17 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7875,8 +9071,6 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7906,7 +9100,17 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7931,8 +9135,6 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7962,7 +9164,17 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7987,8 +9199,6 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8018,7 +9228,17 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8043,8 +9263,6 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8074,7 +9292,17 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8099,8 +9327,6 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8130,7 +9356,17 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8155,8 +9391,6 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8186,7 +9420,17 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8211,8 +9455,6 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8242,7 +9484,17 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8263,15 +9515,20 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8292,15 +9549,20 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8321,15 +9583,20 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8350,15 +9617,20 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8379,15 +9651,20 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8408,15 +9685,20 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8437,15 +9719,20 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8466,15 +9753,20 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8495,15 +9787,20 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8524,15 +9821,20 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8553,15 +9855,20 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8582,15 +9889,20 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8611,15 +9923,20 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8640,15 +9957,20 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8669,15 +9991,20 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8698,15 +10025,20 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8729,17 +10061,22 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8762,17 +10099,22 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8795,17 +10137,22 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8828,17 +10175,22 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8861,17 +10213,22 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8894,17 +10251,22 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8927,17 +10289,22 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8960,17 +10327,22 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8993,17 +10365,22 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9026,17 +10403,22 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9059,17 +10441,22 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9092,17 +10479,22 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9125,17 +10517,22 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9158,17 +10555,22 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9191,17 +10593,22 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9224,17 +10631,22 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp index c44920db6dd1..ba25d9089547 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.h" -#include "util/except.h" #include #include #include @@ -16,1524 +15,2067 @@ namespace rocjitsu { namespace cdna4 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddBf16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferInvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferWbl2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddBf16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddF16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnBf16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnF16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64TrB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64TrB4Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64TrB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96TrB6Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinF64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode); -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode); -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode); -std::unique_ptr decodeSSetValuCoexecModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrPkI8I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrPkU8I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBitop3B16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBitop3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef322xpk16Bf6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef322xpk16Fp6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32F16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32F16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32F32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32F32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32Bf16Bf6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32Bf16Fp6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32Bf6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32Bf6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32F16Bf6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32F16Fp6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32F32Bf6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32F32Fp6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32Fp6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk32Fp6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkBf16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkBf16Fp4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkBf16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkBf8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkBf8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkF16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkF16Fp4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkF16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkF32Fp4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkFp4Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkFp4F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkFp4F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkFp8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkFp8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32PkFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrBf8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrBf8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrFp8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrFp8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk32Bf6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk32Bf6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk32Bf6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk32Fp6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk32Fp6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk32Fp6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPkFp4F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPkFp4F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrBf16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32Bf16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpLegacyF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogLegacyF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximum3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x128F8f6f4Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x64F8f6f4Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3216x16x64I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x32I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimum3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16SwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16SwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane32SwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPermlane32SwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaximum3F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinimum3F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMovB32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPrngB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPrngB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x128Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x128Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x128Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x128Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Bf16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32F16Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x64Bf8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x64Bf8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x64Fp8Bf8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacF3232x32x64Fp8Fp8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacI3216x16x128I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSmfmacI3232x32x64I8Vop3pMfma(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddBf16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferInvMubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferWbl2Mubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddBf16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddF16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnBf16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnF16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64TrB16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64TrB4Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64TrB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96TrB6Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetValuCoexecModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprMovB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprMovB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrPkI8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrPkU8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBitop3B16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBitop3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef322xpk16Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef322xpk16Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32F16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32F16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32F32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32F32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32Bf16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32Bf16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32F16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32F16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32F32Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32F32Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk32Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkBf16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkBf16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkBf16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkBf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkF16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkF16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkF16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkF32Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkFp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkFp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkFp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkFp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32PkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrBf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrFp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk32Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk32Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk32Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk32Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk32Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk32Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPkFp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPkFp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32Bf16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpLegacyF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogLegacyF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x128F8f6f4Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x64F8f6f4Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3216x16x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16SwapB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16SwapB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane32SwapB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane32SwapB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaximum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinimum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMovB32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPrngB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPrngB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x128Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x128Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x128Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x128Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x64Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x64Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x64Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacF3232x32x64Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacI3216x16x128I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSmfmacI3232x32x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr decodeVop3pX2Prefix(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult decodeVop3pX2Prefix(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1549,90 +2091,103 @@ struct DecoderImpl { static const std::array sub_decode_mtbuf; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeVop3pX2Prefix(const MachineInst *opcode) { +DecodeResult DecoderImpl::decodeVop3pX2Prefix(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { const uint32_t suffix_encoding = (opcode[2] >> 23) & 0x1FFu; const uint32_t suffix_opcode = (opcode[2] >> 16) & 0x7Fu; if (suffix_encoding != encoding::kVop3pMfma || (suffix_opcode != kVMfmaF3216x16x128F8f6f4Vop3pMfma && suffix_opcode != kVMfmaF3232x32x64F8f6f4Vop3pMfma)) - return decodeInvalid(opcode); + return decodeInvalid(opcode, emit_error); if (suffix_opcode == kVMfmaF3216x16x128F8f6f4Vop3pMfma) return std::make_unique(opcode + 2, true); return std::make_unique(opcode + 2, true); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h index 5da96952c00e..8950b050d29c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA4_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace cdna4 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 4; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace cdna4 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds.cpp index 932e74b9d428..e1ed88906020 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/ds.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -36,7 +35,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +97,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -117,7 +128,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -144,7 +159,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -171,7 +190,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -198,7 +221,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -225,7 +252,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -252,7 +283,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -279,7 +314,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +345,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +376,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +413,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -391,7 +442,11 @@ DsWriteB32Ds::DsWriteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -422,7 +477,11 @@ DsWrite2B32Ds::DsWrite2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -453,7 +512,12 @@ DsWrite2st64B32Ds::DsWrite2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +550,11 @@ DsCmpstB32Ds::DsCmpstB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -519,7 +587,11 @@ DsCmpstF32Ds::DsCmpstF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -546,7 +618,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -573,7 +649,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +666,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +697,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,7 +728,11 @@ DsPkAddF16Ds::DsPkAddF16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddF16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddF16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -667,7 +759,11 @@ DsPkAddBf16Ds::DsPkAddBf16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddBf16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddBf16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -692,7 +788,12 @@ DsWriteAddtidB32Ds::DsWriteAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +818,11 @@ DsWriteB8Ds::DsWriteB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -742,7 +847,11 @@ DsWriteB16Ds::DsWriteB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -775,7 +884,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -808,7 +921,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +958,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -874,7 +995,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -907,7 +1032,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -940,7 +1069,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -973,7 +1106,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1006,7 +1143,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1039,7 +1180,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1217,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1105,7 +1254,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1291,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1177,7 +1334,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1210,7 +1372,12 @@ DsWrxchgRtnB32Ds::DsWrxchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1249,7 +1416,12 @@ DsWrxchg2RtnB32Ds::DsWrxchg2RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1288,7 +1460,12 @@ DsWrxchg2st64RtnB32Ds::DsWrxchg2st64RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1327,7 +1504,12 @@ DsCmpstRtnB32Ds::DsCmpstRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1366,7 +1548,12 @@ DsCmpstRtnF32Ds::DsCmpstRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1399,7 +1586,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1432,7 +1623,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1470,7 +1665,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,7 +1702,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1528,7 +1731,11 @@ DsReadB32Ds::DsReadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1553,7 +1760,11 @@ DsRead2B32Ds::DsRead2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1578,7 +1789,12 @@ DsRead2st64B32Ds::DsRead2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1603,7 +1819,11 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1628,7 +1848,11 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1653,7 +1877,11 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1678,7 +1906,11 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +1931,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1726,7 +1962,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1753,7 +1993,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1780,7 +2025,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1807,7 +2056,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1834,7 +2087,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1861,7 +2118,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1888,7 +2149,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1915,7 +2180,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1942,7 +2211,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1969,7 +2242,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1996,7 +2273,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2023,7 +2304,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2050,7 +2335,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2077,7 +2366,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2110,7 +2403,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2135,7 +2432,11 @@ DsWriteB64Ds::DsWriteB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2166,7 +2467,11 @@ DsWrite2B64Ds::DsWrite2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2197,7 +2502,12 @@ DsWrite2st64B64Ds::DsWrite2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2230,7 +2540,11 @@ DsCmpstB64Ds::DsCmpstB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2263,7 +2577,11 @@ DsCmpstF64Ds::DsCmpstF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2290,7 +2608,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2317,7 +2639,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2342,7 +2668,12 @@ DsWriteB8D16HiDs::DsWriteB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2367,7 +2698,12 @@ DsWriteB16D16HiDs::DsWriteB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2392,7 +2728,11 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2423,7 +2763,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2454,7 +2799,11 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2485,7 +2834,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2516,7 +2870,11 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2547,7 +2905,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2580,7 +2943,11 @@ DsAddF64Ds::DsAddF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2613,7 +2980,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2646,7 +3017,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2679,7 +3054,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2712,7 +3091,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2745,7 +3128,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2778,7 +3165,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2811,7 +3202,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2844,7 +3239,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2877,7 +3276,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2910,7 +3313,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2943,7 +3350,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2976,7 +3387,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3015,7 +3430,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3048,7 +3468,12 @@ DsWrxchgRtnB64Ds::DsWrxchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3087,7 +3512,12 @@ DsWrxchg2RtnB64Ds::DsWrxchg2RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3126,7 +3556,12 @@ DsWrxchg2st64RtnB64Ds::DsWrxchg2st64RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3165,7 +3600,12 @@ DsCmpstRtnB64Ds::DsCmpstRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3204,7 +3644,12 @@ DsCmpstRtnF64Ds::DsCmpstRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3237,7 +3682,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3270,7 +3719,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3295,7 +3748,11 @@ DsReadB64Ds::DsReadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3320,7 +3777,11 @@ DsRead2B64Ds::DsRead2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3345,7 +3806,12 @@ DsRead2st64B64Ds::DsRead2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3378,7 +3844,11 @@ DsAddRtnF64Ds::DsAddRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3411,7 +3881,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3436,7 +3911,12 @@ DsReadAddtidB32Ds::DsReadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3469,7 +3949,12 @@ DsPkAddRtnF16Ds::DsPkAddRtnF16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnF16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnF16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_rtn_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3502,7 +3987,12 @@ DsPkAddRtnBf16Ds::DsPkAddRtnBf16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnBf16Ds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnBf16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_pk_add_rtn_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3527,7 +4017,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3552,7 +4046,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3577,7 +4075,11 @@ DsWriteB96Ds::DsWriteB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3602,7 +4104,11 @@ DsWriteB128Ds::DsWriteB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3627,7 +4133,12 @@ DsReadB64TrB4Ds::DsReadB64TrB4Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64TrB4Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64TrB4Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64_tr_b4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3652,7 +4163,12 @@ DsReadB96TrB6Ds::DsReadB96TrB6Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96TrB6Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96TrB6Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96_tr_b6", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3677,7 +4193,12 @@ DsReadB64TrB8Ds::DsReadB64TrB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64TrB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64TrB8Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64_tr_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3702,7 +4223,12 @@ DsReadB64TrB16Ds::DsReadB64TrB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64TrB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64TrB16Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64_tr_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3727,7 +4253,11 @@ DsReadB96Ds::DsReadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3752,7 +4282,11 @@ DsReadB128Ds::DsReadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h index cd2f07fd9483..86496d5606fe 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna4/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/flat.cpp index 5831909337e8..36ecc7d3056c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/flat.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -50,7 +49,12 @@ FlatLoadUbyteFlat::FlatLoadUbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +95,12 @@ FlatLoadSbyteFlat::FlatLoadSbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -132,7 +141,12 @@ FlatLoadUshortFlat::FlatLoadUshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -173,7 +187,12 @@ FlatLoadSshortFlat::FlatLoadSshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +233,12 @@ FlatLoadDwordFlat::FlatLoadDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -255,7 +279,12 @@ FlatLoadDwordx2Flat::FlatLoadDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +325,12 @@ FlatLoadDwordx3Flat::FlatLoadDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +371,12 @@ FlatLoadDwordx4Flat::FlatLoadDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -378,7 +417,12 @@ FlatStoreByteFlat::FlatStoreByteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -419,7 +463,12 @@ FlatStoreByteD16HiFlat::FlatStoreByteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -460,7 +509,12 @@ FlatStoreShortFlat::FlatStoreShortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +555,12 @@ FlatStoreShortD16HiFlat::FlatStoreShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -542,7 +601,12 @@ FlatStoreDwordFlat::FlatStoreDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -583,7 +647,12 @@ FlatStoreDwordx2Flat::FlatStoreDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -624,7 +693,12 @@ FlatStoreDwordx3Flat::FlatStoreDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -665,7 +739,12 @@ FlatStoreDwordx4Flat::FlatStoreDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -706,7 +785,12 @@ FlatLoadUbyteD16Flat::FlatLoadUbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -754,7 +838,12 @@ FlatLoadUbyteD16HiFlat::FlatLoadUbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -802,7 +891,12 @@ FlatLoadSbyteD16Flat::FlatLoadSbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -850,7 +944,12 @@ FlatLoadSbyteD16HiFlat::FlatLoadSbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -898,7 +997,12 @@ FlatLoadShortD16Flat::FlatLoadShortD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -946,7 +1050,12 @@ FlatLoadShortD16HiFlat::FlatLoadShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1004,7 +1113,12 @@ FlatAtomicSwapFlat::FlatAtomicSwapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1055,7 +1169,12 @@ FlatAtomicCmpswapFlat::FlatAtomicCmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1106,7 +1225,12 @@ FlatAtomicAddFlat::FlatAtomicAddFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1157,7 +1281,12 @@ FlatAtomicSubFlat::FlatAtomicSubFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1337,12 @@ FlatAtomicSminFlat::FlatAtomicSminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1393,12 @@ FlatAtomicUminFlat::FlatAtomicUminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1310,7 +1449,12 @@ FlatAtomicSmaxFlat::FlatAtomicSmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1361,7 +1505,12 @@ FlatAtomicUmaxFlat::FlatAtomicUmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1412,7 +1561,12 @@ FlatAtomicAndFlat::FlatAtomicAndFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1463,7 +1617,12 @@ FlatAtomicOrFlat::FlatAtomicOrFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1514,7 +1673,12 @@ FlatAtomicXorFlat::FlatAtomicXorFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1565,7 +1729,12 @@ FlatAtomicIncFlat::FlatAtomicIncFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1616,7 +1785,12 @@ FlatAtomicDecFlat::FlatAtomicDecFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1667,7 +1841,12 @@ FlatAtomicAddF32Flat::FlatAtomicAddF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1718,7 +1897,12 @@ FlatAtomicPkAddF16Flat::FlatAtomicPkAddF16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddF16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1769,7 +1953,12 @@ FlatAtomicAddF64Flat::FlatAtomicAddF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1820,7 +2009,12 @@ FlatAtomicMinF64Flat::FlatAtomicMinF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1871,7 +2065,12 @@ FlatAtomicMaxF64Flat::FlatAtomicMaxF64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxF64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxF64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1922,7 +2121,12 @@ FlatAtomicPkAddBf16Flat::FlatAtomicPkAddBf16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddBf16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1973,7 +2177,12 @@ FlatAtomicSwapX2Flat::FlatAtomicSwapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2024,7 +2233,12 @@ FlatAtomicCmpswapX2Flat::FlatAtomicCmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2075,7 +2289,12 @@ FlatAtomicAddX2Flat::FlatAtomicAddX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2126,7 +2345,12 @@ FlatAtomicSubX2Flat::FlatAtomicSubX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2177,7 +2401,12 @@ FlatAtomicSminX2Flat::FlatAtomicSminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2228,7 +2457,12 @@ FlatAtomicUminX2Flat::FlatAtomicUminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2279,7 +2513,12 @@ FlatAtomicSmaxX2Flat::FlatAtomicSmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2330,7 +2569,12 @@ FlatAtomicUmaxX2Flat::FlatAtomicUmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2381,7 +2625,12 @@ FlatAtomicAndX2Flat::FlatAtomicAndX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2432,7 +2681,12 @@ FlatAtomicOrX2Flat::FlatAtomicOrX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2483,7 +2737,12 @@ FlatAtomicXorX2Flat::FlatAtomicXorX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2534,7 +2793,12 @@ FlatAtomicIncX2Flat::FlatAtomicIncX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2585,7 +2849,12 @@ FlatAtomicDecX2Flat::FlatAtomicDecX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mtbuf.cpp index 3d01bff8ea32..1324e171ea29 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mtbuf.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -49,7 +48,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -79,7 +83,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -109,7 +118,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +153,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +188,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -199,7 +223,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -229,7 +258,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +293,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +328,12 @@ TbufferLoadFormatD16XMtbuf::TbufferLoadFormatD16XMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +369,13 @@ TbufferLoadFormatD16XyMtbuf::TbufferLoadFormatD16XyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -355,7 +405,13 @@ TbufferLoadFormatD16XyzMtbuf::TbufferLoadFormatD16XyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -391,7 +447,13 @@ TbufferLoadFormatD16XyzwMtbuf::TbufferLoadFormatD16XyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +483,13 @@ TbufferStoreFormatD16XMtbuf::TbufferStoreFormatD16XMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +519,13 @@ TbufferStoreFormatD16XyMtbuf::TbufferStoreFormatD16XyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +555,13 @@ TbufferStoreFormatD16XyzMtbuf::TbufferStoreFormatD16XyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -511,7 +591,13 @@ TbufferStoreFormatD16XyzwMtbuf::TbufferStoreFormatD16XyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf.cpp index eebf9ab75b34..537b81a12195 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/mubuf.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -49,7 +48,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -79,7 +83,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -109,7 +118,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +153,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +188,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -199,7 +223,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -229,7 +258,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +293,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +328,12 @@ BufferLoadFormatD16XMubuf::BufferLoadFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -326,7 +370,12 @@ BufferLoadFormatD16XyMubuf::BufferLoadFormatD16XyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +405,13 @@ BufferLoadFormatD16XyzMubuf::BufferLoadFormatD16XyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -393,7 +448,13 @@ BufferLoadFormatD16XyzwMubuf::BufferLoadFormatD16XyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -423,7 +484,12 @@ BufferStoreFormatD16XMubuf::BufferStoreFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -453,7 +519,13 @@ BufferStoreFormatD16XyMubuf::BufferStoreFormatD16XyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -483,7 +555,13 @@ BufferStoreFormatD16XyzMubuf::BufferStoreFormatD16XyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -513,7 +591,13 @@ BufferStoreFormatD16XyzwMubuf::BufferStoreFormatD16XyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,7 +627,12 @@ BufferLoadUbyteMubuf::BufferLoadUbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -573,7 +662,12 @@ BufferLoadSbyteMubuf::BufferLoadSbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -603,7 +697,12 @@ BufferLoadUshortMubuf::BufferLoadUshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -633,7 +732,12 @@ BufferLoadSshortMubuf::BufferLoadSshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -663,7 +767,12 @@ BufferLoadDwordMubuf::BufferLoadDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -693,7 +802,12 @@ BufferLoadDwordx2Mubuf::BufferLoadDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -723,7 +837,12 @@ BufferLoadDwordx3Mubuf::BufferLoadDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -753,7 +872,12 @@ BufferLoadDwordx4Mubuf::BufferLoadDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -783,7 +907,12 @@ BufferStoreByteMubuf::BufferStoreByteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -813,7 +942,12 @@ BufferStoreByteD16HiMubuf::BufferStoreByteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -843,7 +977,12 @@ BufferStoreShortMubuf::BufferStoreShortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +1012,12 @@ BufferStoreShortD16HiMubuf::BufferStoreShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1047,12 @@ BufferStoreDwordMubuf::BufferStoreDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -933,7 +1082,12 @@ BufferStoreDwordx2Mubuf::BufferStoreDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -963,7 +1117,12 @@ BufferStoreDwordx3Mubuf::BufferStoreDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -993,7 +1152,12 @@ BufferStoreDwordx4Mubuf::BufferStoreDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1023,7 +1187,12 @@ BufferLoadUbyteD16Mubuf::BufferLoadUbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1060,7 +1229,12 @@ BufferLoadUbyteD16HiMubuf::BufferLoadUbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1271,12 @@ BufferLoadSbyteD16Mubuf::BufferLoadSbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1134,7 +1313,12 @@ BufferLoadSbyteD16HiMubuf::BufferLoadSbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1171,7 +1355,12 @@ BufferLoadShortD16Mubuf::BufferLoadShortD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1397,12 @@ BufferLoadShortD16HiMubuf::BufferLoadShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1245,7 +1439,13 @@ BufferLoadFormatD16HiXMubuf::BufferLoadFormatD16HiXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1282,7 +1482,13 @@ BufferStoreFormatD16HiXMubuf::BufferStoreFormatD16HiXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1295,7 +1501,12 @@ BufferWbl2Mubuf::BufferWbl2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferWbl2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferWbl2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_wbl2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1308,7 +1519,11 @@ BufferInvMubuf::BufferInvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferInvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferInvMubuf(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1342,7 +1557,12 @@ BufferAtomicSwapMubuf::BufferAtomicSwapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1381,7 +1601,12 @@ BufferAtomicCmpswapMubuf::BufferAtomicCmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1415,7 +1640,12 @@ BufferAtomicAddMubuf::BufferAtomicAddMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1449,7 +1679,12 @@ BufferAtomicSubMubuf::BufferAtomicSubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1483,7 +1718,12 @@ BufferAtomicSminMubuf::BufferAtomicSminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1517,7 +1757,12 @@ BufferAtomicUminMubuf::BufferAtomicUminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1551,7 +1796,12 @@ BufferAtomicSmaxMubuf::BufferAtomicSmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1585,7 +1835,12 @@ BufferAtomicUmaxMubuf::BufferAtomicUmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1619,7 +1874,12 @@ BufferAtomicAndMubuf::BufferAtomicAndMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1653,7 +1913,12 @@ BufferAtomicOrMubuf::BufferAtomicOrMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1687,7 +1952,12 @@ BufferAtomicXorMubuf::BufferAtomicXorMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1721,7 +1991,12 @@ BufferAtomicIncMubuf::BufferAtomicIncMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2030,12 @@ BufferAtomicDecMubuf::BufferAtomicDecMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1789,7 +2069,12 @@ BufferAtomicAddF32Mubuf::BufferAtomicAddF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1823,7 +2108,12 @@ BufferAtomicPkAddF16Mubuf::BufferAtomicPkAddF16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddF16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1857,7 +2147,12 @@ BufferAtomicAddF64Mubuf::BufferAtomicAddF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1891,7 +2186,12 @@ BufferAtomicMinF64Mubuf::BufferAtomicMinF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1925,7 +2225,12 @@ BufferAtomicMaxF64Mubuf::BufferAtomicMaxF64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxF64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1959,7 +2264,12 @@ BufferAtomicPkAddBf16Mubuf::BufferAtomicPkAddBf16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddBf16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddBf16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1993,7 +2303,12 @@ BufferAtomicSwapX2Mubuf::BufferAtomicSwapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2347,12 @@ BufferAtomicCmpswapX2Mubuf::BufferAtomicCmpswapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2066,7 +2386,12 @@ BufferAtomicAddX2Mubuf::BufferAtomicAddX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2100,7 +2425,12 @@ BufferAtomicSubX2Mubuf::BufferAtomicSubX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2134,7 +2464,12 @@ BufferAtomicSminX2Mubuf::BufferAtomicSminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2168,7 +2503,12 @@ BufferAtomicUminX2Mubuf::BufferAtomicUminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2202,7 +2542,12 @@ BufferAtomicSmaxX2Mubuf::BufferAtomicSmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2236,7 +2581,12 @@ BufferAtomicUmaxX2Mubuf::BufferAtomicUmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2270,7 +2620,12 @@ BufferAtomicAndX2Mubuf::BufferAtomicAndX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2304,7 +2659,12 @@ BufferAtomicOrX2Mubuf::BufferAtomicOrX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2338,7 +2698,12 @@ BufferAtomicXorX2Mubuf::BufferAtomicXorX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2372,7 +2737,12 @@ BufferAtomicIncX2Mubuf::BufferAtomicIncX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2406,7 +2776,12 @@ BufferAtomicDecX2Mubuf::BufferAtomicDecX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp index 66ab86206f6d..3ca0381cdcde 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem.cpp index 51aa900a3972..8c55f3261b6e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem.cpp @@ -8,7 +8,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx940_cache_flags.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx9_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -47,7 +46,11 @@ SLoadDwordSmem::SLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -70,7 +73,12 @@ SLoadDwordx2Smem::SLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -93,7 +101,12 @@ SLoadDwordx4Smem::SLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +129,12 @@ SLoadDwordx8Smem::SLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +157,12 @@ SLoadDwordx16Smem::SLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +185,12 @@ SScratchLoadDwordSmem::SScratchLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -185,7 +213,12 @@ SScratchLoadDwordx2Smem::SScratchLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -208,7 +241,12 @@ SScratchLoadDwordx4Smem::SScratchLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +269,12 @@ SBufferLoadDwordSmem::SBufferLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -254,7 +297,12 @@ SBufferLoadDwordx2Smem::SBufferLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -277,7 +325,12 @@ SBufferLoadDwordx4Smem::SBufferLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +353,12 @@ SBufferLoadDwordx8Smem::SBufferLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +381,12 @@ SBufferLoadDwordx16Smem::SBufferLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -346,7 +409,12 @@ SStoreDwordSmem::SStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -369,7 +437,12 @@ SStoreDwordx2Smem::SStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -392,7 +465,12 @@ SStoreDwordx4Smem::SStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -415,7 +493,12 @@ SScratchStoreDwordSmem::SScratchStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -438,7 +521,12 @@ SScratchStoreDwordx2Smem::SScratchStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -461,7 +549,12 @@ SScratchStoreDwordx4Smem::SScratchStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -484,7 +577,12 @@ SBufferStoreDwordSmem::SBufferStoreDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -507,7 +605,12 @@ SBufferStoreDwordx2Smem::SBufferStoreDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -530,7 +633,12 @@ SBufferStoreDwordx4Smem::SBufferStoreDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferStoreDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferStoreDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,7 +651,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -556,7 +668,11 @@ SDcacheWbSmem::SDcacheWbSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -569,7 +685,12 @@ SDcacheInvVolSmem::SDcacheInvVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +703,12 @@ SDcacheWbVolSmem::SDcacheWbVolSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheWbVolSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheWbVolSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_wb_vol", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -597,7 +723,11 @@ SMemtimeSmem::SMemtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -612,7 +742,12 @@ SMemrealtimeSmem::SMemrealtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memrealtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -631,7 +766,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +789,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -667,7 +811,12 @@ SDcacheDiscardSmem::SDcacheDiscardSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +833,12 @@ SDcacheDiscardX2Smem::SDcacheDiscardX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheDiscardX2Smem(const MachineInst *opcode) { +DecodeResult decodeSDcacheDiscardX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_discard_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +858,12 @@ SBufferAtomicSwapSmem::SBufferAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -724,7 +883,12 @@ SBufferAtomicCmpswapSmem::SBufferAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -744,7 +908,12 @@ SBufferAtomicAddSmem::SBufferAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -764,7 +933,12 @@ SBufferAtomicSubSmem::SBufferAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -784,7 +958,12 @@ SBufferAtomicSminSmem::SBufferAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +983,12 @@ SBufferAtomicUminSmem::SBufferAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -824,7 +1008,12 @@ SBufferAtomicSmaxSmem::SBufferAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -844,7 +1033,12 @@ SBufferAtomicUmaxSmem::SBufferAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +1058,12 @@ SBufferAtomicAndSmem::SBufferAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -884,7 +1083,12 @@ SBufferAtomicOrSmem::SBufferAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -904,7 +1108,12 @@ SBufferAtomicXorSmem::SBufferAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1133,12 @@ SBufferAtomicIncSmem::SBufferAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -944,7 +1158,12 @@ SBufferAtomicDecSmem::SBufferAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1183,12 @@ SBufferAtomicSwapX2Smem::SBufferAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -984,7 +1208,12 @@ SBufferAtomicCmpswapX2Smem::SBufferAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1004,7 +1233,12 @@ SBufferAtomicAddX2Smem::SBufferAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1024,7 +1258,12 @@ SBufferAtomicSubX2Smem::SBufferAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1044,7 +1283,12 @@ SBufferAtomicSminX2Smem::SBufferAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1064,7 +1308,12 @@ SBufferAtomicUminX2Smem::SBufferAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1084,7 +1333,12 @@ SBufferAtomicSmaxX2Smem::SBufferAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1104,7 +1358,12 @@ SBufferAtomicUmaxX2Smem::SBufferAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1383,12 @@ SBufferAtomicAndX2Smem::SBufferAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1408,12 @@ SBufferAtomicOrX2Smem::SBufferAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1164,7 +1433,12 @@ SBufferAtomicXorX2Smem::SBufferAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1184,7 +1458,12 @@ SBufferAtomicIncX2Smem::SBufferAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1204,7 +1483,12 @@ SBufferAtomicDecX2Smem::SBufferAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1224,7 +1508,12 @@ SAtomicSwapSmem::SAtomicSwapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1244,7 +1533,12 @@ SAtomicCmpswapSmem::SAtomicCmpswapSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1264,7 +1558,11 @@ SAtomicAddSmem::SAtomicAddSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1284,7 +1582,11 @@ SAtomicSubSmem::SAtomicSubSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1304,7 +1606,12 @@ SAtomicSminSmem::SAtomicSminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1324,7 +1631,12 @@ SAtomicUminSmem::SAtomicUminSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1344,7 +1656,12 @@ SAtomicSmaxSmem::SAtomicSmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1364,7 +1681,12 @@ SAtomicUmaxSmem::SAtomicUmaxSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1384,7 +1706,11 @@ SAtomicAndSmem::SAtomicAndSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1404,7 +1730,11 @@ SAtomicOrSmem::SAtomicOrSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1424,7 +1754,11 @@ SAtomicXorSmem::SAtomicXorSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1444,7 +1778,11 @@ SAtomicIncSmem::SAtomicIncSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1464,7 +1802,11 @@ SAtomicDecSmem::SAtomicDecSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecSmem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1484,7 +1826,12 @@ SAtomicSwapX2Smem::SAtomicSwapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSwapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSwapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,7 +1851,12 @@ SAtomicCmpswapX2Smem::SAtomicCmpswapX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicCmpswapX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicCmpswapX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1524,7 +1876,12 @@ SAtomicAddX2Smem::SAtomicAddX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAddX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAddX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1544,7 +1901,12 @@ SAtomicSubX2Smem::SAtomicSubX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSubX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSubX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1564,7 +1926,12 @@ SAtomicSminX2Smem::SAtomicSminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1951,12 @@ SAtomicUminX2Smem::SAtomicUminX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUminX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUminX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1976,12 @@ SAtomicSmaxX2Smem::SAtomicSmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicSmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicSmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1624,7 +2001,12 @@ SAtomicUmaxX2Smem::SAtomicUmaxX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicUmaxX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicUmaxX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +2026,12 @@ SAtomicAndX2Smem::SAtomicAndX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicAndX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicAndX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1664,7 +2051,12 @@ SAtomicOrX2Smem::SAtomicOrX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicOrX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicOrX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1684,7 +2076,12 @@ SAtomicXorX2Smem::SAtomicXorX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicXorX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicXorX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1704,7 +2101,12 @@ SAtomicIncX2Smem::SAtomicIncX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicIncX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicIncX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1724,7 +2126,12 @@ SAtomicDecX2Smem::SAtomicDecX2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtomicDecX2Smem(const MachineInst *opcode) { +DecodeResult decodeSAtomicDecX2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1.cpp index 0f17152b6827..46d812d58768 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +173,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +201,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +230,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +255,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +281,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -295,7 +339,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -319,7 +368,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +398,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +424,11 @@ SFf0I32B32Sop1::SFf0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +450,11 @@ SFf0I32B64Sop1::SFf0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +475,11 @@ SFf1I32B32Sop1::SFf1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +501,11 @@ SFf1I32B64Sop1::SFf1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +526,12 @@ SFlbitI32B32Sop1::SFlbitI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +553,12 @@ SFlbitI32B64Sop1::SFlbitI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +579,11 @@ SFlbitI32Sop1::SFlbitI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +605,12 @@ SFlbitI32I64Sop1::SFlbitI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +631,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -559,7 +657,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -581,7 +684,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -603,7 +711,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +738,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -647,7 +765,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -665,7 +788,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +811,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +838,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -725,7 +860,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -757,7 +896,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -790,7 +934,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -822,7 +971,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -854,7 +1008,12 @@ SAndn2SaveexecB64Sop1::SAndn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -886,7 +1045,12 @@ SOrn2SaveexecB64Sop1::SOrn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -918,7 +1082,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -950,7 +1119,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -982,7 +1156,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1006,7 +1185,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1031,7 +1215,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1051,7 +1240,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1071,7 +1265,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1095,7 +1294,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1120,7 +1324,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1140,7 +1349,12 @@ SCbranchJoinSop1::SCbranchJoinSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchJoinSop1(const MachineInst *opcode) { +DecodeResult decodeSCbranchJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cbranch_join", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1164,7 +1378,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1188,7 +1406,12 @@ SSetGprIdxIdxSop1::SSetGprIdxIdxSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxIdxSop1(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxIdxSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_set_gpr_idx_idx", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1220,7 +1443,12 @@ SAndn1SaveexecB64Sop1::SAndn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1252,7 +1480,12 @@ SOrn1SaveexecB64Sop1::SOrn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1284,7 +1517,12 @@ SAndn1WrexecB64Sop1::SAndn1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1316,7 +1554,12 @@ SAndn2WrexecB64Sop1::SAndn2WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1337,7 +1580,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop2.cpp index 9394c82a9485..ac67272fd80d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +280,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +314,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +348,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +382,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +454,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +490,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +525,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +562,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +596,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +632,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +666,11 @@ SAndn2B32Sop2::SAndn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +702,11 @@ SAndn2B64Sop2::SAndn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +736,11 @@ SOrn2B32Sop2::SOrn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +772,11 @@ SOrn2B64Sop2::SOrn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +806,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +842,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -779,7 +876,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -811,7 +912,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +946,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +982,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1016,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1051,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1085,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1120,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1154,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1189,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1220,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1251,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1282,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1316,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1350,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1385,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1420,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1444,12 @@ SCbranchGForkSop2::SCbranchGForkSop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchGForkSop2(const MachineInst *opcode) { +DecodeResult decodeSCbranchGForkSop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cbranch_g_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1479,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1338,7 +1513,12 @@ SRfeRestoreB64Sop2::SRfeRestoreB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeRestoreB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSRfeRestoreB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_rfe_restore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1365,7 +1545,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1392,7 +1576,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,7 +1610,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1645,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1680,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1715,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1749,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1569,7 +1782,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1596,7 +1814,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp index 9233c83e4ee3..21619b28e47d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -482,7 +549,11 @@ SSetvskipSopc::SSetvskipSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetvskipSopc(const MachineInst *opcode) { +DecodeResult decodeSSetvskipSopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_setvskip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +579,12 @@ SSetGprIdxOnSopc::SSetGprIdxOnSopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOnSopc(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOnSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_set_gpr_idx_on", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +614,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +648,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopk.cpp index 1863d66ce42a..e96791a9f0f6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -46,7 +49,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +73,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,7 +97,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +121,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +145,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +169,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +193,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +217,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -206,7 +241,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -226,7 +265,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +289,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +313,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -286,7 +337,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +362,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +384,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +405,12 @@ SCbranchIForkSopk::SCbranchIForkSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchIForkSopk(const MachineInst *opcode) { +DecodeResult decodeSCbranchIForkSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cbranch_i_fork", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +427,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +448,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +477,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +511,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopp.cpp index e6b50602c8ff..4ee3c46e58ee 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -36,7 +39,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +60,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +82,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +106,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +136,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +166,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +196,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +226,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +256,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +280,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +299,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +338,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +357,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +376,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +398,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,7 +420,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -362,7 +440,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +457,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +476,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +496,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +517,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +537,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +577,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +597,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +616,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +634,12 @@ SSetGprIdxOffSopp::SSetGprIdxOffSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxOffSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxOffSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_off", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -528,7 +659,12 @@ SSetGprIdxModeSopp::SSetGprIdxModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetGprIdxModeSopp(const MachineInst *opcode) { +DecodeResult decodeSSetGprIdxModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_gpr_idx_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -542,7 +678,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +698,12 @@ SSetValuCoexecModeSopp::SSetValuCoexecModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetValuCoexecModeSopp(const MachineInst *opcode) { +DecodeResult decodeSSetValuCoexecModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_valu_coexec_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp index 21020572e4f2..cadb59644b1d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,14 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_nop_sdwa" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +78,14 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -86,14 +99,20 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_readfirstlane_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -120,12 +139,17 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -151,12 +175,17 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_i32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -206,7 +235,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +293,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +351,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +409,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -406,7 +467,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +532,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -513,7 +590,16 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +649,16 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +708,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,12 +744,17 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -663,14 +772,19 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -720,7 +834,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +893,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -820,7 +952,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -870,7 +1011,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -897,12 +1047,17 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_U32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_u32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -928,12 +1083,17 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_U32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_cvt_f64_u32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -960,12 +1120,17 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_TRUNC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_trunc_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -992,12 +1157,17 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CEIL_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_ceil_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1016,14 +1186,19 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RNDNE_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rndne_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1050,12 +1225,17 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FLOOR_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_floor_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1104,7 +1284,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f32_sdwa" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1153,7 +1341,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f32_sdwa" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1202,7 +1398,14 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1251,7 +1454,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f32_sdwa" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1300,7 +1511,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f32_sdwa" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1568,14 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1398,7 +1624,14 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1680,14 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1737,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1795,14 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1565,14 +1821,19 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RCP_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rcp_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1591,14 +1852,19 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RSQ_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_rsq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1647,7 +1913,14 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1666,14 +1939,19 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SQRT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_sqrt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1722,7 +2000,14 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1771,7 +2056,14 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1820,7 +2112,14 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1869,7 +2168,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_bfrev_b32_sdwa" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1918,7 +2225,14 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : "v_ffbh_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1967,7 +2281,14 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : "v_ffbl_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2016,7 +2337,14 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : "v_ffbh_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2043,12 +2371,18 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_exp_i32_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2075,12 +2409,18 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_frexp_mant_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2107,12 +2447,17 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FRACT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_fract_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2162,7 +2507,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2212,7 +2566,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2225,7 +2588,11 @@ VClrexcpVop1::VClrexcpVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop1::validate_encoding( + "v_clrexcp_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2275,7 +2642,16 @@ VScreenPartition4seB32Vop1::VScreenPartition4seB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_screen_partition_4se_b32_sdwa" + : "v_screen_partition_4se_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2701,14 @@ VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b64_sdwa" + : "v_mov_b64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2376,7 +2759,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2433,7 +2824,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2490,7 +2889,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2547,7 +2954,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2603,7 +3018,14 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2659,7 +3081,14 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2715,7 +3144,14 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2771,7 +3207,14 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2827,7 +3270,14 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2884,7 +3334,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2941,7 +3400,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2997,7 +3465,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f16_sdwa" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3053,7 +3529,14 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3109,7 +3592,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f16_sdwa" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3165,7 +3656,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f16_sdwa" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3221,7 +3720,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f16_sdwa" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3277,7 +3784,14 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3333,7 +3847,14 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3389,7 +3910,16 @@ VExpLegacyF32Vop1::VExpLegacyF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpLegacyF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpLegacyF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_exp_legacy_f32_sdwa" + : "v_exp_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3439,7 +3969,16 @@ VLogLegacyF32Vop1::VLogLegacyF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogLegacyF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogLegacyF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_log_legacy_f32_sdwa" + : "v_log_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3490,7 +4029,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3547,7 +4095,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3603,7 +4160,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3625,14 +4191,19 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_swap_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3684,7 +4255,16 @@ VAccvgprMovB32Vop1::VAccvgprMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVAccvgprMovB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_accvgpr_mov_b32_sdwa" + : "v_accvgpr_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3734,7 +4314,15 @@ VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_fp8_sdwa" + : "v_cvt_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3784,7 +4372,15 @@ VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_bf8_sdwa" + : "v_cvt_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3835,7 +4431,16 @@ VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_fp8_sdwa" + : "v_cvt_pk_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3886,7 +4491,16 @@ VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pk_f32_bf8_sdwa" + : "v_cvt_pk_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3935,7 +4549,14 @@ VPrngB32Vop1::VPrngB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPrngB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPrngB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_prng_b32_sdwa" + : "v_prng_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3951,14 +4572,20 @@ VPermlane16SwapB32Vop1::VPermlane16SwapB32Vop1(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_PERMLANE16_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PERMLANE16_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPermlane16SwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPermlane16SwapB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_permlane16_swap_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3974,14 +4601,20 @@ VPermlane32SwapB32Vop1::VPermlane32SwapB32Vop1(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_PERMLANE32_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PERMLANE32_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPermlane32SwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPermlane32SwapB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + "v_permlane32_swap_b32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_PERMLANE32_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PERMLANE32_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4032,7 +4665,16 @@ VCvtF32Bf16Vop1::VCvtF32Bf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_bf16_sdwa" + : "v_cvt_f32_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp index 883a0f88f760..29df2aa1684e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -67,7 +66,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +130,14 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +192,14 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +255,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,12 +293,17 @@ VFmacF64Vop2::VFmacF64Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -323,7 +358,14 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -379,7 +421,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +485,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -491,7 +550,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -547,7 +614,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +678,14 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +740,14 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -712,7 +802,14 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -767,7 +864,14 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -822,7 +926,14 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +988,14 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -933,7 +1051,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -989,7 +1116,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1045,7 +1181,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1100,7 +1245,14 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1307,14 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1210,7 +1369,14 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1239,12 +1405,18 @@ VDot2cF32Bf16Vop2::VDot2cF32Bf16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_BF16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32Bf16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32Bf16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_f32_bf16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_BF16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1269,15 +1441,20 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAMK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmamk_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1302,15 +1479,20 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAAK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmaak_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1369,7 +1551,15 @@ VAddCoU32Vop2::VAddCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_u32_sdwa" + : "v_add_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1428,7 +1618,15 @@ VSubCoU32Vop2::VSubCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_u32_sdwa" + : "v_sub_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1487,7 +1685,16 @@ VSubrevCoU32Vop2::VSubrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_u32_sdwa" + : "v_subrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1549,7 +1756,15 @@ VAddcCoU32Vop2::VAddcCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_addc_co_u32_sdwa" + : "v_addc_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1611,7 +1826,15 @@ VSubbCoU32Vop2::VSubbCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subb_co_u32_sdwa" + : "v_subb_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +1896,16 @@ VSubbrevCoU32Vop2::VSubbrevCoU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subbrev_co_u32_sdwa" + : "v_subbrev_co_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1729,7 +1961,14 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1791,7 +2030,14 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1854,7 +2100,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1916,7 +2170,14 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1952,12 +2213,17 @@ VMacF16Vop2::VMacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_mac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1990,15 +2256,20 @@ VMadmkF16Vop2::VMadmkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADMK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F16 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVMadmkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madmk_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2031,15 +2302,20 @@ VMadakF16Vop2::VMadakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_MADAK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F16 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVMadakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_madak_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2101,7 +2377,14 @@ VAddU16Vop2::VAddU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u16_sdwa" + : "v_add_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2163,7 +2446,14 @@ VSubU16Vop2::VSubU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u16_sdwa" + : "v_sub_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2226,7 +2516,15 @@ VSubrevU16Vop2::VSubrevU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u16_sdwa" + : "v_subrev_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2289,7 +2587,15 @@ VMulLoU16Vop2::VMulLoU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_lo_u16_sdwa" + : "v_mul_lo_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2352,7 +2658,16 @@ VLshlrevB16Vop2::VLshlrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b16_sdwa" + : "v_lshlrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2415,7 +2730,16 @@ VLshrrevB16Vop2::VLshrrevB16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b16_sdwa" + : "v_lshrrev_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2478,7 +2802,16 @@ VAshrrevI16Vop2::VAshrrevI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i16_sdwa" + : "v_ashrrev_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2540,7 +2873,14 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2602,7 +2942,14 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2664,7 +3011,14 @@ VMaxU16Vop2::VMaxU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u16_sdwa" + : "v_max_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2726,7 +3080,14 @@ VMaxI16Vop2::VMaxI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i16_sdwa" + : "v_max_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2788,7 +3149,14 @@ VMinU16Vop2::VMinU16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u16_sdwa" + : "v_min_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2850,7 +3218,14 @@ VMinI16Vop2::VMinI16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i16_sdwa" + : "v_min_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2912,7 +3287,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ldexp_f16_sdwa" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2973,7 +3356,14 @@ VAddU32Vop2::VAddU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_u32_sdwa" + : "v_add_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3028,7 +3418,14 @@ VSubU32Vop2::VSubU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_u32_sdwa" + : "v_sub_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3084,7 +3481,15 @@ VSubrevU32Vop2::VSubrevU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_u32_sdwa" + : "v_subrev_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3113,12 +3518,18 @@ VDot2cF32F16Vop2::VDot2cF32F16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_f32_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3147,12 +3558,18 @@ VDot2cI32I16Vop2::VDot2cI32I16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_I32_I16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot2c_i32_i16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_I32_I16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3181,12 +3598,18 @@ VDot4cI32I8Vop2::VDot4cI32I8Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT4C_I32_I8 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot4c_i32_i8_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT4C_I32_I8 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3215,12 +3638,18 @@ VDot8cI32I4Vop2::VDot8cI32I4Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT8C_I32_I4 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_dot8c_i32_i4_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT8C_I32_I4 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3249,12 +3678,17 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_fmac_f32_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3283,12 +3717,17 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) dpp_bank_mask_ = dp->bank_mask; dpp_bound_ctrl_ = dp->bound_ctrl; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PK_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + "v_pk_fmac_f16_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3343,7 +3782,14 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3.cpp index 27ae16fd4aab..53340848e313 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -21,7 +20,11 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -38,7 +41,11 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -55,7 +62,12 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readfirstlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +84,11 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -89,7 +105,11 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +126,11 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +147,11 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -157,7 +189,11 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +210,11 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +237,11 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +258,12 @@ VCvtRpiI32F32Vop3::VCvtRpiI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_rpi_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +280,12 @@ VCvtFlrI32F32Vop3::VCvtFlrI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_flr_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -248,7 +302,12 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_off_f32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +324,11 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -282,7 +345,11 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +366,12 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -316,7 +388,12 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +410,12 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +432,12 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -367,7 +454,11 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +475,11 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +496,11 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +517,11 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +538,11 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +559,11 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +580,11 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +601,11 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +622,11 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +643,11 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +664,11 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +685,11 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +706,11 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -588,7 +727,11 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -605,7 +748,12 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_iflag_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -622,7 +770,11 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -639,7 +791,11 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -656,7 +812,11 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -673,7 +833,11 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -690,7 +854,11 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +875,11 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -724,7 +896,11 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +917,11 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +938,11 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -775,7 +959,11 @@ VFfbhU32Vop3::VFfbhU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -792,7 +980,11 @@ VFfblB32Vop3::VFfblB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +1001,11 @@ VFfbhI32Vop3::VFfbhI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -826,7 +1022,12 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -843,7 +1044,12 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -860,7 +1066,11 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1087,12 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1109,12 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -907,7 +1127,11 @@ VClrexcpVop3::VClrexcpVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_clrexcp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1148,12 @@ VScreenPartition4seB32Vop3::VScreenPartition4seB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVScreenPartition4seB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVScreenPartition4seB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_screen_partition_4se_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -941,7 +1170,11 @@ VMovB64Vop3::VMovB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1191,11 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -981,7 +1218,11 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1004,7 +1245,11 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1027,7 +1272,11 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1299,11 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1073,7 +1326,11 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1353,11 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1119,7 +1380,11 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1407,11 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1434,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1188,7 +1462,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1211,7 +1490,11 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1234,7 +1517,11 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1257,7 +1544,11 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1280,7 +1571,11 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1303,7 +1598,11 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1326,7 +1625,11 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1652,11 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1372,7 +1679,12 @@ VExpLegacyF32Vop3::VExpLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1389,7 +1701,12 @@ VLogLegacyF32Vop3::VLogLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1406,7 +1723,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1429,7 +1751,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1779,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sat_pk_u8_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1477,7 +1809,11 @@ VSwapB32Vop3::VSwapB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1500,7 +1836,12 @@ VAccvgprMovB32Vop3::VAccvgprMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAccvgprMovB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_accvgpr_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1517,7 +1858,11 @@ VCvtF32Fp8Vop3::VCvtF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1534,7 +1879,11 @@ VCvtF32Bf8Vop3::VCvtF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1551,7 +1900,12 @@ VCvtPkF32Fp8Vop3::VCvtPkF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_f32_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1568,7 +1922,12 @@ VCvtPkF32Bf8Vop3::VCvtPkF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_f32_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1585,7 +1944,11 @@ VPrngB32Vop3::VPrngB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPrngB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPrngB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_prng_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1967,12 @@ VPermlane16SwapB32Vop3::VPermlane16SwapB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermlane16SwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16SwapB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_permlane16_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1623,7 +1991,12 @@ VPermlane32SwapB32Vop3::VPermlane32SwapB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermlane32SwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane32SwapB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_permlane32_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1640,7 +2013,12 @@ VCvtF32Bf16Vop3::VCvtF32Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1661,7 +2039,12 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cndmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1680,7 +2063,11 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +2086,11 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1718,7 +2109,11 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1738,7 +2133,11 @@ VFmacF64Vop3::VFmacF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1757,7 +2156,11 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2179,11 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1795,7 +2202,12 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1814,7 +2226,11 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1833,7 +2249,12 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1852,7 +2273,11 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1871,7 +2296,11 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1890,7 +2319,11 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1909,7 +2342,11 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1928,7 +2365,11 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1947,7 +2388,11 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1966,7 +2411,12 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1985,7 +2435,12 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2004,7 +2459,12 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2023,7 +2483,11 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2042,7 +2506,11 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2061,7 +2529,11 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2081,7 +2553,12 @@ VDot2cF32Bf16Vop3::VDot2cF32Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cF32Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_f32_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2100,7 +2577,11 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2125,7 +2606,11 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2150,7 +2635,11 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2175,7 +2664,11 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2201,7 +2694,11 @@ VMacF16Vop3::VMacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2226,7 +2723,11 @@ VAddU16Vop3::VAddU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2251,7 +2752,11 @@ VSubU16Vop3::VSubU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2276,7 +2781,11 @@ VSubrevU16Vop3::VSubrevU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2301,7 +2810,11 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2326,7 +2839,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2351,7 +2869,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2376,7 +2899,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2401,7 +2929,11 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2426,7 +2958,11 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2451,7 +2987,11 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2476,7 +3016,11 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2501,7 +3045,11 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2526,7 +3074,11 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2551,7 +3103,11 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2576,7 +3132,11 @@ VAddU32Vop3::VAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2595,7 +3155,11 @@ VSubU32Vop3::VSubU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2614,7 +3178,11 @@ VSubrevU32Vop3::VSubrevU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2634,7 +3202,12 @@ VDot2cF32F16Vop3::VDot2cF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2654,7 +3227,12 @@ VDot2cI32I16Vop3::VDot2cI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cI32I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2674,7 +3252,12 @@ VDot4cI32I8Vop3::VDot4cI32I8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot4c_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2694,7 +3277,12 @@ VDot8cI32I4Vop3::VDot8cI32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8cI32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot8cI32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot8c_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2714,7 +3302,11 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2734,7 +3326,11 @@ VPkFmacF16Vop3::VPkFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pk_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3349,11 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2774,7 +3374,11 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2795,7 +3399,11 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2816,7 +3424,11 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubeid_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2837,7 +3449,11 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubesc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2858,7 +3474,11 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubetc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2879,7 +3499,11 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubema_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2900,7 +3524,11 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2921,7 +3549,11 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2942,7 +3574,11 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2963,7 +3599,11 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2984,7 +3624,11 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3005,7 +3649,11 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lerp_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3026,7 +3674,12 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbit_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3047,7 +3700,12 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbyte_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3068,7 +3726,11 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3089,7 +3751,11 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3110,7 +3776,11 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3131,7 +3801,11 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3152,7 +3826,11 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3173,7 +3851,11 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3194,7 +3876,11 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3215,7 +3901,11 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3236,7 +3926,11 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3257,7 +3951,11 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3278,7 +3976,11 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3299,7 +4001,11 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3320,7 +4026,11 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3341,7 +4051,12 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3362,7 +4077,12 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3383,7 +4103,12 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3407,7 +4132,12 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3431,7 +4161,12 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3452,7 +4187,11 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_msad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3473,7 +4212,12 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_qsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3494,7 +4238,12 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3515,7 +4264,12 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3536,7 +4290,12 @@ VMadLegacyF16Vop3::VMadLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3563,7 +4322,12 @@ VMadLegacyU16Vop3::VMadLegacyU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyU16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3590,7 +4354,12 @@ VMadLegacyI16Vop3::VMadLegacyI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3617,7 +4386,11 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_perm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3638,7 +4411,12 @@ VFmaLegacyF16Vop3::VFmaLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3665,7 +4443,12 @@ VDivFixupLegacyF16Vop3::VDivFixupLegacyF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupLegacyF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_legacy_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3691,7 +4474,12 @@ VCvtPkaccumU8F32Vop3::VCvtPkaccumU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkaccumU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkaccum_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3712,7 +4500,11 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3733,7 +4525,11 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3754,7 +4550,11 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3775,7 +4575,11 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3802,7 +4606,11 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3829,7 +4637,11 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3856,7 +4668,11 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3883,7 +4699,11 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3910,7 +4730,11 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3937,7 +4761,11 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3964,7 +4792,11 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3991,7 +4823,11 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4018,7 +4854,12 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4039,7 +4880,12 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_lshl_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4060,7 +4906,11 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4081,7 +4931,11 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4102,7 +4956,11 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4123,7 +4981,11 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4144,7 +5006,11 @@ VMadF16Vop3::VMadF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4171,7 +5037,11 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4198,7 +5068,11 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4225,7 +5099,11 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4252,7 +5130,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4279,7 +5162,12 @@ VLshlAddU64Vop3::VLshlAddU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4300,7 +5188,11 @@ VBitop3B16Vop3::VBitop3B16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBitop3B16Vop3(const MachineInst *opcode) { +DecodeResult decodeVBitop3B16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bitop3_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4327,7 +5219,11 @@ VBitop3B32Vop3::VBitop3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBitop3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBitop3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bitop3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4348,7 +5244,12 @@ VCvtScalef32PkFp8F32Vop3::VCvtScalef32PkFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_fp8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4375,7 +5276,12 @@ VCvtScalef32PkBf8F32Vop3::VCvtScalef32PkBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_bf8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4402,7 +5308,12 @@ VCvtScalef32SrFp8F32Vop3::VCvtScalef32SrFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_sr_fp8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4429,7 +5340,12 @@ VCvtScalef32SrBf8F32Vop3::VCvtScalef32SrBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_sr_bf8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4454,7 +5370,12 @@ VCvtScalef32PkF32Fp8Vop3::VCvtScalef32PkF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_f32_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4473,7 +5394,12 @@ VCvtScalef32PkF32Bf8Vop3::VCvtScalef32PkF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_f32_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4492,7 +5418,12 @@ VCvtScalef32F32Fp8Vop3::VCvtScalef32F32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32F32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32F32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_f32_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4511,7 +5442,12 @@ VCvtScalef32F32Bf8Vop3::VCvtScalef32F32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32F32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32F32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_f32_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4532,7 +5468,12 @@ VCvtScalef32PkFp4F32Vop3::VCvtScalef32PkFp4F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkFp4F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkFp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_fp4_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4559,7 +5500,13 @@ VCvtScalef32SrPkFp4F32Vop3::VCvtScalef32SrPkFp4F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPkFp4F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPkFp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk_fp4_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4584,7 +5531,12 @@ VCvtScalef32PkF32Fp4Vop3::VCvtScalef32PkF32Fp4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkF32Fp4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkF32Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_f32_fp4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4603,7 +5555,12 @@ VCvtScalef32PkFp8F16Vop3::VCvtScalef32PkFp8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkFp8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_fp8_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4628,7 +5585,12 @@ VCvtScalef32PkBf8F16Vop3::VCvtScalef32PkBf8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkBf8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_bf8_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4655,7 +5617,12 @@ VCvtScalef32SrFp8F16Vop3::VCvtScalef32SrFp8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrFp8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_sr_fp8_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4682,7 +5649,12 @@ VCvtScalef32SrBf8F16Vop3::VCvtScalef32SrBf8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrBf8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_sr_bf8_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4707,7 +5679,12 @@ VCvtScalef32PkFp8Bf16Vop3::VCvtScalef32PkFp8Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkFp8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkFp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_fp8_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4732,7 +5709,12 @@ VCvtScalef32PkBf8Bf16Vop3::VCvtScalef32PkBf8Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkBf8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkBf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_bf8_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4759,7 +5741,12 @@ VCvtScalef32SrFp8Bf16Vop3::VCvtScalef32SrFp8Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrFp8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrFp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_sr_fp8_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4786,7 +5773,12 @@ VCvtScalef32SrBf8Bf16Vop3::VCvtScalef32SrBf8Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrBf8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrBf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_sr_bf8_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4811,7 +5803,12 @@ VCvtScalef32PkF16Fp8Vop3::VCvtScalef32PkF16Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkF16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkF16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_f16_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4830,7 +5827,12 @@ VCvtScalef32PkF16Bf8Vop3::VCvtScalef32PkF16Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkF16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkF16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_f16_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4849,7 +5851,12 @@ VCvtScalef32F16Fp8Vop3::VCvtScalef32F16Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32F16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32F16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_f16_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4874,7 +5881,12 @@ VCvtScalef32F16Bf8Vop3::VCvtScalef32F16Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32F16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32F16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_f16_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4899,7 +5911,12 @@ VCvtScalef32PkFp4F16Vop3::VCvtScalef32PkFp4F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkFp4F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkFp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_fp4_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4924,7 +5941,12 @@ VCvtScalef32PkFp4Bf16Vop3::VCvtScalef32PkFp4Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkFp4Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkFp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_fp4_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4951,7 +5973,13 @@ VCvtScalef32SrPkFp4F16Vop3::VCvtScalef32SrPkFp4F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPkFp4F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPkFp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk_fp4_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4978,7 +6006,13 @@ VCvtScalef32SrPkFp4Bf16Vop3::VCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPkFp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk_fp4_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5003,7 +6037,12 @@ VCvtScalef32PkF16Fp4Vop3::VCvtScalef32PkF16Fp4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkF16Fp4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkF16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_f16_fp4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5022,7 +6061,12 @@ VCvtScalef32PkBf16Fp4Vop3::VCvtScalef32PkBf16Fp4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkBf16Fp4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkBf16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_bf16_fp4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5043,7 +6087,13 @@ VCvtScalef322xpk16Fp6F32Vop3::VCvtScalef322xpk16Fp6F32Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef322xpk16Fp6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef322xpk16Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_2xpk16_fp6_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5064,7 +6114,13 @@ VCvtScalef322xpk16Bf6F32Vop3::VCvtScalef322xpk16Bf6F32Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef322xpk16Bf6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef322xpk16Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_2xpk16_bf6_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5085,7 +6141,13 @@ VCvtScalef32SrPk32Fp6F32Vop3::VCvtScalef32SrPk32Fp6F32Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk32Fp6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk32Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk32_fp6_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5106,7 +6168,13 @@ VCvtScalef32SrPk32Bf6F32Vop3::VCvtScalef32SrPk32Bf6F32Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk32Bf6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk32Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk32_bf6_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5125,7 +6193,13 @@ VCvtScalef32Pk32F32Fp6Vop3::VCvtScalef32Pk32F32Fp6Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32F32Fp6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32F32Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_f32_fp6", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5144,7 +6218,13 @@ VCvtScalef32Pk32F32Bf6Vop3::VCvtScalef32Pk32F32Bf6Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32F32Bf6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32F32Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_f32_bf6", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5163,7 +6243,13 @@ VCvtScalef32Pk32Fp6F16Vop3::VCvtScalef32Pk32Fp6F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32Fp6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_fp6_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5182,7 +6268,13 @@ VCvtScalef32Pk32Fp6Bf16Vop3::VCvtScalef32Pk32Fp6Bf16Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32Fp6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_fp6_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5201,7 +6293,13 @@ VCvtScalef32Pk32Bf6F16Vop3::VCvtScalef32Pk32Bf6F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32Bf6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_bf6_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5220,7 +6318,13 @@ VCvtScalef32Pk32Bf6Bf16Vop3::VCvtScalef32Pk32Bf6Bf16Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32Bf6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_bf6_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5241,7 +6345,13 @@ VCvtScalef32SrPk32Fp6F16Vop3::VCvtScalef32SrPk32Fp6F16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk32Fp6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk32Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk32_fp6_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5262,7 +6372,13 @@ VCvtScalef32SrPk32Fp6Bf16Vop3::VCvtScalef32SrPk32Fp6Bf16Vop3(const MachineInst * } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk32Fp6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk32Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk32_fp6_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5283,7 +6399,13 @@ VCvtScalef32SrPk32Bf6F16Vop3::VCvtScalef32SrPk32Bf6F16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk32Bf6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk32Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk32_bf6_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5304,7 +6426,13 @@ VCvtScalef32SrPk32Bf6Bf16Vop3::VCvtScalef32SrPk32Bf6Bf16Vop3(const MachineInst * } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk32Bf6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk32Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_sr_pk32_bf6_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5323,7 +6451,13 @@ VCvtScalef32Pk32F16Fp6Vop3::VCvtScalef32Pk32F16Fp6Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32F16Fp6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32F16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_f16_fp6", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5342,7 +6476,13 @@ VCvtScalef32Pk32Bf16Fp6Vop3::VCvtScalef32Pk32Bf16Fp6Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32Bf16Fp6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32Bf16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_bf16_fp6", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5361,7 +6501,13 @@ VCvtScalef32Pk32F16Bf6Vop3::VCvtScalef32Pk32F16Bf6Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32F16Bf6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32F16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_f16_bf6", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5380,7 +6526,13 @@ VCvtScalef32Pk32Bf16Bf6Vop3::VCvtScalef32Pk32Bf16Bf6Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk32Bf16Bf6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk32Bf16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vop3::validate_encoding("v_cvt_scalef32_pk32_bf16_bf6", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5401,7 +6553,12 @@ VAshrPkI8I32Vop3::VAshrPkI8I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrPkI8I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrPkI8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashr_pk_i8_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5428,7 +6585,12 @@ VAshrPkU8I32Vop3::VAshrPkU8I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrPkU8I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrPkU8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashr_pk_u8_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5453,7 +6615,12 @@ VCvtPkF16F32Vop3::VCvtPkF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5472,7 +6639,12 @@ VCvtPkBf16F32Vop3::VCvtPkBf16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_bf16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5491,7 +6663,12 @@ VCvtScalef32PkBf16Fp8Vop3::VCvtScalef32PkBf16Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkBf16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkBf16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_bf16_fp8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5510,7 +6687,12 @@ VCvtScalef32PkBf16Bf8Vop3::VCvtScalef32PkBf16Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtScalef32PkBf16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32PkBf16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_scalef32_pk_bf16_bf8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5529,7 +6711,11 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5548,7 +6734,11 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5567,7 +6757,11 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5586,7 +6780,11 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5605,7 +6803,11 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5624,7 +6826,11 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5643,7 +6849,11 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5662,7 +6872,11 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5681,7 +6895,11 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5700,7 +6918,12 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5720,7 +6943,12 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_writelane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5745,7 +6973,12 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bcnt_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5764,7 +6997,12 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_lo_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5783,7 +7021,12 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_hi_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5802,7 +7045,12 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5821,7 +7069,12 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5840,7 +7093,12 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5859,7 +7117,12 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trig_preop_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5878,7 +7141,11 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5897,7 +7164,12 @@ VCvtPknormI16F32Vop3::VCvtPknormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5916,7 +7188,12 @@ VCvtPknormU16F32Vop3::VCvtPknormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5935,7 +7212,12 @@ VCvtPkrtzF16F32Vop3::VCvtPkrtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkrtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5954,7 +7236,12 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u16_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5973,7 +7260,12 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_i16_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5992,7 +7284,12 @@ VCvtPknormI16F16Vop3::VCvtPknormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6011,7 +7308,12 @@ VCvtPknormU16F16Vop3::VCvtPknormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6030,7 +7332,11 @@ VAddI32Vop3::VAddI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6049,7 +7355,11 @@ VSubI32Vop3::VSubI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6068,7 +7378,11 @@ VAddI16Vop3::VAddI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6093,7 +7407,11 @@ VSubI16Vop3::VSubI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6118,7 +7436,12 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pack_b32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6137,7 +7460,12 @@ VMulLegacyF32Vop3::VMulLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6156,7 +7484,12 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_fp8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6181,7 +7514,12 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_bf8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6206,7 +7544,12 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_sr_fp8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6231,7 +7574,12 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_sr_bf8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6256,7 +7604,12 @@ VCvtSrF16F32Vop3::VCvtSrF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_sr_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6281,7 +7634,12 @@ VCvtSrBf16F32Vop3::VCvtSrBf16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrBf16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_sr_bf16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6308,7 +7666,12 @@ VMinimum3F32Vop3::VMinimum3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimum3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_minimum3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6329,7 +7692,12 @@ VMaximum3F32Vop3::VMaximum3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximum3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_maximum3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6348,7 +7716,12 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6371,7 +7744,12 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6390,7 +7768,12 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6413,7 +7796,12 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6432,7 +7820,12 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6455,7 +7848,12 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6474,7 +7872,11 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6493,7 +7895,11 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6512,7 +7918,11 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6531,7 +7941,11 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6550,7 +7964,11 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6569,7 +7987,11 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6588,7 +8010,11 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6607,7 +8033,11 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6626,7 +8056,11 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6645,7 +8079,11 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6664,7 +8102,11 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6683,7 +8125,11 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6702,7 +8148,11 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6721,7 +8171,11 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6740,7 +8194,11 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6759,7 +8217,11 @@ VCmpTruF16Vop3::VCmpTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6782,7 +8244,11 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6805,7 +8271,11 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6828,7 +8298,11 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6851,7 +8325,11 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6874,7 +8352,11 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6897,7 +8379,11 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6920,7 +8406,11 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6943,7 +8433,11 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6966,7 +8460,11 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6989,7 +8487,12 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7012,7 +8515,12 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7035,7 +8543,12 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7058,7 +8571,12 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7081,7 +8599,12 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7104,7 +8627,12 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7127,7 +8655,12 @@ VCmpxTruF16Vop3::VCmpxTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7146,7 +8679,11 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7165,7 +8702,11 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7184,7 +8725,11 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7203,7 +8748,11 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7222,7 +8771,11 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7241,7 +8794,11 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7260,7 +8817,11 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7279,7 +8840,11 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7298,7 +8863,11 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7317,7 +8886,11 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7336,7 +8909,11 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7355,7 +8932,11 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7374,7 +8955,11 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7393,7 +8978,11 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7412,7 +9001,11 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7431,7 +9024,11 @@ VCmpTruF32Vop3::VCmpTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7454,7 +9051,11 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7477,7 +9078,11 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7500,7 +9105,11 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7523,7 +9132,11 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7546,7 +9159,11 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7569,7 +9186,11 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7592,7 +9213,11 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7615,7 +9240,11 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7638,7 +9267,11 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7661,7 +9294,12 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7684,7 +9322,12 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7707,7 +9350,12 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7730,7 +9378,12 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7753,7 +9406,12 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7776,7 +9434,12 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7799,7 +9462,12 @@ VCmpxTruF32Vop3::VCmpxTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7818,7 +9486,11 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7837,7 +9509,11 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7856,7 +9532,11 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7875,7 +9555,11 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7894,7 +9578,11 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7913,7 +9601,11 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7932,7 +9624,11 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7951,7 +9647,11 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7970,7 +9670,11 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7989,7 +9693,11 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8008,7 +9716,11 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8027,7 +9739,11 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8046,7 +9762,11 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8065,7 +9785,11 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8084,7 +9808,11 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8103,7 +9831,11 @@ VCmpTruF64Vop3::VCmpTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8126,7 +9858,11 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8149,7 +9885,11 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8172,7 +9912,11 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8195,7 +9939,11 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8218,7 +9966,11 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8241,7 +9993,11 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8264,7 +10020,11 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8287,7 +10047,11 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8310,7 +10074,11 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8333,7 +10101,12 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8356,7 +10129,12 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8379,7 +10157,12 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8402,7 +10185,12 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8425,7 +10213,12 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8448,7 +10241,12 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8471,7 +10269,12 @@ VCmpxTruF64Vop3::VCmpxTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8490,7 +10293,11 @@ VCmpFI16Vop3::VCmpFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8509,7 +10316,11 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8528,7 +10339,11 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8547,7 +10362,11 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8566,7 +10385,11 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8585,7 +10408,11 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8604,7 +10431,11 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8623,7 +10454,11 @@ VCmpTI16Vop3::VCmpTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8642,7 +10477,11 @@ VCmpFU16Vop3::VCmpFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8661,7 +10500,11 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8680,7 +10523,11 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8699,7 +10546,11 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8718,7 +10569,11 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8737,7 +10592,11 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8756,7 +10615,11 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8775,7 +10638,11 @@ VCmpTU16Vop3::VCmpTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8798,7 +10665,11 @@ VCmpxFI16Vop3::VCmpxFI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8821,7 +10692,11 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8844,7 +10719,11 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8867,7 +10746,11 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8890,7 +10773,11 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8913,7 +10800,11 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8936,7 +10827,11 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8959,7 +10854,11 @@ VCmpxTI16Vop3::VCmpxTI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8982,7 +10881,11 @@ VCmpxFU16Vop3::VCmpxFU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9005,7 +10908,11 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9028,7 +10935,11 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9051,7 +10962,11 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9074,7 +10989,11 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9097,7 +11016,11 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9120,7 +11043,11 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9143,7 +11070,11 @@ VCmpxTU16Vop3::VCmpxTU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9162,7 +11093,11 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9181,7 +11116,11 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9200,7 +11139,11 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9219,7 +11162,11 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9238,7 +11185,11 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9257,7 +11208,11 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9276,7 +11231,11 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9295,7 +11254,11 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9314,7 +11277,11 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9333,7 +11300,11 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9352,7 +11323,11 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9371,7 +11346,11 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9390,7 +11369,11 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9409,7 +11392,11 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9428,7 +11415,11 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9447,7 +11438,11 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9470,7 +11465,11 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9493,7 +11492,11 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9516,7 +11519,11 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9539,7 +11546,11 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9562,7 +11573,11 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9585,7 +11600,11 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9608,7 +11627,11 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9631,7 +11654,11 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9654,7 +11681,11 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9677,7 +11708,11 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9700,7 +11735,11 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9723,7 +11762,11 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9746,7 +11789,11 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9769,7 +11816,11 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9792,7 +11843,11 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9815,7 +11870,11 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9834,7 +11893,11 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9853,7 +11916,11 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9872,7 +11939,11 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9891,7 +11962,11 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9910,7 +11985,11 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9929,7 +12008,11 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9948,7 +12031,11 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9967,7 +12054,11 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9986,7 +12077,11 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10005,7 +12100,11 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10024,7 +12123,11 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10043,7 +12146,11 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10062,7 +12169,11 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10081,7 +12192,11 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10100,7 +12215,11 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10119,7 +12238,11 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10142,7 +12265,11 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10165,7 +12292,11 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10188,7 +12319,11 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10211,7 +12346,11 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10234,7 +12373,11 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10257,7 +12400,11 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10280,7 +12427,11 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10303,7 +12454,11 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10326,7 +12481,11 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10349,7 +12508,11 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10372,7 +12535,11 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10395,7 +12562,11 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10418,7 +12589,11 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10441,7 +12616,11 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10464,7 +12643,11 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10487,7 +12670,11 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10508,7 +12695,12 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10529,7 +12721,12 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10550,7 +12747,12 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10573,7 +12775,12 @@ VAddcCoU32Vop3SdstEnc::VAddcCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddcCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_addc_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10596,7 +12803,12 @@ VSubbCoU32Vop3SdstEnc::VSubbCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subb_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10619,7 +12831,12 @@ VSubbrevCoU32Vop3SdstEnc::VSubbrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubbrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subbrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10642,7 +12859,12 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10665,7 +12887,12 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10688,7 +12915,12 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_u64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10711,7 +12943,12 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_i64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.cpp index 459e512dfacd..4730fa64f459 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -59,7 +58,11 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +81,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +105,11 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +128,11 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -135,7 +151,12 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +175,12 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -173,7 +199,12 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +223,11 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -211,7 +246,11 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +271,11 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -251,7 +294,11 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +317,11 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +340,11 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -308,7 +363,11 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +388,11 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -348,7 +411,11 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -367,7 +434,11 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -386,7 +457,11 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +480,11 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -426,7 +505,12 @@ VDot2F32Bf16Vop3p::VDot2F32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -447,7 +531,12 @@ VPkMinimum3F16Vop3p::VPkMinimum3F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinimum3F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinimum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_minimum3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +557,12 @@ VPkMaximum3F16Vop3p::VPkMaximum3F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaximum3F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaximum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_maximum3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -489,7 +583,12 @@ VMadMixF32Vop3p::VMadMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mix_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -511,7 +610,12 @@ VMadMixloF16Vop3p::VMadMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixlo_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -539,7 +643,12 @@ VMadMixhiF16Vop3p::VMadMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVMadMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_mad_mixhi_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -566,7 +675,12 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -587,7 +701,12 @@ VDot2I32I16Vop3p::VDot2I32I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -608,7 +727,12 @@ VDot2U32U16Vop3p::VDot2U32U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -629,7 +753,12 @@ VDot4I32I8Vop3p::VDot4I32I8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +779,12 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -671,7 +805,12 @@ VDot8I32I4Vop3p::VDot8I32I4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -692,7 +831,12 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_u32_u4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -713,7 +857,11 @@ VPkFmaF32Vop3p::VPkFmaF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -732,7 +880,11 @@ VPkMulF32Vop3p::VPkMulF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -751,7 +903,11 @@ VPkAddF32Vop3p::VPkAddF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +926,11 @@ VPkMovB32Vop3p::VPkMovB32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMovB32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMovB32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +951,12 @@ VAccvgprReadVop3p::VAccvgprReadVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprReadVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprReadVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_read", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +974,12 @@ VAccvgprWriteVop3p::VAccvgprWriteVop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAccvgprWriteVop3p(const MachineInst *opcode) { +DecodeResult decodeVAccvgprWriteVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_accvgpr_write", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -857,7 +1027,13 @@ VMfmaF3216x16x128F8f6f4Vop3pMfma::VMfmaF3216x16x128F8f6f4Vop3pMfma(const Machine } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x128F8f6f4Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x128F8f6f4Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x128_f8f6f4", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -905,7 +1081,13 @@ VMfmaF3232x32x64F8f6f4Vop3pMfma::VMfmaF3232x32x64F8f6f4Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x64F8f6f4Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x64F8f6f4Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x64_f8f6f4", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -943,7 +1125,13 @@ VMfmaF3216x16x32Bf16Vop3pMfma::VMfmaF3216x16x32Bf16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -981,7 +1169,13 @@ VMfmaI3216x16x64I8Vop3pMfma::VMfmaI3216x16x64I8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x64I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x64_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1019,7 +1213,13 @@ VMfmaF3232x32x16Bf16Vop3pMfma::VMfmaF3232x32x16Bf16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1257,13 @@ VMfmaI3232x32x32I8Vop3pMfma::VMfmaI3232x32x32I8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x32I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x32_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1094,7 +1300,13 @@ VSmfmacF3216x16x64Bf16Vop3pMfma::VSmfmacF3216x16x64Bf16Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1131,7 +1343,13 @@ VSmfmacI3216x16x128I8Vop3pMfma::VSmfmacI3216x16x128I8Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacI3216x16x128I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacI3216x16x128I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_i32_16x16x128_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1168,7 +1386,13 @@ VSmfmacF3216x16x128Bf8Bf8Vop3pMfma::VSmfmacF3216x16x128Bf8Bf8Vop3pMfma(const Mac } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x128Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x128Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x128_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1429,13 @@ VSmfmacF3216x16x128Bf8Fp8Vop3pMfma::VSmfmacF3216x16x128Bf8Fp8Vop3pMfma(const Mac } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x128Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x128Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x128_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1242,7 +1472,13 @@ VSmfmacF3216x16x128Fp8Bf8Vop3pMfma::VSmfmacF3216x16x128Fp8Bf8Vop3pMfma(const Mac } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x128Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x128Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x128_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1280,7 +1516,13 @@ VMfmaF3232x32x12bF32Vop3pMfma::VMfmaF3232x32x12bF32Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x12bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x1_2b_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1318,7 +1560,13 @@ VMfmaF3216x16x14bF32Vop3pMfma::VMfmaF3216x16x14bF32Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x14bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x1_4b_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1356,7 +1604,13 @@ VMfmaF324x4x116bF32Vop3pMfma::VMfmaF324x4x116bF32Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x116bF32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x1_16b_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1393,7 +1647,13 @@ VSmfmacF3216x16x128Fp8Fp8Vop3pMfma::VSmfmacF3216x16x128Fp8Fp8Vop3pMfma(const Mac } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x128Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x128Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x128_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1431,7 +1691,13 @@ VMfmaF3232x32x2F32Vop3pMfma::VMfmaF3232x32x2F32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x2F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x2_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1469,7 +1735,13 @@ VMfmaF3216x16x4F32Vop3pMfma::VMfmaF3216x16x4F32Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x4F32Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4_f32", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1506,7 +1778,13 @@ VSmfmacF3232x32x32Bf16Vop3pMfma::VSmfmacF3232x32x32Bf16Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1543,7 +1821,13 @@ VSmfmacI3232x32x64I8Vop3pMfma::VSmfmacI3232x32x64I8Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVSmfmacI3232x32x64I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacI3232x32x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_i32_32x32x64_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1581,7 +1865,13 @@ VMfmaF3232x32x42bF16Vop3pMfma::VMfmaF3232x32x42bF16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x42bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4_2b_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1619,7 +1909,13 @@ VMfmaF3216x16x44bF16Vop3pMfma::VMfmaF3216x16x44bF16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x44bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4_4b_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1657,7 +1953,13 @@ VMfmaF324x4x416bF16Vop3pMfma::VMfmaF324x4x416bF16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x416bF16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4_16b_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1694,7 +1996,13 @@ VSmfmacF3232x32x64Bf8Bf8Vop3pMfma::VSmfmacF3232x32x64Bf8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x64Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x64Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x64_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1732,7 +2040,13 @@ VMfmaF3232x32x8F16Vop3pMfma::VMfmaF3232x32x8F16Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1770,7 +2084,13 @@ VMfmaF3216x16x16F16Vop3pMfma::VMfmaF3216x16x16F16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1807,7 +2127,13 @@ VSmfmacF3232x32x64Bf8Fp8Vop3pMfma::VSmfmacF3232x32x64Bf8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x64Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x64Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x64_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1844,7 +2170,13 @@ VSmfmacF3232x32x64Fp8Bf8Vop3pMfma::VSmfmacF3232x32x64Fp8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x64Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x64Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x64_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1882,7 +2214,13 @@ VMfmaI3232x32x42bI8Vop3pMfma::VMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x42bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x4_2b_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1920,7 +2258,13 @@ VMfmaI3216x16x44bI8Vop3pMfma::VMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x44bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x4_4b_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1958,7 +2302,13 @@ VMfmaI324x4x416bI8Vop3pMfma::VMfmaI324x4x416bI8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI324x4x416bI8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_4x4x4_16b_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1995,7 +2345,13 @@ VSmfmacF3232x32x64Fp8Fp8Vop3pMfma::VSmfmacF3232x32x64Fp8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x64Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x64Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x64_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2033,7 +2389,13 @@ VMfmaF3216x16x32F16Vop3pMfma::VMfmaF3216x16x32F16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2071,7 +2433,13 @@ VMfmaF3232x32x16F16Vop3pMfma::VMfmaF3232x32x16F16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2109,7 +2477,13 @@ VMfmaI3232x32x16I8Vop3pMfma::VMfmaI3232x32x16I8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3232x32x16I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_32x32x16_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2147,7 +2521,13 @@ VMfmaI3216x16x32I8Vop3pMfma::VMfmaI3216x16x32I8Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaI3216x16x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_i32_16x16x32_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2184,7 +2564,13 @@ VSmfmacF3216x16x64F16Vop3pMfma::VSmfmacF3216x16x64F16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2221,7 +2607,13 @@ VSmfmacF3232x32x32F16Vop3pMfma::VSmfmacF3232x32x32F16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2259,7 +2651,13 @@ VMfmaF3232x32x42bBf16Vop3pMfma::VMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x42bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x4_2b_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2297,7 +2695,13 @@ VMfmaF3216x16x44bBf16Vop3pMfma::VMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x44bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x4_4b_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2335,7 +2739,13 @@ VMfmaF324x4x416bBf16Vop3pMfma::VMfmaF324x4x416bBf16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF324x4x416bBf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_4x4x4_16b_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2373,7 +2783,13 @@ VMfmaF3232x32x8Bf16Vop3pMfma::VMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *in } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x8Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x8_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2411,7 +2827,13 @@ VMfmaF3216x16x16Bf16Vop3pMfma::VMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x16_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2448,7 +2870,13 @@ VSmfmacF3216x16x32F16Vop3pMfma::VSmfmacF3216x16x32F16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x32F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x32_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2485,7 +2913,13 @@ VSmfmacF3232x32x16F16Vop3pMfma::VSmfmacF3232x32x16F16Vop3pMfma(const MachineInst } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x16F16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x16_f16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2522,7 +2956,13 @@ VSmfmacF3216x16x32Bf16Vop3pMfma::VSmfmacF3216x16x32Bf16Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x32Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x32_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2559,7 +2999,13 @@ VSmfmacF3232x32x16Bf16Vop3pMfma::VSmfmacF3232x32x16Bf16Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x16Bf16Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x16_bf16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2596,7 +3042,13 @@ VSmfmacI3216x16x64I8Vop3pMfma::VSmfmacI3216x16x64I8Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacI3216x16x64I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_i32_16x16x64_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2633,7 +3085,13 @@ VSmfmacI3232x32x32I8Vop3pMfma::VSmfmacI3232x32x32I8Vop3pMfma(const MachineInst * } namespace detail { -std::unique_ptr decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacI3232x32x32I8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_i32_32x32x32_i8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2671,7 +3129,13 @@ VMfmaF6416x16x4F64Vop3pMfma::VMfmaF6416x16x4F64Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF6416x16x4F64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f64_16x16x4_f64", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2709,7 +3173,13 @@ VMfmaF644x4x44bF64Vop3pMfma::VMfmaF644x4x44bF64Vop3pMfma(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF644x4x44bF64Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f64_4x4x4_4b_f64", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2747,7 +3217,13 @@ VMfmaF3216x16x32Bf8Bf8Vop3pMfma::VMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2785,7 +3261,13 @@ VMfmaF3216x16x32Bf8Fp8Vop3pMfma::VMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2823,7 +3305,13 @@ VMfmaF3216x16x32Fp8Bf8Vop3pMfma::VMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2861,7 +3349,13 @@ VMfmaF3216x16x32Fp8Fp8Vop3pMfma::VMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3216x16x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_16x16x32_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2899,7 +3393,13 @@ VMfmaF3232x32x16Bf8Bf8Vop3pMfma::VMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2937,7 +3437,13 @@ VMfmaF3232x32x16Bf8Fp8Vop3pMfma::VMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2975,7 +3481,13 @@ VMfmaF3232x32x16Fp8Bf8Vop3pMfma::VMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3013,7 +3525,13 @@ VMfmaF3232x32x16Fp8Fp8Vop3pMfma::VMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineIn } namespace detail { -std::unique_ptr decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVMfmaF3232x32x16Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_mfma_f32_32x32x16_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3050,7 +3568,13 @@ VSmfmacF3216x16x64Bf8Bf8Vop3pMfma::VSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3087,7 +3611,13 @@ VSmfmacF3216x16x64Bf8Fp8Vop3pMfma::VSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3124,7 +3654,13 @@ VSmfmacF3216x16x64Fp8Bf8Vop3pMfma::VSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3161,7 +3697,13 @@ VSmfmacF3216x16x64Fp8Fp8Vop3pMfma::VSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3216x16x64Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_16x16x64_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3198,7 +3740,13 @@ VSmfmacF3232x32x32Bf8Bf8Vop3pMfma::VSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Bf8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_bf8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3235,7 +3783,13 @@ VSmfmacF3232x32x32Bf8Fp8Vop3pMfma::VSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Bf8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_bf8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3272,7 +3826,13 @@ VSmfmacF3232x32x32Fp8Bf8Vop3pMfma::VSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Fp8Bf8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_fp8_bf8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3309,7 +3869,13 @@ VSmfmacF3232x32x32Fp8Fp8Vop3pMfma::VSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const Machi } namespace detail { -std::unique_ptr decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode) { +DecodeResult decodeVSmfmacF3232x32x32Fp8Fp8Vop3pMfma(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3pMfma::validate_encoding( + "v_smfmac_f32_32x32x32_fp8_fp8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp index 35859f8f9cbe..69dc6f4e7547 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,8 +30,6 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -60,7 +57,18 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -85,8 +93,6 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -116,7 +122,18 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,15 +154,21 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -168,17 +191,23 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -202,8 +231,6 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -231,7 +258,18 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -257,8 +295,6 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -288,7 +324,18 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -311,8 +358,6 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -340,7 +385,17 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -364,8 +419,6 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -393,7 +446,17 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -417,8 +480,6 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -446,7 +507,17 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -470,8 +541,6 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -499,7 +568,17 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -523,8 +602,6 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -552,7 +629,17 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -576,8 +663,6 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -605,7 +690,17 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -629,8 +724,6 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -658,7 +751,17 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -681,8 +784,6 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -710,7 +811,17 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -733,8 +844,6 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -762,7 +871,17 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -786,8 +905,6 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -815,7 +932,17 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -839,8 +966,6 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -868,7 +993,17 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -892,8 +1027,6 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -921,7 +1054,17 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -945,8 +1088,6 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -974,7 +1115,17 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -998,8 +1149,6 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1027,7 +1176,17 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1051,8 +1210,6 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1080,7 +1237,17 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1104,8 +1271,6 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1133,7 +1298,17 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1159,8 +1334,6 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1190,7 +1363,17 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1216,8 +1399,6 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1247,7 +1428,17 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1273,8 +1464,6 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1304,7 +1493,17 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1330,8 +1529,6 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1361,7 +1558,17 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1387,8 +1594,6 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1418,7 +1623,17 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1444,8 +1659,6 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1475,7 +1688,17 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1501,8 +1724,6 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1532,7 +1753,17 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1558,8 +1789,6 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1589,7 +1818,17 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1615,8 +1854,6 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1646,7 +1883,17 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1672,8 +1919,6 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1703,7 +1948,18 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1729,8 +1985,6 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1760,7 +2014,18 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1786,8 +2051,6 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1817,7 +2080,18 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1843,8 +2117,6 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1874,7 +2146,18 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1900,8 +2183,6 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1931,7 +2212,18 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1957,8 +2249,6 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1988,7 +2278,18 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2014,8 +2315,6 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2045,7 +2344,18 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2067,8 +2377,6 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2096,7 +2404,17 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2119,8 +2437,6 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2148,7 +2464,17 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2171,8 +2497,6 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2200,7 +2524,17 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2223,8 +2557,6 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2252,7 +2584,17 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2275,8 +2617,6 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2304,7 +2644,17 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2327,8 +2677,6 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2356,7 +2704,17 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2379,8 +2737,6 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2408,7 +2764,17 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2430,8 +2796,6 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2459,7 +2823,17 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2481,8 +2855,6 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2510,7 +2882,17 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2533,8 +2915,6 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2562,7 +2942,17 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2585,8 +2975,6 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2614,7 +3002,17 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2637,8 +3035,6 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2666,7 +3062,17 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2689,8 +3095,6 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2718,7 +3122,17 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2741,8 +3155,6 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2770,7 +3182,17 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2793,8 +3215,6 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2822,7 +3242,17 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2845,8 +3275,6 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2874,7 +3302,17 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2899,8 +3337,6 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2930,7 +3366,17 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2955,8 +3401,6 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2986,7 +3430,17 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3011,8 +3465,6 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3042,7 +3494,17 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3067,8 +3529,6 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3098,7 +3558,17 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3123,8 +3593,6 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3154,7 +3622,17 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3179,8 +3657,6 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3210,7 +3686,17 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3235,8 +3721,6 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3266,7 +3750,17 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3291,8 +3785,6 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3322,7 +3814,17 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3347,8 +3849,6 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3378,7 +3878,17 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3403,8 +3913,6 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3434,7 +3942,18 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3459,8 +3978,6 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3490,7 +4007,18 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3515,8 +4043,6 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3546,7 +4072,18 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3571,8 +4108,6 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3602,7 +4137,18 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3627,8 +4173,6 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3658,7 +4202,18 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3683,8 +4238,6 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3714,7 +4267,18 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3739,8 +4303,6 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3770,7 +4332,18 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3791,15 +4364,20 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3820,15 +4398,20 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3849,15 +4432,20 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3878,15 +4466,20 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3907,15 +4500,20 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3936,15 +4534,20 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3965,15 +4568,20 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -3994,15 +4602,20 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4023,15 +4636,20 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4052,15 +4670,20 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4081,15 +4704,20 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4110,15 +4738,20 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4139,15 +4772,20 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4168,15 +4806,20 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4197,15 +4840,20 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4226,15 +4874,20 @@ VCmpTruF64Vopc::VCmpTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4257,17 +4910,22 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4290,17 +4948,22 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4323,17 +4986,22 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4356,17 +5024,22 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4389,17 +5062,22 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4422,17 +5100,22 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4455,17 +5138,22 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4488,17 +5176,22 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4521,17 +5214,22 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4554,17 +5252,23 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4587,17 +5291,23 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4620,17 +5330,23 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4653,17 +5369,23 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4686,17 +5408,23 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4719,17 +5447,23 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4752,17 +5486,23 @@ VCmpxTruF64Vopc::VCmpxTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4785,8 +5525,6 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4814,7 +5552,17 @@ VCmpFI16Vopc::VCmpFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i16_sdwa" + : "v_cmp_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4838,8 +5586,6 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4867,7 +5613,17 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4891,8 +5647,6 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4920,7 +5674,17 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4944,8 +5708,6 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4973,7 +5735,17 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4997,8 +5769,6 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5026,7 +5796,17 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5050,8 +5830,6 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5079,7 +5857,17 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5103,8 +5891,6 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5132,7 +5918,17 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5155,8 +5951,6 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5184,7 +5978,17 @@ VCmpTI16Vopc::VCmpTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i16_sdwa" + : "v_cmp_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5207,8 +6011,6 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5236,7 +6038,17 @@ VCmpFU16Vopc::VCmpFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u16_sdwa" + : "v_cmp_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5260,8 +6072,6 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5289,7 +6099,17 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5313,8 +6133,6 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5342,7 +6160,17 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5366,8 +6194,6 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5395,7 +6221,17 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5419,8 +6255,6 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5448,7 +6282,17 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5472,8 +6316,6 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5501,7 +6343,17 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5525,8 +6377,6 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5554,7 +6404,17 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5577,8 +6437,6 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5606,7 +6464,17 @@ VCmpTU16Vopc::VCmpTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u16_sdwa" + : "v_cmp_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5632,8 +6500,6 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5663,7 +6529,17 @@ VCmpxFI16Vopc::VCmpxFI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i16_sdwa" + : "v_cmpx_f_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5689,8 +6565,6 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5720,7 +6594,17 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5746,8 +6630,6 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5777,7 +6659,17 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5803,8 +6695,6 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5834,7 +6724,17 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5860,8 +6760,6 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5891,7 +6789,17 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5917,8 +6825,6 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5948,7 +6854,17 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5974,8 +6890,6 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6005,7 +6919,17 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6031,8 +6955,6 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6062,7 +6984,17 @@ VCmpxTI16Vopc::VCmpxTI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i16_sdwa" + : "v_cmpx_t_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6088,8 +7020,6 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6119,7 +7049,17 @@ VCmpxFU16Vopc::VCmpxFU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u16_sdwa" + : "v_cmpx_f_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6145,8 +7085,6 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6176,7 +7114,17 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6202,8 +7150,6 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6233,7 +7179,17 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6259,8 +7215,6 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6290,7 +7244,17 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6316,8 +7280,6 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6347,7 +7309,17 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6373,8 +7345,6 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6404,7 +7374,17 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6430,8 +7410,6 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6461,7 +7439,17 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6487,8 +7475,6 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6518,7 +7504,17 @@ VCmpxTU16Vopc::VCmpxTU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u16_sdwa" + : "v_cmpx_t_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6540,8 +7536,6 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6569,7 +7563,17 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6592,8 +7596,6 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6621,7 +7623,17 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6644,8 +7656,6 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6673,7 +7683,17 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6696,8 +7716,6 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6725,7 +7743,17 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6748,8 +7776,6 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6777,7 +7803,17 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6800,8 +7836,6 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6829,7 +7863,17 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6852,8 +7896,6 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6881,7 +7923,17 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6903,8 +7955,6 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6932,7 +7982,17 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6954,8 +8014,6 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6983,7 +8041,17 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7006,8 +8074,6 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7035,7 +8101,17 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7058,8 +8134,6 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7087,7 +8161,17 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7110,8 +8194,6 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7139,7 +8221,17 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7162,8 +8254,6 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7191,7 +8281,17 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7214,8 +8314,6 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7243,7 +8341,17 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7266,8 +8374,6 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7295,7 +8401,17 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7317,8 +8433,6 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7346,7 +8460,17 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7371,8 +8495,6 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7402,7 +8524,17 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7427,8 +8559,6 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7458,7 +8588,17 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7483,8 +8623,6 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7514,7 +8652,17 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7539,8 +8687,6 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7570,7 +8716,17 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7595,8 +8751,6 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7626,7 +8780,17 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7651,8 +8815,6 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7682,7 +8844,17 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7707,8 +8879,6 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7738,7 +8908,17 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7763,8 +8943,6 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7794,7 +8972,17 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7819,8 +9007,6 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7850,7 +9036,17 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7875,8 +9071,6 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7906,7 +9100,17 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7931,8 +9135,6 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7962,7 +9164,17 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7987,8 +9199,6 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8018,7 +9228,17 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8043,8 +9263,6 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8074,7 +9292,17 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8099,8 +9327,6 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8130,7 +9356,17 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8155,8 +9391,6 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8186,7 +9420,17 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8211,8 +9455,6 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8242,7 +9484,17 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8263,15 +9515,20 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8292,15 +9549,20 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8321,15 +9583,20 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8350,15 +9617,20 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8379,15 +9651,20 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8408,15 +9685,20 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8437,15 +9719,20 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8466,15 +9753,20 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8495,15 +9787,20 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8524,15 +9821,20 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8553,15 +9855,20 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8582,15 +9889,20 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8611,15 +9923,20 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8640,15 +9957,20 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8669,15 +9991,20 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8698,15 +10025,20 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8729,17 +10061,22 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8762,17 +10099,22 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8795,17 +10137,22 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8828,17 +10175,22 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8861,17 +10213,22 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8894,17 +10251,22 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8927,17 +10289,22 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8960,17 +10327,22 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8993,17 +10365,22 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9026,17 +10403,22 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9059,17 +10441,22 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9092,17 +10479,22 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9125,17 +10517,22 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9158,17 +10555,22 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9191,17 +10593,22 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -9224,17 +10631,22 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.cpp index da13eadf99cd..c948026d9491 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.h" -#include "util/except.h" #include #include #include @@ -16,1642 +15,2270 @@ namespace rocjitsu { namespace cdna5 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddF64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxNumF64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinNumF64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB128Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB96Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB128Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB96Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadAsyncToLdsB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadAsyncToLdsB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadAsyncToLdsB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadAsyncToLdsB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeClusterLoadB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendVds(const MachineInst *opcode); -std::unique_ptr decodeDsAtomicAsyncBarrierArriveB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAtomicBarrierArriveRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteFiB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCondSubRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCondSubU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeVds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadAddtidB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB128Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB96Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadTr16B128Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadTr4B64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadTr6B96Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadTr8B64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumRtnF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumRtnF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumRtnF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumRtnF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsNopVds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddBf16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddF16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnBf16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnF16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreAddtidB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB128Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB96Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubClampRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubClampU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxNumF64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinNumF64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB128Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB96Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16B16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16I8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16U8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadMonitorB128Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadMonitorB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadMonitorB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatPrefetchB8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB128Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB96Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddF64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxNumF64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinNumF64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalInvVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadAsyncToLdsB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadAsyncToLdsB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadAsyncToLdsB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadAsyncToLdsB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB96Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadBlockVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadI16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadI8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadMonitorB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadMonitorB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadMonitorB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadTr16B128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadTr4B64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadTr6B96Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadTr8B64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadU16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadU8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalPrefetchB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreAsyncFromLdsB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreAsyncFromLdsB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreAsyncFromLdsB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreAsyncFromLdsB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB96Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreBlockVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalWbVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalWbinvVglobal(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddCoCiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddCoI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddCoU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddNcU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddPcI64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAddkCoI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAllocVgprSop1(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierInitSop1(const MachineInst *opcode); -std::unique_ptr decodeSBarrierJoinSop1(const MachineInst *opcode); -std::unique_ptr decodeSBarrierLeaveSopp(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSignalSop1(const MachineInst *opcode); -std::unique_ptr decodeSBarrierWaitSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB96Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadI16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadI8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadU16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadU8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferPrefetchDataSmem(const MachineInst *opcode); -std::unique_ptr decodeSCallI64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCeilF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCeilF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode); -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNeqF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNeqF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNleF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNleF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNlgF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNlgF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNltF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNltF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpOF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpOF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpUF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpUF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF16F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32F16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32I32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtHiF32F16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtI32F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCvtU32F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode); -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFloorF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFloorF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFmaakF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmacF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmacF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmamkF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSGetBarrierStateSop1(const MachineInst *opcode); -std::unique_ptr decodeSGetPcI64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetShaderCyclesU64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB96Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadI16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadI8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadU16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadU8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxNumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxNumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaximumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaximumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinNumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinNumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinimumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinimumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMonitorSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchDataPcRelSmem(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchDataSmem(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchInstPcRelSmem(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchInstSmem(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeI64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRndneF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRndneF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetPcI64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetVgprMsbSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetprioIncWgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSSleepVarSop1(const MachineInst *opcode); -std::unique_ptr decodeSSubCoCiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubCoI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubCoU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubNcU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwapPcI64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTruncF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTruncF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitAluSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitAsynccntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitDscntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitKmcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitLoadcntDscntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitLoadcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitStorecntDscntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitStorecntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitTensorcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitXcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWakeupBarrierSop1(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB128Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB32Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB64Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB96Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadBlockVscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16B16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16I8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16U8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadI16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadI8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadU16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadU8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB128Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB32Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB64Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB96Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreBlockVscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeTensorLoadToLdsVimage(const MachineInst *opcode); -std::unique_ptr decodeTensorStoreFromLdsVimage(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrPkI8I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrPkU8I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBitop3B16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBitop3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF16Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF16Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkFp8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk16Bf16Bf6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk16Bf16Fp6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk16F16Bf6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk16F16Fp6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk16F32Bf6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk16F32Fp6Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8Bf16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8Bf16Fp4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8Bf16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8F16Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8F16Fp4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8F16Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8F32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8F32Fp4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalePk8F32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk16Bf6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk16Bf6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk16Bf6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk16Fp6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk16Fp6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk16Fp6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Bf8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Bf8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Bf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Fp4Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Fp4F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Fp4F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Fp8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Fp8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32Pk8Fp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrBf8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrFp8F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrPkBf16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrPkF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVExpBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadNcI64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadNcU64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3NumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3NumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximum3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximum3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumminimumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumminimumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3NumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3NumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3NumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3NumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimum3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimum3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimummaximumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimummaximumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermPk16B4U4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermPk16B6U4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermPk16B8U4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16SwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16SwapB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16VarB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlaneBcastB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlaneDownB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlaneIdxGenB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlaneUpB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlaneXorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16VarB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMax3I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMax3NumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMax3U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxNumBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxNumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaximum3F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaximumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMin3I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMin3NumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMin3U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinNumBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinNumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinimum3F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinimumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulBf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPrngB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPrngB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPk4I4I8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPk4I4I8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPk4U4U8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPk4U4U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacBf16f3216x16x64Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF1616x16x64F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x64Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x64F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacI3216x16x128Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVTanhBf16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTanhBf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTanhF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTanhF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTanhF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTanhF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWmmaBf1616x16x32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x4F32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3232x16x128F4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x64Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddF64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxNumF64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinNumF64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadAsyncToLdsB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadAsyncToLdsB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadAsyncToLdsB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadAsyncToLdsB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeClusterLoadB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAtomicAsyncBarrierArriveB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAtomicBarrierArriveRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteFiB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondSubRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondSubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadTr16B128Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadTr4B64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadTr6B96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadTr8B64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddBf16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddF16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnBf16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnF16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubClampRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubClampU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxNumF64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinNumF64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16B16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16I8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16U8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI8Vflat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadMonitorB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadMonitorB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadMonitorB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU8Vflat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatPrefetchB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddF64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxNumF64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinNumF64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalInvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadAsyncToLdsB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadAsyncToLdsB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadAsyncToLdsB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadAsyncToLdsB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadI16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadMonitorB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadMonitorB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadMonitorB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadTr16B128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadTr4B64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadTr6B96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadTr8B64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadU16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalPrefetchB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreAsyncFromLdsB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreAsyncFromLdsB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreAsyncFromLdsB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreAsyncFromLdsB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalWbVglobal(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalWbinvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddCoCiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkCoI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAllocVgprSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierInitSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierLeaveSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSignalSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierWaitSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB96Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadI16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadI8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadU16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadU8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallI64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCeilF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCeilF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNeqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNeqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNleF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNleF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNlgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNlgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNltF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNltF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpOF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpOF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpUF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpUF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF16F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32F16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32I32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtHiF32F16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtI32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtU32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFloorF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFloorF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmaakF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmacF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmacF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmamkF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetBarrierStateSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetShaderCyclesU64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB96Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadI16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadI8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadU16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadU8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaximumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaximumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinimumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinimumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMonitorSleepSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchDataPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchInstPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchInstSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRndneF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRndneF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetVgprMsbSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioIncWgSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepVarSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubCoCiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwapPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTruncF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTruncF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitAsynccntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitDscntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitKmcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitLoadcntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitLoadcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitStorecntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitStorecntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitTensorcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitXcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupBarrierSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16B16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16I8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16U8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadI16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadU16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTensorLoadToLdsVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTensorStoreFromLdsVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrPkI8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrPkU8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBitop3B16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBitop3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF16Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF16Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk16Bf16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk16Bf16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk16F16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk16F16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk16F32Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk16F32Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8Bf16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8Bf16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8Bf16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8F16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8F16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8F16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8F32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8F32Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalePk8F32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk16Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk16Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk16Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk16Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk16Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk16Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Bf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Bf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Bf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Fp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Fp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Fp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Fp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Fp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32Pk8Fp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrPkBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrPkF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadNcI64I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadNcU64U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3NumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3NumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumminimumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumminimumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3NumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3NumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3NumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3NumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimummaximumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimummaximumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermPk16B4U4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermPk16B6U4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermPk16B8U4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16SwapB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16SwapB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlaneBcastB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlaneDownB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlaneIdxGenB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlaneUpB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlaneXorB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddBf16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddMaxI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddMaxU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddMinI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddMinU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaBf16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMax3I16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMax3NumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMax3U16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxNumBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaximum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaximumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMin3I16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMin3NumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMin3U16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinNumBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinimum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinimumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulBf16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPrngB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPrngB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPk4I4I8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPk4I4I8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPk4U4U8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPk4U4U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacBf16f3216x16x64Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF1616x16x64F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x64Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x64F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacI3216x16x128Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTanhBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTanhBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTanhF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTanhF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTanhF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTanhF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaBf1616x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x4F32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3232x16x128F4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x64Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr decodeVopd(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeVbuffer(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr decodeVWmmaScaleF32Vop3px2(const MachineInst *opcode); - static std::unique_ptr subDecodeVimage(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeVds(const MachineInst *opcode); - static std::unique_ptr subDecodeVflat(const MachineInst *opcode); - static std::unique_ptr subDecodeVscratch(const MachineInst *opcode); - static std::unique_ptr subDecodeVglobal(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult decodeVopd(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult decodeVWmmaScaleF32Vop3px2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1677,98 +2304,117 @@ bool isVop3pOp(const MachineInst opcode, uint32_t op) { } // namespace -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::decodeVopd(const MachineInst *opcode) { +DecodeResult DecoderImpl::decodeVopd(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vopd::validate_encoding(opcode, emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVbuffer(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vbuffer::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vbuffer[op.op](opcode); + return sub_decode_vbuffer[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeVWmmaScaleF32Vop3px2(const MachineInst *opcode) { +DecodeResult DecoderImpl::decodeVWmmaScaleF32Vop3px2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { if (!isVop3pOp(opcode[2], 0x33) && !isVop3pOp(opcode[2], 0x88)) - return decodeInvalid(opcode); + return decodeInvalid(opcode, emit_error); return std::make_unique(opcode); } -std::unique_ptr DecoderImpl::subDecodeVimage(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vimage::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vimage[op.op](opcode); + return sub_decode_vimage[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVds(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vds[op.op](opcode); + return sub_decode_vds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVflat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vflat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vflat[op.op](opcode); + return sub_decode_vflat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVscratch(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vscratch::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vscratch[op.op](opcode); + return sub_decode_vscratch[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVglobal(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vglobal::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vglobal[op.op](opcode); + return sub_decode_vglobal[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h index 984a4d721cdc..8ec16fb24d64 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_CDNA5_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace cdna5 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 4; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace cdna5 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp index eb7033bdca4d..c0cab68d9137 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.cpp @@ -5,7 +5,6 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h" -#include "util/except.h" #include #include @@ -176,19 +175,12 @@ bool Sop1::has_encoded_literal32() const { } } -Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Sop1::Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.ssrc0 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.ssrc0 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); else if (has_encoded_literal32()) @@ -311,21 +303,12 @@ bool Sopc::has_encoded_literal32() const { } } -Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Sopc::Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.ssrc0 == 255) || - (num_encoded_sources > 1 && inst_.ssrc1 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.ssrc0 == 254) || - (num_encoded_sources > 1 && inst_.ssrc1 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); else if (has_encoded_literal32()) @@ -558,21 +541,12 @@ bool Sop2::has_encoded_literal32() const { } } -Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Sop2::Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.ssrc0 == 255) || - (num_encoded_sources > 1 && inst_.ssrc1 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.ssrc0 == 254) || - (num_encoded_sources > 1 && inst_.ssrc1 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); else if (has_encoded_literal32() || hasImpliedLiteral()) @@ -844,19 +818,12 @@ bool Vop1::has_encoded_literal32() const { } } -Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Vop1::Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.src0 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.src0 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); else if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || @@ -1252,19 +1219,12 @@ bool Vopc::has_encoded_literal32() const { } } -Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Vopc::Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.src0 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.src0 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (has_encoded_literal64()) size_ += 2 * sizeof(MachineInst); else if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0) || @@ -1418,19 +1378,12 @@ bool Vop2::has_encoded_literal32() const { } } -Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Vop2::Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.src0 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.src0 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); if (hasImpliedLiteral()) size_ += impliedLiteralWordCount() * sizeof(MachineInst); else if (hasImpliedLiteral64() || has_encoded_literal64()) @@ -2042,26 +1995,12 @@ bool Vop3::has_encoded_literal32() const { } } -Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources) +Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.src0 == 255) || - (num_encoded_sources > 1 && inst_.src1 == 255) || - (num_encoded_sources > 2 && inst_.src2 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.src0 == 254) || - (num_encoded_sources > 1 && inst_.src1 == 254) || - (num_encoded_sources > 2 && inst_.src2 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -2202,7 +2141,6 @@ bool Vop3p::has_encoded_literal32() const { } Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support, int num_encoded_sources, ExtensionDecodePolicy extension_policy) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); @@ -2210,23 +2148,6 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; if (extension_policy == ExtensionDecodePolicy::Decode) { - if ((num_encoded_sources > 0 && inst_.src0 == 254) || - (num_encoded_sources > 1 && inst_.src1 == 254) || - (num_encoded_sources > 2 && inst_.src2 == 254)) - throw util::InvalidInst("Vop3p does not support Literal64", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.src0 == 255) || - (num_encoded_sources > 1 && inst_.src1 == 255) || - (num_encoded_sources > 2 && inst_.src2 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.src0 == 254) || - (num_encoded_sources > 1 && inst_.src1 == 254) || - (num_encoded_sources > 2 && inst_.src2 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -2409,25 +2330,12 @@ bool Vop3SdstEnc::has_encoded_literal32() const { } Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, - ExecuteFn exec_fn, LiteralSupport literal_support, int num_encoded_sources) + ExecuteFn exec_fn) : IsaInstruction(mnemonic, exec_fn), inst_(*inst) { size_ = sizeof(OpEncoding); raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if (!supports_literal(literal_support, LiteralSupport::Literal32) && - ((num_encoded_sources > 0 && inst_.src0 == 255) || - (num_encoded_sources > 1 && inst_.src1 == 255) || - (num_encoded_sources > 2 && inst_.src2 == 255))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 32-bit literals", ""); - if (!supports_literal(literal_support, LiteralSupport::Literal64) && - ((num_encoded_sources > 0 && inst_.src0 == 254) || - (num_encoded_sources > 1 && inst_.src1 == 254) || - (num_encoded_sources > 2 && inst_.src2 == 254))) - throw util::InvalidInst(std::string(mnemonic) + " does not support 64-bit literals", ""); - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h index 72a758545e66..4f8fa959337c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna5/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include @@ -378,10 +379,23 @@ enum class LiteralSupport : uint8_t { class Sop1 : public IsaInstruction { public: - Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + Sop1(std::string_view mnemonic, const Sop1MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal64() const; bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Sop1MachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 1) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.ssrc0 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.ssrc0 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + return Result::success(); + } bool default_encoding(); bool has_lit_0(); bool has_lit64_0(); @@ -392,10 +406,25 @@ class Sop1 : public IsaInstruction { class Sopc : public IsaInstruction { public: - Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 2); + Sopc(std::string_view mnemonic, const SopcMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal64() const; bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const SopcMachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 2) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.ssrc0 == 255) || + (num_encoded_sources > 1 && inst_.ssrc1 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.ssrc0 == 254) || + (num_encoded_sources > 1 && inst_.ssrc1 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + return Result::success(); + } bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -429,10 +458,25 @@ class Sopk : public IsaInstruction { class Sop2 : public IsaInstruction { public: - Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 2); + Sop2(std::string_view mnemonic, const Sop2MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal64() const; bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Sop2MachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 2) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.ssrc0 == 255) || + (num_encoded_sources > 1 && inst_.ssrc1 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.ssrc0 == 254) || + (num_encoded_sources > 1 && inst_.ssrc1 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + return Result::success(); + } bool default_encoding(); bool has_lit_0(); bool has_lit_1(); @@ -457,10 +501,23 @@ class Smem : public IsaInstruction { class Vop1 : public IsaInstruction { public: - Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + Vop1(std::string_view mnemonic, const Vop1MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal64() const; bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop1MachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 1) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.src0 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.src0 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -495,10 +552,23 @@ class Vop1 : public IsaInstruction { class Vopc : public IsaInstruction { public: - Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + Vopc(std::string_view mnemonic, const VopcMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal64() const; bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const VopcMachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 1) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.src0 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.src0 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + return Result::success(); + } void build_modifiers(std::string &out) const override; bool default_encoding(); bool has_lit(); @@ -530,10 +600,23 @@ class Vopc : public IsaInstruction { class Vop2 : public IsaInstruction { public: - Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 1); + Vop2(std::string_view mnemonic, const Vop2MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal64() const; bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop2MachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 1) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.src0 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.src0 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -572,9 +655,29 @@ class Vop2 : public IsaInstruction { class Vop3 : public IsaInstruction { public: - Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 3); + Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3MachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 3) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.src0 == 255) || + (num_encoded_sources > 1 && inst_.src1 == 255) || + (num_encoded_sources > 2 && inst_.src2 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.src0 == 254) || + (num_encoded_sources > 1 && inst_.src1 == 254) || + (num_encoded_sources > 2 && inst_.src2 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -604,9 +707,36 @@ class Vop3p : public IsaInstruction { public: enum class ExtensionDecodePolicy { Decode, Skip }; Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 3, ExtensionDecodePolicy extension_policy = ExtensionDecodePolicy::Decode); bool has_encoded_literal32() const; + static Result + validate_encoding([[maybe_unused]] std::string_view mnemonic, const Vop3pMachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 3, + ExtensionDecodePolicy extension_policy = ExtensionDecodePolicy::Decode) { + const auto &inst_ = *inst; + if (extension_policy == ExtensionDecodePolicy::Decode) { + if ((num_encoded_sources > 0 && inst_.src0 == 254) || + (num_encoded_sources > 1 && inst_.src1 == 254) || + (num_encoded_sources > 2 && inst_.src2 == 254)) [[unlikely]] + return emit_error.emit() << "Vop3p does not support Literal64"; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.src0 == 255) || + (num_encoded_sources > 1 && inst_.src1 == 255) || + (num_encoded_sources > 2 && inst_.src2 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.src0 == 254) || + (num_encoded_sources > 1 && inst_.src1 == 254) || + (num_encoded_sources > 2 && inst_.src2 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + } + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; @@ -680,9 +810,29 @@ class Vglobal : public IsaInstruction { class Vop3SdstEnc : public IsaInstruction { public: - Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn, - LiteralSupport literal_support = LiteralSupport::Both, int num_encoded_sources = 3); + Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3SdstEncMachineInst *inst, + const util::DiagnosticEmitter &emit_error, + LiteralSupport literal_support = LiteralSupport::Both, + int num_encoded_sources = 3) { + const auto &inst_ = *inst; + if (!supports_literal(literal_support, LiteralSupport::Literal32) && + ((num_encoded_sources > 0 && inst_.src0 == 255) || + (num_encoded_sources > 1 && inst_.src1 == 255) || + (num_encoded_sources > 2 && inst_.src2 == 255))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 32-bit literals"; + if (!supports_literal(literal_support, LiteralSupport::Literal64) && + ((num_encoded_sources > 0 && inst_.src0 == 254) || + (num_encoded_sources > 1 && inst_.src1 == 254) || + (num_encoded_sources > 2 && inst_.src2 == 254))) [[unlikely]] + return emit_error.emit() << mnemonic << " does not support 64-bit literals"; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; void implicit_use_operands(std::vector &operands) const override; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp index 0ae1f82257a8..d5d6482fa9ca 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem.cpp index 76980d528221..25d611e835fa 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SLoadB32Smem::SLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -60,7 +63,11 @@ SLoadB64Smem::SLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +90,11 @@ SLoadB128Smem::SLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +117,11 @@ SLoadB256Smem::SLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SLoadB512Smem::SLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -152,7 +171,11 @@ SLoadB96Smem::SLoadB96Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB96Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB96Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +198,11 @@ SLoadI8Smem::SLoadI8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadI8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadI8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -198,7 +225,11 @@ SLoadU8Smem::SLoadU8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadU8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadU8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +252,11 @@ SLoadI16Smem::SLoadI16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadI16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadI16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -244,7 +279,11 @@ SLoadU16Smem::SLoadU16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadU16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadU16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -267,7 +306,12 @@ SBufferLoadB32Smem::SBufferLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +334,12 @@ SBufferLoadB64Smem::SBufferLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +362,12 @@ SBufferLoadB128Smem::SBufferLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +390,12 @@ SBufferLoadB256Smem::SBufferLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +418,12 @@ SBufferLoadB512Smem::SBufferLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -382,7 +446,12 @@ SBufferLoadB96Smem::SBufferLoadB96Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB96Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB96Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +474,12 @@ SBufferLoadI8Smem::SBufferLoadI8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadI8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadI8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +502,12 @@ SBufferLoadU8Smem::SBufferLoadU8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadU8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadU8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +530,12 @@ SBufferLoadI16Smem::SBufferLoadI16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadI16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadI16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -474,7 +558,12 @@ SBufferLoadU16Smem::SBufferLoadU16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadU16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadU16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +576,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -506,7 +599,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,7 +622,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -546,7 +648,12 @@ SPrefetchInstSmem::SPrefetchInstSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchInstSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchInstSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_inst", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -565,7 +672,12 @@ SPrefetchInstPcRelSmem::SPrefetchInstPcRelSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchInstPcRelSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchInstPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_inst_pc_rel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +698,12 @@ SPrefetchDataSmem::SPrefetchDataSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchDataSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_data", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -607,7 +724,12 @@ SBufferPrefetchDataSmem::SBufferPrefetchDataSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferPrefetchDataSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_prefetch_data", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +748,12 @@ SPrefetchDataPcRelSmem::SPrefetchDataPcRelSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchDataPcRelSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchDataPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_data_pc_rel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1.cpp index 6a1f302593e5..d48ef9ea52ce 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -36,7 +35,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +69,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -99,7 +106,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -133,7 +144,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +176,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,15 +209,18 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SGetShaderCyclesU64Sop1::SGetShaderCyclesU64Sop1(const MachineInst *inst) : Sop1("s_get_shader_cycles_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SGetShaderCyclesU64Sop1), LiteralSupport::None, - 0), + selected_exec_fn(InstructionExecutionId::SGetShaderCyclesU64Sop1)), sdst(64, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst) { dst_operands_[0] = &sdst; num_src_ = 0; @@ -206,7 +228,13 @@ SGetShaderCyclesU64Sop1::SGetShaderCyclesU64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetShaderCyclesU64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetShaderCyclesU64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_get_shader_cycles_u64", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +262,11 @@ SCtzI32B32Sop1::SCtzI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -263,7 +295,11 @@ SCtzI32B64Sop1::SCtzI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -291,7 +327,11 @@ SClzI32U32Sop1::SClzI32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -320,7 +360,11 @@ SClzI32U64Sop1::SClzI32U64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -348,7 +392,11 @@ SClsI32Sop1::SClsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -377,7 +425,11 @@ SClsI32I64Sop1::SClsI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +457,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -434,7 +490,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -463,7 +524,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -492,7 +558,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +592,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -550,7 +626,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -578,7 +659,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -609,7 +695,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,7 +730,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -672,7 +767,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -703,7 +803,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -735,7 +840,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -766,7 +876,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -798,7 +913,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -829,7 +949,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -861,7 +985,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -892,7 +1020,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1056,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -962,7 +1098,12 @@ SAndSaveexecB32Sop1::SAndSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1001,7 +1142,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1186,12 @@ SOrSaveexecB32Sop1::SOrSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1080,7 +1231,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1118,7 +1274,12 @@ SXorSaveexecB32Sop1::SXorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1157,7 +1318,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1195,7 +1361,12 @@ SNandSaveexecB32Sop1::SNandSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1234,7 +1405,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1272,7 +1448,12 @@ SNorSaveexecB32Sop1::SNorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1311,7 +1492,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1535,12 @@ SXnorSaveexecB32Sop1::SXnorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1388,7 +1579,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1426,7 +1622,12 @@ SAndNot0SaveexecB32Sop1::SAndNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1465,7 +1666,12 @@ SAndNot0SaveexecB64Sop1::SAndNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,7 +1709,12 @@ SOrNot0SaveexecB32Sop1::SOrNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1542,7 +1753,12 @@ SOrNot0SaveexecB64Sop1::SOrNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1580,7 +1796,12 @@ SAndNot1SaveexecB32Sop1::SAndNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1619,7 +1840,12 @@ SAndNot1SaveexecB64Sop1::SAndNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1657,7 +1883,12 @@ SOrNot1SaveexecB32Sop1::SOrNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1696,7 +1927,12 @@ SOrNot1SaveexecB64Sop1::SOrNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1734,7 +1970,12 @@ SAndNot0WrexecB32Sop1::SAndNot0WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1773,7 +2014,12 @@ SAndNot0WrexecB64Sop1::SAndNot0WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1811,7 +2057,12 @@ SAndNot1WrexecB32Sop1::SAndNot1WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1850,14 +2101,19 @@ SAndNot1WrexecB64Sop1::SAndNot1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) : Sop1("s_movrels_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SMovrelsB32Sop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SMovrelsB32Sop1)), sdst(32, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SREG, reinterpret_cast(inst)->ssrc0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -1870,14 +2126,20 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_movrels_b32", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) : Sop1("s_movrels_b64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SMovrelsB64Sop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SMovrelsB64Sop1)), sdst(64, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(64, OperandType::OPR_SREG, reinterpret_cast(inst)->ssrc0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -1890,7 +2152,13 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_movrels_b64", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1921,7 +2189,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1953,14 +2226,19 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) : Sop1("s_movrelsd_2_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SMovrelsd2B32Sop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SMovrelsd2B32Sop1)), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SREG, reinterpret_cast(inst)->ssrc0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -1973,14 +2251,20 @@ SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_movrelsd_2_b32", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SGetPcI64Sop1::SGetPcI64Sop1(const MachineInst *inst) : Sop1("s_get_pc_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SGetPcI64Sop1), LiteralSupport::None, 0), + selected_exec_fn(InstructionExecutionId::SGetPcI64Sop1)), sdst(64, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), pc(64, OperandType::OPR_PC, 0) { dst_operands_[0] = &sdst; @@ -1991,14 +2275,19 @@ SGetPcI64Sop1::SGetPcI64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetPcI64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_get_pc_i64", reinterpret_cast(opcode), + emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SSetPcI64Sop1::SSetPcI64Sop1(const MachineInst *inst) : Sop1("s_set_pc_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SSetPcI64Sop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SSetPcI64Sop1)), ssrc0(64, OperandType::OPR_SREG, reinterpret_cast(inst)->ssrc0), pc(64, OperandType::OPR_PC, 0) { src_operands_[0] = &ssrc0; @@ -2010,14 +2299,19 @@ SSetPcI64Sop1::SSetPcI64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetPcI64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_set_pc_i64", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SSwapPcI64Sop1::SSwapPcI64Sop1(const MachineInst *inst) : Sop1("s_swap_pc_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SSwapPcI64Sop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SSwapPcI64Sop1)), sdst(64, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(64, OperandType::OPR_SREG, reinterpret_cast(inst)->ssrc0), pc(64, OperandType::OPR_PC, 0), pc_in(64, OperandType::OPR_PC, 0) { @@ -2033,14 +2327,19 @@ SSwapPcI64Sop1::SSwapPcI64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwapPcI64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwapPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_swap_pc_i64", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SRfeI64Sop1::SRfeI64Sop1(const MachineInst *inst) : Sop1("s_rfe_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SRfeI64Sop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SRfeI64Sop1)), ssrc0(64, OperandType::OPR_SREG, reinterpret_cast(inst)->ssrc0), pc(64, OperandType::OPR_PC, 0) { src_operands_[0] = &ssrc0; @@ -2051,7 +2350,12 @@ SRfeI64Sop1::SRfeI64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeI64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_rfe_i64", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2082,14 +2386,18 @@ SAddPcI64Sop1::SAddPcI64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddPcI64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAddPcI64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_add_pc_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SSendmsgRtnB32Sop1::SSendmsgRtnB32Sop1(const MachineInst *inst) : Sop1("s_sendmsg_rtn_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SSendmsgRtnB32Sop1), LiteralSupport::None, 0), + selected_exec_fn(InstructionExecutionId::SSendmsgRtnB32Sop1)), sdst(32, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SENDMSG_RTN, reinterpret_cast(inst)->ssrc0) { dst_operands_[0] = &sdst; @@ -2099,14 +2407,20 @@ SSendmsgRtnB32Sop1::SSendmsgRtnB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_sendmsg_rtn_b32", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SSendmsgRtnB64Sop1::SSendmsgRtnB64Sop1(const MachineInst *inst) : Sop1("s_sendmsg_rtn_b64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SSendmsgRtnB64Sop1), LiteralSupport::None, 0), + selected_exec_fn(InstructionExecutionId::SSendmsgRtnB64Sop1)), sdst(64, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SENDMSG_RTN, reinterpret_cast(inst)->ssrc0) { dst_operands_[0] = &sdst; @@ -2116,14 +2430,20 @@ SSendmsgRtnB64Sop1::SSendmsgRtnB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_sendmsg_rtn_b64", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SBarrierSignalSop1::SBarrierSignalSop1(const MachineInst *inst) : Sop1("s_barrier_signal", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SBarrierSignalSop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SBarrierSignalSop1)), ssrc0(32, OperandType::OPR_SSRC_BARRIER_ID, reinterpret_cast(inst)->ssrc0) { src_operands_[0] = &ssrc0; @@ -2133,15 +2453,20 @@ SBarrierSignalSop1::SBarrierSignalSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSignalSop1(const MachineInst *opcode) { +DecodeResult decodeSBarrierSignalSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_barrier_signal", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SBarrierSignalIsfirstSop1::SBarrierSignalIsfirstSop1(const MachineInst *inst) : Sop1("s_barrier_signal_isfirst", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SBarrierSignalIsfirstSop1), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SBarrierSignalIsfirstSop1)), ssrc0(32, OperandType::OPR_SSRC_BARRIER_ID, reinterpret_cast(inst)->ssrc0), scc(1, OperandType::OPR_SSRC_SPECIAL_SCC, 253) { @@ -2153,14 +2478,20 @@ SBarrierSignalIsfirstSop1::SBarrierSignalIsfirstSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode) { +DecodeResult decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_barrier_signal_isfirst", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SGetBarrierStateSop1::SGetBarrierStateSop1(const MachineInst *inst) : Sop1("s_get_barrier_state", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SGetBarrierStateSop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SGetBarrierStateSop1)), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SSRC_BARRIER_ID, reinterpret_cast(inst)->ssrc0) { @@ -2171,14 +2502,20 @@ SGetBarrierStateSop1::SGetBarrierStateSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetBarrierStateSop1(const MachineInst *opcode) { +DecodeResult decodeSGetBarrierStateSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_get_barrier_state", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SBarrierInitSop1::SBarrierInitSop1(const MachineInst *inst) : Sop1("s_barrier_init", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SBarrierInitSop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SBarrierInitSop1)), ssrc0(32, OperandType::OPR_SSRC_BARRIER_ID, reinterpret_cast(inst)->ssrc0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -2190,14 +2527,20 @@ SBarrierInitSop1::SBarrierInitSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierInitSop1(const MachineInst *opcode) { +DecodeResult decodeSBarrierInitSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_barrier_init", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SBarrierJoinSop1::SBarrierJoinSop1(const MachineInst *inst) : Sop1("s_barrier_join", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SBarrierJoinSop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SBarrierJoinSop1)), ssrc0(32, OperandType::OPR_SSRC_BARRIER_ID, reinterpret_cast(inst)->ssrc0) { src_operands_[0] = &ssrc0; @@ -2206,7 +2549,13 @@ SBarrierJoinSop1::SBarrierJoinSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierJoinSop1(const MachineInst *opcode) { +DecodeResult decodeSBarrierJoinSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Sop1::validate_encoding("s_barrier_join", reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2235,14 +2584,18 @@ SAllocVgprSop1::SAllocVgprSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAllocVgprSop1(const MachineInst *opcode) { +DecodeResult decodeSAllocVgprSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_alloc_vgpr", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SWakeupBarrierSop1::SWakeupBarrierSop1(const MachineInst *inst) : Sop1("s_wakeup_barrier", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SWakeupBarrierSop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::SWakeupBarrierSop1)), ssrc0(32, OperandType::OPR_SSRC_BARRIER_ID, reinterpret_cast(inst)->ssrc0) { src_operands_[0] = &ssrc0; @@ -2251,7 +2604,13 @@ SWakeupBarrierSop1::SWakeupBarrierSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupBarrierSop1(const MachineInst *opcode) { +DecodeResult decodeSWakeupBarrierSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding("s_wakeup_barrier", + reinterpret_cast(opcode), + emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2277,7 +2636,11 @@ SSleepVarSop1::SSleepVarSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepVarSop1(const MachineInst *opcode) { +DecodeResult decodeSSleepVarSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sleep_var", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2305,7 +2668,11 @@ SCeilF32Sop1::SCeilF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCeilF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCeilF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2333,7 +2700,11 @@ SFloorF32Sop1::SFloorF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFloorF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFloorF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2361,7 +2732,11 @@ STruncF32Sop1::STruncF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTruncF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSTruncF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2389,7 +2764,11 @@ SRndneF32Sop1::SRndneF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRndneF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSRndneF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2417,7 +2796,11 @@ SCvtF32I32Sop1::SCvtF32I32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32I32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32I32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2445,7 +2828,11 @@ SCvtF32U32Sop1::SCvtF32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2473,7 +2860,11 @@ SCvtI32F32Sop1::SCvtI32F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtI32F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtI32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2501,7 +2892,11 @@ SCvtU32F32Sop1::SCvtU32F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtU32F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtU32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2529,7 +2924,11 @@ SCvtF16F32Sop1::SCvtF16F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF16F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF16F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2571,7 +2970,11 @@ SCvtF32F16Sop1::SCvtF32F16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32F16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32F16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2600,7 +3003,12 @@ SCvtHiF32F16Sop1::SCvtHiF32F16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtHiF32F16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtHiF32F16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_hi_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2629,7 +3037,11 @@ SCeilF16Sop1::SCeilF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCeilF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCeilF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2670,7 +3082,11 @@ SFloorF16Sop1::SFloorF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFloorF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSFloorF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2712,7 +3128,11 @@ STruncF16Sop1::STruncF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTruncF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSTruncF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2754,7 +3174,11 @@ SRndneF16Sop1::SRndneF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRndneF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSRndneF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop2.cpp index ba87047125e8..b6738f1169cf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -25,11 +24,6 @@ SAddCoU32Sop2::SAddCoU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ADD_CO_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -56,7 +50,17 @@ SAddCoU32Sop2::SAddCoU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddCoU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ADD_CO_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -74,11 +78,6 @@ SSubCoU32Sop2::SSubCoU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_SUB_CO_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -105,7 +104,17 @@ SSubCoU32Sop2::SSubCoU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubCoU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_SUB_CO_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -123,11 +132,6 @@ SAddCoI32Sop2::SAddCoI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ADD_CO_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -154,7 +158,17 @@ SAddCoI32Sop2::SAddCoI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddCoI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_add_co_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ADD_CO_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -172,11 +186,6 @@ SSubCoI32Sop2::SSubCoI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_SUB_CO_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -203,7 +212,17 @@ SSubCoI32Sop2::SSubCoI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubCoI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_sub_co_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_SUB_CO_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -223,11 +242,6 @@ SAddCoCiU32Sop2::SAddCoCiU32Sop2(const MachineInst *inst) src_operands_[2] = &scc_in; num_src_ = 3; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ADD_CO_CI_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -255,7 +269,18 @@ SAddCoCiU32Sop2::SAddCoCiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddCoCiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddCoCiU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_add_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ADD_CO_CI_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -275,11 +300,6 @@ SSubCoCiU32Sop2::SSubCoCiU32Sop2(const MachineInst *inst) src_operands_[2] = &scc_in; num_src_ = 3; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_SUB_CO_CI_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -307,7 +327,18 @@ SSubCoCiU32Sop2::SSubCoCiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubCoCiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubCoCiU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_sub_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_SUB_CO_CI_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -325,11 +356,6 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ABSDIFF_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -356,7 +382,18 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ABSDIFF_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -374,11 +411,6 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHL_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -405,7 +437,17 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHL_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -423,11 +465,6 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHL_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -455,7 +492,17 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHL_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -473,11 +520,6 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHR_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -504,7 +546,17 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHR_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -522,11 +574,6 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHR_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -554,7 +601,17 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHR_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -572,11 +629,6 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ASHR_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -603,7 +655,17 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ASHR_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -621,11 +683,6 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ASHR_I64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -653,7 +710,17 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ASHR_I64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -671,11 +738,6 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHL1_ADD_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -702,7 +764,18 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHL1_ADD_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -720,11 +793,6 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHL2_ADD_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -751,7 +819,18 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHL2_ADD_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -769,11 +848,6 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHL3_ADD_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -800,7 +874,18 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHL3_ADD_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -818,11 +903,6 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_LSHL4_ADD_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -849,7 +929,18 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_LSHL4_ADD_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -867,11 +958,6 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MIN_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -898,7 +984,17 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MIN_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -916,11 +1012,6 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MIN_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -947,7 +1038,17 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MIN_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -965,11 +1066,6 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MAX_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -996,7 +1092,17 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MAX_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1014,11 +1120,6 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MAX_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1045,7 +1146,17 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MAX_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1063,11 +1174,6 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_AND_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1094,7 +1200,17 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_AND_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1112,11 +1228,6 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_AND_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1145,7 +1256,17 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_AND_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1163,11 +1284,6 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_OR_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1195,7 +1311,17 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_OR_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1213,11 +1339,6 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_OR_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1247,7 +1368,17 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_OR_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1265,11 +1396,6 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_XOR_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1296,7 +1422,17 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_XOR_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1314,11 +1450,6 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_XOR_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1347,7 +1478,17 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_XOR_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1365,11 +1506,6 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_NAND_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1396,7 +1532,17 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_NAND_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1414,11 +1560,6 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_NAND_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1447,7 +1588,17 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_NAND_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1465,11 +1616,6 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_NOR_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1496,7 +1642,17 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_NOR_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1514,11 +1670,6 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_NOR_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1547,7 +1698,17 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_NOR_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1565,11 +1726,6 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_XNOR_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1596,7 +1752,17 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_XNOR_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1614,11 +1780,6 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_XNOR_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1647,7 +1808,17 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_XNOR_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1665,11 +1836,6 @@ SAndNot1B32Sop2::SAndNot1B32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_AND_NOT1_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1696,7 +1862,18 @@ SAndNot1B32Sop2::SAndNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_and_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_AND_NOT1_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1714,11 +1891,6 @@ SAndNot1B64Sop2::SAndNot1B64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_AND_NOT1_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1747,7 +1919,18 @@ SAndNot1B64Sop2::SAndNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_and_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_AND_NOT1_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1765,11 +1948,6 @@ SOrNot1B32Sop2::SOrNot1B32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_OR_NOT1_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1796,7 +1974,17 @@ SOrNot1B32Sop2::SOrNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_or_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_OR_NOT1_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1814,11 +2002,6 @@ SOrNot1B64Sop2::SOrNot1B64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_OR_NOT1_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1847,7 +2030,17 @@ SOrNot1B64Sop2::SOrNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_or_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_OR_NOT1_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1865,11 +2058,6 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BFE_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1896,7 +2084,17 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BFE_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1914,11 +2112,6 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BFE_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1945,7 +2138,17 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BFE_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1963,11 +2166,6 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BFE_U64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -1995,7 +2193,17 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BFE_U64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2013,11 +2221,6 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) dst_operands_[1] = &scc; num_src_ = 2; num_dst_ = 2; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BFE_I64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -2045,7 +2248,17 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BFE_I64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2061,11 +2274,6 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BFM_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2091,7 +2299,17 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BFM_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2107,11 +2325,6 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BFM_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2137,7 +2350,17 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BFM_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2153,11 +2376,6 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MUL_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2183,7 +2401,17 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MUL_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2199,11 +2427,6 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MUL_HI_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2229,7 +2452,17 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MUL_HI_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2245,11 +2478,6 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MUL_HI_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2275,7 +2503,17 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MUL_HI_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2293,11 +2531,6 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) src_operands_[2] = &scc; num_src_ = 3; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CSELECT_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2324,7 +2557,18 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CSELECT_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2342,11 +2586,6 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) src_operands_[2] = &scc; num_src_ = 3; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CSELECT_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -2375,7 +2614,18 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CSELECT_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2391,11 +2641,6 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_PACK_LL_B32_B16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -2423,7 +2668,18 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_PACK_LL_B32_B16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2439,11 +2695,6 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_PACK_LH_B32_B16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -2470,7 +2721,18 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_PACK_LH_B32_B16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2486,11 +2748,6 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_PACK_HH_B32_B16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2516,7 +2773,18 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_PACK_HH_B32_B16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2532,11 +2800,6 @@ SPackHlB32B16Sop2::SPackHlB32B16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_PACK_HL_B32_B16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2563,7 +2826,18 @@ SPackHlB32B16Sop2::SPackHlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_pack_hl_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_PACK_HL_B32_B16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2579,11 +2853,6 @@ SAddF32Sop2::SAddF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ADD_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2609,7 +2878,17 @@ SAddF32Sop2::SAddF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ADD_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2625,11 +2904,6 @@ SSubF32Sop2::SSubF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_SUB_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2655,7 +2929,17 @@ SSubF32Sop2::SSubF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_SUB_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2671,11 +2955,6 @@ SMinNumF32Sop2::SMinNumF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MIN_NUM_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2701,7 +2980,17 @@ SMinNumF32Sop2::SMinNumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinNumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_min_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MIN_NUM_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2717,11 +3006,6 @@ SMaxNumF32Sop2::SMaxNumF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MAX_NUM_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2747,7 +3031,17 @@ SMaxNumF32Sop2::SMaxNumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxNumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_max_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MAX_NUM_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2763,11 +3057,6 @@ SMulF32Sop2::SMulF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MUL_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2793,14 +3082,24 @@ SMulF32Sop2::SMulF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MUL_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail SFmaakF32Sop2::SFmaakF32Sop2(const MachineInst *inst) : Sop2("s_fmaak_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SFmaakF32Sop2), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::SFmaakF32Sop2)), sdst(32, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->ssrc0), ssrc1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->ssrc1), @@ -2825,14 +3124,19 @@ SFmaakF32Sop2::SFmaakF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmaakF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmaakF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Sop2::validate_encoding("s_fmaak_f32", reinterpret_cast(opcode), + emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail SFmamkF32Sop2::SFmamkF32Sop2(const MachineInst *inst) : Sop2("s_fmamk_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::SFmamkF32Sop2), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::SFmamkF32Sop2)), sdst(32, OperandType::OPR_SDST, reinterpret_cast(inst)->sdst), ssrc0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->ssrc0), literal(32, OperandType::OPR_SIMM32, 0), @@ -2857,7 +3161,12 @@ SFmamkF32Sop2::SFmamkF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmamkF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmamkF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Sop2::validate_encoding("s_fmamk_f32", reinterpret_cast(opcode), + emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2874,11 +3183,6 @@ SFmacF32Sop2::SFmacF32Sop2(const MachineInst *inst) src_operands_[2] = &ssrc1; num_src_ = 3; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_FMAC_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2904,7 +3208,17 @@ SFmacF32Sop2::SFmacF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmacF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmacF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_FMAC_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2920,11 +3234,6 @@ SCvtPkRtzF16F32Sop2::SCvtPkRtzF16F32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CVT_PK_RTZ_F16_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2950,7 +3259,18 @@ SCvtPkRtzF16F32Sop2::SCvtPkRtzF16F32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_cvt_pk_rtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CVT_PK_RTZ_F16_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2966,11 +3286,6 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ADD_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -2998,7 +3313,17 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ADD_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3026,11 +3351,6 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_SUB_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3058,7 +3378,17 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_SUB_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3086,11 +3416,6 @@ SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MIN_NUM_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3118,7 +3443,17 @@ SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinNumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_min_num_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MIN_NUM_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3147,11 +3482,6 @@ SMaxNumF16Sop2::SMaxNumF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MAX_NUM_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3179,7 +3509,17 @@ SMaxNumF16Sop2::SMaxNumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxNumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_max_num_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MAX_NUM_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3208,11 +3548,6 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MUL_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3240,7 +3575,17 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MUL_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3269,11 +3614,6 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) src_operands_[2] = &ssrc1; num_src_ = 3; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_FMAC_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3301,7 +3641,17 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmacF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmacF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_FMAC_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3329,11 +3679,6 @@ SMinimumF32Sop2::SMinimumF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MINIMUM_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -3359,7 +3704,18 @@ SMinimumF32Sop2::SMinimumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinimumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinimumF32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_minimum_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MINIMUM_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3375,11 +3731,6 @@ SMaximumF32Sop2::SMaximumF32Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MAXIMUM_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -3405,7 +3756,18 @@ SMaximumF32Sop2::SMaximumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaximumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaximumF32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_maximum_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MAXIMUM_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3421,11 +3783,6 @@ SMinimumF16Sop2::SMinimumF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MINIMUM_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3453,7 +3810,18 @@ SMinimumF16Sop2::SMinimumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinimumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinimumF16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_minimum_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MINIMUM_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3482,11 +3850,6 @@ SMaximumF16Sop2::SMaximumF16Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MAXIMUM_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -3514,7 +3877,18 @@ SMaximumF16Sop2::SMaximumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaximumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaximumF16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_maximum_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MAXIMUM_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3543,11 +3917,6 @@ SAddNcU64Sop2::SAddNcU64Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_ADD_NC_U64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -3575,7 +3944,17 @@ SAddNcU64Sop2::SAddNcU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddNcU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_add_nc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_ADD_NC_U64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3591,11 +3970,6 @@ SSubNcU64Sop2::SSubNcU64Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_SUB_NC_U64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -3623,7 +3997,17 @@ SSubNcU64Sop2::SSubNcU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubNcU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_sub_nc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_SUB_NC_U64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -3639,11 +4023,6 @@ SMulU64Sop2::SMulU64Sop2(const MachineInst *inst) src_operands_[1] = &ssrc1; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_MUL_U64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -3671,7 +4050,17 @@ SMulU64Sop2::SMulU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sop2::validate_encoding( + "s_mul_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_MUL_U64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopc.cpp index 404a8cb6d342..4bbd0e7e1855 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,11 +22,6 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_EQ_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -54,7 +48,17 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_EQ_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -70,11 +74,6 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LG_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -101,7 +100,17 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LG_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -117,11 +126,6 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GT_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -148,7 +152,17 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GT_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -164,11 +178,6 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GE_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -195,7 +204,17 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GE_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -211,11 +230,6 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LT_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -242,7 +256,17 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LT_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -258,11 +282,6 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LE_I32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -289,7 +308,17 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LE_I32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -305,11 +334,6 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_EQ_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -336,7 +360,17 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_EQ_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -352,11 +386,6 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LG_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -383,7 +412,17 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LG_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -399,11 +438,6 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GT_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -430,7 +464,17 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GT_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -446,11 +490,6 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GE_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -477,7 +516,17 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GE_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -493,11 +542,6 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LT_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -524,7 +568,17 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LT_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -540,11 +594,6 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LE_U32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -571,7 +620,17 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LE_U32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -587,11 +646,6 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BITCMP0_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -618,7 +672,18 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BITCMP0_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -634,11 +699,6 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BITCMP1_B32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -665,7 +725,18 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BITCMP1_B32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -681,11 +752,6 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BITCMP0_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -713,7 +779,18 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BITCMP0_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -729,11 +806,6 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_BITCMP1_B64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -761,7 +833,18 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_BITCMP1_B64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -777,11 +860,6 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_EQ_U64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -810,7 +888,17 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_EQ_U64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -826,11 +914,6 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LG_U64 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand::make_literal32( 64, @@ -859,7 +942,17 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LG_U64 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -875,11 +968,6 @@ SCmpLtF32Sopc::SCmpLtF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LT_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -906,7 +994,17 @@ SCmpLtF32Sopc::SCmpLtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LT_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -922,11 +1020,6 @@ SCmpLtF16Sopc::SCmpLtF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LT_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -955,7 +1048,17 @@ SCmpLtF16Sopc::SCmpLtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LT_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -971,11 +1074,6 @@ SCmpEqF32Sopc::SCmpEqF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_EQ_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1002,7 +1100,17 @@ SCmpEqF32Sopc::SCmpEqF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_EQ_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1018,11 +1126,6 @@ SCmpEqF16Sopc::SCmpEqF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_EQ_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1051,7 +1154,17 @@ SCmpEqF16Sopc::SCmpEqF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_EQ_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1067,11 +1180,6 @@ SCmpLeF32Sopc::SCmpLeF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LE_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1098,7 +1206,17 @@ SCmpLeF32Sopc::SCmpLeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LE_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1114,11 +1232,6 @@ SCmpLeF16Sopc::SCmpLeF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LE_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1147,7 +1260,17 @@ SCmpLeF16Sopc::SCmpLeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LE_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1163,11 +1286,6 @@ SCmpGtF32Sopc::SCmpGtF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GT_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1194,7 +1312,17 @@ SCmpGtF32Sopc::SCmpGtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GT_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1210,11 +1338,6 @@ SCmpGtF16Sopc::SCmpGtF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GT_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1243,7 +1366,17 @@ SCmpGtF16Sopc::SCmpGtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GT_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1259,11 +1392,6 @@ SCmpLgF32Sopc::SCmpLgF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LG_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1290,7 +1418,17 @@ SCmpLgF32Sopc::SCmpLgF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LG_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1306,11 +1444,6 @@ SCmpLgF16Sopc::SCmpLgF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_LG_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1339,7 +1472,17 @@ SCmpLgF16Sopc::SCmpLgF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_LG_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1355,11 +1498,6 @@ SCmpGeF32Sopc::SCmpGeF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GE_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1386,7 +1524,17 @@ SCmpGeF32Sopc::SCmpGeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GE_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1402,11 +1550,6 @@ SCmpGeF16Sopc::SCmpGeF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_GE_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1435,7 +1578,17 @@ SCmpGeF16Sopc::SCmpGeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_GE_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1451,11 +1604,6 @@ SCmpOF32Sopc::SCmpOF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_O_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1482,7 +1630,17 @@ SCmpOF32Sopc::SCmpOF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpOF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpOF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_O_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1498,11 +1656,6 @@ SCmpOF16Sopc::SCmpOF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_O_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1531,7 +1684,17 @@ SCmpOF16Sopc::SCmpOF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpOF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpOF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_O_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1547,11 +1710,6 @@ SCmpUF32Sopc::SCmpUF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_U_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1578,7 +1736,17 @@ SCmpUF32Sopc::SCmpUF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpUF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpUF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_U_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1594,11 +1762,6 @@ SCmpUF16Sopc::SCmpUF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_U_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1627,7 +1790,17 @@ SCmpUF16Sopc::SCmpUF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpUF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpUF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_U_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1643,11 +1816,6 @@ SCmpNgeF32Sopc::SCmpNgeF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NGE_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1674,7 +1842,17 @@ SCmpNgeF32Sopc::SCmpNgeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NGE_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1690,11 +1868,6 @@ SCmpNgeF16Sopc::SCmpNgeF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NGE_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1723,7 +1896,17 @@ SCmpNgeF16Sopc::SCmpNgeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NGE_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1739,11 +1922,6 @@ SCmpNlgF32Sopc::SCmpNlgF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NLG_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1770,7 +1948,17 @@ SCmpNlgF32Sopc::SCmpNlgF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNlgF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNlgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NLG_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1786,11 +1974,6 @@ SCmpNlgF16Sopc::SCmpNlgF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NLG_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1819,7 +2002,17 @@ SCmpNlgF16Sopc::SCmpNlgF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNlgF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNlgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NLG_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1835,11 +2028,6 @@ SCmpNgtF32Sopc::SCmpNgtF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NGT_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1866,7 +2054,17 @@ SCmpNgtF32Sopc::SCmpNgtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NGT_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1882,11 +2080,6 @@ SCmpNgtF16Sopc::SCmpNgtF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NGT_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -1915,7 +2108,17 @@ SCmpNgtF16Sopc::SCmpNgtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NGT_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1931,11 +2134,6 @@ SCmpNleF32Sopc::SCmpNleF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NLE_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -1962,7 +2160,17 @@ SCmpNleF32Sopc::SCmpNleF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNleF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNleF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NLE_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -1978,11 +2186,6 @@ SCmpNleF16Sopc::SCmpNleF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NLE_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -2011,7 +2214,17 @@ SCmpNleF16Sopc::SCmpNleF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNleF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNleF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NLE_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2027,11 +2240,6 @@ SCmpNeqF32Sopc::SCmpNeqF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NEQ_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2058,7 +2266,17 @@ SCmpNeqF32Sopc::SCmpNeqF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNeqF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNeqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NEQ_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2074,11 +2292,6 @@ SCmpNeqF16Sopc::SCmpNeqF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NEQ_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -2107,7 +2320,17 @@ SCmpNeqF16Sopc::SCmpNeqF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNeqF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNeqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NEQ_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2123,11 +2346,6 @@ SCmpNltF32Sopc::SCmpNltF32Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NLT_F32 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand( 32, OperandType::OPR_SIMM32, @@ -2154,7 +2372,17 @@ SCmpNltF32Sopc::SCmpNltF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNltF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNltF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NLT_F32 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail @@ -2170,11 +2398,6 @@ SCmpNltF16Sopc::SCmpNltF16Sopc(const MachineInst *inst) dst_operands_[0] = &scc; num_src_ = 2; num_dst_ = 1; - if ((reinterpret_cast(inst)->ssrc0 == 255 || - reinterpret_cast(inst)->ssrc1 == 255) && - (reinterpret_cast(inst)->ssrc0 == 254 || - reinterpret_cast(inst)->ssrc1 == 254)) - throw util::InvalidInst("S_CMP_NLT_F16 may not mix 32-bit and 64-bit literals", ""); if (reinterpret_cast(inst)->ssrc0 == 255) ssrc0 = Operand(16, OperandType::OPR_SIMM32, @@ -2203,7 +2426,17 @@ SCmpNltF16Sopc::SCmpNltF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNltF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNltF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Sopc::validate_encoding( + "s_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if ((reinterpret_cast(inst)->ssrc0 == 255 || + reinterpret_cast(inst)->ssrc1 == 255) && + (reinterpret_cast(inst)->ssrc0 == 254 || + reinterpret_cast(inst)->ssrc1 == 254)) [[unlikely]] + return emit_error.emit() << "S_CMP_NLT_F16 may not mix 32-bit and 64-bit literals"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopk.cpp index c5966611ebcd..50e27cb8542f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -39,7 +42,11 @@ SVersionSopk::SVersionSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode) { +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_version", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,7 +68,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,7 +93,11 @@ SAddkCoI32Sopk::SAddkCoI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkCoI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkCoI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_co_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +115,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -117,7 +136,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -134,7 +157,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -165,7 +192,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -201,7 +233,11 @@ SCallI64Sopk::SCallI64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallI64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallI64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp.cpp index 8ded96be83be..950353e2453d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -37,7 +40,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +59,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +78,12 @@ SMonitorSleepSopp::SMonitorSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMonitorSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSMonitorSleepSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_monitor_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,7 +98,11 @@ SClauseSopp::SClauseSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode) { +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_clause", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -98,7 +118,12 @@ SSetVgprMsbSopp::SSetVgprMsbSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetVgprMsbSopp(const MachineInst *opcode) { +DecodeResult decodeSSetVgprMsbSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_set_vgpr_msb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -113,7 +138,11 @@ SDelayAluSopp::SDelayAluSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode) { +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_delay_alu", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +158,11 @@ SWaitAluSopp::SWaitAluSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitAluSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_alu", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +176,11 @@ SWaitIdleSopp::SWaitIdleSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_idle", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -158,7 +195,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -173,7 +214,11 @@ SRoundModeSopp::SRoundModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode) { +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_round_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -188,7 +233,12 @@ SDenormModeSopp::SDenormModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode) { +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_denorm_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -204,7 +254,12 @@ SBarrierWaitSopp::SBarrierWaitSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierWaitSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierWaitSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier_wait", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -220,7 +275,12 @@ SBarrierLeaveSopp::SBarrierLeaveSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierLeaveSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierLeaveSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier_leave", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +293,11 @@ SCodeEndSopp::SCodeEndSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode) { +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_code_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +314,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -275,7 +343,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +373,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +403,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +433,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +463,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +493,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -419,7 +517,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -433,7 +535,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -446,7 +553,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -461,7 +572,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -479,7 +594,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -497,7 +616,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +636,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +656,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,7 +677,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -558,7 +697,12 @@ STtracedataImmSopp::STtracedataImmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata_imm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +715,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +734,12 @@ SSetprioIncWgSopp::SSetprioIncWgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioIncWgSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioIncWgSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio_inc_wg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +755,12 @@ SWaitLoadcntSopp::SWaitLoadcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitLoadcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitLoadcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_loadcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -618,7 +776,12 @@ SWaitStorecntSopp::SWaitStorecntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitStorecntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitStorecntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_storecnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -634,7 +797,11 @@ SWaitXcntSopp::SWaitXcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitXcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitXcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_xcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +817,11 @@ SWaitDscntSopp::SWaitDscntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitDscntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitDscntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_dscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +837,11 @@ SWaitKmcntSopp::SWaitKmcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitKmcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitKmcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_kmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -682,7 +857,12 @@ SWaitLoadcntDscntSopp::SWaitLoadcntDscntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitLoadcntDscntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitLoadcntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_loadcnt_dscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -698,7 +878,12 @@ SWaitStorecntDscntSopp::SWaitStorecntDscntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitStorecntDscntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitStorecntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_storecnt_dscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -714,7 +899,12 @@ SWaitAsynccntSopp::SWaitAsynccntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitAsynccntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitAsynccntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_asynccnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -730,7 +920,12 @@ SWaitTensorcntSopp::SWaitTensorcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitTensorcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitTensorcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_tensorcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vbuffer.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vbuffer.cpp index 1f33e1c51d0b..8912ca185223 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vbuffer.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vbuffer.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vbuffer.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -46,7 +45,12 @@ BufferLoadU8Vbuffer::BufferLoadU8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +78,12 @@ BufferLoadI8Vbuffer::BufferLoadI8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +111,12 @@ BufferLoadU16Vbuffer::BufferLoadU16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -130,7 +144,12 @@ BufferLoadI16Vbuffer::BufferLoadI16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -158,7 +177,12 @@ BufferLoadB32Vbuffer::BufferLoadB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +210,12 @@ BufferLoadB64Vbuffer::BufferLoadB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +243,12 @@ BufferLoadB96Vbuffer::BufferLoadB96Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB96Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -242,7 +276,12 @@ BufferLoadB128Vbuffer::BufferLoadB128Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB128Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ BufferStoreB8Vbuffer::BufferStoreB8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -298,7 +342,12 @@ BufferStoreB16Vbuffer::BufferStoreB16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -326,7 +375,12 @@ BufferStoreB32Vbuffer::BufferStoreB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -354,7 +408,12 @@ BufferStoreB64Vbuffer::BufferStoreB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -382,7 +441,12 @@ BufferStoreB96Vbuffer::BufferStoreB96Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB96Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -410,7 +474,12 @@ BufferStoreB128Vbuffer::BufferStoreB128Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB128Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -438,7 +507,12 @@ BufferLoadD16U8Vbuffer::BufferLoadD16U8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -479,7 +553,12 @@ BufferLoadD16I8Vbuffer::BufferLoadD16I8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +599,12 @@ BufferLoadD16B16Vbuffer::BufferLoadD16B16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -561,7 +645,12 @@ BufferLoadD16HiU8Vbuffer::BufferLoadD16HiU8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +691,12 @@ BufferLoadD16HiI8Vbuffer::BufferLoadD16HiI8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -643,7 +737,12 @@ BufferLoadD16HiB16Vbuffer::BufferLoadD16HiB16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +783,12 @@ BufferStoreD16HiB8Vbuffer::BufferStoreD16HiB8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -712,7 +816,12 @@ BufferStoreD16HiB16Vbuffer::BufferStoreD16HiB16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -744,7 +853,12 @@ BufferAtomicSwapB32Vbuffer::BufferAtomicSwapB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -778,7 +892,13 @@ BufferAtomicCmpswapB32Vbuffer::BufferAtomicCmpswapB32Vbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_cmpswap_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -810,7 +930,12 @@ BufferAtomicAddU32Vbuffer::BufferAtomicAddU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -842,7 +967,12 @@ BufferAtomicSubU32Vbuffer::BufferAtomicSubU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -874,7 +1004,13 @@ BufferAtomicSubClampU32Vbuffer::BufferAtomicSubClampU32Vbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_sub_clamp_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -906,7 +1042,12 @@ BufferAtomicMinI32Vbuffer::BufferAtomicMinI32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -938,7 +1079,12 @@ BufferAtomicMinU32Vbuffer::BufferAtomicMinU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -970,7 +1116,12 @@ BufferAtomicMaxI32Vbuffer::BufferAtomicMaxI32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1002,7 +1153,12 @@ BufferAtomicMaxU32Vbuffer::BufferAtomicMaxU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1034,7 +1190,12 @@ BufferAtomicAndB32Vbuffer::BufferAtomicAndB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1066,7 +1227,12 @@ BufferAtomicOrB32Vbuffer::BufferAtomicOrB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1264,12 @@ BufferAtomicXorB32Vbuffer::BufferAtomicXorB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1130,7 +1301,12 @@ BufferAtomicIncU32Vbuffer::BufferAtomicIncU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1162,7 +1338,12 @@ BufferAtomicDecU32Vbuffer::BufferAtomicDecU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1194,7 +1375,12 @@ BufferAtomicSwapB64Vbuffer::BufferAtomicSwapB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1414,13 @@ BufferAtomicCmpswapB64Vbuffer::BufferAtomicCmpswapB64Vbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_cmpswap_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1260,7 +1452,12 @@ BufferAtomicAddU64Vbuffer::BufferAtomicAddU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1292,7 +1489,12 @@ BufferAtomicSubU64Vbuffer::BufferAtomicSubU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1324,7 +1526,12 @@ BufferAtomicMinI64Vbuffer::BufferAtomicMinI64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1356,7 +1563,12 @@ BufferAtomicMinU64Vbuffer::BufferAtomicMinU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1388,7 +1600,12 @@ BufferAtomicMaxI64Vbuffer::BufferAtomicMaxI64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1420,7 +1637,12 @@ BufferAtomicMaxU64Vbuffer::BufferAtomicMaxU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1674,12 @@ BufferAtomicAndB64Vbuffer::BufferAtomicAndB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1484,7 +1711,12 @@ BufferAtomicOrB64Vbuffer::BufferAtomicOrB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1516,7 +1748,12 @@ BufferAtomicXorB64Vbuffer::BufferAtomicXorB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1548,7 +1785,12 @@ BufferAtomicIncU64Vbuffer::BufferAtomicIncU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1580,7 +1822,12 @@ BufferAtomicDecU64Vbuffer::BufferAtomicDecU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1612,7 +1859,13 @@ BufferAtomicCondSubU32Vbuffer::BufferAtomicCondSubU32Vbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_cond_sub_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1897,13 @@ BufferAtomicMinNumF32Vbuffer::BufferAtomicMinNumF32Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_min_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1676,7 +1935,13 @@ BufferAtomicMaxNumF32Vbuffer::BufferAtomicMaxNumF32Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_max_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1708,7 +1973,12 @@ BufferAtomicAddF64Vbuffer::BufferAtomicAddF64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1740,7 +2010,12 @@ BufferAtomicAddF32Vbuffer::BufferAtomicAddF32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1772,7 +2047,13 @@ BufferAtomicPkAddF16Vbuffer::BufferAtomicPkAddF16Vbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2085,13 @@ BufferAtomicPkAddBf16Vbuffer::BufferAtomicPkAddBf16Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_pk_add_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1836,7 +2123,13 @@ BufferAtomicMinNumF64Vbuffer::BufferAtomicMinNumF64Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicMinNumF64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinNumF64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_min_num_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1868,7 +2161,13 @@ BufferAtomicMaxNumF64Vbuffer::BufferAtomicMaxNumF64Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicMaxNumF64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxNumF64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_max_num_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vds.cpp index 1e0b7248166f..938113647c03 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vds.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -33,7 +32,11 @@ DsAddU32Vds::DsAddU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -58,7 +61,11 @@ DsSubU32Vds::DsSubU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +90,11 @@ DsRsubU32Vds::DsRsubU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -108,7 +119,11 @@ DsIncU32Vds::DsIncU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -133,7 +148,11 @@ DsDecU32Vds::DsDecU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -158,7 +177,11 @@ DsMinI32Vds::DsMinI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -183,7 +206,11 @@ DsMaxI32Vds::DsMaxI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -208,7 +235,11 @@ DsMinU32Vds::DsMinU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +264,11 @@ DsMaxU32Vds::DsMaxU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -258,7 +293,11 @@ DsAndB32Vds::DsAndB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +322,11 @@ DsOrB32Vds::DsOrB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -308,7 +351,11 @@ DsXorB32Vds::DsXorB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +383,11 @@ DsMskorB32Vds::DsMskorB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +410,11 @@ DsStoreB32Vds::DsStoreB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -385,7 +440,12 @@ DsStore2addrB32Vds::DsStore2addrB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -411,7 +471,12 @@ DsStore2addrStride64B32Vds::DsStore2addrStride64B32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -439,7 +504,12 @@ DsCmpstoreB32Vds::DsCmpstoreB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -464,7 +534,11 @@ DsMinNumF32Vds::DsMinNumF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -489,7 +563,11 @@ DsMaxNumF32Vds::DsMaxNumF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -502,7 +580,11 @@ DsNopVds::DsNopVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopVds(const MachineInst *opcode) { +DecodeResult decodeDsNopVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +609,11 @@ DsAddF32Vds::DsAddF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -550,7 +636,11 @@ DsStoreB8Vds::DsStoreB8Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -573,7 +663,11 @@ DsStoreB16Vds::DsStoreB16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +695,11 @@ DsAddRtnU32Vds::DsAddRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -629,7 +727,11 @@ DsSubRtnU32Vds::DsSubRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +759,12 @@ DsRsubRtnU32Vds::DsRsubRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -685,7 +792,11 @@ DsIncRtnU32Vds::DsIncRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -713,7 +824,11 @@ DsDecRtnU32Vds::DsDecRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +856,11 @@ DsMinRtnI32Vds::DsMinRtnI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -769,7 +888,11 @@ DsMaxRtnI32Vds::DsMaxRtnI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -797,7 +920,11 @@ DsMinRtnU32Vds::DsMinRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -825,7 +952,11 @@ DsMaxRtnU32Vds::DsMaxRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -853,7 +984,11 @@ DsAndRtnB32Vds::DsAndRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -881,7 +1016,11 @@ DsOrRtnB32Vds::DsOrRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -909,7 +1048,11 @@ DsXorRtnB32Vds::DsXorRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -940,7 +1083,12 @@ DsMskorRtnB32Vds::DsMskorRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -968,7 +1116,12 @@ DsStorexchgRtnB32Vds::DsStorexchgRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -999,7 +1152,12 @@ DsStorexchg2addrRtnB32Vds::DsStorexchg2addrRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_2addr_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1030,7 +1188,13 @@ DsStorexchg2addrStride64RtnB32Vds::DsStorexchg2addrStride64RtnB32Vds(const Machi } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1225,12 @@ DsCmpstoreRtnB32Vds::DsCmpstoreRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1089,7 +1258,12 @@ DsMinNumRtnF32Vds::DsMinNumRtnF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumRtnF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1117,7 +1291,12 @@ DsMaxNumRtnF32Vds::DsMaxNumRtnF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumRtnF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1136,7 +1315,12 @@ DsSwizzleB32Vds::DsSwizzleB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1159,7 +1343,11 @@ DsLoadB32Vds::DsLoadB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1182,7 +1370,12 @@ DsLoad2addrB32Vds::DsLoad2addrB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1398,12 @@ DsLoad2addrStride64B32Vds::DsLoad2addrStride64B32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1426,11 @@ DsLoadI8Vds::DsLoadI8Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1251,7 +1453,11 @@ DsLoadU8Vds::DsLoadU8Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1274,7 +1480,11 @@ DsLoadI16Vds::DsLoadI16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1297,7 +1507,11 @@ DsLoadU16Vds::DsLoadU16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1319,7 +1533,11 @@ DsConsumeVds::DsConsumeVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeVds(const MachineInst *opcode) { +DecodeResult decodeDsConsumeVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1341,7 +1559,11 @@ DsAppendVds::DsAppendVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendVds(const MachineInst *opcode) { +DecodeResult decodeDsAppendVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1366,7 +1588,11 @@ DsAddU64Vds::DsAddU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1391,7 +1617,11 @@ DsSubU64Vds::DsSubU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1416,7 +1646,11 @@ DsRsubU64Vds::DsRsubU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1441,7 +1675,11 @@ DsIncU64Vds::DsIncU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1704,11 @@ DsDecU64Vds::DsDecU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1491,7 +1733,11 @@ DsMinI64Vds::DsMinI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1516,7 +1762,11 @@ DsMaxI64Vds::DsMaxI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1791,11 @@ DsMinU64Vds::DsMinU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1566,7 +1820,11 @@ DsMaxU64Vds::DsMaxU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1591,7 +1849,11 @@ DsAndB64Vds::DsAndB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1616,7 +1878,11 @@ DsOrB64Vds::DsOrB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1641,7 +1907,11 @@ DsXorB64Vds::DsXorB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1669,7 +1939,11 @@ DsMskorB64Vds::DsMskorB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1692,7 +1966,11 @@ DsStoreB64Vds::DsStoreB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1718,7 +1996,12 @@ DsStore2addrB64Vds::DsStore2addrB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1744,7 +2027,12 @@ DsStore2addrStride64B64Vds::DsStore2addrStride64B64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1772,7 +2060,12 @@ DsCmpstoreB64Vds::DsCmpstoreB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2090,11 @@ DsMinNumF64Vds::DsMinNumF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1822,7 +2119,11 @@ DsMaxNumF64Vds::DsMaxNumF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1847,7 +2148,11 @@ DsAddF64Vds::DsAddF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1869,7 +2174,13 @@ DsAtomicAsyncBarrierArriveB64Vds::DsAtomicAsyncBarrierArriveB64Vds(const Machine } namespace detail { -std::unique_ptr decodeDsAtomicAsyncBarrierArriveB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAtomicAsyncBarrierArriveB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_atomic_async_barrier_arrive_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1897,7 +2208,11 @@ DsAddRtnU64Vds::DsAddRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1925,7 +2240,11 @@ DsSubRtnU64Vds::DsSubRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1953,7 +2272,12 @@ DsRsubRtnU64Vds::DsRsubRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1981,7 +2305,11 @@ DsIncRtnU64Vds::DsIncRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2009,7 +2337,11 @@ DsDecRtnU64Vds::DsDecRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2037,7 +2369,11 @@ DsMinRtnI64Vds::DsMinRtnI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2065,7 +2401,11 @@ DsMaxRtnI64Vds::DsMaxRtnI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2093,7 +2433,11 @@ DsMinRtnU64Vds::DsMinRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2121,7 +2465,11 @@ DsMaxRtnU64Vds::DsMaxRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2149,7 +2497,11 @@ DsAndRtnB64Vds::DsAndRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2177,7 +2529,11 @@ DsOrRtnB64Vds::DsOrRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2205,7 +2561,11 @@ DsXorRtnB64Vds::DsXorRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2236,7 +2596,12 @@ DsMskorRtnB64Vds::DsMskorRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2264,7 +2629,12 @@ DsStorexchgRtnB64Vds::DsStorexchgRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2295,7 +2665,12 @@ DsStorexchg2addrRtnB64Vds::DsStorexchg2addrRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_2addr_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2326,7 +2701,13 @@ DsStorexchg2addrStride64RtnB64Vds::DsStorexchg2addrStride64RtnB64Vds(const Machi } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2357,7 +2738,12 @@ DsCmpstoreRtnB64Vds::DsCmpstoreRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2385,7 +2771,12 @@ DsMinNumRtnF64Vds::DsMinNumRtnF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumRtnF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2413,7 +2804,12 @@ DsMaxNumRtnF64Vds::DsMaxNumRtnF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumRtnF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2441,7 +2837,11 @@ DsAddRtnF64Vds::DsAddRtnF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2469,7 +2869,13 @@ DsAtomicBarrierArriveRtnB64Vds::DsAtomicBarrierArriveRtnB64Vds(const MachineInst } namespace detail { -std::unique_ptr decodeDsAtomicBarrierArriveRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAtomicBarrierArriveRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_atomic_barrier_arrive_rtn_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2492,7 +2898,11 @@ DsLoadB64Vds::DsLoadB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2515,7 +2925,12 @@ DsLoad2addrB64Vds::DsLoad2addrB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2538,7 +2953,12 @@ DsLoad2addrStride64B64Vds::DsLoad2addrStride64B64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2566,7 +2986,11 @@ DsAddRtnF32Vds::DsAddRtnF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2594,7 +3018,12 @@ DsCondxchg32RtnB64Vds::DsCondxchg32RtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2619,7 +3048,12 @@ DsCondSubU32Vds::DsCondSubU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondSubU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCondSubU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cond_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2644,7 +3078,12 @@ DsSubClampU32Vds::DsSubClampU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubClampU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubClampU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_clamp_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2669,7 +3108,11 @@ DsPkAddF16Vds::DsPkAddF16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddF16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddF16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2694,7 +3137,11 @@ DsPkAddBf16Vds::DsPkAddBf16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddBf16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddBf16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2717,7 +3164,12 @@ DsStoreB8D16HiVds::DsStoreB8D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2740,7 +3192,12 @@ DsStoreB16D16HiVds::DsStoreB16D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2763,7 +3220,11 @@ DsLoadU8D16Vds::DsLoadU8D16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2799,7 +3260,12 @@ DsLoadU8D16HiVds::DsLoadU8D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2835,7 +3301,11 @@ DsLoadI8D16Vds::DsLoadI8D16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2871,7 +3341,12 @@ DsLoadI8D16HiVds::DsLoadI8D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2907,7 +3382,12 @@ DsLoadU16D16Vds::DsLoadU16D16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2943,7 +3423,12 @@ DsLoadU16D16HiVds::DsLoadU16D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2984,7 +3469,12 @@ DsCondSubRtnU32Vds::DsCondSubRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondSubRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCondSubRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cond_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3012,7 +3502,12 @@ DsSubClampRtnU32Vds::DsSubClampRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubClampRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubClampRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_clamp_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3040,7 +3535,12 @@ DsPkAddRtnF16Vds::DsPkAddRtnF16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnF16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnF16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_rtn_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3068,7 +3568,12 @@ DsPkAddRtnBf16Vds::DsPkAddRtnBf16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnBf16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnBf16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_rtn_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3090,7 +3595,12 @@ DsStoreAddtidB32Vds::DsStoreAddtidB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreAddtidB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3112,7 +3622,12 @@ DsLoadAddtidB32Vds::DsLoadAddtidB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadAddtidB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3134,7 +3649,12 @@ DsPermuteB32Vds::DsPermuteB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3156,7 +3676,12 @@ DsBpermuteB32Vds::DsBpermuteB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3178,7 +3703,12 @@ DsBpermuteFiB32Vds::DsBpermuteFiB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteFiB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteFiB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_bpermute_fi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3201,7 +3731,11 @@ DsStoreB96Vds::DsStoreB96Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB96Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3224,7 +3758,11 @@ DsStoreB128Vds::DsStoreB128Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB128Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3247,7 +3785,12 @@ DsLoadTr4B64Vds::DsLoadTr4B64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadTr4B64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadTr4B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_tr4_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3270,7 +3813,12 @@ DsLoadTr6B96Vds::DsLoadTr6B96Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadTr6B96Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadTr6B96Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_tr6_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3293,7 +3841,12 @@ DsLoadTr16B128Vds::DsLoadTr16B128Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadTr16B128Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadTr16B128Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_tr16_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3316,7 +3869,12 @@ DsLoadTr8B64Vds::DsLoadTr8B64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadTr8B64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadTr8B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_tr8_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3339,7 +3897,11 @@ DsLoadB96Vds::DsLoadB96Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB96Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3362,7 +3924,11 @@ DsLoadB128Vds::DsLoadB128Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB128Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vflat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vflat.cpp index 4046bd71eca7..125847e8fc5d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vflat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vflat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vflat.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ FlatLoadU8Vflat::FlatLoadU8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -69,7 +73,12 @@ FlatLoadI8Vflat::FlatLoadI8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -96,7 +105,12 @@ FlatLoadU16Vflat::FlatLoadU16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +137,12 @@ FlatLoadI16Vflat::FlatLoadI16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -150,7 +169,12 @@ FlatLoadB32Vflat::FlatLoadB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +201,12 @@ FlatLoadB64Vflat::FlatLoadB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -204,7 +233,12 @@ FlatLoadB96Vflat::FlatLoadB96Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB96Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +265,12 @@ FlatLoadB128Vflat::FlatLoadB128Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB128Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -258,7 +297,12 @@ FlatStoreB8Vflat::FlatStoreB8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -285,7 +329,12 @@ FlatStoreB16Vflat::FlatStoreB16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -312,7 +361,12 @@ FlatStoreB32Vflat::FlatStoreB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -339,7 +393,12 @@ FlatStoreB64Vflat::FlatStoreB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +425,12 @@ FlatStoreB96Vflat::FlatStoreB96Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB96Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -393,7 +457,12 @@ FlatStoreB128Vflat::FlatStoreB128Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB128Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -420,7 +489,12 @@ FlatLoadD16U8Vflat::FlatLoadD16U8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16U8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16U8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -460,7 +534,12 @@ FlatLoadD16I8Vflat::FlatLoadD16I8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16I8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16I8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -500,7 +579,12 @@ FlatLoadD16B16Vflat::FlatLoadD16B16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16B16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16B16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -540,7 +624,12 @@ FlatLoadD16HiU8Vflat::FlatLoadD16HiU8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -580,7 +669,12 @@ FlatLoadD16HiI8Vflat::FlatLoadD16HiI8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,7 +714,12 @@ FlatLoadD16HiB16Vflat::FlatLoadD16HiB16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -660,7 +759,12 @@ FlatStoreD16HiB8Vflat::FlatStoreD16HiB8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +791,12 @@ FlatStoreD16HiB16Vflat::FlatStoreD16HiB16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -720,7 +829,12 @@ FlatAtomicSwapB32Vflat::FlatAtomicSwapB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -753,7 +867,12 @@ FlatAtomicCmpswapB32Vflat::FlatAtomicCmpswapB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_cmpswap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -786,7 +905,12 @@ FlatAtomicAddU32Vflat::FlatAtomicAddU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -819,7 +943,12 @@ FlatAtomicSubU32Vflat::FlatAtomicSubU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -852,7 +981,12 @@ FlatAtomicSubClampU32Vflat::FlatAtomicSubClampU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_sub_clamp_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -885,7 +1019,12 @@ FlatAtomicMinI32Vflat::FlatAtomicMinI32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -918,7 +1057,12 @@ FlatAtomicMinU32Vflat::FlatAtomicMinU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1095,12 @@ FlatAtomicMaxI32Vflat::FlatAtomicMaxI32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -984,7 +1133,12 @@ FlatAtomicMaxU32Vflat::FlatAtomicMaxU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1171,12 @@ FlatAtomicAndB32Vflat::FlatAtomicAndB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1209,12 @@ FlatAtomicOrB32Vflat::FlatAtomicOrB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1247,12 @@ FlatAtomicXorB32Vflat::FlatAtomicXorB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1116,7 +1285,12 @@ FlatAtomicIncU32Vflat::FlatAtomicIncU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1149,7 +1323,12 @@ FlatAtomicDecU32Vflat::FlatAtomicDecU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1182,7 +1361,12 @@ FlatAtomicSwapB64Vflat::FlatAtomicSwapB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1215,7 +1399,12 @@ FlatAtomicCmpswapB64Vflat::FlatAtomicCmpswapB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_cmpswap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1248,7 +1437,12 @@ FlatAtomicAddU64Vflat::FlatAtomicAddU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1281,7 +1475,12 @@ FlatAtomicSubU64Vflat::FlatAtomicSubU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1314,7 +1513,12 @@ FlatAtomicMinI64Vflat::FlatAtomicMinI64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1347,7 +1551,12 @@ FlatAtomicMinU64Vflat::FlatAtomicMinU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1380,7 +1589,12 @@ FlatAtomicMaxI64Vflat::FlatAtomicMaxI64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1413,7 +1627,12 @@ FlatAtomicMaxU64Vflat::FlatAtomicMaxU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1446,7 +1665,12 @@ FlatAtomicAndB64Vflat::FlatAtomicAndB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1479,7 +1703,12 @@ FlatAtomicOrB64Vflat::FlatAtomicOrB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1741,12 @@ FlatAtomicXorB64Vflat::FlatAtomicXorB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1545,7 +1779,12 @@ FlatAtomicIncU64Vflat::FlatAtomicIncU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1578,7 +1817,12 @@ FlatAtomicDecU64Vflat::FlatAtomicDecU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1611,7 +1855,12 @@ FlatAtomicCondSubU32Vflat::FlatAtomicCondSubU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_cond_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1893,12 @@ FlatAtomicMinNumF32Vflat::FlatAtomicMinNumF32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1677,7 +1931,12 @@ FlatAtomicMaxNumF32Vflat::FlatAtomicMaxNumF32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1710,7 +1969,12 @@ FlatAtomicAddF64Vflat::FlatAtomicAddF64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1743,7 +2007,12 @@ FlatAtomicAddF32Vflat::FlatAtomicAddF32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2045,12 @@ FlatAtomicPkAddF16Vflat::FlatAtomicPkAddF16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1809,7 +2083,12 @@ FlatAtomicPkAddBf16Vflat::FlatAtomicPkAddBf16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1842,7 +2121,12 @@ FlatAtomicMinNumF64Vflat::FlatAtomicMinNumF64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinNumF64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinNumF64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_num_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1875,7 +2159,12 @@ FlatAtomicMaxNumF64Vflat::FlatAtomicMaxNumF64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxNumF64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxNumF64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_num_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1898,7 +2187,12 @@ FlatPrefetchB8Vflat::FlatPrefetchB8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatPrefetchB8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatPrefetchB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_prefetch_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1925,7 +2219,12 @@ FlatLoadMonitorB32Vflat::FlatLoadMonitorB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadMonitorB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadMonitorB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_monitor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1952,7 +2251,12 @@ FlatLoadMonitorB64Vflat::FlatLoadMonitorB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadMonitorB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadMonitorB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_monitor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1979,7 +2283,12 @@ FlatLoadMonitorB128Vflat::FlatLoadMonitorB128Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadMonitorB128Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadMonitorB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_monitor_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal.cpp index 8b7f951d037b..29ac09676724 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vglobal.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ GlobalLoadU8Vglobal::GlobalLoadU8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadU8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -69,7 +73,12 @@ GlobalLoadI8Vglobal::GlobalLoadI8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadI8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -96,7 +105,12 @@ GlobalLoadU16Vglobal::GlobalLoadU16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadU16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadU16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +137,12 @@ GlobalLoadI16Vglobal::GlobalLoadI16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadI16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadI16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -150,7 +169,12 @@ GlobalLoadB32Vglobal::GlobalLoadB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +201,12 @@ GlobalLoadB64Vglobal::GlobalLoadB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -204,7 +233,12 @@ GlobalLoadB96Vglobal::GlobalLoadB96Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB96Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +265,12 @@ GlobalLoadB128Vglobal::GlobalLoadB128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -258,7 +297,12 @@ GlobalStoreB8Vglobal::GlobalStoreB8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -285,7 +329,12 @@ GlobalStoreB16Vglobal::GlobalStoreB16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -312,7 +361,12 @@ GlobalStoreB32Vglobal::GlobalStoreB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -339,7 +393,12 @@ GlobalStoreB64Vglobal::GlobalStoreB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +425,12 @@ GlobalStoreB96Vglobal::GlobalStoreB96Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB96Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -393,7 +457,12 @@ GlobalStoreB128Vglobal::GlobalStoreB128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -420,7 +489,12 @@ GlobalLoadD16U8Vglobal::GlobalLoadD16U8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -460,7 +534,12 @@ GlobalLoadD16I8Vglobal::GlobalLoadD16I8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -500,7 +579,12 @@ GlobalLoadD16B16Vglobal::GlobalLoadD16B16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -540,7 +624,12 @@ GlobalLoadD16HiU8Vglobal::GlobalLoadD16HiU8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -580,7 +669,12 @@ GlobalLoadD16HiI8Vglobal::GlobalLoadD16HiI8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,7 +714,12 @@ GlobalLoadD16HiB16Vglobal::GlobalLoadD16HiB16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -660,7 +759,12 @@ GlobalStoreD16HiB8Vglobal::GlobalStoreD16HiB8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +791,12 @@ GlobalStoreD16HiB16Vglobal::GlobalStoreD16HiB16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -710,7 +819,12 @@ GlobalLoadAddtidB32Vglobal::GlobalLoadAddtidB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -733,7 +847,12 @@ GlobalStoreAddtidB32Vglobal::GlobalStoreAddtidB32Vglobal(const MachineInst *inst } namespace detail { -std::unique_ptr decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -746,7 +865,12 @@ GlobalInvVglobal::GlobalInvVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalInvVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalInvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -759,7 +883,12 @@ GlobalWbVglobal::GlobalWbVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalWbVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalWbVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_wb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -792,7 +921,12 @@ GlobalAtomicSwapB32Vglobal::GlobalAtomicSwapB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -825,7 +959,13 @@ GlobalAtomicCmpswapB32Vglobal::GlobalAtomicCmpswapB32Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_cmpswap_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +998,12 @@ GlobalAtomicAddU32Vglobal::GlobalAtomicAddU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -891,7 +1036,12 @@ GlobalAtomicSubU32Vglobal::GlobalAtomicSubU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1074,13 @@ GlobalAtomicSubClampU32Vglobal::GlobalAtomicSubClampU32Vglobal(const MachineInst } namespace detail { -std::unique_ptr decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_sub_clamp_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -957,7 +1113,12 @@ GlobalAtomicMinI32Vglobal::GlobalAtomicMinI32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -990,7 +1151,12 @@ GlobalAtomicMinU32Vglobal::GlobalAtomicMinU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1023,7 +1189,12 @@ GlobalAtomicMaxI32Vglobal::GlobalAtomicMaxI32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1227,12 @@ GlobalAtomicMaxU32Vglobal::GlobalAtomicMaxU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1089,7 +1265,12 @@ GlobalAtomicAndB32Vglobal::GlobalAtomicAndB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1122,7 +1303,12 @@ GlobalAtomicOrB32Vglobal::GlobalAtomicOrB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1341,12 @@ GlobalAtomicXorB32Vglobal::GlobalAtomicXorB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1188,7 +1379,12 @@ GlobalAtomicIncU32Vglobal::GlobalAtomicIncU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1417,12 @@ GlobalAtomicDecU32Vglobal::GlobalAtomicDecU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1254,7 +1455,12 @@ GlobalAtomicSwapB64Vglobal::GlobalAtomicSwapB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1287,7 +1493,13 @@ GlobalAtomicCmpswapB64Vglobal::GlobalAtomicCmpswapB64Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_cmpswap_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1320,7 +1532,12 @@ GlobalAtomicAddU64Vglobal::GlobalAtomicAddU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1353,7 +1570,12 @@ GlobalAtomicSubU64Vglobal::GlobalAtomicSubU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1386,7 +1608,12 @@ GlobalAtomicMinI64Vglobal::GlobalAtomicMinI64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1646,12 @@ GlobalAtomicMinU64Vglobal::GlobalAtomicMinU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1684,12 @@ GlobalAtomicMaxI64Vglobal::GlobalAtomicMaxI64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1485,7 +1722,12 @@ GlobalAtomicMaxU64Vglobal::GlobalAtomicMaxU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1760,12 @@ GlobalAtomicAndB64Vglobal::GlobalAtomicAndB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1551,7 +1798,12 @@ GlobalAtomicOrB64Vglobal::GlobalAtomicOrB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1836,12 @@ GlobalAtomicXorB64Vglobal::GlobalAtomicXorB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1617,7 +1874,12 @@ GlobalAtomicIncU64Vglobal::GlobalAtomicIncU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1650,7 +1912,12 @@ GlobalAtomicDecU64Vglobal::GlobalAtomicDecU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1663,7 +1930,12 @@ GlobalWbinvVglobal::GlobalWbinvVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalWbinvVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalWbinvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_wbinv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1696,7 +1968,13 @@ GlobalAtomicCondSubU32Vglobal::GlobalAtomicCondSubU32Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_cond_sub_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1729,7 +2007,13 @@ GlobalAtomicMinNumF32Vglobal::GlobalAtomicMinNumF32Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_min_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1762,7 +2046,13 @@ GlobalAtomicMaxNumF32Vglobal::GlobalAtomicMaxNumF32Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_max_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1791,7 +2081,12 @@ GlobalLoadBlockVglobal::GlobalLoadBlockVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadBlockVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1820,7 +2115,12 @@ GlobalStoreBlockVglobal::GlobalStoreBlockVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreBlockVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1853,7 +2153,12 @@ GlobalAtomicAddF64Vglobal::GlobalAtomicAddF64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddF64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddF64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1886,7 +2191,12 @@ GlobalAtomicAddF32Vglobal::GlobalAtomicAddF32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1913,7 +2223,12 @@ GlobalLoadTr16B128Vglobal::GlobalLoadTr16B128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadTr16B128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadTr16B128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_tr16_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1940,7 +2255,12 @@ GlobalLoadTr8B64Vglobal::GlobalLoadTr8B64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadTr8B64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadTr8B64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_tr8_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1973,7 +2293,13 @@ GlobalAtomicPkAddF16Vglobal::GlobalAtomicPkAddF16Vglobal(const MachineInst *inst } namespace detail { -std::unique_ptr decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2332,13 @@ GlobalAtomicPkAddBf16Vglobal::GlobalAtomicPkAddBf16Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_pk_add_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2039,7 +2371,13 @@ GlobalAtomicMinNumF64Vglobal::GlobalAtomicMinNumF64Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicMinNumF64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinNumF64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_min_num_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2072,7 +2410,13 @@ GlobalAtomicMaxNumF64Vglobal::GlobalAtomicMaxNumF64Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxNumF64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxNumF64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_max_num_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2095,7 +2439,12 @@ GlobalPrefetchB8Vglobal::GlobalPrefetchB8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalPrefetchB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalPrefetchB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_prefetch_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2124,7 +2473,13 @@ GlobalLoadAsyncToLdsB8Vglobal::GlobalLoadAsyncToLdsB8Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalLoadAsyncToLdsB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadAsyncToLdsB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_load_async_to_lds_b8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2153,7 +2508,13 @@ GlobalLoadAsyncToLdsB32Vglobal::GlobalLoadAsyncToLdsB32Vglobal(const MachineInst } namespace detail { -std::unique_ptr decodeGlobalLoadAsyncToLdsB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadAsyncToLdsB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_load_async_to_lds_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2182,7 +2543,13 @@ GlobalLoadAsyncToLdsB64Vglobal::GlobalLoadAsyncToLdsB64Vglobal(const MachineInst } namespace detail { -std::unique_ptr decodeGlobalLoadAsyncToLdsB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadAsyncToLdsB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_load_async_to_lds_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2211,7 +2578,13 @@ GlobalLoadAsyncToLdsB128Vglobal::GlobalLoadAsyncToLdsB128Vglobal(const MachineIn } namespace detail { -std::unique_ptr decodeGlobalLoadAsyncToLdsB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadAsyncToLdsB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_load_async_to_lds_b128", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2240,7 +2613,13 @@ GlobalStoreAsyncFromLdsB8Vglobal::GlobalStoreAsyncFromLdsB8Vglobal(const Machine } namespace detail { -std::unique_ptr decodeGlobalStoreAsyncFromLdsB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreAsyncFromLdsB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_store_async_from_lds_b8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2269,7 +2648,13 @@ GlobalStoreAsyncFromLdsB32Vglobal::GlobalStoreAsyncFromLdsB32Vglobal(const Machi } namespace detail { -std::unique_ptr decodeGlobalStoreAsyncFromLdsB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreAsyncFromLdsB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_store_async_from_lds_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2298,7 +2683,13 @@ GlobalStoreAsyncFromLdsB64Vglobal::GlobalStoreAsyncFromLdsB64Vglobal(const Machi } namespace detail { -std::unique_ptr decodeGlobalStoreAsyncFromLdsB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreAsyncFromLdsB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_store_async_from_lds_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2327,7 +2718,13 @@ GlobalStoreAsyncFromLdsB128Vglobal::GlobalStoreAsyncFromLdsB128Vglobal(const Mac } namespace detail { -std::unique_ptr decodeGlobalStoreAsyncFromLdsB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreAsyncFromLdsB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_store_async_from_lds_b128", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2356,7 +2753,12 @@ ClusterLoadB32Vglobal::ClusterLoadB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeClusterLoadB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "cluster_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2385,7 +2787,12 @@ ClusterLoadB64Vglobal::ClusterLoadB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeClusterLoadB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "cluster_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2414,7 +2821,12 @@ ClusterLoadB128Vglobal::ClusterLoadB128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeClusterLoadB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "cluster_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2446,7 +2858,13 @@ ClusterLoadAsyncToLdsB8Vglobal::ClusterLoadAsyncToLdsB8Vglobal(const MachineInst } namespace detail { -std::unique_ptr decodeClusterLoadAsyncToLdsB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadAsyncToLdsB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("cluster_load_async_to_lds_b8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2478,7 +2896,13 @@ ClusterLoadAsyncToLdsB32Vglobal::ClusterLoadAsyncToLdsB32Vglobal(const MachineIn } namespace detail { -std::unique_ptr decodeClusterLoadAsyncToLdsB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadAsyncToLdsB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("cluster_load_async_to_lds_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2510,7 +2934,13 @@ ClusterLoadAsyncToLdsB64Vglobal::ClusterLoadAsyncToLdsB64Vglobal(const MachineIn } namespace detail { -std::unique_ptr decodeClusterLoadAsyncToLdsB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadAsyncToLdsB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("cluster_load_async_to_lds_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2542,7 +2972,13 @@ ClusterLoadAsyncToLdsB128Vglobal::ClusterLoadAsyncToLdsB128Vglobal(const Machine } namespace detail { -std::unique_ptr decodeClusterLoadAsyncToLdsB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeClusterLoadAsyncToLdsB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("cluster_load_async_to_lds_b128", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2569,7 +3005,12 @@ GlobalLoadMonitorB32Vglobal::GlobalLoadMonitorB32Vglobal(const MachineInst *inst } namespace detail { -std::unique_ptr decodeGlobalLoadMonitorB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadMonitorB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_monitor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2596,7 +3037,12 @@ GlobalLoadMonitorB64Vglobal::GlobalLoadMonitorB64Vglobal(const MachineInst *inst } namespace detail { -std::unique_ptr decodeGlobalLoadMonitorB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadMonitorB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_monitor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2623,7 +3069,13 @@ GlobalLoadMonitorB128Vglobal::GlobalLoadMonitorB128Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalLoadMonitorB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadMonitorB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_load_monitor_b128", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2650,7 +3102,12 @@ GlobalLoadTr4B64Vglobal::GlobalLoadTr4B64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadTr4B64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadTr4B64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_tr4_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2677,7 +3134,12 @@ GlobalLoadTr6B96Vglobal::GlobalLoadTr6B96Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadTr6B96Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadTr6B96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_tr6_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vimage.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vimage.cpp index d079b9fec585..88b54ad504c3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vimage.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vimage.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vimage.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -28,7 +27,12 @@ TensorLoadToLdsVimage::TensorLoadToLdsVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTensorLoadToLdsVimage(const MachineInst *opcode) { +DecodeResult decodeTensorLoadToLdsVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "tensor_load_to_lds", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ TensorStoreFromLdsVimage::TensorStoreFromLdsVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTensorStoreFromLdsVimage(const MachineInst *opcode) { +DecodeResult decodeTensorStoreFromLdsVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "tensor_store_from_lds", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop1.cpp index 55dca8ee2577..cf931372ef7e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -17,13 +16,21 @@ VNopVop1::VNopVop1(const MachineInst *inst) : Vop1(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_nop_dpp" : "v_nop_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VNopVop1), LiteralSupport::None, 0) { + selected_exec_fn(InstructionExecutionId::VNopVop1)) { num_src_ = 0; num_dst_ = 0; } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_dpp" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -73,7 +80,15 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_dpp" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,21 +98,30 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) ? "v_readfirstlane_b32_dpp" : "v_readfirstlane_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VReadfirstlaneB32Vop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VReadfirstlaneB32Vop1)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_dpp" + : "v_readfirstlane_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -135,14 +159,22 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_dpp" + : "v_cvt_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -179,14 +211,22 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_dpp" + : "v_cvt_f64_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -236,7 +276,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_dpp" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -286,7 +334,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_dpp" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +392,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_dpp" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -386,7 +450,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_dpp" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -438,7 +510,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_dpp" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +583,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_dpp" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -553,7 +641,16 @@ VCvtNearestI32F32Vop1::VCvtNearestI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_dpp" + : "v_cvt_nearest_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -603,7 +700,16 @@ VCvtFloorI32F32Vop1::VCvtFloorI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_dpp" + : "v_cvt_floor_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -653,7 +759,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_dpp" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -691,14 +806,22 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_dpp" + : "v_cvt_f32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -735,14 +858,22 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_dpp" + : "v_cvt_f64_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -792,7 +923,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_dpp" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -842,7 +982,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_dpp" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -892,7 +1041,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_dpp" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -942,7 +1100,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_dpp" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -980,14 +1147,22 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_dpp" + : "v_cvt_u32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1024,14 +1199,22 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_dpp" + : "v_cvt_f64_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1069,14 +1252,22 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_dpp" + : "v_trunc_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1114,14 +1305,22 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_dpp" + : "v_ceil_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1159,14 +1358,22 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_dpp" + : "v_rndne_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1204,14 +1411,22 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_dpp" + : "v_floor_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1221,13 +1436,21 @@ VPipeflushVop1::VPipeflushVop1(const MachineInst *inst) ? "v_pipeflush_dpp" : "v_pipeflush_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPipeflushVop1), LiteralSupport::None, 0) { + selected_exec_fn(InstructionExecutionId::VPipeflushVop1)) { num_src_ = 0; num_dst_ = 0; } namespace detail { -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_dpp" + : "v_pipeflush_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1281,7 +1504,15 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_dpp" + : "v_mov_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,14 +1562,22 @@ VMovB64Vop1::VMovB64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MOV_B64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVMovB64Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b64_dpp" + : "v_mov_b64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MOV_B64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1388,7 +1627,15 @@ VTanhF32Vop1::VTanhF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTanhF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTanhF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_tanh_f32_dpp" + : "v_tanh_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1442,7 +1689,15 @@ VTanhF16Vop1::VTanhF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTanhF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTanhF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_tanh_f16_dpp" + : "v_tanh_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,7 +1759,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_dpp" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1554,7 +1817,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_dpp" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1875,15 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_dpp" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1654,7 +1933,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_dpp" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1704,7 +1991,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_dpp" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1754,7 +2049,15 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_dpp" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2107,15 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_dpp" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1854,7 +2165,15 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_dpp" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1904,7 +2223,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_dpp" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1954,7 +2282,15 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_dpp" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1983,15 +2319,23 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_dpp" + : "v_rcp_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2020,15 +2364,23 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_dpp" + : "v_rsq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2078,7 +2430,15 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_dpp" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2107,15 +2467,23 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_dpp" + : "v_sqrt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2165,7 +2533,15 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_dpp" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2215,7 +2591,15 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_dpp" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2265,7 +2649,15 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_dpp" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2315,7 +2707,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_dpp" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2365,7 +2765,15 @@ VClzI32U32Vop1::VClzI32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_dpp" + : "v_clz_i32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2415,7 +2823,15 @@ VCtzI32B32Vop1::VCtzI32B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_dpp" + : "v_ctz_i32_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2465,7 +2881,15 @@ VClsI32Vop1::VClsI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_dpp" + : "v_cls_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2503,14 +2927,23 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_dpp" + : "v_frexp_exp_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2548,14 +2981,23 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_dpp" + : "v_frexp_mant_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2593,14 +3035,22 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_dpp" + : "v_fract_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2650,7 +3100,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_dpp" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2700,7 +3159,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_dpp" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3221,16 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_dpp" + : "v_movreld_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2763,7 +3240,7 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) ? "v_movrels_b32_dpp" : "v_movrels_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovrelsB32Vop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VMovrelsB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -2795,7 +3272,16 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_dpp" + : "v_movrels_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2805,7 +3291,7 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) ? "v_movrelsd_b32_dpp" : "v_movrelsd_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovrelsdB32Vop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VMovrelsdB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -2837,7 +3323,16 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_dpp" + : "v_movrelsd_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2847,7 +3342,7 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) ? "v_movrelsd_2_b32_dpp" : "v_movrelsd_2_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovrelsd2B32Vop1), LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VMovrelsd2B32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -2879,7 +3374,16 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_dpp" + : "v_movrelsd_2_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2889,8 +3393,7 @@ VPermlane16SwapB32Vop1::VPermlane16SwapB32Vop1(const MachineInst *inst) ? "v_permlane16_swap_b32_dpp" : "v_permlane16_swap_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlane16SwapB32Vop1), LiteralSupport::None, - 0), + selected_exec_fn(InstructionExecutionId::VPermlane16SwapB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2899,15 +3402,24 @@ VPermlane16SwapB32Vop1::VPermlane16SwapB32Vop1(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_SWAP_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlane16SwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPermlane16SwapB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_swap_b32_dpp" + : "v_permlane16_swap_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_SWAP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2961,7 +3473,15 @@ VTanhBf16Vop1::VTanhBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTanhBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTanhBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_tanh_bf16_dpp" + : "v_tanh_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3024,7 +3544,15 @@ VPrngB32Vop1::VPrngB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPrngB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPrngB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_prng_b32_dpp" + : "v_prng_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3078,7 +3606,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_dpp" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3145,7 +3681,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_dpp" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3212,7 +3756,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_dpp" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3279,7 +3831,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_dpp" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3346,7 +3906,15 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_dpp" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3412,7 +3980,15 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_dpp" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3478,7 +4054,15 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_dpp" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3544,7 +4128,15 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_dpp" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3610,7 +4202,15 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_dpp" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3676,7 +4276,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_dpp" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3743,7 +4352,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_dpp" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3810,7 +4428,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_dpp" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3877,7 +4503,15 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_dpp" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3943,7 +4577,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_dpp" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4010,7 +4652,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_dpp" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4077,7 +4727,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_dpp" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4144,7 +4802,15 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_dpp" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4210,7 +4876,15 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_dpp" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4274,7 +4948,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_dpp" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4341,7 +5024,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_dpp" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4408,7 +5100,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_dpp" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4431,7 +5132,7 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) ? "v_swap_b32_dpp" : "v_swap_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwapB32Vop1), LiteralSupport::None, 0), + selected_exec_fn(InstructionExecutionId::VSwapB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -4440,15 +5141,23 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b32_dpp" + : "v_swap_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4458,7 +5167,7 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) ? "v_swap_b16_dpp" : "v_swap_b16_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwapB16Vop1), LiteralSupport::None, 0), + selected_exec_fn(InstructionExecutionId::VSwapB16Vop1)), vdst(16, OperandType::OPR_VGPR, static_cast(reinterpret_cast(inst)->vdst), true, true), @@ -4469,15 +5178,23 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b16_dpp" + : "v_swap_b16_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4503,7 +5220,7 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) ? "v_swaprel_b32_dpp" : "v_swaprel_b32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwaprelB32Vop1), LiteralSupport::None, 0), + selected_exec_fn(InstructionExecutionId::VSwaprelB32Vop1)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -4512,16 +5229,25 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) src_operands_[0] = &m0; num_src_ = 1; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAPREL_B32 does not support DPP", ""); m0.apply_fieldless_caps(false, false, false); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swaprel_b32_dpp" + : "v_swaprel_b32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4575,7 +5301,15 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_dpp" + : "v_not_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4639,7 +5373,15 @@ VCvtI32I16Vop1::VCvtI32I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_dpp" + : "v_cvt_i32_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4691,7 +5433,15 @@ VCvtU32U16Vop1::VCvtU32U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_dpp" + : "v_cvt_u32_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4741,7 +5491,15 @@ VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_fp8_dpp" + : "v_cvt_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4791,7 +5549,15 @@ VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_bf8_dpp" + : "v_cvt_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4821,15 +5587,24 @@ VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(16, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_fp8_dpp" + : "v_cvt_pk_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4859,15 +5634,24 @@ VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(16, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_bf8_dpp" + : "v_cvt_pk_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4919,7 +5703,16 @@ VCvtF32Bf16Vop1::VCvtF32Bf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_bf16_dpp" + : "v_cvt_f32_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4971,7 +5764,16 @@ VSatPk4I4I8Vop1::VSatPk4I4I8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPk4I4I8Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPk4I4I8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk4_i4_i8_dpp" + : "v_sat_pk4_i4_i8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5036,7 +5838,16 @@ VSatPk4U4U8Vop1::VSatPk4U4U8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPk4U4U8Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPk4U4U8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk4_u4_u8_dpp" + : "v_sat_pk4_u4_u8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5101,7 +5912,16 @@ VCvtPkF16Fp8Vop1::VCvtPkF16Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF16Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF16Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f16_fp8_dpp" + : "v_cvt_pk_f16_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5153,7 +5973,16 @@ VCvtPkF16Bf8Vop1::VCvtPkF16Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF16Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF16Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f16_bf8_dpp" + : "v_cvt_pk_f16_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5205,7 +6034,15 @@ VCvtF16Fp8Vop1::VCvtF16Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_fp8_dpp" + : "v_cvt_f16_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5270,7 +6107,15 @@ VCvtF16Bf8Vop1::VCvtF16Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_bf8_dpp" + : "v_cvt_f16_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5337,7 +6182,15 @@ VRcpBf16Vop1::VRcpBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_bf16_dpp" + : "v_rcp_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5403,7 +6256,15 @@ VSqrtBf16Vop1::VSqrtBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_bf16_dpp" + : "v_sqrt_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5470,7 +6331,15 @@ VRsqBf16Vop1::VRsqBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_bf16_dpp" + : "v_rsq_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5536,7 +6405,15 @@ VLogBf16Vop1::VLogBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_bf16_dpp" + : "v_log_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5602,7 +6479,15 @@ VExpBf16Vop1::VExpBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_bf16_dpp" + : "v_exp_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5668,7 +6553,15 @@ VSinBf16Vop1::VSinBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_bf16_dpp" + : "v_sin_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5734,7 +6627,15 @@ VCosBf16Vop1::VCosBf16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosBf16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosBf16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_bf16_dpp" + : "v_cos_bf16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop2.cpp index b3713b693cec..e66296706722 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -64,7 +63,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_dpp" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -104,15 +112,23 @@ VAddF64Vop2::VAddF64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVAddF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f64_dpp" + : "v_add_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -165,7 +181,15 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_dpp" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -218,7 +242,15 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_dpp" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -271,7 +303,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_dpp" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,15 +351,23 @@ VMulF64Vop2::VMulF64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f64_dpp" + : "v_mul_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -372,7 +420,16 @@ VMulDx9ZeroF32Vop2::VMulDx9ZeroF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_dpp" + : "v_mul_dx9_zero_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -425,7 +482,15 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_dpp" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +543,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_dpp" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +604,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_dpp" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -584,7 +666,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_dpp" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -637,7 +727,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_dpp" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -677,15 +776,23 @@ VMinNumF64Vop2::VMinNumF64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_NUM_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMinNumF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f64_dpp" + : "v_min_num_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_NUM_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -725,15 +832,23 @@ VMaxNumF64Vop2::VMaxNumF64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_NUM_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMaxNumF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f64_dpp" + : "v_max_num_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_NUM_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -786,7 +901,15 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_dpp" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -839,7 +962,15 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_dpp" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -892,7 +1023,15 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_dpp" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -945,7 +1084,15 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_dpp" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -998,7 +1145,15 @@ VMinNumF32Vop2::VMinNumF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f32_dpp" + : "v_min_num_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1051,7 +1206,15 @@ VMaxNumF32Vop2::VMaxNumF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f32_dpp" + : "v_max_num_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1092,15 +1255,23 @@ VFmacF64Vop2::VFmacF64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVFmacF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f64_dpp" + : "v_fmac_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1153,7 +1324,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_dpp" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1206,7 +1386,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_dpp" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1448,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_dpp" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1312,7 +1510,15 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_dpp" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1365,7 +1571,15 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_dpp" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1418,7 +1632,15 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_dpp" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1471,7 +1693,15 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_dpp" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1510,15 +1740,24 @@ VLshlrevB64Vop2::VLshlrevB64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHLREV_B64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b64_dpp" + : "v_lshlrev_b64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHLREV_B64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1577,7 +1816,16 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_dpp" + : "v_add_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1636,7 +1884,16 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_dpp" + : "v_sub_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1695,7 +1952,16 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_dpp" + : "v_subrev_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1705,7 +1971,7 @@ VFmamkF64Vop2::VFmamkF64Vop2(const MachineInst *inst) ? "v_fmamk_f64_dpp" : "v_fmamk_f64_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmamkF64Vop2), LiteralSupport::Literal64), + selected_exec_fn(InstructionExecutionId::VFmamkF64Vop2)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), literal64(64, OperandType::OPR_SIMM64, 0), @@ -1727,16 +1993,24 @@ VFmamkF64Vop2::VFmamkF64Vop2(const MachineInst *inst) (static_cast(reinterpret_cast(inst)[2]) << 32) | reinterpret_cast(inst)[1], true); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } namespace detail { -std::unique_ptr decodeVFmamkF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f64_dpp" + : "v_fmamk_f64_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal64); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1746,7 +2020,7 @@ VFmaakF64Vop2::VFmaakF64Vop2(const MachineInst *inst) ? "v_fmaak_f64_dpp" : "v_fmaak_f64_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaakF64Vop2), LiteralSupport::Literal64), + selected_exec_fn(InstructionExecutionId::VFmaakF64Vop2)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), vsrc1(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vsrc1), @@ -1768,16 +2042,24 @@ VFmaakF64Vop2::VFmaakF64Vop2(const MachineInst *inst) (static_cast(reinterpret_cast(inst)[2]) << 32) | reinterpret_cast(inst)[1], true); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVFmaakF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f64_dpp" + : "v_fmaak_f64_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal64); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1830,7 +2112,15 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_dpp" + : "v_add_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1883,7 +2173,15 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_dpp" + : "v_sub_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1936,7 +2234,16 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_dpp" + : "v_subrev_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1976,15 +2283,23 @@ VAddNcU64Vop2::VAddNcU64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_NC_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVAddNcU64Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u64_dpp" + : "v_add_nc_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_NC_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2024,15 +2339,23 @@ VSubNcU64Vop2::VSubNcU64Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SUB_NC_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVSubNcU64Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u64_dpp" + : "v_sub_nc_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SUB_NC_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2063,16 +2386,24 @@ VMulU64Vop2::VMulU64Vop2(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_U64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulU64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u64_dpp" + : "v_mul_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2126,7 +2457,15 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_dpp" + : "v_fmac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2136,7 +2475,7 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) ? "v_fmamk_f32_dpp" : "v_fmamk_f32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmamkF32Vop2), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmamkF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), literal(32, OperandType::OPR_SIMM32, 0), @@ -2154,16 +2493,24 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) literal = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f32_dpp" + : "v_fmamk_f32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2173,7 +2520,7 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) ? "v_fmaak_f32_dpp" : "v_fmaak_f32_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaakF32Vop2), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaakF32Vop2)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), vsrc1(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vsrc1), @@ -2191,16 +2538,24 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) literal = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f32_dpp" + : "v_fmaak_f32_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2253,7 +2608,16 @@ VCvtPkRtzF16F32Vop2::VCvtPkRtzF16F32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_dpp" + : "v_cvt_pk_rtz_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2311,7 +2675,15 @@ VMinNumF16Vop2::VMinNumF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f16_dpp" + : "v_min_num_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2382,7 +2754,15 @@ VMaxNumF16Vop2::VMaxNumF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f16_dpp" + : "v_max_num_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2453,7 +2833,15 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_dpp" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2523,7 +2911,15 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_dpp" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2593,7 +2989,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_dpp" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2664,7 +3068,15 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_dpp" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2735,7 +3147,15 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_dpp" + : "v_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2757,7 +3177,7 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) ? "v_fmamk_f16_dpp" : "v_fmamk_f16_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmamkF16Vop2), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmamkF16Vop2)), vdst(16, OperandType::OPR_VGPR, static_cast(reinterpret_cast(inst)->vdst), false, true), @@ -2781,16 +3201,24 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM16, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src2); } namespace detail { -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f16_dpp" + : "v_fmamk_f16_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2813,7 +3241,7 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) ? "v_fmaak_f16_dpp" : "v_fmaak_f16_e32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaakF16Vop2), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaakF16Vop2)), vdst(16, OperandType::OPR_VGPR, static_cast(reinterpret_cast(inst)->vdst), false, true), @@ -2837,16 +3265,24 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM16, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f16_dpp" + : "v_fmaak_f16_e32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2917,7 +3353,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_dpp" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2961,16 +3405,24 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(32, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMAC_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fmac_f16_dpp" + : "v_pk_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp index 4e17cb8b99a8..fdc545fa2f7f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -18,7 +17,7 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) ? "v_trunc_f64_e64_dpp" : "v_trunc_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTruncF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VTruncF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -39,14 +38,22 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_e64_dpp" + : "v_trunc_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -56,7 +63,7 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) ? "v_ceil_f64_e64_dpp" : "v_ceil_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCeilF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCeilF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -77,14 +84,22 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_e64_dpp" + : "v_ceil_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -94,7 +109,7 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) ? "v_rndne_f64_e64_dpp" : "v_rndne_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRndneF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRndneF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -115,14 +130,22 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_e64_dpp" + : "v_rndne_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -132,7 +155,7 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) ? "v_floor_f64_e64_dpp" : "v_floor_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFloorF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VFloorF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -153,14 +176,22 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_e64_dpp" + : "v_floor_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -170,7 +201,7 @@ VTanhF32Vop3::VTanhF32Vop3(const MachineInst *inst) ? "v_tanh_f32_e64_dpp" : "v_tanh_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTanhF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VTanhF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -203,7 +234,15 @@ VTanhF32Vop3::VTanhF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTanhF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTanhF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_tanh_f32_e64_dpp" + : "v_tanh_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -213,7 +252,7 @@ VTanhF16Vop3::VTanhF16Vop3(const MachineInst *inst) ? "v_tanh_f16_e64_dpp" : "v_tanh_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTanhF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VTanhF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -250,7 +289,15 @@ VTanhF16Vop3::VTanhF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTanhF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTanhF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_tanh_f16_e64_dpp" + : "v_tanh_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -272,7 +319,7 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) ? "v_fract_f32_e64_dpp" : "v_fract_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFractF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VFractF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -305,7 +352,15 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_e64_dpp" + : "v_fract_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +370,7 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) ? "v_trunc_f32_e64_dpp" : "v_trunc_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTruncF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VTruncF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -348,7 +403,15 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_e64_dpp" + : "v_trunc_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -358,7 +421,7 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) ? "v_ceil_f32_e64_dpp" : "v_ceil_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCeilF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCeilF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -391,7 +454,15 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_e64_dpp" + : "v_ceil_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +472,7 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) ? "v_rndne_f32_e64_dpp" : "v_rndne_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRndneF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRndneF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -434,7 +505,15 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_e64_dpp" + : "v_rndne_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -444,7 +523,7 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) ? "v_floor_f32_e64_dpp" : "v_floor_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFloorF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VFloorF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -477,7 +556,15 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_e64_dpp" + : "v_floor_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +574,7 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) ? "v_exp_f32_e64_dpp" : "v_exp_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VExpF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VExpF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -520,7 +607,15 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_e64_dpp" + : "v_exp_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -530,7 +625,7 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) ? "v_log_f32_e64_dpp" : "v_log_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLogF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VLogF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -563,7 +658,15 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_e64_dpp" + : "v_log_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -573,7 +676,7 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) ? "v_rcp_f32_e64_dpp" : "v_rcp_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRcpF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRcpF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -606,7 +709,15 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_e64_dpp" + : "v_rcp_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -616,8 +727,7 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) ? "v_rcp_iflag_f32_e64_dpp" : "v_rcp_iflag_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRcpIflagF32Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VRcpIflagF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -650,7 +760,16 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_e64_dpp" + : "v_rcp_iflag_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -660,7 +779,7 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) ? "v_rsq_f32_e64_dpp" : "v_rsq_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRsqF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRsqF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -693,7 +812,15 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_e64_dpp" + : "v_rsq_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -703,7 +830,7 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) ? "v_rcp_f64_e64_dpp" : "v_rcp_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRcpF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRcpF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -715,15 +842,23 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_e64_dpp" + : "v_rcp_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -733,7 +868,7 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) ? "v_rsq_f64_e64_dpp" : "v_rsq_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRsqF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRsqF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -745,15 +880,23 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_e64_dpp" + : "v_rsq_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -763,7 +906,7 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) ? "v_sqrt_f32_e64_dpp" : "v_sqrt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSqrtF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSqrtF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -796,7 +939,15 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_e64_dpp" + : "v_sqrt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -806,7 +957,7 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) ? "v_sqrt_f64_e64_dpp" : "v_sqrt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSqrtF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSqrtF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -818,15 +969,23 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_e64_dpp" + : "v_sqrt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -836,7 +995,7 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) ? "v_sin_f32_e64_dpp" : "v_sin_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSinF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSinF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -869,7 +1028,15 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_e64_dpp" + : "v_sin_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -879,7 +1046,7 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) ? "v_cos_f32_e64_dpp" : "v_cos_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCosF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCosF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -912,7 +1079,15 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_e64_dpp" + : "v_cos_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -922,7 +1097,7 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) ? "v_not_b32_e64_dpp" : "v_not_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VNotB32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VNotB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -955,7 +1130,15 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_e64_dpp" + : "v_not_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -965,7 +1148,7 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) ? "v_bfrev_b32_e64_dpp" : "v_bfrev_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBfrevB32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VBfrevB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -998,7 +1181,15 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_e64_dpp" + : "v_bfrev_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1008,7 +1199,7 @@ VClzI32U32Vop3::VClzI32U32Vop3(const MachineInst *inst) ? "v_clz_i32_u32_e64_dpp" : "v_clz_i32_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VClzI32U32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VClzI32U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1041,7 +1232,15 @@ VClzI32U32Vop3::VClzI32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_e64_dpp" + : "v_clz_i32_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1051,7 +1250,7 @@ VCtzI32B32Vop3::VCtzI32B32Vop3(const MachineInst *inst) ? "v_ctz_i32_b32_e64_dpp" : "v_ctz_i32_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCtzI32B32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCtzI32B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1084,7 +1283,15 @@ VCtzI32B32Vop3::VCtzI32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_e64_dpp" + : "v_ctz_i32_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1094,7 +1301,7 @@ VClsI32Vop3::VClsI32Vop3(const MachineInst *inst) ? "v_cls_i32_e64_dpp" : "v_cls_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VClsI32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VClsI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1127,7 +1334,15 @@ VClsI32Vop3::VClsI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_e64_dpp" + : "v_cls_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1352,7 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) ? "v_fract_f64_e64_dpp" : "v_fract_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFractF64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VFractF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1158,14 +1373,22 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_e64_dpp" + : "v_fract_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1175,7 +1398,7 @@ VTanhBf16Vop3::VTanhBf16Vop3(const MachineInst *inst) ? "v_tanh_bf16_e64_dpp" : "v_tanh_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTanhBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VTanhBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1212,7 +1435,15 @@ VTanhBf16Vop3::VTanhBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTanhBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTanhBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_tanh_bf16_e64_dpp" + : "v_tanh_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1235,7 +1466,7 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) ? "v_rcp_f16_e64_dpp" : "v_rcp_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRcpF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRcpF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1272,7 +1503,15 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_e64_dpp" + : "v_rcp_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1294,7 +1533,7 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) ? "v_sqrt_f16_e64_dpp" : "v_sqrt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSqrtF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSqrtF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1331,7 +1570,15 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_e64_dpp" + : "v_sqrt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1353,7 +1600,7 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) ? "v_rsq_f16_e64_dpp" : "v_rsq_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRsqF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRsqF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1390,7 +1637,15 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_e64_dpp" + : "v_rsq_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1412,7 +1667,7 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) ? "v_log_f16_e64_dpp" : "v_log_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLogF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VLogF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1449,7 +1704,15 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_e64_dpp" + : "v_log_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1471,7 +1734,7 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) ? "v_exp_f16_e64_dpp" : "v_exp_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VExpF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VExpF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1508,7 +1771,15 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_e64_dpp" + : "v_exp_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1530,7 +1801,7 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) ? "v_floor_f16_e64_dpp" : "v_floor_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFloorF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VFloorF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1567,7 +1838,15 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_e64_dpp" + : "v_floor_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1590,7 +1869,7 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) ? "v_ceil_f16_e64_dpp" : "v_ceil_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCeilF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCeilF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1627,7 +1906,15 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_e64_dpp" + : "v_ceil_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1649,7 +1936,7 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) ? "v_trunc_f16_e64_dpp" : "v_trunc_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTruncF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VTruncF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1686,7 +1973,15 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_e64_dpp" + : "v_trunc_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1709,7 +2004,7 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) ? "v_rndne_f16_e64_dpp" : "v_rndne_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRndneF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRndneF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1746,7 +2041,15 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_e64_dpp" + : "v_rndne_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1769,7 +2072,7 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) ? "v_fract_f16_e64_dpp" : "v_fract_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFractF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VFractF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1806,7 +2109,15 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_e64_dpp" + : "v_fract_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1829,7 +2140,7 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) ? "v_sin_f16_e64_dpp" : "v_sin_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSinF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSinF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1866,7 +2177,15 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_e64_dpp" + : "v_sin_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1888,7 +2207,7 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) ? "v_cos_f16_e64_dpp" : "v_cos_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCosF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCosF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1925,7 +2244,15 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_e64_dpp" + : "v_cos_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1947,7 +2274,7 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) ? "v_not_b16_e64_dpp" : "v_not_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VNotB16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VNotB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1984,7 +2311,15 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_e64_dpp" + : "v_not_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2341,7 @@ VRcpBf16Vop3::VRcpBf16Vop3(const MachineInst *inst) ? "v_rcp_bf16_e64_dpp" : "v_rcp_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRcpBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRcpBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2043,7 +2378,15 @@ VRcpBf16Vop3::VRcpBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_bf16_e64_dpp" + : "v_rcp_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2065,7 +2408,7 @@ VSqrtBf16Vop3::VSqrtBf16Vop3(const MachineInst *inst) ? "v_sqrt_bf16_e64_dpp" : "v_sqrt_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSqrtBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSqrtBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2102,7 +2445,15 @@ VSqrtBf16Vop3::VSqrtBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_bf16_e64_dpp" + : "v_sqrt_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2125,7 +2476,7 @@ VRsqBf16Vop3::VRsqBf16Vop3(const MachineInst *inst) ? "v_rsq_bf16_e64_dpp" : "v_rsq_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VRsqBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VRsqBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2162,7 +2513,15 @@ VRsqBf16Vop3::VRsqBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_bf16_e64_dpp" + : "v_rsq_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2184,7 +2543,7 @@ VLogBf16Vop3::VLogBf16Vop3(const MachineInst *inst) ? "v_log_bf16_e64_dpp" : "v_log_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLogBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VLogBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2221,7 +2580,15 @@ VLogBf16Vop3::VLogBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_bf16_e64_dpp" + : "v_log_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2243,7 +2610,7 @@ VExpBf16Vop3::VExpBf16Vop3(const MachineInst *inst) ? "v_exp_bf16_e64_dpp" : "v_exp_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VExpBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VExpBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2280,7 +2647,15 @@ VExpBf16Vop3::VExpBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_bf16_e64_dpp" + : "v_exp_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2302,7 +2677,7 @@ VSinBf16Vop3::VSinBf16Vop3(const MachineInst *inst) ? "v_sin_bf16_e64_dpp" : "v_sin_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSinBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSinBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2339,7 +2714,15 @@ VSinBf16Vop3::VSinBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_bf16_e64_dpp" + : "v_sin_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2361,7 +2744,7 @@ VCosBf16Vop3::VCosBf16Vop3(const MachineInst *inst) ? "v_cos_bf16_e64_dpp" : "v_cos_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCosBf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCosBf16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -2398,7 +2781,15 @@ VCosBf16Vop3::VCosBf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosBf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosBf16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_bf16_e64_dpp" + : "v_cos_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2420,7 +2811,7 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) ? "v_add_f64_e64_dpp" : "v_add_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2448,15 +2839,23 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f64_e64_dpp" + : "v_add_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2466,7 +2865,7 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) ? "v_add_f32_e64_dpp" : "v_add_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2506,7 +2905,15 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_e64_dpp" + : "v_add_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2516,7 +2923,7 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) ? "v_sub_f32_e64_dpp" : "v_sub_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2556,7 +2963,15 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_e64_dpp" + : "v_sub_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2566,7 +2981,7 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) ? "v_subrev_f32_e64_dpp" : "v_subrev_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubrevF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubrevF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2606,7 +3021,15 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_e64_dpp" + : "v_subrev_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2616,7 +3039,7 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) ? "v_mul_f64_e64_dpp" : "v_mul_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2644,15 +3067,23 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f64_e64_dpp" + : "v_mul_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2662,8 +3093,7 @@ VMulDx9ZeroF32Vop3::VMulDx9ZeroF32Vop3(const MachineInst *inst) ? "v_mul_dx9_zero_f32_e64_dpp" : "v_mul_dx9_zero_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulDx9ZeroF32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VMulDx9ZeroF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2703,7 +3133,16 @@ VMulDx9ZeroF32Vop3::VMulDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_e64_dpp" + : "v_mul_dx9_zero_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2713,7 +3152,7 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) ? "v_mul_f32_e64_dpp" : "v_mul_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2753,7 +3192,15 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_e64_dpp" + : "v_mul_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2763,7 +3210,7 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) ? "v_mul_i32_i24_e64_dpp" : "v_mul_i32_i24", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulI32I24Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulI32I24Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2803,7 +3250,15 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_e64_dpp" + : "v_mul_i32_i24", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2813,8 +3268,7 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) ? "v_mul_hi_i32_i24_e64_dpp" : "v_mul_hi_i32_i24", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulHiI32I24Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VMulHiI32I24Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2854,7 +3308,16 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_e64_dpp" + : "v_mul_hi_i32_i24", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2864,7 +3327,7 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) ? "v_mul_u32_u24_e64_dpp" : "v_mul_u32_u24", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulU32U24Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulU32U24Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2904,7 +3367,15 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_e64_dpp" + : "v_mul_u32_u24", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2914,8 +3385,7 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) ? "v_mul_hi_u32_u24_e64_dpp" : "v_mul_hi_u32_u24", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulHiU32U24Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VMulHiU32U24Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2955,7 +3425,16 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_e64_dpp" + : "v_mul_hi_u32_u24", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2965,7 +3444,7 @@ VMinNumF64Vop3::VMinNumF64Vop3(const MachineInst *inst) ? "v_min_num_f64_e64_dpp" : "v_min_num_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinNumF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinNumF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2993,15 +3472,23 @@ VMinNumF64Vop3::VMinNumF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_NUM_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMinNumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f64_e64_dpp" + : "v_min_num_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_NUM_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -3011,7 +3498,7 @@ VMaxNumF64Vop3::VMaxNumF64Vop3(const MachineInst *inst) ? "v_max_num_f64_e64_dpp" : "v_max_num_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxNumF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxNumF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3039,15 +3526,23 @@ VMaxNumF64Vop3::VMaxNumF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_NUM_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMaxNumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f64_e64_dpp" + : "v_max_num_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_NUM_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -3057,7 +3552,7 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) ? "v_min_i32_e64_dpp" : "v_min_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3097,7 +3592,15 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_e64_dpp" + : "v_min_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3107,7 +3610,7 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) ? "v_max_i32_e64_dpp" : "v_max_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3147,7 +3650,15 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_e64_dpp" + : "v_max_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3157,7 +3668,7 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) ? "v_min_u32_e64_dpp" : "v_min_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3197,7 +3708,15 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_e64_dpp" + : "v_min_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3207,7 +3726,7 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) ? "v_max_u32_e64_dpp" : "v_max_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3247,7 +3766,15 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_e64_dpp" + : "v_max_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3257,7 +3784,7 @@ VMinNumF32Vop3::VMinNumF32Vop3(const MachineInst *inst) ? "v_min_num_f32_e64_dpp" : "v_min_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinNumF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinNumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3297,7 +3824,15 @@ VMinNumF32Vop3::VMinNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f32_e64_dpp" + : "v_min_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3307,7 +3842,7 @@ VMaxNumF32Vop3::VMaxNumF32Vop3(const MachineInst *inst) ? "v_max_num_f32_e64_dpp" : "v_max_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxNumF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxNumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3347,7 +3882,15 @@ VMaxNumF32Vop3::VMaxNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f32_e64_dpp" + : "v_max_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3357,7 +3900,7 @@ VFmacF64Vop3::VFmacF64Vop3(const MachineInst *inst) ? "v_fmac_f64_e64_dpp" : "v_fmac_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmacF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VFmacF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3386,15 +3929,23 @@ VFmacF64Vop3::VFmacF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVFmacF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f64_e64_dpp" + : "v_fmac_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -3404,7 +3955,7 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) ? "v_lshlrev_b32_e64_dpp" : "v_lshlrev_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshlrevB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLshlrevB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3444,7 +3995,16 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_e64_dpp" + : "v_lshlrev_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3454,7 +4014,7 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) ? "v_lshrrev_b32_e64_dpp" : "v_lshrrev_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshrrevB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLshrrevB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3494,7 +4054,16 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_e64_dpp" + : "v_lshrrev_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3504,7 +4073,7 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) ? "v_ashrrev_i32_e64_dpp" : "v_ashrrev_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAshrrevI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAshrrevI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3544,7 +4113,16 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_e64_dpp" + : "v_ashrrev_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3554,7 +4132,7 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) ? "v_and_b32_e64_dpp" : "v_and_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAndB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAndB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3594,7 +4172,15 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_e64_dpp" + : "v_and_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3604,7 +4190,7 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) ? "v_or_b32_e64_dpp" : "v_or_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VOrB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VOrB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3644,7 +4230,15 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_e64_dpp" + : "v_or_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3654,7 +4248,7 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) ? "v_xor_b32_e64_dpp" : "v_xor_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VXorB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VXorB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3694,7 +4288,15 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_e64_dpp" + : "v_xor_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3704,7 +4306,7 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) ? "v_xnor_b32_e64_dpp" : "v_xnor_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VXnorB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VXnorB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3744,7 +4346,15 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_e64_dpp" + : "v_xnor_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3754,7 +4364,7 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) ? "v_lshlrev_b64_e64_dpp" : "v_lshlrev_b64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshlrevB64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLshlrevB64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3781,15 +4391,24 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHLREV_B64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b64_e64_dpp" + : "v_lshlrev_b64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHLREV_B64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -3799,7 +4418,7 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) ? "v_add_nc_u32_e64_dpp" : "v_add_nc_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddNcU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddNcU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3839,7 +4458,15 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_e64_dpp" + : "v_add_nc_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3849,7 +4476,7 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) ? "v_sub_nc_u32_e64_dpp" : "v_sub_nc_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubNcU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubNcU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3889,7 +4516,15 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_e64_dpp" + : "v_sub_nc_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3899,8 +4534,7 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) ? "v_subrev_nc_u32_e64_dpp" : "v_subrev_nc_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubrevNcU32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VSubrevNcU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3940,7 +4574,16 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_e64_dpp" + : "v_subrev_nc_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3950,7 +4593,7 @@ VAddNcU64Vop3::VAddNcU64Vop3(const MachineInst *inst) ? "v_add_nc_u64_e64_dpp" : "v_add_nc_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddNcU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddNcU64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3978,15 +4621,23 @@ VAddNcU64Vop3::VAddNcU64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_NC_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVAddNcU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u64_e64_dpp" + : "v_add_nc_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_NC_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -3996,7 +4647,7 @@ VSubNcU64Vop3::VSubNcU64Vop3(const MachineInst *inst) ? "v_sub_nc_u64_e64_dpp" : "v_sub_nc_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubNcU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubNcU64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4024,15 +4675,23 @@ VSubNcU64Vop3::VSubNcU64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SUB_NC_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVSubNcU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u64_e64_dpp" + : "v_sub_nc_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SUB_NC_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -4042,7 +4701,7 @@ VMulU64Vop3::VMulU64Vop3(const MachineInst *inst) ? "v_mul_u64_e64_dpp" : "v_mul_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulU64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4061,16 +4720,24 @@ VMulU64Vop3::VMulU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_U64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u64_e64_dpp" + : "v_mul_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4080,7 +4747,7 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) ? "v_fmac_f32_e64_dpp" : "v_fmac_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmacF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VFmacF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4121,7 +4788,15 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_e64_dpp" + : "v_fmac_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4131,7 +4806,7 @@ VMinNumF16Vop3::VMinNumF16Vop3(const MachineInst *inst) ? "v_min_num_f16_e64_dpp" : "v_min_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinNumF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinNumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4179,7 +4854,15 @@ VMinNumF16Vop3::VMinNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f16_e64_dpp" + : "v_min_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4202,7 +4885,7 @@ VMaxNumF16Vop3::VMaxNumF16Vop3(const MachineInst *inst) ? "v_max_num_f16_e64_dpp" : "v_max_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxNumF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxNumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4250,7 +4933,15 @@ VMaxNumF16Vop3::VMaxNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f16_e64_dpp" + : "v_max_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4273,7 +4964,7 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) ? "v_add_f16_e64_dpp" : "v_add_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4321,7 +5012,15 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_e64_dpp" + : "v_add_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4343,7 +5042,7 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) ? "v_sub_f16_e64_dpp" : "v_sub_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4391,7 +5090,15 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_e64_dpp" + : "v_sub_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4413,7 +5120,7 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) ? "v_subrev_f16_e64_dpp" : "v_subrev_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubrevF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubrevF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4461,7 +5168,15 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_e64_dpp" + : "v_subrev_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4484,7 +5199,7 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) ? "v_mul_f16_e64_dpp" : "v_mul_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4532,7 +5247,15 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_e64_dpp" + : "v_mul_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4554,7 +5277,7 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) ? "v_fmac_f16_e64_dpp" : "v_fmac_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmacF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VFmacF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4603,7 +5326,15 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_e64_dpp" + : "v_fmac_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4625,7 +5356,7 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) ? "v_ldexp_f16_e64_dpp" : "v_ldexp_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLdexpF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLdexpF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4673,7 +5404,15 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_e64_dpp" + : "v_ldexp_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4696,7 +5435,7 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) ? "v_div_fixup_f32_e64_dpp" : "v_div_fixup_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivFixupF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivFixupF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4719,9 +5458,6 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -4729,7 +5465,19 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f32_e64_dpp" + : "v_div_fixup_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4739,7 +5487,7 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) ? "v_div_fixup_f64_e64_dpp" : "v_div_fixup_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivFixupF64Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivFixupF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4774,8 +5522,6 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -4783,7 +5529,18 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f64_e64_dpp" + : "v_div_fixup_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -4793,7 +5550,7 @@ VBitop3B16Vop3::VBitop3B16Vop3(const MachineInst *inst) ? "v_bitop3_b16_e64_dpp" : "v_bitop3_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBitop3B16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VBitop3B16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4852,7 +5609,15 @@ VBitop3B16Vop3::VBitop3B16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBitop3B16Vop3(const MachineInst *opcode) { +DecodeResult decodeVBitop3B16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bitop3_b16_e64_dpp" + : "v_bitop3_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4875,7 +5640,7 @@ VBitop3B32Vop3::VBitop3B32Vop3(const MachineInst *inst) ? "v_bitop3_b32_e64_dpp" : "v_bitop3_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBitop3B32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VBitop3B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4922,7 +5687,15 @@ VBitop3B32Vop3::VBitop3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBitop3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBitop3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bitop3_b32_e64_dpp" + : "v_bitop3_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4932,7 +5705,7 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) ? "v_div_fmas_f32_e64_dpp" : "v_div_fmas_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivFmasF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivFmasF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4957,9 +5730,6 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F32 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4968,7 +5738,19 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f32_e64_dpp" + : "v_div_fmas_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4978,7 +5760,7 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) ? "v_div_fmas_f64_e64_dpp" : "v_div_fmas_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivFmasF64Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivFmasF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5015,8 +5797,6 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F64 does not support DPP8", ""); vcc.apply_fieldless_caps(false, false, false); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -5025,7 +5805,18 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f64_e64_dpp" + : "v_div_fmas_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -5035,7 +5826,7 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) ? "v_div_fixup_f16_e64_dpp" : "v_div_fixup_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivFixupF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivFixupF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5094,7 +5885,16 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f16_e64_dpp" + : "v_div_fixup_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5117,26 +5917,35 @@ VSExpF32Vop3::VSExpF32Vop3(const MachineInst *inst) ? "v_s_exp_f32_e64_dpp" : "v_s_exp_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSExpF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSExpF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_EXP_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_EXP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_exp_f32_e64_dpp" + : "v_s_exp_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5146,27 +5955,36 @@ VSExpF16Vop3::VSExpF16Vop3(const MachineInst *inst) ? "v_s_exp_f16_e64_dpp" : "v_s_exp_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSExpF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSExpF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_EXP_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_EXP_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_exp_f16_e64_dpp" + : "v_s_exp_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5176,26 +5994,35 @@ VSLogF32Vop3::VSLogF32Vop3(const MachineInst *inst) ? "v_s_log_f32_e64_dpp" : "v_s_log_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSLogF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSLogF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_LOG_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_LOG_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_log_f32_e64_dpp" + : "v_s_log_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5205,27 +6032,36 @@ VSLogF16Vop3::VSLogF16Vop3(const MachineInst *inst) ? "v_s_log_f16_e64_dpp" : "v_s_log_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSLogF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSLogF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_LOG_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_LOG_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_log_f16_e64_dpp" + : "v_s_log_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5235,26 +6071,35 @@ VSRcpF32Vop3::VSRcpF32Vop3(const MachineInst *inst) ? "v_s_rcp_f32_e64_dpp" : "v_s_rcp_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSRcpF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSRcpF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RCP_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RCP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rcp_f32_e64_dpp" + : "v_s_rcp_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5264,27 +6109,36 @@ VSRcpF16Vop3::VSRcpF16Vop3(const MachineInst *inst) ? "v_s_rcp_f16_e64_dpp" : "v_s_rcp_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSRcpF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSRcpF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RCP_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RCP_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rcp_f16_e64_dpp" + : "v_s_rcp_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5294,26 +6148,35 @@ VSRsqF32Vop3::VSRsqF32Vop3(const MachineInst *inst) ? "v_s_rsq_f32_e64_dpp" : "v_s_rsq_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSRsqF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSRsqF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RSQ_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RSQ_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rsq_f32_e64_dpp" + : "v_s_rsq_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5323,27 +6186,36 @@ VSRsqF16Vop3::VSRsqF16Vop3(const MachineInst *inst) ? "v_s_rsq_f16_e64_dpp" : "v_s_rsq_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSRsqF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSRsqF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RSQ_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RSQ_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rsq_f16_e64_dpp" + : "v_s_rsq_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5353,26 +6225,35 @@ VSSqrtF32Vop3::VSSqrtF32Vop3(const MachineInst *inst) ? "v_s_sqrt_f32_e64_dpp" : "v_s_sqrt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSSqrtF32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSSqrtF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_SQRT_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_SQRT_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_sqrt_f32_e64_dpp" + : "v_s_sqrt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5382,27 +6263,36 @@ VSSqrtF16Vop3::VSSqrtF16Vop3(const MachineInst *inst) ? "v_s_sqrt_f16_e64_dpp" : "v_s_sqrt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSSqrtF16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSSqrtF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_SQRT_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_SQRT_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_sqrt_f16_e64_dpp" + : "v_s_sqrt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5412,7 +6302,7 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) ? "v_add_nc_u16_e64_dpp" : "v_add_nc_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddNcU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddNcU16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5460,7 +6350,15 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u16_e64_dpp" + : "v_add_nc_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5483,7 +6381,7 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) ? "v_sub_nc_u16_e64_dpp" : "v_sub_nc_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubNcU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubNcU16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5531,7 +6429,15 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u16_e64_dpp" + : "v_sub_nc_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5554,7 +6460,7 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) ? "v_mul_lo_u16_e64_dpp" : "v_mul_lo_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulLoU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulLoU16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5602,7 +6508,15 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u16_e64_dpp" + : "v_mul_lo_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5625,7 +6539,7 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) ? "v_max_u16_e64_dpp" : "v_max_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxU16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5673,7 +6587,15 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u16_e64_dpp" + : "v_max_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5695,7 +6617,7 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) ? "v_max_i16_e64_dpp" : "v_max_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxI16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5743,7 +6665,15 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i16_e64_dpp" + : "v_max_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5765,7 +6695,7 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) ? "v_min_u16_e64_dpp" : "v_min_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinU16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5813,7 +6743,15 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u16_e64_dpp" + : "v_min_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5835,7 +6773,7 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) ? "v_min_i16_e64_dpp" : "v_min_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinI16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5883,7 +6821,15 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i16_e64_dpp" + : "v_min_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5905,7 +6851,7 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) ? "v_add_nc_i16_e64_dpp" : "v_add_nc_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddNcI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddNcI16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -5953,7 +6899,15 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i16_e64_dpp" + : "v_add_nc_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5976,7 +6930,7 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) ? "v_sub_nc_i16_e64_dpp" : "v_sub_nc_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubNcI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubNcI16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6024,7 +6978,15 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i16_e64_dpp" + : "v_sub_nc_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6047,7 +7009,7 @@ VMinU64Vop3::VMinU64Vop3(const MachineInst *inst) ? "v_min_u64_e64_dpp" : "v_min_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinU64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6075,15 +7037,23 @@ VMinU64Vop3::VMinU64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMinU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u64_e64_dpp" + : "v_min_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6093,7 +7063,7 @@ VMaxU64Vop3::VMaxU64Vop3(const MachineInst *inst) ? "v_max_u64_e64_dpp" : "v_max_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxU64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6121,15 +7091,23 @@ VMaxU64Vop3::VMaxU64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMaxU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u64_e64_dpp" + : "v_max_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6139,7 +7117,7 @@ VMinI64Vop3::VMinI64Vop3(const MachineInst *inst) ? "v_min_i64_e64_dpp" : "v_min_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinI64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6167,15 +7145,23 @@ VMinI64Vop3::VMinI64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_I64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMinI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i64_e64_dpp" + : "v_min_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_I64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6185,7 +7171,7 @@ VMaxI64Vop3::VMaxI64Vop3(const MachineInst *inst) ? "v_max_i64_e64_dpp" : "v_max_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaxI64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6213,15 +7199,23 @@ VMaxI64Vop3::VMaxI64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_I64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMaxI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i64_e64_dpp" + : "v_max_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_I64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6231,7 +7225,7 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) ? "v_ldexp_f32_e64_dpp" : "v_ldexp_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLdexpF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLdexpF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6271,7 +7265,15 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f32_e64_dpp" + : "v_ldexp_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6281,7 +7283,7 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) ? "v_bfm_b32_e64_dpp" : "v_bfm_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBfmB32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VBfmB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6321,7 +7323,15 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfm_b32_e64_dpp" + : "v_bfm_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6331,7 +7341,7 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) ? "v_bcnt_u32_b32_e64_dpp" : "v_bcnt_u32_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBcntU32B32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VBcntU32B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6371,7 +7381,16 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bcnt_u32_b32_e64_dpp" + : "v_bcnt_u32_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6381,8 +7400,7 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) ? "v_mbcnt_lo_u32_b32_e64_dpp" : "v_mbcnt_lo_u32_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMbcntLoU32B32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VMbcntLoU32B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6422,7 +7440,16 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_lo_u32_b32_e64_dpp" + : "v_mbcnt_lo_u32_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6432,8 +7459,7 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) ? "v_mbcnt_hi_u32_b32_e64_dpp" : "v_mbcnt_hi_u32_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMbcntHiU32B32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VMbcntHiU32B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6473,7 +7499,16 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_hi_u32_b32_e64_dpp" + : "v_mbcnt_hi_u32_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6483,7 +7518,7 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) ? "v_sub_nc_i32_e64_dpp" : "v_sub_nc_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubNcI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubNcI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6523,7 +7558,15 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i32_e64_dpp" + : "v_sub_nc_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6533,7 +7576,7 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) ? "v_add_nc_i32_e64_dpp" : "v_add_nc_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddNcI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddNcI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6573,7 +7616,15 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i32_e64_dpp" + : "v_add_nc_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6583,7 +7634,7 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) ? "v_ldexp_f64_e64_dpp" : "v_ldexp_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLdexpF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLdexpF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6610,15 +7661,23 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LDEXP_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f64_e64_dpp" + : "v_ldexp_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LDEXP_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6628,7 +7687,7 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) ? "v_mul_lo_u32_e64_dpp" : "v_mul_lo_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulLoU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulLoU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6654,15 +7713,23 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_LO_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u32_e64_dpp" + : "v_mul_lo_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_LO_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6672,7 +7739,7 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) ? "v_mul_hi_u32_e64_dpp" : "v_mul_hi_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulHiU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulHiU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6698,15 +7765,23 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_e64_dpp" + : "v_mul_hi_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6716,7 +7791,7 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) ? "v_mul_hi_i32_e64_dpp" : "v_mul_hi_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMulHiI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMulHiI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6742,15 +7817,23 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_I32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_e64_dpp" + : "v_mul_hi_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_I32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -6760,7 +7843,7 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) ? "v_lshlrev_b16_e64_dpp" : "v_lshlrev_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshlrevB16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLshlrevB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6808,7 +7891,16 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b16_e64_dpp" + : "v_lshlrev_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6831,7 +7923,7 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) ? "v_lshrrev_b16_e64_dpp" : "v_lshrrev_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshrrevB16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLshrrevB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6879,7 +7971,16 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b16_e64_dpp" + : "v_lshrrev_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6902,7 +8003,7 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) ? "v_ashrrev_i16_e64_dpp" : "v_ashrrev_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAshrrevI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAshrrevI16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -6950,7 +8051,16 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i16_e64_dpp" + : "v_ashrrev_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6973,7 +8083,7 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) ? "v_lshrrev_b64_e64_dpp" : "v_lshrrev_b64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshrrevB64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VLshrrevB64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7000,15 +8110,24 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHRREV_B64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b64_e64_dpp" + : "v_lshrrev_b64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHRREV_B64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7018,7 +8137,7 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) ? "v_ashrrev_i64_e64_dpp" : "v_ashrrev_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAshrrevI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAshrrevI64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7045,15 +8164,24 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ASHRREV_I64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i64_e64_dpp" + : "v_ashrrev_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ASHRREV_I64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7063,7 +8191,7 @@ VMinimumF64Vop3::VMinimumF64Vop3(const MachineInst *inst) ? "v_minimum_f64_e64_dpp" : "v_minimum_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimumF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinimumF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7091,15 +8219,24 @@ VMinimumF64Vop3::VMinimumF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MINIMUM_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMinimumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimumF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum_f64_e64_dpp" + : "v_minimum_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MINIMUM_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7109,7 +8246,7 @@ VMaximumF64Vop3::VMaximumF64Vop3(const MachineInst *inst) ? "v_maximum_f64_e64_dpp" : "v_maximum_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximumF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaximumF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7137,15 +8274,24 @@ VMaximumF64Vop3::VMaximumF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAXIMUM_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVMaximumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum_f64_e64_dpp" + : "v_maximum_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAXIMUM_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7155,7 +8301,7 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) ? "v_and_b16_e64_dpp" : "v_and_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAndB16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAndB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7203,7 +8349,15 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b16_e64_dpp" + : "v_and_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7225,7 +8379,7 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) ? "v_or_b16_e64_dpp" : "v_or_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VOrB16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VOrB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7273,7 +8427,15 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b16_e64_dpp" + : "v_or_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7295,7 +8457,7 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) ? "v_xor_b16_e64_dpp" : "v_xor_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VXorB16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VXorB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7343,7 +8505,15 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b16_e64_dpp" + : "v_xor_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7365,7 +8535,7 @@ VMinimumF32Vop3::VMinimumF32Vop3(const MachineInst *inst) ? "v_minimum_f32_e64_dpp" : "v_minimum_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimumF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinimumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7405,7 +8575,16 @@ VMinimumF32Vop3::VMinimumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum_f32_e64_dpp" + : "v_minimum_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7415,7 +8594,7 @@ VMaximumF32Vop3::VMaximumF32Vop3(const MachineInst *inst) ? "v_maximum_f32_e64_dpp" : "v_maximum_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximumF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaximumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7455,7 +8634,16 @@ VMaximumF32Vop3::VMaximumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum_f32_e64_dpp" + : "v_maximum_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7465,7 +8653,7 @@ VMinimumF16Vop3::VMinimumF16Vop3(const MachineInst *inst) ? "v_minimum_f16_e64_dpp" : "v_minimum_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimumF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMinimumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7513,7 +8701,16 @@ VMinimumF16Vop3::VMinimumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum_f16_e64_dpp" + : "v_minimum_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7536,7 +8733,7 @@ VMaximumF16Vop3::VMaximumF16Vop3(const MachineInst *inst) ? "v_maximum_f16_e64_dpp" : "v_maximum_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximumF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VMaximumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -7584,7 +8781,16 @@ VMaximumF16Vop3::VMaximumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum_f16_e64_dpp" + : "v_maximum_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7607,8 +8813,7 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) ? "v_add_co_ci_u32_e64_dpp" : "v_add_co_ci_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddCoCiU32Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAddCoCiU32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7652,7 +8857,17 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_e64_dpp" + : "v_add_co_ci_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7662,8 +8877,7 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) ? "v_sub_co_ci_u32_e64_dpp" : "v_sub_co_ci_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubCoCiU32Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VSubCoCiU32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7707,7 +8921,17 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_e64_dpp" + : "v_sub_co_ci_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7717,8 +8941,7 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) ? "v_subrev_co_ci_u32_e64_dpp" : "v_subrev_co_ci_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubrevCoCiU32Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VSubrevCoCiU32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7762,7 +8985,17 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_e64_dpp" + : "v_subrev_co_ci_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7772,8 +9005,7 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) ? "v_div_scale_f32_e64_dpp" : "v_div_scale_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivScaleF32Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivScaleF32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7798,9 +9030,6 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) src2 = Operand(32, OperandType::OPR_SIMM32, static_cast( reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7808,7 +9037,21 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f32_e64_dpp" + : "v_div_scale_f32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7818,8 +9061,7 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) ? "v_div_scale_f64_e64_dpp" : "v_div_scale_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDivScaleF64Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDivScaleF64Vop3SdstEnc)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7859,8 +9101,6 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7868,7 +9108,20 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f64_e64_dpp" + : "v_div_scale_f64", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7878,8 +9131,7 @@ VMadCoU64U32Vop3SdstEnc::VMadCoU64U32Vop3SdstEnc(const MachineInst *inst) ? "v_mad_co_u64_u32_e64_dpp" : "v_mad_co_u64_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadCoU64U32Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadCoU64U32Vop3SdstEnc)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7915,8 +9167,6 @@ VMadCoU64U32Vop3SdstEnc::VMadCoU64U32Vop3SdstEnc(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_CO_U64_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7924,7 +9174,20 @@ VMadCoU64U32Vop3SdstEnc::VMadCoU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_co_u64_u32_e64_dpp" + : "v_mad_co_u64_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_CO_U64_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7934,8 +9197,7 @@ VMadCoI64I32Vop3SdstEnc::VMadCoI64I32Vop3SdstEnc(const MachineInst *inst) ? "v_mad_co_i64_i32_e64_dpp" : "v_mad_co_i64_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadCoI64I32Vop3SdstEnc), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadCoI64I32Vop3SdstEnc)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -7971,8 +9233,6 @@ VMadCoI64I32Vop3SdstEnc::VMadCoI64I32Vop3SdstEnc(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_CO_I64_I32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7980,7 +9240,20 @@ VMadCoI64I32Vop3SdstEnc::VMadCoI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_co_i64_i32_e64_dpp" + : "v_mad_co_i64_i32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_CO_I64_I32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -7990,8 +9263,7 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) ? "v_add_co_u32_e64_dpp" : "v_add_co_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddCoU32Vop3SdstEnc), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VAddCoU32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -8033,7 +9305,17 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_u32_e64_dpp" + : "v_add_co_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8043,8 +9325,7 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) ? "v_sub_co_u32_e64_dpp" : "v_sub_co_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubCoU32Vop3SdstEnc), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubCoU32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -8086,7 +9367,17 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_u32_e64_dpp" + : "v_sub_co_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8096,8 +9387,7 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) ? "v_subrev_co_u32_e64_dpp" : "v_subrev_co_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSubrevCoU32Vop3SdstEnc), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VSubrevCoU32Vop3SdstEnc)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), sdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->sdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), @@ -8139,7 +9429,17 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_u32_e64_dpp" + : "v_subrev_co_u32", + reinterpret_cast(opcode), emit_error, + LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cmp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cmp.cpp index 01d786d86778..157d6d26e589 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cmp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cmp.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -18,7 +17,7 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) ? "v_cmp_lt_f16_e64_dpp" : "v_cmp_lt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -65,7 +64,15 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_e64_dpp" + : "v_cmp_lt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +82,7 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) ? "v_cmp_eq_f16_e64_dpp" : "v_cmp_eq_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -122,7 +129,15 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_e64_dpp" + : "v_cmp_eq_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -132,7 +147,7 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) ? "v_cmp_le_f16_e64_dpp" : "v_cmp_le_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -179,7 +194,15 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_e64_dpp" + : "v_cmp_le_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -189,7 +212,7 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) ? "v_cmp_gt_f16_e64_dpp" : "v_cmp_gt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -236,7 +259,15 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_e64_dpp" + : "v_cmp_gt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +277,7 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) ? "v_cmp_lg_f16_e64_dpp" : "v_cmp_lg_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLgF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLgF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -293,7 +324,15 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_e64_dpp" + : "v_cmp_lg_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -303,7 +342,7 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) ? "v_cmp_ge_f16_e64_dpp" : "v_cmp_ge_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -350,7 +389,15 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_e64_dpp" + : "v_cmp_ge_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +407,7 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) ? "v_cmp_o_f16_e64_dpp" : "v_cmp_o_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpOF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpOF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -407,7 +454,15 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_e64_dpp" + : "v_cmp_o_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -417,7 +472,7 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) ? "v_cmp_u_f16_e64_dpp" : "v_cmp_u_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpUF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpUF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -464,7 +519,15 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_e64_dpp" + : "v_cmp_u_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -474,7 +537,7 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) ? "v_cmp_nge_f16_e64_dpp" : "v_cmp_nge_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNgeF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -521,7 +584,15 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_e64_dpp" + : "v_cmp_nge_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +602,7 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) ? "v_cmp_nlg_f16_e64_dpp" : "v_cmp_nlg_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNlgF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -578,7 +649,15 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_e64_dpp" + : "v_cmp_nlg_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -588,7 +667,7 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) ? "v_cmp_ngt_f16_e64_dpp" : "v_cmp_ngt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNgtF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -635,7 +714,15 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_e64_dpp" + : "v_cmp_ngt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -645,7 +732,7 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) ? "v_cmp_nle_f16_e64_dpp" : "v_cmp_nle_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNleF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNleF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -692,7 +779,15 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_e64_dpp" + : "v_cmp_nle_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -702,7 +797,7 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) ? "v_cmp_neq_f16_e64_dpp" : "v_cmp_neq_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeqF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -749,7 +844,15 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_e64_dpp" + : "v_cmp_neq_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -759,7 +862,7 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) ? "v_cmp_nlt_f16_e64_dpp" : "v_cmp_nlt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNltF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNltF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -806,7 +909,15 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_e64_dpp" + : "v_cmp_nlt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -816,7 +927,7 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) ? "v_cmp_lt_f32_e64_dpp" : "v_cmp_lt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -855,7 +966,15 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_e64_dpp" + : "v_cmp_lt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -865,7 +984,7 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) ? "v_cmp_eq_f32_e64_dpp" : "v_cmp_eq_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -904,7 +1023,15 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_e64_dpp" + : "v_cmp_eq_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -914,7 +1041,7 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) ? "v_cmp_le_f32_e64_dpp" : "v_cmp_le_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -953,7 +1080,15 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_e64_dpp" + : "v_cmp_le_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -963,7 +1098,7 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) ? "v_cmp_gt_f32_e64_dpp" : "v_cmp_gt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1002,7 +1137,15 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_e64_dpp" + : "v_cmp_gt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1012,7 +1155,7 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) ? "v_cmp_lg_f32_e64_dpp" : "v_cmp_lg_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLgF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLgF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1051,7 +1194,15 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_e64_dpp" + : "v_cmp_lg_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1212,7 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) ? "v_cmp_ge_f32_e64_dpp" : "v_cmp_ge_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1100,7 +1251,15 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_e64_dpp" + : "v_cmp_ge_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1269,7 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) ? "v_cmp_o_f32_e64_dpp" : "v_cmp_o_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpOF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpOF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1149,7 +1308,15 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_e64_dpp" + : "v_cmp_o_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1159,7 +1326,7 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) ? "v_cmp_u_f32_e64_dpp" : "v_cmp_u_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpUF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpUF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1198,7 +1365,15 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_e64_dpp" + : "v_cmp_u_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1383,7 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) ? "v_cmp_nge_f32_e64_dpp" : "v_cmp_nge_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNgeF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1247,7 +1422,15 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_e64_dpp" + : "v_cmp_nge_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1257,7 +1440,7 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) ? "v_cmp_nlg_f32_e64_dpp" : "v_cmp_nlg_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNlgF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1296,7 +1479,15 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_e64_dpp" + : "v_cmp_nlg_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1306,7 +1497,7 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) ? "v_cmp_ngt_f32_e64_dpp" : "v_cmp_ngt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNgtF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1345,7 +1536,15 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_e64_dpp" + : "v_cmp_ngt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1355,7 +1554,7 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) ? "v_cmp_nle_f32_e64_dpp" : "v_cmp_nle_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNleF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNleF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1394,7 +1593,15 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_e64_dpp" + : "v_cmp_nle_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1404,7 +1611,7 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) ? "v_cmp_neq_f32_e64_dpp" : "v_cmp_neq_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeqF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1443,7 +1650,15 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_e64_dpp" + : "v_cmp_neq_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1453,7 +1668,7 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) ? "v_cmp_nlt_f32_e64_dpp" : "v_cmp_nlt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNltF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNltF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1492,7 +1707,15 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_e64_dpp" + : "v_cmp_nlt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1502,7 +1725,7 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) ? "v_cmp_lt_f64_e64_dpp" : "v_cmp_lt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1521,15 +1744,23 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_e64_dpp" + : "v_cmp_lt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1539,7 +1770,7 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) ? "v_cmp_eq_f64_e64_dpp" : "v_cmp_eq_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1558,15 +1789,23 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_e64_dpp" + : "v_cmp_eq_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1576,7 +1815,7 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) ? "v_cmp_le_f64_e64_dpp" : "v_cmp_le_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1595,15 +1834,23 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_e64_dpp" + : "v_cmp_le_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1613,7 +1860,7 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) ? "v_cmp_gt_f64_e64_dpp" : "v_cmp_gt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1632,15 +1879,23 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_e64_dpp" + : "v_cmp_gt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1650,7 +1905,7 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) ? "v_cmp_lg_f64_e64_dpp" : "v_cmp_lg_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLgF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLgF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1669,15 +1924,23 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_e64_dpp" + : "v_cmp_lg_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1687,7 +1950,7 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) ? "v_cmp_ge_f64_e64_dpp" : "v_cmp_ge_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1706,15 +1969,23 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_e64_dpp" + : "v_cmp_ge_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1724,7 +1995,7 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) ? "v_cmp_o_f64_e64_dpp" : "v_cmp_o_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpOF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpOF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1743,15 +2014,23 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_e64_dpp" + : "v_cmp_o_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1761,7 +2040,7 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) ? "v_cmp_u_f64_e64_dpp" : "v_cmp_u_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpUF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpUF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1780,15 +2059,23 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_e64_dpp" + : "v_cmp_u_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1798,7 +2085,7 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) ? "v_cmp_nge_f64_e64_dpp" : "v_cmp_nge_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNgeF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNgeF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1817,15 +2104,23 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_e64_dpp" + : "v_cmp_nge_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1835,7 +2130,7 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) ? "v_cmp_nlg_f64_e64_dpp" : "v_cmp_nlg_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNlgF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNlgF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1854,15 +2149,23 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_e64_dpp" + : "v_cmp_nlg_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1872,7 +2175,7 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) ? "v_cmp_ngt_f64_e64_dpp" : "v_cmp_ngt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNgtF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNgtF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1891,15 +2194,23 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_e64_dpp" + : "v_cmp_ngt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1909,7 +2220,7 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) ? "v_cmp_nle_f64_e64_dpp" : "v_cmp_nle_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNleF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNleF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1928,15 +2239,23 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_e64_dpp" + : "v_cmp_nle_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1946,7 +2265,7 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) ? "v_cmp_neq_f64_e64_dpp" : "v_cmp_neq_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeqF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeqF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1965,15 +2284,23 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_e64_dpp" + : "v_cmp_neq_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1983,7 +2310,7 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) ? "v_cmp_nlt_f64_e64_dpp" : "v_cmp_nlt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNltF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNltF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2002,15 +2329,23 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_e64_dpp" + : "v_cmp_nlt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2020,7 +2355,7 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) ? "v_cmp_lt_i16_e64_dpp" : "v_cmp_lt_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtI16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2067,7 +2402,15 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_e64_dpp" + : "v_cmp_lt_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2077,7 +2420,7 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) ? "v_cmp_eq_i16_e64_dpp" : "v_cmp_eq_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqI16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2124,7 +2467,15 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_e64_dpp" + : "v_cmp_eq_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2134,7 +2485,7 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) ? "v_cmp_le_i16_e64_dpp" : "v_cmp_le_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeI16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2181,7 +2532,15 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_e64_dpp" + : "v_cmp_le_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2191,7 +2550,7 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) ? "v_cmp_gt_i16_e64_dpp" : "v_cmp_gt_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtI16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2238,7 +2597,15 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_e64_dpp" + : "v_cmp_gt_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2248,7 +2615,7 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) ? "v_cmp_ne_i16_e64_dpp" : "v_cmp_ne_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeI16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2295,7 +2662,15 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_e64_dpp" + : "v_cmp_ne_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2305,7 +2680,7 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) ? "v_cmp_ge_i16_e64_dpp" : "v_cmp_ge_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeI16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2352,7 +2727,15 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_e64_dpp" + : "v_cmp_ge_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2362,7 +2745,7 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) ? "v_cmp_lt_u16_e64_dpp" : "v_cmp_lt_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtU16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2409,7 +2792,15 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_e64_dpp" + : "v_cmp_lt_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2419,7 +2810,7 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) ? "v_cmp_eq_u16_e64_dpp" : "v_cmp_eq_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqU16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2466,7 +2857,15 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_e64_dpp" + : "v_cmp_eq_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2476,7 +2875,7 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) ? "v_cmp_le_u16_e64_dpp" : "v_cmp_le_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeU16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2523,7 +2922,15 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_e64_dpp" + : "v_cmp_le_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2533,7 +2940,7 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) ? "v_cmp_gt_u16_e64_dpp" : "v_cmp_gt_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtU16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2580,7 +2987,15 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_e64_dpp" + : "v_cmp_gt_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2590,7 +3005,7 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) ? "v_cmp_ne_u16_e64_dpp" : "v_cmp_ne_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeU16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2637,7 +3052,15 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_e64_dpp" + : "v_cmp_ne_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2647,7 +3070,7 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) ? "v_cmp_ge_u16_e64_dpp" : "v_cmp_ge_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeU16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2694,7 +3117,15 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_e64_dpp" + : "v_cmp_ge_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2704,7 +3135,7 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) ? "v_cmp_lt_i32_e64_dpp" : "v_cmp_lt_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtI32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2743,7 +3174,15 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_e64_dpp" + : "v_cmp_lt_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3192,7 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) ? "v_cmp_eq_i32_e64_dpp" : "v_cmp_eq_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqI32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2792,7 +3231,15 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_e64_dpp" + : "v_cmp_eq_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2802,7 +3249,7 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) ? "v_cmp_le_i32_e64_dpp" : "v_cmp_le_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeI32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2841,7 +3288,15 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_e64_dpp" + : "v_cmp_le_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2851,7 +3306,7 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) ? "v_cmp_gt_i32_e64_dpp" : "v_cmp_gt_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtI32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2890,7 +3345,15 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_e64_dpp" + : "v_cmp_gt_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2900,7 +3363,7 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) ? "v_cmp_ne_i32_e64_dpp" : "v_cmp_ne_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeI32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2939,7 +3402,15 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_e64_dpp" + : "v_cmp_ne_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2949,7 +3420,7 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) ? "v_cmp_ge_i32_e64_dpp" : "v_cmp_ge_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeI32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2988,7 +3459,15 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_e64_dpp" + : "v_cmp_ge_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2998,7 +3477,7 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) ? "v_cmp_lt_u32_e64_dpp" : "v_cmp_lt_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtU32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3037,7 +3516,15 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_e64_dpp" + : "v_cmp_lt_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3047,7 +3534,7 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) ? "v_cmp_eq_u32_e64_dpp" : "v_cmp_eq_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqU32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3086,7 +3573,15 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_e64_dpp" + : "v_cmp_eq_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3096,7 +3591,7 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) ? "v_cmp_le_u32_e64_dpp" : "v_cmp_le_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeU32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3135,7 +3630,15 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_e64_dpp" + : "v_cmp_le_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3145,7 +3648,7 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) ? "v_cmp_gt_u32_e64_dpp" : "v_cmp_gt_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtU32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3184,7 +3687,15 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_e64_dpp" + : "v_cmp_gt_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3194,7 +3705,7 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) ? "v_cmp_ne_u32_e64_dpp" : "v_cmp_ne_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeU32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3233,7 +3744,15 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_e64_dpp" + : "v_cmp_ne_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3243,7 +3762,7 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) ? "v_cmp_ge_u32_e64_dpp" : "v_cmp_ge_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeU32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3282,7 +3801,15 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_e64_dpp" + : "v_cmp_ge_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3292,7 +3819,7 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) ? "v_cmp_lt_i64_e64_dpp" : "v_cmp_lt_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtI64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3311,15 +3838,23 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_e64_dpp" + : "v_cmp_lt_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3329,7 +3864,7 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) ? "v_cmp_eq_i64_e64_dpp" : "v_cmp_eq_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqI64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3348,15 +3883,23 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_e64_dpp" + : "v_cmp_eq_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3366,7 +3909,7 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) ? "v_cmp_le_i64_e64_dpp" : "v_cmp_le_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeI64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3385,15 +3928,23 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_e64_dpp" + : "v_cmp_le_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3403,7 +3954,7 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) ? "v_cmp_gt_i64_e64_dpp" : "v_cmp_gt_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtI64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3422,15 +3973,23 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_e64_dpp" + : "v_cmp_gt_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3440,7 +3999,7 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) ? "v_cmp_ne_i64_e64_dpp" : "v_cmp_ne_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeI64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3459,15 +4018,23 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_e64_dpp" + : "v_cmp_ne_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3477,7 +4044,7 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) ? "v_cmp_ge_i64_e64_dpp" : "v_cmp_ge_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeI64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3496,15 +4063,23 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_e64_dpp" + : "v_cmp_ge_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3514,7 +4089,7 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) ? "v_cmp_lt_u64_e64_dpp" : "v_cmp_lt_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLtU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLtU64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3533,15 +4108,23 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_e64_dpp" + : "v_cmp_lt_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3551,7 +4134,7 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) ? "v_cmp_eq_u64_e64_dpp" : "v_cmp_eq_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpEqU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpEqU64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3570,15 +4153,23 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_e64_dpp" + : "v_cmp_eq_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3588,7 +4179,7 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) ? "v_cmp_le_u64_e64_dpp" : "v_cmp_le_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpLeU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpLeU64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3607,15 +4198,23 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_e64_dpp" + : "v_cmp_le_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3625,7 +4224,7 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) ? "v_cmp_gt_u64_e64_dpp" : "v_cmp_gt_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGtU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGtU64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3644,15 +4243,23 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_e64_dpp" + : "v_cmp_gt_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3662,7 +4269,7 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) ? "v_cmp_ne_u64_e64_dpp" : "v_cmp_ne_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpNeU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpNeU64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3681,15 +4288,23 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_e64_dpp" + : "v_cmp_ne_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3699,7 +4314,7 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) ? "v_cmp_ge_u64_e64_dpp" : "v_cmp_ge_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpGeU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpGeU64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3718,15 +4333,23 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_e64_dpp" + : "v_cmp_ge_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3736,8 +4359,7 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) ? "v_cmp_class_f16_e64_dpp" : "v_cmp_class_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpClassF16Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCmpClassF16Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3784,7 +4406,16 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_e64_dpp" + : "v_cmp_class_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3794,8 +4425,7 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) ? "v_cmp_class_f32_e64_dpp" : "v_cmp_class_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpClassF32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCmpClassF32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3834,7 +4464,16 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_e64_dpp" + : "v_cmp_class_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3844,8 +4483,7 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) ? "v_cmp_class_f64_e64_dpp" : "v_cmp_class_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpClassF64Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCmpClassF64Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3863,15 +4501,24 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_e64_dpp" + : "v_cmp_class_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3881,7 +4528,7 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) ? "v_cmpx_lt_f16_e64_dpp" : "v_cmpx_lt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3932,7 +4579,15 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_e64_dpp" + : "v_cmpx_lt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3942,7 +4597,7 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) ? "v_cmpx_eq_f16_e64_dpp" : "v_cmpx_eq_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3993,7 +4648,15 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_e64_dpp" + : "v_cmpx_eq_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4003,7 +4666,7 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) ? "v_cmpx_le_f16_e64_dpp" : "v_cmpx_le_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4054,7 +4717,15 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_e64_dpp" + : "v_cmpx_le_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4064,7 +4735,7 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) ? "v_cmpx_gt_f16_e64_dpp" : "v_cmpx_gt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4115,7 +4786,15 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_e64_dpp" + : "v_cmpx_gt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4125,7 +4804,7 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) ? "v_cmpx_lg_f16_e64_dpp" : "v_cmpx_lg_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLgF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4176,7 +4855,15 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_e64_dpp" + : "v_cmpx_lg_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4186,7 +4873,7 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) ? "v_cmpx_ge_f16_e64_dpp" : "v_cmpx_ge_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4237,7 +4924,15 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_e64_dpp" + : "v_cmpx_ge_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4247,7 +4942,7 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) ? "v_cmpx_o_f16_e64_dpp" : "v_cmpx_o_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxOF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxOF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4298,7 +4993,15 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_e64_dpp" + : "v_cmpx_o_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4308,7 +5011,7 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) ? "v_cmpx_u_f16_e64_dpp" : "v_cmpx_u_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxUF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxUF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4359,7 +5062,15 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_e64_dpp" + : "v_cmpx_u_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4369,7 +5080,7 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) ? "v_cmpx_nge_f16_e64_dpp" : "v_cmpx_nge_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNgeF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4420,7 +5131,16 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_e64_dpp" + : "v_cmpx_nge_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4430,7 +5150,7 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) ? "v_cmpx_nlg_f16_e64_dpp" : "v_cmpx_nlg_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNlgF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4481,7 +5201,16 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_e64_dpp" + : "v_cmpx_nlg_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4491,7 +5220,7 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) ? "v_cmpx_ngt_f16_e64_dpp" : "v_cmpx_ngt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNgtF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4542,7 +5271,16 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_e64_dpp" + : "v_cmpx_ngt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4552,7 +5290,7 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) ? "v_cmpx_nle_f16_e64_dpp" : "v_cmpx_nle_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNleF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4603,7 +5341,16 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_e64_dpp" + : "v_cmpx_nle_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4613,7 +5360,7 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) ? "v_cmpx_neq_f16_e64_dpp" : "v_cmpx_neq_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeqF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4664,7 +5411,16 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_e64_dpp" + : "v_cmpx_neq_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4674,7 +5430,7 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) ? "v_cmpx_nlt_f16_e64_dpp" : "v_cmpx_nlt_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNltF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4725,7 +5481,16 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_e64_dpp" + : "v_cmpx_nlt_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4735,7 +5500,7 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) ? "v_cmpx_lt_f32_e64_dpp" : "v_cmpx_lt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4778,7 +5543,15 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_e64_dpp" + : "v_cmpx_lt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4788,7 +5561,7 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) ? "v_cmpx_eq_f32_e64_dpp" : "v_cmpx_eq_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4831,7 +5604,15 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_e64_dpp" + : "v_cmpx_eq_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4841,7 +5622,7 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) ? "v_cmpx_le_f32_e64_dpp" : "v_cmpx_le_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4884,7 +5665,15 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_e64_dpp" + : "v_cmpx_le_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4894,7 +5683,7 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) ? "v_cmpx_gt_f32_e64_dpp" : "v_cmpx_gt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4937,7 +5726,15 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_e64_dpp" + : "v_cmpx_gt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4947,7 +5744,7 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) ? "v_cmpx_lg_f32_e64_dpp" : "v_cmpx_lg_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLgF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4990,7 +5787,15 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_e64_dpp" + : "v_cmpx_lg_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5000,7 +5805,7 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) ? "v_cmpx_ge_f32_e64_dpp" : "v_cmpx_ge_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5043,7 +5848,15 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_e64_dpp" + : "v_cmpx_ge_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5053,7 +5866,7 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) ? "v_cmpx_o_f32_e64_dpp" : "v_cmpx_o_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxOF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxOF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5096,7 +5909,15 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_e64_dpp" + : "v_cmpx_o_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5106,7 +5927,7 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) ? "v_cmpx_u_f32_e64_dpp" : "v_cmpx_u_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxUF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxUF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5149,7 +5970,15 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_e64_dpp" + : "v_cmpx_u_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5159,7 +5988,7 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) ? "v_cmpx_nge_f32_e64_dpp" : "v_cmpx_nge_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNgeF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5202,7 +6031,16 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_e64_dpp" + : "v_cmpx_nge_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5212,7 +6050,7 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) ? "v_cmpx_nlg_f32_e64_dpp" : "v_cmpx_nlg_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNlgF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5255,7 +6093,16 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_e64_dpp" + : "v_cmpx_nlg_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5265,7 +6112,7 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) ? "v_cmpx_ngt_f32_e64_dpp" : "v_cmpx_ngt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNgtF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5308,7 +6155,16 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_e64_dpp" + : "v_cmpx_ngt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5318,7 +6174,7 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) ? "v_cmpx_nle_f32_e64_dpp" : "v_cmpx_nle_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNleF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5361,7 +6217,16 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_e64_dpp" + : "v_cmpx_nle_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5371,7 +6236,7 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) ? "v_cmpx_neq_f32_e64_dpp" : "v_cmpx_neq_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeqF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5414,7 +6279,16 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_e64_dpp" + : "v_cmpx_neq_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5424,7 +6298,7 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) ? "v_cmpx_nlt_f32_e64_dpp" : "v_cmpx_nlt_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNltF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5467,7 +6341,16 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_e64_dpp" + : "v_cmpx_nlt_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5477,7 +6360,7 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) ? "v_cmpx_lt_f64_e64_dpp" : "v_cmpx_lt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5498,9 +6381,6 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5508,7 +6388,18 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_e64_dpp" + : "v_cmpx_lt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5518,7 +6409,7 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) ? "v_cmpx_eq_f64_e64_dpp" : "v_cmpx_eq_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5539,9 +6430,6 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5549,7 +6437,18 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_e64_dpp" + : "v_cmpx_eq_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5559,7 +6458,7 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) ? "v_cmpx_le_f64_e64_dpp" : "v_cmpx_le_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5580,9 +6479,6 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5590,7 +6486,18 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_e64_dpp" + : "v_cmpx_le_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5600,7 +6507,7 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) ? "v_cmpx_gt_f64_e64_dpp" : "v_cmpx_gt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5621,9 +6528,6 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5631,7 +6535,18 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_e64_dpp" + : "v_cmpx_gt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5641,7 +6556,7 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) ? "v_cmpx_lg_f64_e64_dpp" : "v_cmpx_lg_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLgF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLgF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5662,9 +6577,6 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5672,7 +6584,18 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_e64_dpp" + : "v_cmpx_lg_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5682,7 +6605,7 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) ? "v_cmpx_ge_f64_e64_dpp" : "v_cmpx_ge_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5703,9 +6626,6 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5713,7 +6633,18 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_e64_dpp" + : "v_cmpx_ge_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5723,7 +6654,7 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) ? "v_cmpx_o_f64_e64_dpp" : "v_cmpx_o_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxOF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxOF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5744,9 +6675,6 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5754,7 +6682,18 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_e64_dpp" + : "v_cmpx_o_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5764,7 +6703,7 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) ? "v_cmpx_u_f64_e64_dpp" : "v_cmpx_u_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxUF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxUF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5785,9 +6724,6 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5795,7 +6731,18 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_e64_dpp" + : "v_cmpx_u_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5805,7 +6752,7 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) ? "v_cmpx_nge_f64_e64_dpp" : "v_cmpx_nge_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNgeF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNgeF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5826,9 +6773,6 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5836,7 +6780,19 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_e64_dpp" + : "v_cmpx_nge_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5846,7 +6802,7 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) ? "v_cmpx_nlg_f64_e64_dpp" : "v_cmpx_nlg_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNlgF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNlgF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5867,9 +6823,6 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5877,7 +6830,19 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_e64_dpp" + : "v_cmpx_nlg_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5887,7 +6852,7 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) ? "v_cmpx_ngt_f64_e64_dpp" : "v_cmpx_ngt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNgtF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNgtF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5908,9 +6873,6 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5918,7 +6880,19 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_e64_dpp" + : "v_cmpx_ngt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5928,7 +6902,7 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) ? "v_cmpx_nle_f64_e64_dpp" : "v_cmpx_nle_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNleF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNleF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5949,9 +6923,6 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -5959,7 +6930,19 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_e64_dpp" + : "v_cmpx_nle_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5969,7 +6952,7 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) ? "v_cmpx_neq_f64_e64_dpp" : "v_cmpx_neq_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeqF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeqF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -5990,9 +6973,6 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -6000,7 +6980,19 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_e64_dpp" + : "v_cmpx_neq_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6010,7 +7002,7 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) ? "v_cmpx_nlt_f64_e64_dpp" : "v_cmpx_nlt_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNltF64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNltF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6031,9 +7023,6 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -6041,7 +7030,19 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_e64_dpp" + : "v_cmpx_nlt_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6051,7 +7052,7 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) ? "v_cmpx_lt_i16_e64_dpp" : "v_cmpx_lt_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtI16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6102,7 +7103,15 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_e64_dpp" + : "v_cmpx_lt_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6112,7 +7121,7 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) ? "v_cmpx_eq_i16_e64_dpp" : "v_cmpx_eq_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqI16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6163,7 +7172,15 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_e64_dpp" + : "v_cmpx_eq_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6173,7 +7190,7 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) ? "v_cmpx_le_i16_e64_dpp" : "v_cmpx_le_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeI16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6224,7 +7241,15 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_e64_dpp" + : "v_cmpx_le_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6234,7 +7259,7 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) ? "v_cmpx_gt_i16_e64_dpp" : "v_cmpx_gt_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtI16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6285,7 +7310,15 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_e64_dpp" + : "v_cmpx_gt_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6295,7 +7328,7 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) ? "v_cmpx_ne_i16_e64_dpp" : "v_cmpx_ne_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeI16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6346,7 +7379,15 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_e64_dpp" + : "v_cmpx_ne_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6356,7 +7397,7 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) ? "v_cmpx_ge_i16_e64_dpp" : "v_cmpx_ge_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeI16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6407,7 +7448,15 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_e64_dpp" + : "v_cmpx_ge_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6417,7 +7466,7 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) ? "v_cmpx_lt_u16_e64_dpp" : "v_cmpx_lt_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtU16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6468,7 +7517,15 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_e64_dpp" + : "v_cmpx_lt_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6478,7 +7535,7 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) ? "v_cmpx_eq_u16_e64_dpp" : "v_cmpx_eq_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqU16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6529,7 +7586,15 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_e64_dpp" + : "v_cmpx_eq_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6539,7 +7604,7 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) ? "v_cmpx_le_u16_e64_dpp" : "v_cmpx_le_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeU16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6590,7 +7655,15 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_e64_dpp" + : "v_cmpx_le_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6600,7 +7673,7 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) ? "v_cmpx_gt_u16_e64_dpp" : "v_cmpx_gt_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtU16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6651,7 +7724,15 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_e64_dpp" + : "v_cmpx_gt_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6661,7 +7742,7 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) ? "v_cmpx_ne_u16_e64_dpp" : "v_cmpx_ne_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeU16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6712,7 +7793,15 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_e64_dpp" + : "v_cmpx_ne_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6722,7 +7811,7 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) ? "v_cmpx_ge_u16_e64_dpp" : "v_cmpx_ge_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeU16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6773,7 +7862,15 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_e64_dpp" + : "v_cmpx_ge_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6783,7 +7880,7 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) ? "v_cmpx_lt_i32_e64_dpp" : "v_cmpx_lt_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtI32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6826,7 +7923,15 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_e64_dpp" + : "v_cmpx_lt_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6836,7 +7941,7 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) ? "v_cmpx_eq_i32_e64_dpp" : "v_cmpx_eq_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqI32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6879,7 +7984,15 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_e64_dpp" + : "v_cmpx_eq_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6889,7 +8002,7 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) ? "v_cmpx_le_i32_e64_dpp" : "v_cmpx_le_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeI32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6932,7 +8045,15 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_e64_dpp" + : "v_cmpx_le_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6942,7 +8063,7 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) ? "v_cmpx_gt_i32_e64_dpp" : "v_cmpx_gt_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtI32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -6985,7 +8106,15 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_e64_dpp" + : "v_cmpx_gt_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6995,7 +8124,7 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) ? "v_cmpx_ne_i32_e64_dpp" : "v_cmpx_ne_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeI32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7038,7 +8167,15 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_e64_dpp" + : "v_cmpx_ne_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7048,7 +8185,7 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) ? "v_cmpx_ge_i32_e64_dpp" : "v_cmpx_ge_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeI32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7091,7 +8228,15 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_e64_dpp" + : "v_cmpx_ge_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7101,7 +8246,7 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) ? "v_cmpx_lt_u32_e64_dpp" : "v_cmpx_lt_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtU32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7144,7 +8289,15 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_e64_dpp" + : "v_cmpx_lt_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7154,7 +8307,7 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) ? "v_cmpx_eq_u32_e64_dpp" : "v_cmpx_eq_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqU32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7197,7 +8350,15 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_e64_dpp" + : "v_cmpx_eq_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7207,7 +8368,7 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) ? "v_cmpx_le_u32_e64_dpp" : "v_cmpx_le_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeU32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7250,7 +8411,15 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_e64_dpp" + : "v_cmpx_le_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7260,7 +8429,7 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) ? "v_cmpx_gt_u32_e64_dpp" : "v_cmpx_gt_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtU32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7303,7 +8472,15 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_e64_dpp" + : "v_cmpx_gt_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7313,7 +8490,7 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) ? "v_cmpx_ne_u32_e64_dpp" : "v_cmpx_ne_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeU32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7356,7 +8533,15 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_e64_dpp" + : "v_cmpx_ne_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7366,7 +8551,7 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) ? "v_cmpx_ge_u32_e64_dpp" : "v_cmpx_ge_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeU32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7409,7 +8594,15 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_e64_dpp" + : "v_cmpx_ge_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7419,7 +8612,7 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) ? "v_cmpx_lt_i64_e64_dpp" : "v_cmpx_lt_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtI64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7440,9 +8633,6 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7450,7 +8640,18 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_e64_dpp" + : "v_cmpx_lt_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7460,7 +8661,7 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) ? "v_cmpx_eq_i64_e64_dpp" : "v_cmpx_eq_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqI64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7481,9 +8682,6 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7491,7 +8689,18 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_e64_dpp" + : "v_cmpx_eq_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7501,7 +8710,7 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) ? "v_cmpx_le_i64_e64_dpp" : "v_cmpx_le_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeI64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7522,9 +8731,6 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7532,7 +8738,18 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_e64_dpp" + : "v_cmpx_le_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7542,7 +8759,7 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) ? "v_cmpx_gt_i64_e64_dpp" : "v_cmpx_gt_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtI64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7563,9 +8780,6 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7573,7 +8787,18 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_e64_dpp" + : "v_cmpx_gt_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7583,7 +8808,7 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) ? "v_cmpx_ne_i64_e64_dpp" : "v_cmpx_ne_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeI64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7604,9 +8829,6 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7614,7 +8836,18 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_e64_dpp" + : "v_cmpx_ne_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7624,7 +8857,7 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) ? "v_cmpx_ge_i64_e64_dpp" : "v_cmpx_ge_i64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeI64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeI64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7645,9 +8878,6 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7655,7 +8885,18 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_e64_dpp" + : "v_cmpx_ge_i64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7665,7 +8906,7 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) ? "v_cmpx_lt_u64_e64_dpp" : "v_cmpx_lt_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLtU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLtU64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7686,9 +8927,6 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7696,7 +8934,18 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_e64_dpp" + : "v_cmpx_lt_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7706,7 +8955,7 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) ? "v_cmpx_eq_u64_e64_dpp" : "v_cmpx_eq_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxEqU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxEqU64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7727,9 +8976,6 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7737,7 +8983,18 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_e64_dpp" + : "v_cmpx_eq_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7747,7 +9004,7 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) ? "v_cmpx_le_u64_e64_dpp" : "v_cmpx_le_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxLeU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxLeU64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7768,9 +9025,6 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7778,7 +9032,18 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_e64_dpp" + : "v_cmpx_le_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7788,7 +9053,7 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) ? "v_cmpx_gt_u64_e64_dpp" : "v_cmpx_gt_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGtU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGtU64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7809,9 +9074,6 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7819,7 +9081,18 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_e64_dpp" + : "v_cmpx_gt_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7829,7 +9102,7 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) ? "v_cmpx_ne_u64_e64_dpp" : "v_cmpx_ne_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxNeU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxNeU64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7850,9 +9123,6 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7860,7 +9130,18 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_e64_dpp" + : "v_cmpx_ne_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7870,7 +9151,7 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) ? "v_cmpx_ge_u64_e64_dpp" : "v_cmpx_ge_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxGeU64Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCmpxGeU64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7891,9 +9172,6 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -7901,7 +9179,18 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_e64_dpp" + : "v_cmpx_ge_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7911,8 +9200,7 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) ? "v_cmpx_class_f16_e64_dpp" : "v_cmpx_class_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCmpxClassF16Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -7963,7 +9251,16 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_e64_dpp" + : "v_cmpx_class_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7973,8 +9270,7 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) ? "v_cmpx_class_f32_e64_dpp" : "v_cmpx_class_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCmpxClassF32Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -8017,7 +9313,16 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_e64_dpp" + : "v_cmpx_class_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8027,8 +9332,7 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) ? "v_cmpx_class_f64_e64_dpp" : "v_cmpx_class_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCmpxClassF64Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCmpxClassF64Vop3)), vdst(64, OperandType::OPR_EXEC, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -8048,9 +9352,6 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -8058,7 +9359,19 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_e64_dpp" + : "v_cmpx_class_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cvt.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cvt.cpp index c476fcda28e5..2039ec9a1ccb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cvt.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_cvt.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -18,7 +17,7 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) ? "v_cvt_i32_f64_e64_dpp" : "v_cvt_i32_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtI32F64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtI32F64Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -39,14 +38,22 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_e64_dpp" + : "v_cvt_i32_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -56,7 +63,7 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) ? "v_cvt_f64_i32_e64_dpp" : "v_cvt_f64_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF64I32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF64I32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -76,14 +83,22 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_e64_dpp" + : "v_cvt_f64_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -93,7 +108,7 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) ? "v_cvt_f32_i32_e64_dpp" : "v_cvt_f32_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32I32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32I32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -126,7 +141,15 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_e64_dpp" + : "v_cvt_f32_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -136,7 +159,7 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) ? "v_cvt_f32_u32_e64_dpp" : "v_cvt_f32_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32U32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -169,7 +192,15 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_e64_dpp" + : "v_cvt_f32_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -179,7 +210,7 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) ? "v_cvt_u32_f32_e64_dpp" : "v_cvt_u32_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtU32F32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtU32F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -212,7 +243,15 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_e64_dpp" + : "v_cvt_u32_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -222,7 +261,7 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) ? "v_cvt_i32_f32_e64_dpp" : "v_cvt_i32_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtI32F32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtI32F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -255,7 +294,15 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_e64_dpp" + : "v_cvt_i32_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +312,7 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) ? "v_cvt_f16_f32_e64_dpp" : "v_cvt_f16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF16F32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF16F32Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -298,7 +345,15 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_e64_dpp" + : "v_cvt_f16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -321,7 +376,7 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) ? "v_cvt_f32_f16_e64_dpp" : "v_cvt_f32_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32F16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32F16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -358,7 +413,15 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_e64_dpp" + : "v_cvt_f32_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,8 +431,7 @@ VCvtNearestI32F32Vop3::VCvtNearestI32F32Vop3(const MachineInst *inst) ? "v_cvt_nearest_i32_f32_e64_dpp" : "v_cvt_nearest_i32_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtNearestI32F32Vop3), - LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtNearestI32F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -402,7 +464,16 @@ VCvtNearestI32F32Vop3::VCvtNearestI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_e64_dpp" + : "v_cvt_nearest_i32_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -412,8 +483,7 @@ VCvtFloorI32F32Vop3::VCvtFloorI32F32Vop3(const MachineInst *inst) ? "v_cvt_floor_i32_f32_e64_dpp" : "v_cvt_floor_i32_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtFloorI32F32Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtFloorI32F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -446,7 +516,16 @@ VCvtFloorI32F32Vop3::VCvtFloorI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_e64_dpp" + : "v_cvt_floor_i32_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,8 +535,7 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) ? "v_cvt_off_f32_i4_e64_dpp" : "v_cvt_off_f32_i4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtOffF32I4Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtOffF32I4Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -490,7 +568,16 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_e64_dpp" + : "v_cvt_off_f32_i4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -500,7 +587,7 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) ? "v_cvt_f32_f64_e64_dpp" : "v_cvt_f32_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32F64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32F64Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -521,14 +608,22 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_e64_dpp" + : "v_cvt_f32_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -538,7 +633,7 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) ? "v_cvt_f64_f32_e64_dpp" : "v_cvt_f64_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF64F32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF64F32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -558,14 +653,22 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_e64_dpp" + : "v_cvt_f64_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -575,8 +678,7 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) ? "v_cvt_f32_ubyte0_e64_dpp" : "v_cvt_f32_ubyte0", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte0Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte0Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -609,7 +711,16 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_e64_dpp" + : "v_cvt_f32_ubyte0", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -619,8 +730,7 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) ? "v_cvt_f32_ubyte1_e64_dpp" : "v_cvt_f32_ubyte1", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte1Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte1Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -653,7 +763,16 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_e64_dpp" + : "v_cvt_f32_ubyte1", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -663,8 +782,7 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) ? "v_cvt_f32_ubyte2_e64_dpp" : "v_cvt_f32_ubyte2", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte2Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte2Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -697,7 +815,16 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_e64_dpp" + : "v_cvt_f32_ubyte2", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,8 +834,7 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) ? "v_cvt_f32_ubyte3_e64_dpp" : "v_cvt_f32_ubyte3", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte3Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Ubyte3Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -741,7 +867,16 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_e64_dpp" + : "v_cvt_f32_ubyte3", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -751,7 +886,7 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) ? "v_cvt_u32_f64_e64_dpp" : "v_cvt_u32_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtU32F64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtU32F64Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -772,14 +907,22 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_e64_dpp" + : "v_cvt_u32_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -789,7 +932,7 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) ? "v_cvt_f64_u32_e64_dpp" : "v_cvt_f64_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF64U32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF64U32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -809,14 +952,22 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_e64_dpp" + : "v_cvt_f64_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -826,8 +977,7 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) ? "v_frexp_exp_i32_f64_e64_dpp" : "v_frexp_exp_i32_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFrexpExpI32F64Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VFrexpExpI32F64Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -848,14 +998,23 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_e64_dpp" + : "v_frexp_exp_i32_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -865,8 +1024,7 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) ? "v_frexp_mant_f64_e64_dpp" : "v_frexp_mant_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFrexpMantF64Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VFrexpMantF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -887,14 +1045,23 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_e64_dpp" + : "v_frexp_mant_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -904,8 +1071,7 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) ? "v_frexp_exp_i32_f32_e64_dpp" : "v_frexp_exp_i32_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFrexpExpI32F32Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VFrexpExpI32F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -938,7 +1104,16 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_e64_dpp" + : "v_frexp_exp_i32_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -948,8 +1123,7 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) ? "v_frexp_mant_f32_e64_dpp" : "v_frexp_mant_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFrexpMantF32Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VFrexpMantF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -982,7 +1156,16 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_e64_dpp" + : "v_frexp_mant_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -992,7 +1175,7 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) ? "v_cvt_f16_u16_e64_dpp" : "v_cvt_f16_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF16U16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF16U16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1029,7 +1212,15 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_e64_dpp" + : "v_cvt_f16_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1243,7 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) ? "v_cvt_f16_i16_e64_dpp" : "v_cvt_f16_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF16I16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF16I16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1089,7 +1280,15 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_e64_dpp" + : "v_cvt_f16_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1311,7 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) ? "v_cvt_u16_f16_e64_dpp" : "v_cvt_u16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtU16F16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtU16F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1149,7 +1348,15 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_e64_dpp" + : "v_cvt_u16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1172,7 +1379,7 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) ? "v_cvt_i16_f16_e64_dpp" : "v_cvt_i16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtI16F16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtI16F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1209,7 +1416,15 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_e64_dpp" + : "v_cvt_i16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1232,8 +1447,7 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) ? "v_frexp_mant_f16_e64_dpp" : "v_frexp_mant_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFrexpMantF16Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VFrexpMantF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1270,7 +1484,16 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_e64_dpp" + : "v_frexp_mant_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,8 +1516,7 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) ? "v_frexp_exp_i16_f16_e64_dpp" : "v_frexp_exp_i16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFrexpExpI16F16Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VFrexpExpI16F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1331,7 +1553,16 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_e64_dpp" + : "v_frexp_exp_i16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1354,8 +1585,7 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) ? "v_cvt_norm_i16_f16_e64_dpp" : "v_cvt_norm_i16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtNormI16F16Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtNormI16F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1392,7 +1622,16 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_e64_dpp" + : "v_cvt_norm_i16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1415,8 +1654,7 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) ? "v_cvt_norm_u16_f16_e64_dpp" : "v_cvt_norm_u16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtNormU16F16Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtNormU16F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1453,7 +1691,16 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_e64_dpp" + : "v_cvt_norm_u16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1476,7 +1723,7 @@ VCvtI32I16Vop3::VCvtI32I16Vop3(const MachineInst *inst) ? "v_cvt_i32_i16_e64_dpp" : "v_cvt_i32_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtI32I16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtI32I16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1513,7 +1760,15 @@ VCvtI32I16Vop3::VCvtI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_e64_dpp" + : "v_cvt_i32_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1523,7 +1778,7 @@ VCvtU32U16Vop3::VCvtU32U16Vop3(const MachineInst *inst) ? "v_cvt_u32_u16_e64_dpp" : "v_cvt_u32_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtU32U16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtU32U16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1560,7 +1815,15 @@ VCvtU32U16Vop3::VCvtU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_e64_dpp" + : "v_cvt_u32_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1570,7 +1833,7 @@ VCvtF32Fp8Vop3::VCvtF32Fp8Vop3(const MachineInst *inst) ? "v_cvt_f32_fp8_e64_dpp" : "v_cvt_f32_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Fp8Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Fp8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1603,7 +1866,15 @@ VCvtF32Fp8Vop3::VCvtF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_fp8_e64_dpp" + : "v_cvt_f32_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1613,7 +1884,7 @@ VCvtF32Bf8Vop3::VCvtF32Bf8Vop3(const MachineInst *inst) ? "v_cvt_f32_bf8_e64_dpp" : "v_cvt_f32_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Bf8Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Bf8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1646,7 +1917,15 @@ VCvtF32Bf8Vop3::VCvtF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_bf8_e64_dpp" + : "v_cvt_f32_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1656,8 +1935,7 @@ VCvtPkF32Fp8Vop3::VCvtPkF32Fp8Vop3(const MachineInst *inst) ? "v_cvt_pk_f32_fp8_e64_dpp" : "v_cvt_pk_f32_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkF32Fp8Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtPkF32Fp8Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1672,15 +1950,24 @@ VCvtPkF32Fp8Vop3::VCvtPkF32Fp8Vop3(const MachineInst *inst) (((amdgpu::vop3_opsel(inst_) >> 0) & 1u) * 16u)) & 0xFFFFu), true); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_fp8_e64_dpp" + : "v_cvt_pk_f32_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1690,8 +1977,7 @@ VCvtPkF32Bf8Vop3::VCvtPkF32Bf8Vop3(const MachineInst *inst) ? "v_cvt_pk_f32_bf8_e64_dpp" : "v_cvt_pk_f32_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkF32Bf8Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtPkF32Bf8Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1706,15 +1992,24 @@ VCvtPkF32Bf8Vop3::VCvtPkF32Bf8Vop3(const MachineInst *inst) (((amdgpu::vop3_opsel(inst_) >> 0) & 1u) * 16u)) & 0xFFFFu), true); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_bf8_e64_dpp" + : "v_cvt_pk_f32_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1724,7 +2019,7 @@ VCvtF32Bf16Vop3::VCvtF32Bf16Vop3(const MachineInst *inst) ? "v_cvt_f32_bf16_e64_dpp" : "v_cvt_f32_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF32Bf16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF32Bf16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1761,7 +2056,16 @@ VCvtF32Bf16Vop3::VCvtF32Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_bf16_e64_dpp" + : "v_cvt_f32_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1771,8 +2075,7 @@ VCvtPkF16Fp8Vop3::VCvtPkF16Fp8Vop3(const MachineInst *inst) ? "v_cvt_pk_f16_fp8_e64_dpp" : "v_cvt_pk_f16_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkF16Fp8Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtPkF16Fp8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1809,7 +2112,16 @@ VCvtPkF16Fp8Vop3::VCvtPkF16Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f16_fp8_e64_dpp" + : "v_cvt_pk_f16_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,8 +2131,7 @@ VCvtPkF16Bf8Vop3::VCvtPkF16Bf8Vop3(const MachineInst *inst) ? "v_cvt_pk_f16_bf8_e64_dpp" : "v_cvt_pk_f16_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkF16Bf8Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtPkF16Bf8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1857,7 +2168,16 @@ VCvtPkF16Bf8Vop3::VCvtPkF16Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f16_bf8_e64_dpp" + : "v_cvt_pk_f16_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1867,7 +2187,7 @@ VCvtF16Fp8Vop3::VCvtF16Fp8Vop3(const MachineInst *inst) ? "v_cvt_f16_fp8_e64_dpp" : "v_cvt_f16_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF16Fp8Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF16Fp8Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1900,7 +2220,15 @@ VCvtF16Fp8Vop3::VCvtF16Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_fp8_e64_dpp" + : "v_cvt_f16_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1923,7 +2251,7 @@ VCvtF16Bf8Vop3::VCvtF16Bf8Vop3(const MachineInst *inst) ? "v_cvt_f16_bf8_e64_dpp" : "v_cvt_f16_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtF16Bf8Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VCvtF16Bf8Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(8, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -1956,7 +2284,15 @@ VCvtF16Bf8Vop3::VCvtF16Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_bf8_e64_dpp" + : "v_cvt_f16_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1979,8 +2315,7 @@ VCvtPkRtzF16F32Vop3::VCvtPkRtzF16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_rtz_f16_f32_e64_dpp" : "v_cvt_pk_rtz_f16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkRtzF16F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkRtzF16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2020,7 +2355,16 @@ VCvtPkRtzF16F32Vop3::VCvtPkRtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_e64_dpp" + : "v_cvt_pk_rtz_f16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2030,7 +2374,7 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) ? "v_cvt_pk_u8_f32_e64_dpp" : "v_cvt_pk_u8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkU8F32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtPkU8F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2077,7 +2421,16 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u8_f32_e64_dpp" + : "v_cvt_pk_u8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2087,8 +2440,7 @@ VCvtScalef32SrPk8Fp4F32Vop3::VCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *inst ? "v_cvt_scalef32_sr_pk8_fp4_f32_e64_dpp" : "v_cvt_scalef32_sr_pk8_fp4_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp4F32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp4F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2107,9 +2459,6 @@ VCvtScalef32SrPk8Fp4F32Vop3::VCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *inst src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_FP4_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2117,7 +2466,19 @@ VCvtScalef32SrPk8Fp4F32Vop3::VCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Fp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_fp4_f32_e64_dpp" + : "v_cvt_scalef32_sr_pk8_fp4_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_FP4_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2127,8 +2488,7 @@ VCvtScalef32SrPk8Fp8F32Vop3::VCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *inst ? "v_cvt_scalef32_sr_pk8_fp8_f32_e64_dpp" : "v_cvt_scalef32_sr_pk8_fp8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp8F32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp8F32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2147,9 +2507,6 @@ VCvtScalef32SrPk8Fp8F32Vop3::VCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *inst src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_FP8_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2157,7 +2514,19 @@ VCvtScalef32SrPk8Fp8F32Vop3::VCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Fp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_fp8_f32_e64_dpp" + : "v_cvt_scalef32_sr_pk8_fp8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_FP8_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2167,8 +2536,7 @@ VCvtScalef32SrPk8Bf8F32Vop3::VCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *inst ? "v_cvt_scalef32_sr_pk8_bf8_f32_e64_dpp" : "v_cvt_scalef32_sr_pk8_bf8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Bf8F32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Bf8F32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2187,9 +2555,6 @@ VCvtScalef32SrPk8Bf8F32Vop3::VCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *inst src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_BF8_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2197,7 +2562,19 @@ VCvtScalef32SrPk8Bf8F32Vop3::VCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Bf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_bf8_f32_e64_dpp" + : "v_cvt_scalef32_sr_pk8_bf8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_BF8_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2207,8 +2584,7 @@ VCvtScalePk8F16Fp4Vop3::VCvtScalePk8F16Fp4Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_f16_fp4_e64_dpp" : "v_cvt_scale_pk8_f16_fp4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8F16Fp4Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8F16Fp4Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2221,16 +2597,25 @@ VCvtScalePk8F16Fp4Vop3::VCvtScalePk8F16Fp4Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_F16_FP4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8F16Fp4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8F16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_f16_fp4_e64_dpp" + : "v_cvt_scale_pk8_f16_fp4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_F16_FP4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2240,8 +2625,7 @@ VCvtScalePk8Bf16Fp4Vop3::VCvtScalePk8Bf16Fp4Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_bf16_fp4_e64_dpp" : "v_cvt_scale_pk8_bf16_fp4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8Bf16Fp4Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8Bf16Fp4Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2254,16 +2638,25 @@ VCvtScalePk8Bf16Fp4Vop3::VCvtScalePk8Bf16Fp4Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_BF16_FP4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8Bf16Fp4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8Bf16Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_bf16_fp4_e64_dpp" + : "v_cvt_scale_pk8_bf16_fp4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_BF16_FP4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2273,8 +2666,7 @@ VCvtScalePk8F32Fp4Vop3::VCvtScalePk8F32Fp4Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_f32_fp4_e64_dpp" : "v_cvt_scale_pk8_f32_fp4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8F32Fp4Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8F32Fp4Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2287,16 +2679,25 @@ VCvtScalePk8F32Fp4Vop3::VCvtScalePk8F32Fp4Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_F32_FP4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8F32Fp4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8F32Fp4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_f32_fp4_e64_dpp" + : "v_cvt_scale_pk8_f32_fp4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_F32_FP4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2306,8 +2707,7 @@ VCvtScalePk8F16Fp8Vop3::VCvtScalePk8F16Fp8Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_f16_fp8_e64_dpp" : "v_cvt_scale_pk8_f16_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8F16Fp8Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8F16Fp8Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2320,16 +2720,25 @@ VCvtScalePk8F16Fp8Vop3::VCvtScalePk8F16Fp8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_F16_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8F16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8F16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_f16_fp8_e64_dpp" + : "v_cvt_scale_pk8_f16_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_F16_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2339,8 +2748,7 @@ VCvtScalePk8Bf16Fp8Vop3::VCvtScalePk8Bf16Fp8Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_bf16_fp8_e64_dpp" : "v_cvt_scale_pk8_bf16_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8Bf16Fp8Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8Bf16Fp8Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2353,16 +2761,25 @@ VCvtScalePk8Bf16Fp8Vop3::VCvtScalePk8Bf16Fp8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_BF16_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8Bf16Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8Bf16Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_bf16_fp8_e64_dpp" + : "v_cvt_scale_pk8_bf16_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_BF16_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2372,8 +2789,7 @@ VCvtScalePk8F32Fp8Vop3::VCvtScalePk8F32Fp8Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_f32_fp8_e64_dpp" : "v_cvt_scale_pk8_f32_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8F32Fp8Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8F32Fp8Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2386,16 +2802,25 @@ VCvtScalePk8F32Fp8Vop3::VCvtScalePk8F32Fp8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_F32_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8F32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8F32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_f32_fp8_e64_dpp" + : "v_cvt_scale_pk8_f32_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_F32_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2405,8 +2830,7 @@ VCvtScalePk8F16Bf8Vop3::VCvtScalePk8F16Bf8Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_f16_bf8_e64_dpp" : "v_cvt_scale_pk8_f16_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8F16Bf8Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8F16Bf8Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2419,16 +2843,25 @@ VCvtScalePk8F16Bf8Vop3::VCvtScalePk8F16Bf8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_F16_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8F16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8F16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_f16_bf8_e64_dpp" + : "v_cvt_scale_pk8_f16_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_F16_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2438,8 +2871,7 @@ VCvtScalePk8Bf16Bf8Vop3::VCvtScalePk8Bf16Bf8Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_bf16_bf8_e64_dpp" : "v_cvt_scale_pk8_bf16_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8Bf16Bf8Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8Bf16Bf8Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2452,16 +2884,25 @@ VCvtScalePk8Bf16Bf8Vop3::VCvtScalePk8Bf16Bf8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_BF16_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8Bf16Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8Bf16Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_bf16_bf8_e64_dpp" + : "v_cvt_scale_pk8_bf16_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_BF16_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2471,8 +2912,7 @@ VCvtScalePk8F32Bf8Vop3::VCvtScalePk8F32Bf8Vop3(const MachineInst *inst) ? "v_cvt_scale_pk8_f32_bf8_e64_dpp" : "v_cvt_scale_pk8_f32_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk8F32Bf8Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk8F32Bf8Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2485,16 +2925,25 @@ VCvtScalePk8F32Bf8Vop3::VCvtScalePk8F32Bf8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK8_F32_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk8F32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk8F32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk8_f32_bf8_e64_dpp" + : "v_cvt_scale_pk8_f32_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK8_F32_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2504,8 +2953,7 @@ VCvtScalef32Pk8Fp4F32Vop3::VCvtScalef32Pk8Fp4F32Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_fp4_f32_e64_dpp" : "v_cvt_scalef32_pk8_fp4_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp4F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp4F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2518,16 +2966,25 @@ VCvtScalef32Pk8Fp4F32Vop3::VCvtScalef32Pk8Fp4F32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_FP4_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Fp4F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Fp4F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_fp4_f32_e64_dpp" + : "v_cvt_scalef32_pk8_fp4_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_FP4_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2537,8 +2994,7 @@ VCvtScalef32Pk8Fp4F16Vop3::VCvtScalef32Pk8Fp4F16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_fp4_f16_e64_dpp" : "v_cvt_scalef32_pk8_fp4_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp4F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp4F16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2551,16 +3007,25 @@ VCvtScalef32Pk8Fp4F16Vop3::VCvtScalef32Pk8Fp4F16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_FP4_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Fp4F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Fp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_fp4_f16_e64_dpp" + : "v_cvt_scalef32_pk8_fp4_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_FP4_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2570,8 +3035,7 @@ VCvtScalef32Pk8Fp8Bf16Vop3::VCvtScalef32Pk8Fp8Bf16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_fp8_bf16_e64_dpp" : "v_cvt_scalef32_pk8_fp8_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp8Bf16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp8Bf16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2584,16 +3048,25 @@ VCvtScalef32Pk8Fp8Bf16Vop3::VCvtScalef32Pk8Fp8Bf16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_FP8_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Fp8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Fp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_fp8_bf16_e64_dpp" + : "v_cvt_scalef32_pk8_fp8_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_FP8_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2603,8 +3076,7 @@ VCvtScalef32Pk8Bf8Bf16Vop3::VCvtScalef32Pk8Bf8Bf16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_bf8_bf16_e64_dpp" : "v_cvt_scalef32_pk8_bf8_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Bf8Bf16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Bf8Bf16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2617,16 +3089,25 @@ VCvtScalef32Pk8Bf8Bf16Vop3::VCvtScalef32Pk8Bf8Bf16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_BF8_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Bf8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Bf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_bf8_bf16_e64_dpp" + : "v_cvt_scalef32_pk8_bf8_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_BF8_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2636,8 +3117,7 @@ VCvtScalef32Pk8Fp4Bf16Vop3::VCvtScalef32Pk8Fp4Bf16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_fp4_bf16_e64_dpp" : "v_cvt_scalef32_pk8_fp4_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp4Bf16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp4Bf16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2650,16 +3130,25 @@ VCvtScalef32Pk8Fp4Bf16Vop3::VCvtScalef32Pk8Fp4Bf16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_FP4_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Fp4Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Fp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_fp4_bf16_e64_dpp" + : "v_cvt_scalef32_pk8_fp4_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_FP4_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2669,8 +3158,7 @@ VCvtScalef32SrPk8Fp4F16Vop3::VCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *inst ? "v_cvt_scalef32_sr_pk8_fp4_f16_e64_dpp" : "v_cvt_scalef32_sr_pk8_fp4_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp4F16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp4F16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2689,9 +3177,6 @@ VCvtScalef32SrPk8Fp4F16Vop3::VCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *inst src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_FP4_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2699,7 +3184,19 @@ VCvtScalef32SrPk8Fp4F16Vop3::VCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Fp4F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_fp4_f16_e64_dpp" + : "v_cvt_scalef32_sr_pk8_fp4_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_FP4_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2709,8 +3206,7 @@ VCvtScalef32SrPk8Fp4Bf16Vop3::VCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk8_fp4_bf16_e64_dpp" : "v_cvt_scalef32_sr_pk8_fp4_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp4Bf16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp4Bf16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2729,9 +3225,6 @@ VCvtScalef32SrPk8Fp4Bf16Vop3::VCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_FP4_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2739,7 +3232,19 @@ VCvtScalef32SrPk8Fp4Bf16Vop3::VCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Fp4Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_fp4_bf16_e64_dpp" + : "v_cvt_scalef32_sr_pk8_fp4_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_FP4_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2749,8 +3254,7 @@ VCvtScalef32SrPk8Fp8F16Vop3::VCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *inst ? "v_cvt_scalef32_sr_pk8_fp8_f16_e64_dpp" : "v_cvt_scalef32_sr_pk8_fp8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp8F16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp8F16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2769,9 +3273,6 @@ VCvtScalef32SrPk8Fp8F16Vop3::VCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *inst src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_FP8_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2779,7 +3280,19 @@ VCvtScalef32SrPk8Fp8F16Vop3::VCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Fp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_fp8_f16_e64_dpp" + : "v_cvt_scalef32_sr_pk8_fp8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_FP8_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2789,8 +3302,7 @@ VCvtScalef32SrPk8Fp8Bf16Vop3::VCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk8_fp8_bf16_e64_dpp" : "v_cvt_scalef32_sr_pk8_fp8_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp8Bf16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Fp8Bf16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2809,9 +3321,6 @@ VCvtScalef32SrPk8Fp8Bf16Vop3::VCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_FP8_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2819,7 +3328,19 @@ VCvtScalef32SrPk8Fp8Bf16Vop3::VCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Fp8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_fp8_bf16_e64_dpp" + : "v_cvt_scalef32_sr_pk8_fp8_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_FP8_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2829,8 +3350,7 @@ VCvtScalef32SrPk8Bf8F16Vop3::VCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *inst ? "v_cvt_scalef32_sr_pk8_bf8_f16_e64_dpp" : "v_cvt_scalef32_sr_pk8_bf8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Bf8F16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Bf8F16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2849,9 +3369,6 @@ VCvtScalef32SrPk8Bf8F16Vop3::VCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *inst src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_BF8_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2859,7 +3376,19 @@ VCvtScalef32SrPk8Bf8F16Vop3::VCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Bf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_bf8_f16_e64_dpp" + : "v_cvt_scalef32_sr_pk8_bf8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_BF8_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2869,8 +3398,7 @@ VCvtScalef32SrPk8Bf8Bf16Vop3::VCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk8_bf8_bf16_e64_dpp" : "v_cvt_scalef32_sr_pk8_bf8_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Bf8Bf16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk8Bf8Bf16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2889,9 +3417,6 @@ VCvtScalef32SrPk8Bf8Bf16Vop3::VCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK8_BF8_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2899,7 +3424,19 @@ VCvtScalef32SrPk8Bf8Bf16Vop3::VCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk8Bf8Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk8_bf8_bf16_e64_dpp" + : "v_cvt_scalef32_sr_pk8_bf8_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK8_BF8_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2909,8 +3446,7 @@ VCvtScalef32Pk8Fp8F32Vop3::VCvtScalef32Pk8Fp8F32Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_fp8_f32_e64_dpp" : "v_cvt_scalef32_pk8_fp8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp8F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp8F32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2923,16 +3459,25 @@ VCvtScalef32Pk8Fp8F32Vop3::VCvtScalef32Pk8Fp8F32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_FP8_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Fp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Fp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_fp8_f32_e64_dpp" + : "v_cvt_scalef32_pk8_fp8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_FP8_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2942,8 +3487,7 @@ VCvtScalef32Pk8Fp8F16Vop3::VCvtScalef32Pk8Fp8F16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_fp8_f16_e64_dpp" : "v_cvt_scalef32_pk8_fp8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp8F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Fp8F16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2956,16 +3500,25 @@ VCvtScalef32Pk8Fp8F16Vop3::VCvtScalef32Pk8Fp8F16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_FP8_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Fp8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Fp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_fp8_f16_e64_dpp" + : "v_cvt_scalef32_pk8_fp8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_FP8_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2975,8 +3528,7 @@ VCvtScalef32Pk8Bf8F32Vop3::VCvtScalef32Pk8Bf8F32Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_bf8_f32_e64_dpp" : "v_cvt_scalef32_pk8_bf8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Bf8F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Bf8F32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -2989,16 +3541,25 @@ VCvtScalef32Pk8Bf8F32Vop3::VCvtScalef32Pk8Bf8F32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_BF8_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Bf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Bf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_bf8_f32_e64_dpp" + : "v_cvt_scalef32_pk8_bf8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_BF8_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3008,8 +3569,7 @@ VCvtScalef32Pk8Bf8F16Vop3::VCvtScalef32Pk8Bf8F16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk8_bf8_f16_e64_dpp" : "v_cvt_scalef32_pk8_bf8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Bf8F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk8Bf8F16Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(128, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3022,16 +3582,25 @@ VCvtScalef32Pk8Bf8F16Vop3::VCvtScalef32Pk8Bf8F16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK8_BF8_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk8Bf8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk8Bf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk8_bf8_f16_e64_dpp" + : "v_cvt_scalef32_pk8_bf8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK8_BF8_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3041,8 +3610,7 @@ VCvtScalePk16F16Fp6Vop3::VCvtScalePk16F16Fp6Vop3(const MachineInst *inst) ? "v_cvt_scale_pk16_f16_fp6_e64_dpp" : "v_cvt_scale_pk16_f16_fp6", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk16F16Fp6Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk16F16Fp6Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(96, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3055,16 +3623,25 @@ VCvtScalePk16F16Fp6Vop3::VCvtScalePk16F16Fp6Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK16_F16_FP6 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk16F16Fp6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk16F16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk16_f16_fp6_e64_dpp" + : "v_cvt_scale_pk16_f16_fp6", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK16_F16_FP6 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3074,8 +3651,7 @@ VCvtScalePk16Bf16Fp6Vop3::VCvtScalePk16Bf16Fp6Vop3(const MachineInst *inst) ? "v_cvt_scale_pk16_bf16_fp6_e64_dpp" : "v_cvt_scale_pk16_bf16_fp6", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk16Bf16Fp6Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk16Bf16Fp6Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(96, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3088,16 +3664,25 @@ VCvtScalePk16Bf16Fp6Vop3::VCvtScalePk16Bf16Fp6Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK16_BF16_FP6 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk16Bf16Fp6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk16Bf16Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk16_bf16_fp6_e64_dpp" + : "v_cvt_scale_pk16_bf16_fp6", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK16_BF16_FP6 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3107,8 +3692,7 @@ VCvtScalePk16F32Fp6Vop3::VCvtScalePk16F32Fp6Vop3(const MachineInst *inst) ? "v_cvt_scale_pk16_f32_fp6_e64_dpp" : "v_cvt_scale_pk16_f32_fp6", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk16F32Fp6Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk16F32Fp6Vop3)), vdst(512, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(96, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3121,16 +3705,25 @@ VCvtScalePk16F32Fp6Vop3::VCvtScalePk16F32Fp6Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK16_F32_FP6 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk16F32Fp6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk16F32Fp6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk16_f32_fp6_e64_dpp" + : "v_cvt_scale_pk16_f32_fp6", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK16_F32_FP6 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3140,8 +3733,7 @@ VCvtScalePk16F16Bf6Vop3::VCvtScalePk16F16Bf6Vop3(const MachineInst *inst) ? "v_cvt_scale_pk16_f16_bf6_e64_dpp" : "v_cvt_scale_pk16_f16_bf6", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk16F16Bf6Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk16F16Bf6Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(96, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3154,16 +3746,25 @@ VCvtScalePk16F16Bf6Vop3::VCvtScalePk16F16Bf6Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK16_F16_BF6 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk16F16Bf6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk16F16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk16_f16_bf6_e64_dpp" + : "v_cvt_scale_pk16_f16_bf6", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK16_F16_BF6 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3173,8 +3774,7 @@ VCvtScalePk16Bf16Bf6Vop3::VCvtScalePk16Bf16Bf6Vop3(const MachineInst *inst) ? "v_cvt_scale_pk16_bf16_bf6_e64_dpp" : "v_cvt_scale_pk16_bf16_bf6", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk16Bf16Bf6Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk16Bf16Bf6Vop3)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(96, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3187,16 +3787,25 @@ VCvtScalePk16Bf16Bf6Vop3::VCvtScalePk16Bf16Bf6Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK16_BF16_BF6 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk16Bf16Bf6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk16Bf16Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk16_bf16_bf6_e64_dpp" + : "v_cvt_scale_pk16_bf16_bf6", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK16_BF16_BF6 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3206,8 +3815,7 @@ VCvtScalePk16F32Bf6Vop3::VCvtScalePk16F32Bf6Vop3(const MachineInst *inst) ? "v_cvt_scale_pk16_f32_bf6_e64_dpp" : "v_cvt_scale_pk16_f32_bf6", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalePk16F32Bf6Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalePk16F32Bf6Vop3)), vdst(512, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(96, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3220,16 +3828,25 @@ VCvtScalePk16F32Bf6Vop3::VCvtScalePk16F32Bf6Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALE_PK16_F32_BF6 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalePk16F32Bf6Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalePk16F32Bf6Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scale_pk16_f32_bf6_e64_dpp" + : "v_cvt_scale_pk16_f32_bf6", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALE_PK16_F32_BF6 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3239,8 +3856,7 @@ VCvtScalef32Pk16Fp6F32Vop3::VCvtScalef32Pk16Fp6F32Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk16_fp6_f32_e64_dpp" : "v_cvt_scalef32_pk16_fp6_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Fp6F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Fp6F32Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3253,16 +3869,25 @@ VCvtScalef32Pk16Fp6F32Vop3::VCvtScalef32Pk16Fp6F32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK16_FP6_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk16Fp6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk16Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk16_fp6_f32_e64_dpp" + : "v_cvt_scalef32_pk16_fp6_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK16_FP6_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3272,8 +3897,7 @@ VCvtScalef32Pk16Bf6F32Vop3::VCvtScalef32Pk16Bf6F32Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk16_bf6_f32_e64_dpp" : "v_cvt_scalef32_pk16_bf6_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Bf6F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Bf6F32Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3286,16 +3910,25 @@ VCvtScalef32Pk16Bf6F32Vop3::VCvtScalef32Pk16Bf6F32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK16_BF6_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk16Bf6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk16Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk16_bf6_f32_e64_dpp" + : "v_cvt_scalef32_pk16_bf6_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK16_BF6_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3305,8 +3938,7 @@ VCvtScalef32Pk16Fp6F16Vop3::VCvtScalef32Pk16Fp6F16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk16_fp6_f16_e64_dpp" : "v_cvt_scalef32_pk16_fp6_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Fp6F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Fp6F16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3319,16 +3951,25 @@ VCvtScalef32Pk16Fp6F16Vop3::VCvtScalef32Pk16Fp6F16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK16_FP6_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk16Fp6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk16Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk16_fp6_f16_e64_dpp" + : "v_cvt_scalef32_pk16_fp6_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK16_FP6_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3338,8 +3979,7 @@ VCvtScalef32Pk16Bf6F16Vop3::VCvtScalef32Pk16Bf6F16Vop3(const MachineInst *inst) ? "v_cvt_scalef32_pk16_bf6_f16_e64_dpp" : "v_cvt_scalef32_pk16_bf6_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Bf6F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Bf6F16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3352,16 +3992,25 @@ VCvtScalef32Pk16Bf6F16Vop3::VCvtScalef32Pk16Bf6F16Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK16_BF6_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk16Bf6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk16Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk16_bf6_f16_e64_dpp" + : "v_cvt_scalef32_pk16_bf6_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK16_BF6_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3371,8 +4020,7 @@ VCvtScalef32Pk16Fp6Bf16Vop3::VCvtScalef32Pk16Fp6Bf16Vop3(const MachineInst *inst ? "v_cvt_scalef32_pk16_fp6_bf16_e64_dpp" : "v_cvt_scalef32_pk16_fp6_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Fp6Bf16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Fp6Bf16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3385,16 +4033,25 @@ VCvtScalef32Pk16Fp6Bf16Vop3::VCvtScalef32Pk16Fp6Bf16Vop3(const MachineInst *inst src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK16_FP6_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk16Fp6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk16Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk16_fp6_bf16_e64_dpp" + : "v_cvt_scalef32_pk16_fp6_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK16_FP6_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3404,8 +4061,7 @@ VCvtScalef32Pk16Bf6Bf16Vop3::VCvtScalef32Pk16Bf6Bf16Vop3(const MachineInst *inst ? "v_cvt_scalef32_pk16_bf6_bf16_e64_dpp" : "v_cvt_scalef32_pk16_bf6_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Bf6Bf16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtScalef32Pk16Bf6Bf16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3418,16 +4074,25 @@ VCvtScalef32Pk16Bf6Bf16Vop3::VCvtScalef32Pk16Bf6Bf16Vop3(const MachineInst *inst src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_PK16_BF6_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCvtScalef32Pk16Bf6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32Pk16Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_pk16_bf6_bf16_e64_dpp" + : "v_cvt_scalef32_pk16_bf6_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_PK16_BF6_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3437,8 +4102,7 @@ VCvtScalef32SrPk16Fp6F32Vop3::VCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk16_fp6_f32_e64_dpp" : "v_cvt_scalef32_sr_pk16_fp6_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Fp6F32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Fp6F32Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3457,9 +4121,6 @@ VCvtScalef32SrPk16Fp6F32Vop3::VCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK16_FP6_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3467,7 +4128,19 @@ VCvtScalef32SrPk16Fp6F32Vop3::VCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk16Fp6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk16_fp6_f32_e64_dpp" + : "v_cvt_scalef32_sr_pk16_fp6_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK16_FP6_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3477,8 +4150,7 @@ VCvtScalef32SrPk16Bf6F32Vop3::VCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk16_bf6_f32_e64_dpp" : "v_cvt_scalef32_sr_pk16_bf6_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Bf6F32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Bf6F32Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3497,9 +4169,6 @@ VCvtScalef32SrPk16Bf6F32Vop3::VCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK16_BF6_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3507,7 +4176,19 @@ VCvtScalef32SrPk16Bf6F32Vop3::VCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk16Bf6F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk16_bf6_f32_e64_dpp" + : "v_cvt_scalef32_sr_pk16_bf6_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK16_BF6_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3517,8 +4198,7 @@ VCvtScalef32SrPk16Fp6F16Vop3::VCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk16_fp6_f16_e64_dpp" : "v_cvt_scalef32_sr_pk16_fp6_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Fp6F16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Fp6F16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3537,9 +4217,6 @@ VCvtScalef32SrPk16Fp6F16Vop3::VCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK16_FP6_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3547,7 +4224,19 @@ VCvtScalef32SrPk16Fp6F16Vop3::VCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk16Fp6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk16_fp6_f16_e64_dpp" + : "v_cvt_scalef32_sr_pk16_fp6_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK16_FP6_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3557,8 +4246,7 @@ VCvtScalef32SrPk16Bf6F16Vop3::VCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *in ? "v_cvt_scalef32_sr_pk16_bf6_f16_e64_dpp" : "v_cvt_scalef32_sr_pk16_bf6_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Bf6F16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Bf6F16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3577,9 +4265,6 @@ VCvtScalef32SrPk16Bf6F16Vop3::VCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *in src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK16_BF6_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3587,7 +4272,19 @@ VCvtScalef32SrPk16Bf6F16Vop3::VCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *in } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk16Bf6F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk16_bf6_f16_e64_dpp" + : "v_cvt_scalef32_sr_pk16_bf6_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK16_BF6_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3597,8 +4294,7 @@ VCvtScalef32SrPk16Fp6Bf16Vop3::VCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst * ? "v_cvt_scalef32_sr_pk16_fp6_bf16_e64_dpp" : "v_cvt_scalef32_sr_pk16_fp6_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Fp6Bf16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Fp6Bf16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3617,9 +4313,6 @@ VCvtScalef32SrPk16Fp6Bf16Vop3::VCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst * src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK16_FP6_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3627,7 +4320,19 @@ VCvtScalef32SrPk16Fp6Bf16Vop3::VCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst * } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk16Fp6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk16_fp6_bf16_e64_dpp" + : "v_cvt_scalef32_sr_pk16_fp6_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK16_FP6_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3637,8 +4342,7 @@ VCvtScalef32SrPk16Bf6Bf16Vop3::VCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst * ? "v_cvt_scalef32_sr_pk16_bf6_bf16_e64_dpp" : "v_cvt_scalef32_sr_pk16_bf6_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Bf6Bf16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtScalef32SrPk16Bf6Bf16Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3657,9 +4361,6 @@ VCvtScalef32SrPk16Bf6Bf16Vop3::VCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst * src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_SCALEF32_SR_PK16_BF6_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3667,7 +4368,19 @@ VCvtScalef32SrPk16Bf6Bf16Vop3::VCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst * } namespace detail { -std::unique_ptr decodeVCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtScalef32SrPk16Bf6Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_scalef32_sr_pk16_bf6_bf16_e64_dpp" + : "v_cvt_scalef32_sr_pk16_bf6_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_SCALEF32_SR_PK16_BF6_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3677,8 +4390,7 @@ VCvtPkI16F32Vop3::VCvtPkI16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_i16_f32_e64_dpp" : "v_cvt_pk_i16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkI16F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkI16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3718,7 +4430,16 @@ VCvtPkI16F32Vop3::VCvtPkI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_f32_e64_dpp" + : "v_cvt_pk_i16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3728,8 +4449,7 @@ VCvtPkU16F32Vop3::VCvtPkU16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_u16_f32_e64_dpp" : "v_cvt_pk_u16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkU16F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkU16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3769,7 +4489,16 @@ VCvtPkU16F32Vop3::VCvtPkU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_f32_e64_dpp" + : "v_cvt_pk_u16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3779,7 +4508,7 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) ? "v_pack_b32_f16_e64_dpp" : "v_pack_b32_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPackB32F16Vop3), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPackB32F16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3827,7 +4556,16 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pack_b32_f16_e64_dpp" + : "v_pack_b32_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3837,8 +4575,7 @@ VCvtPkNormI16F16Vop3::VCvtPkNormI16F16Vop3(const MachineInst *inst) ? "v_cvt_pk_norm_i16_f16_e64_dpp" : "v_cvt_pk_norm_i16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkNormI16F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtPkNormI16F16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3886,7 +4623,16 @@ VCvtPkNormI16F16Vop3::VCvtPkNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f16_e64_dpp" + : "v_cvt_pk_norm_i16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3896,8 +4642,7 @@ VCvtPkNormU16F16Vop3::VCvtPkNormU16F16Vop3(const MachineInst *inst) ? "v_cvt_pk_norm_u16_f16_e64_dpp" : "v_cvt_pk_norm_u16_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkNormU16F16Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtPkNormU16F16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3945,7 +4690,16 @@ VCvtPkNormU16F16Vop3::VCvtPkNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f16_e64_dpp" + : "v_cvt_pk_norm_u16_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3955,8 +4709,7 @@ VCvtPkNormI16F32Vop3::VCvtPkNormI16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_norm_i16_f32_e64_dpp" : "v_cvt_pk_norm_i16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkNormI16F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtPkNormI16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -3996,7 +4749,16 @@ VCvtPkNormI16F32Vop3::VCvtPkNormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f32_e64_dpp" + : "v_cvt_pk_norm_i16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4006,8 +4768,7 @@ VCvtPkNormU16F32Vop3::VCvtPkNormU16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_norm_u16_f32_e64_dpp" : "v_cvt_pk_norm_u16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkNormU16F32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VCvtPkNormU16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4047,7 +4808,16 @@ VCvtPkNormU16F32Vop3::VCvtPkNormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f32_e64_dpp" + : "v_cvt_pk_norm_u16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4057,8 +4827,7 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) ? "v_cvt_pk_u16_u32_e64_dpp" : "v_cvt_pk_u16_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkU16U32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkU16U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4098,7 +4867,16 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_u32_e64_dpp" + : "v_cvt_pk_u16_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4108,8 +4886,7 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) ? "v_cvt_pk_i16_i32_e64_dpp" : "v_cvt_pk_i16_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkI16I32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkI16I32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4149,7 +4926,16 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_i32_e64_dpp" + : "v_cvt_pk_i16_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4159,8 +4945,7 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) ? "v_cvt_pk_fp8_f32_e64_dpp" : "v_cvt_pk_fp8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkFp8F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkFp8F32Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4200,7 +4985,16 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_fp8_f32_e64_dpp" + : "v_cvt_pk_fp8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4223,8 +5017,7 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) ? "v_cvt_pk_bf8_f32_e64_dpp" : "v_cvt_pk_bf8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkBf8F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkBf8F32Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4264,7 +5057,16 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_bf8_f32_e64_dpp" + : "v_cvt_pk_bf8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4287,8 +5089,7 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) ? "v_cvt_sr_fp8_f32_e64_dpp" : "v_cvt_sr_fp8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtSrFp8F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtSrFp8F32Vop3)), vdst(8, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4328,7 +5129,16 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_fp8_f32_e64_dpp" + : "v_cvt_sr_fp8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4351,8 +5161,7 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) ? "v_cvt_sr_bf8_f32_e64_dpp" : "v_cvt_sr_bf8_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtSrBf8F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtSrBf8F32Vop3)), vdst(8, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4392,7 +5201,16 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_bf8_f32_e64_dpp" + : "v_cvt_sr_bf8_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4415,8 +5233,7 @@ VCvtPkBf16F32Vop3::VCvtPkBf16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_bf16_f32_e64_dpp" : "v_cvt_pk_bf16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkBf16F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkBf16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4456,7 +5273,16 @@ VCvtPkBf16F32Vop3::VCvtPkBf16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_bf16_f32_e64_dpp" + : "v_cvt_pk_bf16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4466,8 +5292,7 @@ VCvtSrPkBf16F32Vop3::VCvtSrPkBf16F32Vop3(const MachineInst *inst) ? "v_cvt_sr_pk_bf16_f32_e64_dpp" : "v_cvt_sr_pk_bf16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtSrPkBf16F32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtSrPkBf16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4514,7 +5339,16 @@ VCvtSrPkBf16F32Vop3::VCvtSrPkBf16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrPkBf16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrPkBf16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_pk_bf16_f32_e64_dpp" + : "v_cvt_sr_pk_bf16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4524,8 +5358,7 @@ VCvtPkF16F32Vop3::VCvtPkF16F32Vop3(const MachineInst *inst) ? "v_cvt_pk_f16_f32_e64_dpp" : "v_cvt_pk_f16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkF16F32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtPkF16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4565,7 +5398,16 @@ VCvtPkF16F32Vop3::VCvtPkF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f16_f32_e64_dpp" + : "v_cvt_pk_f16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4575,7 +5417,7 @@ VCvtSrPkF16F32Vop3::VCvtSrPkF16F32Vop3(const MachineInst *inst) ? "v_cvt_sr_pk_f16_f32_e64_dpp" : "v_cvt_sr_pk_f16_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtSrPkF16F32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCvtSrPkF16F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4622,7 +5464,16 @@ VCvtSrPkF16F32Vop3::VCvtSrPkF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrPkF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrPkF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_pk_f16_f32_e64_dpp" + : "v_cvt_sr_pk_f16_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4632,8 +5483,7 @@ VCvtPkFp8F16Vop3::VCvtPkFp8F16Vop3(const MachineInst *inst) ? "v_cvt_pk_fp8_f16_e64_dpp" : "v_cvt_pk_fp8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkFp8F16Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtPkFp8F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOINLINE, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -4666,7 +5516,16 @@ VCvtPkFp8F16Vop3::VCvtPkFp8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkFp8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_fp8_f16_e64_dpp" + : "v_cvt_pk_fp8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4689,8 +5548,7 @@ VCvtPkBf8F16Vop3::VCvtPkBf8F16Vop3(const MachineInst *inst) ? "v_cvt_pk_bf8_f16_e64_dpp" : "v_cvt_pk_bf8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtPkBf8F16Vop3), LiteralSupport::Literal32, - 1), + selected_exec_fn(InstructionExecutionId::VCvtPkBf8F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_NOINLINE, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -4723,7 +5581,16 @@ VCvtPkBf8F16Vop3::VCvtPkBf8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_bf8_f16_e64_dpp" + : "v_cvt_pk_bf8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4746,8 +5613,7 @@ VCvtSrFp8F16Vop3::VCvtSrFp8F16Vop3(const MachineInst *inst) ? "v_cvt_sr_fp8_f16_e64_dpp" : "v_cvt_sr_fp8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtSrFp8F16Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtSrFp8F16Vop3)), vdst(8, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4791,7 +5657,16 @@ VCvtSrFp8F16Vop3::VCvtSrFp8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrFp8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrFp8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_fp8_f16_e64_dpp" + : "v_cvt_sr_fp8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4814,8 +5689,7 @@ VCvtSrBf8F16Vop3::VCvtSrBf8F16Vop3(const MachineInst *inst) ? "v_cvt_sr_bf8_f16_e64_dpp" : "v_cvt_sr_bf8_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCvtSrBf8F16Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VCvtSrBf8F16Vop3)), vdst(8, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -4859,7 +5733,16 @@ VCvtSrBf8F16Vop3::VCvtSrBf8F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrBf8F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrBf8F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_bf8_f16_e64_dpp" + : "v_cvt_sr_bf8_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_data.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_data.cpp index 7b60a9fdffd8..8f3efcd1b984 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_data.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_data.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -18,7 +17,7 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) ? "v_mov_b32_e64_dpp" : "v_mov_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovB32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VMovB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -51,7 +50,15 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_e64_dpp" + : "v_mov_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,22 +68,30 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) ? "v_readfirstlane_b32_e64_dpp" : "v_readfirstlane_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VReadfirstlaneB32Vop3), LiteralSupport::None, - 1), + selected_exec_fn(InstructionExecutionId::VReadfirstlaneB32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_e64_dpp" + : "v_readfirstlane_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -86,7 +101,7 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) ? "v_mov_b16_e64_dpp" : "v_mov_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovB16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VMovB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -123,7 +138,15 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_e64_dpp" + : "v_mov_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -145,7 +168,7 @@ VMovB64Vop3::VMovB64Vop3(const MachineInst *inst) ? "v_mov_b64_e64_dpp" : "v_mov_b64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovB64Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VMovB64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -166,14 +189,22 @@ VMovB64Vop3::VMovB64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MOV_B64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVMovB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b64_e64_dpp" + : "v_mov_b64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MOV_B64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -183,7 +214,7 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) ? "v_movreld_b32_e64_dpp" : "v_movreld_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovreldB32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VMovreldB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -219,7 +250,16 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_e64_dpp" + : "v_movreld_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -229,7 +269,7 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) ? "v_movrels_b32_e64_dpp" : "v_movrels_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovrelsB32Vop3), LiteralSupport::None, 1), + selected_exec_fn(InstructionExecutionId::VMovrelsB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -261,7 +301,16 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_e64_dpp" + : "v_movrels_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -271,8 +320,7 @@ VPermlane16SwapB32Vop3::VPermlane16SwapB32Vop3(const MachineInst *inst) ? "v_permlane16_swap_b32_e64_dpp" : "v_permlane16_swap_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlane16SwapB32Vop3), LiteralSupport::None, - 0), + selected_exec_fn(InstructionExecutionId::VPermlane16SwapB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -281,15 +329,24 @@ VPermlane16SwapB32Vop3::VPermlane16SwapB32Vop3(const MachineInst *inst) src_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_SWAP_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlane16SwapB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16SwapB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_swap_b32_e64_dpp" + : "v_permlane16_swap_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_SWAP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -299,7 +356,7 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) ? "v_cndmask_b32_e64_dpp" : "v_cndmask_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCndmaskB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCndmaskB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -341,7 +398,16 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_e64_dpp" + : "v_cndmask_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -351,7 +417,7 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) ? "v_cubeid_f32_e64_dpp" : "v_cubeid_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCubeidF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCubeidF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -398,7 +464,15 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubeid_f32_e64_dpp" + : "v_cubeid_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +482,7 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) ? "v_cubesc_f32_e64_dpp" : "v_cubesc_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCubescF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCubescF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -455,7 +529,15 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubesc_f32_e64_dpp" + : "v_cubesc_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -465,7 +547,7 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) ? "v_cubetc_f32_e64_dpp" : "v_cubetc_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCubetcF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCubetcF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -512,7 +594,15 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubetc_f32_e64_dpp" + : "v_cubetc_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -522,7 +612,7 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) ? "v_cubema_f32_e64_dpp" : "v_cubema_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCubemaF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCubemaF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -569,7 +659,15 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubema_f32_e64_dpp" + : "v_cubema_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -579,7 +677,7 @@ VPermPk16B4U4Vop3::VPermPk16B4U4Vop3(const MachineInst *inst) ? "v_perm_pk16_b4_u4_e64_dpp" : "v_perm_pk16_b4_u4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermPk16B4U4Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermPk16B4U4Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -603,9 +701,6 @@ VPermPk16B4U4Vop3::VPermPk16B4U4Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERM_PK16_B4_U4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -613,7 +708,19 @@ VPermPk16B4U4Vop3::VPermPk16B4U4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermPk16B4U4Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermPk16B4U4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_pk16_b4_u4_e64_dpp" + : "v_perm_pk16_b4_u4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERM_PK16_B4_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -623,7 +730,7 @@ VPermPk16B6U4Vop3::VPermPk16B6U4Vop3(const MachineInst *inst) ? "v_perm_pk16_b6_u4_e64_dpp" : "v_perm_pk16_b6_u4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermPk16B6U4Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermPk16B6U4Vop3)), vdst(96, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -648,9 +755,6 @@ VPermPk16B6U4Vop3::VPermPk16B6U4Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERM_PK16_B6_U4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -658,7 +762,19 @@ VPermPk16B6U4Vop3::VPermPk16B6U4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermPk16B6U4Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermPk16B6U4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_pk16_b6_u4_e64_dpp" + : "v_perm_pk16_b6_u4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERM_PK16_B6_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -668,7 +784,7 @@ VPermPk16B8U4Vop3::VPermPk16B8U4Vop3(const MachineInst *inst) ? "v_perm_pk16_b8_u4_e64_dpp" : "v_perm_pk16_b8_u4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermPk16B8U4Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermPk16B8U4Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -694,9 +810,6 @@ VPermPk16B8U4Vop3::VPermPk16B8U4Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERM_PK16_B8_U4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -704,7 +817,19 @@ VPermPk16B8U4Vop3::VPermPk16B8U4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermPk16B8U4Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermPk16B8U4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_pk16_b8_u4_e64_dpp" + : "v_perm_pk16_b8_u4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERM_PK16_B8_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -714,7 +839,7 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) ? "v_perm_b32_e64_dpp" : "v_perm_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -761,7 +886,15 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_b32_e64_dpp" + : "v_perm_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -771,7 +904,7 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) ? "v_permlane16_b32_e64_dpp" : "v_permlane16_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlane16B32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermlane16B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1), @@ -790,15 +923,24 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_b32_e64_dpp" + : "v_permlane16_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -808,8 +950,7 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) ? "v_permlanex16_b32_e64_dpp" : "v_permlanex16_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlanex16B32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermlanex16B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1), @@ -828,15 +969,24 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANEX16_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlanex16_b32_e64_dpp" + : "v_permlanex16_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANEX16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -846,7 +996,7 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) ? "v_cndmask_b16_e64_dpp" : "v_cndmask_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VCndmaskB16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VCndmaskB16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -896,7 +1046,16 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b16_e64_dpp" + : "v_cndmask_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -919,8 +1078,7 @@ VPermlaneBcastB32Vop3::VPermlaneBcastB32Vop3(const MachineInst *inst) ? "v_permlane_bcast_b32_e64_dpp" : "v_permlane_bcast_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlaneBcastB32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermlaneBcastB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1), @@ -939,15 +1097,24 @@ VPermlaneBcastB32Vop3::VPermlaneBcastB32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE_BCAST_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlaneBcastB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlaneBcastB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane_bcast_b32_e64_dpp" + : "v_permlane_bcast_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE_BCAST_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -957,7 +1124,7 @@ VPermlaneUpB32Vop3::VPermlaneUpB32Vop3(const MachineInst *inst) ? "v_permlane_up_b32_e64_dpp" : "v_permlane_up_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlaneUpB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermlaneUpB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1), @@ -976,15 +1143,24 @@ VPermlaneUpB32Vop3::VPermlaneUpB32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE_UP_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlaneUpB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlaneUpB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane_up_b32_e64_dpp" + : "v_permlane_up_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE_UP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -994,8 +1170,7 @@ VPermlaneDownB32Vop3::VPermlaneDownB32Vop3(const MachineInst *inst) ? "v_permlane_down_b32_e64_dpp" : "v_permlane_down_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlaneDownB32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermlaneDownB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1), @@ -1014,15 +1189,24 @@ VPermlaneDownB32Vop3::VPermlaneDownB32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE_DOWN_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlaneDownB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlaneDownB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane_down_b32_e64_dpp" + : "v_permlane_down_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE_DOWN_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1032,8 +1216,7 @@ VPermlaneXorB32Vop3::VPermlaneXorB32Vop3(const MachineInst *inst) ? "v_permlane_xor_b32_e64_dpp" : "v_permlane_xor_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlaneXorB32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPermlaneXorB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1), @@ -1052,15 +1235,24 @@ VPermlaneXorB32Vop3::VPermlaneXorB32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE_XOR_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlaneXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlaneXorB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane_xor_b32_e64_dpp" + : "v_permlane_xor_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE_XOR_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1070,8 +1262,7 @@ VPermlane16VarB32Vop3::VPermlane16VarB32Vop3(const MachineInst *inst) ? "v_permlane16_var_b32_e64_dpp" : "v_permlane16_var_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlane16VarB32Vop3), LiteralSupport::None, - 2), + selected_exec_fn(InstructionExecutionId::VPermlane16VarB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1) { @@ -1080,16 +1271,25 @@ VPermlane16VarB32Vop3::VPermlane16VarB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_VAR_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPermlane16VarB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_var_b32_e64_dpp" + : "v_permlane16_var_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_VAR_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1099,8 +1299,7 @@ VPermlanex16VarB32Vop3::VPermlanex16VarB32Vop3(const MachineInst *inst) ? "v_permlanex16_var_b32_e64_dpp" : "v_permlanex16_var_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlanex16VarB32Vop3), LiteralSupport::None, - 2), + selected_exec_fn(InstructionExecutionId::VPermlanex16VarB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1) { @@ -1109,16 +1308,25 @@ VPermlanex16VarB32Vop3::VPermlanex16VarB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANEX16_VAR_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPermlanex16VarB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlanex16_var_b32_e64_dpp" + : "v_permlanex16_var_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANEX16_VAR_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1128,8 +1336,7 @@ VPermlaneIdxGenB32Vop3::VPermlaneIdxGenB32Vop3(const MachineInst *inst) ? "v_permlane_idx_gen_b32_e64_dpp" : "v_permlane_idx_gen_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPermlaneIdxGenB32Vop3), - LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPermlaneIdxGenB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src1) { @@ -1142,15 +1349,24 @@ VPermlaneIdxGenB32Vop3::VPermlaneIdxGenB32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE_IDX_GEN_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVPermlaneIdxGenB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlaneIdxGenB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane_idx_gen_b32_e64_dpp" + : "v_permlane_idx_gen_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE_IDX_GEN_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1160,7 +1376,7 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) ? "v_readlane_b32_e64_dpp" : "v_readlane_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VReadlaneB32Vop3), LiteralSupport::None, 2), + selected_exec_fn(InstructionExecutionId::VReadlaneB32Vop3)), vdst(32, OperandType::OPR_SREG, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC_LANESEL, reinterpret_cast(inst)->src1) { @@ -1169,14 +1385,23 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READLANE_B32 does not support DPP", ""); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readlane_b32_e64_dpp" + : "v_readlane_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1186,8 +1411,7 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) ? "v_writelane_b32_e64_dpp" : "v_writelane_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWritelaneB32Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VWritelaneB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SSRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SSRC_LANESEL, reinterpret_cast(inst)->src1) { @@ -1201,14 +1425,23 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WRITELANE_B32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_writelane_b32_e64_dpp" + : "v_writelane_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_WRITELANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp index 3edd4686df6d..b3537a235be2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -18,13 +17,21 @@ VNopVop3::VNopVop3(const MachineInst *inst) ? "v_nop_e64_dpp" : "v_nop", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VNopVop3), LiteralSupport::None, 0) { + selected_exec_fn(InstructionExecutionId::VNopVop3)) { num_src_ = 0; num_dst_ = 0; } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_e64_dpp" + : "v_nop", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -34,13 +41,21 @@ VPipeflushVop3::VPipeflushVop3(const MachineInst *inst) ? "v_pipeflush_e64_dpp" : "v_pipeflush", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPipeflushVop3), LiteralSupport::None, 0) { + selected_exec_fn(InstructionExecutionId::VPipeflushVop3)) { num_src_ = 0; num_dst_ = 0; } namespace detail { -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_e64_dpp" + : "v_pipeflush", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 0); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -50,7 +65,7 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) ? "v_movrelsd_b32_e64_dpp" : "v_movrelsd_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovrelsdB32Vop3), LiteralSupport::None, 1), + selected_exec_fn(InstructionExecutionId::VMovrelsdB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -82,7 +97,16 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_e64_dpp" + : "v_movrelsd_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -92,7 +116,7 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) ? "v_movrelsd_2_b32_e64_dpp" : "v_movrelsd_2_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMovrelsd2B32Vop3), LiteralSupport::None, 1), + selected_exec_fn(InstructionExecutionId::VMovrelsd2B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), m0(32, OperandType::OPR_SDST_M0, 125) { @@ -124,7 +148,16 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_e64_dpp" + : "v_movrelsd_2_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -134,7 +167,7 @@ VPrngB32Vop3::VPrngB32Vop3(const MachineInst *inst) ? "v_prng_b32_e64_dpp" : "v_prng_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPrngB32Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VPrngB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -167,7 +200,15 @@ VPrngB32Vop3::VPrngB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPrngB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPrngB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_prng_b32_e64_dpp" + : "v_prng_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -177,7 +218,7 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) ? "v_sat_pk_u8_i16_e64_dpp" : "v_sat_pk_u8_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSatPkU8I16Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSatPkU8I16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -210,7 +251,16 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_e64_dpp" + : "v_sat_pk_u8_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +283,7 @@ VSatPk4I4I8Vop3::VSatPk4I4I8Vop3(const MachineInst *inst) ? "v_sat_pk4_i4_i8_e64_dpp" : "v_sat_pk4_i4_i8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSatPk4I4I8Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSatPk4I4I8Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -266,7 +316,16 @@ VSatPk4I4I8Vop3::VSatPk4I4I8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPk4I4I8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPk4I4I8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk4_i4_i8_e64_dpp" + : "v_sat_pk4_i4_i8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +348,7 @@ VSatPk4U4U8Vop3::VSatPk4U4U8Vop3(const MachineInst *inst) ? "v_sat_pk4_u4_u8_e64_dpp" : "v_sat_pk4_u4_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSatPk4U4U8Vop3), LiteralSupport::Literal32, 1), + selected_exec_fn(InstructionExecutionId::VSatPk4U4U8Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0) { dst_operands_[0] = &vdst; @@ -322,7 +381,16 @@ VSatPk4U4U8Vop3::VSatPk4U4U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPk4U4U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPk4U4U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk4_u4_u8_e64_dpp" + : "v_sat_pk4_u4_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 1); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -345,7 +413,7 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) ? "v_mullit_f32_e64_dpp" : "v_mullit_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMullitF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMullitF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -392,7 +460,15 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mullit_f32_e64_dpp" + : "v_mullit_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -402,7 +478,7 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) ? "v_qsad_pk_u16_u8_e64_dpp" : "v_qsad_pk_u16_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VQsadPkU16U8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VQsadPkU16U8Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -427,9 +503,6 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_QSAD_PK_U16_U8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -437,7 +510,19 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_qsad_pk_u16_u8_e64_dpp" + : "v_qsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_QSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -447,7 +532,7 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) ? "v_mqsad_pk_u16_u8_e64_dpp" : "v_mqsad_pk_u16_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMqsadPkU16U8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMqsadPkU16U8Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -472,9 +557,6 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_PK_U16_U8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -482,7 +564,19 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_pk_u16_u8_e64_dpp" + : "v_mqsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -492,7 +586,7 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) ? "v_mqsad_u32_u8_e64_dpp" : "v_mqsad_u32_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMqsadU32U8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMqsadU32U8Vop3)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -512,9 +606,6 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_U32_U8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -522,7 +613,19 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_u32_u8_e64_dpp" + : "v_mqsad_u32_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -532,8 +635,7 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) ? "v_trig_preop_f64_e64_dpp" : "v_trig_preop_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VTrigPreopF64Vop3), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VTrigPreopF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -551,16 +653,25 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRIG_PREOP_F64 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trig_preop_f64_e64_dpp" + : "v_trig_preop_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRIG_PREOP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_ternary.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_ternary.cpp index 292d9c1b332a..5aae89826d2a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_ternary.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_ternary.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -18,7 +17,7 @@ VFmaDx9ZeroF32Vop3::VFmaDx9ZeroF32Vop3(const MachineInst *inst) ? "v_fma_dx9_zero_f32_e64_dpp" : "v_fma_dx9_zero_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaDx9ZeroF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaDx9ZeroF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -65,7 +64,16 @@ VFmaDx9ZeroF32Vop3::VFmaDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_dx9_zero_f32_e64_dpp" + : "v_fma_dx9_zero_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +83,7 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) ? "v_mad_i32_i24_e64_dpp" : "v_mad_i32_i24", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadI32I24Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadI32I24Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(24, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(24, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -122,7 +130,15 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i24_e64_dpp" + : "v_mad_i32_i24", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -132,7 +148,7 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) ? "v_mad_u32_u24_e64_dpp" : "v_mad_u32_u24", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadU32U24Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadU32U24Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(24, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(24, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -179,7 +195,15 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u24_e64_dpp" + : "v_mad_u32_u24", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -189,7 +213,7 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) ? "v_bfe_u32_e64_dpp" : "v_bfe_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBfeU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VBfeU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -236,7 +260,15 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_u32_e64_dpp" + : "v_bfe_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +278,7 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) ? "v_bfe_i32_e64_dpp" : "v_bfe_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBfeI32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VBfeI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -293,7 +325,15 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_i32_e64_dpp" + : "v_bfe_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -303,7 +343,7 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) ? "v_bfi_b32_e64_dpp" : "v_bfi_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBfiB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VBfiB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -350,7 +390,15 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfi_b32_e64_dpp" + : "v_bfi_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +408,7 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) ? "v_fma_f32_e64_dpp" : "v_fma_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -407,7 +455,15 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f32_e64_dpp" + : "v_fma_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -417,7 +473,7 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) ? "v_fma_f64_e64_dpp" : "v_fma_f64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaF64Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaF64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -452,8 +508,6 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMA_F64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -461,7 +515,17 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f64_e64_dpp" + : "v_fma_f64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMA_F64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -471,7 +535,7 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) ? "v_lerp_u8_e64_dpp" : "v_lerp_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLerpU8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VLerpU8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -518,7 +582,15 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lerp_u8_e64_dpp" + : "v_lerp_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -528,7 +600,7 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) ? "v_alignbit_b32_e64_dpp" : "v_alignbit_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAlignbitB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAlignbitB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -579,7 +651,16 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbit_b32_e64_dpp" + : "v_alignbit_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -589,7 +670,7 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) ? "v_alignbyte_b32_e64_dpp" : "v_alignbyte_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAlignbyteB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAlignbyteB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -640,7 +721,16 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbyte_b32_e64_dpp" + : "v_alignbyte_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +740,7 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) ? "v_min3_i32_e64_dpp" : "v_min3_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMin3I32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMin3I32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -697,7 +787,15 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i32_e64_dpp" + : "v_min3_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +805,7 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) ? "v_min3_u32_e64_dpp" : "v_min3_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMin3U32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMin3U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -754,7 +852,15 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u32_e64_dpp" + : "v_min3_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -764,7 +870,7 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) ? "v_max3_i32_e64_dpp" : "v_max3_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMax3I32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMax3I32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -811,7 +917,15 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i32_e64_dpp" + : "v_max3_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -821,7 +935,7 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) ? "v_max3_u32_e64_dpp" : "v_max3_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMax3U32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMax3U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -868,7 +982,15 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u32_e64_dpp" + : "v_max3_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -878,7 +1000,7 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) ? "v_med3_i32_e64_dpp" : "v_med3_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMed3I32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMed3I32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -925,7 +1047,15 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i32_e64_dpp" + : "v_med3_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -935,7 +1065,7 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) ? "v_med3_u32_e64_dpp" : "v_med3_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMed3U32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMed3U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -982,7 +1112,15 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u32_e64_dpp" + : "v_med3_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -992,7 +1130,7 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) ? "v_sad_u8_e64_dpp" : "v_sad_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSadU8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VSadU8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1039,7 +1177,15 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u8_e64_dpp" + : "v_sad_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1049,7 +1195,7 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) ? "v_sad_hi_u8_e64_dpp" : "v_sad_hi_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSadHiU8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VSadHiU8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1096,7 +1242,15 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_hi_u8_e64_dpp" + : "v_sad_hi_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1106,7 +1260,7 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) ? "v_sad_u16_e64_dpp" : "v_sad_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSadU16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VSadU16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1153,7 +1307,15 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u16_e64_dpp" + : "v_sad_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1163,7 +1325,7 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) ? "v_sad_u32_e64_dpp" : "v_sad_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSadU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VSadU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1210,7 +1372,15 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u32_e64_dpp" + : "v_sad_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1220,7 +1390,7 @@ VMin3NumF32Vop3::VMin3NumF32Vop3(const MachineInst *inst) ? "v_min3_num_f32_e64_dpp" : "v_min3_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMin3NumF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMin3NumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1267,7 +1437,16 @@ VMin3NumF32Vop3::VMin3NumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3NumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3NumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_num_f32_e64_dpp" + : "v_min3_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1277,7 +1456,7 @@ VMax3NumF32Vop3::VMax3NumF32Vop3(const MachineInst *inst) ? "v_max3_num_f32_e64_dpp" : "v_max3_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMax3NumF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMax3NumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1324,7 +1503,16 @@ VMax3NumF32Vop3::VMax3NumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3NumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3NumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_num_f32_e64_dpp" + : "v_max3_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1334,7 +1522,7 @@ VMin3NumF16Vop3::VMin3NumF16Vop3(const MachineInst *inst) ? "v_min3_num_f16_e64_dpp" : "v_min3_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMin3NumF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMin3NumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1393,7 +1581,16 @@ VMin3NumF16Vop3::VMin3NumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3NumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3NumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_num_f16_e64_dpp" + : "v_min3_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1416,7 +1613,7 @@ VMax3NumF16Vop3::VMax3NumF16Vop3(const MachineInst *inst) ? "v_max3_num_f16_e64_dpp" : "v_max3_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMax3NumF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMax3NumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1475,7 +1672,16 @@ VMax3NumF16Vop3::VMax3NumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3NumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3NumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_num_f16_e64_dpp" + : "v_max3_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1498,7 +1704,7 @@ VMinimum3F32Vop3::VMinimum3F32Vop3(const MachineInst *inst) ? "v_minimum3_f32_e64_dpp" : "v_minimum3_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimum3F32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinimum3F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1545,7 +1751,16 @@ VMinimum3F32Vop3::VMinimum3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimum3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum3_f32_e64_dpp" + : "v_minimum3_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1555,7 +1770,7 @@ VMaximum3F32Vop3::VMaximum3F32Vop3(const MachineInst *inst) ? "v_maximum3_f32_e64_dpp" : "v_maximum3_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximum3F32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaximum3F32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1602,7 +1817,16 @@ VMaximum3F32Vop3::VMaximum3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximum3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum3_f32_e64_dpp" + : "v_maximum3_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1612,7 +1836,7 @@ VMinimum3F16Vop3::VMinimum3F16Vop3(const MachineInst *inst) ? "v_minimum3_f16_e64_dpp" : "v_minimum3_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimum3F16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinimum3F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1671,7 +1895,16 @@ VMinimum3F16Vop3::VMinimum3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimum3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum3_f16_e64_dpp" + : "v_minimum3_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1694,7 +1927,7 @@ VMaximum3F16Vop3::VMaximum3F16Vop3(const MachineInst *inst) ? "v_maximum3_f16_e64_dpp" : "v_maximum3_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximum3F16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaximum3F16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1753,7 +1986,16 @@ VMaximum3F16Vop3::VMaximum3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximum3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum3_f16_e64_dpp" + : "v_maximum3_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2018,7 @@ VMed3NumF32Vop3::VMed3NumF32Vop3(const MachineInst *inst) ? "v_med3_num_f32_e64_dpp" : "v_med3_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMed3NumF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMed3NumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1823,7 +2065,16 @@ VMed3NumF32Vop3::VMed3NumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3NumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3NumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_num_f32_e64_dpp" + : "v_med3_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1833,7 +2084,7 @@ VMed3NumF16Vop3::VMed3NumF16Vop3(const MachineInst *inst) ? "v_med3_num_f16_e64_dpp" : "v_med3_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMed3NumF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMed3NumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1892,7 +2143,16 @@ VMed3NumF16Vop3::VMed3NumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3NumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3NumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_num_f16_e64_dpp" + : "v_med3_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1915,7 +2175,7 @@ VMadU32Vop3::VMadU32Vop3(const MachineInst *inst) ? "v_mad_u32_e64_dpp" : "v_mad_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1947,8 +2207,6 @@ VMadU32Vop3::VMadU32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1956,7 +2214,17 @@ VMadU32Vop3::VMadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_e64_dpp" + : "v_mad_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAD_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -1966,7 +2234,7 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) ? "v_msad_u8_e64_dpp" : "v_msad_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMsadU8Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMsadU8Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2013,7 +2281,15 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_msad_u8_e64_dpp" + : "v_msad_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2023,7 +2299,7 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) ? "v_xor3_b32_e64_dpp" : "v_xor3_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VXor3B32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VXor3B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2070,7 +2346,15 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor3_b32_e64_dpp" + : "v_xor3_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2080,7 +2364,7 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) ? "v_mad_u16_e64_dpp" : "v_mad_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadU16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadU16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2139,7 +2423,15 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u16_e64_dpp" + : "v_mad_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2161,7 +2453,7 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) ? "v_xad_u32_e64_dpp" : "v_xad_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VXadU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VXadU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2208,7 +2500,15 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xad_u32_e64_dpp" + : "v_xad_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2218,7 +2518,7 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) ? "v_lshl_add_u32_e64_dpp" : "v_lshl_add_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshlAddU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VLshlAddU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2265,7 +2565,16 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_add_u32_e64_dpp" + : "v_lshl_add_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2275,7 +2584,7 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) ? "v_add_lshl_u32_e64_dpp" : "v_add_lshl_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddLshlU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAddLshlU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2322,7 +2631,16 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_lshl_u32_e64_dpp" + : "v_add_lshl_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2332,7 +2650,7 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) ? "v_fma_f16_e64_dpp" : "v_fma_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2391,7 +2709,15 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f16_e64_dpp" + : "v_fma_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2413,7 +2739,7 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) ? "v_min3_i16_e64_dpp" : "v_min3_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMin3I16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMin3I16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2472,7 +2798,15 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i16_e64_dpp" + : "v_min3_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2494,7 +2828,7 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) ? "v_min3_u16_e64_dpp" : "v_min3_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMin3U16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMin3U16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2553,7 +2887,15 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u16_e64_dpp" + : "v_min3_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2575,7 +2917,7 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) ? "v_max3_i16_e64_dpp" : "v_max3_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMax3I16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMax3I16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2634,7 +2976,15 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i16_e64_dpp" + : "v_max3_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2656,7 +3006,7 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) ? "v_max3_u16_e64_dpp" : "v_max3_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMax3U16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMax3U16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2715,7 +3065,15 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u16_e64_dpp" + : "v_max3_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2737,7 +3095,7 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) ? "v_med3_i16_e64_dpp" : "v_med3_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMed3I16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMed3I16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2796,7 +3154,15 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i16_e64_dpp" + : "v_med3_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2818,7 +3184,7 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) ? "v_med3_u16_e64_dpp" : "v_med3_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMed3U16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMed3U16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2877,7 +3243,15 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u16_e64_dpp" + : "v_med3_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2899,7 +3273,7 @@ VLshlAddU64Vop3::VLshlAddU64Vop3(const MachineInst *inst) ? "v_lshl_add_u64_e64_dpp" : "v_lshl_add_u64", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshlAddU64Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VLshlAddU64Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2933,8 +3307,6 @@ VLshlAddU64Vop3::VLshlAddU64Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHL_ADD_U64 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2942,7 +3314,18 @@ VLshlAddU64Vop3::VLshlAddU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_add_u64_e64_dpp" + : "v_lshl_add_u64", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHL_ADD_U64 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -2952,7 +3335,7 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) ? "v_mad_i16_e64_dpp" : "v_mad_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadI16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadI16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3011,7 +3394,15 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i16_e64_dpp" + : "v_mad_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3033,7 +3424,7 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) ? "v_add3_u32_e64_dpp" : "v_add3_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAdd3U32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAdd3U32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3080,7 +3471,15 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add3_u32_e64_dpp" + : "v_add3_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3090,7 +3489,7 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) ? "v_lshl_or_b32_e64_dpp" : "v_lshl_or_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VLshlOrB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VLshlOrB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3137,7 +3536,15 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_or_b32_e64_dpp" + : "v_lshl_or_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3147,7 +3554,7 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) ? "v_and_or_b32_e64_dpp" : "v_and_or_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAndOrB32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAndOrB32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3194,7 +3601,15 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_or_b32_e64_dpp" + : "v_and_or_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3204,7 +3619,7 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) ? "v_or3_b32_e64_dpp" : "v_or3_b32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VOr3B32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VOr3B32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3251,7 +3666,15 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or3_b32_e64_dpp" + : "v_or3_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3261,7 +3684,7 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) ? "v_mad_u32_u16_e64_dpp" : "v_mad_u32_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadU32U16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadU32U16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3316,7 +3739,15 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u16_e64_dpp" + : "v_mad_u32_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3326,7 +3757,7 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) ? "v_mad_i32_i16_e64_dpp" : "v_mad_i32_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadI32I16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadI32I16Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3381,7 +3812,15 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i16_e64_dpp" + : "v_mad_i32_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3391,7 +3830,7 @@ VAddMaxI32Vop3::VAddMaxI32Vop3(const MachineInst *inst) ? "v_add_max_i32_e64_dpp" : "v_add_max_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddMaxI32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAddMaxI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3438,7 +3877,15 @@ VAddMaxI32Vop3::VAddMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_max_i32_e64_dpp" + : "v_add_max_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3448,7 +3895,7 @@ VAddMaxU32Vop3::VAddMaxU32Vop3(const MachineInst *inst) ? "v_add_max_u32_e64_dpp" : "v_add_max_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddMaxU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAddMaxU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3495,7 +3942,15 @@ VAddMaxU32Vop3::VAddMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_max_u32_e64_dpp" + : "v_add_max_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3505,7 +3960,7 @@ VAddMinI32Vop3::VAddMinI32Vop3(const MachineInst *inst) ? "v_add_min_i32_e64_dpp" : "v_add_min_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddMinI32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAddMinI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3552,7 +4007,15 @@ VAddMinI32Vop3::VAddMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_min_i32_e64_dpp" + : "v_add_min_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3562,7 +4025,7 @@ VAddMinU32Vop3::VAddMinU32Vop3(const MachineInst *inst) ? "v_add_min_u32_e64_dpp" : "v_add_min_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAddMinU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAddMinU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3609,7 +4072,15 @@ VAddMinU32Vop3::VAddMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_min_u32_e64_dpp" + : "v_add_min_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3619,7 +4090,7 @@ VMaxminU32Vop3::VMaxminU32Vop3(const MachineInst *inst) ? "v_maxmin_u32_e64_dpp" : "v_maxmin_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxminU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaxminU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3666,7 +4137,15 @@ VMaxminU32Vop3::VMaxminU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_u32_e64_dpp" + : "v_maxmin_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3676,7 +4155,7 @@ VMinmaxU32Vop3::VMinmaxU32Vop3(const MachineInst *inst) ? "v_minmax_u32_e64_dpp" : "v_minmax_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinmaxU32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinmaxU32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3723,7 +4202,15 @@ VMinmaxU32Vop3::VMinmaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_u32_e64_dpp" + : "v_minmax_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3733,7 +4220,7 @@ VMaxminI32Vop3::VMaxminI32Vop3(const MachineInst *inst) ? "v_maxmin_i32_e64_dpp" : "v_maxmin_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxminI32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaxminI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3780,7 +4267,15 @@ VMaxminI32Vop3::VMaxminI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_i32_e64_dpp" + : "v_maxmin_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3790,7 +4285,7 @@ VMinmaxI32Vop3::VMinmaxI32Vop3(const MachineInst *inst) ? "v_minmax_i32_e64_dpp" : "v_minmax_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinmaxI32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinmaxI32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3837,7 +4332,15 @@ VMinmaxI32Vop3::VMinmaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_i32_e64_dpp" + : "v_minmax_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3847,7 +4350,7 @@ VMinmaxNumF32Vop3::VMinmaxNumF32Vop3(const MachineInst *inst) ? "v_minmax_num_f32_e64_dpp" : "v_minmax_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinmaxNumF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinmaxNumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3894,7 +4397,16 @@ VMinmaxNumF32Vop3::VMinmaxNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_num_f32_e64_dpp" + : "v_minmax_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3904,7 +4416,7 @@ VMaxminNumF32Vop3::VMaxminNumF32Vop3(const MachineInst *inst) ? "v_maxmin_num_f32_e64_dpp" : "v_maxmin_num_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxminNumF32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaxminNumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -3951,7 +4463,16 @@ VMaxminNumF32Vop3::VMaxminNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_num_f32_e64_dpp" + : "v_maxmin_num_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3961,7 +4482,7 @@ VMinmaxNumF16Vop3::VMinmaxNumF16Vop3(const MachineInst *inst) ? "v_minmax_num_f16_e64_dpp" : "v_minmax_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinmaxNumF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinmaxNumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4020,7 +4541,16 @@ VMinmaxNumF16Vop3::VMinmaxNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_num_f16_e64_dpp" + : "v_minmax_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4043,7 +4573,7 @@ VMaxminNumF16Vop3::VMaxminNumF16Vop3(const MachineInst *inst) ? "v_maxmin_num_f16_e64_dpp" : "v_maxmin_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaxminNumF16Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaxminNumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4102,7 +4632,16 @@ VMaxminNumF16Vop3::VMaxminNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_num_f16_e64_dpp" + : "v_maxmin_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4125,8 +4664,7 @@ VMinimummaximumF32Vop3::VMinimummaximumF32Vop3(const MachineInst *inst) ? "v_minimummaximum_f32_e64_dpp" : "v_minimummaximum_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimummaximumF32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinimummaximumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4173,7 +4711,16 @@ VMinimummaximumF32Vop3::VMinimummaximumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimummaximumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimummaximumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimummaximum_f32_e64_dpp" + : "v_minimummaximum_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4183,8 +4730,7 @@ VMaximumminimumF32Vop3::VMaximumminimumF32Vop3(const MachineInst *inst) ? "v_maximumminimum_f32_e64_dpp" : "v_maximumminimum_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximumminimumF32Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaximumminimumF32Vop3)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4231,7 +4777,16 @@ VMaximumminimumF32Vop3::VMaximumminimumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumminimumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumminimumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximumminimum_f32_e64_dpp" + : "v_maximumminimum_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4241,8 +4796,7 @@ VMinimummaximumF16Vop3::VMinimummaximumF16Vop3(const MachineInst *inst) ? "v_minimummaximum_f16_e64_dpp" : "v_minimummaximum_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMinimummaximumF16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMinimummaximumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4301,7 +4855,16 @@ VMinimummaximumF16Vop3::VMinimummaximumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimummaximumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimummaximumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimummaximum_f16_e64_dpp" + : "v_minimummaximum_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4324,8 +4887,7 @@ VMaximumminimumF16Vop3::VMaximumminimumF16Vop3(const MachineInst *inst) ? "v_maximumminimum_f16_e64_dpp" : "v_maximumminimum_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMaximumminimumF16Vop3), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMaximumminimumF16Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(16, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4384,7 +4946,16 @@ VMaximumminimumF16Vop3::VMaximumminimumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumminimumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumminimumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximumminimum_f16_e64_dpp" + : "v_maximumminimum_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4407,7 +4978,7 @@ VAshrPkI8I32Vop3::VAshrPkI8I32Vop3(const MachineInst *inst) ? "v_ashr_pk_i8_i32_e64_dpp" : "v_ashr_pk_i8_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAshrPkI8I32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAshrPkI8I32Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4454,7 +5025,16 @@ VAshrPkI8I32Vop3::VAshrPkI8I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrPkI8I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrPkI8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashr_pk_i8_i32_e64_dpp" + : "v_ashr_pk_i8_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4477,7 +5057,7 @@ VAshrPkU8I32Vop3::VAshrPkU8I32Vop3(const MachineInst *inst) ? "v_ashr_pk_u8_i32_e64_dpp" : "v_ashr_pk_u8_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VAshrPkU8I32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VAshrPkU8I32Vop3)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4524,7 +5104,16 @@ VAshrPkU8I32Vop3::VAshrPkU8I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrPkU8I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrPkU8I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashr_pk_u8_i32_e64_dpp" + : "v_ashr_pk_u8_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4547,7 +5136,7 @@ VMadNcU64U32Vop3::VMadNcU64U32Vop3(const MachineInst *inst) ? "v_mad_nc_u64_u32_e64_dpp" : "v_mad_nc_u64_u32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadNcU64U32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadNcU64U32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4580,8 +5169,6 @@ VMadNcU64U32Vop3::VMadNcU64U32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_NC_U64_U32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -4589,7 +5176,18 @@ VMadNcU64U32Vop3::VMadNcU64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadNcU64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadNcU64U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_nc_u64_u32_e64_dpp" + : "v_mad_nc_u64_u32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAD_NC_U64_U32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail @@ -4599,7 +5197,7 @@ VMadNcI64I32Vop3::VMadNcI64I32Vop3(const MachineInst *inst) ? "v_mad_nc_i64_i32_e64_dpp" : "v_mad_nc_i64_i32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VMadNcI64I32Vop3), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VMadNcI64I32Vop3)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -4632,8 +5230,6 @@ VMadNcI64I32Vop3::VMadNcI64I32Vop3(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_NC_I64_I32 does not support DPP8", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -4641,7 +5237,18 @@ VMadNcI64I32Vop3::VMadNcI64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadNcI64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadNcI64I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_nc_i64_i32_e64_dpp" + : "v_mad_nc_i64_i32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAD_NC_I64_I32 does not support DPP8"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp index 62e86c3209da..578abd3f40db 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -106,7 +105,7 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) ? "v_pk_mad_i16_e64_dpp" : "v_pk_mad_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMadI16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMadI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -129,9 +128,6 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -139,7 +135,19 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_i16_e64_dpp" + : "v_pk_mad_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -149,8 +157,7 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) ? "v_pk_mul_lo_u16_e64_dpp" : "v_pk_mul_lo_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMulLoU16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMulLoU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -167,16 +174,27 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_LO_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_lo_u16_e64_dpp" + : "v_pk_mul_lo_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_LO_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -186,7 +204,7 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) ? "v_pk_add_i16_e64_dpp" : "v_pk_add_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddI16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkAddI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -203,16 +221,26 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_i16_e64_dpp" + : "v_pk_add_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -222,7 +250,7 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) ? "v_pk_sub_i16_e64_dpp" : "v_pk_sub_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkSubI16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkSubI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -239,16 +267,26 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_i16_e64_dpp" + : "v_pk_sub_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -258,8 +296,7 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) ? "v_pk_lshlrev_b16_e64_dpp" : "v_pk_lshlrev_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkLshlrevB16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkLshlrevB16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -276,16 +313,27 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHLREV_B16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshlrev_b16_e64_dpp" + : "v_pk_lshlrev_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHLREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -295,8 +343,7 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) ? "v_pk_lshrrev_b16_e64_dpp" : "v_pk_lshrrev_b16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkLshrrevB16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkLshrrevB16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -313,16 +360,27 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHRREV_B16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshrrev_b16_e64_dpp" + : "v_pk_lshrrev_b16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHRREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -332,8 +390,7 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) ? "v_pk_ashrrev_i16_e64_dpp" : "v_pk_ashrrev_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAshrrevI16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkAshrrevI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -350,16 +407,27 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ASHRREV_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_ashrrev_i16_e64_dpp" + : "v_pk_ashrrev_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ASHRREV_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -369,7 +437,7 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) ? "v_pk_max_i16_e64_dpp" : "v_pk_max_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMaxI16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkMaxI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -386,16 +454,26 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_i16_e64_dpp" + : "v_pk_max_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -405,7 +483,7 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) ? "v_pk_min_i16_e64_dpp" : "v_pk_min_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMinI16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkMinI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -422,16 +500,26 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_i16_e64_dpp" + : "v_pk_min_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -441,7 +529,7 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) ? "v_pk_mad_u16_e64_dpp" : "v_pk_mad_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMadU16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMadU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -464,9 +552,6 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -474,7 +559,19 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_u16_e64_dpp" + : "v_pk_mad_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -484,7 +581,7 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) ? "v_pk_add_u16_e64_dpp" : "v_pk_add_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddU16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkAddU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -501,16 +598,26 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_u16_e64_dpp" + : "v_pk_add_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -520,7 +627,7 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) ? "v_pk_sub_u16_e64_dpp" : "v_pk_sub_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkSubU16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkSubU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -537,16 +644,26 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_u16_e64_dpp" + : "v_pk_sub_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -556,7 +673,7 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) ? "v_pk_max_u16_e64_dpp" : "v_pk_max_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMaxU16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkMaxU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -573,16 +690,26 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_u16_e64_dpp" + : "v_pk_max_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -592,7 +719,7 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) ? "v_pk_min_u16_e64_dpp" : "v_pk_min_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMinU16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkMinU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -609,16 +736,26 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_u16_e64_dpp" + : "v_pk_min_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -628,7 +765,7 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) ? "v_pk_fma_f16_e64_dpp" : "v_pk_fma_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkFmaF16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkFmaF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -651,9 +788,6 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMA_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -661,7 +795,19 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fma_f16_e64_dpp" + : "v_pk_fma_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_FMA_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -671,7 +817,7 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) ? "v_pk_add_f16_e64_dpp" : "v_pk_add_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddF16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkAddF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -688,16 +834,26 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_f16_e64_dpp" + : "v_pk_add_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -707,7 +863,7 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) ? "v_pk_mul_f16_e64_dpp" : "v_pk_mul_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMulF16Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkMulF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -724,16 +880,26 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_f16_e64_dpp" + : "v_pk_mul_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -743,7 +909,7 @@ VPkFmaBf16Vop3p::VPkFmaBf16Vop3p(const MachineInst *inst) ? "v_pk_fma_bf16_e64_dpp" : "v_pk_fma_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkFmaBf16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkFmaBf16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -766,9 +932,6 @@ VPkFmaBf16Vop3p::VPkFmaBf16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMA_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -776,7 +939,20 @@ VPkFmaBf16Vop3p::VPkFmaBf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fma_bf16_e64_dpp" + : "v_pk_fma_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_FMA_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -786,7 +962,7 @@ VPkAddMaxI16Vop3p::VPkAddMaxI16Vop3p(const MachineInst *inst) ? "v_pk_add_max_i16_e64_dpp" : "v_pk_add_max_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddMaxI16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkAddMaxI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -809,9 +985,6 @@ VPkAddMaxI16Vop3p::VPkAddMaxI16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_MAX_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -819,7 +992,20 @@ VPkAddMaxI16Vop3p::VPkAddMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddMaxI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_max_i16_e64_dpp" + : "v_pk_add_max_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_MAX_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -829,7 +1015,7 @@ VPkAddMaxU16Vop3p::VPkAddMaxU16Vop3p(const MachineInst *inst) ? "v_pk_add_max_u16_e64_dpp" : "v_pk_add_max_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddMaxU16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkAddMaxU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -852,9 +1038,6 @@ VPkAddMaxU16Vop3p::VPkAddMaxU16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_MAX_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -862,7 +1045,20 @@ VPkAddMaxU16Vop3p::VPkAddMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddMaxU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_max_u16_e64_dpp" + : "v_pk_add_max_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_MAX_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -872,7 +1068,7 @@ VDot4I32Iu8Vop3p::VDot4I32Iu8Vop3p(const MachineInst *inst) ? "v_dot4_i32_iu8_e64_dpp" : "v_dot4_i32_iu8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDot4I32Iu8Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDot4I32Iu8Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -895,9 +1091,6 @@ VDot4I32Iu8Vop3p::VDot4I32Iu8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_I32_IU8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -905,7 +1098,20 @@ VDot4I32Iu8Vop3p::VDot4I32Iu8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_i32_iu8_e64_dpp" + : "v_dot4_i32_iu8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_I32_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -915,7 +1121,7 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) ? "v_dot4_u32_u8_e64_dpp" : "v_dot4_u32_u8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDot4U32U8Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDot4U32U8Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -938,9 +1144,6 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_U32_U8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -948,7 +1151,20 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_u32_u8_e64_dpp" + : "v_dot4_u32_u8", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1174,7 @@ VDot8I32Iu4Vop3p::VDot8I32Iu4Vop3p(const MachineInst *inst) ? "v_dot8_i32_iu4_e64_dpp" : "v_dot8_i32_iu4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDot8I32Iu4Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDot8I32Iu4Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -981,9 +1197,6 @@ VDot8I32Iu4Vop3p::VDot8I32Iu4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_I32_IU4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -991,7 +1204,20 @@ VDot8I32Iu4Vop3p::VDot8I32Iu4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_i32_iu4_e64_dpp" + : "v_dot8_i32_iu4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_I32_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1001,7 +1227,7 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) ? "v_dot8_u32_u4_e64_dpp" : "v_dot8_u32_u4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VDot8U32U4Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VDot8U32U4Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1024,9 +1250,6 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_U32_U4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1034,7 +1257,20 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_u32_u4_e64_dpp" + : "v_dot8_u32_u4", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_U32_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1044,8 +1280,7 @@ VPkMinNumF16Vop3p::VPkMinNumF16Vop3p(const MachineInst *inst) ? "v_pk_min_num_f16_e64_dpp" : "v_pk_min_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMinNumF16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMinNumF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1062,16 +1297,27 @@ VPkMinNumF16Vop3p::VPkMinNumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_NUM_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMinNumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_num_f16_e64_dpp" + : "v_pk_min_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_NUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1081,8 +1327,7 @@ VPkMaxNumF16Vop3p::VPkMaxNumF16Vop3p(const MachineInst *inst) ? "v_pk_max_num_f16_e64_dpp" : "v_pk_max_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMaxNumF16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMaxNumF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1099,16 +1344,27 @@ VPkMaxNumF16Vop3p::VPkMaxNumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_NUM_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMaxNumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_num_f16_e64_dpp" + : "v_pk_max_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_NUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1118,8 +1374,7 @@ VPkMinimumF16Vop3p::VPkMinimumF16Vop3p(const MachineInst *inst) ? "v_pk_minimum_f16_e64_dpp" : "v_pk_minimum_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMinimumF16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMinimumF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1136,16 +1391,27 @@ VPkMinimumF16Vop3p::VPkMinimumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MINIMUM_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMinimumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinimumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_minimum_f16_e64_dpp" + : "v_pk_minimum_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MINIMUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1155,8 +1421,7 @@ VPkMaximumF16Vop3p::VPkMaximumF16Vop3p(const MachineInst *inst) ? "v_pk_maximum_f16_e64_dpp" : "v_pk_maximum_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMaximumF16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMaximumF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1173,16 +1438,27 @@ VPkMaximumF16Vop3p::VPkMaximumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAXIMUM_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMaximumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaximumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_maximum_f16_e64_dpp" + : "v_pk_maximum_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAXIMUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1192,7 +1468,7 @@ VPkFmaF32Vop3p::VPkFmaF32Vop3p(const MachineInst *inst) ? "v_pk_fma_f32_e64_dpp" : "v_pk_fma_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkFmaF32Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkFmaF32Vop3p)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1218,9 +1494,6 @@ VPkFmaF32Vop3p::VPkFmaF32Vop3p(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::Replicate32); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMA_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1228,7 +1501,19 @@ VPkFmaF32Vop3p::VPkFmaF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fma_f32_e64_dpp" + : "v_pk_fma_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_FMA_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1523,7 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) ? "v_fma_mix_f32_e64_dpp" : "v_fma_mix_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaMixF32Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaMixF32Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1285,7 +1570,16 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mix_f32_e64_dpp" + : "v_fma_mix_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1295,7 +1589,7 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) ? "v_fma_mixlo_f16_e64_dpp" : "v_fma_mixlo_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaMixloF16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaMixloF16Vop3p)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1343,7 +1637,16 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixlo_f16_e64_dpp" + : "v_fma_mixlo_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1366,7 +1669,7 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) ? "v_fma_mixhi_f16_e64_dpp" : "v_fma_mixhi_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaMixhiF16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaMixhiF16Vop3p)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1414,7 +1717,16 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixhi_f16_e64_dpp" + : "v_fma_mixhi_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1437,8 +1749,7 @@ VPkAddBf16Vop3p::VPkAddBf16Vop3p(const MachineInst *inst) ? "v_pk_add_bf16_e64_dpp" : "v_pk_add_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddBf16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkAddBf16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1455,16 +1766,27 @@ VPkAddBf16Vop3p::VPkAddBf16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkAddBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_bf16_e64_dpp" + : "v_pk_add_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1474,7 +1796,7 @@ VPkMulF32Vop3p::VPkMulF32Vop3p(const MachineInst *inst) ? "v_pk_mul_f32_e64_dpp" : "v_pk_mul_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMulF32Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkMulF32Vop3p)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1493,16 +1815,26 @@ VPkMulF32Vop3p::VPkMulF32Vop3p(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::Replicate32); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMulF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_f32_e64_dpp" + : "v_pk_mul_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1844,7 @@ VPkAddF32Vop3p::VPkAddF32Vop3p(const MachineInst *inst) ? "v_pk_add_f32_e64_dpp" : "v_pk_add_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddF32Vop3p), LiteralSupport::Literal32, 2), + selected_exec_fn(InstructionExecutionId::VPkAddF32Vop3p)), vdst(64, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1531,16 +1863,26 @@ VPkAddF32Vop3p::VPkAddF32Vop3p(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::Replicate32); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkAddF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_f32_e64_dpp" + : "v_pk_add_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1550,8 +1892,7 @@ VPkMulBf16Vop3p::VPkMulBf16Vop3p(const MachineInst *inst) ? "v_pk_mul_bf16_e64_dpp" : "v_pk_mul_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMulBf16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMulBf16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1568,16 +1909,27 @@ VPkMulBf16Vop3p::VPkMulBf16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMulBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_bf16_e64_dpp" + : "v_pk_mul_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1587,8 +1939,7 @@ VPkMinNumBf16Vop3p::VPkMinNumBf16Vop3p(const MachineInst *inst) ? "v_pk_min_num_bf16_e64_dpp" : "v_pk_min_num_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMinNumBf16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMinNumBf16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1605,16 +1956,27 @@ VPkMinNumBf16Vop3p::VPkMinNumBf16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_NUM_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMinNumBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinNumBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_num_bf16_e64_dpp" + : "v_pk_min_num_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_NUM_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1624,8 +1986,7 @@ VPkMaxNumBf16Vop3p::VPkMaxNumBf16Vop3p(const MachineInst *inst) ? "v_pk_max_num_bf16_e64_dpp" : "v_pk_max_num_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMaxNumBf16Vop3p), LiteralSupport::Literal32, - 2), + selected_exec_fn(InstructionExecutionId::VPkMaxNumBf16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { @@ -1642,16 +2003,27 @@ VPkMaxNumBf16Vop3p::VPkMaxNumBf16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_NUM_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVPkMaxNumBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxNumBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_num_bf16_e64_dpp" + : "v_pk_max_num_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, + 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_NUM_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1661,7 +2033,7 @@ VPkAddMinI16Vop3p::VPkAddMinI16Vop3p(const MachineInst *inst) ? "v_pk_add_min_i16_e64_dpp" : "v_pk_add_min_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddMinI16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkAddMinI16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1684,9 +2056,6 @@ VPkAddMinI16Vop3p::VPkAddMinI16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_MIN_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1694,7 +2063,20 @@ VPkAddMinI16Vop3p::VPkAddMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddMinI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_min_i16_e64_dpp" + : "v_pk_add_min_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_MIN_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1704,7 +2086,7 @@ VPkAddMinU16Vop3p::VPkAddMinU16Vop3p(const MachineInst *inst) ? "v_pk_add_min_u16_e64_dpp" : "v_pk_add_min_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkAddMinU16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkAddMinU16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1727,9 +2109,6 @@ VPkAddMinU16Vop3p::VPkAddMinU16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_MIN_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1737,7 +2116,20 @@ VPkAddMinU16Vop3p::VPkAddMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddMinU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_min_u16_e64_dpp" + : "v_pk_add_min_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_MIN_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1747,7 +2139,7 @@ VPkMax3I16Vop3p::VPkMax3I16Vop3p(const MachineInst *inst) ? "v_pk_max3_i16_e64_dpp" : "v_pk_max3_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMax3I16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMax3I16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1770,9 +2162,6 @@ VPkMax3I16Vop3p::VPkMax3I16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX3_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1780,7 +2169,20 @@ VPkMax3I16Vop3p::VPkMax3I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMax3I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMax3I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max3_i16_e64_dpp" + : "v_pk_max3_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX3_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1790,7 +2192,7 @@ VPkMax3U16Vop3p::VPkMax3U16Vop3p(const MachineInst *inst) ? "v_pk_max3_u16_e64_dpp" : "v_pk_max3_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMax3U16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMax3U16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1813,9 +2215,6 @@ VPkMax3U16Vop3p::VPkMax3U16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX3_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1823,7 +2222,20 @@ VPkMax3U16Vop3p::VPkMax3U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMax3U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMax3U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max3_u16_e64_dpp" + : "v_pk_max3_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX3_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1833,7 +2245,7 @@ VPkMin3I16Vop3p::VPkMin3I16Vop3p(const MachineInst *inst) ? "v_pk_min3_i16_e64_dpp" : "v_pk_min3_i16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMin3I16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMin3I16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1856,9 +2268,6 @@ VPkMin3I16Vop3p::VPkMin3I16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN3_I16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1866,7 +2275,20 @@ VPkMin3I16Vop3p::VPkMin3I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMin3I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMin3I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min3_i16_e64_dpp" + : "v_pk_min3_i16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN3_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1876,7 +2298,7 @@ VPkMin3U16Vop3p::VPkMin3U16Vop3p(const MachineInst *inst) ? "v_pk_min3_u16_e64_dpp" : "v_pk_min3_u16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMin3U16Vop3p), LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMin3U16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1899,9 +2321,6 @@ VPkMin3U16Vop3p::VPkMin3U16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN3_U16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1909,7 +2328,20 @@ VPkMin3U16Vop3p::VPkMin3U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMin3U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMin3U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min3_u16_e64_dpp" + : "v_pk_min3_u16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN3_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1919,8 +2351,7 @@ VWmmaF3216x16x128F8f6f4Vop3p::VWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *in ? "v_wmma_f32_16x16x128_f8f6f4_e64_dpp" : "v_wmma_f32_16x16x128_f8f6f4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128F8f6f4Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128F8f6f4Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(gfx1250_matrix_fmt_operand_size_bits(reinterpret_cast(inst)->opsel, 16, 128), @@ -1938,9 +2369,6 @@ VWmmaF3216x16x128F8f6f4Vop3p::VWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X128_F8F6F4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1948,7 +2376,20 @@ VWmmaF3216x16x128F8f6f4Vop3p::VWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x128_f8f6f4_e64_dpp" + : "v_wmma_f32_16x16x128_f8f6f4", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_F8F6F4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1965,8 +2406,7 @@ VPkMinimum3F16Vop3p::VPkMinimum3F16Vop3p(const MachineInst *inst) ? "v_pk_minimum3_f16_e64_dpp" : "v_pk_minimum3_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMinimum3F16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMinimum3F16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -1989,9 +2429,6 @@ VPkMinimum3F16Vop3p::VPkMinimum3F16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MINIMUM3_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -1999,7 +2436,20 @@ VPkMinimum3F16Vop3p::VPkMinimum3F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinimum3F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinimum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_minimum3_f16_e64_dpp" + : "v_pk_minimum3_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MINIMUM3_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2009,8 +2459,7 @@ VPkMaximum3F16Vop3p::VPkMaximum3F16Vop3p(const MachineInst *inst) ? "v_pk_maximum3_f16_e64_dpp" : "v_pk_maximum3_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMaximum3F16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMaximum3F16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2033,9 +2482,6 @@ VPkMaximum3F16Vop3p::VPkMaximum3F16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAXIMUM3_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2043,7 +2489,20 @@ VPkMaximum3F16Vop3p::VPkMaximum3F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaximum3F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaximum3F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_maximum3_f16_e64_dpp" + : "v_pk_maximum3_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAXIMUM3_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2053,8 +2512,7 @@ VPkMin3NumF16Vop3p::VPkMin3NumF16Vop3p(const MachineInst *inst) ? "v_pk_min3_num_f16_e64_dpp" : "v_pk_min3_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMin3NumF16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMin3NumF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2077,9 +2535,6 @@ VPkMin3NumF16Vop3p::VPkMin3NumF16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN3_NUM_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2087,7 +2542,20 @@ VPkMin3NumF16Vop3p::VPkMin3NumF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMin3NumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMin3NumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min3_num_f16_e64_dpp" + : "v_pk_min3_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN3_NUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2097,8 +2565,7 @@ VPkMax3NumF16Vop3p::VPkMax3NumF16Vop3p(const MachineInst *inst) ? "v_pk_max3_num_f16_e64_dpp" : "v_pk_max3_num_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VPkMax3NumF16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VPkMax3NumF16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2121,9 +2588,6 @@ VPkMax3NumF16Vop3p::VPkMax3NumF16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX3_NUM_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2131,7 +2595,20 @@ VPkMax3NumF16Vop3p::VPkMax3NumF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMax3NumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMax3NumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max3_num_f16_e64_dpp" + : "v_pk_max3_num_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX3_NUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2141,8 +2618,7 @@ VFmaMixF32Bf16Vop3p::VFmaMixF32Bf16Vop3p(const MachineInst *inst) ? "v_fma_mix_f32_bf16_e64_dpp" : "v_fma_mix_f32_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaMixF32Bf16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaMixF32Bf16Vop3p)), vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2189,7 +2665,16 @@ VFmaMixF32Bf16Vop3p::VFmaMixF32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mix_f32_bf16_e64_dpp" + : "v_fma_mix_f32_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2199,8 +2684,7 @@ VFmaMixloBf16Vop3p::VFmaMixloBf16Vop3p(const MachineInst *inst) ? "v_fma_mixlo_bf16_e64_dpp" : "v_fma_mixlo_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaMixloBf16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaMixloBf16Vop3p)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2248,7 +2732,16 @@ VFmaMixloBf16Vop3p::VFmaMixloBf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixlo_bf16_e64_dpp" + : "v_fma_mixlo_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2271,8 +2764,7 @@ VFmaMixhiBf16Vop3p::VFmaMixhiBf16Vop3p(const MachineInst *inst) ? "v_fma_mixhi_bf16_e64_dpp" : "v_fma_mixhi_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VFmaMixhiBf16Vop3p), - LiteralSupport::Literal32), + selected_exec_fn(InstructionExecutionId::VFmaMixhiBf16Vop3p)), vdst(16, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1), @@ -2320,7 +2812,16 @@ VFmaMixhiBf16Vop3p::VFmaMixhiBf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiBf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiBf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixhi_bf16_e64_dpp" + : "v_fma_mixhi_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2343,8 +2844,7 @@ VWmmaF3216x16x4F32Vop3p::VWmmaF3216x16x4F32Vop3p(const MachineInst *inst) ? "v_wmma_f32_16x16x4_f32_e64_dpp" : "v_wmma_f32_16x16x4_f32", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x4F32Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x4F32Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(64, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2356,9 +2856,6 @@ VWmmaF3216x16x4F32Vop3p::VWmmaF3216x16x4F32Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X4_F32 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2366,7 +2863,20 @@ VWmmaF3216x16x4F32Vop3p::VWmmaF3216x16x4F32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x4F32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x4F32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x4_f32_e64_dpp" + : "v_wmma_f32_16x16x4_f32", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X4_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2376,8 +2886,7 @@ VWmmaF3216x16x32F16Vop3p::VWmmaF3216x16x32F16Vop3p(const MachineInst *inst) ? "v_wmma_f32_16x16x32_f16_e64_dpp" : "v_wmma_f32_16x16x32_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x32F16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x32F16Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2389,9 +2898,6 @@ VWmmaF3216x16x32F16Vop3p::VWmmaF3216x16x32F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X32_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2399,7 +2905,20 @@ VWmmaF3216x16x32F16Vop3p::VWmmaF3216x16x32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x32_f16_e64_dpp" + : "v_wmma_f32_16x16x32_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X32_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2409,8 +2928,7 @@ VWmmaF1616x16x32F16Vop3p::VWmmaF1616x16x32F16Vop3p(const MachineInst *inst) ? "v_wmma_f16_16x16x32_f16_e64_dpp" : "v_wmma_f16_16x16x32_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x32F16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x32F16Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2422,9 +2940,6 @@ VWmmaF1616x16x32F16Vop3p::VWmmaF1616x16x32F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X32_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2432,7 +2947,20 @@ VWmmaF1616x16x32F16Vop3p::VWmmaF1616x16x32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x32_f16_e64_dpp" + : "v_wmma_f16_16x16x32_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X32_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2442,8 +2970,7 @@ VWmmaF3216x16x32Bf16Vop3p::VWmmaF3216x16x32Bf16Vop3p(const MachineInst *inst) ? "v_wmma_f32_16x16x32_bf16_e64_dpp" : "v_wmma_f32_16x16x32_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x32Bf16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x32Bf16Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2455,9 +2982,6 @@ VWmmaF3216x16x32Bf16Vop3p::VWmmaF3216x16x32Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X32_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2465,7 +2989,20 @@ VWmmaF3216x16x32Bf16Vop3p::VWmmaF3216x16x32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x32_bf16_e64_dpp" + : "v_wmma_f32_16x16x32_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X32_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2475,8 +3012,7 @@ VWmmaBf1616x16x32Bf16Vop3p::VWmmaBf1616x16x32Bf16Vop3p(const MachineInst *inst) ? "v_wmma_bf16_16x16x32_bf16_e64_dpp" : "v_wmma_bf16_16x16x32_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaBf1616x16x32Bf16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaBf1616x16x32Bf16Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2488,9 +3024,6 @@ VWmmaBf1616x16x32Bf16Vop3p::VWmmaBf1616x16x32Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_BF16_16X16X32_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2498,7 +3031,20 @@ VWmmaBf1616x16x32Bf16Vop3p::VWmmaBf1616x16x32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaBf1616x16x32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaBf1616x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_bf16_16x16x32_bf16_e64_dpp" + : "v_wmma_bf16_16x16x32_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_BF16_16X16X32_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2508,8 +3054,7 @@ VWmmaBf16f3216x16x32Bf16Vop3p::VWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst * ? "v_wmma_bf16f32_16x16x32_bf16_e64_dpp" : "v_wmma_bf16f32_16x16x32_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaBf16f3216x16x32Bf16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaBf16f3216x16x32Bf16Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2521,9 +3066,6 @@ VWmmaBf16f3216x16x32Bf16Vop3p::VWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst * src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_BF16F32_16X16X32_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2531,7 +3073,20 @@ VWmmaBf16f3216x16x32Bf16Vop3p::VWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst * } namespace detail { -std::unique_ptr decodeVWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaBf16f3216x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_bf16f32_16x16x32_bf16_e64_dpp" + : "v_wmma_bf16f32_16x16x32_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_BF16F32_16X16X32_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2541,8 +3096,7 @@ VSwmmacF3216x16x64F16Vop3p::VSwmmacF3216x16x64F16Vop3p(const MachineInst *inst) ? "v_swmmac_f32_16x16x64_f16_e64_dpp" : "v_swmmac_f32_16x16x64_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x64F16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x64F16Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2553,9 +3107,6 @@ VSwmmacF3216x16x64F16Vop3p::VSwmmacF3216x16x64F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X64_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2563,7 +3114,20 @@ VSwmmacF3216x16x64F16Vop3p::VSwmmacF3216x16x64F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x64F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x64F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x64_f16_e64_dpp" + : "v_swmmac_f32_16x16x64_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X64_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2582,8 +3146,7 @@ VSwmmacF3216x16x64Bf16Vop3p::VSwmmacF3216x16x64Bf16Vop3p(const MachineInst *inst ? "v_swmmac_f32_16x16x64_bf16_e64_dpp" : "v_swmmac_f32_16x16x64_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x64Bf16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x64Bf16Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2594,9 +3157,6 @@ VSwmmacF3216x16x64Bf16Vop3p::VSwmmacF3216x16x64Bf16Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X64_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2604,7 +3164,20 @@ VSwmmacF3216x16x64Bf16Vop3p::VSwmmacF3216x16x64Bf16Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x64Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x64Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x64_bf16_e64_dpp" + : "v_swmmac_f32_16x16x64_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X64_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2623,8 +3196,7 @@ VSwmmacF1616x16x64F16Vop3p::VSwmmacF1616x16x64F16Vop3p(const MachineInst *inst) ? "v_swmmac_f16_16x16x64_f16_e64_dpp" : "v_swmmac_f16_16x16x64_f16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x64F16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x64F16Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2635,9 +3207,6 @@ VSwmmacF1616x16x64F16Vop3p::VSwmmacF1616x16x64F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F16_16X16X64_F16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2645,7 +3214,20 @@ VSwmmacF1616x16x64F16Vop3p::VSwmmacF1616x16x64F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSwmmacF1616x16x64F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF1616x16x64F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f16_16x16x64_f16_e64_dpp" + : "v_swmmac_f16_16x16x64_f16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F16_16X16X64_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2664,8 +3246,7 @@ VSwmmacBf1616x16x64Bf16Vop3p::VSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *in ? "v_swmmac_bf16_16x16x64_bf16_e64_dpp" : "v_swmmac_bf16_16x16x64_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacBf1616x16x64Bf16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacBf1616x16x64Bf16Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2676,9 +3257,6 @@ VSwmmacBf1616x16x64Bf16Vop3p::VSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_BF16_16X16X64_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2686,7 +3264,20 @@ VSwmmacBf1616x16x64Bf16Vop3p::VSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacBf1616x16x64Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_bf16_16x16x64_bf16_e64_dpp" + : "v_swmmac_bf16_16x16x64_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_BF16_16X16X64_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2705,8 +3296,7 @@ VSwmmacBf16f3216x16x64Bf16Vop3p::VSwmmacBf16f3216x16x64Bf16Vop3p(const MachineIn ? "v_swmmac_bf16f32_16x16x64_bf16_e64_dpp" : "v_swmmac_bf16f32_16x16x64_bf16", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacBf16f3216x16x64Bf16Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacBf16f3216x16x64Bf16Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2717,9 +3307,6 @@ VSwmmacBf16f3216x16x64Bf16Vop3p::VSwmmacBf16f3216x16x64Bf16Vop3p(const MachineIn src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_BF16F32_16X16X64_BF16 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2727,7 +3314,20 @@ VSwmmacBf16f3216x16x64Bf16Vop3p::VSwmmacBf16f3216x16x64Bf16Vop3p(const MachineIn } namespace detail { -std::unique_ptr decodeVSwmmacBf16f3216x16x64Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacBf16f3216x16x64Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_bf16f32_16x16x64_bf16_e64_dpp" + : "v_swmmac_bf16f32_16x16x64_bf16", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_BF16F32_16X16X64_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2746,8 +3346,7 @@ VWmmaF3216x16x64Fp8Fp8Vop3p::VWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *inst ? "v_wmma_f32_16x16x64_fp8_fp8_e64_dpp" : "v_wmma_f32_16x16x64_fp8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Fp8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Fp8Fp8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2759,9 +3358,6 @@ VWmmaF3216x16x64Fp8Fp8Vop3p::VWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X64_FP8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2769,7 +3365,20 @@ VWmmaF3216x16x64Fp8Fp8Vop3p::VWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x64Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x64_fp8_fp8_e64_dpp" + : "v_wmma_f32_16x16x64_fp8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X64_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2779,8 +3388,7 @@ VWmmaF3216x16x64Fp8Bf8Vop3p::VWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *inst ? "v_wmma_f32_16x16x64_fp8_bf8_e64_dpp" : "v_wmma_f32_16x16x64_fp8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Fp8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Fp8Bf8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2792,9 +3400,6 @@ VWmmaF3216x16x64Fp8Bf8Vop3p::VWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X64_FP8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2802,7 +3407,20 @@ VWmmaF3216x16x64Fp8Bf8Vop3p::VWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x64Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x64_fp8_bf8_e64_dpp" + : "v_wmma_f32_16x16x64_fp8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X64_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2812,8 +3430,7 @@ VWmmaF3216x16x64Bf8Fp8Vop3p::VWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *inst ? "v_wmma_f32_16x16x64_bf8_fp8_e64_dpp" : "v_wmma_f32_16x16x64_bf8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Bf8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Bf8Fp8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2825,9 +3442,6 @@ VWmmaF3216x16x64Bf8Fp8Vop3p::VWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X64_BF8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2835,7 +3449,20 @@ VWmmaF3216x16x64Bf8Fp8Vop3p::VWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x64Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x64_bf8_fp8_e64_dpp" + : "v_wmma_f32_16x16x64_bf8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X64_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2845,8 +3472,7 @@ VWmmaF3216x16x64Bf8Bf8Vop3p::VWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *inst ? "v_wmma_f32_16x16x64_bf8_bf8_e64_dpp" : "v_wmma_f32_16x16x64_bf8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Bf8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x64Bf8Bf8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2858,9 +3484,6 @@ VWmmaF3216x16x64Bf8Bf8Vop3p::VWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X64_BF8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2868,7 +3491,20 @@ VWmmaF3216x16x64Bf8Bf8Vop3p::VWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x64Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x64_bf8_bf8_e64_dpp" + : "v_wmma_f32_16x16x64_bf8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X64_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2878,8 +3514,7 @@ VWmmaF1616x16x64Fp8Fp8Vop3p::VWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *inst ? "v_wmma_f16_16x16x64_fp8_fp8_e64_dpp" : "v_wmma_f16_16x16x64_fp8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Fp8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Fp8Fp8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2891,9 +3526,6 @@ VWmmaF1616x16x64Fp8Fp8Vop3p::VWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X64_FP8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2901,7 +3533,20 @@ VWmmaF1616x16x64Fp8Fp8Vop3p::VWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x64Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x64_fp8_fp8_e64_dpp" + : "v_wmma_f16_16x16x64_fp8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X64_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2911,8 +3556,7 @@ VWmmaF1616x16x64Fp8Bf8Vop3p::VWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *inst ? "v_wmma_f16_16x16x64_fp8_bf8_e64_dpp" : "v_wmma_f16_16x16x64_fp8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Fp8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Fp8Bf8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2924,9 +3568,6 @@ VWmmaF1616x16x64Fp8Bf8Vop3p::VWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X64_FP8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2934,7 +3575,20 @@ VWmmaF1616x16x64Fp8Bf8Vop3p::VWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x64Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x64_fp8_bf8_e64_dpp" + : "v_wmma_f16_16x16x64_fp8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X64_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2944,8 +3598,7 @@ VWmmaF1616x16x64Bf8Fp8Vop3p::VWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *inst ? "v_wmma_f16_16x16x64_bf8_fp8_e64_dpp" : "v_wmma_f16_16x16x64_bf8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Bf8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Bf8Fp8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2957,9 +3610,6 @@ VWmmaF1616x16x64Bf8Fp8Vop3p::VWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X64_BF8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -2967,7 +3617,20 @@ VWmmaF1616x16x64Bf8Fp8Vop3p::VWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x64Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x64_bf8_fp8_e64_dpp" + : "v_wmma_f16_16x16x64_bf8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X64_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2977,8 +3640,7 @@ VWmmaF1616x16x64Bf8Bf8Vop3p::VWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *inst ? "v_wmma_f16_16x16x64_bf8_bf8_e64_dpp" : "v_wmma_f16_16x16x64_bf8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Bf8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x64Bf8Bf8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -2990,9 +3652,6 @@ VWmmaF1616x16x64Bf8Bf8Vop3p::VWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X64_BF8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3000,7 +3659,20 @@ VWmmaF1616x16x64Bf8Bf8Vop3p::VWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x64Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x64_bf8_bf8_e64_dpp" + : "v_wmma_f16_16x16x64_bf8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X64_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3010,8 +3682,7 @@ VWmmaI3216x16x64Iu8Vop3p::VWmmaI3216x16x64Iu8Vop3p(const MachineInst *inst) ? "v_wmma_i32_16x16x64_iu8_e64_dpp" : "v_wmma_i32_16x16x64_iu8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaI3216x16x64Iu8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaI3216x16x64Iu8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3023,9 +3694,6 @@ VWmmaI3216x16x64Iu8Vop3p::VWmmaI3216x16x64Iu8Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X64_IU8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3033,7 +3701,20 @@ VWmmaI3216x16x64Iu8Vop3p::VWmmaI3216x16x64Iu8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x64Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x64Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x64_iu8_e64_dpp" + : "v_wmma_i32_16x16x64_iu8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X64_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3043,8 +3724,7 @@ VSwmmacF3216x16x128Fp8Fp8Vop3p::VSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst ? "v_swmmac_f32_16x16x128_fp8_fp8_e64_dpp" : "v_swmmac_f32_16x16x128_fp8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Fp8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Fp8Fp8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3055,9 +3735,6 @@ VSwmmacF3216x16x128Fp8Fp8Vop3p::VSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X128_FP8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3065,7 +3742,20 @@ VSwmmacF3216x16x128Fp8Fp8Vop3p::VSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x128_fp8_fp8_e64_dpp" + : "v_swmmac_f32_16x16x128_fp8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X128_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3084,8 +3774,7 @@ VSwmmacF3216x16x128Fp8Bf8Vop3p::VSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst ? "v_swmmac_f32_16x16x128_fp8_bf8_e64_dpp" : "v_swmmac_f32_16x16x128_fp8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Fp8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Fp8Bf8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3096,9 +3785,6 @@ VSwmmacF3216x16x128Fp8Bf8Vop3p::VSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X128_FP8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3106,7 +3792,20 @@ VSwmmacF3216x16x128Fp8Bf8Vop3p::VSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x128_fp8_bf8_e64_dpp" + : "v_swmmac_f32_16x16x128_fp8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X128_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3125,8 +3824,7 @@ VSwmmacF3216x16x128Bf8Fp8Vop3p::VSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst ? "v_swmmac_f32_16x16x128_bf8_fp8_e64_dpp" : "v_swmmac_f32_16x16x128_bf8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Bf8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Bf8Fp8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3137,9 +3835,6 @@ VSwmmacF3216x16x128Bf8Fp8Vop3p::VSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X128_BF8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3147,7 +3842,20 @@ VSwmmacF3216x16x128Bf8Fp8Vop3p::VSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x128_bf8_fp8_e64_dpp" + : "v_swmmac_f32_16x16x128_bf8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X128_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3166,8 +3874,7 @@ VSwmmacF3216x16x128Bf8Bf8Vop3p::VSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst ? "v_swmmac_f32_16x16x128_bf8_bf8_e64_dpp" : "v_swmmac_f32_16x16x128_bf8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Bf8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF3216x16x128Bf8Bf8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3178,9 +3885,6 @@ VSwmmacF3216x16x128Bf8Bf8Vop3p::VSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X128_BF8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3188,7 +3892,20 @@ VSwmmacF3216x16x128Bf8Bf8Vop3p::VSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x128_bf8_bf8_e64_dpp" + : "v_swmmac_f32_16x16x128_bf8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X128_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3207,8 +3924,7 @@ VSwmmacF1616x16x128Fp8Fp8Vop3p::VSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst ? "v_swmmac_f16_16x16x128_fp8_fp8_e64_dpp" : "v_swmmac_f16_16x16x128_fp8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Fp8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Fp8Fp8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3219,9 +3935,6 @@ VSwmmacF1616x16x128Fp8Fp8Vop3p::VSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F16_16X16X128_FP8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3229,7 +3942,20 @@ VSwmmacF1616x16x128Fp8Fp8Vop3p::VSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f16_16x16x128_fp8_fp8_e64_dpp" + : "v_swmmac_f16_16x16x128_fp8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F16_16X16X128_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3248,8 +3974,7 @@ VSwmmacF1616x16x128Fp8Bf8Vop3p::VSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst ? "v_swmmac_f16_16x16x128_fp8_bf8_e64_dpp" : "v_swmmac_f16_16x16x128_fp8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Fp8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Fp8Bf8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3260,9 +3985,6 @@ VSwmmacF1616x16x128Fp8Bf8Vop3p::VSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F16_16X16X128_FP8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3270,7 +3992,20 @@ VSwmmacF1616x16x128Fp8Bf8Vop3p::VSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f16_16x16x128_fp8_bf8_e64_dpp" + : "v_swmmac_f16_16x16x128_fp8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F16_16X16X128_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3289,8 +4024,7 @@ VSwmmacF1616x16x128Bf8Fp8Vop3p::VSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst ? "v_swmmac_f16_16x16x128_bf8_fp8_e64_dpp" : "v_swmmac_f16_16x16x128_bf8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Bf8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Bf8Fp8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3301,9 +4035,6 @@ VSwmmacF1616x16x128Bf8Fp8Vop3p::VSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F16_16X16X128_BF8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3311,7 +4042,20 @@ VSwmmacF1616x16x128Bf8Fp8Vop3p::VSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f16_16x16x128_bf8_fp8_e64_dpp" + : "v_swmmac_f16_16x16x128_bf8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F16_16X16X128_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3330,8 +4074,7 @@ VSwmmacF1616x16x128Bf8Bf8Vop3p::VSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst ? "v_swmmac_f16_16x16x128_bf8_bf8_e64_dpp" : "v_swmmac_f16_16x16x128_bf8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Bf8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacF1616x16x128Bf8Bf8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3342,9 +4085,6 @@ VSwmmacF1616x16x128Bf8Bf8Vop3p::VSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F16_16X16X128_BF8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3352,7 +4092,20 @@ VSwmmacF1616x16x128Bf8Bf8Vop3p::VSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst } namespace detail { -std::unique_ptr decodeVSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f16_16x16x128_bf8_bf8_e64_dpp" + : "v_swmmac_f16_16x16x128_bf8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F16_16X16X128_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3371,8 +4124,7 @@ VSwmmacI3216x16x128Iu8Vop3p::VSwmmacI3216x16x128Iu8Vop3p(const MachineInst *inst ? "v_swmmac_i32_16x16x128_iu8_e64_dpp" : "v_swmmac_i32_16x16x128_iu8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VSwmmacI3216x16x128Iu8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VSwmmacI3216x16x128Iu8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3383,9 +4135,6 @@ VSwmmacI3216x16x128Iu8Vop3p::VSwmmacI3216x16x128Iu8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_I32_16X16X128_IU8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3393,7 +4142,20 @@ VSwmmacI3216x16x128Iu8Vop3p::VSwmmacI3216x16x128Iu8Vop3p(const MachineInst *inst } namespace detail { -std::unique_ptr decodeVSwmmacI3216x16x128Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacI3216x16x128Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_i32_16x16x128_iu8_e64_dpp" + : "v_swmmac_i32_16x16x128_iu8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_I32_16X16X128_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3412,8 +4174,7 @@ VWmmaF3216x16x128Fp8Fp8Vop3p::VWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *in ? "v_wmma_f32_16x16x128_fp8_fp8_e64_dpp" : "v_wmma_f32_16x16x128_fp8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Fp8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Fp8Fp8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3424,18 +4185,6 @@ VWmmaF3216x16x128Fp8Fp8Vop3p::VWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F32_16X16X128_FP8_FP8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X128_FP8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3443,7 +4192,29 @@ VWmmaF3216x16x128Fp8Fp8Vop3p::VWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x128_fp8_fp8_e64_dpp" + : "v_wmma_f32_16x16x128_fp8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_FP8_FP8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3453,8 +4224,7 @@ VWmmaF3216x16x128Fp8Bf8Vop3p::VWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *in ? "v_wmma_f32_16x16x128_fp8_bf8_e64_dpp" : "v_wmma_f32_16x16x128_fp8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Fp8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Fp8Bf8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3465,18 +4235,6 @@ VWmmaF3216x16x128Fp8Bf8Vop3p::VWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F32_16X16X128_FP8_BF8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X128_FP8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3484,7 +4242,29 @@ VWmmaF3216x16x128Fp8Bf8Vop3p::VWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x128_fp8_bf8_e64_dpp" + : "v_wmma_f32_16x16x128_fp8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_FP8_BF8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3494,8 +4274,7 @@ VWmmaF3216x16x128Bf8Fp8Vop3p::VWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *in ? "v_wmma_f32_16x16x128_bf8_fp8_e64_dpp" : "v_wmma_f32_16x16x128_bf8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Bf8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Bf8Fp8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3506,18 +4285,6 @@ VWmmaF3216x16x128Bf8Fp8Vop3p::VWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F32_16X16X128_BF8_FP8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X128_BF8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3525,7 +4292,29 @@ VWmmaF3216x16x128Bf8Fp8Vop3p::VWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x128_bf8_fp8_e64_dpp" + : "v_wmma_f32_16x16x128_bf8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_BF8_FP8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3535,8 +4324,7 @@ VWmmaF3216x16x128Bf8Bf8Vop3p::VWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *in ? "v_wmma_f32_16x16x128_bf8_bf8_e64_dpp" : "v_wmma_f32_16x16x128_bf8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Bf8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128Bf8Bf8Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3547,18 +4335,6 @@ VWmmaF3216x16x128Bf8Bf8Vop3p::VWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F32_16X16X128_BF8_BF8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X128_BF8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3566,7 +4342,29 @@ VWmmaF3216x16x128Bf8Bf8Vop3p::VWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x128_bf8_bf8_e64_dpp" + : "v_wmma_f32_16x16x128_bf8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_BF8_BF8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X128_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3576,8 +4374,7 @@ VWmmaF1616x16x128Fp8Fp8Vop3p::VWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *in ? "v_wmma_f16_16x16x128_fp8_fp8_e64_dpp" : "v_wmma_f16_16x16x128_fp8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Fp8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Fp8Fp8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3588,18 +4385,6 @@ VWmmaF1616x16x128Fp8Fp8Vop3p::VWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F16_16X16X128_FP8_FP8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X128_FP8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3607,7 +4392,29 @@ VWmmaF1616x16x128Fp8Fp8Vop3p::VWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x128Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x128_fp8_fp8_e64_dpp" + : "v_wmma_f16_16x16x128_fp8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_FP8_FP8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3617,8 +4424,7 @@ VWmmaF1616x16x128Fp8Bf8Vop3p::VWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *in ? "v_wmma_f16_16x16x128_fp8_bf8_e64_dpp" : "v_wmma_f16_16x16x128_fp8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Fp8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Fp8Bf8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3629,18 +4435,6 @@ VWmmaF1616x16x128Fp8Bf8Vop3p::VWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F16_16X16X128_FP8_BF8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X128_FP8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3648,7 +4442,29 @@ VWmmaF1616x16x128Fp8Bf8Vop3p::VWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x128Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x128_fp8_bf8_e64_dpp" + : "v_wmma_f16_16x16x128_fp8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_FP8_BF8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3658,8 +4474,7 @@ VWmmaF1616x16x128Bf8Fp8Vop3p::VWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *in ? "v_wmma_f16_16x16x128_bf8_fp8_e64_dpp" : "v_wmma_f16_16x16x128_bf8_fp8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Bf8Fp8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Bf8Fp8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3670,18 +4485,6 @@ VWmmaF1616x16x128Bf8Fp8Vop3p::VWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F16_16X16X128_BF8_FP8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X128_BF8_FP8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3689,7 +4492,29 @@ VWmmaF1616x16x128Bf8Fp8Vop3p::VWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x128Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x128_bf8_fp8_e64_dpp" + : "v_wmma_f16_16x16x128_bf8_fp8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_BF8_FP8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3699,8 +4524,7 @@ VWmmaF1616x16x128Bf8Bf8Vop3p::VWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *in ? "v_wmma_f16_16x16x128_bf8_bf8_e64_dpp" : "v_wmma_f16_16x16x128_bf8_bf8", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Bf8Bf8Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF1616x16x128Bf8Bf8Vop3p)), vdst(128, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3711,18 +4535,6 @@ VWmmaF1616x16x128Bf8Bf8Vop3p::VWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *in src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (!((reinterpret_cast(inst)->src2 >= 0 && - reinterpret_cast(inst)->src2 <= 124) || - (reinterpret_cast(inst)->src2 >= 128 && - reinterpret_cast(inst)->src2 <= 208) || - (reinterpret_cast(inst)->src2 >= 240 && - reinterpret_cast(inst)->src2 <= 248) || - (reinterpret_cast(inst)->src2 >= 256 && - reinterpret_cast(inst)->src2 <= 511))) - throw util::InvalidInst("V_WMMA_F16_16X16X128_BF8_BF8 has an invalid accumulator selector", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X128_BF8_BF8 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3730,7 +4542,29 @@ VWmmaF1616x16x128Bf8Bf8Vop3p::VWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *in } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x128Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x128_bf8_bf8_e64_dpp" + : "v_wmma_f16_16x16x128_bf8_bf8", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (!((reinterpret_cast(inst)->src2 >= 0 && + reinterpret_cast(inst)->src2 <= 124) || + (reinterpret_cast(inst)->src2 >= 128 && + reinterpret_cast(inst)->src2 <= 208) || + (reinterpret_cast(inst)->src2 >= 240 && + reinterpret_cast(inst)->src2 <= 248) || + (reinterpret_cast(inst)->src2 >= 256 && + reinterpret_cast(inst)->src2 <= 511))) [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_BF8_BF8 has an invalid accumulator selector"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X128_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3740,8 +4574,7 @@ VWmmaF3232x16x128F4Vop3p::VWmmaF3232x16x128F4Vop3p(const MachineInst *inst) ? "v_wmma_f32_32x16x128_f4_e64_dpp" : "v_wmma_f32_32x16x128_f4", reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VWmmaF3232x16x128F4Vop3p), - LiteralSupport::None), + selected_exec_fn(InstructionExecutionId::VWmmaF3232x16x128F4Vop3p)), vdst(512, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), src0(512, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), src1(256, OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src1), @@ -3753,9 +4586,6 @@ VWmmaF3232x16x128F4Vop3p::VWmmaF3232x16x128F4Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_32X16X128_F4 does not support DPP", ""); vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); @@ -3763,14 +4593,27 @@ VWmmaF3232x16x128F4Vop3p::VWmmaF3232x16x128F4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWmmaF3232x16x128F4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3232x16x128F4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_32x16x128_f4_e64_dpp" + : "v_wmma_f32_32x16x128_f4", + reinterpret_cast(opcode), emit_error, LiteralSupport::None); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_32X16X128_F4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail VWmmaScaleF32Vop3px2::VWmmaScaleF32Vop3px2(const MachineInst *inst) : Vop3p(gfx1250_scaled_wmma_mnemonic(inst), reinterpret_cast(inst + 2), - selected_exec_fn(InstructionExecutionId::VWmmaScaleF32Vop3px2), LiteralSupport::Both, 3, + selected_exec_fn(InstructionExecutionId::VWmmaScaleF32Vop3px2), Vop3p::ExtensionDecodePolicy::Skip), vdst(gfx1250_scaled_wmma_dst_size_bits(inst), OperandType::OPR_VGPR, reinterpret_cast(inst + 2)->vdst), diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmp.cpp index 334e4fa5b08b..da8dc18b37a9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmp.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -64,7 +63,15 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_dpp" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -120,7 +127,15 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_dpp" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -176,7 +191,15 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_dpp" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +255,15 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_dpp" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +319,15 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_dpp" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +383,15 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_dpp" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +447,15 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_dpp" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +511,15 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_dpp" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +575,15 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_dpp" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +639,15 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_dpp" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -624,7 +703,15 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_dpp" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -680,7 +767,15 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_dpp" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -736,7 +831,15 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_dpp" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -792,7 +895,15 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_dpp" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -845,7 +956,15 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_dpp" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -898,7 +1017,15 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_dpp" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1078,15 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_dpp" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1004,7 +1139,15 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_dpp" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1200,15 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_dpp" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1261,15 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_dpp" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1163,7 +1322,15 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_dpp" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1216,7 +1383,15 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_dpp" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1269,7 +1444,15 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_dpp" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1322,7 +1505,15 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_dpp" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1375,7 +1566,15 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_dpp" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1428,7 +1627,15 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_dpp" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1688,15 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_dpp" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1534,7 +1749,15 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_dpp" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1565,16 +1788,24 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_dpp" + : "v_cmp_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1605,16 +1836,24 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_dpp" + : "v_cmp_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1645,16 +1884,24 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_dpp" + : "v_cmp_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1685,16 +1932,24 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_dpp" + : "v_cmp_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1725,16 +1980,24 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_dpp" + : "v_cmp_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1765,16 +2028,24 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_dpp" + : "v_cmp_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1805,16 +2076,24 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_dpp" + : "v_cmp_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1845,16 +2124,24 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_dpp" + : "v_cmp_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1885,16 +2172,24 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_dpp" + : "v_cmp_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1925,16 +2220,24 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_dpp" + : "v_cmp_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1965,16 +2268,24 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_dpp" + : "v_cmp_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2005,16 +2316,24 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_dpp" + : "v_cmp_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2045,16 +2364,24 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_dpp" + : "v_cmp_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2085,16 +2412,24 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_dpp" + : "v_cmp_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2150,7 +2485,15 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_dpp" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2206,7 +2549,15 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_dpp" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2262,7 +2613,15 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_dpp" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2318,7 +2677,15 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_dpp" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2374,7 +2741,15 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_dpp" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2430,7 +2805,15 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_dpp" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2486,7 +2869,15 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_dpp" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2542,7 +2933,15 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_dpp" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2598,7 +2997,15 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_dpp" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2654,7 +3061,15 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_dpp" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2710,7 +3125,15 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_dpp" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2766,7 +3189,15 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_dpp" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2819,7 +3250,15 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_dpp" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2872,7 +3311,15 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_dpp" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2925,7 +3372,15 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_dpp" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2978,7 +3433,15 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_dpp" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3031,7 +3494,15 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_dpp" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3084,7 +3555,15 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_dpp" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3137,7 +3616,15 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_dpp" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3190,7 +3677,15 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_dpp" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3243,7 +3738,15 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_dpp" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3296,7 +3799,15 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_dpp" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3349,7 +3860,15 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_dpp" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3402,7 +3921,15 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_dpp" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3433,16 +3960,24 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_dpp" + : "v_cmp_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3473,16 +4008,24 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_dpp" + : "v_cmp_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3513,16 +4056,24 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_dpp" + : "v_cmp_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3553,16 +4104,24 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_dpp" + : "v_cmp_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3593,16 +4152,24 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_dpp" + : "v_cmp_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3633,16 +4200,24 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_dpp" + : "v_cmp_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3673,16 +4248,24 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_dpp" + : "v_cmp_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3713,16 +4296,24 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_dpp" + : "v_cmp_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3753,16 +4344,24 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_dpp" + : "v_cmp_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3793,16 +4392,24 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_dpp" + : "v_cmp_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3833,16 +4440,24 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_dpp" + : "v_cmp_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3873,16 +4488,24 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_dpp" + : "v_cmp_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3938,7 +4561,16 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_dpp" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3991,7 +4623,16 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_dpp" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4022,16 +4663,25 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); vsrc1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_dpp" + : "v_cmp_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmpx.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmpx.cpp index a952ac3da05b..aee8d67c1122 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmpx.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc_cmpx.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -68,7 +67,15 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_dpp" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -128,7 +135,15 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_dpp" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -188,7 +203,15 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_dpp" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -248,7 +271,15 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_dpp" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -308,7 +339,15 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_dpp" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,7 +407,15 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_dpp" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +475,15 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_dpp" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +543,15 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_dpp" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -548,7 +611,16 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_dpp" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -608,7 +680,16 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_dpp" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -668,7 +749,16 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_dpp" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -728,7 +818,16 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_dpp" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -788,7 +887,16 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_dpp" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -848,7 +956,16 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_dpp" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -905,7 +1022,15 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_dpp" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -962,7 +1087,15 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_dpp" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1019,7 +1152,15 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_dpp" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1076,7 +1217,15 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_dpp" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1133,7 +1282,15 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_dpp" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1190,7 +1347,15 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_dpp" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1247,7 +1412,15 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_dpp" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1304,7 +1477,15 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_dpp" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1361,7 +1542,16 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_dpp" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1418,7 +1608,16 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_dpp" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1475,7 +1674,16 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_dpp" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1532,7 +1740,16 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_dpp" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1589,7 +1806,16 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_dpp" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1646,7 +1872,16 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_dpp" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1679,9 +1914,6 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1690,7 +1922,18 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_dpp" + : "v_cmpx_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1723,9 +1966,6 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1734,7 +1974,18 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_dpp" + : "v_cmpx_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1767,9 +2018,6 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1778,7 +2026,18 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_dpp" + : "v_cmpx_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1811,9 +2070,6 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1822,7 +2078,18 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_dpp" + : "v_cmpx_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1855,9 +2122,6 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1866,7 +2130,18 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_dpp" + : "v_cmpx_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1899,9 +2174,6 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1910,7 +2182,18 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_dpp" + : "v_cmpx_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1943,9 +2226,6 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1954,7 +2234,18 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_dpp" + : "v_cmpx_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1987,9 +2278,6 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -1998,7 +2286,18 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_dpp" + : "v_cmpx_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2031,9 +2330,6 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -2042,7 +2338,19 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_dpp" + : "v_cmpx_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2075,9 +2383,6 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -2086,7 +2391,19 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_dpp" + : "v_cmpx_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2119,9 +2436,6 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -2130,7 +2444,19 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_dpp" + : "v_cmpx_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2163,9 +2489,6 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -2174,7 +2497,19 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_dpp" + : "v_cmpx_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2207,9 +2542,6 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -2218,7 +2550,19 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_dpp" + : "v_cmpx_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2251,9 +2595,6 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -2262,7 +2603,19 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_dpp" + : "v_cmpx_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2322,7 +2675,15 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_dpp" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2382,7 +2743,15 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_dpp" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2442,7 +2811,15 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_dpp" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2502,7 +2879,15 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_dpp" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2562,7 +2947,15 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_dpp" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2622,7 +3015,15 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_dpp" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2682,7 +3083,15 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_dpp" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2742,7 +3151,15 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_dpp" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2802,7 +3219,15 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_dpp" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2862,7 +3287,15 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_dpp" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2922,7 +3355,15 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_dpp" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2982,7 +3423,15 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_dpp" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3039,7 +3488,15 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_dpp" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3096,7 +3553,15 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_dpp" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3153,7 +3618,15 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_dpp" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3210,7 +3683,15 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_dpp" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3267,7 +3748,15 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_dpp" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3324,7 +3813,15 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_dpp" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3381,7 +3878,15 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_dpp" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3438,7 +3943,15 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_dpp" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3495,7 +4008,15 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_dpp" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3552,7 +4073,15 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_dpp" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3609,7 +4138,15 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_dpp" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3666,7 +4203,15 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_dpp" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3699,9 +4244,6 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3710,7 +4252,18 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_dpp" + : "v_cmpx_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3743,9 +4296,6 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3754,7 +4304,18 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_dpp" + : "v_cmpx_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3787,9 +4348,6 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3798,7 +4356,18 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_dpp" + : "v_cmpx_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3831,9 +4400,6 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3842,7 +4408,18 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_dpp" + : "v_cmpx_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3875,9 +4452,6 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3886,7 +4460,18 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_dpp" + : "v_cmpx_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3919,9 +4504,6 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3930,7 +4512,18 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_dpp" + : "v_cmpx_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3963,9 +4556,6 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -3974,7 +4564,18 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_dpp" + : "v_cmpx_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4007,9 +4608,6 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4018,7 +4616,18 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_dpp" + : "v_cmpx_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4051,9 +4660,6 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4062,7 +4668,18 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_dpp" + : "v_cmpx_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4095,9 +4712,6 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4106,7 +4720,18 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_dpp" + : "v_cmpx_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4139,9 +4764,6 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4150,7 +4772,18 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_dpp" + : "v_cmpx_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4183,9 +4816,6 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4194,7 +4824,18 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_dpp" + : "v_cmpx_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4254,7 +4895,16 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_dpp" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4311,7 +4961,16 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_dpp" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4344,9 +5003,6 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) (static_cast(words[literal_word + 1]) << 32) | words[literal_word]; src0 = Operand(64, OperandType::OPR_SIMM64, literal64, true); } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); @@ -4355,7 +5011,19 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_dpp" + : "v_cmpx_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.cpp index 6c188be221b7..7ff9f518e22f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.cpp @@ -136,6 +136,43 @@ bool Vopd::is_float64_op(uint16_t op) { } } +Result Vopd::validate_encoding(const MachineInst *inst, const util::DiagnosticEmitter &emit_error) { + const auto *words = reinterpret_cast(inst); + const uint32_t word0 = words[0]; + const uint32_t word1 = words[1]; + if ((word0 >> 24) == 0xCF) { + const uint16_t opx = static_cast((word0 >> 18) & 0x3F); + const uint16_t opy = static_cast((word0 >> 12) & 0x3F); + if (!is_valid_opcode(opx, kVopd3XOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD3 X opcode"; + if (!is_valid_opcode(opy, kVopd3YOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD3 Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcx0 == 255 || srcy0 == 254 || srcy0 == 255) [[unlikely]] + return emit_error.emit() << "VOPD3 does not support literal selectors"; + const uint32_t word2 = words[2]; + const uint16_t vdstx = static_cast(word2 & 0xFF); + const uint16_t vdsty = static_cast((word2 >> 24) & 0xFF); + const uint32_t x_end = vdstx + (is_float64_op(opx) ? 2 : 1); + const uint32_t y_end = vdsty + (is_float64_op(opy) ? 2 : 1); + if (vdstx < y_end && vdsty < x_end) [[unlikely]] + return emit_error.emit() << "VOPD3 destination ranges overlap"; + return Result::success(); + } + const uint16_t opx = static_cast((word0 >> 22) & 0xF); + const uint16_t opy = static_cast((word0 >> 17) & 0x1F); + if (!is_valid_opcode(opx, kVopdXOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD X opcode"; + if (!is_valid_opcode(opy, kVopdYOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcy0 == 254) [[unlikely]] + return emit_error.emit() << "VOPD does not support 64-bit literals"; + return Result::success(); +} + Vopd::Vopd(const MachineInst *inst) : IsaInstruction("vopd", selected_exec_fn(InstructionExecutionId::Vopd)), dstx_(32, OperandType::OPR_VGPR, 0), dsty_(32, OperandType::OPR_VGPR, 0), @@ -154,14 +191,8 @@ Vopd::Vopd(const MachineInst *inst) word2_ = words[2]; opx_ = static_cast((word0_ >> 18) & 0x3F); opy_ = static_cast((word0_ >> 12) & 0x3F); - if (!is_valid_opcode(opx_, kVopd3XOpcodeMask)) - throw util::InvalidInst("invalid VOPD3 X opcode", ""); - if (!is_valid_opcode(opy_, kVopd3YOpcodeMask)) - throw util::InvalidInst("invalid VOPD3 Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); - if (srcx0 == 254 || srcx0 == 255 || srcy0 == 254 || srcy0 == 255) - throw util::InvalidInst("VOPD3 does not support literal selectors", ""); negx_ = static_cast((word1_ >> 9) & 0x7); negy_ = static_cast((word1_ >> 12) & 0x7); uint16_t vsrcx1 = static_cast((word1_ >> 16) & 0xFF); @@ -173,10 +204,6 @@ Vopd::Vopd(const MachineInst *inst) uint32_t x_bits = is_float64_op(opx_) ? 64 : 32; uint32_t y_bits = is_float64_op(opy_) ? 64 : 32; - const uint32_t x_end = vdstx + x_bits / 32; - const uint32_t y_end = vdsty + y_bits / 32; - if (vdstx < y_end && vdsty < x_end) - throw util::InvalidInst("VOPD3 destination ranges overlap", ""); dstx_ = Operand(x_bits, OperandType::OPR_VGPR, vdstx); dsty_ = Operand(y_bits, OperandType::OPR_VGPR, vdsty); srcx0_ = make_src0(x_bits, true, false, 0, srcx0); @@ -192,16 +219,10 @@ Vopd::Vopd(const MachineInst *inst) encoding_id_ = 0x32; opx_ = static_cast((word0_ >> 22) & 0xF); opy_ = static_cast((word0_ >> 17) & 0x1F); - if (!is_valid_opcode(opx_, kVopdXOpcodeMask)) - throw util::InvalidInst("invalid VOPD X opcode", ""); - if (!is_valid_opcode(opy_, kVopdYOpcodeMask)) - throw util::InvalidInst("invalid VOPD Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t vsrcx1 = static_cast((word0_ >> 9) & 0xFF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); uint16_t vsrcy1 = static_cast((word1_ >> 9) & 0xFF); - if (srcx0 == 254 || srcy0 == 254) - throw util::InvalidInst("VOPD does not support 64-bit literals", ""); uint16_t vdstx = static_cast((word1_ >> 24) & 0xFF); uint16_t vdsty_hi = static_cast((word1_ >> 17) & 0x7F); uint16_t vdsty = static_cast((vdsty_hi << 1) | ((~vdstx) & 1u)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.h index 3d1a636d1aae..154eb5c8c4d8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vopd.h @@ -9,6 +9,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/encodings.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.h" +#include "rocjitsu/isa/decode_result.h" #include #include @@ -18,6 +19,8 @@ namespace cdna5 { class Vopd : public IsaInstruction { public: explicit Vopd(const MachineInst *inst); + static Result validate_encoding(const MachineInst *inst, + const util::DiagnosticEmitter &emit_error); void execute_impl(amdgpu::Wavefront &wf); private: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vscratch.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vscratch.cpp index 2f2fe3c78fc4..a8b5ded9f88a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vscratch.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vscratch.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vscratch.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -33,7 +32,12 @@ ScratchLoadU8Vscratch::ScratchLoadU8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadU8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -58,7 +62,12 @@ ScratchLoadI8Vscratch::ScratchLoadI8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadI8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +92,12 @@ ScratchLoadU16Vscratch::ScratchLoadU16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadU16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadU16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -108,7 +122,12 @@ ScratchLoadI16Vscratch::ScratchLoadI16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadI16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadI16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -133,7 +152,12 @@ ScratchLoadB32Vscratch::ScratchLoadB32Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB32Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -158,7 +182,12 @@ ScratchLoadB64Vscratch::ScratchLoadB64Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB64Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -183,7 +212,12 @@ ScratchLoadB96Vscratch::ScratchLoadB96Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB96Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -208,7 +242,12 @@ ScratchLoadB128Vscratch::ScratchLoadB128Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB128Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +272,12 @@ ScratchStoreB8Vscratch::ScratchStoreB8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -258,7 +302,12 @@ ScratchStoreB16Vscratch::ScratchStoreB16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +332,12 @@ ScratchStoreB32Vscratch::ScratchStoreB32Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB32Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -308,7 +362,12 @@ ScratchStoreB64Vscratch::ScratchStoreB64Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB64Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -333,7 +392,12 @@ ScratchStoreB96Vscratch::ScratchStoreB96Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB96Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -358,7 +422,12 @@ ScratchStoreB128Vscratch::ScratchStoreB128Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB128Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -383,7 +452,12 @@ ScratchLoadD16U8Vscratch::ScratchLoadD16U8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16U8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16U8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +495,12 @@ ScratchLoadD16I8Vscratch::ScratchLoadD16I8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16I8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16I8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -459,7 +538,12 @@ ScratchLoadD16B16Vscratch::ScratchLoadD16B16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16B16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16B16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -497,7 +581,12 @@ ScratchLoadD16HiU8Vscratch::ScratchLoadD16HiU8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -535,7 +624,12 @@ ScratchLoadD16HiI8Vscratch::ScratchLoadD16HiI8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -573,7 +667,13 @@ ScratchLoadD16HiB16Vscratch::ScratchLoadD16HiB16Vscratch(const MachineInst *inst } namespace detail { -std::unique_ptr decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_hi_b16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -611,7 +711,13 @@ ScratchStoreD16HiB8Vscratch::ScratchStoreD16HiB8Vscratch(const MachineInst *inst } namespace detail { -std::unique_ptr decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_d16_hi_b8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -636,7 +742,13 @@ ScratchStoreD16HiB16Vscratch::ScratchStoreD16HiB16Vscratch(const MachineInst *in } namespace detail { -std::unique_ptr decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_d16_hi_b16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -663,7 +775,12 @@ ScratchLoadBlockVscratch::ScratchLoadBlockVscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadBlockVscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -690,7 +807,12 @@ ScratchStoreBlockVscratch::ScratchStoreBlockVscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreBlockVscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.cpp index e1e4a665a1b2..9956f46b5cb6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3p.h" -#include "util/except.h" #include #include #include @@ -15,1426 +14,1922 @@ namespace rocjitsu { namespace rdna1 { namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeExpExp(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicFcmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicFmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicFminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4COMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather8hPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetWaveidInWorkgroupSmem(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSInstPrefetchSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubvectorLoopBeginSopk(const MachineInst *opcode); -std::unique_ptr decodeSSubvectorLoopEndSopk(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpMovF32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpMovF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1F32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1llF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1lvF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMacLegacyF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMacLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMadmkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicFcmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicFmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicFminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4COMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather8hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetWaveidInWorkgroupSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSInstPrefetchSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubvectorLoopBeginSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubvectorLoopEndSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpMovF32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpMovF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1llF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1lvF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMacLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadmkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeVintrp(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMimg(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1452,88 +1947,102 @@ struct DecoderImpl { static const std::array sub_decode_smem; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVintrp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vintrp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vintrp[op.op](opcode); + return sub_decode_vintrp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMimg(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mimg::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mimg[op.op](opcode); + return sub_decode_mimg[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h index 59b4c77a7b8b..9caccc94e896 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA1_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace rdna1 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 3; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace rdna1 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/ds.cpp index 56da97398dd4..4c07bd8a7fca 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/ds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/ds.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +84,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +111,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +138,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +165,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +219,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +246,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +273,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +300,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +327,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -309,7 +356,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +381,11 @@ DsWriteB32Ds::DsWriteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +408,11 @@ DsWrite2B32Ds::DsWrite2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +435,12 @@ DsWrite2st64B32Ds::DsWrite2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +465,11 @@ DsCmpstB32Ds::DsCmpstB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -426,7 +494,11 @@ DsCmpstF32Ds::DsCmpstF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -449,7 +521,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +548,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +565,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +592,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +609,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +629,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -549,7 +646,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +665,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -577,7 +682,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -592,7 +701,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +726,11 @@ DsWriteB8Ds::DsWriteB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -634,7 +751,11 @@ DsWriteB16Ds::DsWriteB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +780,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +809,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -709,7 +838,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -734,7 +867,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -759,7 +896,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -784,7 +925,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +954,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +983,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1012,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -884,7 +1041,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -909,7 +1070,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1099,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -961,7 +1130,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -986,7 +1160,12 @@ DsWrxchgRtnB32Ds::DsWrxchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1013,7 +1192,12 @@ DsWrxchg2RtnB32Ds::DsWrxchg2RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1224,12 @@ DsWrxchg2st64RtnB32Ds::DsWrxchg2st64RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1256,12 @@ DsCmpstRtnB32Ds::DsCmpstRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1094,7 +1288,12 @@ DsCmpstRtnF32Ds::DsCmpstRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1119,7 +1318,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1347,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1170,7 +1377,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,7 +1398,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1423,11 @@ DsReadB32Ds::DsReadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1229,7 +1448,11 @@ DsRead2B32Ds::DsRead2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1250,7 +1473,12 @@ DsRead2st64B32Ds::DsRead2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1499,11 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1298,7 +1530,11 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1325,7 +1561,11 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1592,11 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1379,7 +1623,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1400,7 +1648,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1420,7 +1672,12 @@ DsOrderedCountDs::DsOrderedCountDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode) { +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_ordered_count", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1443,7 +1700,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1727,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1489,7 +1754,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1781,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1535,7 +1808,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1558,7 +1835,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1581,7 +1862,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1889,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1627,7 +1916,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1650,7 +1943,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +1970,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1696,7 +1997,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1721,7 +2026,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1742,7 +2051,11 @@ DsWriteB64Ds::DsWriteB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1765,7 +2078,11 @@ DsWrite2B64Ds::DsWrite2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1788,7 +2105,12 @@ DsWrite2st64B64Ds::DsWrite2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1813,7 +2135,11 @@ DsCmpstB64Ds::DsCmpstB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1838,7 +2164,11 @@ DsCmpstF64Ds::DsCmpstF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1861,7 +2191,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1884,7 +2218,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1909,7 +2247,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1934,7 +2276,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1959,7 +2305,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1984,7 +2334,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2009,7 +2363,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2034,7 +2392,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2059,7 +2421,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2084,7 +2450,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2109,7 +2479,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2134,7 +2508,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2159,7 +2537,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2184,7 +2566,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2209,7 +2595,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2236,7 +2626,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2261,7 +2656,12 @@ DsWrxchgRtnB64Ds::DsWrxchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2288,7 +2688,12 @@ DsWrxchg2RtnB64Ds::DsWrxchg2RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2315,7 +2720,12 @@ DsWrxchg2st64RtnB64Ds::DsWrxchg2st64RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2342,7 +2752,12 @@ DsCmpstRtnB64Ds::DsCmpstRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2369,7 +2784,12 @@ DsCmpstRtnF64Ds::DsCmpstRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2394,7 +2814,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2419,7 +2843,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2440,7 +2868,11 @@ DsReadB64Ds::DsReadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2461,7 +2893,11 @@ DsRead2B64Ds::DsRead2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2482,7 +2918,12 @@ DsRead2st64B64Ds::DsRead2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2507,7 +2948,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2528,7 +2974,12 @@ DsWriteB8D16HiDs::DsWriteB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2549,7 +3000,12 @@ DsWriteB16D16HiDs::DsWriteB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2570,7 +3026,11 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2597,7 +3057,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2624,7 +3089,11 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2651,7 +3120,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2678,7 +3152,11 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2705,7 +3183,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2732,7 +3215,12 @@ DsWriteAddtidB32Ds::DsWriteAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3241,12 @@ DsReadAddtidB32Ds::DsReadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2772,7 +3265,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2791,7 +3288,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2812,7 +3314,11 @@ DsWriteB96Ds::DsWriteB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2833,7 +3339,11 @@ DsWriteB128Ds::DsWriteB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2854,7 +3364,11 @@ DsReadB96Ds::DsReadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2875,7 +3389,11 @@ DsReadB128Ds::DsReadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h index bac9b161e9dc..90dd1a7a3b32 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/rdna1/isa.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/exp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/exp.cpp index 0fc8344b2588..e45ccf9d0804 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/exp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/exp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/exp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -33,7 +32,11 @@ ExpExp::ExpExp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeExpExp(const MachineInst *opcode) { +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Exp::validate_encoding("exp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/flat.cpp index c3df7903b801..4128ff6ffa7d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/flat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/flat.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -40,7 +39,12 @@ FlatLoadUbyteFlat::FlatLoadUbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +76,12 @@ FlatLoadSbyteFlat::FlatLoadSbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -104,7 +113,12 @@ FlatLoadUshortFlat::FlatLoadUshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -136,7 +150,12 @@ FlatLoadSshortFlat::FlatLoadSshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +187,12 @@ FlatLoadDwordFlat::FlatLoadDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -200,7 +224,12 @@ FlatLoadDwordx2Flat::FlatLoadDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +261,12 @@ FlatLoadDwordx4Flat::FlatLoadDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +298,12 @@ FlatLoadDwordx3Flat::FlatLoadDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +335,12 @@ FlatStoreByteFlat::FlatStoreByteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -328,7 +372,12 @@ FlatStoreByteD16HiFlat::FlatStoreByteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +409,12 @@ FlatStoreShortFlat::FlatStoreShortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -392,7 +446,12 @@ FlatStoreShortD16HiFlat::FlatStoreShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +483,12 @@ FlatStoreDwordFlat::FlatStoreDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +520,12 @@ FlatStoreDwordx2Flat::FlatStoreDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +557,12 @@ FlatStoreDwordx4Flat::FlatStoreDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +594,12 @@ FlatStoreDwordx3Flat::FlatStoreDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +631,12 @@ FlatLoadUbyteD16Flat::FlatLoadUbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -591,7 +675,12 @@ FlatLoadUbyteD16HiFlat::FlatLoadUbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -630,7 +719,12 @@ FlatLoadSbyteD16Flat::FlatLoadSbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -669,7 +763,12 @@ FlatLoadSbyteD16HiFlat::FlatLoadSbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +807,12 @@ FlatLoadShortD16Flat::FlatLoadShortD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -747,7 +851,12 @@ FlatLoadShortD16HiFlat::FlatLoadShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -789,7 +898,12 @@ FlatAtomicSwapFlat::FlatAtomicSwapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -824,7 +938,12 @@ FlatAtomicCmpswapFlat::FlatAtomicCmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +978,12 @@ FlatAtomicAddFlat::FlatAtomicAddFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1018,12 @@ FlatAtomicSubFlat::FlatAtomicSubFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -929,7 +1058,12 @@ FlatAtomicSminFlat::FlatAtomicSminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1098,12 @@ FlatAtomicUminFlat::FlatAtomicUminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -999,7 +1138,12 @@ FlatAtomicSmaxFlat::FlatAtomicSmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1034,7 +1178,12 @@ FlatAtomicUmaxFlat::FlatAtomicUmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1069,7 +1218,12 @@ FlatAtomicAndFlat::FlatAtomicAndFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1104,7 +1258,12 @@ FlatAtomicOrFlat::FlatAtomicOrFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1139,7 +1298,12 @@ FlatAtomicXorFlat::FlatAtomicXorFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1174,7 +1338,12 @@ FlatAtomicIncFlat::FlatAtomicIncFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1209,7 +1378,12 @@ FlatAtomicDecFlat::FlatAtomicDecFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1244,7 +1418,12 @@ FlatAtomicFcmpswapFlat::FlatAtomicFcmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fcmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1458,12 @@ FlatAtomicFminFlat::FlatAtomicFminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1314,7 +1498,12 @@ FlatAtomicFmaxFlat::FlatAtomicFmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1538,12 @@ FlatAtomicSwapX2Flat::FlatAtomicSwapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1384,7 +1578,12 @@ FlatAtomicCmpswapX2Flat::FlatAtomicCmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1618,12 @@ FlatAtomicAddX2Flat::FlatAtomicAddX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1454,7 +1658,12 @@ FlatAtomicSubX2Flat::FlatAtomicSubX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1489,7 +1698,12 @@ FlatAtomicSminX2Flat::FlatAtomicSminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1524,7 +1738,12 @@ FlatAtomicUminX2Flat::FlatAtomicUminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1559,7 +1778,12 @@ FlatAtomicSmaxX2Flat::FlatAtomicSmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1594,7 +1818,12 @@ FlatAtomicUmaxX2Flat::FlatAtomicUmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1629,7 +1858,12 @@ FlatAtomicAndX2Flat::FlatAtomicAndX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1664,7 +1898,12 @@ FlatAtomicOrX2Flat::FlatAtomicOrX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +1938,12 @@ FlatAtomicXorX2Flat::FlatAtomicXorX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1734,7 +1978,12 @@ FlatAtomicIncX2Flat::FlatAtomicIncX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1769,7 +2018,12 @@ FlatAtomicDecX2Flat::FlatAtomicDecX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2058,12 @@ FlatAtomicFcmpswapX2Flat::FlatAtomicFcmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fcmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1839,7 +2098,12 @@ FlatAtomicFminX2Flat::FlatAtomicFminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1874,7 +2138,12 @@ FlatAtomicFmaxX2Flat::FlatAtomicFmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mimg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mimg.cpp index d1850f9cac22..0b8b592f35d7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mimg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mimg.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/mimg.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -26,7 +25,11 @@ ImageLoadMimg::ImageLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -45,7 +48,12 @@ ImageLoadMipMimg::ImageLoadMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +72,12 @@ ImageLoadPckMimg::ImageLoadPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +96,12 @@ ImageLoadPckSgnMimg::ImageLoadPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +120,12 @@ ImageLoadMipPckMimg::ImageLoadMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +144,12 @@ ImageLoadMipPckSgnMimg::ImageLoadMipPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ ImageStoreMimg::ImageStoreMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +191,12 @@ ImageStoreMipMimg::ImageStoreMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +215,12 @@ ImageStorePckMimg::ImageStorePckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +239,12 @@ ImageStoreMipPckMimg::ImageStoreMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +263,12 @@ ImageGetResinfoMimg::ImageGetResinfoMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -236,7 +288,12 @@ ImageAtomicSwapMimg::ImageAtomicSwapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +313,12 @@ ImageAtomicCmpswapMimg::ImageAtomicCmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -276,7 +338,12 @@ ImageAtomicAddMimg::ImageAtomicAddMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +363,12 @@ ImageAtomicSubMimg::ImageAtomicSubMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -316,7 +388,12 @@ ImageAtomicSminMimg::ImageAtomicSminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +413,12 @@ ImageAtomicUminMimg::ImageAtomicUminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +438,12 @@ ImageAtomicSmaxMimg::ImageAtomicSmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +463,12 @@ ImageAtomicUmaxMimg::ImageAtomicUmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -396,7 +488,12 @@ ImageAtomicAndMimg::ImageAtomicAndMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -416,7 +513,12 @@ ImageAtomicOrMimg::ImageAtomicOrMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +538,12 @@ ImageAtomicXorMimg::ImageAtomicXorMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +563,12 @@ ImageAtomicIncMimg::ImageAtomicIncMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +588,12 @@ ImageAtomicDecMimg::ImageAtomicDecMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -496,7 +613,12 @@ ImageAtomicFcmpswapMimg::ImageAtomicFcmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicFcmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicFcmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_fcmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +638,12 @@ ImageAtomicFminMimg::ImageAtomicFminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicFminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicFminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_fmin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +663,12 @@ ImageAtomicFmaxMimg::ImageAtomicFmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicFmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicFmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_fmax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +689,12 @@ ImageSampleMimg::ImageSampleMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -578,7 +715,12 @@ ImageSampleClMimg::ImageSampleClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -599,7 +741,12 @@ ImageSampleDMimg::ImageSampleDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,7 +767,12 @@ ImageSampleDClMimg::ImageSampleDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -641,7 +793,12 @@ ImageSampleLMimg::ImageSampleLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +819,12 @@ ImageSampleBMimg::ImageSampleBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -683,7 +845,12 @@ ImageSampleBClMimg::ImageSampleBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +871,12 @@ ImageSampleLzMimg::ImageSampleLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -725,7 +897,12 @@ ImageSampleCMimg::ImageSampleCMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -746,7 +923,12 @@ ImageSampleCClMimg::ImageSampleCClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -767,7 +949,12 @@ ImageSampleCDMimg::ImageSampleCDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -788,7 +975,12 @@ ImageSampleCDClMimg::ImageSampleCDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +1001,12 @@ ImageSampleCLMimg::ImageSampleCLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -830,7 +1027,12 @@ ImageSampleCBMimg::ImageSampleCBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -851,7 +1053,12 @@ ImageSampleCBClMimg::ImageSampleCBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -872,7 +1079,12 @@ ImageSampleCLzMimg::ImageSampleCLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -893,7 +1105,12 @@ ImageSampleOMimg::ImageSampleOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -914,7 +1131,12 @@ ImageSampleClOMimg::ImageSampleClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -935,7 +1157,12 @@ ImageSampleDOMimg::ImageSampleDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -956,7 +1183,12 @@ ImageSampleDClOMimg::ImageSampleDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -977,7 +1209,12 @@ ImageSampleLOMimg::ImageSampleLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -998,7 +1235,12 @@ ImageSampleBOMimg::ImageSampleBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1019,7 +1261,12 @@ ImageSampleBClOMimg::ImageSampleBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1287,12 @@ ImageSampleLzOMimg::ImageSampleLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1313,12 @@ ImageSampleCOMimg::ImageSampleCOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1339,12 @@ ImageSampleCClOMimg::ImageSampleCClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1103,7 +1365,12 @@ ImageSampleCDOMimg::ImageSampleCDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1391,12 @@ ImageSampleCDClOMimg::ImageSampleCDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1145,7 +1417,12 @@ ImageSampleCLOMimg::ImageSampleCLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1166,7 +1443,12 @@ ImageSampleCBOMimg::ImageSampleCBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,7 +1469,12 @@ ImageSampleCBClOMimg::ImageSampleCBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1495,12 @@ ImageSampleCLzOMimg::ImageSampleCLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1229,7 +1521,12 @@ ImageGather4Mimg::ImageGather4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1250,7 +1547,12 @@ ImageGather4ClMimg::ImageGather4ClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1269,7 +1571,12 @@ ImageLoadBy2Mimg::ImageLoadBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1288,7 +1595,12 @@ ImageLoadBy4Mimg::ImageLoadBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1621,12 @@ ImageGather4LMimg::ImageGather4LMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1330,7 +1647,12 @@ ImageGather4BMimg::ImageGather4BMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1351,7 +1673,12 @@ ImageGather4BClMimg::ImageGather4BClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1372,7 +1699,12 @@ ImageGather4LzMimg::ImageGather4LzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1393,7 +1725,12 @@ ImageGather4CMimg::ImageGather4CMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1414,7 +1751,12 @@ ImageGather4CClMimg::ImageGather4CClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1433,7 +1775,12 @@ ImageLoadMipBy2Mimg::ImageLoadMipBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1799,12 @@ ImageLoadMipBy4Mimg::ImageLoadMipBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1473,7 +1825,12 @@ ImageGather4CLMimg::ImageGather4CLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1494,7 +1851,12 @@ ImageGather4CBMimg::ImageGather4CBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1515,7 +1877,12 @@ ImageGather4CBClMimg::ImageGather4CBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1536,7 +1903,12 @@ ImageGather4CLzMimg::ImageGather4CLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1557,7 +1929,12 @@ ImageGather4OMimg::ImageGather4OMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1578,7 +1955,12 @@ ImageGather4ClOMimg::ImageGather4ClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1597,7 +1979,12 @@ ImageStoreBy2Mimg::ImageStoreBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1616,7 +2003,12 @@ ImageStoreBy4Mimg::ImageStoreBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1637,7 +2029,12 @@ ImageGather4LOMimg::ImageGather4LOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1658,7 +2055,12 @@ ImageGather4BOMimg::ImageGather4BOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1679,7 +2081,12 @@ ImageGather4BClOMimg::ImageGather4BClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1700,7 +2107,12 @@ ImageGather4LzOMimg::ImageGather4LzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1721,7 +2133,12 @@ ImageGather4COMimg::ImageGather4COMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4COMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4COMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1742,7 +2159,12 @@ ImageGather4CClOMimg::ImageGather4CClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1761,7 +2183,12 @@ ImageStoreMipBy2Mimg::ImageStoreMipBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1780,7 +2207,12 @@ ImageStoreMipBy4Mimg::ImageStoreMipBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1801,7 +2233,12 @@ ImageGather4CLOMimg::ImageGather4CLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1822,7 +2259,12 @@ ImageGather4CBOMimg::ImageGather4CBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1843,7 +2285,12 @@ ImageGather4CBClOMimg::ImageGather4CBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1864,7 +2311,12 @@ ImageGather4CLzOMimg::ImageGather4CLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1885,7 +2337,12 @@ ImageGetLodMimg::ImageGetLodMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_lod", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1906,7 +2363,12 @@ ImageGather4hMimg::ImageGather4hMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1927,7 +2389,12 @@ ImageGather4hPckMimg::ImageGather4hPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1948,7 +2415,12 @@ ImageGather8hPckMimg::ImageGather8hPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather8hPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather8hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather8h_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1969,7 +2441,12 @@ ImageSampleCdMimg::ImageSampleCdMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1990,7 +2467,12 @@ ImageSampleCdClMimg::ImageSampleCdClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2011,7 +2493,12 @@ ImageSampleCCdMimg::ImageSampleCCdMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2519,12 @@ ImageSampleCCdClMimg::ImageSampleCCdClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2053,7 +2545,12 @@ ImageSampleCdOMimg::ImageSampleCdOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2074,7 +2571,12 @@ ImageSampleCdClOMimg::ImageSampleCdClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2095,7 +2597,12 @@ ImageSampleCCdOMimg::ImageSampleCCdOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2116,7 +2623,12 @@ ImageSampleCCdClOMimg::ImageSampleCCdClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2135,7 +2647,12 @@ ImageLoadPck2Mimg::ImageLoadPck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2154,7 +2671,12 @@ ImageLoadPck4Mimg::ImageLoadPck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2173,7 +2695,12 @@ ImageLoadMipPck2Mimg::ImageLoadMipPck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2192,7 +2719,12 @@ ImageLoadMipPck4Mimg::ImageLoadMipPck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2211,7 +2743,12 @@ ImageStorePck2Mimg::ImageStorePck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2230,7 +2767,12 @@ ImageStorePck4Mimg::ImageStorePck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2249,7 +2791,12 @@ ImageStoreMipPck2Mimg::ImageStoreMipPck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2268,7 +2815,12 @@ ImageStoreMipPck4Mimg::ImageStoreMipPck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2287,7 +2839,12 @@ ImageMsaaLoadMimg::ImageMsaaLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_msaa_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2308,7 +2865,12 @@ ImageSampleDG16Mimg::ImageSampleDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2329,7 +2891,12 @@ ImageSampleDClG16Mimg::ImageSampleDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2350,7 +2917,12 @@ ImageSampleCDG16Mimg::ImageSampleCDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2371,7 +2943,12 @@ ImageSampleCDClG16Mimg::ImageSampleCDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2392,7 +2969,12 @@ ImageSampleDOG16Mimg::ImageSampleDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2413,7 +2995,12 @@ ImageSampleDClOG16Mimg::ImageSampleDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2434,7 +3021,12 @@ ImageSampleCDOG16Mimg::ImageSampleCDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2455,7 +3047,12 @@ ImageSampleCDClOG16Mimg::ImageSampleCDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2476,7 +3073,12 @@ ImageSampleCdG16Mimg::ImageSampleCdG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2497,7 +3099,12 @@ ImageSampleCdClG16Mimg::ImageSampleCdClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2518,7 +3125,12 @@ ImageSampleCCdG16Mimg::ImageSampleCCdG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2539,7 +3151,12 @@ ImageSampleCCdClG16Mimg::ImageSampleCCdClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2560,7 +3177,12 @@ ImageSampleCdOG16Mimg::ImageSampleCdOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2581,7 +3203,12 @@ ImageSampleCdClOG16Mimg::ImageSampleCdClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2602,7 +3229,12 @@ ImageSampleCCdOG16Mimg::ImageSampleCCdOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2623,7 +3255,12 @@ ImageSampleCCdClOG16Mimg::ImageSampleCCdClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mtbuf.cpp index 5600fd17933c..f548f75e360f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mtbuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/mtbuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -68,7 +72,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -93,7 +102,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +132,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +162,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +192,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +222,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -218,7 +252,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +282,12 @@ TbufferLoadFormatD16XMtbuf::TbufferLoadFormatD16XMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -274,7 +318,13 @@ TbufferLoadFormatD16XyMtbuf::TbufferLoadFormatD16XyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +349,13 @@ TbufferLoadFormatD16XyzMtbuf::TbufferLoadFormatD16XyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +386,13 @@ TbufferLoadFormatD16XyzwMtbuf::TbufferLoadFormatD16XyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -355,7 +417,13 @@ TbufferStoreFormatD16XMtbuf::TbufferStoreFormatD16XMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -380,7 +448,13 @@ TbufferStoreFormatD16XyMtbuf::TbufferStoreFormatD16XyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +479,13 @@ TbufferStoreFormatD16XyzMtbuf::TbufferStoreFormatD16XyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +510,13 @@ TbufferStoreFormatD16XyzwMtbuf::TbufferStoreFormatD16XyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf.cpp index bfa5a970e3d6..382bdf8942b9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/mubuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -68,7 +72,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -93,7 +102,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +132,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +162,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +192,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +222,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -218,7 +252,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +282,12 @@ BufferLoadUbyteMubuf::BufferLoadUbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -268,7 +312,12 @@ BufferLoadSbyteMubuf::BufferLoadSbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -293,7 +342,12 @@ BufferLoadUshortMubuf::BufferLoadUshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +372,12 @@ BufferLoadSshortMubuf::BufferLoadSshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +402,12 @@ BufferLoadDwordMubuf::BufferLoadDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,7 +432,12 @@ BufferLoadDwordx2Mubuf::BufferLoadDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -393,7 +462,12 @@ BufferLoadDwordx4Mubuf::BufferLoadDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +492,12 @@ BufferLoadDwordx3Mubuf::BufferLoadDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -443,7 +522,12 @@ BufferStoreByteMubuf::BufferStoreByteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +552,12 @@ BufferStoreByteD16HiMubuf::BufferStoreByteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -493,7 +582,12 @@ BufferStoreShortMubuf::BufferStoreShortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -518,7 +612,12 @@ BufferStoreShortD16HiMubuf::BufferStoreShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,7 +642,12 @@ BufferStoreDwordMubuf::BufferStoreDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +672,12 @@ BufferStoreDwordx2Mubuf::BufferStoreDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +702,12 @@ BufferStoreDwordx4Mubuf::BufferStoreDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -618,7 +732,12 @@ BufferStoreDwordx3Mubuf::BufferStoreDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -643,7 +762,12 @@ BufferLoadUbyteD16Mubuf::BufferLoadUbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -675,7 +799,12 @@ BufferLoadUbyteD16HiMubuf::BufferLoadUbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +836,12 @@ BufferLoadSbyteD16Mubuf::BufferLoadSbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,7 +873,12 @@ BufferLoadSbyteD16HiMubuf::BufferLoadSbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -771,7 +910,12 @@ BufferLoadShortD16Mubuf::BufferLoadShortD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -803,7 +947,12 @@ BufferLoadShortD16HiMubuf::BufferLoadShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -835,7 +984,13 @@ BufferLoadFormatD16HiXMubuf::BufferLoadFormatD16HiXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -867,7 +1022,13 @@ BufferStoreFormatD16HiXMubuf::BufferStoreFormatD16HiXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1055,12 @@ BufferAtomicSwapMubuf::BufferAtomicSwapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -922,7 +1088,12 @@ BufferAtomicCmpswapMubuf::BufferAtomicCmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -949,7 +1120,12 @@ BufferAtomicAddMubuf::BufferAtomicAddMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -976,7 +1152,12 @@ BufferAtomicSubMubuf::BufferAtomicSubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1003,7 +1184,12 @@ BufferAtomicSminMubuf::BufferAtomicSminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1030,7 +1216,12 @@ BufferAtomicUminMubuf::BufferAtomicUminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1248,12 @@ BufferAtomicSmaxMubuf::BufferAtomicSmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1084,7 +1280,12 @@ BufferAtomicUmaxMubuf::BufferAtomicUmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1111,7 +1312,12 @@ BufferAtomicAndMubuf::BufferAtomicAndMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1344,12 @@ BufferAtomicOrMubuf::BufferAtomicOrMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1376,12 @@ BufferAtomicXorMubuf::BufferAtomicXorMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1192,7 +1408,12 @@ BufferAtomicIncMubuf::BufferAtomicIncMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1219,7 +1440,12 @@ BufferAtomicDecMubuf::BufferAtomicDecMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1247,7 +1473,12 @@ BufferAtomicFcmpswapMubuf::BufferAtomicFcmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fcmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1274,7 +1505,12 @@ BufferAtomicFminMubuf::BufferAtomicFminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1301,7 +1537,12 @@ BufferAtomicFmaxMubuf::BufferAtomicFmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1328,7 +1569,12 @@ BufferAtomicSwapX2Mubuf::BufferAtomicSwapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1356,7 +1602,12 @@ BufferAtomicCmpswapX2Mubuf::BufferAtomicCmpswapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1383,7 +1634,12 @@ BufferAtomicAddX2Mubuf::BufferAtomicAddX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1410,7 +1666,12 @@ BufferAtomicSubX2Mubuf::BufferAtomicSubX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1437,7 +1698,12 @@ BufferAtomicSminX2Mubuf::BufferAtomicSminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1464,7 +1730,12 @@ BufferAtomicUminX2Mubuf::BufferAtomicUminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1491,7 +1762,12 @@ BufferAtomicSmaxX2Mubuf::BufferAtomicSmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1794,12 @@ BufferAtomicUmaxX2Mubuf::BufferAtomicUmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1545,7 +1826,12 @@ BufferAtomicAndX2Mubuf::BufferAtomicAndX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1572,7 +1858,12 @@ BufferAtomicOrX2Mubuf::BufferAtomicOrX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1599,7 +1890,12 @@ BufferAtomicXorX2Mubuf::BufferAtomicXorX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1626,7 +1922,12 @@ BufferAtomicIncX2Mubuf::BufferAtomicIncX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1653,7 +1954,12 @@ BufferAtomicDecX2Mubuf::BufferAtomicDecX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1681,7 +1987,12 @@ BufferAtomicFcmpswapX2Mubuf::BufferAtomicFcmpswapX2Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fcmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1708,7 +2019,12 @@ BufferAtomicFminX2Mubuf::BufferAtomicFminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1735,7 +2051,12 @@ BufferAtomicFmaxX2Mubuf::BufferAtomicFmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1748,7 +2069,12 @@ BufferGl0InvMubuf::BufferGl0InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl0_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1761,7 +2087,12 @@ BufferGl1InvMubuf::BufferGl1InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1786,7 +2117,12 @@ BufferLoadFormatD16XMubuf::BufferLoadFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,7 +2154,12 @@ BufferLoadFormatD16XyMubuf::BufferLoadFormatD16XyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1843,7 +2184,13 @@ BufferLoadFormatD16XyzMubuf::BufferLoadFormatD16XyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1875,7 +2222,13 @@ BufferLoadFormatD16XyzwMubuf::BufferLoadFormatD16XyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1900,7 +2253,12 @@ BufferStoreFormatD16XMubuf::BufferStoreFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1925,7 +2283,13 @@ BufferStoreFormatD16XyMubuf::BufferStoreFormatD16XyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1950,7 +2314,13 @@ BufferStoreFormatD16XyzMubuf::BufferStoreFormatD16XyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1975,7 +2345,13 @@ BufferStoreFormatD16XyzwMubuf::BufferStoreFormatD16XyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp index 177a7234ee98..2b114c0e17c9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem.cpp index cebdc043b13c..6379102089f8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SLoadDwordSmem::SLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -56,7 +59,12 @@ SLoadDwordx2Smem::SLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +85,12 @@ SLoadDwordx4Smem::SLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -98,7 +111,12 @@ SLoadDwordx8Smem::SLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +137,12 @@ SLoadDwordx16Smem::SLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +163,12 @@ SScratchLoadDwordSmem::SScratchLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +189,12 @@ SScratchLoadDwordx2Smem::SScratchLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -182,7 +215,12 @@ SScratchLoadDwordx4Smem::SScratchLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSScratchLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSScratchLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_scratch_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +241,12 @@ SBufferLoadDwordSmem::SBufferLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +267,12 @@ SBufferLoadDwordx2Smem::SBufferLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -245,7 +293,12 @@ SBufferLoadDwordx4Smem::SBufferLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,12 @@ SBufferLoadDwordx8Smem::SBufferLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +345,12 @@ SBufferLoadDwordx16Smem::SBufferLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +363,11 @@ SGl1InvSmem::SGl1InvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode) { +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +380,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -328,7 +399,11 @@ SMemtimeSmem::SMemtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +418,12 @@ SMemrealtimeSmem::SMemrealtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memrealtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -363,7 +443,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -383,7 +467,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +487,12 @@ SGetWaveidInWorkgroupSmem::SGetWaveidInWorkgroupSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetWaveidInWorkgroupSmem(const MachineInst *opcode) { +DecodeResult decodeSGetWaveidInWorkgroupSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_get_waveid_in_workgroup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1.cpp index 8aa7152fcda3..52cda4805e49 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +173,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +201,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +230,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +255,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +281,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -295,7 +339,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -319,7 +368,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +398,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +424,11 @@ SFf0I32B32Sop1::SFf0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +450,11 @@ SFf0I32B64Sop1::SFf0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +475,11 @@ SFf1I32B32Sop1::SFf1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +501,11 @@ SFf1I32B64Sop1::SFf1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +526,12 @@ SFlbitI32B32Sop1::SFlbitI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +553,12 @@ SFlbitI32B64Sop1::SFlbitI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +579,11 @@ SFlbitI32Sop1::SFlbitI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +605,12 @@ SFlbitI32I64Sop1::SFlbitI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +632,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +658,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +685,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -604,7 +712,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +739,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +766,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +789,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -685,7 +812,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +839,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +861,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +897,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +935,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -823,7 +972,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +1009,12 @@ SAndn2SaveexecB64Sop1::SAndn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -887,7 +1046,12 @@ SOrn2SaveexecB64Sop1::SOrn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -919,7 +1083,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1120,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -983,7 +1157,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1007,7 +1186,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1216,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1241,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1266,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1295,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1325,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1145,7 +1354,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1177,7 +1390,12 @@ SAndn1SaveexecB64Sop1::SAndn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1209,7 +1427,12 @@ SOrn1SaveexecB64Sop1::SOrn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1241,7 +1464,12 @@ SAndn1WrexecB64Sop1::SAndn1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1273,7 +1501,12 @@ SAndn2WrexecB64Sop1::SAndn2WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1294,7 +1527,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1325,7 +1563,12 @@ SAndSaveexecB32Sop1::SAndSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1357,7 +1600,12 @@ SOrSaveexecB32Sop1::SOrSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1388,7 +1636,12 @@ SXorSaveexecB32Sop1::SXorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1672,12 @@ SAndn2SaveexecB32Sop1::SAndn2SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1450,7 +1708,12 @@ SOrn2SaveexecB32Sop1::SOrn2SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1744,12 @@ SNandSaveexecB32Sop1::SNandSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1780,12 @@ SNorSaveexecB32Sop1::SNorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1543,7 +1816,12 @@ SXnorSaveexecB32Sop1::SXnorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1574,7 +1852,12 @@ SAndn1SaveexecB32Sop1::SAndn1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1605,7 +1888,12 @@ SOrn1SaveexecB32Sop1::SOrn1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1636,7 +1924,12 @@ SAndn1WrexecB32Sop1::SAndn1WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1667,7 +1960,12 @@ SAndn2WrexecB32Sop1::SAndn2WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1687,7 +1985,12 @@ SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop2.cpp index 1982018182a4..51b424b470a3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +280,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +314,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +348,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +382,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +454,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +490,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +525,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +562,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +596,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +632,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +666,11 @@ SAndn2B32Sop2::SAndn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +702,11 @@ SAndn2B64Sop2::SAndn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +736,11 @@ SOrn2B32Sop2::SOrn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +772,11 @@ SOrn2B64Sop2::SOrn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +806,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +842,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -779,7 +876,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -811,7 +912,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +946,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +982,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1016,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1051,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1085,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1120,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1154,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1189,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1220,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1251,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1282,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1316,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1350,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1385,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1420,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1289,7 +1454,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1319,7 +1489,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1524,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1379,7 +1559,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1409,7 +1594,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1438,7 +1628,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1661,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1493,7 +1693,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1725,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1756,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopc.cpp index b220bf03cb13..85a5f949f420 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +554,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -517,7 +588,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopk.cpp index b030a14e8491..ec854ade67d3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -39,7 +42,11 @@ SVersionSopk::SVersionSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode) { +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_version", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,7 +68,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,7 +92,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -101,7 +116,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +140,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +164,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +188,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -181,7 +212,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -201,7 +236,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +260,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -241,7 +284,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +308,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +332,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -301,7 +356,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -322,7 +381,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -340,7 +403,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +424,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -374,7 +445,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +474,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +508,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +535,12 @@ SWaitcntVscntSopk::SWaitcntVscntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +558,12 @@ SWaitcntVmcntSopk::SWaitcntVmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +581,12 @@ SWaitcntExpcntSopk::SWaitcntExpcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_expcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -505,7 +604,12 @@ SWaitcntLgkmcntSopk::SWaitcntLgkmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_lgkmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -529,7 +633,12 @@ SSubvectorLoopBeginSopk::SSubvectorLoopBeginSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubvectorLoopBeginSopk(const MachineInst *opcode) { +DecodeResult decodeSSubvectorLoopBeginSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_subvector_loop_begin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -553,7 +662,12 @@ SSubvectorLoopEndSopk::SSubvectorLoopEndSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubvectorLoopEndSopk(const MachineInst *opcode) { +DecodeResult decodeSSubvectorLoopEndSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_subvector_loop_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopp.cpp index 52fb35a4806a..d507f20aa227 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -36,7 +39,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +60,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +82,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +106,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +136,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +166,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +196,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +226,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +256,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +280,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +299,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +338,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +357,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +376,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +398,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,7 +420,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -362,7 +440,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +457,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +476,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +496,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +517,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +537,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +577,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +597,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +616,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -509,7 +635,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -522,7 +653,11 @@ SCodeEndSopp::SCodeEndSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode) { +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_code_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +672,12 @@ SInstPrefetchSopp::SInstPrefetchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSInstPrefetchSopp(const MachineInst *opcode) { +DecodeResult decodeSInstPrefetchSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_inst_prefetch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +692,11 @@ SClauseSopp::SClauseSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode) { +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_clause", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -566,7 +710,11 @@ SWaitIdleSopp::SWaitIdleSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_idle", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -583,7 +731,12 @@ SWaitcntDepctrSopp::SWaitcntDepctrSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt_depctr", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -598,7 +751,11 @@ SRoundModeSopp::SRoundModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode) { +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_round_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +770,12 @@ SDenormModeSopp::SDenormModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode) { +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_denorm_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -631,7 +793,12 @@ STtracedataImmSopp::STtracedataImmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata_imm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vintrp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vintrp.cpp index 61c53f735f0f..8cc97d7a565b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vintrp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vintrp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vintrp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,12 @@ VInterpP1F32Vintrp::VInterpP1F32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1F32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpP1F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_p1_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +56,12 @@ VInterpP2F32Vintrp::VInterpP2F32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +83,12 @@ VInterpMovF32Vintrp::VInterpMovF32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpMovF32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpMovF32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_mov_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp index 7ba174a19384..fd363dababeb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,15 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_dpp" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +90,16 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_dpp" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,15 +116,24 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_dpp" + : "v_readfirstlane_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -130,15 +155,23 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_dpp" + : "v_cvt_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -159,15 +192,23 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_dpp" + : "v_cvt_f64_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -228,7 +269,17 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_dpp" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +340,17 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_dpp" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +411,17 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_dpp" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -411,7 +482,17 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_dpp" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +553,17 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_dpp" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -540,7 +631,17 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_dpp" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +702,18 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_rpi_i32_f32_dpp" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +774,18 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_flr_i32_f32_dpp" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -723,7 +846,18 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_dpp" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -745,15 +879,23 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_dpp" + : "v_cvt_f32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -774,15 +916,23 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_dpp" + : "v_cvt_f64_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -843,7 +993,18 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_dpp" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -904,7 +1065,18 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_dpp" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -965,7 +1137,18 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_dpp" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1026,7 +1209,18 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_dpp" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1048,15 +1242,23 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_U32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_dpp" + : "v_cvt_u32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1077,15 +1279,23 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_U32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_dpp" + : "v_cvt_f64_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1107,15 +1317,23 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_TRUNC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_dpp" + : "v_trunc_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1137,15 +1355,23 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CEIL_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_dpp" + : "v_ceil_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1167,15 +1393,23 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RNDNE_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_dpp" + : "v_rndne_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1197,15 +1431,23 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FLOOR_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_dpp" + : "v_floor_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1463,15 @@ VPipeflushVop1::VPipeflushVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_dpp" + : "v_pipeflush_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1281,7 +1531,17 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_dpp" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1341,7 +1601,17 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_dpp" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1671,16 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_dpp" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1461,7 +1740,17 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_dpp" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1521,7 +1810,17 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_dpp" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1581,7 +1880,16 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_dpp" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1641,7 +1949,16 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_dpp" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1701,7 +2018,16 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_dpp" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1762,7 +2088,18 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_dpp" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1822,7 +2159,16 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_dpp" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1844,15 +2190,23 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RCP_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_dpp" + : "v_rcp_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1874,15 +2228,23 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RSQ_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_dpp" + : "v_rsq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1942,7 +2304,16 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_dpp" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1964,15 +2335,23 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SQRT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_dpp" + : "v_sqrt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2411,16 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_dpp" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2092,7 +2480,16 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_dpp" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2152,7 +2549,16 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_dpp" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2212,7 +2618,17 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_bfrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_dpp" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2272,7 +2688,16 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ffbh_u32_dpp" + : "v_ffbh_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2332,7 +2757,16 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ffbl_b32_dpp" + : "v_ffbl_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2392,7 +2826,16 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ffbh_i32_dpp" + : "v_ffbh_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2414,15 +2857,24 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_dpp" + : "v_frexp_exp_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2444,15 +2896,24 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_dpp" + : "v_frexp_mant_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2474,15 +2935,23 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FRACT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_dpp" + : "v_fract_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2543,7 +3012,18 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_dpp" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2604,7 +3084,18 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_dpp" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2620,7 +3111,15 @@ VClrexcpVop1::VClrexcpVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clrexcp_dpp" + : "v_clrexcp_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2684,7 +3183,18 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movreld_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_dpp" + : "v_movreld_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2744,7 +3254,18 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrels_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_dpp" + : "v_movrels_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2804,7 +3325,18 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_dpp" + : "v_movrelsd_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2864,7 +3396,18 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_2_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_dpp" + : "v_movrelsd_2_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2926,7 +3469,17 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_dpp" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2994,7 +3547,17 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_dpp" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3062,7 +3625,17 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_dpp" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3130,7 +3703,17 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_dpp" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3197,7 +3780,16 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_dpp" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3264,7 +3856,16 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_dpp" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3331,7 +3932,16 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_dpp" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3398,7 +4008,16 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_dpp" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3465,7 +4084,16 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_dpp" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3533,7 +4161,18 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_dpp" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3601,7 +4240,18 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_dpp" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3668,7 +4318,17 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_dpp" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3735,7 +4395,16 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_dpp" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3802,7 +4471,17 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_dpp" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3869,7 +4548,17 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_dpp" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3936,7 +4625,17 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_dpp" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4003,7 +4702,16 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_dpp" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4070,7 +4778,16 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_dpp" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4137,7 +4854,18 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_dpp" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4199,7 +4927,18 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_dpp" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4267,7 +5006,18 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_dpp" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4292,15 +5042,23 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b32_dpp" + : "v_swap_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4321,16 +5079,25 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) src_operands_[2] = &m0; num_src_ = 3; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAPREL_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAPREL_B32 does not support SDWA", ""); m0.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swaprel_b32_dpp" + : "v_swaprel_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp index 3913a0d2f21f..2150e7c48d39 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -78,7 +77,18 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_dpp" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,12 +129,21 @@ VDot2cF32F16Vop2::VDot2cF32F16Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2c_f32_f16_dpp" + : "v_dot2c_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -190,7 +209,16 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_dpp" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +284,16 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_dpp" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +360,17 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_dpp" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,15 +394,24 @@ VMacLegacyF32Vop2::VMacLegacyF32Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAC_LEGACY_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_LEGACY_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacLegacyF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mac_legacy_f32_dpp" + : "v_mac_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAC_LEGACY_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_LEGACY_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -422,7 +478,18 @@ VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_legacy_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_legacy_f32_dpp" + : "v_mul_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +555,16 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_dpp" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -555,7 +631,17 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_dpp" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -622,7 +708,18 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_dpp" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -689,7 +786,17 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_dpp" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -756,7 +863,18 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_dpp" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -797,12 +915,21 @@ VDot4cI32I8Vop2::VDot4cI32I8Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT4C_I32_I8 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4c_i32_i8_dpp" + : "v_dot4c_i32_i8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT4C_I32_I8 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -868,7 +995,16 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f32_dpp" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1070,16 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f32_dpp" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1000,7 +1145,16 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_dpp" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1066,7 +1220,16 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_dpp" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1132,7 +1295,16 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_dpp" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1198,7 +1370,16 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_dpp" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1265,7 +1446,18 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_dpp" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1332,7 +1524,18 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_dpp" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1399,7 +1602,18 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_dpp" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1465,7 +1679,16 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_dpp" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1531,7 +1754,16 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_dpp" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1597,7 +1829,16 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_dpp" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1663,7 +1904,16 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_dpp" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1704,12 +1954,20 @@ VMacF32Vop2::VMacF32Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVMacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mac_f32_dpp" + : "v_mac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1737,16 +1995,24 @@ VMadmkF32Vop2::VMadmkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MADMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADMK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVMadmkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadmkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_madmk_f32_dpp" + : "v_madmk_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MADMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1774,16 +2040,24 @@ VMadakF32Vop2::VMadakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MADAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_MADAK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVMadakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMadakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_madak_f32_dpp" + : "v_madak_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MADAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_MADAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1850,7 +2124,17 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_dpp" + : "v_add_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1917,7 +2201,17 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_dpp" + : "v_sub_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1984,7 +2278,18 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_dpp" + : "v_subrev_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2057,7 +2362,18 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_dpp" + : "v_add_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2130,7 +2446,18 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_dpp" + : "v_sub_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2203,7 +2530,18 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_dpp" + : "v_subrev_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2244,12 +2582,20 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_dpp" + : "v_fmac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2277,16 +2623,24 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAMK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f32_dpp" + : "v_fmamk_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2314,16 +2668,24 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAAK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f32_dpp" + : "v_fmaak_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2390,7 +2752,18 @@ VCvtPkrtzF16F32Vop2::VCvtPkrtzF16F32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pkrtz_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pkrtz_f16_f32_dpp" + : "v_cvt_pkrtz_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2457,7 +2830,16 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_dpp" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2530,7 +2912,16 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_dpp" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2604,7 +2995,17 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_dpp" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2677,7 +3078,16 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_dpp" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2725,12 +3135,20 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_dpp" + : "v_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2766,16 +3184,24 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAMK_F16 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f16_dpp" + : "v_fmamk_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2811,16 +3237,24 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAAK_F16 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f16_dpp" + : "v_fmaak_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2893,7 +3327,16 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f16_dpp" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2966,7 +3409,16 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f16_dpp" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3039,7 +3491,17 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ldexp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_dpp" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3086,12 +3548,20 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PK_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fmac_f16_dpp" + : "v_pk_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3.cpp index 52c291d849f0..a05334ec4d0f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -30,7 +29,12 @@ VInterpP1F32Vop3::VInterpP1F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +57,12 @@ VInterpP2F32Vop3::VInterpP2F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +84,12 @@ VInterpMovF32Vop3::VInterpMovF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpMovF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpMovF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_mov_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -88,7 +102,11 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -109,7 +127,11 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +148,12 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readfirstlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +175,11 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +200,11 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,7 +225,11 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -211,7 +250,11 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +275,11 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +300,11 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -274,7 +325,11 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -302,7 +357,11 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +382,12 @@ VCvtRpiI32F32Vop3::VCvtRpiI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_rpi_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +408,12 @@ VCvtFlrI32F32Vop3::VCvtFlrI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_flr_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +434,12 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_off_f32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +461,11 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +486,11 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -429,7 +511,12 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -450,7 +537,12 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -471,7 +563,12 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -492,7 +589,12 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -514,7 +616,11 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -535,7 +641,11 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +667,11 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -579,7 +693,11 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +719,11 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +745,11 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -636,7 +762,11 @@ VPipeflushVop3::VPipeflushVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pipeflush", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +787,11 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +812,11 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +837,11 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -720,7 +862,11 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +887,11 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,7 +912,11 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -783,7 +937,11 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +962,11 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -825,7 +987,12 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_iflag_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -846,7 +1013,11 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -868,7 +1039,11 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1065,11 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -911,7 +1090,11 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -933,7 +1116,11 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -954,7 +1141,11 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -975,7 +1166,11 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -996,7 +1191,11 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1216,11 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1038,7 +1241,11 @@ VFfbhU32Vop3::VFfbhU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1059,7 +1266,11 @@ VFfblB32Vop3::VFfblB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1080,7 +1291,11 @@ VFfbhI32Vop3::VFfbhI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1102,7 +1317,12 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1344,12 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1146,7 +1371,11 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1396,12 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1188,7 +1422,12 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1201,7 +1440,11 @@ VClrexcpVop3::VClrexcpVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_clrexcp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1225,7 +1468,12 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1245,7 +1493,12 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1265,7 +1518,12 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movrelsd_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1285,7 +1543,12 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1307,7 +1570,11 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1335,7 +1602,11 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1363,7 +1634,11 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1391,7 +1666,11 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1698,11 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1730,11 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1475,7 +1762,11 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,7 +1794,11 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1531,7 +1826,11 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1559,7 +1858,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1587,7 +1891,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1615,7 +1924,11 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1643,7 +1956,11 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1671,7 +1988,11 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +2020,11 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1727,7 +2052,11 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2084,11 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1783,7 +2116,11 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1810,7 +2147,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sat_pk_u8_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1832,7 +2174,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1860,7 +2207,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1895,7 +2247,12 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cndmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1923,7 +2280,12 @@ VDot2cF32F16Vop3::VDot2cF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot2c_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1950,7 +2312,11 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1977,7 +2343,11 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2004,7 +2374,11 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2406,12 @@ VMacLegacyF32Vop3::VMacLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2059,7 +2438,12 @@ VMulLegacyF32Vop3::VMulLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2086,7 +2470,11 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2113,7 +2501,11 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2140,7 +2532,12 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2167,7 +2564,11 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2194,7 +2595,12 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2222,7 +2628,12 @@ VDot4cI32I8Vop3::VDot4cI32I8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_dot4c_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2249,7 +2660,11 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2276,7 +2691,11 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2303,7 +2722,11 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2330,7 +2753,11 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2357,7 +2784,11 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2384,7 +2815,11 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2411,7 +2846,12 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2438,7 +2878,12 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2465,7 +2910,12 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2492,7 +2942,11 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2519,7 +2973,11 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2546,7 +3004,11 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2573,7 +3035,11 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2601,7 +3067,11 @@ VMacF32Vop3::VMacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2628,7 +3098,11 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2655,7 +3129,11 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2682,7 +3160,12 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_nc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2710,7 +3193,11 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2737,7 +3224,12 @@ VCvtPkrtzF16F32Vop3::VCvtPkrtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkrtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2766,7 +3258,11 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2801,7 +3297,11 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2836,7 +3336,11 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2871,7 +3375,11 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2907,7 +3415,11 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2942,7 +3454,11 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2977,7 +3493,11 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3012,7 +3532,11 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3051,7 +3575,12 @@ VMadLegacyF32Vop3::VMadLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3084,7 +3613,11 @@ VMadF32Vop3::VMadF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3117,7 +3650,11 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3150,7 +3687,11 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3183,7 +3724,11 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubeid_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3216,7 +3761,11 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubesc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3249,7 +3798,11 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubetc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3282,7 +3835,11 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubema_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3315,7 +3872,11 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3348,7 +3909,11 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3381,7 +3946,11 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3414,7 +3983,11 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3450,7 +4023,11 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3483,7 +4060,11 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lerp_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3516,7 +4097,12 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbit_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3549,7 +4135,12 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbyte_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3582,7 +4173,11 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mullit_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3615,7 +4210,11 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3648,7 +4247,11 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3681,7 +4284,11 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3714,7 +4321,11 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3747,7 +4358,11 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3780,7 +4395,11 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3813,7 +4432,11 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3846,7 +4469,11 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3879,7 +4506,11 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3912,7 +4543,11 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3945,7 +4580,11 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3978,7 +4617,11 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4011,7 +4654,11 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4044,7 +4691,12 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4077,7 +4729,12 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4113,7 +4770,12 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4142,7 +4804,11 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4171,7 +4837,11 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4200,7 +4870,11 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4229,7 +4903,11 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4257,7 +4935,11 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4284,7 +4966,11 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4311,7 +4997,11 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4338,7 +5028,11 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4374,7 +5068,12 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4413,7 +5112,12 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4446,7 +5150,11 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_msad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4481,7 +5189,12 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_qsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4516,7 +5229,12 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4544,7 +5262,12 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trig_preop_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4574,7 +5297,12 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4607,7 +5335,11 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4635,7 +5367,12 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4663,7 +5400,12 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4691,7 +5433,12 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4720,7 +5467,11 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4755,7 +5506,11 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4790,7 +5545,11 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4825,7 +5584,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4860,7 +5624,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4895,7 +5664,11 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4930,7 +5703,11 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4965,7 +5742,11 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5000,7 +5781,11 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5035,7 +5820,11 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5070,7 +5859,11 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5105,7 +5898,12 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pack_b32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5134,7 +5932,12 @@ VCvtPknormI16F16Vop3::VCvtPknormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5163,7 +5966,12 @@ VCvtPknormU16F16Vop3::VCvtPknormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5192,7 +6000,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5234,7 +6047,11 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5259,7 +6076,12 @@ VInterpP1llF16Vop3::VInterpP1llF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1llF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1llF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1ll_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5280,7 +6102,12 @@ VInterpP1lvF16Vop3::VInterpP1lvF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1lvF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1lvF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1lv_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5313,7 +6140,11 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_perm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5346,7 +6177,11 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5379,7 +6214,12 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5412,7 +6252,12 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_lshl_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5448,7 +6293,11 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5490,7 +6339,11 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5532,7 +6385,11 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5574,7 +6431,11 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5616,7 +6477,11 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5658,7 +6523,11 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5700,7 +6569,11 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5742,7 +6615,11 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5784,7 +6661,11 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5826,7 +6707,11 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5853,7 +6738,12 @@ VInterpP2F16Vop3::VInterpP2F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5895,7 +6785,11 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5937,7 +6831,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5962,7 +6861,12 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5986,7 +6890,12 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_writelane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6013,7 +6922,11 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6040,7 +6953,11 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6067,7 +6984,12 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bcnt_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6094,7 +7016,12 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_lo_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6121,7 +7048,12 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_hi_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6148,7 +7080,12 @@ VCvtPknormI16F32Vop3::VCvtPknormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6175,7 +7112,12 @@ VCvtPknormU16F32Vop3::VCvtPknormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6202,7 +7144,12 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u16_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6229,7 +7176,12 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_i16_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6262,7 +7214,11 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6295,7 +7251,11 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6328,7 +7288,11 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6361,7 +7325,11 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6396,7 +7364,11 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6431,7 +7403,11 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6458,7 +7434,11 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6487,7 +7467,12 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_permlane16_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6516,7 +7501,12 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_permlanex16_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6543,7 +7533,11 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6570,7 +7564,11 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6597,7 +7595,11 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6624,7 +7626,11 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6651,7 +7657,11 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6678,7 +7688,11 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6705,7 +7719,11 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6732,7 +7750,11 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6759,7 +7781,11 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6786,7 +7812,11 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6813,7 +7843,11 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6840,7 +7874,11 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6867,7 +7905,11 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6894,7 +7936,11 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6921,7 +7967,11 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6948,7 +7998,11 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6975,7 +8029,11 @@ VCmpTruF32Vop3::VCmpTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7006,7 +8064,11 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7037,7 +8099,11 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7068,7 +8134,11 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7099,7 +8169,11 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7130,7 +8204,11 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7161,7 +8239,11 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7192,7 +8274,11 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7223,7 +8309,11 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7254,7 +8344,11 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7285,7 +8379,12 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7316,7 +8415,12 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7347,7 +8451,12 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7378,7 +8487,12 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7409,7 +8523,12 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7440,7 +8559,12 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7471,7 +8595,12 @@ VCmpxTruF32Vop3::VCmpxTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7500,7 +8629,11 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7529,7 +8662,11 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7558,7 +8695,11 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7587,7 +8728,11 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7616,7 +8761,11 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7645,7 +8794,11 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7674,7 +8827,11 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7703,7 +8860,11 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7732,7 +8893,11 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7761,7 +8926,11 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7790,7 +8959,11 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7819,7 +8992,11 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7848,7 +9025,11 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7877,7 +9058,11 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7906,7 +9091,11 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7935,7 +9124,11 @@ VCmpTruF64Vop3::VCmpTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7968,7 +9161,11 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8001,7 +9198,11 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8034,7 +9235,11 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8067,7 +9272,11 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8100,7 +9309,11 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8133,7 +9346,11 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8166,7 +9383,11 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8199,7 +9420,11 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8232,7 +9457,11 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8265,7 +9494,12 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8298,7 +9532,12 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8331,7 +9570,12 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8364,7 +9608,12 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8397,7 +9646,12 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8430,7 +9684,12 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8463,7 +9722,12 @@ VCmpxTruF64Vop3::VCmpxTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8490,7 +9754,11 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8517,7 +9785,11 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8544,7 +9816,11 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8571,7 +9847,11 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8598,7 +9878,11 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8625,7 +9909,11 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8652,7 +9940,11 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8679,7 +9971,11 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8706,7 +10002,12 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8735,7 +10036,11 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8764,7 +10069,11 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8793,7 +10102,11 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8822,7 +10135,11 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8851,7 +10168,11 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8880,7 +10201,11 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8909,7 +10234,12 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8940,7 +10270,11 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8971,7 +10305,11 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9002,7 +10340,11 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9033,7 +10375,11 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9064,7 +10410,11 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9095,7 +10445,11 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9126,7 +10480,11 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9157,7 +10515,11 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9188,7 +10550,12 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9221,7 +10588,11 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9254,7 +10625,11 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9287,7 +10662,11 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9320,7 +10699,11 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9353,7 +10736,11 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9386,7 +10773,11 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9419,7 +10810,12 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9448,7 +10844,11 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9477,7 +10877,11 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9506,7 +10910,11 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9535,7 +10943,11 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9564,7 +10976,11 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9593,7 +11009,11 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9622,7 +11042,11 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9651,7 +11075,11 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9679,7 +11107,12 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9708,7 +11141,11 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9737,7 +11174,11 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9766,7 +11207,11 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9795,7 +11240,11 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9824,7 +11273,11 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9853,7 +11306,11 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9886,7 +11343,11 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9919,7 +11380,11 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9952,7 +11417,11 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9985,7 +11454,11 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10018,7 +11491,11 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10051,7 +11528,11 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10084,7 +11565,11 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10117,7 +11602,11 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10149,7 +11638,12 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10182,7 +11676,11 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10215,7 +11713,11 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10248,7 +11750,11 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10281,7 +11787,11 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10314,7 +11824,11 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10347,7 +11861,11 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10374,7 +11892,11 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10401,7 +11923,11 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10428,7 +11954,11 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10455,7 +11985,11 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10482,7 +12016,11 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10509,7 +12047,11 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10536,7 +12078,11 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10563,7 +12109,11 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10592,7 +12142,11 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10621,7 +12175,11 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10650,7 +12208,11 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10679,7 +12241,11 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10708,7 +12274,11 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10737,7 +12307,11 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10766,7 +12340,11 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10795,7 +12373,11 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10826,7 +12408,11 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10857,7 +12443,11 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10888,7 +12478,11 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10919,7 +12513,11 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10950,7 +12548,11 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10981,7 +12583,11 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11012,7 +12618,11 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11043,7 +12653,11 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11076,7 +12690,11 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11109,7 +12727,11 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11142,7 +12764,11 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11175,7 +12801,11 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11208,7 +12838,11 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11241,7 +12875,11 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11274,7 +12912,11 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11307,7 +12949,11 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11336,7 +12982,11 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11365,7 +13015,11 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11394,7 +13048,11 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11423,7 +13081,11 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11452,7 +13114,11 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11481,7 +13147,11 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11510,7 +13180,11 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11539,7 +13213,11 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11568,7 +13246,11 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11597,7 +13279,11 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11626,7 +13312,11 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11655,7 +13345,11 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11684,7 +13378,11 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11713,7 +13411,11 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11742,7 +13444,11 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11771,7 +13477,11 @@ VCmpTruF16Vop3::VCmpTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11804,7 +13514,11 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11837,7 +13551,11 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11870,7 +13588,11 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11903,7 +13625,11 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11936,7 +13662,11 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11969,7 +13699,11 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12002,7 +13736,11 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12035,7 +13773,11 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12068,7 +13810,11 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12101,7 +13847,12 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12134,7 +13885,12 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12167,7 +13923,12 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12200,7 +13961,12 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12233,7 +13999,12 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12266,7 +14037,12 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12299,7 +14075,12 @@ VCmpxTruF16Vop3::VCmpxTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12330,7 +14111,12 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12361,7 +14147,12 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12392,7 +14183,12 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12427,7 +14223,12 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12468,7 +14269,12 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12505,7 +14311,12 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_u64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12542,7 +14353,12 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_i64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12571,7 +14387,12 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12600,7 +14421,12 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12629,7 +14455,12 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3p.cpp index 29bb375e0504..52d060ca8985 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,7 +40,11 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -68,7 +71,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -95,7 +103,11 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +134,11 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -149,7 +165,12 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -176,7 +197,12 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +229,12 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -230,7 +261,11 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -257,7 +292,11 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +329,11 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -317,7 +360,11 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +391,11 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +422,11 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +453,11 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -431,7 +490,11 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -458,7 +521,11 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +552,11 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +583,11 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -539,7 +614,11 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +651,12 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -605,7 +689,12 @@ VDot2I32I16Vop3p::VDot2I32I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +727,12 @@ VDot2U32U16Vop3p::VDot2U32U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -671,7 +765,12 @@ VDot4I32I8Vop3p::VDot4I32I8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +803,12 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -737,7 +841,12 @@ VDot8I32I4Vop3p::VDot8I32I4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +879,12 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_u32_u4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -803,7 +917,12 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_fma_mix_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -837,7 +956,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_fma_mixlo_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1001,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_fma_mixhi_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp index dd47ddaf752e..19a003ec65ed 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -30,9 +29,6 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -60,7 +56,18 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -83,9 +90,6 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -113,7 +117,18 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -136,9 +151,6 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -166,7 +178,18 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -189,9 +212,6 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -219,7 +239,18 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -242,9 +273,6 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -272,7 +300,18 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -295,9 +334,6 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -325,7 +361,18 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -348,9 +395,6 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -378,7 +422,18 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -400,9 +455,6 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -430,7 +482,18 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -452,9 +515,6 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -482,7 +542,18 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -505,9 +576,6 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -535,7 +603,18 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -558,9 +637,6 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -588,7 +664,18 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -611,9 +698,6 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -641,7 +725,18 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -664,9 +759,6 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -694,7 +786,18 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -717,9 +820,6 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -747,7 +847,18 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -770,9 +881,6 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -800,7 +908,18 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -823,9 +942,6 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -853,7 +969,18 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -878,9 +1005,6 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -910,7 +1034,18 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -935,9 +1070,6 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -967,7 +1099,18 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -992,9 +1135,6 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1024,7 +1164,18 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1049,9 +1200,6 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1081,7 +1229,18 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1106,9 +1265,6 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1138,7 +1294,18 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1163,9 +1330,6 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1195,7 +1359,18 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1220,9 +1395,6 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1252,7 +1424,18 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1277,9 +1460,6 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1309,7 +1489,18 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1334,9 +1525,6 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1366,7 +1554,18 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1391,9 +1590,6 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1423,7 +1619,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1448,9 +1656,6 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1480,7 +1685,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1505,9 +1722,6 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1537,7 +1751,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1562,9 +1788,6 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1594,7 +1817,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1619,9 +1854,6 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1651,7 +1883,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1676,9 +1920,6 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1708,7 +1949,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1733,9 +1986,6 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1765,7 +2015,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1786,16 +2048,21 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1816,16 +2083,21 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1846,16 +2118,21 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1876,16 +2153,21 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1906,16 +2188,21 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1936,16 +2223,21 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1966,16 +2258,21 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1996,16 +2293,21 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2026,16 +2328,21 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2056,16 +2363,21 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2086,16 +2398,21 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2116,16 +2433,21 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2146,16 +2468,21 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2176,16 +2503,21 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2206,16 +2538,21 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2236,16 +2573,21 @@ VCmpTruF64Vopc::VCmpTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2268,18 +2610,23 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2302,18 +2649,23 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2336,18 +2688,23 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2370,18 +2727,23 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2404,18 +2766,23 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2438,18 +2805,23 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LG_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2472,18 +2844,23 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2506,18 +2883,23 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_O_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2540,18 +2922,23 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_U_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2574,18 +2961,24 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2608,18 +3001,24 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2642,18 +3041,24 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2676,18 +3081,24 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2710,18 +3121,24 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2744,18 +3161,24 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2778,18 +3201,24 @@ VCmpxTruF64Vopc::VCmpxTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2811,9 +3240,6 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2841,7 +3267,18 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2864,9 +3301,6 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2894,7 +3328,18 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2917,9 +3362,6 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2947,7 +3389,18 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2970,9 +3423,6 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3000,7 +3450,18 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3023,9 +3484,6 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3053,7 +3511,18 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3076,9 +3545,6 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3106,7 +3572,18 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3129,9 +3606,6 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3159,7 +3633,18 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3181,9 +3666,6 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3211,7 +3693,18 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3234,9 +3727,6 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3264,7 +3754,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3288,9 +3790,6 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3318,7 +3817,18 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3342,9 +3852,6 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3372,7 +3879,18 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3396,9 +3914,6 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3426,7 +3941,18 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3450,9 +3976,6 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3480,7 +4003,18 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3504,9 +4038,6 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3534,7 +4065,18 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3558,9 +4100,6 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3588,7 +4127,18 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3612,9 +4162,6 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3642,7 +4189,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3667,9 +4226,6 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3699,7 +4255,18 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3724,9 +4291,6 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3756,7 +4320,18 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3781,9 +4356,6 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3813,7 +4385,18 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3838,9 +4421,6 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3870,7 +4450,18 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3895,9 +4486,6 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3927,7 +4515,18 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3952,9 +4551,6 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3984,7 +4580,18 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4009,9 +4616,6 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4041,7 +4645,18 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4066,9 +4681,6 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4098,7 +4710,18 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4123,9 +4746,6 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4155,7 +4775,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4181,9 +4813,6 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4213,7 +4842,18 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4239,9 +4879,6 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4271,7 +4908,18 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4297,9 +4945,6 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4329,7 +4974,18 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4355,9 +5011,6 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4387,7 +5040,18 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4413,9 +5077,6 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4445,7 +5106,18 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4471,9 +5143,6 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4503,7 +5172,18 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4529,9 +5209,6 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4561,7 +5238,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4582,16 +5271,21 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4612,16 +5306,21 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4642,16 +5341,21 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4672,16 +5376,21 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4702,16 +5411,21 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4732,16 +5446,21 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4762,16 +5481,21 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4792,16 +5516,21 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4822,16 +5551,22 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4855,9 +5590,6 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4885,7 +5617,18 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4909,9 +5652,6 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4939,7 +5679,18 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4963,9 +5714,6 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4993,7 +5741,18 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5017,9 +5776,6 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5047,7 +5803,18 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5071,9 +5838,6 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5101,7 +5865,18 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5125,9 +5900,6 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5155,7 +5927,18 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5178,18 +5961,23 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5212,18 +6000,23 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5246,18 +6039,23 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5280,18 +6078,23 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5314,18 +6117,23 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5348,18 +6156,23 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5382,18 +6195,23 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5416,18 +6234,23 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5450,18 +6273,24 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5487,9 +6316,6 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5519,7 +6345,18 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5545,9 +6382,6 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5577,7 +6411,18 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5603,9 +6448,6 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5635,7 +6477,18 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5661,9 +6514,6 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5693,7 +6543,18 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5719,9 +6580,6 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5751,7 +6609,18 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5777,9 +6646,6 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5809,7 +6675,18 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5831,9 +6708,6 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5861,7 +6735,18 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5884,9 +6769,6 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5914,7 +6796,18 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5937,9 +6830,6 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5967,7 +6857,18 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5990,9 +6891,6 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6020,7 +6918,18 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6043,9 +6952,6 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6073,7 +6979,18 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6096,9 +7013,6 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6126,7 +7040,18 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6149,9 +7074,6 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6179,7 +7101,18 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6201,9 +7134,6 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6231,7 +7161,18 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6254,9 +7195,6 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6284,7 +7222,18 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6308,9 +7257,6 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6338,7 +7284,18 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6362,9 +7319,6 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6392,7 +7346,18 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6416,9 +7381,6 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6446,7 +7408,18 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6470,9 +7443,6 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6500,7 +7470,18 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6524,9 +7505,6 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6554,7 +7532,18 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6578,9 +7567,6 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6608,7 +7594,18 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6631,9 +7628,6 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6661,7 +7655,18 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6686,9 +7691,6 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6718,7 +7720,18 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6743,9 +7756,6 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6775,7 +7785,18 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6800,9 +7821,6 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6832,7 +7850,18 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6857,9 +7886,6 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6889,7 +7915,18 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6914,9 +7951,6 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6946,7 +7980,18 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6971,9 +8016,6 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7003,7 +8045,18 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7028,9 +8081,6 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7060,7 +8110,18 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7085,9 +8146,6 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7117,7 +8175,18 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7143,9 +8212,6 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7175,7 +8241,18 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7201,9 +8278,6 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7233,7 +8307,18 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7259,9 +8344,6 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7291,7 +8373,18 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7317,9 +8410,6 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7349,7 +8439,18 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7375,9 +8476,6 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7407,7 +8505,18 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7433,9 +8542,6 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7465,7 +8571,18 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7491,9 +8608,6 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7523,7 +8637,18 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7549,9 +8674,6 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7581,7 +8703,18 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7602,16 +8735,21 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7632,16 +8770,21 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7662,16 +8805,21 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7692,16 +8840,21 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7722,16 +8875,21 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7752,16 +8910,21 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7782,16 +8945,21 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7812,16 +8980,21 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7844,9 +9017,6 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7874,7 +9044,18 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7898,9 +9079,6 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7928,7 +9106,18 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7952,9 +9141,6 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7982,7 +9168,18 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8006,9 +9203,6 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8036,7 +9230,18 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8060,9 +9265,6 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8090,7 +9292,18 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8114,9 +9327,6 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8144,7 +9354,18 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8168,9 +9389,6 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8198,7 +9416,18 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8222,9 +9451,6 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8252,7 +9478,18 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8275,18 +9512,23 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8309,18 +9551,23 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8343,18 +9590,23 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8377,18 +9629,23 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8411,18 +9668,23 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8445,18 +9707,23 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8479,18 +9746,23 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8513,18 +9785,23 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8550,9 +9827,6 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8582,7 +9856,18 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8608,9 +9893,6 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8640,7 +9922,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8666,9 +9960,6 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8698,7 +9989,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8724,9 +10027,6 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8756,7 +10056,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8782,9 +10094,6 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8814,7 +10123,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8840,9 +10161,6 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8872,7 +10190,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8898,9 +10228,6 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8930,7 +10257,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8956,9 +10295,6 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8988,7 +10324,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.cpp index e47e2c58550b..ccc52bf30c67 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3p.h" -#include "util/except.h" #include #include #include @@ -15,1415 +14,1908 @@ namespace rocjitsu { namespace rdna2 { namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCsubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeExpExp(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicFminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicFcmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicFmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicFminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode); -std::unique_ptr decodeImageBvh64IntersectRayMimg(const MachineInst *opcode); -std::unique_ptr decodeImageBvhIntersectRayMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4COMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather8hPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCCdOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCdOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipBy2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipBy4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePck2Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePck4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSInstPrefetchSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubvectorLoopBeginSopk(const MachineInst *opcode); -std::unique_ptr decodeSSubvectorLoopEndSopk(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode); -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacLegacyF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpMovF32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpMovF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1F32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1llF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP1lvF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vintrp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCsubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicFminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicFcmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicFmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicFminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvh64IntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvhIntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4COMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather8hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSInstPrefetchSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubvectorLoopBeginSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubvectorLoopEndSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpMovF32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpMovF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1llF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP1lvF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeVintrp(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMimg(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1441,88 +1933,102 @@ struct DecoderImpl { static const std::array sub_decode_smem; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVintrp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vintrp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vintrp[op.op](opcode); + return sub_decode_vintrp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMimg(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mimg::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mimg[op.op](opcode); + return sub_decode_mimg[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h index 0956717cd90b..21d2acb0d7df 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA2_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace rdna2 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 3; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace rdna2 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/ds.cpp index 31df9559a7ee..3f48a824cbc3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/ds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/ds.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +84,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +111,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +138,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +165,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +219,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +246,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +273,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +300,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +327,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -309,7 +356,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +381,11 @@ DsWriteB32Ds::DsWriteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +408,11 @@ DsWrite2B32Ds::DsWrite2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +435,12 @@ DsWrite2st64B32Ds::DsWrite2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +465,11 @@ DsCmpstB32Ds::DsCmpstB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -426,7 +494,11 @@ DsCmpstF32Ds::DsCmpstF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -449,7 +521,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +548,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +565,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +592,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +609,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +629,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -549,7 +646,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +665,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -577,7 +682,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -592,7 +701,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +726,11 @@ DsWriteB8Ds::DsWriteB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -634,7 +751,11 @@ DsWriteB16Ds::DsWriteB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +780,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +809,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -709,7 +838,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -734,7 +867,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -759,7 +896,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -784,7 +925,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +954,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +983,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1012,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -884,7 +1041,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -909,7 +1070,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1099,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -961,7 +1130,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -986,7 +1160,12 @@ DsWrxchgRtnB32Ds::DsWrxchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1013,7 +1192,12 @@ DsWrxchg2RtnB32Ds::DsWrxchg2RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1224,12 @@ DsWrxchg2st64RtnB32Ds::DsWrxchg2st64RtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1256,12 @@ DsCmpstRtnB32Ds::DsCmpstRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1094,7 +1288,12 @@ DsCmpstRtnF32Ds::DsCmpstRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1119,7 +1318,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1347,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1170,7 +1377,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,7 +1398,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1423,11 @@ DsReadB32Ds::DsReadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1229,7 +1448,11 @@ DsRead2B32Ds::DsRead2B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1250,7 +1473,12 @@ DsRead2st64B32Ds::DsRead2st64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1499,11 @@ DsReadI8Ds::DsReadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1298,7 +1530,11 @@ DsReadU8Ds::DsReadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1325,7 +1561,11 @@ DsReadI16Ds::DsReadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1592,11 @@ DsReadU16Ds::DsReadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1379,7 +1623,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1400,7 +1648,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1420,7 +1672,12 @@ DsOrderedCountDs::DsOrderedCountDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode) { +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_ordered_count", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1443,7 +1700,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1727,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1489,7 +1754,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1781,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1535,7 +1808,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1558,7 +1835,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1581,7 +1862,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1889,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1627,7 +1916,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1650,7 +1943,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +1970,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1696,7 +1997,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1721,7 +2026,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1742,7 +2051,11 @@ DsWriteB64Ds::DsWriteB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1765,7 +2078,11 @@ DsWrite2B64Ds::DsWrite2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1788,7 +2105,12 @@ DsWrite2st64B64Ds::DsWrite2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrite2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrite2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1813,7 +2135,11 @@ DsCmpstB64Ds::DsCmpstB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1838,7 +2164,11 @@ DsCmpstF64Ds::DsCmpstF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1861,7 +2191,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1884,7 +2218,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1909,7 +2247,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1934,7 +2276,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1959,7 +2305,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1984,7 +2334,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2009,7 +2363,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2034,7 +2392,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2059,7 +2421,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2084,7 +2450,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2109,7 +2479,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2134,7 +2508,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2159,7 +2537,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2184,7 +2566,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2209,7 +2595,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2236,7 +2626,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2261,7 +2656,12 @@ DsWrxchgRtnB64Ds::DsWrxchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2288,7 +2688,12 @@ DsWrxchg2RtnB64Ds::DsWrxchg2RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2315,7 +2720,12 @@ DsWrxchg2st64RtnB64Ds::DsWrxchg2st64RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrxchg2st64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrxchg2st64_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2342,7 +2752,12 @@ DsCmpstRtnB64Ds::DsCmpstRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2369,7 +2784,12 @@ DsCmpstRtnF64Ds::DsCmpstRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpst_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2394,7 +2814,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2419,7 +2843,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2440,7 +2868,11 @@ DsReadB64Ds::DsReadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2461,7 +2893,11 @@ DsRead2B64Ds::DsRead2B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2B64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2482,7 +2918,12 @@ DsRead2st64B64Ds::DsRead2st64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRead2st64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRead2st64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read2st64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2507,7 +2948,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2528,7 +2974,12 @@ DsWriteB8D16HiDs::DsWriteB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2549,7 +3000,12 @@ DsWriteB16D16HiDs::DsWriteB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsWriteB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2570,7 +3026,11 @@ DsReadU8D16Ds::DsReadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2597,7 +3057,12 @@ DsReadU8D16HiDs::DsReadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2624,7 +3089,11 @@ DsReadI8D16Ds::DsReadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2651,7 +3120,12 @@ DsReadI8D16HiDs::DsReadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2678,7 +3152,11 @@ DsReadU16D16Ds::DsReadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2705,7 +3183,12 @@ DsReadU16D16HiDs::DsReadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsReadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2732,7 +3215,12 @@ DsWriteAddtidB32Ds::DsWriteAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3241,12 @@ DsReadAddtidB32Ds::DsReadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2772,7 +3265,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2791,7 +3288,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2812,7 +3314,11 @@ DsWriteB96Ds::DsWriteB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2833,7 +3339,11 @@ DsWriteB128Ds::DsWriteB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWriteB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsWriteB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_write_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2854,7 +3364,11 @@ DsReadB96Ds::DsReadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2875,7 +3389,11 @@ DsReadB128Ds::DsReadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsReadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsReadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_read_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h index 0e60f5d4701a..783fd483d328 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/rdna2/isa.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/exp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/exp.cpp index b4d92dd598e7..4e027fe2de49 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/exp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/exp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/exp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -33,7 +32,11 @@ ExpExp::ExpExp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeExpExp(const MachineInst *opcode) { +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Exp::validate_encoding("exp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/flat.cpp index 8476f258f048..8f10f8d28cb2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/flat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/flat.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -40,7 +39,12 @@ FlatLoadUbyteFlat::FlatLoadUbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +76,12 @@ FlatLoadSbyteFlat::FlatLoadSbyteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -104,7 +113,12 @@ FlatLoadUshortFlat::FlatLoadUshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -136,7 +150,12 @@ FlatLoadSshortFlat::FlatLoadSshortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSshortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSshortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +187,12 @@ FlatLoadDwordFlat::FlatLoadDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -200,7 +224,12 @@ FlatLoadDwordx2Flat::FlatLoadDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +261,12 @@ FlatLoadDwordx4Flat::FlatLoadDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +298,12 @@ FlatLoadDwordx3Flat::FlatLoadDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +335,12 @@ FlatStoreByteFlat::FlatStoreByteFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -328,7 +372,12 @@ FlatStoreByteD16HiFlat::FlatStoreByteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreByteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreByteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +409,12 @@ FlatStoreShortFlat::FlatStoreShortFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -392,7 +446,12 @@ FlatStoreShortD16HiFlat::FlatStoreShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +483,12 @@ FlatStoreDwordFlat::FlatStoreDwordFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordFlat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +520,12 @@ FlatStoreDwordx2Flat::FlatStoreDwordx2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +557,12 @@ FlatStoreDwordx4Flat::FlatStoreDwordx4Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx4Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx4Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +594,12 @@ FlatStoreDwordx3Flat::FlatStoreDwordx3Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreDwordx3Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreDwordx3Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +631,12 @@ FlatLoadUbyteD16Flat::FlatLoadUbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -591,7 +675,12 @@ FlatLoadUbyteD16HiFlat::FlatLoadUbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadUbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -630,7 +719,12 @@ FlatLoadSbyteD16Flat::FlatLoadSbyteD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -669,7 +763,12 @@ FlatLoadSbyteD16HiFlat::FlatLoadSbyteD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadSbyteD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +807,12 @@ FlatLoadShortD16Flat::FlatLoadShortD16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -747,7 +851,12 @@ FlatLoadShortD16HiFlat::FlatLoadShortD16HiFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadShortD16HiFlat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadShortD16HiFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -789,7 +898,12 @@ FlatAtomicSwapFlat::FlatAtomicSwapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -824,7 +938,12 @@ FlatAtomicCmpswapFlat::FlatAtomicCmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +978,12 @@ FlatAtomicAddFlat::FlatAtomicAddFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1018,12 @@ FlatAtomicSubFlat::FlatAtomicSubFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -929,7 +1058,12 @@ FlatAtomicSminFlat::FlatAtomicSminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1098,12 @@ FlatAtomicUminFlat::FlatAtomicUminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -999,7 +1138,12 @@ FlatAtomicSmaxFlat::FlatAtomicSmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1034,7 +1178,12 @@ FlatAtomicUmaxFlat::FlatAtomicUmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1069,7 +1218,12 @@ FlatAtomicAndFlat::FlatAtomicAndFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1104,7 +1258,12 @@ FlatAtomicOrFlat::FlatAtomicOrFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1139,7 +1298,12 @@ FlatAtomicXorFlat::FlatAtomicXorFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1174,7 +1338,12 @@ FlatAtomicIncFlat::FlatAtomicIncFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1209,7 +1378,12 @@ FlatAtomicDecFlat::FlatAtomicDecFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1244,7 +1418,12 @@ FlatAtomicFcmpswapFlat::FlatAtomicFcmpswapFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFcmpswapFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fcmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1279,7 +1458,12 @@ FlatAtomicFminFlat::FlatAtomicFminFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFminFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFminFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1314,7 +1498,12 @@ FlatAtomicFmaxFlat::FlatAtomicFmaxFlat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFmaxFlat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFmaxFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1538,12 @@ FlatAtomicSwapX2Flat::FlatAtomicSwapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1384,7 +1578,12 @@ FlatAtomicCmpswapX2Flat::FlatAtomicCmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1618,12 @@ FlatAtomicAddX2Flat::FlatAtomicAddX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1454,7 +1658,12 @@ FlatAtomicSubX2Flat::FlatAtomicSubX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1489,7 +1698,12 @@ FlatAtomicSminX2Flat::FlatAtomicSminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1524,7 +1738,12 @@ FlatAtomicUminX2Flat::FlatAtomicUminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1559,7 +1778,12 @@ FlatAtomicSmaxX2Flat::FlatAtomicSmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1594,7 +1818,12 @@ FlatAtomicUmaxX2Flat::FlatAtomicUmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicUmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1629,7 +1858,12 @@ FlatAtomicAndX2Flat::FlatAtomicAndX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1664,7 +1898,12 @@ FlatAtomicOrX2Flat::FlatAtomicOrX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +1938,12 @@ FlatAtomicXorX2Flat::FlatAtomicXorX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1734,7 +1978,12 @@ FlatAtomicIncX2Flat::FlatAtomicIncX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1769,7 +2018,12 @@ FlatAtomicDecX2Flat::FlatAtomicDecX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2058,12 @@ FlatAtomicFcmpswapX2Flat::FlatAtomicFcmpswapX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFcmpswapX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fcmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1839,7 +2098,12 @@ FlatAtomicFminX2Flat::FlatAtomicFminX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFminX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFminX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1874,7 +2138,12 @@ FlatAtomicFmaxX2Flat::FlatAtomicFmaxX2Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicFmaxX2Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_fmax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mimg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mimg.cpp index dc539406e662..72fef6dbd1ff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mimg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mimg.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/mimg.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -26,7 +25,11 @@ ImageLoadMimg::ImageLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -45,7 +48,12 @@ ImageLoadMipMimg::ImageLoadMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +72,12 @@ ImageLoadPckMimg::ImageLoadPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +96,12 @@ ImageLoadPckSgnMimg::ImageLoadPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +120,12 @@ ImageLoadMipPckMimg::ImageLoadMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +144,12 @@ ImageLoadMipPckSgnMimg::ImageLoadMipPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ ImageStoreMimg::ImageStoreMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +191,12 @@ ImageStoreMipMimg::ImageStoreMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +215,12 @@ ImageStorePckMimg::ImageStorePckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +239,12 @@ ImageStoreMipPckMimg::ImageStoreMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +263,12 @@ ImageGetResinfoMimg::ImageGetResinfoMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -236,7 +288,12 @@ ImageAtomicSwapMimg::ImageAtomicSwapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +313,12 @@ ImageAtomicCmpswapMimg::ImageAtomicCmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -276,7 +338,12 @@ ImageAtomicAddMimg::ImageAtomicAddMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +363,12 @@ ImageAtomicSubMimg::ImageAtomicSubMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -316,7 +388,12 @@ ImageAtomicSminMimg::ImageAtomicSminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +413,12 @@ ImageAtomicUminMimg::ImageAtomicUminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -356,7 +438,12 @@ ImageAtomicSmaxMimg::ImageAtomicSmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +463,12 @@ ImageAtomicUmaxMimg::ImageAtomicUmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -396,7 +488,12 @@ ImageAtomicAndMimg::ImageAtomicAndMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -416,7 +513,12 @@ ImageAtomicOrMimg::ImageAtomicOrMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +538,12 @@ ImageAtomicXorMimg::ImageAtomicXorMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +563,12 @@ ImageAtomicIncMimg::ImageAtomicIncMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +588,12 @@ ImageAtomicDecMimg::ImageAtomicDecMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -496,7 +613,12 @@ ImageAtomicFcmpswapMimg::ImageAtomicFcmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicFcmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicFcmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_fcmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +638,12 @@ ImageAtomicFminMimg::ImageAtomicFminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicFminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicFminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_fmin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +663,12 @@ ImageAtomicFmaxMimg::ImageAtomicFmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicFmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicFmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_fmax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +689,12 @@ ImageSampleMimg::ImageSampleMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -578,7 +715,12 @@ ImageSampleClMimg::ImageSampleClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -599,7 +741,12 @@ ImageSampleDMimg::ImageSampleDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -620,7 +767,12 @@ ImageSampleDClMimg::ImageSampleDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -641,7 +793,12 @@ ImageSampleLMimg::ImageSampleLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +819,12 @@ ImageSampleBMimg::ImageSampleBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -683,7 +845,12 @@ ImageSampleBClMimg::ImageSampleBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +871,12 @@ ImageSampleLzMimg::ImageSampleLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -725,7 +897,12 @@ ImageSampleCMimg::ImageSampleCMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -746,7 +923,12 @@ ImageSampleCClMimg::ImageSampleCClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -767,7 +949,12 @@ ImageSampleCDMimg::ImageSampleCDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -788,7 +975,12 @@ ImageSampleCDClMimg::ImageSampleCDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +1001,12 @@ ImageSampleCLMimg::ImageSampleCLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -830,7 +1027,12 @@ ImageSampleCBMimg::ImageSampleCBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -851,7 +1053,12 @@ ImageSampleCBClMimg::ImageSampleCBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -872,7 +1079,12 @@ ImageSampleCLzMimg::ImageSampleCLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -893,7 +1105,12 @@ ImageSampleOMimg::ImageSampleOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -914,7 +1131,12 @@ ImageSampleClOMimg::ImageSampleClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -935,7 +1157,12 @@ ImageSampleDOMimg::ImageSampleDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -956,7 +1183,12 @@ ImageSampleDClOMimg::ImageSampleDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -977,7 +1209,12 @@ ImageSampleLOMimg::ImageSampleLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -998,7 +1235,12 @@ ImageSampleBOMimg::ImageSampleBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1019,7 +1261,12 @@ ImageSampleBClOMimg::ImageSampleBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1287,12 @@ ImageSampleLzOMimg::ImageSampleLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1313,12 @@ ImageSampleCOMimg::ImageSampleCOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1339,12 @@ ImageSampleCClOMimg::ImageSampleCClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1103,7 +1365,12 @@ ImageSampleCDOMimg::ImageSampleCDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1391,12 @@ ImageSampleCDClOMimg::ImageSampleCDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1145,7 +1417,12 @@ ImageSampleCLOMimg::ImageSampleCLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1166,7 +1443,12 @@ ImageSampleCBOMimg::ImageSampleCBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,7 +1469,12 @@ ImageSampleCBClOMimg::ImageSampleCBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1495,12 @@ ImageSampleCLzOMimg::ImageSampleCLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1229,7 +1521,12 @@ ImageGather4Mimg::ImageGather4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1250,7 +1547,12 @@ ImageGather4ClMimg::ImageGather4ClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1269,7 +1571,12 @@ ImageLoadBy2Mimg::ImageLoadBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1288,7 +1595,12 @@ ImageLoadBy4Mimg::ImageLoadBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1309,7 +1621,12 @@ ImageGather4LMimg::ImageGather4LMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1330,7 +1647,12 @@ ImageGather4BMimg::ImageGather4BMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1351,7 +1673,12 @@ ImageGather4BClMimg::ImageGather4BClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1372,7 +1699,12 @@ ImageGather4LzMimg::ImageGather4LzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1393,7 +1725,12 @@ ImageGather4CMimg::ImageGather4CMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1414,7 +1751,12 @@ ImageGather4CClMimg::ImageGather4CClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1433,7 +1775,12 @@ ImageLoadMipBy2Mimg::ImageLoadMipBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1452,7 +1799,12 @@ ImageLoadMipBy4Mimg::ImageLoadMipBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1473,7 +1825,12 @@ ImageGather4CLMimg::ImageGather4CLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1494,7 +1851,12 @@ ImageGather4CBMimg::ImageGather4CBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1515,7 +1877,12 @@ ImageGather4CBClMimg::ImageGather4CBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1536,7 +1903,12 @@ ImageGather4CLzMimg::ImageGather4CLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1557,7 +1929,12 @@ ImageGather4OMimg::ImageGather4OMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1578,7 +1955,12 @@ ImageGather4ClOMimg::ImageGather4ClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1597,7 +1979,12 @@ ImageStoreBy2Mimg::ImageStoreBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1616,7 +2003,12 @@ ImageStoreBy4Mimg::ImageStoreBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1637,7 +2029,12 @@ ImageGather4LOMimg::ImageGather4LOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1658,7 +2055,12 @@ ImageGather4BOMimg::ImageGather4BOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1679,7 +2081,12 @@ ImageGather4BClOMimg::ImageGather4BClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1700,7 +2107,12 @@ ImageGather4LzOMimg::ImageGather4LzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1721,7 +2133,12 @@ ImageGather4COMimg::ImageGather4COMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4COMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4COMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1742,7 +2159,12 @@ ImageGather4CClOMimg::ImageGather4CClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1761,7 +2183,12 @@ ImageStoreMipBy2Mimg::ImageStoreMipBy2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipBy2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipBy2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_by2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1780,7 +2207,12 @@ ImageStoreMipBy4Mimg::ImageStoreMipBy4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipBy4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipBy4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_by4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1801,7 +2233,12 @@ ImageGather4CLOMimg::ImageGather4CLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1822,7 +2259,12 @@ ImageGather4CBOMimg::ImageGather4CBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1843,7 +2285,12 @@ ImageGather4CBClOMimg::ImageGather4CBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1864,7 +2311,12 @@ ImageGather4CLzOMimg::ImageGather4CLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1885,7 +2337,12 @@ ImageGetLodMimg::ImageGetLodMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_lod", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1906,7 +2363,12 @@ ImageGather4hMimg::ImageGather4hMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1927,7 +2389,12 @@ ImageGather4hPckMimg::ImageGather4hPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1948,7 +2415,12 @@ ImageGather8hPckMimg::ImageGather8hPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather8hPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather8hPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather8h_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1969,7 +2441,12 @@ ImageSampleCdMimg::ImageSampleCdMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1990,7 +2467,12 @@ ImageSampleCdClMimg::ImageSampleCdClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2011,7 +2493,12 @@ ImageSampleCCdMimg::ImageSampleCCdMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2519,12 @@ ImageSampleCCdClMimg::ImageSampleCCdClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2053,7 +2545,12 @@ ImageSampleCdOMimg::ImageSampleCdOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2074,7 +2571,12 @@ ImageSampleCdClOMimg::ImageSampleCdClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2095,7 +2597,12 @@ ImageSampleCCdOMimg::ImageSampleCCdOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2116,7 +2623,12 @@ ImageSampleCCdClOMimg::ImageSampleCCdClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2135,7 +2647,12 @@ ImageLoadPck2Mimg::ImageLoadPck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2154,7 +2671,12 @@ ImageLoadPck4Mimg::ImageLoadPck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2173,7 +2695,12 @@ ImageLoadMipPck2Mimg::ImageLoadMipPck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2192,7 +2719,12 @@ ImageLoadMipPck4Mimg::ImageLoadMipPck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2211,7 +2743,12 @@ ImageStorePck2Mimg::ImageStorePck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2230,7 +2767,12 @@ ImageStorePck4Mimg::ImageStorePck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2249,7 +2791,12 @@ ImageStoreMipPck2Mimg::ImageStoreMipPck2Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPck2Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPck2Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2268,7 +2815,12 @@ ImageStoreMipPck4Mimg::ImageStoreMipPck4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPck4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPck4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2287,7 +2839,12 @@ ImageMsaaLoadMimg::ImageMsaaLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_msaa_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2308,7 +2865,12 @@ ImageSampleDG16Mimg::ImageSampleDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2329,7 +2891,12 @@ ImageSampleDClG16Mimg::ImageSampleDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2350,7 +2917,12 @@ ImageSampleCDG16Mimg::ImageSampleCDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2371,7 +2943,12 @@ ImageSampleCDClG16Mimg::ImageSampleCDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2392,7 +2969,12 @@ ImageSampleDOG16Mimg::ImageSampleDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2413,7 +2995,12 @@ ImageSampleDClOG16Mimg::ImageSampleDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2434,7 +3021,12 @@ ImageSampleCDOG16Mimg::ImageSampleCDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2455,7 +3047,12 @@ ImageSampleCDClOG16Mimg::ImageSampleCDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2474,7 +3071,12 @@ ImageBvhIntersectRayMimg::ImageBvhIntersectRayMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvhIntersectRayMimg(const MachineInst *opcode) { +DecodeResult decodeImageBvhIntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_bvh_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2493,7 +3095,12 @@ ImageBvh64IntersectRayMimg::ImageBvh64IntersectRayMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvh64IntersectRayMimg(const MachineInst *opcode) { +DecodeResult decodeImageBvh64IntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_bvh64_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2514,7 +3121,12 @@ ImageSampleCdG16Mimg::ImageSampleCdG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2535,7 +3147,12 @@ ImageSampleCdClG16Mimg::ImageSampleCdClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2556,7 +3173,12 @@ ImageSampleCCdG16Mimg::ImageSampleCCdG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2577,7 +3199,12 @@ ImageSampleCCdClG16Mimg::ImageSampleCCdClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2598,7 +3225,12 @@ ImageSampleCdOG16Mimg::ImageSampleCdOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2619,7 +3251,12 @@ ImageSampleCdClOG16Mimg::ImageSampleCdClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCdClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cd_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2640,7 +3277,12 @@ ImageSampleCCdOG16Mimg::ImageSampleCCdOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2661,7 +3303,12 @@ ImageSampleCCdClOG16Mimg::ImageSampleCCdClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCCdClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cd_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mtbuf.cpp index 3492d42a0faa..a9a4bd439534 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mtbuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/mtbuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -68,7 +72,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -93,7 +102,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +132,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +162,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +192,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +222,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -218,7 +252,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +282,12 @@ TbufferLoadFormatD16XMtbuf::TbufferLoadFormatD16XMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -274,7 +318,13 @@ TbufferLoadFormatD16XyMtbuf::TbufferLoadFormatD16XyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +349,13 @@ TbufferLoadFormatD16XyzMtbuf::TbufferLoadFormatD16XyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +386,13 @@ TbufferLoadFormatD16XyzwMtbuf::TbufferLoadFormatD16XyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -355,7 +417,13 @@ TbufferStoreFormatD16XMtbuf::TbufferStoreFormatD16XMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -380,7 +448,13 @@ TbufferStoreFormatD16XyMtbuf::TbufferStoreFormatD16XyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +479,13 @@ TbufferStoreFormatD16XyzMtbuf::TbufferStoreFormatD16XyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +510,13 @@ TbufferStoreFormatD16XyzwMtbuf::TbufferStoreFormatD16XyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatD16XyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf.cpp index 097bd1d47acd..69d15a88975f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/mubuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -43,7 +42,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -68,7 +72,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -93,7 +102,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +132,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +162,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +192,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +222,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -218,7 +252,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +282,12 @@ BufferLoadUbyteMubuf::BufferLoadUbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -268,7 +312,12 @@ BufferLoadSbyteMubuf::BufferLoadSbyteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -293,7 +342,12 @@ BufferLoadUshortMubuf::BufferLoadUshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ushort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +372,12 @@ BufferLoadSshortMubuf::BufferLoadSshortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSshortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSshortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sshort", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +402,12 @@ BufferLoadDwordMubuf::BufferLoadDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,7 +432,12 @@ BufferLoadDwordx2Mubuf::BufferLoadDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -393,7 +462,12 @@ BufferLoadDwordx4Mubuf::BufferLoadDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -418,7 +492,12 @@ BufferLoadDwordx3Mubuf::BufferLoadDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -443,7 +522,12 @@ BufferStoreByteMubuf::BufferStoreByteMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +552,12 @@ BufferStoreByteD16HiMubuf::BufferStoreByteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreByteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_byte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -493,7 +582,12 @@ BufferStoreShortMubuf::BufferStoreShortMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -518,7 +612,12 @@ BufferStoreShortD16HiMubuf::BufferStoreShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,7 +642,12 @@ BufferStoreDwordMubuf::BufferStoreDwordMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -568,7 +672,12 @@ BufferStoreDwordx2Mubuf::BufferStoreDwordx2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +702,12 @@ BufferStoreDwordx4Mubuf::BufferStoreDwordx4Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx4Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -618,7 +732,12 @@ BufferStoreDwordx3Mubuf::BufferStoreDwordx3Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreDwordx3Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_dwordx3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -643,7 +762,12 @@ BufferLoadUbyteD16Mubuf::BufferLoadUbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -675,7 +799,12 @@ BufferLoadUbyteD16HiMubuf::BufferLoadUbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadUbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_ubyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -707,7 +836,12 @@ BufferLoadSbyteD16Mubuf::BufferLoadSbyteD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,7 +873,12 @@ BufferLoadSbyteD16HiMubuf::BufferLoadSbyteD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadSbyteD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_sbyte_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -771,7 +910,12 @@ BufferLoadShortD16Mubuf::BufferLoadShortD16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -803,7 +947,12 @@ BufferLoadShortD16HiMubuf::BufferLoadShortD16HiMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadShortD16HiMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_short_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -835,7 +984,13 @@ BufferLoadFormatD16HiXMubuf::BufferLoadFormatD16HiXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -867,7 +1022,13 @@ BufferStoreFormatD16HiXMubuf::BufferStoreFormatD16HiXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16HiXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_hi_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1055,12 @@ BufferAtomicSwapMubuf::BufferAtomicSwapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -922,7 +1088,12 @@ BufferAtomicCmpswapMubuf::BufferAtomicCmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -949,7 +1120,12 @@ BufferAtomicAddMubuf::BufferAtomicAddMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -976,7 +1152,12 @@ BufferAtomicSubMubuf::BufferAtomicSubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1003,7 +1184,12 @@ BufferAtomicCsubMubuf::BufferAtomicCsubMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCsubMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCsubMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_csub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1030,7 +1216,12 @@ BufferAtomicSminMubuf::BufferAtomicSminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1248,12 @@ BufferAtomicUminMubuf::BufferAtomicUminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1084,7 +1280,12 @@ BufferAtomicSmaxMubuf::BufferAtomicSmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1111,7 +1312,12 @@ BufferAtomicUmaxMubuf::BufferAtomicUmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1344,12 @@ BufferAtomicAndMubuf::BufferAtomicAndMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1165,7 +1376,12 @@ BufferAtomicOrMubuf::BufferAtomicOrMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1192,7 +1408,12 @@ BufferAtomicXorMubuf::BufferAtomicXorMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1219,7 +1440,12 @@ BufferAtomicIncMubuf::BufferAtomicIncMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1246,7 +1472,12 @@ BufferAtomicDecMubuf::BufferAtomicDecMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1274,7 +1505,12 @@ BufferAtomicFcmpswapMubuf::BufferAtomicFcmpswapMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFcmpswapMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fcmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1301,7 +1537,12 @@ BufferAtomicFminMubuf::BufferAtomicFminMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFminMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFminMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1328,7 +1569,12 @@ BufferAtomicFmaxMubuf::BufferAtomicFmaxMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFmaxMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFmaxMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1355,7 +1601,12 @@ BufferAtomicSwapX2Mubuf::BufferAtomicSwapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1383,7 +1634,12 @@ BufferAtomicCmpswapX2Mubuf::BufferAtomicCmpswapX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1410,7 +1666,12 @@ BufferAtomicAddX2Mubuf::BufferAtomicAddX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1437,7 +1698,12 @@ BufferAtomicSubX2Mubuf::BufferAtomicSubX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1464,7 +1730,12 @@ BufferAtomicSminX2Mubuf::BufferAtomicSminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1491,7 +1762,12 @@ BufferAtomicUminX2Mubuf::BufferAtomicUminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1794,12 @@ BufferAtomicSmaxX2Mubuf::BufferAtomicSmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_smax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1545,7 +1826,12 @@ BufferAtomicUmaxX2Mubuf::BufferAtomicUmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicUmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_umax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1572,7 +1858,12 @@ BufferAtomicAndX2Mubuf::BufferAtomicAndX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1599,7 +1890,12 @@ BufferAtomicOrX2Mubuf::BufferAtomicOrX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1626,7 +1922,12 @@ BufferAtomicXorX2Mubuf::BufferAtomicXorX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1653,7 +1954,12 @@ BufferAtomicIncX2Mubuf::BufferAtomicIncX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1680,7 +1986,12 @@ BufferAtomicDecX2Mubuf::BufferAtomicDecX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1708,7 +2019,12 @@ BufferAtomicFcmpswapX2Mubuf::BufferAtomicFcmpswapX2Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFcmpswapX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fcmpswap_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1735,7 +2051,12 @@ BufferAtomicFminX2Mubuf::BufferAtomicFminX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFminX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmin_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1762,7 +2083,12 @@ BufferAtomicFmaxX2Mubuf::BufferAtomicFmaxX2Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicFmaxX2Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_fmax_x2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1775,7 +2101,12 @@ BufferGl0InvMubuf::BufferGl0InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl0_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1788,7 +2119,12 @@ BufferGl1InvMubuf::BufferGl1InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1813,7 +2149,12 @@ BufferLoadFormatD16XMubuf::BufferLoadFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1845,7 +2186,12 @@ BufferLoadFormatD16XyMubuf::BufferLoadFormatD16XyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_d16_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1870,7 +2216,13 @@ BufferLoadFormatD16XyzMubuf::BufferLoadFormatD16XyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1902,7 +2254,13 @@ BufferLoadFormatD16XyzwMubuf::BufferLoadFormatD16XyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1927,7 +2285,12 @@ BufferStoreFormatD16XMubuf::BufferStoreFormatD16XMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_d16_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1952,7 +2315,13 @@ BufferStoreFormatD16XyMubuf::BufferStoreFormatD16XyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1977,7 +2346,13 @@ BufferStoreFormatD16XyzMubuf::BufferStoreFormatD16XyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2002,7 +2377,13 @@ BufferStoreFormatD16XyzwMubuf::BufferStoreFormatD16XyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatD16XyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_format_d16_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp index 383d17e174c9..c14eba407f4c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem.cpp index a1edb9a7c619..1fb7cdfc9773 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx10_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SLoadDwordSmem::SLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -56,7 +59,12 @@ SLoadDwordx2Smem::SLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +85,12 @@ SLoadDwordx4Smem::SLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -98,7 +111,12 @@ SLoadDwordx8Smem::SLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +137,12 @@ SLoadDwordx16Smem::SLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +163,12 @@ SBufferLoadDwordSmem::SBufferLoadDwordSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dword", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +189,12 @@ SBufferLoadDwordx2Smem::SBufferLoadDwordx2Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx2Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx2Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -182,7 +215,12 @@ SBufferLoadDwordx4Smem::SBufferLoadDwordx4Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx4Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx4Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +241,12 @@ SBufferLoadDwordx8Smem::SBufferLoadDwordx8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +267,12 @@ SBufferLoadDwordx16Smem::SBufferLoadDwordx16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadDwordx16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadDwordx16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_dwordx16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -237,7 +285,11 @@ SGl1InvSmem::SGl1InvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode) { +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +302,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +321,11 @@ SMemtimeSmem::SMemtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemtimeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -280,7 +340,12 @@ SMemrealtimeSmem::SMemrealtimeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMemrealtimeSmem(const MachineInst *opcode) { +DecodeResult decodeSMemrealtimeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_memrealtime", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1.cpp index e2edae8254d1..21173ca0bce6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +173,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +201,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +230,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +255,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -246,7 +281,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -270,7 +309,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -295,7 +339,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -319,7 +368,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +398,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +424,11 @@ SFf0I32B32Sop1::SFf0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +450,11 @@ SFf0I32B64Sop1::SFf0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf0I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +475,11 @@ SFf1I32B32Sop1::SFf1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +501,11 @@ SFf1I32B64Sop1::SFf1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFf1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFf1I32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ff1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +526,12 @@ SFlbitI32B32Sop1::SFlbitI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -473,7 +553,12 @@ SFlbitI32B64Sop1::SFlbitI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -494,7 +579,11 @@ SFlbitI32Sop1::SFlbitI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -516,7 +605,12 @@ SFlbitI32I64Sop1::SFlbitI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFlbitI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSFlbitI32I64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_flbit_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -538,7 +632,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -560,7 +658,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +685,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -604,7 +712,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +739,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +766,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +789,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -685,7 +812,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +839,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +861,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +897,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +935,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -823,7 +972,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -855,7 +1009,12 @@ SAndn2SaveexecB64Sop1::SAndn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -887,7 +1046,12 @@ SOrn2SaveexecB64Sop1::SOrn2SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -919,7 +1083,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1120,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -983,7 +1157,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1007,7 +1186,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1216,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1052,7 +1241,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1072,7 +1266,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1096,7 +1295,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1325,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1145,7 +1354,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1177,7 +1390,12 @@ SAndn1SaveexecB64Sop1::SAndn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1209,7 +1427,12 @@ SOrn1SaveexecB64Sop1::SOrn1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1241,7 +1464,12 @@ SAndn1WrexecB64Sop1::SAndn1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1273,7 +1501,12 @@ SAndn2WrexecB64Sop1::SAndn2WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1294,7 +1527,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1325,7 +1563,12 @@ SAndSaveexecB32Sop1::SAndSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1357,7 +1600,12 @@ SOrSaveexecB32Sop1::SOrSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1388,7 +1636,12 @@ SXorSaveexecB32Sop1::SXorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1672,12 @@ SAndn2SaveexecB32Sop1::SAndn2SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1450,7 +1708,12 @@ SOrn2SaveexecB32Sop1::SOrn2SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn2SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn2_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1744,12 @@ SNandSaveexecB32Sop1::SNandSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1512,7 +1780,12 @@ SNorSaveexecB32Sop1::SNorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1543,7 +1816,12 @@ SXnorSaveexecB32Sop1::SXnorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1574,7 +1852,12 @@ SAndn1SaveexecB32Sop1::SAndn1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1605,7 +1888,12 @@ SOrn1SaveexecB32Sop1::SOrn1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrn1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_orn1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1636,7 +1924,12 @@ SAndn1WrexecB32Sop1::SAndn1WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn1WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn1_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1667,7 +1960,12 @@ SAndn2WrexecB32Sop1::SAndn2WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndn2WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_andn2_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1687,7 +1985,12 @@ SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop2.cpp index 2d6739fb577a..3a75ff6ea2ad 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +280,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -283,7 +314,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +348,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +382,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +454,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +490,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -468,7 +525,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +562,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -531,7 +596,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -563,7 +632,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -593,7 +666,11 @@ SAndn2B32Sop2::SAndn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +702,11 @@ SAndn2B64Sop2::SAndn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_andn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -655,7 +736,11 @@ SOrn2B32Sop2::SOrn2B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +772,11 @@ SOrn2B64Sop2::SOrn2B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrn2B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrn2B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_orn2_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -717,7 +806,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +842,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -779,7 +876,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -811,7 +912,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +946,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -873,7 +982,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -903,7 +1016,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1051,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1085,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1120,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1154,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1189,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1220,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1251,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1282,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1316,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1197,7 +1350,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1385,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1420,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1289,7 +1454,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1319,7 +1489,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1349,7 +1524,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1379,7 +1559,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1409,7 +1594,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1438,7 +1628,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1466,7 +1661,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1493,7 +1693,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1725,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1756,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopc.cpp index 598a63641fc1..bc216c3468d1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +554,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -517,7 +588,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopk.cpp index 710e3b9f2f21..8d845870311a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -39,7 +42,11 @@ SVersionSopk::SVersionSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode) { +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_version", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,7 +68,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,7 +92,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -101,7 +116,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +140,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +164,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +188,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -181,7 +212,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -201,7 +236,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +260,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -241,7 +284,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +308,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +332,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -301,7 +356,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -322,7 +381,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -340,7 +403,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +424,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -374,7 +445,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +474,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +508,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +535,12 @@ SWaitcntVscntSopk::SWaitcntVscntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +558,12 @@ SWaitcntVmcntSopk::SWaitcntVmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +581,12 @@ SWaitcntExpcntSopk::SWaitcntExpcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_expcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -505,7 +604,12 @@ SWaitcntLgkmcntSopk::SWaitcntLgkmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_lgkmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -529,7 +633,12 @@ SSubvectorLoopBeginSopk::SSubvectorLoopBeginSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubvectorLoopBeginSopk(const MachineInst *opcode) { +DecodeResult decodeSSubvectorLoopBeginSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_subvector_loop_begin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -553,7 +662,12 @@ SSubvectorLoopEndSopk::SSubvectorLoopEndSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubvectorLoopEndSopk(const MachineInst *opcode) { +DecodeResult decodeSSubvectorLoopEndSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_subvector_loop_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopp.cpp index c52ae8cb6626..c663fe267001 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -36,7 +39,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +60,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +82,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +106,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -116,7 +136,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +166,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -166,7 +196,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +226,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -216,7 +256,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +280,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +299,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +319,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +338,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +357,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +376,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +398,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,7 +420,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -362,7 +440,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +457,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +476,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +496,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +517,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +537,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +557,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +577,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +597,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +616,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -509,7 +635,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -522,7 +653,11 @@ SCodeEndSopp::SCodeEndSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode) { +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_code_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -537,7 +672,12 @@ SInstPrefetchSopp::SInstPrefetchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSInstPrefetchSopp(const MachineInst *opcode) { +DecodeResult decodeSInstPrefetchSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_inst_prefetch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +692,11 @@ SClauseSopp::SClauseSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode) { +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_clause", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -569,7 +713,12 @@ SWaitcntDepctrSopp::SWaitcntDepctrSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt_depctr", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -584,7 +733,11 @@ SRoundModeSopp::SRoundModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode) { +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_round_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -599,7 +752,12 @@ SDenormModeSopp::SDenormModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode) { +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_denorm_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +775,12 @@ STtracedataImmSopp::STtracedataImmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata_imm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vintrp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vintrp.cpp index d83da06422bc..9a2da70c03ee 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vintrp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vintrp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vintrp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,12 @@ VInterpP1F32Vintrp::VInterpP1F32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1F32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpP1F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_p1_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +56,12 @@ VInterpP2F32Vintrp::VInterpP2F32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +83,12 @@ VInterpMovF32Vintrp::VInterpMovF32Vintrp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpMovF32Vintrp(const MachineInst *opcode) { +DecodeResult decodeVInterpMovF32Vintrp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vintrp::validate_encoding( + "v_interp_mov_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp index 34a79a8aa5d7..392bbed68336 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,15 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_dpp" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +90,16 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mov_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_dpp" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,15 +116,24 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_dpp" + : "v_readfirstlane_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -130,15 +155,23 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_dpp" + : "v_cvt_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -159,15 +192,23 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_I32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_dpp" + : "v_cvt_f64_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -228,7 +269,17 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_dpp" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -289,7 +340,17 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_dpp" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +411,17 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_dpp" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -411,7 +482,17 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_dpp" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +553,17 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_dpp" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -540,7 +631,17 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_dpp" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +702,18 @@ VCvtRpiI32F32Vop1::VCvtRpiI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_rpi_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_rpi_i32_f32_dpp" + : "v_cvt_rpi_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +774,18 @@ VCvtFlrI32F32Vop1::VCvtFlrI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_flr_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_flr_i32_f32_dpp" + : "v_cvt_flr_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -723,7 +846,18 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_off_f32_i4_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_dpp" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -745,15 +879,23 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_dpp" + : "v_cvt_f32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -774,15 +916,23 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_dpp" + : "v_cvt_f64_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -843,7 +993,18 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte0_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_dpp" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -904,7 +1065,18 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte1_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_dpp" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -965,7 +1137,18 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte2_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_dpp" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1026,7 +1209,18 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f32_ubyte3_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_dpp" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1048,15 +1242,23 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_U32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_dpp" + : "v_cvt_u32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1077,15 +1279,23 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CVT_F64_U32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_dpp" + : "v_cvt_f64_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1107,15 +1317,23 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_TRUNC_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_dpp" + : "v_trunc_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1137,15 +1355,23 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CEIL_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_dpp" + : "v_ceil_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1167,15 +1393,23 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RNDNE_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_dpp" + : "v_rndne_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1197,15 +1431,23 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FLOOR_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_dpp" + : "v_floor_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1463,15 @@ VPipeflushVop1::VPipeflushVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_dpp" + : "v_pipeflush_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1281,7 +1531,17 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_dpp" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1341,7 +1601,17 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_dpp" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1671,16 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_dpp" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1461,7 +1740,17 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_dpp" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1521,7 +1810,17 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_dpp" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1581,7 +1880,16 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_dpp" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1641,7 +1949,16 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_dpp" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1701,7 +2018,16 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_dpp" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1762,7 +2088,18 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rcp_iflag_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_dpp" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1822,7 +2159,16 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_dpp" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1844,15 +2190,23 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RCP_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_dpp" + : "v_rcp_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1874,15 +2228,23 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_RSQ_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_dpp" + : "v_rsq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1942,7 +2304,16 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_dpp" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1964,15 +2335,23 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SQRT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_dpp" + : "v_sqrt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2411,16 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_dpp" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2092,7 +2480,16 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_dpp" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2152,7 +2549,16 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_not_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_dpp" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2212,7 +2618,17 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_bfrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_dpp" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2272,7 +2688,16 @@ VFfbhU32Vop1::VFfbhU32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ffbh_u32_dpp" + : "v_ffbh_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2332,7 +2757,16 @@ VFfblB32Vop1::VFfblB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbl_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ffbl_b32_dpp" + : "v_ffbl_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2392,7 +2826,16 @@ VFfbhI32Vop1::VFfbhI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ffbh_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ffbh_i32_dpp" + : "v_ffbh_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2414,15 +2857,24 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_dpp" + : "v_frexp_exp_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2444,15 +2896,24 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_dpp" + : "v_frexp_mant_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2474,15 +2935,23 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FRACT_F64 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_dpp" + : "v_fract_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2543,7 +3012,18 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i32_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_dpp" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2604,7 +3084,18 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_dpp" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2620,7 +3111,15 @@ VClrexcpVop1::VClrexcpVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop1(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clrexcp_dpp" + : "v_clrexcp_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2684,7 +3183,18 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movreld_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_dpp" + : "v_movreld_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2744,7 +3254,18 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrels_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_dpp" + : "v_movrels_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2804,7 +3325,18 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_dpp" + : "v_movrelsd_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2864,7 +3396,18 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_movrelsd_2_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_dpp" + : "v_movrelsd_2_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2926,7 +3469,17 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_u16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_dpp" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2994,7 +3547,17 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_f16_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_dpp" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3062,7 +3625,17 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_dpp" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3130,7 +3703,17 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_dpp" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3197,7 +3780,16 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rcp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_dpp" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3264,7 +3856,16 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sqrt_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_dpp" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3331,7 +3932,16 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_rsq_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_dpp" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3398,7 +4008,16 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_log_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_dpp" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3465,7 +4084,16 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_exp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_dpp" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3533,7 +4161,18 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_mant_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_dpp" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3601,7 +4240,18 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_frexp_exp_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_dpp" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3668,7 +4318,17 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_floor_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_dpp" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3735,7 +4395,16 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_ceil_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_dpp" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3802,7 +4471,17 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_trunc_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_dpp" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3869,7 +4548,17 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_rndne_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_dpp" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3936,7 +4625,17 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_fract_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_dpp" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4003,7 +4702,16 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sin_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_dpp" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4070,7 +4778,16 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_cos_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_dpp" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4137,7 +4854,18 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sat_pk_u8_i16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_dpp" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4199,7 +4927,18 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_i16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_dpp" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4267,7 +5006,18 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_norm_u16_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_dpp" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4292,15 +5042,23 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAP_B32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b32_dpp" + : "v_swap_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4321,16 +5079,25 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) src_operands_[2] = &m0; num_src_ = 3; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAPREL_B32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_SWAPREL_B32 does not support SDWA", ""); m0.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swaprel_b32_dpp" + : "v_swaprel_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp index ff63955e646c..2c50961214ad 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -78,7 +77,18 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cndmask_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_dpp" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,12 +129,21 @@ VDot2cF32F16Vop2::VDot2cF32F16Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT2C_F32_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot2cF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2cF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2c_f32_f16_dpp" + : "v_dot2c_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT2C_F32_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -190,7 +209,16 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_dpp" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -256,7 +284,16 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_dpp" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +360,17 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_dpp" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -347,15 +394,24 @@ VFmacLegacyF32Vop2::VFmacLegacyF32Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_LEGACY_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_LEGACY_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacLegacyF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_legacy_f32_dpp" + : "v_fmac_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_LEGACY_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_LEGACY_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -422,7 +478,18 @@ VMulLegacyF32Vop2::VMulLegacyF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_legacy_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_legacy_f32_dpp" + : "v_mul_legacy_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +555,16 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_dpp" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -555,7 +631,17 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_dpp" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -622,7 +708,18 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_i32_i24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_dpp" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -689,7 +786,17 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_dpp" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -756,7 +863,18 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_mul_hi_u32_u24_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_dpp" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -797,12 +915,21 @@ VDot4cI32I8Vop2::VDot4cI32I8Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_DOT4C_I32_I8 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVDot4cI32I8Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot4cI32I8Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4c_i32_i8_dpp" + : "v_dot4c_i32_i8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_DOT4C_I32_I8 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -868,7 +995,16 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f32_dpp" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1070,16 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f32_dpp" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1000,7 +1145,16 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_dpp" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1066,7 +1220,16 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_dpp" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1132,7 +1295,16 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_dpp" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1198,7 +1370,16 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_dpp" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1265,7 +1446,18 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshrrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_dpp" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1332,7 +1524,18 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ashrrev_i32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_dpp" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1399,7 +1602,18 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_lshlrev_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_dpp" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1465,7 +1679,16 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_and_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_dpp" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1531,7 +1754,16 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_or_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_dpp" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1597,7 +1829,16 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_dpp" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1663,7 +1904,16 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_xnor_b32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_dpp" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1730,7 +1980,17 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_dpp" + : "v_add_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2057,17 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_dpp" + : "v_sub_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1864,7 +2134,18 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_nc_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_dpp" + : "v_subrev_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1937,7 +2218,18 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_add_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_dpp" + : "v_add_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2010,7 +2302,18 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_sub_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_dpp" + : "v_sub_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2083,7 +2386,18 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_co_ci_u32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_dpp" + : "v_subrev_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2124,12 +2438,20 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F32 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_dpp" + : "v_fmac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2157,16 +2479,24 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAMK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f32_dpp" + : "v_fmamk_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2194,16 +2524,24 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAAK_F32 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f32_dpp" + : "v_fmaak_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2270,7 +2608,18 @@ VCvtPkrtzF16F32Vop2::VCvtPkrtzF16F32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cvt_pkrtz_f16_f32_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pkrtz_f16_f32_dpp" + : "v_cvt_pkrtz_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2337,7 +2686,16 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_add_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_dpp" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2410,7 +2768,16 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_sub_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_dpp" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2484,7 +2851,17 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_subrev_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_dpp" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2557,7 +2934,16 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_mul_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_dpp" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2605,12 +2991,20 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_dpp" + : "v_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2646,16 +3040,24 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAMK_F16 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f16_dpp" + : "v_fmamk_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2691,16 +3093,24 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F16 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_FMAAK_F16 does not support SDWA", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f16_dpp" + : "v_fmaak_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2773,7 +3183,16 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_max_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f16_dpp" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2846,7 +3265,16 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA ? "v_min_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f16_dpp" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2919,7 +3347,17 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_ldexp_f16_sdwa" + : amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_dpp" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2966,12 +3404,20 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) dpp_bound_ctrl_ = dp->bound_ctrl; dpp_fi_ = dp->fi; } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_PK_FMAC_F16 does not support SDWA", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fmac_f16_dpp" + : "v_pk_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3.cpp index 143cc24cc41d..2a9da7d3d6e0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -30,7 +29,12 @@ VInterpP1F32Vop3::VInterpP1F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -53,7 +57,12 @@ VInterpP2F32Vop3::VInterpP2F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -75,7 +84,12 @@ VInterpMovF32Vop3::VInterpMovF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpMovF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpMovF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_mov_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -88,7 +102,11 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -109,7 +127,11 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +148,12 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readfirstlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +175,11 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +200,11 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,7 +225,11 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -211,7 +250,11 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +275,11 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +300,11 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -274,7 +325,11 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -302,7 +357,11 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +382,12 @@ VCvtRpiI32F32Vop3::VCvtRpiI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtRpiI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtRpiI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_rpi_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +408,12 @@ VCvtFlrI32F32Vop3::VCvtFlrI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFlrI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFlrI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_flr_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +434,12 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_off_f32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +461,11 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -408,7 +486,11 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -429,7 +511,12 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -450,7 +537,12 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -471,7 +563,12 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte2", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -492,7 +589,12 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f32_ubyte3", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -514,7 +616,11 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -535,7 +641,11 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -557,7 +667,11 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -579,7 +693,11 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +719,11 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +745,11 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -636,7 +762,11 @@ VPipeflushVop3::VPipeflushVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pipeflush", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -657,7 +787,11 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +812,11 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +837,11 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -720,7 +862,11 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +887,11 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,7 +912,11 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -783,7 +937,11 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +962,11 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -825,7 +987,12 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_iflag_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -846,7 +1013,11 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -868,7 +1039,11 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1065,11 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -911,7 +1090,11 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -933,7 +1116,11 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -954,7 +1141,11 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -975,7 +1166,11 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -996,7 +1191,11 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1216,11 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1038,7 +1241,11 @@ VFfbhU32Vop3::VFfbhU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1059,7 +1266,11 @@ VFfblB32Vop3::VFfblB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfblB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfblB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1080,7 +1291,11 @@ VFfbhI32Vop3::VFfbhI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFfbhI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFfbhI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ffbh_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1102,7 +1317,12 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1124,7 +1344,12 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1146,7 +1371,11 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1167,7 +1396,12 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1188,7 +1422,12 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1201,7 +1440,11 @@ VClrexcpVop3::VClrexcpVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClrexcpVop3(const MachineInst *opcode) { +DecodeResult decodeVClrexcpVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_clrexcp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1225,7 +1468,12 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1245,7 +1493,12 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1265,7 +1518,12 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movrelsd_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1285,7 +1543,12 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1307,7 +1570,11 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1335,7 +1602,11 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_f16_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1363,7 +1634,11 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1391,7 +1666,11 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1419,7 +1698,11 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rcp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1730,11 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sqrt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1475,7 +1762,11 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rsq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,7 +1794,11 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_log_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1531,7 +1826,11 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_exp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1559,7 +1858,12 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_mant_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1587,7 +1891,12 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_frexp_exp_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1615,7 +1924,11 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1643,7 +1956,11 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1671,7 +1988,11 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +2020,11 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1727,7 +2052,11 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fract_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2084,11 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sin_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1783,7 +2116,11 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cos_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1810,7 +2147,12 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sat_pk_u8_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1832,7 +2174,12 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1860,7 +2207,12 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_norm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1895,7 +2247,12 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cndmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1922,7 +2279,11 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1949,7 +2310,11 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1976,7 +2341,11 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2004,7 +2373,12 @@ VFmacLegacyF32Vop3::VFmacLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2031,7 +2405,12 @@ VMulLegacyF32Vop3::VMulLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2058,7 +2437,11 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2085,7 +2468,11 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2112,7 +2499,12 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2139,7 +2531,11 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2166,7 +2562,12 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2193,7 +2594,11 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2220,7 +2625,11 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2247,7 +2656,11 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2274,7 +2687,11 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2301,7 +2718,11 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2328,7 +2749,11 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2355,7 +2780,12 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2382,7 +2812,12 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2409,7 +2844,12 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2436,7 +2876,11 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2463,7 +2907,11 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2490,7 +2938,11 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2517,7 +2969,11 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2544,7 +3000,11 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2571,7 +3031,11 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2598,7 +3062,12 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_nc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2626,7 +3095,11 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2653,7 +3126,12 @@ VCvtPkrtzF16F32Vop3::VCvtPkrtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkrtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pkrtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2682,7 +3160,11 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2717,7 +3199,11 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2752,7 +3238,11 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_subrev_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2787,7 +3277,11 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2823,7 +3317,11 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2858,7 +3356,11 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2893,7 +3395,11 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2928,7 +3434,11 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2967,7 +3477,12 @@ VFmaLegacyF32Vop3::VFmaLegacyF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaLegacyF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaLegacyF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_legacy_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3000,7 +3515,11 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3033,7 +3552,11 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u24", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3066,7 +3589,11 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubeid_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3099,7 +3626,11 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubesc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3132,7 +3663,11 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubetc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3165,7 +3700,11 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cubema_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3198,7 +3737,11 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3231,7 +3774,11 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3264,7 +3811,11 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3297,7 +3848,11 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3333,7 +3888,11 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3366,7 +3925,11 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lerp_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3399,7 +3962,12 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbit_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3432,7 +4000,12 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_alignbyte_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3465,7 +4038,11 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mullit_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3498,7 +4075,11 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3531,7 +4112,11 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3564,7 +4149,11 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3597,7 +4186,11 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3630,7 +4223,11 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3663,7 +4260,11 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3696,7 +4297,11 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3729,7 +4334,11 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3762,7 +4371,11 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3795,7 +4408,11 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3828,7 +4445,11 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3861,7 +4482,11 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3894,7 +4519,11 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3927,7 +4556,12 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u8_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3960,7 +4594,12 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3996,7 +4635,12 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4025,7 +4669,11 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4054,7 +4702,11 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4083,7 +4735,11 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4112,7 +4768,11 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4140,7 +4800,11 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4167,7 +4831,11 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4194,7 +4862,11 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4221,7 +4893,11 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4257,7 +4933,12 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4296,7 +4977,12 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fmas_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4329,7 +5015,11 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_msad_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4364,7 +5054,12 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_qsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4399,7 +5094,12 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_pk_u16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4427,7 +5127,12 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_trig_preop_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4457,7 +5162,12 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mqsad_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4490,7 +5200,11 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xor3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4518,7 +5232,12 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4546,7 +5265,12 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4574,7 +5298,12 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4603,7 +5332,11 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4638,7 +5371,11 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4673,7 +5410,11 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4708,7 +5449,12 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4743,7 +5489,12 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4778,7 +5529,11 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4813,7 +5568,11 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4848,7 +5607,11 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4883,7 +5646,11 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4918,7 +5685,11 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4953,7 +5724,11 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4988,7 +5763,12 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_pack_b32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5017,7 +5797,12 @@ VCvtPknormI16F16Vop3::VCvtPknormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5046,7 +5831,12 @@ VCvtPknormU16F16Vop3::VCvtPknormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5075,7 +5865,12 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5117,7 +5912,11 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5142,7 +5941,12 @@ VInterpP1llF16Vop3::VInterpP1llF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1llF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1llF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1ll_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5163,7 +5967,12 @@ VInterpP1lvF16Vop3::VInterpP1lvF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP1lvF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP1lvF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p1lv_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5196,7 +6005,11 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_perm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5229,7 +6042,11 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_xad_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5262,7 +6079,12 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5295,7 +6117,12 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_lshl_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5331,7 +6158,11 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5373,7 +6204,11 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5415,7 +6250,11 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5457,7 +6296,11 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_min3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5499,7 +6342,11 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5541,7 +6388,11 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5583,7 +6434,11 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_max3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5625,7 +6480,11 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5667,7 +6526,11 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5709,7 +6572,11 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_med3_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5736,7 +6603,12 @@ VInterpP2F16Vop3::VInterpP2F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_interp_p2_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5778,7 +6650,11 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5820,7 +6696,12 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_div_fixup_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5845,7 +6726,12 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_readlane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5869,7 +6755,12 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_writelane_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5896,7 +6787,11 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_ldexp_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5923,7 +6818,11 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5950,7 +6849,12 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_bcnt_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5977,7 +6881,12 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_lo_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6004,7 +6913,12 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mbcnt_hi_u32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6031,7 +6945,12 @@ VCvtPknormI16F32Vop3::VCvtPknormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_i16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6058,7 +6977,12 @@ VCvtPknormU16F32Vop3::VCvtPknormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPknormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPknormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pknorm_u16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6085,7 +7009,12 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_u16_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6112,7 +7041,12 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cvt_pk_i16_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6145,7 +7079,11 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add3_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6178,7 +7116,11 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_lshl_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6211,7 +7153,11 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_and_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6244,7 +7190,11 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_or3_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6279,7 +7229,11 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6314,7 +7268,11 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_mad_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6341,7 +7299,11 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_sub_nc_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6370,7 +7332,12 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_permlane16_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6399,7 +7366,12 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_permlanex16_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6426,7 +7398,11 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_add_nc_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6453,7 +7429,11 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6480,7 +7460,11 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6507,7 +7491,11 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6534,7 +7522,11 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6561,7 +7553,11 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6588,7 +7584,11 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6615,7 +7615,11 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6642,7 +7646,11 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6669,7 +7677,11 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6696,7 +7708,11 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6723,7 +7739,11 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6750,7 +7770,11 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6777,7 +7801,11 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6804,7 +7832,11 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6831,7 +7863,11 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6858,7 +7894,11 @@ VCmpTruF32Vop3::VCmpTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6889,7 +7929,11 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6920,7 +7964,11 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6951,7 +7999,11 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6982,7 +8034,11 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7013,7 +8069,11 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7044,7 +8104,11 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7075,7 +8139,11 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7106,7 +8174,11 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7137,7 +8209,11 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7168,7 +8244,12 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7199,7 +8280,12 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7230,7 +8316,12 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7261,7 +8352,12 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7292,7 +8388,12 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7323,7 +8424,12 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7354,7 +8460,12 @@ VCmpxTruF32Vop3::VCmpxTruF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7383,7 +8494,11 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7412,7 +8527,11 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7441,7 +8560,11 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7470,7 +8593,11 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7499,7 +8626,11 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7528,7 +8659,11 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7557,7 +8692,11 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7586,7 +8725,11 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7615,7 +8758,11 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7644,7 +8791,11 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7673,7 +8824,11 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7702,7 +8857,11 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7731,7 +8890,11 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7760,7 +8923,11 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7789,7 +8956,11 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7818,7 +8989,11 @@ VCmpTruF64Vop3::VCmpTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7851,7 +9026,11 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7884,7 +9063,11 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7917,7 +9100,11 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7950,7 +9137,11 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7983,7 +9174,11 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8016,7 +9211,11 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8049,7 +9248,11 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8082,7 +9285,11 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8115,7 +9322,11 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8148,7 +9359,12 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8181,7 +9397,12 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8214,7 +9435,12 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8247,7 +9473,12 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8280,7 +9511,12 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8313,7 +9549,12 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8346,7 +9587,12 @@ VCmpxTruF64Vop3::VCmpxTruF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8373,7 +9619,11 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8400,7 +9650,11 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8427,7 +9681,11 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8454,7 +9712,11 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8481,7 +9743,11 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8508,7 +9774,11 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8535,7 +9805,11 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8562,7 +9836,11 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8589,7 +9867,12 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8618,7 +9901,11 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8647,7 +9934,11 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8676,7 +9967,11 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8705,7 +10000,11 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8734,7 +10033,11 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8763,7 +10066,11 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8792,7 +10099,12 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8823,7 +10135,11 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8854,7 +10170,11 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8885,7 +10205,11 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8916,7 +10240,11 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8947,7 +10275,11 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8978,7 +10310,11 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9009,7 +10345,11 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9040,7 +10380,11 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9071,7 +10415,12 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9104,7 +10453,11 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9137,7 +10490,11 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9170,7 +10527,11 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9203,7 +10564,11 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9236,7 +10601,11 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9269,7 +10638,11 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9302,7 +10675,12 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9331,7 +10709,11 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9360,7 +10742,11 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9389,7 +10775,11 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9418,7 +10808,11 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9447,7 +10841,11 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9476,7 +10874,11 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9505,7 +10907,11 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9534,7 +10940,11 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9562,7 +10972,12 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9591,7 +11006,11 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9620,7 +11039,11 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9649,7 +11072,11 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9678,7 +11105,11 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9707,7 +11138,11 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9736,7 +11171,11 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9769,7 +11208,11 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9802,7 +11245,11 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9835,7 +11282,11 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9868,7 +11319,11 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9901,7 +11356,11 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9934,7 +11393,11 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9967,7 +11430,11 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10000,7 +11467,11 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10032,7 +11503,12 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_class_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10065,7 +11541,11 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10098,7 +11578,11 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10131,7 +11615,11 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10164,7 +11652,11 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10197,7 +11689,11 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10230,7 +11726,11 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10257,7 +11757,11 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10284,7 +11788,11 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10311,7 +11819,11 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10338,7 +11850,11 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10365,7 +11881,11 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10392,7 +11912,11 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10419,7 +11943,11 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10446,7 +11974,11 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10475,7 +12007,11 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10504,7 +12040,11 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10533,7 +12073,11 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10562,7 +12106,11 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10591,7 +12139,11 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10620,7 +12172,11 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10649,7 +12205,11 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10678,7 +12238,11 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10709,7 +12273,11 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10740,7 +12308,11 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10771,7 +12343,11 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10802,7 +12378,11 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10833,7 +12413,11 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10864,7 +12448,11 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10895,7 +12483,11 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10926,7 +12518,11 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10959,7 +12555,11 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10992,7 +12592,11 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11025,7 +12629,11 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11058,7 +12666,11 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11091,7 +12703,11 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11124,7 +12740,11 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11157,7 +12777,11 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11190,7 +12814,11 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11219,7 +12847,11 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11248,7 +12880,11 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11277,7 +12913,11 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11306,7 +12946,11 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11335,7 +12979,11 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11364,7 +13012,11 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11393,7 +13045,11 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11422,7 +13078,11 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11451,7 +13111,11 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11480,7 +13144,11 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11509,7 +13177,11 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11538,7 +13210,11 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11567,7 +13243,11 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11596,7 +13276,11 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11625,7 +13309,11 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11654,7 +13342,11 @@ VCmpTruF16Vop3::VCmpTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmp_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11687,7 +13379,11 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_f_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11720,7 +13416,11 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_lt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11753,7 +13453,11 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11786,7 +13490,11 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_le_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11819,7 +13527,11 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_gt_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11852,7 +13564,11 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ne_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11885,7 +13601,11 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ge_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11918,7 +13638,11 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_t_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11951,7 +13675,11 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11984,7 +13712,12 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12017,7 +13750,12 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12050,7 +13788,12 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12083,7 +13826,12 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12116,7 +13864,12 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12149,7 +13902,12 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12182,7 +13940,12 @@ VCmpxTruF16Vop3::VCmpxTruF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3::validate_encoding( + "v_cmpx_tru_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12213,7 +13976,12 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12244,7 +14012,12 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12275,7 +14048,12 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12310,7 +14088,12 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12351,7 +14134,12 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_div_scale_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12388,7 +14176,12 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_u64_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12425,7 +14218,12 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_mad_i64_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12454,7 +14252,12 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12483,7 +14286,12 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12512,7 +14320,12 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3SdstEnc::validate_encoding( + "v_subrev_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3p.cpp index 0fb305948880..961e6b93ebc4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,7 +40,11 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -68,7 +71,12 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_lo_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -95,7 +103,11 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +134,11 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -149,7 +165,12 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshlrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -176,7 +197,12 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_lshrrev_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +229,12 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_ashrrev_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -230,7 +261,11 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -257,7 +292,11 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +329,11 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mad_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -317,7 +360,11 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -344,7 +391,11 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_sub_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +422,11 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +453,11 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -431,7 +490,11 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_fma_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -458,7 +521,11 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +552,11 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +583,11 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -539,7 +614,11 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_pk_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +651,12 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -605,7 +689,12 @@ VDot2I32I16Vop3p::VDot2I32I16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2I32I16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2I32I16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +727,12 @@ VDot2U32U16Vop3p::VDot2U32U16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2U32U16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2U32U16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot2_u32_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -671,7 +765,12 @@ VDot4I32I8Vop3p::VDot4I32I8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4I32I8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32I8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -704,7 +803,12 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot4_u32_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -737,7 +841,12 @@ VDot8I32I4Vop3p::VDot8I32I4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8I32I4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32I4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_i32_i4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -770,7 +879,12 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_dot8_u32_u4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -803,7 +917,12 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_fma_mix_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -837,7 +956,12 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_fma_mixlo_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1001,12 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vop3p::validate_encoding( + "v_fma_mixhi_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp index b18060d6c0cf..06bd82535f60 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -30,9 +29,6 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -60,7 +56,18 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f32_sdwa" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -83,9 +90,6 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -113,7 +117,18 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f32_sdwa" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -136,9 +151,6 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -166,7 +178,18 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f32_sdwa" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -189,9 +212,6 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -219,7 +239,18 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f32_sdwa" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -242,9 +273,6 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -272,7 +300,18 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f32_sdwa" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -295,9 +334,6 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -325,7 +361,18 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f32_sdwa" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -348,9 +395,6 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -378,7 +422,18 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f32_sdwa" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -400,9 +455,6 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -430,7 +482,18 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f32_sdwa" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -452,9 +515,6 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -482,7 +542,18 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f32_sdwa" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -505,9 +576,6 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -535,7 +603,18 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f32_sdwa" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -558,9 +637,6 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -588,7 +664,18 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f32_sdwa" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -611,9 +698,6 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -641,7 +725,18 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f32_sdwa" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -664,9 +759,6 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -694,7 +786,18 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f32_sdwa" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -717,9 +820,6 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -747,7 +847,18 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f32_sdwa" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -770,9 +881,6 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -800,7 +908,18 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f32_sdwa" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -823,9 +942,6 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -853,7 +969,18 @@ VCmpTruF32Vopc::VCmpTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f32_sdwa" + : "v_cmp_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -878,9 +1005,6 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -910,7 +1034,18 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f32_sdwa" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -935,9 +1070,6 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -967,7 +1099,18 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f32_sdwa" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -992,9 +1135,6 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1024,7 +1164,18 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f32_sdwa" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1049,9 +1200,6 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1081,7 +1229,18 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f32_sdwa" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1106,9 +1265,6 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1138,7 +1294,18 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f32_sdwa" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1163,9 +1330,6 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1195,7 +1359,18 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f32_sdwa" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1220,9 +1395,6 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1252,7 +1424,18 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f32_sdwa" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1277,9 +1460,6 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1309,7 +1489,18 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f32_sdwa" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1334,9 +1525,6 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1366,7 +1554,18 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f32_sdwa" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1391,9 +1590,6 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1423,7 +1619,19 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f32_sdwa" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1448,9 +1656,6 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1480,7 +1685,19 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f32_sdwa" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1505,9 +1722,6 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1537,7 +1751,19 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f32_sdwa" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1562,9 +1788,6 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1594,7 +1817,19 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f32_sdwa" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1619,9 +1854,6 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1651,7 +1883,19 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f32_sdwa" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1676,9 +1920,6 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1708,7 +1949,19 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f32_sdwa" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1733,9 +1986,6 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_TRU_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -1765,7 +2015,19 @@ VCmpxTruF32Vopc::VCmpxTruF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f32_sdwa" + : "v_cmpx_tru_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1786,16 +2048,21 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1816,16 +2083,21 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1846,16 +2118,21 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1876,16 +2153,21 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1906,16 +2188,21 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1936,16 +2223,21 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1966,16 +2258,21 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -1996,16 +2293,21 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_O_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2026,16 +2328,21 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_U_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2056,16 +2363,21 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2086,16 +2398,21 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLG_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2116,16 +2433,21 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NGT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2146,16 +2468,21 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLE_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2176,16 +2503,21 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2206,16 +2538,21 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NLT_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2236,16 +2573,21 @@ VCmpTruF64Vopc::VCmpTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_TRU_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2268,18 +2610,23 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2302,18 +2649,23 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2336,18 +2688,23 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2370,18 +2727,23 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2404,18 +2766,23 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2438,18 +2805,23 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LG_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2472,18 +2844,23 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2506,18 +2883,23 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_O_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_o_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2540,18 +2922,23 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_U_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_u_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2574,18 +2961,24 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nge_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2608,18 +3001,24 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlg_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2642,18 +3041,24 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ngt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2676,18 +3081,24 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nle_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2710,18 +3121,24 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_neq_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2744,18 +3161,24 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_nlt_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2778,18 +3201,24 @@ VCmpxTruF64Vopc::VCmpxTruF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_TRU_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTruF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_tru_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -2811,9 +3240,6 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2841,7 +3267,18 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_i32_sdwa" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2864,9 +3301,6 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2894,7 +3328,18 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i32_sdwa" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2917,9 +3362,6 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -2947,7 +3389,18 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i32_sdwa" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2970,9 +3423,6 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3000,7 +3450,18 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i32_sdwa" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3023,9 +3484,6 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3053,7 +3511,18 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i32_sdwa" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3076,9 +3545,6 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3106,7 +3572,18 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i32_sdwa" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3129,9 +3606,6 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3159,7 +3633,18 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i32_sdwa" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3181,9 +3666,6 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3211,7 +3693,18 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_i32_sdwa" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3234,9 +3727,6 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3264,7 +3754,19 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f32_sdwa" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3288,9 +3790,6 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3318,7 +3817,18 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_i16_sdwa" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3342,9 +3852,6 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3372,7 +3879,18 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_i16_sdwa" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3396,9 +3914,6 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3426,7 +3941,18 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_i16_sdwa" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3450,9 +3976,6 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3480,7 +4003,18 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_i16_sdwa" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3504,9 +4038,6 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3534,7 +4065,18 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_i16_sdwa" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3558,9 +4100,6 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3588,7 +4127,18 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_i16_sdwa" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3612,9 +4162,6 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3642,7 +4189,19 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_class_f16_sdwa" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3667,9 +4226,6 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3699,7 +4255,18 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_i32_sdwa" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3724,9 +4291,6 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3756,7 +4320,18 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i32_sdwa" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3781,9 +4356,6 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3813,7 +4385,18 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i32_sdwa" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3838,9 +4421,6 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3870,7 +4450,18 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i32_sdwa" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3895,9 +4486,6 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3927,7 +4515,18 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i32_sdwa" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3952,9 +4551,6 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -3984,7 +4580,18 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i32_sdwa" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4009,9 +4616,6 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4041,7 +4645,18 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i32_sdwa" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4066,9 +4681,6 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4098,7 +4710,18 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_i32_sdwa" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4123,9 +4746,6 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4155,7 +4775,19 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f32_sdwa" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4181,9 +4813,6 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4213,7 +4842,18 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_i16_sdwa" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4239,9 +4879,6 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4271,7 +4908,18 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_i16_sdwa" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4297,9 +4945,6 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4329,7 +4974,18 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_i16_sdwa" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4355,9 +5011,6 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4387,7 +5040,18 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_i16_sdwa" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4413,9 +5077,6 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4445,7 +5106,18 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_i16_sdwa" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4471,9 +5143,6 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4503,7 +5172,18 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_i16_sdwa" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4529,9 +5209,6 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4561,7 +5238,19 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_class_f16_sdwa" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4582,16 +5271,21 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4612,16 +5306,21 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4642,16 +5341,21 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4672,16 +5376,21 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4702,16 +5411,21 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4732,16 +5446,21 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4762,16 +5481,21 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4792,16 +5516,21 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_I64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4822,16 +5551,22 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -4855,9 +5590,6 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4885,7 +5617,18 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u16_sdwa" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4909,9 +5652,6 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4939,7 +5679,18 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u16_sdwa" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4963,9 +5714,6 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -4993,7 +5741,18 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u16_sdwa" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5017,9 +5776,6 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5047,7 +5803,18 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u16_sdwa" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5071,9 +5838,6 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5101,7 +5865,18 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u16_sdwa" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5125,9 +5900,6 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5155,7 +5927,18 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u16_sdwa" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5178,18 +5961,23 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5212,18 +6000,23 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5246,18 +6039,23 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5280,18 +6078,23 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5314,18 +6117,23 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5348,18 +6156,23 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5382,18 +6195,23 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5416,18 +6234,23 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_I64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_i64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5450,18 +6273,24 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_class_f64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -5487,9 +6316,6 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5519,7 +6345,18 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u16_sdwa" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5545,9 +6382,6 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5577,7 +6411,18 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u16_sdwa" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5603,9 +6448,6 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5635,7 +6477,18 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u16_sdwa" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5661,9 +6514,6 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5693,7 +6543,18 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u16_sdwa" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5719,9 +6580,6 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5751,7 +6609,18 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u16_sdwa" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5777,9 +6646,6 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5809,7 +6675,18 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u16_sdwa" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5831,9 +6708,6 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5861,7 +6735,18 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_u32_sdwa" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5884,9 +6769,6 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5914,7 +6796,18 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_u32_sdwa" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5937,9 +6830,6 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -5967,7 +6857,18 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_u32_sdwa" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5990,9 +6891,6 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6020,7 +6918,18 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_u32_sdwa" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6043,9 +6952,6 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6073,7 +6979,18 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_u32_sdwa" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6096,9 +7013,6 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6126,7 +7040,18 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ne_u32_sdwa" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6149,9 +7074,6 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6179,7 +7101,18 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_u32_sdwa" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6201,9 +7134,6 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6231,7 +7161,18 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_t_u32_sdwa" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6254,9 +7195,6 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6284,7 +7222,18 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_f_f16_sdwa" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6308,9 +7257,6 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6338,7 +7284,18 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lt_f16_sdwa" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6362,9 +7319,6 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6392,7 +7346,18 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_eq_f16_sdwa" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6416,9 +7381,6 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6446,7 +7408,18 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_le_f16_sdwa" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6470,9 +7443,6 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6500,7 +7470,18 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_gt_f16_sdwa" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6524,9 +7505,6 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6554,7 +7532,18 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_lg_f16_sdwa" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6578,9 +7567,6 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6608,7 +7594,18 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ge_f16_sdwa" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6631,9 +7628,6 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6661,7 +7655,18 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_o_f16_sdwa" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6686,9 +7691,6 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6718,7 +7720,18 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_u32_sdwa" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6743,9 +7756,6 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6775,7 +7785,18 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_u32_sdwa" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6800,9 +7821,6 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6832,7 +7850,18 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_u32_sdwa" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6857,9 +7886,6 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6889,7 +7915,18 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_u32_sdwa" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6914,9 +7951,6 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -6946,7 +7980,18 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_u32_sdwa" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6971,9 +8016,6 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7003,7 +8045,18 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ne_u32_sdwa" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7028,9 +8081,6 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7060,7 +8110,18 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_u32_sdwa" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7085,9 +8146,6 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U32 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(32, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7117,7 +8175,18 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_t_u32_sdwa" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7143,9 +8212,6 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7175,7 +8241,18 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_f_f16_sdwa" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7201,9 +8278,6 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7233,7 +8307,18 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lt_f16_sdwa" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7259,9 +8344,6 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7291,7 +8373,18 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_eq_f16_sdwa" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7317,9 +8410,6 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7349,7 +8439,18 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_le_f16_sdwa" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7375,9 +8476,6 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7407,7 +8505,18 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_gt_f16_sdwa" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7433,9 +8542,6 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7465,7 +8571,18 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_lg_f16_sdwa" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7491,9 +8608,6 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7523,7 +8637,18 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ge_f16_sdwa" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7549,9 +8674,6 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7581,7 +8703,18 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_o_f16_sdwa" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7602,16 +8735,21 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_F_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7632,16 +8770,21 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7662,16 +8805,21 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_EQ_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7692,16 +8840,21 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_LE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7722,16 +8875,21 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GT_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7752,16 +8910,21 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_NE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7782,16 +8945,21 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_GE_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7812,16 +8980,21 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMP_T_U64 does not support SDWA", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmp_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -7844,9 +9017,6 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7874,7 +9044,18 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_u_f16_sdwa" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7898,9 +9079,6 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7928,7 +9106,18 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nge_f16_sdwa" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7952,9 +9141,6 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -7982,7 +9168,18 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlg_f16_sdwa" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8006,9 +9203,6 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8036,7 +9230,18 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_ngt_f16_sdwa" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8060,9 +9265,6 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8090,7 +9292,18 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nle_f16_sdwa" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8114,9 +9327,6 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8144,7 +9354,18 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_neq_f16_sdwa" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8168,9 +9389,6 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8198,7 +9416,18 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_nlt_f16_sdwa" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8222,9 +9451,6 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8252,7 +9478,18 @@ VCmpTruF16Vopc::VCmpTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTruF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmp_tru_f16_sdwa" + : "v_cmp_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8275,18 +9512,23 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_F_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_f_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8309,18 +9551,23 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LT_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_lt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8343,18 +9590,23 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_eq_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8377,18 +9629,23 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_LE_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_le_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8411,18 +9668,23 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GT_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_gt_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8445,18 +9707,23 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_NE_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ne_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8479,18 +9746,23 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_GE_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_ge_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8513,18 +9785,23 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) - throw util::InvalidInst("V_CMPX_T_U64 does not support SDWA", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + "v_cmpx_t_u64_e32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support SDWA"; return std::make_unique(opcode); } } // namespace detail @@ -8550,9 +9827,6 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8582,7 +9856,18 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_u_f16_sdwa" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8608,9 +9893,6 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8640,7 +9922,19 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nge_f16_sdwa" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8666,9 +9960,6 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8698,7 +9989,19 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlg_f16_sdwa" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8724,9 +10027,6 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8756,7 +10056,19 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_ngt_f16_sdwa" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8782,9 +10094,6 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8814,7 +10123,19 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nle_f16_sdwa" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8840,9 +10161,6 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8872,7 +10190,19 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_neq_f16_sdwa" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8898,9 +10228,6 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8930,7 +10257,19 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_nlt_f16_sdwa" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8956,9 +10295,6 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_TRU_F16 does not support DPP", ""); if (reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA) { auto *sw = reinterpret_cast(inst); src0 = Operand(16, sw->s0 ? OperandType::OPR_SRC : OperandType::OPR_VGPR, sw->vsrc0); @@ -8988,7 +10324,19 @@ VCmpxTruF16Vopc::VCmpxTruF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTruF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTruF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + reinterpret_cast(inst)->src0 == amdgpu::SRC_SDWA + ? "v_cmpx_tru_f16_sdwa" + : "v_cmpx_tru_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_TRU_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.cpp index 4bc7adbecb47..5f2f2b962883 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.h" -#include "util/except.h" #include #include #include @@ -16,1397 +15,1845 @@ namespace rocjitsu { namespace rdna3 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB128Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB96Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16B16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16I8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16U8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB128Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB96Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddGsRegRtnDs(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsBvhStackRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubGsRegRtnDs(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeExpExp(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB128Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB96Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16B16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiB16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiI8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiU8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16I8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16U8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB128Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB96Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB8Flat(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode); -std::unique_ptr decodeImageBvh64IntersectRayMimg(const MachineInst *opcode); -std::unique_ptr decodeImageBvhIntersectRayMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode); -std::unique_ptr decodeLdsDirectLoadLdsdir(const MachineInst *opcode); -std::unique_ptr decodeLdsParamLoadLdsdir(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode); -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode); -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitEventSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2F16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2accF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10F16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane64B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16B16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16I8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16U8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddGsRegRtnDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBvhStackRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubGsRegRtnDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB32Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB64Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB96Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16B16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiI8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiU8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16I8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16U8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI16Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU16Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB96Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvh64IntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvhIntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeLdsDirectLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeLdsParamLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitEventSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2accF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane64B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr decodeVopd(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeVinterp(const MachineInst *opcode); - static std::unique_ptr subDecodeLdsdir(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMimg(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult decodeVopd(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1425,97 +1872,116 @@ struct DecoderImpl { static const std::array sub_decode_smem; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::decodeVopd(const MachineInst *opcode) { +DecodeResult DecoderImpl::decodeVopd(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vopd::validate_encoding(opcode, emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVinterp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vinterp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vinterp[op.op](opcode); + return sub_decode_vinterp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeLdsdir(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ldsdir::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ldsdir[op.op](opcode); + return sub_decode_ldsdir[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMimg(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mimg::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mimg[op.op](opcode); + return sub_decode_mimg[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h index 102da776edc3..83f339bea79c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA3_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace rdna3 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 3; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace rdna3 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ds.cpp index 4cbb952ccb54..45cac77f1451 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/ds.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +84,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +111,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +138,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +165,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +219,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +246,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +273,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +300,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +327,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -309,7 +356,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +381,11 @@ DsStoreB32Ds::DsStoreB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +408,12 @@ DsStore2addrB32Ds::DsStore2addrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +436,12 @@ DsStore2addrStride64B32Ds::DsStore2addrStride64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +466,12 @@ DsCmpstoreB32Ds::DsCmpstoreB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -426,7 +496,12 @@ DsCmpstoreF32Ds::DsCmpstoreF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -449,7 +524,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +551,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +568,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +595,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +612,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +632,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -549,7 +649,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +668,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -577,7 +685,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -592,7 +704,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +729,11 @@ DsStoreB8Ds::DsStoreB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -634,7 +754,11 @@ DsStoreB16Ds::DsStoreB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +783,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +812,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -709,7 +841,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -734,7 +870,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -759,7 +899,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -784,7 +928,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +957,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +986,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1015,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -884,7 +1044,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -909,7 +1073,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1102,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -961,7 +1133,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -986,7 +1163,12 @@ DsStorexchgRtnB32Ds::DsStorexchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1013,7 +1195,12 @@ DsStorexchg2addrRtnB32Ds::DsStorexchg2addrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_2addr_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1227,13 @@ DsStorexchg2addrStride64RtnB32Ds::DsStorexchg2addrStride64RtnB32Ds(const Machine } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1260,12 @@ DsCmpstoreRtnB32Ds::DsCmpstoreRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1094,7 +1292,12 @@ DsCmpstoreRtnF32Ds::DsCmpstoreRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1119,7 +1322,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1351,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1170,7 +1381,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,7 +1402,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1427,11 @@ DsLoadB32Ds::DsLoadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1229,7 +1452,12 @@ DsLoad2addrB32Ds::DsLoad2addrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1250,7 +1478,12 @@ DsLoad2addrStride64B32Ds::DsLoad2addrStride64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1504,11 @@ DsLoadI8Ds::DsLoadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1292,7 +1529,11 @@ DsLoadU8Ds::DsLoadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1313,7 +1554,11 @@ DsLoadI16Ds::DsLoadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1334,7 +1579,11 @@ DsLoadU16Ds::DsLoadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1355,7 +1604,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1376,7 +1629,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1658,12 @@ DsOrderedCountDs::DsOrderedCountDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode) { +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_ordered_count", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1424,7 +1686,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1713,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1470,7 +1740,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1493,7 +1767,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1516,7 +1794,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1539,7 +1821,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1562,7 +1848,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1585,7 +1875,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1608,7 +1902,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1631,7 +1929,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1654,7 +1956,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1677,7 +1983,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1702,7 +2012,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1723,7 +2037,11 @@ DsStoreB64Ds::DsStoreB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1746,7 +2064,12 @@ DsStore2addrB64Ds::DsStore2addrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1769,7 +2092,12 @@ DsStore2addrStride64B64Ds::DsStore2addrStride64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1794,7 +2122,12 @@ DsCmpstoreB64Ds::DsCmpstoreB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,7 +2152,12 @@ DsCmpstoreF64Ds::DsCmpstoreF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1842,7 +2180,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1865,7 +2207,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1890,7 +2236,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1915,7 +2265,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1940,7 +2294,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1965,7 +2323,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1990,7 +2352,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2015,7 +2381,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2040,7 +2410,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2065,7 +2439,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2090,7 +2468,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2115,7 +2497,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2140,7 +2526,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2165,7 +2555,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2192,7 +2586,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2217,7 +2616,12 @@ DsStorexchgRtnB64Ds::DsStorexchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2244,7 +2648,12 @@ DsStorexchg2addrRtnB64Ds::DsStorexchg2addrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_2addr_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2271,7 +2680,13 @@ DsStorexchg2addrStride64RtnB64Ds::DsStorexchg2addrStride64RtnB64Ds(const Machine } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2298,7 +2713,12 @@ DsCmpstoreRtnB64Ds::DsCmpstoreRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2745,12 @@ DsCmpstoreRtnF64Ds::DsCmpstoreRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2350,7 +2775,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2375,7 +2804,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2396,7 +2829,11 @@ DsLoadB64Ds::DsLoadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2417,7 +2854,12 @@ DsLoad2addrB64Ds::DsLoad2addrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2438,7 +2880,12 @@ DsLoad2addrStride64B64Ds::DsLoad2addrStride64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2463,7 +2910,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2480,7 +2931,12 @@ DsAddGsRegRtnDs::DsAddGsRegRtnDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddGsRegRtnDs(const MachineInst *opcode) { +DecodeResult decodeDsAddGsRegRtnDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_gs_reg_rtn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2497,7 +2953,12 @@ DsSubGsRegRtnDs::DsSubGsRegRtnDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubGsRegRtnDs(const MachineInst *opcode) { +DecodeResult decodeDsSubGsRegRtnDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_gs_reg_rtn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2522,7 +2983,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2543,7 +3009,12 @@ DsStoreB8D16HiDs::DsStoreB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2564,7 +3035,12 @@ DsStoreB16D16HiDs::DsStoreB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2585,7 +3061,11 @@ DsLoadU8D16Ds::DsLoadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2612,7 +3092,12 @@ DsLoadU8D16HiDs::DsLoadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2639,7 +3124,11 @@ DsLoadI8D16Ds::DsLoadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2666,7 +3155,12 @@ DsLoadI8D16HiDs::DsLoadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2693,7 +3187,11 @@ DsLoadU16D16Ds::DsLoadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2720,7 +3218,12 @@ DsLoadU16D16HiDs::DsLoadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3256,12 @@ DsBvhStackRtnB32Ds::DsBvhStackRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBvhStackRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBvhStackRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bvh_stack_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2774,7 +3282,12 @@ DsStoreAddtidB32Ds::DsStoreAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2795,7 +3308,12 @@ DsLoadAddtidB32Ds::DsLoadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2814,7 +3332,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2833,7 +3355,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2854,7 +3381,11 @@ DsStoreB96Ds::DsStoreB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2875,7 +3406,11 @@ DsStoreB128Ds::DsStoreB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2896,7 +3431,11 @@ DsLoadB96Ds::DsLoadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2917,7 +3456,11 @@ DsLoadB128Ds::DsLoadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp index 033c560753fe..236aa8357ecc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.cpp @@ -5,7 +5,6 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h" -#include "util/except.h" #include #include @@ -1157,9 +1156,6 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -1257,9 +1253,6 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -1466,9 +1459,6 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h index 6cf1495e5c70..be4cd33bc1c5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/rdna3/isa.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include @@ -503,6 +504,15 @@ class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3MachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -529,6 +539,15 @@ class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3pMachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -618,6 +637,15 @@ class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3SdstEncMachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/exp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/exp.cpp index 1127bfc70a69..56967a5088aa 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/exp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/exp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/exp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ ExpExp::ExpExp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeExpExp(const MachineInst *opcode) { +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Exp::validate_encoding("exp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/flat.cpp index f87c5f9c7dab..bbea9938439b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/flat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/flat.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -40,7 +39,11 @@ FlatLoadU8Flat::FlatLoadU8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +75,11 @@ FlatLoadI8Flat::FlatLoadI8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -104,7 +111,12 @@ FlatLoadU16Flat::FlatLoadU16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -136,7 +148,12 @@ FlatLoadI16Flat::FlatLoadI16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +185,12 @@ FlatLoadB32Flat::FlatLoadB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -200,7 +222,12 @@ FlatLoadB64Flat::FlatLoadB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +259,12 @@ FlatLoadB96Flat::FlatLoadB96Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB96Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB96Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +296,12 @@ FlatLoadB128Flat::FlatLoadB128Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB128Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +333,12 @@ FlatStoreB8Flat::FlatStoreB8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -328,7 +370,12 @@ FlatStoreB16Flat::FlatStoreB16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +407,12 @@ FlatStoreB32Flat::FlatStoreB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -392,7 +444,12 @@ FlatStoreB64Flat::FlatStoreB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +481,12 @@ FlatStoreB96Flat::FlatStoreB96Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB96Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB96Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +518,12 @@ FlatStoreB128Flat::FlatStoreB128Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB128Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +555,12 @@ FlatLoadD16U8Flat::FlatLoadD16U8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16U8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16U8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -526,7 +598,12 @@ FlatLoadD16I8Flat::FlatLoadD16I8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16I8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16I8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +641,12 @@ FlatLoadD16B16Flat::FlatLoadD16B16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16B16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16B16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +684,12 @@ FlatLoadD16HiU8Flat::FlatLoadD16HiU8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiU8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiU8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,7 +727,12 @@ FlatLoadD16HiI8Flat::FlatLoadD16HiI8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiI8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiI8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +770,12 @@ FlatLoadD16HiB16Flat::FlatLoadD16HiB16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiB16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -716,7 +813,12 @@ FlatStoreD16HiB8Flat::FlatStoreD16HiB8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -748,7 +850,12 @@ FlatStoreD16HiB16Flat::FlatStoreD16HiB16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -783,7 +890,12 @@ FlatAtomicSwapB32Flat::FlatAtomicSwapB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -818,7 +930,12 @@ FlatAtomicCmpswapB32Flat::FlatAtomicCmpswapB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -853,7 +970,12 @@ FlatAtomicAddU32Flat::FlatAtomicAddU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -888,7 +1010,12 @@ FlatAtomicSubU32Flat::FlatAtomicSubU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1050,12 @@ FlatAtomicMinI32Flat::FlatAtomicMinI32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1090,12 @@ FlatAtomicMinU32Flat::FlatAtomicMinU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -993,7 +1130,12 @@ FlatAtomicMaxI32Flat::FlatAtomicMaxI32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1028,7 +1170,12 @@ FlatAtomicMaxU32Flat::FlatAtomicMaxU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1063,7 +1210,12 @@ FlatAtomicAndB32Flat::FlatAtomicAndB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1250,12 @@ FlatAtomicOrB32Flat::FlatAtomicOrB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1133,7 +1290,12 @@ FlatAtomicXorB32Flat::FlatAtomicXorB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1168,7 +1330,12 @@ FlatAtomicIncU32Flat::FlatAtomicIncU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1203,7 +1370,12 @@ FlatAtomicDecU32Flat::FlatAtomicDecU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1410,12 @@ FlatAtomicSwapB64Flat::FlatAtomicSwapB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1273,7 +1450,12 @@ FlatAtomicCmpswapB64Flat::FlatAtomicCmpswapB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1308,7 +1490,12 @@ FlatAtomicAddU64Flat::FlatAtomicAddU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1343,7 +1530,12 @@ FlatAtomicSubU64Flat::FlatAtomicSubU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1378,7 +1570,12 @@ FlatAtomicMinI64Flat::FlatAtomicMinI64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1413,7 +1610,12 @@ FlatAtomicMinU64Flat::FlatAtomicMinU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1448,7 +1650,12 @@ FlatAtomicMaxI64Flat::FlatAtomicMaxI64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1483,7 +1690,12 @@ FlatAtomicMaxU64Flat::FlatAtomicMaxU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1730,12 @@ FlatAtomicAndB64Flat::FlatAtomicAndB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1553,7 +1770,12 @@ FlatAtomicOrB64Flat::FlatAtomicOrB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1588,7 +1810,12 @@ FlatAtomicXorB64Flat::FlatAtomicXorB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1623,7 +1850,12 @@ FlatAtomicIncU64Flat::FlatAtomicIncU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1658,7 +1890,12 @@ FlatAtomicDecU64Flat::FlatAtomicDecU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1693,7 +1930,12 @@ FlatAtomicCmpswapF32Flat::FlatAtomicCmpswapF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1728,7 +1970,12 @@ FlatAtomicMinF32Flat::FlatAtomicMinF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1763,7 +2010,12 @@ FlatAtomicMaxF32Flat::FlatAtomicMaxF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1798,7 +2050,12 @@ FlatAtomicAddF32Flat::FlatAtomicAddF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ldsdir.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ldsdir.cpp index 52d69baf499f..ede255d6cd95 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ldsdir.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/ldsdir.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/ldsdir.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,12 @@ LdsParamLoadLdsdir::LdsParamLoadLdsdir(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeLdsParamLoadLdsdir(const MachineInst *opcode) { +DecodeResult decodeLdsParamLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ldsdir::validate_encoding( + "lds_param_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ LdsDirectLoadLdsdir::LdsDirectLoadLdsdir(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeLdsDirectLoadLdsdir(const MachineInst *opcode) { +DecodeResult decodeLdsDirectLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ldsdir::validate_encoding( + "lds_direct_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mimg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mimg.cpp index 8ff6c5ee61a9..e4d0715c939d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mimg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mimg.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/mimg.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -26,7 +25,11 @@ ImageLoadMimg::ImageLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -45,7 +48,12 @@ ImageLoadMipMimg::ImageLoadMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +72,12 @@ ImageLoadPckMimg::ImageLoadPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +96,12 @@ ImageLoadPckSgnMimg::ImageLoadPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +120,12 @@ ImageLoadMipPckMimg::ImageLoadMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +144,12 @@ ImageLoadMipPckSgnMimg::ImageLoadMipPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ ImageStoreMimg::ImageStoreMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +191,12 @@ ImageStoreMipMimg::ImageStoreMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +215,12 @@ ImageStorePckMimg::ImageStorePckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +239,12 @@ ImageStoreMipPckMimg::ImageStoreMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -217,7 +264,12 @@ ImageAtomicSwapMimg::ImageAtomicSwapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -237,7 +289,12 @@ ImageAtomicCmpswapMimg::ImageAtomicCmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -257,7 +314,12 @@ ImageAtomicAddMimg::ImageAtomicAddMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -277,7 +339,12 @@ ImageAtomicSubMimg::ImageAtomicSubMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -297,7 +364,12 @@ ImageAtomicSminMimg::ImageAtomicSminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -317,7 +389,12 @@ ImageAtomicUminMimg::ImageAtomicUminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +414,12 @@ ImageAtomicSmaxMimg::ImageAtomicSmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +439,12 @@ ImageAtomicUmaxMimg::ImageAtomicUmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -377,7 +464,12 @@ ImageAtomicAndMimg::ImageAtomicAndMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -397,7 +489,12 @@ ImageAtomicOrMimg::ImageAtomicOrMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -417,7 +514,12 @@ ImageAtomicXorMimg::ImageAtomicXorMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +539,12 @@ ImageAtomicIncMimg::ImageAtomicIncMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +564,12 @@ ImageAtomicDecMimg::ImageAtomicDecMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +588,12 @@ ImageGetResinfoMimg::ImageGetResinfoMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +612,12 @@ ImageMsaaLoadMimg::ImageMsaaLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_msaa_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -514,7 +636,12 @@ ImageBvhIntersectRayMimg::ImageBvhIntersectRayMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvhIntersectRayMimg(const MachineInst *opcode) { +DecodeResult decodeImageBvhIntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_bvh_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -533,7 +660,12 @@ ImageBvh64IntersectRayMimg::ImageBvh64IntersectRayMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvh64IntersectRayMimg(const MachineInst *opcode) { +DecodeResult decodeImageBvh64IntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_bvh64_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +686,12 @@ ImageSampleMimg::ImageSampleMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -575,7 +712,12 @@ ImageSampleDMimg::ImageSampleDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -596,7 +738,12 @@ ImageSampleLMimg::ImageSampleLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +764,12 @@ ImageSampleBMimg::ImageSampleBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +790,12 @@ ImageSampleLzMimg::ImageSampleLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +816,12 @@ ImageSampleCMimg::ImageSampleCMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -680,7 +842,12 @@ ImageSampleCDMimg::ImageSampleCDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -701,7 +868,12 @@ ImageSampleCLMimg::ImageSampleCLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -722,7 +894,12 @@ ImageSampleCBMimg::ImageSampleCBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -743,7 +920,12 @@ ImageSampleCLzMimg::ImageSampleCLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -764,7 +946,12 @@ ImageSampleOMimg::ImageSampleOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -785,7 +972,12 @@ ImageSampleDOMimg::ImageSampleDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -806,7 +998,12 @@ ImageSampleLOMimg::ImageSampleLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -827,7 +1024,12 @@ ImageSampleBOMimg::ImageSampleBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -848,7 +1050,12 @@ ImageSampleLzOMimg::ImageSampleLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -869,7 +1076,12 @@ ImageSampleCOMimg::ImageSampleCOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1102,12 @@ ImageSampleCDOMimg::ImageSampleCDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -911,7 +1128,12 @@ ImageSampleCLOMimg::ImageSampleCLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -932,7 +1154,12 @@ ImageSampleCBOMimg::ImageSampleCBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -953,7 +1180,12 @@ ImageSampleCLzOMimg::ImageSampleCLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -974,7 +1206,12 @@ ImageGather4Mimg::ImageGather4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1232,12 @@ ImageGather4LMimg::ImageGather4LMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1258,12 @@ ImageGather4BMimg::ImageGather4BMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1037,7 +1284,12 @@ ImageGather4LzMimg::ImageGather4LzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1058,7 +1310,12 @@ ImageGather4CMimg::ImageGather4CMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1079,7 +1336,12 @@ ImageGather4CLzMimg::ImageGather4CLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1100,7 +1362,12 @@ ImageGather4OMimg::ImageGather4OMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1388,12 @@ ImageGather4LzOMimg::ImageGather4LzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1414,12 @@ ImageGather4CLzOMimg::ImageGather4CLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1163,7 +1440,12 @@ ImageGetLodMimg::ImageGetLodMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_lod", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1184,7 +1466,12 @@ ImageSampleDG16Mimg::ImageSampleDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1492,12 @@ ImageSampleCDG16Mimg::ImageSampleCDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1226,7 +1518,12 @@ ImageSampleDOG16Mimg::ImageSampleDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1247,7 +1544,12 @@ ImageSampleCDOG16Mimg::ImageSampleCDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1268,7 +1570,12 @@ ImageSampleClMimg::ImageSampleClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1289,7 +1596,12 @@ ImageSampleDClMimg::ImageSampleDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1310,7 +1622,12 @@ ImageSampleBClMimg::ImageSampleBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,7 +1648,12 @@ ImageSampleCClMimg::ImageSampleCClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1674,12 @@ ImageSampleCDClMimg::ImageSampleCDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1373,7 +1700,12 @@ ImageSampleCBClMimg::ImageSampleCBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1726,12 @@ ImageSampleClOMimg::ImageSampleClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1415,7 +1752,12 @@ ImageSampleDClOMimg::ImageSampleDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1436,7 +1778,12 @@ ImageSampleBClOMimg::ImageSampleBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1804,12 @@ ImageSampleCClOMimg::ImageSampleCClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1478,7 +1830,12 @@ ImageSampleCDClOMimg::ImageSampleCDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1499,7 +1856,12 @@ ImageSampleCBClOMimg::ImageSampleCBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1882,12 @@ ImageSampleCDClG16Mimg::ImageSampleCDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1908,12 @@ ImageSampleDClOG16Mimg::ImageSampleDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1562,7 +1934,12 @@ ImageSampleCDClOG16Mimg::ImageSampleCDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1583,7 +1960,12 @@ ImageSampleDClG16Mimg::ImageSampleDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1986,12 @@ ImageGather4ClMimg::ImageGather4ClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1625,7 +2012,12 @@ ImageGather4BClMimg::ImageGather4BClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1646,7 +2038,12 @@ ImageGather4CClMimg::ImageGather4CClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1667,7 +2064,12 @@ ImageGather4CLMimg::ImageGather4CLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1688,7 +2090,12 @@ ImageGather4CBMimg::ImageGather4CBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1709,7 +2116,12 @@ ImageGather4CBClMimg::ImageGather4CBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1730,7 +2142,12 @@ ImageGather4hMimg::ImageGather4hMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mtbuf.cpp index 7923775f5f6a..498d959767ff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mtbuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/mtbuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +70,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +128,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -138,7 +157,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +186,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +215,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -210,7 +244,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +273,12 @@ TbufferLoadD16FormatXMtbuf::TbufferLoadD16FormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_d16_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +308,13 @@ TbufferLoadD16FormatXyMtbuf::TbufferLoadD16FormatXyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +338,13 @@ TbufferLoadD16FormatXyzMtbuf::TbufferLoadD16FormatXyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +374,13 @@ TbufferLoadD16FormatXyzwMtbuf::TbufferLoadD16FormatXyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +404,13 @@ TbufferStoreD16FormatXMtbuf::TbufferStoreD16FormatXMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +434,13 @@ TbufferStoreD16FormatXyMtbuf::TbufferStoreD16FormatXyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +464,13 @@ TbufferStoreD16FormatXyzMtbuf::TbufferStoreD16FormatXyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -414,7 +494,13 @@ TbufferStoreD16FormatXyzwMtbuf::TbufferStoreD16FormatXyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mubuf.cpp index 39cfbfcd9a8a..435d6ceddc6a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/mubuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/mubuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +70,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +128,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -138,7 +157,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +186,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +215,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -210,7 +244,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +273,12 @@ BufferLoadD16FormatXMubuf::BufferLoadD16FormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +308,12 @@ BufferLoadD16FormatXyMubuf::BufferLoadD16FormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +337,13 @@ BufferLoadD16FormatXyzMubuf::BufferLoadD16FormatXyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +373,13 @@ BufferLoadD16FormatXyzwMubuf::BufferLoadD16FormatXyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +403,12 @@ BufferStoreD16FormatXMubuf::BufferStoreD16FormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_d16_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +432,13 @@ BufferStoreD16FormatXyMubuf::BufferStoreD16FormatXyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +462,13 @@ BufferStoreD16FormatXyzMubuf::BufferStoreD16FormatXyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -414,7 +492,13 @@ BufferStoreD16FormatXyzwMubuf::BufferStoreD16FormatXyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -438,7 +522,12 @@ BufferLoadU8Mubuf::BufferLoadU8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -462,7 +551,12 @@ BufferLoadI8Mubuf::BufferLoadI8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +580,12 @@ BufferLoadU16Mubuf::BufferLoadU16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -510,7 +609,12 @@ BufferLoadI16Mubuf::BufferLoadI16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -534,7 +638,12 @@ BufferLoadB32Mubuf::BufferLoadB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -558,7 +667,12 @@ BufferLoadB64Mubuf::BufferLoadB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +696,12 @@ BufferLoadB96Mubuf::BufferLoadB96Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB96Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -606,7 +725,12 @@ BufferLoadB128Mubuf::BufferLoadB128Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB128Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -630,7 +754,12 @@ BufferStoreB8Mubuf::BufferStoreB8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -654,7 +783,12 @@ BufferStoreB16Mubuf::BufferStoreB16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +812,12 @@ BufferStoreB32Mubuf::BufferStoreB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -702,7 +841,12 @@ BufferStoreB64Mubuf::BufferStoreB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +870,12 @@ BufferStoreB96Mubuf::BufferStoreB96Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB96Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -750,7 +899,12 @@ BufferStoreB128Mubuf::BufferStoreB128Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB128Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -774,7 +928,12 @@ BufferLoadD16U8Mubuf::BufferLoadD16U8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16U8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16U8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +963,12 @@ BufferLoadD16I8Mubuf::BufferLoadD16I8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16I8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16I8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +998,12 @@ BufferLoadD16B16Mubuf::BufferLoadD16B16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16B16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16B16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +1033,12 @@ BufferLoadD16HiU8Mubuf::BufferLoadD16HiU8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1068,12 @@ BufferLoadD16HiI8Mubuf::BufferLoadD16HiI8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1103,12 @@ BufferLoadD16HiB16Mubuf::BufferLoadD16HiB16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -954,7 +1138,12 @@ BufferStoreD16HiB8Mubuf::BufferStoreD16HiB8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -978,7 +1167,12 @@ BufferStoreD16HiB16Mubuf::BufferStoreD16HiB16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1002,7 +1196,13 @@ BufferLoadD16HiFormatXMubuf::BufferLoadD16HiFormatXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_d16_hi_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1232,13 @@ BufferStoreD16HiFormatXMubuf::BufferStoreD16HiFormatXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_hi_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1045,7 +1251,12 @@ BufferGl0InvMubuf::BufferGl0InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl0_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1058,7 +1269,12 @@ BufferGl1InvMubuf::BufferGl1InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1084,7 +1300,12 @@ BufferAtomicSwapB32Mubuf::BufferAtomicSwapB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1111,7 +1332,12 @@ BufferAtomicCmpswapB32Mubuf::BufferAtomicCmpswapB32Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1137,7 +1363,12 @@ BufferAtomicAddU32Mubuf::BufferAtomicAddU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1163,7 +1394,12 @@ BufferAtomicSubU32Mubuf::BufferAtomicSubU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1189,7 +1425,12 @@ BufferAtomicCsubU32Mubuf::BufferAtomicCsubU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_csub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1215,7 +1456,12 @@ BufferAtomicMinI32Mubuf::BufferAtomicMinI32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1241,7 +1487,12 @@ BufferAtomicMinU32Mubuf::BufferAtomicMinU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1267,7 +1518,12 @@ BufferAtomicMaxI32Mubuf::BufferAtomicMaxI32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,7 +1549,12 @@ BufferAtomicMaxU32Mubuf::BufferAtomicMaxU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1319,7 +1580,12 @@ BufferAtomicAndB32Mubuf::BufferAtomicAndB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1345,7 +1611,12 @@ BufferAtomicOrB32Mubuf::BufferAtomicOrB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1371,7 +1642,12 @@ BufferAtomicXorB32Mubuf::BufferAtomicXorB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1397,7 +1673,12 @@ BufferAtomicIncU32Mubuf::BufferAtomicIncU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1423,7 +1704,12 @@ BufferAtomicDecU32Mubuf::BufferAtomicDecU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1449,7 +1735,12 @@ BufferAtomicSwapB64Mubuf::BufferAtomicSwapB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1476,7 +1767,12 @@ BufferAtomicCmpswapB64Mubuf::BufferAtomicCmpswapB64Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1502,7 +1798,12 @@ BufferAtomicAddU64Mubuf::BufferAtomicAddU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1528,7 +1829,12 @@ BufferAtomicSubU64Mubuf::BufferAtomicSubU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1554,7 +1860,12 @@ BufferAtomicMinI64Mubuf::BufferAtomicMinI64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1580,7 +1891,12 @@ BufferAtomicMinU64Mubuf::BufferAtomicMinU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1606,7 +1922,12 @@ BufferAtomicMaxI64Mubuf::BufferAtomicMaxI64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1632,7 +1953,12 @@ BufferAtomicMaxU64Mubuf::BufferAtomicMaxU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1658,7 +1984,12 @@ BufferAtomicAndB64Mubuf::BufferAtomicAndB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1684,7 +2015,12 @@ BufferAtomicOrB64Mubuf::BufferAtomicOrB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1710,7 +2046,12 @@ BufferAtomicXorB64Mubuf::BufferAtomicXorB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1736,7 +2077,12 @@ BufferAtomicIncU64Mubuf::BufferAtomicIncU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1762,7 +2108,12 @@ BufferAtomicDecU64Mubuf::BufferAtomicDecU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1789,7 +2140,12 @@ BufferAtomicCmpswapF32Mubuf::BufferAtomicCmpswapF32Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1815,7 +2171,12 @@ BufferAtomicMinF32Mubuf::BufferAtomicMinF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1841,7 +2202,12 @@ BufferAtomicMaxF32Mubuf::BufferAtomicMaxF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1867,7 +2233,12 @@ BufferAtomicAddF32Mubuf::BufferAtomicAddF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp index f77aa906812c..f95491279f3b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem.cpp index 71cb91eb9879..11cbc5345f75 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -34,7 +33,11 @@ SLoadB32Smem::SLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ SLoadB64Smem::SLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +81,11 @@ SLoadB128Smem::SLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -94,7 +105,11 @@ SLoadB256Smem::SLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +129,11 @@ SLoadB512Smem::SLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -134,7 +153,12 @@ SBufferLoadB32Smem::SBufferLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +178,12 @@ SBufferLoadB64Smem::SBufferLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +203,12 @@ SBufferLoadB128Smem::SBufferLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -194,7 +228,12 @@ SBufferLoadB256Smem::SBufferLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +253,12 @@ SBufferLoadB512Smem::SBufferLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -227,7 +271,11 @@ SGl1InvSmem::SGl1InvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode) { +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -240,7 +288,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1.cpp index 9853d75f8dc4..ec7327989dbc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +141,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +167,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ SCtzI32B32Sop1::SCtzI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +218,11 @@ SCtzI32B64Sop1::SCtzI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -212,7 +243,11 @@ SClzI32U32Sop1::SClzI32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +269,11 @@ SClzI32U64Sop1::SClzI32U64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -255,7 +294,11 @@ SClsI32Sop1::SClsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -277,7 +320,11 @@ SClsI32I64Sop1::SClsI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +346,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -321,7 +372,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +399,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +426,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +453,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -409,7 +480,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +506,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -454,7 +535,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +563,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +593,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +622,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +652,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -576,7 +681,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +711,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +740,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +769,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -674,7 +797,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +826,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -730,7 +861,12 @@ SAndSaveexecB32Sop1::SAndSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,7 +898,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -794,7 +935,12 @@ SOrSaveexecB32Sop1::SOrSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -827,7 +973,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +1009,12 @@ SXorSaveexecB32Sop1::SXorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1046,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -921,7 +1082,12 @@ SNandSaveexecB32Sop1::SNandSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -953,7 +1119,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -984,7 +1155,12 @@ SNorSaveexecB32Sop1::SNorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1192,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1047,7 +1228,12 @@ SXnorSaveexecB32Sop1::SXnorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1079,7 +1265,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1301,12 @@ SAndNot0SaveexecB32Sop1::SAndNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1338,12 @@ SAndNot0SaveexecB64Sop1::SAndNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1173,7 +1374,12 @@ SOrNot0SaveexecB32Sop1::SOrNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1411,12 @@ SOrNot0SaveexecB64Sop1::SOrNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1236,7 +1447,12 @@ SAndNot1SaveexecB32Sop1::SAndNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1268,7 +1484,12 @@ SAndNot1SaveexecB64Sop1::SAndNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1299,7 +1520,12 @@ SOrNot1SaveexecB32Sop1::SOrNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,7 +1557,12 @@ SOrNot1SaveexecB64Sop1::SOrNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1362,7 +1593,12 @@ SAndNot0WrexecB32Sop1::SAndNot0WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1630,12 @@ SAndNot0WrexecB64Sop1::SAndNot0WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1425,7 +1666,12 @@ SAndNot1WrexecB32Sop1::SAndNot1WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1703,12 @@ SAndNot1WrexecB64Sop1::SAndNot1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1477,7 +1728,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1753,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1521,7 +1782,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1812,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1566,7 +1837,12 @@ SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1860,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1603,7 +1883,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1626,7 +1910,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1932,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1661,7 +1953,12 @@ SSendmsgRtnB32Sop1::SSendmsgRtnB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sendmsg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1678,7 +1975,12 @@ SSendmsgRtnB64Sop1::SSendmsgRtnB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sendmsg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop2.cpp index 24682631235b..4823e9340189 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +281,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +316,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -314,7 +350,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -345,7 +385,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -406,7 +454,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +488,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +523,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -496,7 +558,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -526,7 +593,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -556,7 +628,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +662,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -616,7 +696,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -646,7 +730,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -676,7 +764,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +800,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,7 +835,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -772,7 +872,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -802,7 +906,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +942,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +976,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -896,7 +1012,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -926,7 +1046,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1082,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -988,7 +1116,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1020,7 +1152,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1186,12 @@ SAndNot1B32Sop2::SAndNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1223,12 @@ SAndNot1B64Sop2::SAndNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1258,11 @@ SOrNot1B32Sop2::SOrNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1294,11 @@ SOrNot1B64Sop2::SOrNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1174,7 +1328,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1204,7 +1362,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1235,7 +1397,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1266,7 +1432,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,7 +1463,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1320,7 +1494,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1347,7 +1525,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1374,7 +1556,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1587,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1431,7 +1621,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1463,7 +1658,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1492,7 +1692,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1725,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1757,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1575,7 +1790,12 @@ SPackHlB32B16Sop2::SPackHlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hl_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopc.cpp index 697eeb650e08..2140cfb75afb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +554,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -517,7 +588,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopk.cpp index 285c857f8636..6375d52cbd56 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -39,7 +42,11 @@ SVersionSopk::SVersionSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode) { +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_version", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,7 +68,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,7 +92,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -101,7 +116,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +140,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +164,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +188,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -181,7 +212,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -201,7 +236,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +260,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -241,7 +284,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +308,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +332,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -301,7 +356,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -322,7 +381,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -340,7 +403,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +424,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -374,7 +445,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +474,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +508,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +535,12 @@ SWaitcntVscntSopk::SWaitcntVscntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +558,12 @@ SWaitcntVmcntSopk::SWaitcntVmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +581,12 @@ SWaitcntExpcntSopk::SWaitcntExpcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_expcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -505,7 +604,12 @@ SWaitcntLgkmcntSopk::SWaitcntLgkmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_lgkmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopp.cpp index 8bed755a248e..8eeb2e3c9a01 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -37,7 +40,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +59,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +78,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,7 +97,13 @@ SSetInstPrefetchDistanceSopp::SSetInstPrefetchDistanceSopp(const MachineInst *in } namespace detail { -std::unique_ptr decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode) { +DecodeResult decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Sopp::validate_encoding("s_set_inst_prefetch_distance", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +118,11 @@ SClauseSopp::SClauseSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode) { +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_clause", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -112,7 +137,11 @@ SDelayAluSopp::SDelayAluSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode) { +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_delay_alu", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +158,12 @@ SWaitcntDepctrSopp::SWaitcntDepctrSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt_depctr", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -145,7 +179,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +197,11 @@ SWaitIdleSopp::SWaitIdleSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_idle", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +217,11 @@ SWaitEventSopp::SWaitEventSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitEventSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitEventSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_event", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,7 +236,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -205,7 +255,11 @@ SRoundModeSopp::SRoundModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode) { +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_round_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -220,7 +274,12 @@ SDenormModeSopp::SDenormModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode) { +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_denorm_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +292,11 @@ SCodeEndSopp::SCodeEndSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode) { +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_code_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +313,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -275,7 +342,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +372,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +402,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +432,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +462,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +492,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -420,7 +517,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +537,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -450,7 +557,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -465,7 +577,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -479,7 +596,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -493,7 +614,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -507,7 +633,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +651,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -535,7 +670,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -553,7 +692,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +714,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +734,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +754,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +775,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -635,7 +798,12 @@ STtracedataImmSopp::STtracedataImmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata_imm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +816,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +834,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vinterp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vinterp.cpp index cf72276021b0..c19d3c35df00 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vinterp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vinterp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vinterp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -28,7 +27,12 @@ VInterpP10F32Vinterp::VInterpP10F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p10_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ VInterpP2F32Vinterp::VInterpP2F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -70,7 +79,12 @@ VInterpP10F16F32Vinterp::VInterpP10F16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10F16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p10_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +105,12 @@ VInterpP2F16F32Vinterp::VInterpP2F16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +137,13 @@ VInterpP10RtzF16F32Vinterp::VInterpP10RtzF16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vinterp::validate_encoding("v_interp_p10_rtz_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +164,12 @@ VInterpP2RtzF16F32Vinterp::VInterpP2RtzF16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_rtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop1.cpp index 2df9e44fb247..fb6d2589bf76 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,15 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_dpp" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +71,15 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_dpp" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,13 +96,22 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_dpp" + : "v_readfirstlane_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -109,13 +133,21 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_dpp" + : "v_cvt_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -136,13 +168,21 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_dpp" + : "v_cvt_f64_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -183,7 +223,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_dpp" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +272,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_dpp" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +321,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_dpp" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +370,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_dpp" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -349,7 +421,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_dpp" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +478,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_dpp" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -439,7 +527,16 @@ VCvtNearestI32F32Vop1::VCvtNearestI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_dpp" + : "v_cvt_nearest_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -480,7 +577,16 @@ VCvtFloorI32F32Vop1::VCvtFloorI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_dpp" + : "v_cvt_floor_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +627,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_dpp" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,13 +658,21 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_dpp" + : "v_cvt_f32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -570,13 +693,21 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_dpp" + : "v_cvt_f64_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -617,7 +748,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_dpp" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -658,7 +798,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_dpp" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +848,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_dpp" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -740,7 +898,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_dpp" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,13 +929,21 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_dpp" + : "v_cvt_u32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -789,13 +964,21 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_dpp" + : "v_cvt_f64_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -817,13 +1000,21 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_dpp" + : "v_trunc_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -845,13 +1036,21 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_dpp" + : "v_ceil_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -873,13 +1072,21 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_dpp" + : "v_rndne_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -901,13 +1108,21 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_dpp" + : "v_floor_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1138,15 @@ VPipeflushVop1::VPipeflushVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_dpp" + : "v_pipeflush_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -968,7 +1191,15 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_dpp" + : "v_mov_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1015,7 +1246,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_dpp" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1295,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_dpp" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1344,15 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_dpp" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1393,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_dpp" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1179,7 +1442,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_dpp" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1220,7 +1491,15 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_dpp" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1261,7 +1540,15 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_dpp" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1302,7 +1589,15 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_dpp" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1343,7 +1638,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_dpp" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1384,7 +1688,15 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_dpp" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1406,13 +1718,21 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_dpp" + : "v_rcp_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1434,13 +1754,21 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_dpp" + : "v_rsq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1809,15 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_dpp" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,13 +1839,21 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_dpp" + : "v_sqrt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1550,7 +1894,15 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_dpp" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1591,7 +1943,15 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_dpp" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1632,7 +1992,15 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_dpp" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +2041,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_dpp" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1714,7 +2090,15 @@ VClzI32U32Vop1::VClzI32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_dpp" + : "v_clz_i32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2139,15 @@ VCtzI32B32Vop1::VCtzI32B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_dpp" + : "v_ctz_i32_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1796,7 +2188,15 @@ VClsI32Vop1::VClsI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_dpp" + : "v_cls_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,13 +2218,22 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_dpp" + : "v_frexp_exp_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1846,13 +2255,22 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_dpp" + : "v_frexp_mant_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1874,13 +2292,21 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_dpp" + : "v_fract_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1921,7 +2347,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_dpp" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1962,7 +2397,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_dpp" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2450,16 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_dpp" + : "v_movreld_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2046,7 +2499,16 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_dpp" + : "v_movrels_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2086,7 +2548,16 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_dpp" + : "v_movrelsd_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2126,7 +2597,16 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_dpp" + : "v_movrelsd_2_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2171,7 +2651,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_dpp" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2222,7 +2710,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_dpp" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2273,7 +2769,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_dpp" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2324,7 +2828,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_dpp" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2375,7 +2887,15 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_dpp" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2426,7 +2946,15 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_dpp" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2477,7 +3005,15 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_dpp" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2528,7 +3064,15 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_dpp" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2579,7 +3123,15 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_dpp" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2630,7 +3182,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_dpp" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2681,7 +3242,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_dpp" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2732,7 +3302,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_dpp" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2783,7 +3361,15 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_dpp" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2834,7 +3420,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_dpp" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2885,7 +3479,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_dpp" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2936,7 +3538,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_dpp" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2987,7 +3597,15 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_dpp" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3038,7 +3656,15 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_dpp" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3087,7 +3713,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_dpp" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3138,7 +3773,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_dpp" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3189,7 +3833,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_dpp" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3214,13 +3867,21 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b32_dpp" + : "v_swap_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3242,13 +3903,21 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b16_dpp" + : "v_swap_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3273,13 +3942,22 @@ VPermlane64B32Vop1::VPermlane64B32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE64_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane64B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPermlane64B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane64_b32_dpp" + : "v_permlane64_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE64_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3300,14 +3978,23 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) src_operands_[2] = &m0; num_src_ = 3; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAPREL_B32 does not support DPP", ""); m0.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swaprel_b32_dpp" + : "v_swaprel_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3352,7 +4039,15 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_dpp" + : "v_not_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3401,7 +4096,15 @@ VCvtI32I16Vop1::VCvtI32I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_dpp" + : "v_cvt_i32_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3444,7 +4147,15 @@ VCvtU32U16Vop1::VCvtU32U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_dpp" + : "v_cvt_u32_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop2.cpp index 24ca6cfe4d88..34a4e088c983 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -54,7 +53,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_dpp" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -98,7 +106,16 @@ VDot2accF32F16Vop2::VDot2accF32F16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2accF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2accF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2acc_f32_f16_dpp" + : "v_dot2acc_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +158,15 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_dpp" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -184,7 +209,15 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_dpp" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -227,7 +260,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_dpp" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -251,13 +292,22 @@ VFmacDx9ZeroF32Vop2::VFmacDx9ZeroF32Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_DX9_ZERO_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_dx9_zero_f32_dpp" + : "v_fmac_dx9_zero_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_DX9_ZERO_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -300,7 +350,16 @@ VMulDx9ZeroF32Vop2::VMulDx9ZeroF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_dpp" + : "v_mul_dx9_zero_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +402,15 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_dpp" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -386,7 +453,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_dpp" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -429,7 +504,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_dpp" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +556,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_dpp" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -515,7 +607,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_dpp" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -558,7 +659,15 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f32_dpp" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +710,15 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f32_dpp" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -644,7 +761,15 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_dpp" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +812,15 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_dpp" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -730,7 +863,15 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_dpp" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -773,7 +914,15 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_dpp" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -816,7 +965,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_dpp" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1017,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_dpp" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -902,7 +1069,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_dpp" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -945,7 +1121,15 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_dpp" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -988,7 +1172,15 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_dpp" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1031,7 +1223,15 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_dpp" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1074,7 +1274,15 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_dpp" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1123,7 +1331,16 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_dpp" + : "v_add_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1172,7 +1389,16 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_dpp" + : "v_sub_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1447,16 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_dpp" + : "v_subrev_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1264,7 +1499,15 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_dpp" + : "v_add_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1307,7 +1550,15 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_dpp" + : "v_sub_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1350,7 +1601,16 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_dpp" + : "v_subrev_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1654,15 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_dpp" + : "v_fmac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,14 +1690,22 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f32_dpp" + : "v_fmamk_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1457,14 +1733,22 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f32_dpp" + : "v_fmaak_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1507,7 +1791,16 @@ VCvtPkRtzF16F32Vop2::VCvtPkRtzF16F32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_dpp" + : "v_cvt_pk_rtz_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1555,7 +1848,15 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_dpp" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1609,7 +1910,15 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_dpp" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1663,7 +1972,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_dpp" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1717,7 +2034,15 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_dpp" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1772,7 +2097,15 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_dpp" + : "v_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1812,14 +2145,22 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F16 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f16_dpp" + : "v_fmamk_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1858,14 +2199,22 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F16 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f16_dpp" + : "v_fmaak_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1919,7 +2268,15 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f16_dpp" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1973,7 +2330,15 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f16_dpp" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2027,7 +2392,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_dpp" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2057,13 +2430,21 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMAC_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fmac_f16_dpp" + : "v_pk_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3.cpp index 6d58c21631dc..5d1542bda0c7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,15 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_e64_dpp" + : "v_nop", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -65,7 +72,15 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_e64_dpp" + : "v_mov_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,13 +97,22 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_e64_dpp" + : "v_readfirstlane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -110,13 +134,21 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_e64_dpp" + : "v_cvt_i32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,13 +169,21 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_e64_dpp" + : "v_cvt_f64_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -184,7 +224,15 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_e64_dpp" + : "v_cvt_f32_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -225,7 +273,15 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_e64_dpp" + : "v_cvt_f32_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +322,15 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_e64_dpp" + : "v_cvt_u32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +371,15 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_e64_dpp" + : "v_cvt_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -348,7 +420,15 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_e64_dpp" + : "v_cvt_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +479,15 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_e64_dpp" + : "v_cvt_f32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -440,7 +528,16 @@ VCvtNearestI32F32Vop3::VCvtNearestI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_e64_dpp" + : "v_cvt_nearest_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +578,16 @@ VCvtFloorI32F32Vop3::VCvtFloorI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_e64_dpp" + : "v_cvt_floor_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -522,7 +628,16 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_e64_dpp" + : "v_cvt_off_f32_i4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -544,13 +659,21 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_e64_dpp" + : "v_cvt_f32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -571,13 +694,21 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_e64_dpp" + : "v_cvt_f64_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -618,7 +749,16 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_e64_dpp" + : "v_cvt_f32_ubyte0", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +799,16 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_e64_dpp" + : "v_cvt_f32_ubyte1", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -700,7 +849,16 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_e64_dpp" + : "v_cvt_f32_ubyte2", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +899,16 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_e64_dpp" + : "v_cvt_f32_ubyte3", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -763,13 +930,21 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_e64_dpp" + : "v_cvt_u32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -790,13 +965,21 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_e64_dpp" + : "v_cvt_f64_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -818,13 +1001,21 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_e64_dpp" + : "v_trunc_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -846,13 +1037,21 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_e64_dpp" + : "v_ceil_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -874,13 +1073,21 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_e64_dpp" + : "v_rndne_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -902,13 +1109,21 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_e64_dpp" + : "v_floor_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1139,15 @@ VPipeflushVop3::VPipeflushVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_e64_dpp" + : "v_pipeflush", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -969,7 +1192,15 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_e64_dpp" + : "v_mov_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1247,15 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_e64_dpp" + : "v_fract_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1296,15 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_e64_dpp" + : "v_trunc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1345,15 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_e64_dpp" + : "v_ceil_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1139,7 +1394,15 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_e64_dpp" + : "v_rndne_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1180,7 +1443,15 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_e64_dpp" + : "v_floor_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1492,15 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_e64_dpp" + : "v_exp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1262,7 +1541,15 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_e64_dpp" + : "v_log_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1303,7 +1590,15 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_e64_dpp" + : "v_rcp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1344,7 +1639,16 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_e64_dpp" + : "v_rcp_iflag_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1385,7 +1689,15 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_e64_dpp" + : "v_rsq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1407,13 +1719,21 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_e64_dpp" + : "v_rcp_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1435,13 +1755,21 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_e64_dpp" + : "v_rsq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1810,15 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_e64_dpp" + : "v_sqrt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,13 +1840,21 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_e64_dpp" + : "v_sqrt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1551,7 +1895,15 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_e64_dpp" + : "v_sin_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1592,7 +1944,15 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_e64_dpp" + : "v_cos_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1633,7 +1993,15 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_e64_dpp" + : "v_not_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1674,7 +2042,15 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_e64_dpp" + : "v_bfrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1715,7 +2091,15 @@ VClzI32U32Vop3::VClzI32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_e64_dpp" + : "v_clz_i32_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1756,7 +2140,15 @@ VCtzI32B32Vop3::VCtzI32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_e64_dpp" + : "v_ctz_i32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2189,15 @@ VClsI32Vop3::VClsI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_e64_dpp" + : "v_cls_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,13 +2219,22 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_e64_dpp" + : "v_frexp_exp_i32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1847,13 +2256,22 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_e64_dpp" + : "v_frexp_mant_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1875,13 +2293,21 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_e64_dpp" + : "v_fract_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1922,7 +2348,16 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_e64_dpp" + : "v_frexp_exp_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1963,7 +2398,16 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_e64_dpp" + : "v_frexp_mant_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2007,7 +2451,16 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_e64_dpp" + : "v_movreld_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2047,7 +2500,16 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_e64_dpp" + : "v_movrels_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2087,7 +2549,16 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_e64_dpp" + : "v_movrelsd_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2127,7 +2598,16 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_e64_dpp" + : "v_movrelsd_2_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2172,7 +2652,15 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_e64_dpp" + : "v_cvt_f16_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2223,7 +2711,15 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_e64_dpp" + : "v_cvt_f16_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2274,7 +2770,15 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_e64_dpp" + : "v_cvt_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2829,15 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_e64_dpp" + : "v_cvt_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2376,7 +2888,15 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_e64_dpp" + : "v_rcp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2427,7 +2947,15 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_e64_dpp" + : "v_sqrt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2478,7 +3006,15 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_e64_dpp" + : "v_rsq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2529,7 +3065,15 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_e64_dpp" + : "v_log_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2580,7 +3124,15 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_e64_dpp" + : "v_exp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2631,7 +3183,16 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_e64_dpp" + : "v_frexp_mant_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2682,7 +3243,16 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_e64_dpp" + : "v_frexp_exp_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2733,7 +3303,15 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_e64_dpp" + : "v_floor_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2784,7 +3362,15 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_e64_dpp" + : "v_ceil_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2835,7 +3421,15 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_e64_dpp" + : "v_trunc_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2886,7 +3480,15 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_e64_dpp" + : "v_rndne_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2937,7 +3539,15 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_e64_dpp" + : "v_fract_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2988,7 +3598,15 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_e64_dpp" + : "v_sin_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3039,7 +3657,15 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_e64_dpp" + : "v_cos_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3086,7 +3712,16 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_e64_dpp" + : "v_sat_pk_u8_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3137,7 +3772,16 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_e64_dpp" + : "v_cvt_norm_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3188,7 +3832,16 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_e64_dpp" + : "v_cvt_norm_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3239,7 +3892,15 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_e64_dpp" + : "v_not_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3290,7 +3951,15 @@ VCvtI32I16Vop3::VCvtI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_e64_dpp" + : "v_cvt_i32_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3335,7 +4004,15 @@ VCvtU32U16Vop3::VCvtU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_e64_dpp" + : "v_cvt_u32_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3384,7 +4061,16 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_e64_dpp" + : "v_cndmask_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3431,7 +4117,15 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_e64_dpp" + : "v_add_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3478,7 +4172,15 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_e64_dpp" + : "v_sub_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3525,7 +4227,15 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_e64_dpp" + : "v_subrev_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3553,13 +4263,22 @@ VFmacDx9ZeroF32Vop3::VFmacDx9ZeroF32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_DX9_ZERO_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_dx9_zero_f32_e64_dpp" + : "v_fmac_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_DX9_ZERO_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3606,7 +4325,16 @@ VMulDx9ZeroF32Vop3::VMulDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_e64_dpp" + : "v_mul_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3653,7 +4381,15 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_e64_dpp" + : "v_mul_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3700,7 +4436,15 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_e64_dpp" + : "v_mul_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3747,7 +4491,16 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_e64_dpp" + : "v_mul_hi_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3794,7 +4547,15 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_e64_dpp" + : "v_mul_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3841,7 +4602,16 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_e64_dpp" + : "v_mul_hi_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3888,7 +4658,15 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f32_e64_dpp" + : "v_min_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3935,7 +4713,15 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f32_e64_dpp" + : "v_max_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3982,7 +4768,15 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_e64_dpp" + : "v_min_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4029,7 +4823,15 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_e64_dpp" + : "v_max_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4076,7 +4878,15 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_e64_dpp" + : "v_min_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4123,7 +4933,15 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_e64_dpp" + : "v_max_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4170,7 +4988,16 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_e64_dpp" + : "v_lshlrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4217,7 +5044,16 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_e64_dpp" + : "v_lshrrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4264,7 +5100,16 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_e64_dpp" + : "v_ashrrev_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4311,7 +5156,15 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_e64_dpp" + : "v_and_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4358,7 +5211,15 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_e64_dpp" + : "v_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4405,7 +5266,15 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_e64_dpp" + : "v_xor_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4452,7 +5321,15 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_e64_dpp" + : "v_xnor_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4499,7 +5376,15 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_e64_dpp" + : "v_add_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4546,7 +5431,15 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_e64_dpp" + : "v_sub_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4593,7 +5486,16 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_e64_dpp" + : "v_subrev_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4641,7 +5543,15 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_e64_dpp" + : "v_fmac_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4688,7 +5598,16 @@ VCvtPkRtzF16F32Vop3::VCvtPkRtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_e64_dpp" + : "v_cvt_pk_rtz_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4743,7 +5662,15 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_e64_dpp" + : "v_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4804,7 +5731,15 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_e64_dpp" + : "v_sub_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4865,7 +5800,15 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_e64_dpp" + : "v_subrev_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4926,7 +5869,15 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_e64_dpp" + : "v_mul_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4988,7 +5939,15 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_e64_dpp" + : "v_fmac_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5049,7 +6008,15 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f16_e64_dpp" + : "v_max_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5110,7 +6077,15 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f16_e64_dpp" + : "v_min_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5171,7 +6146,15 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_e64_dpp" + : "v_ldexp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5230,7 +6213,16 @@ VFmaDx9ZeroF32Vop3::VFmaDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_dx9_zero_f32_e64_dpp" + : "v_fma_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5283,7 +6275,15 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i24_e64_dpp" + : "v_mad_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5336,7 +6336,15 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u24_e64_dpp" + : "v_mad_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5389,7 +6397,15 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubeid_f32_e64_dpp" + : "v_cubeid_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5442,7 +6458,15 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubesc_f32_e64_dpp" + : "v_cubesc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5495,7 +6519,15 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubetc_f32_e64_dpp" + : "v_cubetc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5548,7 +6580,15 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubema_f32_e64_dpp" + : "v_cubema_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5601,7 +6641,15 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_u32_e64_dpp" + : "v_bfe_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5654,7 +6702,15 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_i32_e64_dpp" + : "v_bfe_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5707,7 +6763,15 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfi_b32_e64_dpp" + : "v_bfi_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5760,7 +6824,15 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f32_e64_dpp" + : "v_fma_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5796,13 +6868,21 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMA_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f64_e64_dpp" + : "v_fma_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMA_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5855,7 +6935,15 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lerp_u8_e64_dpp" + : "v_lerp_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5912,7 +7000,16 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbit_b32_e64_dpp" + : "v_alignbit_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5969,7 +7066,16 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbyte_b32_e64_dpp" + : "v_alignbyte_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6022,7 +7128,15 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mullit_f32_e64_dpp" + : "v_mullit_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6075,7 +7189,15 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_f32_e64_dpp" + : "v_min3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6128,7 +7250,15 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i32_e64_dpp" + : "v_min3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6181,7 +7311,15 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u32_e64_dpp" + : "v_min3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6234,7 +7372,15 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_f32_e64_dpp" + : "v_max3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6287,7 +7433,15 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i32_e64_dpp" + : "v_max3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6340,7 +7494,15 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u32_e64_dpp" + : "v_max3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6393,7 +7555,15 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_f32_e64_dpp" + : "v_med3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6446,7 +7616,15 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i32_e64_dpp" + : "v_med3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6499,7 +7677,15 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u32_e64_dpp" + : "v_med3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6552,7 +7738,15 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u8_e64_dpp" + : "v_sad_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6605,7 +7799,15 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_hi_u8_e64_dpp" + : "v_sad_hi_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6658,7 +7860,15 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u16_e64_dpp" + : "v_sad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6711,7 +7921,15 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u32_e64_dpp" + : "v_sad_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6764,7 +7982,16 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u8_f32_e64_dpp" + : "v_cvt_pk_u8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6797,13 +8024,22 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f32_e64_dpp" + : "v_div_fixup_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6839,13 +8075,22 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f64_e64_dpp" + : "v_div_fixup_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6880,14 +8125,23 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F32 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f32_e64_dpp" + : "v_div_fmas_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6925,14 +8179,23 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f64_e64_dpp" + : "v_div_fmas_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6985,7 +8248,15 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_msad_u8_e64_dpp" + : "v_msad_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7020,13 +8291,22 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_QSAD_PK_U16_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_qsad_pk_u16_u8_e64_dpp" + : "v_qsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_QSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7061,13 +8341,22 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_PK_U16_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_pk_u16_u8_e64_dpp" + : "v_mqsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7097,13 +8386,22 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_U32_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_u32_u8_e64_dpp" + : "v_mqsad_u32_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7156,7 +8454,15 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor3_b32_e64_dpp" + : "v_xor3_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7221,7 +8527,15 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u16_e64_dpp" + : "v_mad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7280,7 +8594,15 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_b32_e64_dpp" + : "v_perm_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7333,7 +8655,15 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xad_u32_e64_dpp" + : "v_xad_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7386,7 +8716,16 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_add_u32_e64_dpp" + : "v_lshl_add_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7439,7 +8778,16 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_lshl_u32_e64_dpp" + : "v_add_lshl_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7504,7 +8852,15 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f16_e64_dpp" + : "v_fma_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7575,7 +8931,15 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_f16_e64_dpp" + : "v_min3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7646,7 +9010,15 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i16_e64_dpp" + : "v_min3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7717,7 +9089,15 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u16_e64_dpp" + : "v_min3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7788,7 +9168,15 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_f16_e64_dpp" + : "v_max3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7859,7 +9247,15 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i16_e64_dpp" + : "v_max3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7930,7 +9326,15 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u16_e64_dpp" + : "v_max3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8001,7 +9405,15 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_f16_e64_dpp" + : "v_med3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8072,7 +9484,15 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i16_e64_dpp" + : "v_med3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8143,7 +9563,15 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u16_e64_dpp" + : "v_med3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8214,7 +9642,15 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i16_e64_dpp" + : "v_mad_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8285,7 +9721,16 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f16_e64_dpp" + : "v_div_fixup_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8344,7 +9789,15 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add3_u32_e64_dpp" + : "v_add3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8397,7 +9850,15 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_or_b32_e64_dpp" + : "v_lshl_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8450,7 +9911,15 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_or_b32_e64_dpp" + : "v_and_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8503,7 +9972,15 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or3_b32_e64_dpp" + : "v_or3_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8564,7 +10041,15 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u16_e64_dpp" + : "v_mad_u32_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8625,7 +10110,15 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i16_e64_dpp" + : "v_mad_i32_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8654,13 +10147,22 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_b32_e64_dpp" + : "v_permlane16_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8689,13 +10191,22 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANEX16_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlanex16_b32_e64_dpp" + : "v_permlanex16_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANEX16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8752,7 +10263,16 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b16_e64_dpp" + : "v_cndmask_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8811,7 +10331,15 @@ VMaxminF32Vop3::VMaxminF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_f32_e64_dpp" + : "v_maxmin_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8864,7 +10392,15 @@ VMinmaxF32Vop3::VMinmaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_f32_e64_dpp" + : "v_minmax_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8929,7 +10465,15 @@ VMaxminF16Vop3::VMaxminF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_f16_e64_dpp" + : "v_maxmin_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9000,7 +10544,15 @@ VMinmaxF16Vop3::VMinmaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_f16_e64_dpp" + : "v_minmax_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9059,7 +10611,15 @@ VMaxminU32Vop3::VMaxminU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_u32_e64_dpp" + : "v_maxmin_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9112,7 +10672,15 @@ VMinmaxU32Vop3::VMinmaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_u32_e64_dpp" + : "v_minmax_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9165,7 +10733,15 @@ VMaxminI32Vop3::VMaxminI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_i32_e64_dpp" + : "v_maxmin_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9218,7 +10794,15 @@ VMinmaxI32Vop3::VMinmaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_i32_e64_dpp" + : "v_minmax_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9275,7 +10859,16 @@ VDot2F16F16Vop3::VDot2F16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2F16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f16_f16_e64_dpp" + : "v_dot2_f16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9338,7 +10931,16 @@ VDot2Bf16Bf16Vop3::VDot2Bf16Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_bf16_bf16_e64_dpp" + : "v_dot2_bf16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9399,7 +11001,15 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u16_e64_dpp" + : "v_add_nc_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9460,7 +11070,15 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u16_e64_dpp" + : "v_sub_nc_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9521,7 +11139,15 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u16_e64_dpp" + : "v_mul_lo_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9574,7 +11200,16 @@ VCvtPkI16F32Vop3::VCvtPkI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_f32_e64_dpp" + : "v_cvt_pk_i16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9621,7 +11256,16 @@ VCvtPkU16F32Vop3::VCvtPkU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_f32_e64_dpp" + : "v_cvt_pk_u16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9676,7 +11320,15 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u16_e64_dpp" + : "v_max_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9737,7 +11389,15 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i16_e64_dpp" + : "v_max_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9798,7 +11458,15 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u16_e64_dpp" + : "v_min_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9859,7 +11527,15 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i16_e64_dpp" + : "v_min_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9920,7 +11596,15 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i16_e64_dpp" + : "v_add_nc_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9981,7 +11665,15 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i16_e64_dpp" + : "v_sub_nc_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10042,7 +11734,16 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pack_b32_f16_e64_dpp" + : "v_pack_b32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10097,7 +11798,16 @@ VCvtPkNormI16F16Vop3::VCvtPkNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f16_e64_dpp" + : "v_cvt_pk_norm_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10152,7 +11862,16 @@ VCvtPkNormU16F16Vop3::VCvtPkNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f16_e64_dpp" + : "v_cvt_pk_norm_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10199,7 +11918,15 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f32_e64_dpp" + : "v_ldexp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10246,7 +11973,15 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfm_b32_e64_dpp" + : "v_bfm_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10293,7 +12028,16 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bcnt_u32_b32_e64_dpp" + : "v_bcnt_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10340,7 +12084,16 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_lo_u32_b32_e64_dpp" + : "v_mbcnt_lo_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10387,7 +12140,16 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_hi_u32_b32_e64_dpp" + : "v_mbcnt_hi_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10434,7 +12196,16 @@ VCvtPkNormI16F32Vop3::VCvtPkNormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f32_e64_dpp" + : "v_cvt_pk_norm_i16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10481,7 +12252,16 @@ VCvtPkNormU16F32Vop3::VCvtPkNormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f32_e64_dpp" + : "v_cvt_pk_norm_u16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10528,7 +12308,16 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_u32_e64_dpp" + : "v_cvt_pk_u16_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10575,7 +12364,16 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_i32_e64_dpp" + : "v_cvt_pk_i16_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10622,7 +12420,15 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i32_e64_dpp" + : "v_sub_nc_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10669,7 +12475,15 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i32_e64_dpp" + : "v_add_nc_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10698,13 +12512,21 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f64_e64_dpp" + : "v_add_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10733,13 +12555,21 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f64_e64_dpp" + : "v_mul_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10768,13 +12598,21 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f64_e64_dpp" + : "v_min_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10803,13 +12641,21 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f64_e64_dpp" + : "v_max_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10837,13 +12683,21 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LDEXP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f64_e64_dpp" + : "v_ldexp_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LDEXP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10870,13 +12724,21 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_LO_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u32_e64_dpp" + : "v_mul_lo_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_LO_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10903,13 +12765,21 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_e64_dpp" + : "v_mul_hi_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10936,13 +12806,21 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_e64_dpp" + : "v_mul_hi_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10970,13 +12848,22 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRIG_PREOP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trig_preop_f64_e64_dpp" + : "v_trig_preop_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRIG_PREOP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11031,7 +12918,16 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b16_e64_dpp" + : "v_lshlrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11092,7 +12988,16 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b16_e64_dpp" + : "v_lshrrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11153,7 +13058,16 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i16_e64_dpp" + : "v_ashrrev_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11187,13 +13101,22 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHLREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b64_e64_dpp" + : "v_lshlrev_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHLREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11221,13 +13144,22 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHRREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b64_e64_dpp" + : "v_lshrrev_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHRREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11255,13 +13187,22 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ASHRREV_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i64_e64_dpp" + : "v_ashrrev_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ASHRREV_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11280,13 +13221,22 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readlane_b32_e64_dpp" + : "v_readlane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11310,13 +13260,22 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WRITELANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_writelane_b32_e64_dpp" + : "v_writelane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_WRITELANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11371,7 +13330,15 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b16_e64_dpp" + : "v_and_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11432,7 +13399,15 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b16_e64_dpp" + : "v_or_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11493,7 +13468,15 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b16_e64_dpp" + : "v_xor_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11554,7 +13537,15 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f16_e64_dpp" + : "v_cmp_f_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11609,7 +13600,15 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_e64_dpp" + : "v_cmp_lt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11664,7 +13663,15 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_e64_dpp" + : "v_cmp_eq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11719,7 +13726,15 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_e64_dpp" + : "v_cmp_le_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11774,7 +13789,15 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_e64_dpp" + : "v_cmp_gt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11829,7 +13852,15 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_e64_dpp" + : "v_cmp_lg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11884,7 +13915,15 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_e64_dpp" + : "v_cmp_ge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11939,7 +13978,15 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_e64_dpp" + : "v_cmp_o_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11994,7 +14041,15 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_e64_dpp" + : "v_cmp_u_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12049,7 +14104,15 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_e64_dpp" + : "v_cmp_nge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12104,7 +14167,15 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_e64_dpp" + : "v_cmp_nlg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12159,7 +14230,15 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_e64_dpp" + : "v_cmp_ngt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12214,7 +14293,15 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_e64_dpp" + : "v_cmp_nle_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12269,7 +14356,15 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_e64_dpp" + : "v_cmp_neq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12324,7 +14419,15 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_e64_dpp" + : "v_cmp_nlt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12379,7 +14482,15 @@ VCmpTF16Vop3::VCmpTF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f16_e64_dpp" + : "v_cmp_t_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12426,7 +14537,15 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f32_e64_dpp" + : "v_cmp_f_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12473,7 +14592,15 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_e64_dpp" + : "v_cmp_lt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12520,7 +14647,15 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_e64_dpp" + : "v_cmp_eq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12567,7 +14702,15 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_e64_dpp" + : "v_cmp_le_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12614,7 +14757,15 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_e64_dpp" + : "v_cmp_gt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12661,7 +14812,15 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_e64_dpp" + : "v_cmp_lg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12708,7 +14867,15 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_e64_dpp" + : "v_cmp_ge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12755,7 +14922,15 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_e64_dpp" + : "v_cmp_o_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12802,7 +14977,15 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_e64_dpp" + : "v_cmp_u_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12849,7 +15032,15 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_e64_dpp" + : "v_cmp_nge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12896,7 +15087,15 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_e64_dpp" + : "v_cmp_nlg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12943,7 +15142,15 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_e64_dpp" + : "v_cmp_ngt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12990,7 +15197,15 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_e64_dpp" + : "v_cmp_nle_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13037,7 +15252,15 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_e64_dpp" + : "v_cmp_neq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13084,7 +15307,15 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_e64_dpp" + : "v_cmp_nlt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13131,7 +15362,15 @@ VCmpTF32Vop3::VCmpTF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f32_e64_dpp" + : "v_cmp_t_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13160,13 +15399,21 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f64_e64_dpp" + : "v_cmp_f_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13195,13 +15442,21 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_e64_dpp" + : "v_cmp_lt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13230,13 +15485,21 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_e64_dpp" + : "v_cmp_eq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13265,13 +15528,21 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_e64_dpp" + : "v_cmp_le_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13300,13 +15571,21 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_e64_dpp" + : "v_cmp_gt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13335,13 +15614,21 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_e64_dpp" + : "v_cmp_lg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13370,13 +15657,21 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_e64_dpp" + : "v_cmp_ge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13405,13 +15700,21 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_e64_dpp" + : "v_cmp_o_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13440,13 +15743,21 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_e64_dpp" + : "v_cmp_u_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13475,13 +15786,21 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_e64_dpp" + : "v_cmp_nge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13510,13 +15829,21 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_e64_dpp" + : "v_cmp_nlg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13545,13 +15872,21 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_e64_dpp" + : "v_cmp_ngt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13580,13 +15915,21 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_e64_dpp" + : "v_cmp_nle_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13615,13 +15958,21 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_e64_dpp" + : "v_cmp_neq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13650,13 +16001,21 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_e64_dpp" + : "v_cmp_nlt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13685,13 +16044,21 @@ VCmpTF64Vop3::VCmpTF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpTF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f64_e64_dpp" + : "v_cmp_t_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13746,7 +16113,15 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_e64_dpp" + : "v_cmp_lt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13801,7 +16176,15 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_e64_dpp" + : "v_cmp_eq_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13856,7 +16239,15 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_e64_dpp" + : "v_cmp_le_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13911,7 +16302,15 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_e64_dpp" + : "v_cmp_gt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13966,7 +16365,15 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_e64_dpp" + : "v_cmp_ne_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14021,7 +16428,15 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_e64_dpp" + : "v_cmp_ge_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14076,7 +16491,15 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_e64_dpp" + : "v_cmp_lt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14131,7 +16554,15 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_e64_dpp" + : "v_cmp_eq_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14186,7 +16617,15 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_e64_dpp" + : "v_cmp_le_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14241,7 +16680,15 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_e64_dpp" + : "v_cmp_gt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14296,7 +16743,15 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_e64_dpp" + : "v_cmp_ne_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14351,7 +16806,15 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_e64_dpp" + : "v_cmp_ge_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14398,7 +16861,15 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i32_e64_dpp" + : "v_cmp_f_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14445,7 +16916,15 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_e64_dpp" + : "v_cmp_lt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14492,7 +16971,15 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_e64_dpp" + : "v_cmp_eq_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14539,7 +17026,15 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_e64_dpp" + : "v_cmp_le_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14586,7 +17081,15 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_e64_dpp" + : "v_cmp_gt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14633,7 +17136,15 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_e64_dpp" + : "v_cmp_ne_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14680,7 +17191,15 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_e64_dpp" + : "v_cmp_ge_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14727,7 +17246,15 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i32_e64_dpp" + : "v_cmp_t_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14774,7 +17301,15 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u32_e64_dpp" + : "v_cmp_f_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14821,7 +17356,15 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_e64_dpp" + : "v_cmp_lt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14868,7 +17411,15 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_e64_dpp" + : "v_cmp_eq_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14915,7 +17466,15 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_e64_dpp" + : "v_cmp_le_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14962,7 +17521,15 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_e64_dpp" + : "v_cmp_gt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15009,7 +17576,15 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_e64_dpp" + : "v_cmp_ne_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15056,7 +17631,15 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_e64_dpp" + : "v_cmp_ge_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15103,7 +17686,15 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u32_e64_dpp" + : "v_cmp_t_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15132,13 +17723,21 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i64_e64_dpp" + : "v_cmp_f_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15167,13 +17766,21 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_e64_dpp" + : "v_cmp_lt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15202,13 +17809,21 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_e64_dpp" + : "v_cmp_eq_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15237,13 +17852,21 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_e64_dpp" + : "v_cmp_le_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15272,13 +17895,21 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_e64_dpp" + : "v_cmp_gt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15307,13 +17938,21 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_e64_dpp" + : "v_cmp_ne_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15342,13 +17981,21 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_e64_dpp" + : "v_cmp_ge_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15377,13 +18024,21 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i64_e64_dpp" + : "v_cmp_t_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15412,13 +18067,21 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u64_e64_dpp" + : "v_cmp_f_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15447,13 +18110,21 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_e64_dpp" + : "v_cmp_lt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15482,13 +18153,21 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_e64_dpp" + : "v_cmp_eq_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15517,13 +18196,21 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_e64_dpp" + : "v_cmp_le_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15552,13 +18239,21 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_e64_dpp" + : "v_cmp_gt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15587,13 +18282,21 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_e64_dpp" + : "v_cmp_ne_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15622,13 +18325,21 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_e64_dpp" + : "v_cmp_ge_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15657,13 +18368,21 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u64_e64_dpp" + : "v_cmp_t_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15718,7 +18437,16 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_e64_dpp" + : "v_cmp_class_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15765,7 +18493,16 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_e64_dpp" + : "v_cmp_class_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15793,13 +18530,22 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_e64_dpp" + : "v_cmp_class_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15858,7 +18604,15 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f16_e64_dpp" + : "v_cmpx_f_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15917,7 +18671,15 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_e64_dpp" + : "v_cmpx_lt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15976,7 +18738,15 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_e64_dpp" + : "v_cmpx_eq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16035,7 +18805,15 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_e64_dpp" + : "v_cmpx_le_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16094,7 +18872,15 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_e64_dpp" + : "v_cmpx_gt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16153,7 +18939,15 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_e64_dpp" + : "v_cmpx_lg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16212,7 +19006,15 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_e64_dpp" + : "v_cmpx_ge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16271,7 +19073,15 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_e64_dpp" + : "v_cmpx_o_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16330,7 +19140,15 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_e64_dpp" + : "v_cmpx_u_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16389,7 +19207,16 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_e64_dpp" + : "v_cmpx_nge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16448,7 +19275,16 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_e64_dpp" + : "v_cmpx_nlg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16507,7 +19343,16 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_e64_dpp" + : "v_cmpx_ngt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16566,7 +19411,16 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_e64_dpp" + : "v_cmpx_nle_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16625,7 +19479,16 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_e64_dpp" + : "v_cmpx_neq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16684,7 +19547,16 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_e64_dpp" + : "v_cmpx_nlt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16743,7 +19615,15 @@ VCmpxTF16Vop3::VCmpxTF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f16_e64_dpp" + : "v_cmpx_t_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16794,7 +19674,15 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f32_e64_dpp" + : "v_cmpx_f_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16845,7 +19733,15 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_e64_dpp" + : "v_cmpx_lt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16896,7 +19792,15 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_e64_dpp" + : "v_cmpx_eq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16947,7 +19851,15 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_e64_dpp" + : "v_cmpx_le_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16998,7 +19910,15 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_e64_dpp" + : "v_cmpx_gt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17049,7 +19969,15 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_e64_dpp" + : "v_cmpx_lg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17100,7 +20028,15 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_e64_dpp" + : "v_cmpx_ge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17151,7 +20087,15 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_e64_dpp" + : "v_cmpx_o_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17202,7 +20146,15 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_e64_dpp" + : "v_cmpx_u_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17253,7 +20205,16 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_e64_dpp" + : "v_cmpx_nge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17304,7 +20265,16 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_e64_dpp" + : "v_cmpx_nlg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17355,7 +20325,16 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_e64_dpp" + : "v_cmpx_ngt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17406,7 +20385,16 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_e64_dpp" + : "v_cmpx_nle_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17457,7 +20445,16 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_e64_dpp" + : "v_cmpx_neq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17508,7 +20505,16 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_e64_dpp" + : "v_cmpx_nlt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17559,7 +20565,15 @@ VCmpxTF32Vop3::VCmpxTF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f32_e64_dpp" + : "v_cmpx_t_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17590,15 +20604,23 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f64_e64_dpp" + : "v_cmpx_f_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17629,15 +20651,23 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_e64_dpp" + : "v_cmpx_lt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17668,15 +20698,23 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_e64_dpp" + : "v_cmpx_eq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17707,15 +20745,23 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_e64_dpp" + : "v_cmpx_le_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17746,15 +20792,23 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_e64_dpp" + : "v_cmpx_gt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17785,15 +20839,23 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_e64_dpp" + : "v_cmpx_lg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17824,15 +20886,23 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_e64_dpp" + : "v_cmpx_ge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17863,15 +20933,23 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_e64_dpp" + : "v_cmpx_o_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17902,15 +20980,23 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_e64_dpp" + : "v_cmpx_u_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17941,15 +21027,24 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_e64_dpp" + : "v_cmpx_nge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17980,15 +21075,24 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_e64_dpp" + : "v_cmpx_nlg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18019,15 +21123,24 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_e64_dpp" + : "v_cmpx_ngt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18058,15 +21171,24 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_e64_dpp" + : "v_cmpx_nle_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18097,15 +21219,24 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_e64_dpp" + : "v_cmpx_neq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18136,15 +21267,24 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_e64_dpp" + : "v_cmpx_nlt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18175,15 +21315,23 @@ VCmpxTF64Vop3::VCmpxTF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f64_e64_dpp" + : "v_cmpx_t_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18242,7 +21390,15 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_e64_dpp" + : "v_cmpx_lt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18301,7 +21457,15 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_e64_dpp" + : "v_cmpx_eq_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18360,7 +21524,15 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_e64_dpp" + : "v_cmpx_le_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18419,7 +21591,15 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_e64_dpp" + : "v_cmpx_gt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18478,7 +21658,15 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_e64_dpp" + : "v_cmpx_ne_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18537,7 +21725,15 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_e64_dpp" + : "v_cmpx_ge_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18596,7 +21792,15 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_e64_dpp" + : "v_cmpx_lt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18655,7 +21859,15 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_e64_dpp" + : "v_cmpx_eq_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18714,7 +21926,15 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_e64_dpp" + : "v_cmpx_le_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18773,7 +21993,15 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_e64_dpp" + : "v_cmpx_gt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18832,7 +22060,15 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_e64_dpp" + : "v_cmpx_ne_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18891,7 +22127,15 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_e64_dpp" + : "v_cmpx_ge_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18942,7 +22186,15 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i32_e64_dpp" + : "v_cmpx_f_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18993,7 +22245,15 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_e64_dpp" + : "v_cmpx_lt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19044,7 +22304,15 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_e64_dpp" + : "v_cmpx_eq_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19095,7 +22363,15 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_e64_dpp" + : "v_cmpx_le_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19146,7 +22422,15 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_e64_dpp" + : "v_cmpx_gt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19197,7 +22481,15 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_e64_dpp" + : "v_cmpx_ne_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19248,7 +22540,15 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_e64_dpp" + : "v_cmpx_ge_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19299,7 +22599,15 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i32_e64_dpp" + : "v_cmpx_t_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19350,7 +22658,15 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u32_e64_dpp" + : "v_cmpx_f_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19401,7 +22717,15 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_e64_dpp" + : "v_cmpx_lt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19452,7 +22776,15 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_e64_dpp" + : "v_cmpx_eq_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19503,7 +22835,15 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_e64_dpp" + : "v_cmpx_le_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19554,7 +22894,15 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_e64_dpp" + : "v_cmpx_gt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19605,7 +22953,15 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_e64_dpp" + : "v_cmpx_ne_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19656,7 +23012,15 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_e64_dpp" + : "v_cmpx_ge_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19707,7 +23071,15 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u32_e64_dpp" + : "v_cmpx_t_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19738,15 +23110,23 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i64_e64_dpp" + : "v_cmpx_f_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19777,15 +23157,23 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_e64_dpp" + : "v_cmpx_lt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19816,15 +23204,23 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_e64_dpp" + : "v_cmpx_eq_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19855,15 +23251,23 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_e64_dpp" + : "v_cmpx_le_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19894,15 +23298,23 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_e64_dpp" + : "v_cmpx_gt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19933,15 +23345,23 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_e64_dpp" + : "v_cmpx_ne_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19972,15 +23392,23 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_e64_dpp" + : "v_cmpx_ge_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20011,15 +23439,23 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i64_e64_dpp" + : "v_cmpx_t_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20050,15 +23486,23 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u64_e64_dpp" + : "v_cmpx_f_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20089,15 +23533,23 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_e64_dpp" + : "v_cmpx_lt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20128,15 +23580,23 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_e64_dpp" + : "v_cmpx_eq_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20167,15 +23627,23 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_e64_dpp" + : "v_cmpx_le_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20206,15 +23674,23 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_e64_dpp" + : "v_cmpx_gt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20245,15 +23721,23 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_e64_dpp" + : "v_cmpx_ne_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20284,15 +23768,23 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_e64_dpp" + : "v_cmpx_ge_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20323,15 +23815,23 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u64_e64_dpp" + : "v_cmpx_t_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20390,7 +23890,16 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_e64_dpp" + : "v_cmpx_class_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20441,7 +23950,16 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_e64_dpp" + : "v_cmpx_class_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20471,15 +23989,24 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_e64_dpp" + : "v_cmpx_class_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20530,7 +24057,16 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_e64_dpp" + : "v_add_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20581,7 +24117,16 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_e64_dpp" + : "v_sub_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20632,7 +24177,16 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_e64_dpp" + : "v_subrev_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20667,13 +24221,23 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) src2 = Operand(32, OperandType::OPR_SIMM32, static_cast( reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f32_e64_dpp" + : "v_div_scale_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20714,13 +24278,23 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f64_e64_dpp" + : "v_div_scale_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20757,13 +24331,23 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_U64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u64_u32_e64_dpp" + : "v_mad_u64_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_U64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20800,13 +24384,23 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_I64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i64_i32_e64_dpp" + : "v_mad_i64_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_I64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20855,7 +24449,16 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_u32_e64_dpp" + : "v_add_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20904,7 +24507,16 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_u32_e64_dpp" + : "v_sub_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20953,7 +24565,16 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_u32_e64_dpp" + : "v_subrev_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3p.cpp index da609d9d2452..37f5de6ae94b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,13 +40,22 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_i16_e64_dpp" + : "v_pk_mad_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -74,13 +82,23 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_LO_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_lo_u16_e64_dpp" + : "v_pk_mul_lo_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_LO_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -107,13 +125,22 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_i16_e64_dpp" + : "v_pk_add_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -140,13 +167,22 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_i16_e64_dpp" + : "v_pk_sub_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -173,13 +209,23 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHLREV_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshlrev_b16_e64_dpp" + : "v_pk_lshlrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHLREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -206,13 +252,23 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHRREV_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshrrev_b16_e64_dpp" + : "v_pk_lshrrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHRREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -239,13 +295,23 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ASHRREV_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_ashrrev_i16_e64_dpp" + : "v_pk_ashrrev_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ASHRREV_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -272,13 +338,22 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_i16_e64_dpp" + : "v_pk_max_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -305,13 +380,22 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_i16_e64_dpp" + : "v_pk_min_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -344,13 +428,22 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_u16_e64_dpp" + : "v_pk_mad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -377,13 +470,22 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_u16_e64_dpp" + : "v_pk_add_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -410,13 +512,22 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_u16_e64_dpp" + : "v_pk_sub_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -443,13 +554,22 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_u16_e64_dpp" + : "v_pk_max_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -476,13 +596,22 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_u16_e64_dpp" + : "v_pk_min_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -515,13 +644,22 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMA_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fma_f16_e64_dpp" + : "v_pk_fma_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_FMA_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -548,13 +686,22 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_f16_e64_dpp" + : "v_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -581,13 +728,22 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_f16_e64_dpp" + : "v_pk_mul_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -614,13 +770,22 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_f16_e64_dpp" + : "v_pk_min_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -647,13 +812,22 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_f16_e64_dpp" + : "v_pk_max_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -706,7 +880,16 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f32_f16_e64_dpp" + : "v_dot2_f32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,13 +922,23 @@ VDot4I32Iu8Vop3p::VDot4I32Iu8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_I32_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_i32_iu8_e64_dpp" + : "v_dot4_i32_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_I32_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -778,13 +971,23 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_U32_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_u32_u8_e64_dpp" + : "v_dot4_u32_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -817,13 +1020,23 @@ VDot8I32Iu4Vop3p::VDot8I32Iu4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_I32_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_i32_iu4_e64_dpp" + : "v_dot8_i32_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_I32_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -856,13 +1069,23 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_U32_U4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_u32_u4_e64_dpp" + : "v_dot8_u32_u4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_U32_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -915,7 +1138,16 @@ VDot2F32Bf16Vop3p::VDot2F32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f32_bf16_e64_dpp" + : "v_dot2_f32_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -968,7 +1200,16 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mix_f32_e64_dpp" + : "v_fma_mix_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1022,7 +1263,16 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixlo_f16_e64_dpp" + : "v_fma_mixlo_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1332,16 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixhi_f16_e64_dpp" + : "v_fma_mixhi_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,13 +1369,23 @@ VWmmaF3216x16x16F16Vop3p::VWmmaF3216x16x16F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_f16_e64_dpp" + : "v_wmma_f32_16x16x16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1138,13 +1407,23 @@ VWmmaF3216x16x16Bf16Vop3p::VWmmaF3216x16x16Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_bf16_e64_dpp" + : "v_wmma_f32_16x16x16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1166,13 +1445,23 @@ VWmmaF1616x16x16F16Vop3p::VWmmaF1616x16x16F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X16_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x16_f16_e64_dpp" + : "v_wmma_f16_16x16x16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X16_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1194,13 +1483,23 @@ VWmmaBf1616x16x16Bf16Vop3p::VWmmaBf1616x16x16Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_BF16_16X16X16_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_bf16_16x16x16_bf16_e64_dpp" + : "v_wmma_bf16_16x16x16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_BF16_16X16X16_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1222,13 +1521,23 @@ VWmmaI3216x16x16Iu8Vop3p::VWmmaI3216x16x16Iu8Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X16_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x16_iu8_e64_dpp" + : "v_wmma_i32_16x16x16_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X16_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1250,13 +1559,23 @@ VWmmaI3216x16x16Iu4Vop3p::VWmmaI3216x16x16Iu4Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X16_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x16_iu4_e64_dpp" + : "v_wmma_i32_16x16x16_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X16_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopc.cpp index ea81305949fa..68add128374d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -55,7 +54,15 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f16_dpp" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +109,15 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_dpp" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -149,7 +164,15 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_dpp" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -196,7 +219,15 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_dpp" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +274,15 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_dpp" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +329,15 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_dpp" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +384,15 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_dpp" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +439,15 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_dpp" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -431,7 +494,15 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_dpp" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +549,15 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_dpp" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,7 +604,15 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_dpp" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +659,15 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_dpp" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -619,7 +714,15 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_dpp" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +769,15 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_dpp" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -713,7 +824,15 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_dpp" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -760,7 +879,15 @@ VCmpTF16Vopc::VCmpTF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f16_dpp" + : "v_cmp_t_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +931,15 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f32_dpp" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -848,7 +983,15 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_dpp" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -892,7 +1035,15 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_dpp" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -936,7 +1087,15 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_dpp" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -980,7 +1139,15 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_dpp" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1024,7 +1191,15 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_dpp" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1068,7 +1243,15 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_dpp" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1295,15 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_dpp" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1156,7 +1347,15 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_dpp" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1200,7 +1399,15 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_dpp" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1244,7 +1451,15 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_dpp" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1288,7 +1503,15 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_dpp" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1332,7 +1555,15 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_dpp" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1376,7 +1607,15 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_dpp" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1420,7 +1659,15 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_dpp" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1464,7 +1711,15 @@ VCmpTF32Vopc::VCmpTF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f32_dpp" + : "v_cmp_t_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1488,14 +1743,22 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f64_dpp" + : "v_cmp_f_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1519,14 +1782,22 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_dpp" + : "v_cmp_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1550,14 +1821,22 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_dpp" + : "v_cmp_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1581,14 +1860,22 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_dpp" + : "v_cmp_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1612,14 +1899,22 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_dpp" + : "v_cmp_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1643,14 +1938,22 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_dpp" + : "v_cmp_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1674,14 +1977,22 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_dpp" + : "v_cmp_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1705,14 +2016,22 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_dpp" + : "v_cmp_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1736,14 +2055,22 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_dpp" + : "v_cmp_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1767,14 +2094,22 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_dpp" + : "v_cmp_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1798,14 +2133,22 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_dpp" + : "v_cmp_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1829,14 +2172,22 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_dpp" + : "v_cmp_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1860,14 +2211,22 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_dpp" + : "v_cmp_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1891,14 +2250,22 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_dpp" + : "v_cmp_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1922,14 +2289,22 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_dpp" + : "v_cmp_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1953,14 +2328,22 @@ VCmpTF64Vopc::VCmpTF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f64_dpp" + : "v_cmp_t_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2007,7 +2390,15 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_dpp" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2054,7 +2445,15 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_dpp" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2101,7 +2500,15 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_dpp" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2148,7 +2555,15 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_dpp" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2195,7 +2610,15 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_dpp" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2242,7 +2665,15 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_dpp" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2289,7 +2720,15 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_dpp" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2336,7 +2775,15 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_dpp" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2383,7 +2830,15 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_dpp" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2430,7 +2885,15 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_dpp" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2477,7 +2940,15 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_dpp" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2524,7 +2995,15 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_dpp" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2568,7 +3047,15 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i32_dpp" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2612,7 +3099,15 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_dpp" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2656,7 +3151,15 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_dpp" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2700,7 +3203,15 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_dpp" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2744,7 +3255,15 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_dpp" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2788,7 +3307,15 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_dpp" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2832,7 +3359,15 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_dpp" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2876,7 +3411,15 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i32_dpp" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2920,7 +3463,15 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u32_dpp" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2964,7 +3515,15 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_dpp" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3008,7 +3567,15 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_dpp" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3052,7 +3619,15 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_dpp" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3096,7 +3671,15 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_dpp" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3140,7 +3723,15 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_dpp" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3184,7 +3775,15 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_dpp" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3228,7 +3827,15 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u32_dpp" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3252,14 +3859,22 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i64_dpp" + : "v_cmp_f_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3283,14 +3898,22 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_dpp" + : "v_cmp_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3314,14 +3937,22 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_dpp" + : "v_cmp_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3345,14 +3976,22 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_dpp" + : "v_cmp_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3376,14 +4015,22 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_dpp" + : "v_cmp_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3407,14 +4054,22 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_dpp" + : "v_cmp_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3438,14 +4093,22 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_dpp" + : "v_cmp_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3469,14 +4132,22 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i64_dpp" + : "v_cmp_t_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3500,14 +4171,22 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u64_dpp" + : "v_cmp_f_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3531,14 +4210,22 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_dpp" + : "v_cmp_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3562,14 +4249,22 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_dpp" + : "v_cmp_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3593,14 +4288,22 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_dpp" + : "v_cmp_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3624,14 +4327,22 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_dpp" + : "v_cmp_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3655,14 +4366,22 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_dpp" + : "v_cmp_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3686,14 +4405,22 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_dpp" + : "v_cmp_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3717,14 +4444,22 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u64_dpp" + : "v_cmp_t_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3771,7 +4506,16 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_dpp" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3815,7 +4559,16 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_dpp" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3839,14 +4592,23 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_dpp" + : "v_cmp_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3897,7 +4659,15 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f16_dpp" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3948,7 +4718,15 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_dpp" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3999,7 +4777,15 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_dpp" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4050,7 +4836,15 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_dpp" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4101,7 +4895,15 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_dpp" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4152,7 +4954,15 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_dpp" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4203,7 +5013,15 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_dpp" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4254,7 +5072,15 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_dpp" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4305,7 +5131,15 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_dpp" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4356,7 +5190,16 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_dpp" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4407,7 +5250,16 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_dpp" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4458,7 +5310,16 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_dpp" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4509,7 +5370,16 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_dpp" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4560,7 +5430,16 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_dpp" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4611,7 +5490,16 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_dpp" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4662,7 +5550,15 @@ VCmpxTF16Vopc::VCmpxTF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f16_dpp" + : "v_cmpx_t_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4710,7 +5606,15 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f32_dpp" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4758,7 +5662,15 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_dpp" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4806,7 +5718,15 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_dpp" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4854,7 +5774,15 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_dpp" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4902,7 +5830,15 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_dpp" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4950,7 +5886,15 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_dpp" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4998,7 +5942,15 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_dpp" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5046,7 +5998,15 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_dpp" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5094,7 +6054,15 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_dpp" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5142,7 +6110,16 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_dpp" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5190,7 +6167,16 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_dpp" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5238,7 +6224,16 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_dpp" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5286,7 +6281,16 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_dpp" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5334,7 +6338,16 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_dpp" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5382,7 +6395,16 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_dpp" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5430,7 +6452,15 @@ VCmpxTF32Vopc::VCmpxTF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f32_dpp" + : "v_cmpx_t_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5456,16 +6486,24 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f64_dpp" + : "v_cmpx_f_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5491,16 +6529,24 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_dpp" + : "v_cmpx_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5526,16 +6572,24 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_dpp" + : "v_cmpx_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5561,16 +6615,24 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_dpp" + : "v_cmpx_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5596,16 +6658,24 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_dpp" + : "v_cmpx_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5631,16 +6701,24 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_dpp" + : "v_cmpx_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5666,16 +6744,24 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_dpp" + : "v_cmpx_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5701,16 +6787,24 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_dpp" + : "v_cmpx_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5736,16 +6830,24 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_dpp" + : "v_cmpx_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5771,16 +6873,25 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_dpp" + : "v_cmpx_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5806,16 +6917,25 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_dpp" + : "v_cmpx_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5841,16 +6961,25 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_dpp" + : "v_cmpx_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5876,16 +7005,25 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_dpp" + : "v_cmpx_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5911,16 +7049,25 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_dpp" + : "v_cmpx_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5946,16 +7093,25 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_dpp" + : "v_cmpx_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5981,16 +7137,24 @@ VCmpxTF64Vopc::VCmpxTF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f64_dpp" + : "v_cmpx_t_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6041,7 +7205,15 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_dpp" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6092,7 +7264,15 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_dpp" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6143,7 +7323,15 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_dpp" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6194,7 +7382,15 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_dpp" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6245,7 +7441,15 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_dpp" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6296,7 +7500,15 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_dpp" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6347,7 +7559,15 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_dpp" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6398,7 +7618,15 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_dpp" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6449,7 +7677,15 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_dpp" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6500,7 +7736,15 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_dpp" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6551,7 +7795,15 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_dpp" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6602,7 +7854,15 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_dpp" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6650,7 +7910,15 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i32_dpp" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6698,7 +7966,15 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_dpp" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6746,7 +8022,15 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_dpp" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6794,7 +8078,15 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_dpp" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6842,7 +8134,15 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_dpp" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6890,7 +8190,15 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_dpp" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6938,7 +8246,15 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_dpp" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6986,7 +8302,15 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i32_dpp" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7034,7 +8358,15 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u32_dpp" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7082,7 +8414,15 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_dpp" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7130,7 +8470,15 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_dpp" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7178,7 +8526,15 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_dpp" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7226,7 +8582,15 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_dpp" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7274,7 +8638,15 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_dpp" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7322,7 +8694,15 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_dpp" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7370,7 +8750,15 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u32_dpp" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7396,16 +8784,24 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i64_dpp" + : "v_cmpx_f_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7431,16 +8827,24 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_dpp" + : "v_cmpx_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7466,16 +8870,24 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_dpp" + : "v_cmpx_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7501,16 +8913,24 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_dpp" + : "v_cmpx_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7536,16 +8956,24 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_dpp" + : "v_cmpx_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7571,16 +8999,24 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_dpp" + : "v_cmpx_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7606,16 +9042,24 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_dpp" + : "v_cmpx_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7641,16 +9085,24 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i64_dpp" + : "v_cmpx_t_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7676,16 +9128,24 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u64_dpp" + : "v_cmpx_f_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7711,16 +9171,24 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_dpp" + : "v_cmpx_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7746,16 +9214,24 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_dpp" + : "v_cmpx_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7781,16 +9257,24 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_dpp" + : "v_cmpx_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7816,16 +9300,24 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_dpp" + : "v_cmpx_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7851,16 +9343,24 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_dpp" + : "v_cmpx_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7886,16 +9386,24 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_dpp" + : "v_cmpx_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7921,16 +9429,24 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u64_dpp" + : "v_cmpx_t_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7981,7 +9497,16 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_dpp" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8029,7 +9554,16 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_dpp" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8055,16 +9589,25 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_dpp" + : "v_cmpx_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.cpp index e223251b5c84..708cf75dc392 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.cpp @@ -95,6 +95,24 @@ const char *Vopd::op_name(uint16_t op) { } } +Result Vopd::validate_encoding(const MachineInst *inst, const util::DiagnosticEmitter &emit_error) { + const auto *words = reinterpret_cast(inst); + const uint32_t word0 = words[0]; + const uint32_t word1 = words[1]; + + const uint16_t opx = static_cast((word0 >> 22) & 0xF); + const uint16_t opy = static_cast((word0 >> 17) & 0x1F); + if (!is_valid_opcode(opx, kVopdXOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD X opcode"; + if (!is_valid_opcode(opy, kVopdYOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcy0 == 254) [[unlikely]] + return emit_error.emit() << "VOPD does not support 64-bit literals"; + return Result::success(); +} + Vopd::Vopd(const MachineInst *inst) : IsaInstruction("vopd", selected_exec_fn(InstructionExecutionId::Vopd)), dstx_(32, OperandType::OPR_VGPR, 0), dsty_(32, OperandType::OPR_VGPR, 0), @@ -110,16 +128,10 @@ Vopd::Vopd(const MachineInst *inst) encoding_id_ = 0x32; opx_ = static_cast((word0_ >> 22) & 0xF); opy_ = static_cast((word0_ >> 17) & 0x1F); - if (!is_valid_opcode(opx_, kVopdXOpcodeMask)) - throw util::InvalidInst("invalid VOPD X opcode", ""); - if (!is_valid_opcode(opy_, kVopdYOpcodeMask)) - throw util::InvalidInst("invalid VOPD Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t vsrcx1 = static_cast((word0_ >> 9) & 0xFF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); uint16_t vsrcy1 = static_cast((word1_ >> 9) & 0xFF); - if (srcx0 == 254 || srcy0 == 254) - throw util::InvalidInst("VOPD does not support 64-bit literals", ""); uint16_t vdstx = static_cast((word1_ >> 24) & 0xFF); uint16_t vdsty_hi = static_cast((word1_ >> 17) & 0x7F); uint16_t vdsty = static_cast((vdsty_hi << 1) | ((~vdstx) & 1u)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.h index 7daa1ef45fc9..ad8914f4d055 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/vopd.h @@ -9,6 +9,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/encodings.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.h" +#include "rocjitsu/isa/decode_result.h" #include #include @@ -18,6 +19,8 @@ namespace rdna3 { class Vopd : public IsaInstruction { public: explicit Vopd(const MachineInst *inst); + static Result validate_encoding(const MachineInst *inst, + const util::DiagnosticEmitter &emit_error); void execute_impl(amdgpu::Wavefront &wf); private: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.cpp index 83e7c734f0c6..d51b9d8ee73e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.h" -#include "util/except.h" #include #include #include @@ -16,1463 +15,1920 @@ namespace rocjitsu { namespace rdna3_5 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB128Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB96Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16B16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16I8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16U8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadLdsB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadLdsFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadLdsI16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadLdsI8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadLdsU16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadLdsU8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB128Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB32Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB64Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB96Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddGsRegRtnDs(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsBvhStackRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode); -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsNopDs(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreAddtidB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB128Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8D16HiDs(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB96Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubGsRegRtnDs(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode); -std::unique_ptr decodeExpExp(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinF32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB128Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB96Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16B16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiB16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiI8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiU8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16I8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16U8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB128Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB32Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB64Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB8Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB96Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB16Flat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB8Flat(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode); -std::unique_ptr decodeImageBvh64IntersectRayMimg(const MachineInst *opcode); -std::unique_ptr decodeImageBvhIntersectRayMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode); -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode); -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode); -std::unique_ptr decodeLdsDirectLoadLdsdir(const MachineInst *opcode); -std::unique_ptr decodeLdsParamLoadLdsdir(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCeilF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCeilF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode); -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNeqF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNeqF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNleF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNleF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNlgF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNlgF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNltF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNltF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpOF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpOF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpUF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpUF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF16F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32F16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32I32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtHiF32F16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtI32F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCvtU32F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode); -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFloorF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFloorF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFmaakF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmacF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmacF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmamkF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRndneF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRndneF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSSubF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTruncF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTruncF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitEventSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2F16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2accF32F16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10F16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane64B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16B16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16I8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16U8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadLdsB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadLdsFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadLdsI16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadLdsI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadLdsU16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadLdsU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddGsRegRtnDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBvhStackRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16HiDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubGsRegRtnDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB32Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB64Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB96Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16B16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiI8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiU8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16I8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16U8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI16Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU16Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB96Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvh64IntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvhIntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeLdsDirectLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeLdsParamLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCeilF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCeilF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNeqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNeqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNleF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNleF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNlgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNlgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNltF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNltF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpOF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpOF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpUF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpUF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF16F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32F16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32I32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtHiF32F16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtI32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtU32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFloorF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFloorF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmaakF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmacF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmacF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmamkF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRndneF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRndneF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTruncF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTruncF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitEventSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2accF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane64B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr decodeVopd(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeVinterp(const MachineInst *opcode); - static std::unique_ptr subDecodeLdsdir(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeDs(const MachineInst *opcode); - static std::unique_ptr subDecodeFlat(const MachineInst *opcode); - static std::unique_ptr subDecodeMubuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMtbuf(const MachineInst *opcode); - static std::unique_ptr subDecodeMimg(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult decodeVopd(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1491,97 +1947,116 @@ struct DecoderImpl { static const std::array sub_decode_smem; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::decodeVopd(const MachineInst *opcode) { +DecodeResult DecoderImpl::decodeVopd(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vopd::validate_encoding(opcode, emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVinterp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vinterp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vinterp[op.op](opcode); + return sub_decode_vinterp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeLdsdir(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ldsdir::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ldsdir[op.op](opcode); + return sub_decode_ldsdir[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeDs(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Ds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_ds[op.op](opcode); + return sub_decode_ds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeFlat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeFlat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Flat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_flat[op.op](opcode); + return sub_decode_flat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMubuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mubuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mubuf[op.op](opcode); + return sub_decode_mubuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMtbuf(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mtbuf::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mtbuf[op.op](opcode); + return sub_decode_mtbuf[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeMimg(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Mimg::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_mimg[op.op](opcode); + return sub_decode_mimg[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h index 0ba661ab2a80..6151393ce561 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA3_5_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace rdna3_5 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 3; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace rdna3_5 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ds.cpp index 7ca77efd246d..ad79d1cc2c6e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ds.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,11 @@ DsAddU32Ds::DsAddU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ DsSubU32Ds::DsSubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +84,11 @@ DsRsubU32Ds::DsRsubU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +111,11 @@ DsIncU32Ds::DsIncU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +138,11 @@ DsDecU32Ds::DsDecU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +165,11 @@ DsMinI32Ds::DsMinI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ DsMaxI32Ds::DsMaxI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +219,11 @@ DsMinU32Ds::DsMinU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +246,11 @@ DsMaxU32Ds::DsMaxU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +273,11 @@ DsAndB32Ds::DsAndB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +300,11 @@ DsOrB32Ds::DsOrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +327,11 @@ DsXorB32Ds::DsXorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -309,7 +356,11 @@ DsMskorB32Ds::DsMskorB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +381,11 @@ DsStoreB32Ds::DsStoreB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +408,12 @@ DsStore2addrB32Ds::DsStore2addrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +436,12 @@ DsStore2addrStride64B32Ds::DsStore2addrStride64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +466,12 @@ DsCmpstoreB32Ds::DsCmpstoreB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -426,7 +496,12 @@ DsCmpstoreF32Ds::DsCmpstoreF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -449,7 +524,11 @@ DsMinF32Ds::DsMinF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +551,11 @@ DsMaxF32Ds::DsMaxF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +568,11 @@ DsNopDs::DsNopDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopDs(const MachineInst *opcode) { +DecodeResult decodeDsNopDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -508,7 +595,11 @@ DsAddF32Ds::DsAddF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +612,12 @@ DsGwsSemaReleaseAllDs::DsGwsSemaReleaseAllDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaReleaseAllDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_release_all", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -536,7 +632,11 @@ DsGwsInitDs::DsGwsInitDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsInitDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsInitDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_init", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -549,7 +649,11 @@ DsGwsSemaVDs::DsGwsSemaVDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaVDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaVDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_v", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +668,11 @@ DsGwsSemaBrDs::DsGwsSemaBrDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaBrDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaBrDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_br", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -577,7 +685,11 @@ DsGwsSemaPDs::DsGwsSemaPDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsSemaPDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsSemaPDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_sema_p", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -592,7 +704,11 @@ DsGwsBarrierDs::DsGwsBarrierDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsGwsBarrierDs(const MachineInst *opcode) { +DecodeResult decodeDsGwsBarrierDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_gws_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -613,7 +729,11 @@ DsStoreB8Ds::DsStoreB8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -634,7 +754,11 @@ DsStoreB16Ds::DsStoreB16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +783,11 @@ DsAddRtnU32Ds::DsAddRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -684,7 +812,11 @@ DsSubRtnU32Ds::DsSubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -709,7 +841,11 @@ DsRsubRtnU32Ds::DsRsubRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -734,7 +870,11 @@ DsIncRtnU32Ds::DsIncRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -759,7 +899,11 @@ DsDecRtnU32Ds::DsDecRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -784,7 +928,11 @@ DsMinRtnI32Ds::DsMinRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -809,7 +957,11 @@ DsMaxRtnI32Ds::DsMaxRtnI32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +986,11 @@ DsMinRtnU32Ds::DsMinRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1015,11 @@ DsMaxRtnU32Ds::DsMaxRtnU32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -884,7 +1044,11 @@ DsAndRtnB32Ds::DsAndRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -909,7 +1073,11 @@ DsOrRtnB32Ds::DsOrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -934,7 +1102,11 @@ DsXorRtnB32Ds::DsXorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -961,7 +1133,12 @@ DsMskorRtnB32Ds::DsMskorRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -986,7 +1163,12 @@ DsStorexchgRtnB32Ds::DsStorexchgRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1013,7 +1195,12 @@ DsStorexchg2addrRtnB32Ds::DsStorexchg2addrRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_2addr_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1040,7 +1227,13 @@ DsStorexchg2addrStride64RtnB32Ds::DsStorexchg2addrStride64RtnB32Ds(const Machine } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1260,12 @@ DsCmpstoreRtnB32Ds::DsCmpstoreRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1094,7 +1292,12 @@ DsCmpstoreRtnF32Ds::DsCmpstoreRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnF32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1119,7 +1322,11 @@ DsMinRtnF32Ds::DsMinRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1351,11 @@ DsMaxRtnF32Ds::DsMaxRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1170,7 +1381,11 @@ DsWrapRtnB32Ds::DsWrapRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsWrapRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsWrapRtnB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_wrap_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,7 +1402,11 @@ DsSwizzleB32Ds::DsSwizzleB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1208,7 +1427,11 @@ DsLoadB32Ds::DsLoadB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1229,7 +1452,12 @@ DsLoad2addrB32Ds::DsLoad2addrB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1250,7 +1478,12 @@ DsLoad2addrStride64B32Ds::DsLoad2addrStride64B32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1504,11 @@ DsLoadI8Ds::DsLoadI8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1292,7 +1529,11 @@ DsLoadU8Ds::DsLoadU8Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1313,7 +1554,11 @@ DsLoadI16Ds::DsLoadI16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1334,7 +1579,11 @@ DsLoadU16Ds::DsLoadU16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1355,7 +1604,11 @@ DsConsumeDs::DsConsumeDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeDs(const MachineInst *opcode) { +DecodeResult decodeDsConsumeDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1376,7 +1629,11 @@ DsAppendDs::DsAppendDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendDs(const MachineInst *opcode) { +DecodeResult decodeDsAppendDs(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1658,12 @@ DsOrderedCountDs::DsOrderedCountDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrderedCountDs(const MachineInst *opcode) { +DecodeResult decodeDsOrderedCountDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_ordered_count", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1424,7 +1686,11 @@ DsAddU64Ds::DsAddU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1447,7 +1713,11 @@ DsSubU64Ds::DsSubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1470,7 +1740,11 @@ DsRsubU64Ds::DsRsubU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1493,7 +1767,11 @@ DsIncU64Ds::DsIncU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1516,7 +1794,11 @@ DsDecU64Ds::DsDecU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1539,7 +1821,11 @@ DsMinI64Ds::DsMinI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1562,7 +1848,11 @@ DsMaxI64Ds::DsMaxI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1585,7 +1875,11 @@ DsMinU64Ds::DsMinU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1608,7 +1902,11 @@ DsMaxU64Ds::DsMaxU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1631,7 +1929,11 @@ DsAndB64Ds::DsAndB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1654,7 +1956,11 @@ DsOrB64Ds::DsOrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1677,7 +1983,11 @@ DsXorB64Ds::DsXorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1702,7 +2012,11 @@ DsMskorB64Ds::DsMskorB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1723,7 +2037,11 @@ DsStoreB64Ds::DsStoreB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1746,7 +2064,12 @@ DsStore2addrB64Ds::DsStore2addrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1769,7 +2092,12 @@ DsStore2addrStride64B64Ds::DsStore2addrStride64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1794,7 +2122,12 @@ DsCmpstoreB64Ds::DsCmpstoreB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,7 +2152,12 @@ DsCmpstoreF64Ds::DsCmpstoreF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1842,7 +2180,11 @@ DsMinF64Ds::DsMinF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1865,7 +2207,11 @@ DsMaxF64Ds::DsMaxF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1890,7 +2236,11 @@ DsAddRtnU64Ds::DsAddRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1915,7 +2265,11 @@ DsSubRtnU64Ds::DsSubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1940,7 +2294,11 @@ DsRsubRtnU64Ds::DsRsubRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1965,7 +2323,11 @@ DsIncRtnU64Ds::DsIncRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1990,7 +2352,11 @@ DsDecRtnU64Ds::DsDecRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2015,7 +2381,11 @@ DsMinRtnI64Ds::DsMinRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2040,7 +2410,11 @@ DsMaxRtnI64Ds::DsMaxRtnI64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2065,7 +2439,11 @@ DsMinRtnU64Ds::DsMinRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2090,7 +2468,11 @@ DsMaxRtnU64Ds::DsMaxRtnU64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2115,7 +2497,11 @@ DsAndRtnB64Ds::DsAndRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2140,7 +2526,11 @@ DsOrRtnB64Ds::DsOrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2165,7 +2555,11 @@ DsXorRtnB64Ds::DsXorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2192,7 +2586,12 @@ DsMskorRtnB64Ds::DsMskorRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2217,7 +2616,12 @@ DsStorexchgRtnB64Ds::DsStorexchgRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2244,7 +2648,12 @@ DsStorexchg2addrRtnB64Ds::DsStorexchg2addrRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_storexchg_2addr_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2271,7 +2680,13 @@ DsStorexchg2addrStride64RtnB64Ds::DsStorexchg2addrStride64RtnB64Ds(const Machine } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Ds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2298,7 +2713,12 @@ DsCmpstoreRtnB64Ds::DsCmpstoreRtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2745,12 @@ DsCmpstoreRtnF64Ds::DsCmpstoreRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnF64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_cmpstore_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2350,7 +2775,11 @@ DsMinRtnF64Ds::DsMinRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_min_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2375,7 +2804,11 @@ DsMaxRtnF64Ds::DsMaxRtnF64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnF64Ds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnF64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_max_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2396,7 +2829,11 @@ DsLoadB64Ds::DsLoadB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB64Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2417,7 +2854,12 @@ DsLoad2addrB64Ds::DsLoad2addrB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2438,7 +2880,12 @@ DsLoad2addrStride64B64Ds::DsLoad2addrStride64B64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2463,7 +2910,11 @@ DsAddRtnF32Ds::DsAddRtnF32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Ds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2480,7 +2931,12 @@ DsAddGsRegRtnDs::DsAddGsRegRtnDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddGsRegRtnDs(const MachineInst *opcode) { +DecodeResult decodeDsAddGsRegRtnDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_add_gs_reg_rtn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2497,7 +2953,12 @@ DsSubGsRegRtnDs::DsSubGsRegRtnDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubGsRegRtnDs(const MachineInst *opcode) { +DecodeResult decodeDsSubGsRegRtnDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_sub_gs_reg_rtn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2522,7 +2983,12 @@ DsCondxchg32RtnB64Ds::DsCondxchg32RtnB64Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2543,7 +3009,12 @@ DsStoreB8D16HiDs::DsStoreB8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2564,7 +3035,12 @@ DsStoreB16D16HiDs::DsStoreB16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2585,7 +3061,11 @@ DsLoadU8D16Ds::DsLoadU8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2612,7 +3092,12 @@ DsLoadU8D16HiDs::DsLoadU8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2639,7 +3124,11 @@ DsLoadI8D16Ds::DsLoadI8D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2666,7 +3155,12 @@ DsLoadI8D16HiDs::DsLoadI8D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2693,7 +3187,11 @@ DsLoadU16D16Ds::DsLoadU16D16Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2720,7 +3218,12 @@ DsLoadU16D16HiDs::DsLoadU16D16HiDs(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16HiDs(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16HiDs(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2753,7 +3256,12 @@ DsBvhStackRtnB32Ds::DsBvhStackRtnB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBvhStackRtnB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBvhStackRtnB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bvh_stack_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2774,7 +3282,12 @@ DsStoreAddtidB32Ds::DsStoreAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2795,7 +3308,12 @@ DsLoadAddtidB32Ds::DsLoadAddtidB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadAddtidB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadAddtidB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2814,7 +3332,11 @@ DsPermuteB32Ds::DsPermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2833,7 +3355,12 @@ DsBpermuteB32Ds::DsBpermuteB32Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Ds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Ds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2854,7 +3381,11 @@ DsStoreB96Ds::DsStoreB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2875,7 +3406,11 @@ DsStoreB128Ds::DsStoreB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2896,7 +3431,11 @@ DsLoadB96Ds::DsLoadB96Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB96Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB96Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2917,7 +3456,11 @@ DsLoadB128Ds::DsLoadB128Ds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB128Ds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB128Ds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Ds::validate_encoding( + "ds_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp index d672d80b6c6c..75a3182c4542 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.cpp @@ -5,7 +5,6 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h" -#include "util/except.h" #include #include @@ -1219,9 +1218,6 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -1319,9 +1315,6 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -1528,9 +1521,6 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h index f545ed267776..ac9ca6544580 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/rdna3_5/isa.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include @@ -518,6 +519,15 @@ class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3MachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -544,6 +554,15 @@ class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3pMachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -633,6 +652,15 @@ class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3SdstEncMachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/exp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/exp.cpp index a48a1b0e5714..8e6ea5c9004c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/exp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/exp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/exp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ ExpExp::ExpExp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeExpExp(const MachineInst *opcode) { +DecodeResult decodeExpExp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = + Exp::validate_encoding("exp", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/flat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/flat.cpp index 7c66972f1d8c..e610074b4eb1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/flat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/flat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/flat.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -40,7 +39,11 @@ FlatLoadU8Flat::FlatLoadU8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -72,7 +75,11 @@ FlatLoadI8Flat::FlatLoadI8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI8Flat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -104,7 +111,12 @@ FlatLoadU16Flat::FlatLoadU16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -136,7 +148,12 @@ FlatLoadI16Flat::FlatLoadI16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -168,7 +185,12 @@ FlatLoadB32Flat::FlatLoadB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -200,7 +222,12 @@ FlatLoadB64Flat::FlatLoadB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -232,7 +259,12 @@ FlatLoadB96Flat::FlatLoadB96Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB96Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB96Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +296,12 @@ FlatLoadB128Flat::FlatLoadB128Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB128Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -296,7 +333,12 @@ FlatStoreB8Flat::FlatStoreB8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -328,7 +370,12 @@ FlatStoreB16Flat::FlatStoreB16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -360,7 +407,12 @@ FlatStoreB32Flat::FlatStoreB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -392,7 +444,12 @@ FlatStoreB64Flat::FlatStoreB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +481,12 @@ FlatStoreB96Flat::FlatStoreB96Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB96Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB96Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -456,7 +518,12 @@ FlatStoreB128Flat::FlatStoreB128Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB128Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB128Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -488,7 +555,12 @@ FlatLoadD16U8Flat::FlatLoadD16U8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16U8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16U8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -526,7 +598,12 @@ FlatLoadD16I8Flat::FlatLoadD16I8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16I8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16I8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -564,7 +641,12 @@ FlatLoadD16B16Flat::FlatLoadD16B16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16B16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16B16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +684,12 @@ FlatLoadD16HiU8Flat::FlatLoadD16HiU8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiU8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiU8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -640,7 +727,12 @@ FlatLoadD16HiI8Flat::FlatLoadD16HiI8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiI8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiI8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +770,12 @@ FlatLoadD16HiB16Flat::FlatLoadD16HiB16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiB16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -716,7 +813,12 @@ FlatStoreD16HiB8Flat::FlatStoreD16HiB8Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB8Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB8Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -748,7 +850,12 @@ FlatStoreD16HiB16Flat::FlatStoreD16HiB16Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB16Flat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB16Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -783,7 +890,12 @@ FlatAtomicSwapB32Flat::FlatAtomicSwapB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -818,7 +930,12 @@ FlatAtomicCmpswapB32Flat::FlatAtomicCmpswapB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -853,7 +970,12 @@ FlatAtomicAddU32Flat::FlatAtomicAddU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -888,7 +1010,12 @@ FlatAtomicSubU32Flat::FlatAtomicSubU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1050,12 @@ FlatAtomicMinI32Flat::FlatAtomicMinI32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1090,12 @@ FlatAtomicMinU32Flat::FlatAtomicMinU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -993,7 +1130,12 @@ FlatAtomicMaxI32Flat::FlatAtomicMaxI32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1028,7 +1170,12 @@ FlatAtomicMaxU32Flat::FlatAtomicMaxU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1063,7 +1210,12 @@ FlatAtomicAndB32Flat::FlatAtomicAndB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1250,12 @@ FlatAtomicOrB32Flat::FlatAtomicOrB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1133,7 +1290,12 @@ FlatAtomicXorB32Flat::FlatAtomicXorB32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1168,7 +1330,12 @@ FlatAtomicIncU32Flat::FlatAtomicIncU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1203,7 +1370,12 @@ FlatAtomicDecU32Flat::FlatAtomicDecU32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1410,12 @@ FlatAtomicSwapB64Flat::FlatAtomicSwapB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1273,7 +1450,12 @@ FlatAtomicCmpswapB64Flat::FlatAtomicCmpswapB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1308,7 +1490,12 @@ FlatAtomicAddU64Flat::FlatAtomicAddU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1343,7 +1530,12 @@ FlatAtomicSubU64Flat::FlatAtomicSubU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1378,7 +1570,12 @@ FlatAtomicMinI64Flat::FlatAtomicMinI64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1413,7 +1610,12 @@ FlatAtomicMinU64Flat::FlatAtomicMinU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1448,7 +1650,12 @@ FlatAtomicMaxI64Flat::FlatAtomicMaxI64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1483,7 +1690,12 @@ FlatAtomicMaxU64Flat::FlatAtomicMaxU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1518,7 +1730,12 @@ FlatAtomicAndB64Flat::FlatAtomicAndB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1553,7 +1770,12 @@ FlatAtomicOrB64Flat::FlatAtomicOrB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1588,7 +1810,12 @@ FlatAtomicXorB64Flat::FlatAtomicXorB64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1623,7 +1850,12 @@ FlatAtomicIncU64Flat::FlatAtomicIncU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1658,7 +1890,12 @@ FlatAtomicDecU64Flat::FlatAtomicDecU64Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU64Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU64Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1693,7 +1930,12 @@ FlatAtomicCmpswapF32Flat::FlatAtomicCmpswapF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_cmpswap_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1728,7 +1970,12 @@ FlatAtomicMinF32Flat::FlatAtomicMinF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1763,7 +2010,12 @@ FlatAtomicMaxF32Flat::FlatAtomicMaxF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1798,7 +2050,12 @@ FlatAtomicAddF32Flat::FlatAtomicAddF32Flat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF32Flat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF32Flat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Flat::validate_encoding( + "flat_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ldsdir.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ldsdir.cpp index f96447bdd780..175d1666b090 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ldsdir.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ldsdir.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/ldsdir.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,12 @@ LdsParamLoadLdsdir::LdsParamLoadLdsdir(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeLdsParamLoadLdsdir(const MachineInst *opcode) { +DecodeResult decodeLdsParamLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ldsdir::validate_encoding( + "lds_param_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ LdsDirectLoadLdsdir::LdsDirectLoadLdsdir(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeLdsDirectLoadLdsdir(const MachineInst *opcode) { +DecodeResult decodeLdsDirectLoadLdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Ldsdir::validate_encoding( + "lds_direct_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mimg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mimg.cpp index 9c43801a2634..c2122f7145b4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mimg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mimg.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mimg.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -26,7 +25,11 @@ ImageLoadMimg::ImageLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -45,7 +48,12 @@ ImageLoadMipMimg::ImageLoadMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +72,12 @@ ImageLoadPckMimg::ImageLoadPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +96,12 @@ ImageLoadPckSgnMimg::ImageLoadPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +120,12 @@ ImageLoadMipPckMimg::ImageLoadMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +144,12 @@ ImageLoadMipPckSgnMimg::ImageLoadMipPckSgnMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnMimg(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +168,11 @@ ImageStoreMimg::ImageStoreMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMimg(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +191,12 @@ ImageStoreMipMimg::ImageStoreMipMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -178,7 +215,12 @@ ImageStorePckMimg::ImageStorePckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStorePckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -197,7 +239,12 @@ ImageStoreMipPckMimg::ImageStoreMipPckMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckMimg(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -217,7 +264,12 @@ ImageAtomicSwapMimg::ImageAtomicSwapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -237,7 +289,12 @@ ImageAtomicCmpswapMimg::ImageAtomicCmpswapMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -257,7 +314,12 @@ ImageAtomicAddMimg::ImageAtomicAddMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_add", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -277,7 +339,12 @@ ImageAtomicSubMimg::ImageAtomicSubMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_sub", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -297,7 +364,12 @@ ImageAtomicSminMimg::ImageAtomicSminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -317,7 +389,12 @@ ImageAtomicUminMimg::ImageAtomicUminMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUminMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUminMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umin", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +414,12 @@ ImageAtomicSmaxMimg::ImageAtomicSmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_smax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +439,12 @@ ImageAtomicUmaxMimg::ImageAtomicUmaxMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicUmaxMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicUmaxMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_umax", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -377,7 +464,12 @@ ImageAtomicAndMimg::ImageAtomicAndMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -397,7 +489,12 @@ ImageAtomicOrMimg::ImageAtomicOrMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -417,7 +514,12 @@ ImageAtomicXorMimg::ImageAtomicXorMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -437,7 +539,12 @@ ImageAtomicIncMimg::ImageAtomicIncMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_inc", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +564,12 @@ ImageAtomicDecMimg::ImageAtomicDecMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecMimg(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_atomic_dec", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -476,7 +588,12 @@ ImageGetResinfoMimg::ImageGetResinfoMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -495,7 +612,12 @@ ImageMsaaLoadMimg::ImageMsaaLoadMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageMsaaLoadMimg(const MachineInst *opcode) { +DecodeResult decodeImageMsaaLoadMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_msaa_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -514,7 +636,12 @@ ImageBvhIntersectRayMimg::ImageBvhIntersectRayMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvhIntersectRayMimg(const MachineInst *opcode) { +DecodeResult decodeImageBvhIntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_bvh_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -533,7 +660,12 @@ ImageBvh64IntersectRayMimg::ImageBvh64IntersectRayMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvh64IntersectRayMimg(const MachineInst *opcode) { +DecodeResult decodeImageBvh64IntersectRayMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_bvh64_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -554,7 +686,12 @@ ImageSampleMimg::ImageSampleMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -575,7 +712,12 @@ ImageSampleDMimg::ImageSampleDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -596,7 +738,12 @@ ImageSampleLMimg::ImageSampleLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +764,12 @@ ImageSampleBMimg::ImageSampleBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +790,12 @@ ImageSampleLzMimg::ImageSampleLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +816,12 @@ ImageSampleCMimg::ImageSampleCMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -680,7 +842,12 @@ ImageSampleCDMimg::ImageSampleCDMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -701,7 +868,12 @@ ImageSampleCLMimg::ImageSampleCLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -722,7 +894,12 @@ ImageSampleCBMimg::ImageSampleCBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -743,7 +920,12 @@ ImageSampleCLzMimg::ImageSampleCLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -764,7 +946,12 @@ ImageSampleOMimg::ImageSampleOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -785,7 +972,12 @@ ImageSampleDOMimg::ImageSampleDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -806,7 +998,12 @@ ImageSampleLOMimg::ImageSampleLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -827,7 +1024,12 @@ ImageSampleBOMimg::ImageSampleBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -848,7 +1050,12 @@ ImageSampleLzOMimg::ImageSampleLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -869,7 +1076,12 @@ ImageSampleCOMimg::ImageSampleCOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1102,12 @@ ImageSampleCDOMimg::ImageSampleCDOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -911,7 +1128,12 @@ ImageSampleCLOMimg::ImageSampleCLOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -932,7 +1154,12 @@ ImageSampleCBOMimg::ImageSampleCBOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -953,7 +1180,12 @@ ImageSampleCLzOMimg::ImageSampleCLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -974,7 +1206,12 @@ ImageGather4Mimg::ImageGather4Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4Mimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1232,12 @@ ImageGather4LMimg::ImageGather4LMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1258,12 @@ ImageGather4BMimg::ImageGather4BMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1037,7 +1284,12 @@ ImageGather4LzMimg::ImageGather4LzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1058,7 +1310,12 @@ ImageGather4CMimg::ImageGather4CMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1079,7 +1336,12 @@ ImageGather4CLzMimg::ImageGather4CLzMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1100,7 +1362,12 @@ ImageGather4OMimg::ImageGather4OMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4OMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4OMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1388,12 @@ ImageGather4LzOMimg::ImageGather4LzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1414,12 @@ ImageGather4CLzOMimg::ImageGather4CLzOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzOMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1163,7 +1440,12 @@ ImageGetLodMimg::ImageGetLodMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetLodMimg(const MachineInst *opcode) { +DecodeResult decodeImageGetLodMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_get_lod", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1184,7 +1466,12 @@ ImageSampleDG16Mimg::ImageSampleDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1492,12 @@ ImageSampleCDG16Mimg::ImageSampleCDG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1226,7 +1518,12 @@ ImageSampleDOG16Mimg::ImageSampleDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1247,7 +1544,12 @@ ImageSampleCDOG16Mimg::ImageSampleCDOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1268,7 +1570,12 @@ ImageSampleClMimg::ImageSampleClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1289,7 +1596,12 @@ ImageSampleDClMimg::ImageSampleDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1310,7 +1622,12 @@ ImageSampleBClMimg::ImageSampleBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,7 +1648,12 @@ ImageSampleCClMimg::ImageSampleCClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1674,12 @@ ImageSampleCDClMimg::ImageSampleCDClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1373,7 +1700,12 @@ ImageSampleCBClMimg::ImageSampleCBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1726,12 @@ ImageSampleClOMimg::ImageSampleClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1415,7 +1752,12 @@ ImageSampleDClOMimg::ImageSampleDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1436,7 +1778,12 @@ ImageSampleBClOMimg::ImageSampleBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1804,12 @@ ImageSampleCClOMimg::ImageSampleCClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1478,7 +1830,12 @@ ImageSampleCDClOMimg::ImageSampleCDClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1499,7 +1856,12 @@ ImageSampleCBClOMimg::ImageSampleCBClOMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClOMimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClOMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1882,12 @@ ImageSampleCDClG16Mimg::ImageSampleCDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1908,12 @@ ImageSampleDClOG16Mimg::ImageSampleDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1562,7 +1934,12 @@ ImageSampleCDClOG16Mimg::ImageSampleCDClOG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_c_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1583,7 +1960,12 @@ ImageSampleDClG16Mimg::ImageSampleDClG16Mimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClG16Mimg(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClG16Mimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_sample_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1604,7 +1986,12 @@ ImageGather4ClMimg::ImageGather4ClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1625,7 +2012,12 @@ ImageGather4BClMimg::ImageGather4BClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1646,7 +2038,12 @@ ImageGather4CClMimg::ImageGather4CClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1667,7 +2064,12 @@ ImageGather4CLMimg::ImageGather4CLMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1688,7 +2090,12 @@ ImageGather4CBMimg::ImageGather4CBMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1709,7 +2116,12 @@ ImageGather4CBClMimg::ImageGather4CBClMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1730,7 +2142,12 @@ ImageGather4hMimg::ImageGather4hMimg(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hMimg(const MachineInst *opcode) { +DecodeResult decodeImageGather4hMimg(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mimg::validate_encoding( + "image_gather4h", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mtbuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mtbuf.cpp index 414fbf836d69..8b0d5651bfbb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mtbuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mtbuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mtbuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ TbufferLoadFormatXMtbuf::TbufferLoadFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +70,12 @@ TbufferLoadFormatXyMtbuf::TbufferLoadFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ TbufferLoadFormatXyzMtbuf::TbufferLoadFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +128,12 @@ TbufferLoadFormatXyzwMtbuf::TbufferLoadFormatXyzwMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -138,7 +157,12 @@ TbufferStoreFormatXMtbuf::TbufferStoreFormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +186,12 @@ TbufferStoreFormatXyMtbuf::TbufferStoreFormatXyMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +215,12 @@ TbufferStoreFormatXyzMtbuf::TbufferStoreFormatXyzMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -210,7 +244,12 @@ TbufferStoreFormatXyzwMtbuf::TbufferStoreFormatXyzwMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +273,12 @@ TbufferLoadD16FormatXMtbuf::TbufferLoadD16FormatXMtbuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mtbuf::validate_encoding( + "tbuffer_load_d16_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +308,13 @@ TbufferLoadD16FormatXyMtbuf::TbufferLoadD16FormatXyMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +338,13 @@ TbufferLoadD16FormatXyzMtbuf::TbufferLoadD16FormatXyzMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +374,13 @@ TbufferLoadD16FormatXyzwMtbuf::TbufferLoadD16FormatXyzwMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_load_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +404,13 @@ TbufferStoreD16FormatXMtbuf::TbufferStoreD16FormatXMtbuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +434,13 @@ TbufferStoreD16FormatXyMtbuf::TbufferStoreD16FormatXyMtbuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +464,13 @@ TbufferStoreD16FormatXyzMtbuf::TbufferStoreD16FormatXyzMtbuf(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyzMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -414,7 +494,13 @@ TbufferStoreD16FormatXyzwMtbuf::TbufferStoreD16FormatXyzwMtbuf(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyzwMtbuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mtbuf::validate_encoding("tbuffer_store_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mubuf.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mubuf.cpp index 529c5cb2c1ec..40dc9ae93be0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mubuf.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mubuf.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/mubuf.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -42,7 +41,12 @@ BufferLoadFormatXMubuf::BufferLoadFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -66,7 +70,12 @@ BufferLoadFormatXyMubuf::BufferLoadFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ BufferLoadFormatXyzMubuf::BufferLoadFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +128,12 @@ BufferLoadFormatXyzwMubuf::BufferLoadFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -138,7 +157,12 @@ BufferStoreFormatXMubuf::BufferStoreFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -162,7 +186,12 @@ BufferStoreFormatXyMubuf::BufferStoreFormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -186,7 +215,12 @@ BufferStoreFormatXyzMubuf::BufferStoreFormatXyzMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -210,7 +244,12 @@ BufferStoreFormatXyzwMubuf::BufferStoreFormatXyzwMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +273,12 @@ BufferLoadD16FormatXMubuf::BufferLoadD16FormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -264,7 +308,12 @@ BufferLoadD16FormatXyMubuf::BufferLoadD16FormatXyMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -288,7 +337,13 @@ BufferLoadD16FormatXyzMubuf::BufferLoadD16FormatXyzMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -318,7 +373,13 @@ BufferLoadD16FormatXyzwMubuf::BufferLoadD16FormatXyzwMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +403,12 @@ BufferStoreD16FormatXMubuf::BufferStoreD16FormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_d16_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -366,7 +432,13 @@ BufferStoreD16FormatXyMubuf::BufferStoreD16FormatXyMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +462,13 @@ BufferStoreD16FormatXyzMubuf::BufferStoreD16FormatXyzMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyzMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -414,7 +492,13 @@ BufferStoreD16FormatXyzwMubuf::BufferStoreD16FormatXyzwMubuf(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyzwMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -438,7 +522,12 @@ BufferLoadU8Mubuf::BufferLoadU8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -462,7 +551,12 @@ BufferLoadI8Mubuf::BufferLoadI8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -486,7 +580,12 @@ BufferLoadU16Mubuf::BufferLoadU16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -510,7 +609,12 @@ BufferLoadI16Mubuf::BufferLoadI16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -534,7 +638,12 @@ BufferLoadB32Mubuf::BufferLoadB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -558,7 +667,12 @@ BufferLoadB64Mubuf::BufferLoadB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -582,7 +696,12 @@ BufferLoadB96Mubuf::BufferLoadB96Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB96Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -606,7 +725,12 @@ BufferLoadB128Mubuf::BufferLoadB128Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB128Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -630,7 +754,12 @@ BufferStoreB8Mubuf::BufferStoreB8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -654,7 +783,12 @@ BufferStoreB16Mubuf::BufferStoreB16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -678,7 +812,12 @@ BufferStoreB32Mubuf::BufferStoreB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -702,7 +841,12 @@ BufferStoreB64Mubuf::BufferStoreB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -726,7 +870,12 @@ BufferStoreB96Mubuf::BufferStoreB96Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB96Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB96Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -750,7 +899,12 @@ BufferStoreB128Mubuf::BufferStoreB128Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB128Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB128Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -774,7 +928,12 @@ BufferLoadD16U8Mubuf::BufferLoadD16U8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16U8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16U8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +963,12 @@ BufferLoadD16I8Mubuf::BufferLoadD16I8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16I8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16I8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +998,12 @@ BufferLoadD16B16Mubuf::BufferLoadD16B16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16B16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16B16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +1033,12 @@ BufferLoadD16HiU8Mubuf::BufferLoadD16HiU8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -894,7 +1068,12 @@ BufferLoadD16HiI8Mubuf::BufferLoadD16HiI8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1103,12 @@ BufferLoadD16HiB16Mubuf::BufferLoadD16HiB16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -954,7 +1138,12 @@ BufferStoreD16HiB8Mubuf::BufferStoreD16HiB8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -978,7 +1167,12 @@ BufferStoreD16HiB16Mubuf::BufferStoreD16HiB16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1002,7 +1196,13 @@ BufferLoadD16HiFormatXMubuf::BufferLoadD16HiFormatXMubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_load_d16_hi_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1032,7 +1232,13 @@ BufferStoreD16HiFormatXMubuf::BufferStoreD16HiFormatXMubuf(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Mubuf::validate_encoding("buffer_store_d16_hi_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1045,7 +1251,12 @@ BufferGl0InvMubuf::BufferGl0InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl0InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl0InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl0_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1058,7 +1269,12 @@ BufferGl1InvMubuf::BufferGl1InvMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferGl1InvMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferGl1InvMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1298,12 @@ BufferLoadLdsU8Mubuf::BufferLoadLdsU8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadLdsU8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadLdsU8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_lds_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1106,7 +1327,12 @@ BufferLoadLdsI8Mubuf::BufferLoadLdsI8Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadLdsI8Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadLdsI8Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_lds_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1130,7 +1356,12 @@ BufferLoadLdsU16Mubuf::BufferLoadLdsU16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadLdsU16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadLdsU16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_lds_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1154,7 +1385,12 @@ BufferLoadLdsI16Mubuf::BufferLoadLdsI16Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadLdsI16Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadLdsI16Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_lds_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1178,7 +1414,12 @@ BufferLoadLdsB32Mubuf::BufferLoadLdsB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadLdsB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadLdsB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_lds_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1202,7 +1443,12 @@ BufferLoadLdsFormatXMubuf::BufferLoadLdsFormatXMubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadLdsFormatXMubuf(const MachineInst *opcode) { +DecodeResult decodeBufferLoadLdsFormatXMubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_load_lds_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1228,7 +1474,12 @@ BufferAtomicSwapB32Mubuf::BufferAtomicSwapB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1255,7 +1506,12 @@ BufferAtomicCmpswapB32Mubuf::BufferAtomicCmpswapB32Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1281,7 +1537,12 @@ BufferAtomicAddU32Mubuf::BufferAtomicAddU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1307,7 +1568,12 @@ BufferAtomicSubU32Mubuf::BufferAtomicSubU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1333,7 +1599,12 @@ BufferAtomicCsubU32Mubuf::BufferAtomicCsubU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCsubU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_csub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1359,7 +1630,12 @@ BufferAtomicMinI32Mubuf::BufferAtomicMinI32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1385,7 +1661,12 @@ BufferAtomicMinU32Mubuf::BufferAtomicMinU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1411,7 +1692,12 @@ BufferAtomicMaxI32Mubuf::BufferAtomicMaxI32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1437,7 +1723,12 @@ BufferAtomicMaxU32Mubuf::BufferAtomicMaxU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1463,7 +1754,12 @@ BufferAtomicAndB32Mubuf::BufferAtomicAndB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1489,7 +1785,12 @@ BufferAtomicOrB32Mubuf::BufferAtomicOrB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1515,7 +1816,12 @@ BufferAtomicXorB32Mubuf::BufferAtomicXorB32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1541,7 +1847,12 @@ BufferAtomicIncU32Mubuf::BufferAtomicIncU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1567,7 +1878,12 @@ BufferAtomicDecU32Mubuf::BufferAtomicDecU32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1593,7 +1909,12 @@ BufferAtomicSwapB64Mubuf::BufferAtomicSwapB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1620,7 +1941,12 @@ BufferAtomicCmpswapB64Mubuf::BufferAtomicCmpswapB64Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1646,7 +1972,12 @@ BufferAtomicAddU64Mubuf::BufferAtomicAddU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1672,7 +2003,12 @@ BufferAtomicSubU64Mubuf::BufferAtomicSubU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1698,7 +2034,12 @@ BufferAtomicMinI64Mubuf::BufferAtomicMinI64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1724,7 +2065,12 @@ BufferAtomicMinU64Mubuf::BufferAtomicMinU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1750,7 +2096,12 @@ BufferAtomicMaxI64Mubuf::BufferAtomicMaxI64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2127,12 @@ BufferAtomicMaxU64Mubuf::BufferAtomicMaxU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1802,7 +2158,12 @@ BufferAtomicAndB64Mubuf::BufferAtomicAndB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1828,7 +2189,12 @@ BufferAtomicOrB64Mubuf::BufferAtomicOrB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1854,7 +2220,12 @@ BufferAtomicXorB64Mubuf::BufferAtomicXorB64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1880,7 +2251,12 @@ BufferAtomicIncU64Mubuf::BufferAtomicIncU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1906,7 +2282,12 @@ BufferAtomicDecU64Mubuf::BufferAtomicDecU64Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU64Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1933,7 +2314,12 @@ BufferAtomicCmpswapF32Mubuf::BufferAtomicCmpswapF32Mubuf(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_cmpswap_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1959,7 +2345,12 @@ BufferAtomicMinF32Mubuf::BufferAtomicMinF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1985,7 +2376,12 @@ BufferAtomicMaxF32Mubuf::BufferAtomicMaxF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2011,7 +2407,12 @@ BufferAtomicAddF32Mubuf::BufferAtomicAddF32Mubuf(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Mubuf(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Mubuf::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp index 1bacc1882bab..7b404b5fc71d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem.cpp index 59ce8520f0a7..fa5bab1ef592 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx11_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -34,7 +33,11 @@ SLoadB32Smem::SLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ SLoadB64Smem::SLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -74,7 +81,11 @@ SLoadB128Smem::SLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -94,7 +105,11 @@ SLoadB256Smem::SLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -114,7 +129,11 @@ SLoadB512Smem::SLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -134,7 +153,12 @@ SBufferLoadB32Smem::SBufferLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -154,7 +178,12 @@ SBufferLoadB64Smem::SBufferLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +203,12 @@ SBufferLoadB128Smem::SBufferLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -194,7 +228,12 @@ SBufferLoadB256Smem::SBufferLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -214,7 +253,12 @@ SBufferLoadB512Smem::SBufferLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -227,7 +271,11 @@ SGl1InvSmem::SGl1InvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGl1InvSmem(const MachineInst *opcode) { +DecodeResult decodeSGl1InvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_gl1_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -240,7 +288,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +311,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -278,7 +334,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1.cpp index df579c71de87..22a2b4bfd304 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +141,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +167,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ SCtzI32B32Sop1::SCtzI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +218,11 @@ SCtzI32B64Sop1::SCtzI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -212,7 +243,11 @@ SClzI32U32Sop1::SClzI32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +269,11 @@ SClzI32U64Sop1::SClzI32U64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -255,7 +294,11 @@ SClsI32Sop1::SClsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -277,7 +320,11 @@ SClsI32I64Sop1::SClsI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +346,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -321,7 +372,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +399,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +426,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +453,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -409,7 +480,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +506,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -454,7 +535,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +563,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +593,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +622,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +652,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -576,7 +681,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +711,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +740,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +769,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -674,7 +797,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +826,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -730,7 +861,12 @@ SAndSaveexecB32Sop1::SAndSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,7 +898,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -794,7 +935,12 @@ SOrSaveexecB32Sop1::SOrSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -827,7 +973,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +1009,12 @@ SXorSaveexecB32Sop1::SXorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1046,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -921,7 +1082,12 @@ SNandSaveexecB32Sop1::SNandSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -953,7 +1119,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -984,7 +1155,12 @@ SNorSaveexecB32Sop1::SNorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1192,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1047,7 +1228,12 @@ SXnorSaveexecB32Sop1::SXnorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1079,7 +1265,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1301,12 @@ SAndNot0SaveexecB32Sop1::SAndNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1338,12 @@ SAndNot0SaveexecB64Sop1::SAndNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1173,7 +1374,12 @@ SOrNot0SaveexecB32Sop1::SOrNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1411,12 @@ SOrNot0SaveexecB64Sop1::SOrNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1236,7 +1447,12 @@ SAndNot1SaveexecB32Sop1::SAndNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1268,7 +1484,12 @@ SAndNot1SaveexecB64Sop1::SAndNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1299,7 +1520,12 @@ SOrNot1SaveexecB32Sop1::SOrNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,7 +1557,12 @@ SOrNot1SaveexecB64Sop1::SOrNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1362,7 +1593,12 @@ SAndNot0WrexecB32Sop1::SAndNot0WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1630,12 @@ SAndNot0WrexecB64Sop1::SAndNot0WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1425,7 +1666,12 @@ SAndNot1WrexecB32Sop1::SAndNot1WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1703,12 @@ SAndNot1WrexecB64Sop1::SAndNot1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1477,7 +1728,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1753,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1521,7 +1782,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1812,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1566,7 +1837,12 @@ SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1860,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1603,7 +1883,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1626,7 +1910,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1932,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1661,7 +1953,12 @@ SSendmsgRtnB32Sop1::SSendmsgRtnB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sendmsg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1678,7 +1975,12 @@ SSendmsgRtnB64Sop1::SSendmsgRtnB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sendmsg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1699,7 +2001,11 @@ SCeilF32Sop1::SCeilF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCeilF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCeilF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1720,7 +2026,11 @@ SFloorF32Sop1::SFloorF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFloorF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFloorF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1741,7 +2051,11 @@ STruncF32Sop1::STruncF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTruncF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSTruncF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1762,7 +2076,11 @@ SRndneF32Sop1::SRndneF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRndneF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSRndneF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1783,7 +2101,11 @@ SCvtF32I32Sop1::SCvtF32I32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32I32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32I32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2126,11 @@ SCvtF32U32Sop1::SCvtF32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1825,7 +2151,11 @@ SCvtI32F32Sop1::SCvtI32F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtI32F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtI32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1846,7 +2176,11 @@ SCvtU32F32Sop1::SCvtU32F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtU32F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtU32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1867,7 +2201,11 @@ SCvtF16F32Sop1::SCvtF16F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF16F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF16F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1895,7 +2233,11 @@ SCvtF32F16Sop1::SCvtF32F16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32F16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32F16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1917,7 +2259,12 @@ SCvtHiF32F16Sop1::SCvtHiF32F16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtHiF32F16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtHiF32F16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_hi_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1939,7 +2286,11 @@ SCeilF16Sop1::SCeilF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCeilF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCeilF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1967,7 +2318,11 @@ SFloorF16Sop1::SFloorF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFloorF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSFloorF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1995,7 +2350,11 @@ STruncF16Sop1::STruncF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTruncF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSTruncF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2023,7 +2382,11 @@ SRndneF16Sop1::SRndneF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRndneF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSRndneF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop2.cpp index 73f53e8e61ab..0e330a6bde67 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddU32Sop2::SAddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubU32Sop2::SSubU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddI32Sop2::SAddI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubI32Sop2::SSubI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,11 @@ SAddcU32Sop2::SAddcU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddcU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddcU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_addc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +212,11 @@ SSubbU32Sop2::SSubbU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubbU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubbU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_subb_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +246,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +281,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +316,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -314,7 +350,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -345,7 +385,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +419,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -406,7 +454,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +488,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +523,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -496,7 +558,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -526,7 +593,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -556,7 +628,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +662,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -616,7 +696,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -646,7 +730,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -676,7 +764,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +800,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,7 +835,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -772,7 +872,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -802,7 +906,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +942,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +976,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -896,7 +1012,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -926,7 +1046,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1082,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -988,7 +1116,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1020,7 +1152,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1186,12 @@ SAndNot1B32Sop2::SAndNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1223,12 @@ SAndNot1B64Sop2::SAndNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1258,11 @@ SOrNot1B32Sop2::SOrNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1294,11 @@ SOrNot1B64Sop2::SOrNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1174,7 +1328,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1204,7 +1362,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1235,7 +1397,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1266,7 +1432,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,7 +1463,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1320,7 +1494,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1347,7 +1525,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1374,7 +1556,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1587,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1431,7 +1621,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1463,7 +1658,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1492,7 +1692,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1725,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1757,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1575,7 +1790,12 @@ SPackHlB32B16Sop2::SPackHlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hl_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1602,7 +1822,11 @@ SAddF32Sop2::SAddF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1629,7 +1853,11 @@ SSubF32Sop2::SSubF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1656,7 +1884,11 @@ SMinF32Sop2::SMinF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1683,7 +1915,11 @@ SMaxF32Sop2::SMaxF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1710,7 +1946,11 @@ SMulF32Sop2::SMulF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1743,7 +1983,11 @@ SFmaakF32Sop2::SFmaakF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmaakF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmaakF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmaak_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2020,11 @@ SFmamkF32Sop2::SFmamkF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmamkF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmamkF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmamk_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2052,11 @@ SFmacF32Sop2::SFmacF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmacF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmacF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1831,7 +2083,12 @@ SCvtPkRtzF16F32Sop2::SCvtPkRtzF16F32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cvt_pk_rtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1866,7 +2123,11 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1901,7 +2162,11 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1936,7 +2201,11 @@ SMinF16Sop2::SMinF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1971,7 +2240,11 @@ SMaxF16Sop2::SMaxF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2279,11 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2042,7 +2319,11 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmacF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmacF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopc.cpp index bb3bc98dd634..2d3916097d52 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +554,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -517,7 +588,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +620,11 @@ SCmpLtF32Sopc::SCmpLtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -575,7 +654,11 @@ SCmpLtF16Sopc::SCmpLtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -603,7 +686,11 @@ SCmpEqF32Sopc::SCmpEqF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -633,7 +720,11 @@ SCmpEqF16Sopc::SCmpEqF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -661,7 +752,11 @@ SCmpLeF32Sopc::SCmpLeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -691,7 +786,11 @@ SCmpLeF16Sopc::SCmpLeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -719,7 +818,11 @@ SCmpGtF32Sopc::SCmpGtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +852,11 @@ SCmpGtF16Sopc::SCmpGtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -777,7 +884,11 @@ SCmpLgF32Sopc::SCmpLgF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -807,7 +918,11 @@ SCmpLgF16Sopc::SCmpLgF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -835,7 +950,11 @@ SCmpGeF32Sopc::SCmpGeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -865,7 +984,11 @@ SCmpGeF16Sopc::SCmpGeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -893,7 +1016,11 @@ SCmpOF32Sopc::SCmpOF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpOF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpOF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1050,11 @@ SCmpOF16Sopc::SCmpOF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpOF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpOF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1082,11 @@ SCmpUF32Sopc::SCmpUF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpUF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpUF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -981,7 +1116,11 @@ SCmpUF16Sopc::SCmpUF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpUF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpUF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1009,7 +1148,11 @@ SCmpNgeF32Sopc::SCmpNgeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1039,7 +1182,11 @@ SCmpNgeF16Sopc::SCmpNgeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1214,11 @@ SCmpNlgF32Sopc::SCmpNlgF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNlgF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNlgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1248,11 @@ SCmpNlgF16Sopc::SCmpNlgF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNlgF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNlgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1125,7 +1280,11 @@ SCmpNgtF32Sopc::SCmpNgtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1314,11 @@ SCmpNgtF16Sopc::SCmpNgtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1183,7 +1346,11 @@ SCmpNleF32Sopc::SCmpNleF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNleF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNleF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1213,7 +1380,11 @@ SCmpNleF16Sopc::SCmpNleF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNleF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNleF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1241,7 +1412,11 @@ SCmpNeqF32Sopc::SCmpNeqF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNeqF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNeqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1446,11 @@ SCmpNeqF16Sopc::SCmpNeqF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNeqF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNeqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1299,7 +1478,11 @@ SCmpNltF32Sopc::SCmpNltF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNltF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNltF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1329,7 +1512,11 @@ SCmpNltF16Sopc::SCmpNltF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNltF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNltF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopk.cpp index 43bd77a773a0..4a978ecc3253 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -39,7 +42,11 @@ SVersionSopk::SVersionSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode) { +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_version", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,7 +68,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,7 +92,11 @@ SCmpkEqI32Sopk::SCmpkEqI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -101,7 +116,11 @@ SCmpkLgI32Sopk::SCmpkLgI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -121,7 +140,11 @@ SCmpkGtI32Sopk::SCmpkGtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +164,11 @@ SCmpkGeI32Sopk::SCmpkGeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -161,7 +188,11 @@ SCmpkLtI32Sopk::SCmpkLtI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -181,7 +212,11 @@ SCmpkLeI32Sopk::SCmpkLeI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -201,7 +236,11 @@ SCmpkEqU32Sopk::SCmpkEqU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkEqU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkEqU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +260,11 @@ SCmpkLgU32Sopk::SCmpkLgU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLgU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLgU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -241,7 +284,11 @@ SCmpkGtU32Sopk::SCmpkGtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +308,11 @@ SCmpkGeU32Sopk::SCmpkGeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkGeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkGeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -281,7 +332,11 @@ SCmpkLtU32Sopk::SCmpkLtU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLtU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLtU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -301,7 +356,11 @@ SCmpkLeU32Sopk::SCmpkLeU32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpkLeU32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmpkLeU32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmpk_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -322,7 +381,11 @@ SAddkI32Sopk::SAddkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -340,7 +403,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +424,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -374,7 +445,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +474,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +508,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +535,12 @@ SWaitcntVscntSopk::SWaitcntVscntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVscntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVscntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +558,12 @@ SWaitcntVmcntSopk::SWaitcntVmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntVmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntVmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_vmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +581,12 @@ SWaitcntExpcntSopk::SWaitcntExpcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntExpcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntExpcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_expcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -505,7 +604,12 @@ SWaitcntLgkmcntSopk::SWaitcntLgkmcntSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntLgkmcntSopk(const MachineInst *opcode) { +DecodeResult decodeSWaitcntLgkmcntSopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_waitcnt_lgkmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopp.cpp index d05f7a8a0118..7cd962cf9f42 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -37,7 +40,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +59,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +78,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,7 +97,13 @@ SSetInstPrefetchDistanceSopp::SSetInstPrefetchDistanceSopp(const MachineInst *in } namespace detail { -std::unique_ptr decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode) { +DecodeResult decodeSSetInstPrefetchDistanceSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Sopp::validate_encoding("s_set_inst_prefetch_distance", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +118,11 @@ SClauseSopp::SClauseSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode) { +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_clause", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -112,7 +137,11 @@ SDelayAluSopp::SDelayAluSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode) { +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_delay_alu", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +158,12 @@ SWaitcntDepctrSopp::SWaitcntDepctrSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntDepctrSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntDepctrSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt_depctr", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -145,7 +179,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +197,11 @@ SWaitIdleSopp::SWaitIdleSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_idle", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +217,11 @@ SWaitEventSopp::SWaitEventSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitEventSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitEventSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_event", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,7 +236,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -205,7 +255,11 @@ SRoundModeSopp::SRoundModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode) { +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_round_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -220,7 +274,12 @@ SDenormModeSopp::SDenormModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode) { +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_denorm_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +292,11 @@ SCodeEndSopp::SCodeEndSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode) { +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_code_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +313,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -275,7 +342,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +372,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +402,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +432,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +462,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +492,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -420,7 +517,12 @@ SCbranchCdbgsysSopp::SCbranchCdbgsysSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -435,7 +537,12 @@ SCbranchCdbguserSopp::SCbranchCdbguserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbguserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbguserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbguser", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -450,7 +557,12 @@ SCbranchCdbgsysOrUserSopp::SCbranchCdbgsysOrUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysOrUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_or_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -465,7 +577,12 @@ SCbranchCdbgsysAndUserSopp::SCbranchCdbgsysAndUserSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchCdbgsysAndUserSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_cdbgsys_and_user", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -479,7 +596,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -493,7 +614,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -507,7 +633,12 @@ SEndpgmOrderedPsDoneSopp::SEndpgmOrderedPsDoneSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmOrderedPsDoneSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_ordered_ps_done", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -520,7 +651,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -535,7 +670,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -553,7 +692,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -571,7 +714,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +734,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +754,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -617,7 +775,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -635,7 +798,12 @@ STtracedataImmSopp::STtracedataImmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata_imm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -648,7 +816,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -662,7 +834,11 @@ SBarrierSopp::SBarrierSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vinterp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vinterp.cpp index 5f89a858b640..fd3d7459a14b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vinterp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vinterp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vinterp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -28,7 +27,12 @@ VInterpP10F32Vinterp::VInterpP10F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p10_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ VInterpP2F32Vinterp::VInterpP2F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -70,7 +79,12 @@ VInterpP10F16F32Vinterp::VInterpP10F16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10F16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p10_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +105,12 @@ VInterpP2F16F32Vinterp::VInterpP2F16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +137,13 @@ VInterpP10RtzF16F32Vinterp::VInterpP10RtzF16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vinterp::validate_encoding("v_interp_p10_rtz_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +164,12 @@ VInterpP2RtzF16F32Vinterp::VInterpP2RtzF16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_rtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop1.cpp index f3cd229093cc..b7bb275224bf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,15 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_dpp" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +71,15 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_dpp" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,13 +96,22 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_dpp" + : "v_readfirstlane_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -109,13 +133,21 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_dpp" + : "v_cvt_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -136,13 +168,21 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_dpp" + : "v_cvt_f64_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -183,7 +223,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_dpp" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +272,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_dpp" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +321,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_dpp" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +370,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_dpp" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -349,7 +421,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_dpp" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +478,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_dpp" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -439,7 +527,16 @@ VCvtNearestI32F32Vop1::VCvtNearestI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_dpp" + : "v_cvt_nearest_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -480,7 +577,16 @@ VCvtFloorI32F32Vop1::VCvtFloorI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_dpp" + : "v_cvt_floor_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +627,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_dpp" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,13 +658,21 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_dpp" + : "v_cvt_f32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -570,13 +693,21 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_dpp" + : "v_cvt_f64_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -617,7 +748,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_dpp" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -658,7 +798,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_dpp" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +848,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_dpp" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -740,7 +898,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_dpp" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,13 +929,21 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_dpp" + : "v_cvt_u32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -789,13 +964,21 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_dpp" + : "v_cvt_f64_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -817,13 +1000,21 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_dpp" + : "v_trunc_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -845,13 +1036,21 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_dpp" + : "v_ceil_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -873,13 +1072,21 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_dpp" + : "v_rndne_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -901,13 +1108,21 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_dpp" + : "v_floor_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1138,15 @@ VPipeflushVop1::VPipeflushVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_dpp" + : "v_pipeflush_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -968,7 +1191,15 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_dpp" + : "v_mov_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1015,7 +1246,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_dpp" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1295,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_dpp" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1344,15 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_dpp" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1393,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_dpp" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1179,7 +1442,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_dpp" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1220,7 +1491,15 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_dpp" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1261,7 +1540,15 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_dpp" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1302,7 +1589,15 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_dpp" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1343,7 +1638,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_dpp" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1384,7 +1688,15 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_dpp" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1406,13 +1718,21 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_dpp" + : "v_rcp_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1434,13 +1754,21 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_dpp" + : "v_rsq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1809,15 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_dpp" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,13 +1839,21 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_dpp" + : "v_sqrt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1550,7 +1894,15 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_dpp" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1591,7 +1943,15 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_dpp" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1632,7 +1992,15 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_dpp" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +2041,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_dpp" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1714,7 +2090,15 @@ VClzI32U32Vop1::VClzI32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_dpp" + : "v_clz_i32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2139,15 @@ VCtzI32B32Vop1::VCtzI32B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_dpp" + : "v_ctz_i32_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1796,7 +2188,15 @@ VClsI32Vop1::VClsI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_dpp" + : "v_cls_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,13 +2218,22 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_dpp" + : "v_frexp_exp_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1846,13 +2255,22 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_dpp" + : "v_frexp_mant_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1874,13 +2292,21 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_dpp" + : "v_fract_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1921,7 +2347,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_dpp" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1962,7 +2397,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_dpp" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2450,16 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_dpp" + : "v_movreld_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2046,7 +2499,16 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_dpp" + : "v_movrels_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2086,7 +2548,16 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_dpp" + : "v_movrelsd_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2126,7 +2597,16 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_dpp" + : "v_movrelsd_2_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2171,7 +2651,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_dpp" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2222,7 +2710,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_dpp" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2273,7 +2769,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_dpp" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2324,7 +2828,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_dpp" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2375,7 +2887,15 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_dpp" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2426,7 +2946,15 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_dpp" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2477,7 +3005,15 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_dpp" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2528,7 +3064,15 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_dpp" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2579,7 +3123,15 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_dpp" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2630,7 +3182,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_dpp" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2681,7 +3242,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_dpp" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2732,7 +3302,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_dpp" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2783,7 +3361,15 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_dpp" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2834,7 +3420,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_dpp" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2885,7 +3479,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_dpp" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2936,7 +3538,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_dpp" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2987,7 +3597,15 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_dpp" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3038,7 +3656,15 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_dpp" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3087,7 +3713,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_dpp" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3138,7 +3773,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_dpp" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3189,7 +3833,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_dpp" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3214,13 +3867,21 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b32_dpp" + : "v_swap_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3242,13 +3903,21 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b16_dpp" + : "v_swap_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3273,13 +3942,22 @@ VPermlane64B32Vop1::VPermlane64B32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE64_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane64B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPermlane64B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane64_b32_dpp" + : "v_permlane64_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE64_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3300,14 +3978,23 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) src_operands_[2] = &m0; num_src_ = 3; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAPREL_B32 does not support DPP", ""); m0.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swaprel_b32_dpp" + : "v_swaprel_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3352,7 +4039,15 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_dpp" + : "v_not_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3401,7 +4096,15 @@ VCvtI32I16Vop1::VCvtI32I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_dpp" + : "v_cvt_i32_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3444,7 +4147,15 @@ VCvtU32U16Vop1::VCvtU32U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_dpp" + : "v_cvt_u32_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop2.cpp index 22107ecf22ba..c36d58dc9447 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -54,7 +53,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_dpp" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -98,7 +106,16 @@ VDot2accF32F16Vop2::VDot2accF32F16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2accF32F16Vop2(const MachineInst *opcode) { +DecodeResult decodeVDot2accF32F16Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2acc_f32_f16_dpp" + : "v_dot2acc_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -141,7 +158,15 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_dpp" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -184,7 +209,15 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_dpp" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -227,7 +260,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_dpp" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -251,13 +292,22 @@ VFmacDx9ZeroF32Vop2::VFmacDx9ZeroF32Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_DX9_ZERO_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_dx9_zero_f32_dpp" + : "v_fmac_dx9_zero_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_DX9_ZERO_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -300,7 +350,16 @@ VMulDx9ZeroF32Vop2::VMulDx9ZeroF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_dpp" + : "v_mul_dx9_zero_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +402,15 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_dpp" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -386,7 +453,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_dpp" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -429,7 +504,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_dpp" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +556,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_dpp" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -515,7 +607,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_dpp" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -558,7 +659,15 @@ VMinF32Vop2::VMinF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f32_dpp" + : "v_min_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +710,15 @@ VMaxF32Vop2::VMaxF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f32_dpp" + : "v_max_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -644,7 +761,15 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_dpp" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +812,15 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_dpp" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -730,7 +863,15 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_dpp" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -773,7 +914,15 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_dpp" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -816,7 +965,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_dpp" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1017,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_dpp" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -902,7 +1069,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_dpp" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -945,7 +1121,15 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_dpp" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -988,7 +1172,15 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_dpp" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1031,7 +1223,15 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_dpp" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1074,7 +1274,15 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_dpp" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1123,7 +1331,16 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_dpp" + : "v_add_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1172,7 +1389,16 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_dpp" + : "v_sub_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1447,16 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_dpp" + : "v_subrev_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1264,7 +1499,15 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_dpp" + : "v_add_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1307,7 +1550,15 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_dpp" + : "v_sub_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1350,7 +1601,16 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_dpp" + : "v_subrev_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1654,15 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_dpp" + : "v_fmac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1422,14 +1690,22 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f32_dpp" + : "v_fmamk_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1457,14 +1733,22 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f32_dpp" + : "v_fmaak_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1507,7 +1791,16 @@ VCvtPkRtzF16F32Vop2::VCvtPkRtzF16F32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_dpp" + : "v_cvt_pk_rtz_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1555,7 +1848,15 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_dpp" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1609,7 +1910,15 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_dpp" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1663,7 +1972,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_dpp" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1717,7 +2034,15 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_dpp" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1772,7 +2097,15 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_dpp" + : "v_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1812,14 +2145,22 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F16 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f16_dpp" + : "v_fmamk_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1858,14 +2199,22 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F16 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f16_dpp" + : "v_fmaak_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1919,7 +2268,15 @@ VMaxF16Vop2::VMaxF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f16_dpp" + : "v_max_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1973,7 +2330,15 @@ VMinF16Vop2::VMinF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f16_dpp" + : "v_min_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2027,7 +2392,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_dpp" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2057,13 +2430,21 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMAC_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fmac_f16_dpp" + : "v_pk_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3.cpp index 197d18f72477..99c927dbd47b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,15 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_e64_dpp" + : "v_nop", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -65,7 +72,15 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_e64_dpp" + : "v_mov_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,13 +97,22 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_e64_dpp" + : "v_readfirstlane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -110,13 +134,21 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_e64_dpp" + : "v_cvt_i32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,13 +169,21 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_e64_dpp" + : "v_cvt_f64_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -184,7 +224,15 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_e64_dpp" + : "v_cvt_f32_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -225,7 +273,15 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_e64_dpp" + : "v_cvt_f32_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +322,15 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_e64_dpp" + : "v_cvt_u32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +371,15 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_e64_dpp" + : "v_cvt_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -348,7 +420,15 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_e64_dpp" + : "v_cvt_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +479,15 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_e64_dpp" + : "v_cvt_f32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -440,7 +528,16 @@ VCvtNearestI32F32Vop3::VCvtNearestI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_e64_dpp" + : "v_cvt_nearest_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +578,16 @@ VCvtFloorI32F32Vop3::VCvtFloorI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_e64_dpp" + : "v_cvt_floor_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -522,7 +628,16 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_e64_dpp" + : "v_cvt_off_f32_i4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -544,13 +659,21 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_e64_dpp" + : "v_cvt_f32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -571,13 +694,21 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_e64_dpp" + : "v_cvt_f64_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -618,7 +749,16 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_e64_dpp" + : "v_cvt_f32_ubyte0", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +799,16 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_e64_dpp" + : "v_cvt_f32_ubyte1", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -700,7 +849,16 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_e64_dpp" + : "v_cvt_f32_ubyte2", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +899,16 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_e64_dpp" + : "v_cvt_f32_ubyte3", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -763,13 +930,21 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_e64_dpp" + : "v_cvt_u32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -790,13 +965,21 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_e64_dpp" + : "v_cvt_f64_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -818,13 +1001,21 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_e64_dpp" + : "v_trunc_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -846,13 +1037,21 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_e64_dpp" + : "v_ceil_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -874,13 +1073,21 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_e64_dpp" + : "v_rndne_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -902,13 +1109,21 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_e64_dpp" + : "v_floor_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1139,15 @@ VPipeflushVop3::VPipeflushVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_e64_dpp" + : "v_pipeflush", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -969,7 +1192,15 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_e64_dpp" + : "v_mov_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1247,15 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_e64_dpp" + : "v_fract_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1296,15 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_e64_dpp" + : "v_trunc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1345,15 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_e64_dpp" + : "v_ceil_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1139,7 +1394,15 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_e64_dpp" + : "v_rndne_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1180,7 +1443,15 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_e64_dpp" + : "v_floor_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1492,15 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_e64_dpp" + : "v_exp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1262,7 +1541,15 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_e64_dpp" + : "v_log_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1303,7 +1590,15 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_e64_dpp" + : "v_rcp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1344,7 +1639,16 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_e64_dpp" + : "v_rcp_iflag_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1385,7 +1689,15 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_e64_dpp" + : "v_rsq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1407,13 +1719,21 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_e64_dpp" + : "v_rcp_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1435,13 +1755,21 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_e64_dpp" + : "v_rsq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1810,15 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_e64_dpp" + : "v_sqrt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,13 +1840,21 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_e64_dpp" + : "v_sqrt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1551,7 +1895,15 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_e64_dpp" + : "v_sin_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1592,7 +1944,15 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_e64_dpp" + : "v_cos_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1633,7 +1993,15 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_e64_dpp" + : "v_not_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1674,7 +2042,15 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_e64_dpp" + : "v_bfrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1715,7 +2091,15 @@ VClzI32U32Vop3::VClzI32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_e64_dpp" + : "v_clz_i32_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1756,7 +2140,15 @@ VCtzI32B32Vop3::VCtzI32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_e64_dpp" + : "v_ctz_i32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2189,15 @@ VClsI32Vop3::VClsI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_e64_dpp" + : "v_cls_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,13 +2219,22 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_e64_dpp" + : "v_frexp_exp_i32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1847,13 +2256,22 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_e64_dpp" + : "v_frexp_mant_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1875,13 +2293,21 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_e64_dpp" + : "v_fract_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1922,7 +2348,16 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_e64_dpp" + : "v_frexp_exp_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1963,7 +2398,16 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_e64_dpp" + : "v_frexp_mant_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2007,7 +2451,16 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_e64_dpp" + : "v_movreld_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2047,7 +2500,16 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_e64_dpp" + : "v_movrels_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2087,7 +2549,16 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_e64_dpp" + : "v_movrelsd_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2127,7 +2598,16 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_e64_dpp" + : "v_movrelsd_2_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2172,7 +2652,15 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_e64_dpp" + : "v_cvt_f16_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2223,7 +2711,15 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_e64_dpp" + : "v_cvt_f16_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2274,7 +2770,15 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_e64_dpp" + : "v_cvt_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2829,15 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_e64_dpp" + : "v_cvt_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2376,7 +2888,15 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_e64_dpp" + : "v_rcp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2427,7 +2947,15 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_e64_dpp" + : "v_sqrt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2478,7 +3006,15 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_e64_dpp" + : "v_rsq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2529,7 +3065,15 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_e64_dpp" + : "v_log_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2580,7 +3124,15 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_e64_dpp" + : "v_exp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2631,7 +3183,16 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_e64_dpp" + : "v_frexp_mant_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2682,7 +3243,16 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_e64_dpp" + : "v_frexp_exp_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2733,7 +3303,15 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_e64_dpp" + : "v_floor_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2784,7 +3362,15 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_e64_dpp" + : "v_ceil_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2835,7 +3421,15 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_e64_dpp" + : "v_trunc_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2886,7 +3480,15 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_e64_dpp" + : "v_rndne_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2937,7 +3539,15 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_e64_dpp" + : "v_fract_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2988,7 +3598,15 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_e64_dpp" + : "v_sin_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3039,7 +3657,15 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_e64_dpp" + : "v_cos_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3086,7 +3712,16 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_e64_dpp" + : "v_sat_pk_u8_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3137,7 +3772,16 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_e64_dpp" + : "v_cvt_norm_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3188,7 +3832,16 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_e64_dpp" + : "v_cvt_norm_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3239,7 +3892,15 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_e64_dpp" + : "v_not_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3290,7 +3951,15 @@ VCvtI32I16Vop3::VCvtI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_e64_dpp" + : "v_cvt_i32_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3335,7 +4004,15 @@ VCvtU32U16Vop3::VCvtU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_e64_dpp" + : "v_cvt_u32_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3384,7 +4061,16 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_e64_dpp" + : "v_cndmask_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3431,7 +4117,15 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_e64_dpp" + : "v_add_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3478,7 +4172,15 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_e64_dpp" + : "v_sub_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3525,7 +4227,15 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_e64_dpp" + : "v_subrev_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3553,13 +4263,22 @@ VFmacDx9ZeroF32Vop3::VFmacDx9ZeroF32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAC_DX9_ZERO_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_dx9_zero_f32_e64_dpp" + : "v_fmac_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAC_DX9_ZERO_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3606,7 +4325,16 @@ VMulDx9ZeroF32Vop3::VMulDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_e64_dpp" + : "v_mul_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3653,7 +4381,15 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_e64_dpp" + : "v_mul_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3700,7 +4436,15 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_e64_dpp" + : "v_mul_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3747,7 +4491,16 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_e64_dpp" + : "v_mul_hi_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3794,7 +4547,15 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_e64_dpp" + : "v_mul_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3841,7 +4602,16 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_e64_dpp" + : "v_mul_hi_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3888,7 +4658,15 @@ VMinF32Vop3::VMinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f32_e64_dpp" + : "v_min_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3935,7 +4713,15 @@ VMaxF32Vop3::VMaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f32_e64_dpp" + : "v_max_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3982,7 +4768,15 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_e64_dpp" + : "v_min_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4029,7 +4823,15 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_e64_dpp" + : "v_max_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4076,7 +4878,15 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_e64_dpp" + : "v_min_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4123,7 +4933,15 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_e64_dpp" + : "v_max_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4170,7 +4988,16 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_e64_dpp" + : "v_lshlrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4217,7 +5044,16 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_e64_dpp" + : "v_lshrrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4264,7 +5100,16 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_e64_dpp" + : "v_ashrrev_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4311,7 +5156,15 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_e64_dpp" + : "v_and_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4358,7 +5211,15 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_e64_dpp" + : "v_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4405,7 +5266,15 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_e64_dpp" + : "v_xor_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4452,7 +5321,15 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_e64_dpp" + : "v_xnor_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4499,7 +5376,15 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_e64_dpp" + : "v_add_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4546,7 +5431,15 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_e64_dpp" + : "v_sub_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4593,7 +5486,16 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_e64_dpp" + : "v_subrev_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4641,7 +5543,15 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_e64_dpp" + : "v_fmac_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4688,7 +5598,16 @@ VCvtPkRtzF16F32Vop3::VCvtPkRtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_e64_dpp" + : "v_cvt_pk_rtz_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4743,7 +5662,15 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_e64_dpp" + : "v_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4804,7 +5731,15 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_e64_dpp" + : "v_sub_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4865,7 +5800,15 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_e64_dpp" + : "v_subrev_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4926,7 +5869,15 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_e64_dpp" + : "v_mul_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4988,7 +5939,15 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_e64_dpp" + : "v_fmac_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5049,7 +6008,15 @@ VMaxF16Vop3::VMaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f16_e64_dpp" + : "v_max_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5110,7 +6077,15 @@ VMinF16Vop3::VMinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f16_e64_dpp" + : "v_min_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5171,7 +6146,15 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_e64_dpp" + : "v_ldexp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5230,7 +6213,16 @@ VFmaDx9ZeroF32Vop3::VFmaDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_dx9_zero_f32_e64_dpp" + : "v_fma_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5283,7 +6275,15 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i24_e64_dpp" + : "v_mad_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5336,7 +6336,15 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u24_e64_dpp" + : "v_mad_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5389,7 +6397,15 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubeid_f32_e64_dpp" + : "v_cubeid_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5442,7 +6458,15 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubesc_f32_e64_dpp" + : "v_cubesc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5495,7 +6519,15 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubetc_f32_e64_dpp" + : "v_cubetc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5548,7 +6580,15 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubema_f32_e64_dpp" + : "v_cubema_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5601,7 +6641,15 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_u32_e64_dpp" + : "v_bfe_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5654,7 +6702,15 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_i32_e64_dpp" + : "v_bfe_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5707,7 +6763,15 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfi_b32_e64_dpp" + : "v_bfi_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5760,7 +6824,15 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f32_e64_dpp" + : "v_fma_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5796,13 +6868,21 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMA_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f64_e64_dpp" + : "v_fma_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMA_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5855,7 +6935,15 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lerp_u8_e64_dpp" + : "v_lerp_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5912,7 +7000,16 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbit_b32_e64_dpp" + : "v_alignbit_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5969,7 +7066,16 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbyte_b32_e64_dpp" + : "v_alignbyte_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6022,7 +7128,15 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mullit_f32_e64_dpp" + : "v_mullit_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6075,7 +7189,15 @@ VMin3F32Vop3::VMin3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_f32_e64_dpp" + : "v_min3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6128,7 +7250,15 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i32_e64_dpp" + : "v_min3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6181,7 +7311,15 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u32_e64_dpp" + : "v_min3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6234,7 +7372,15 @@ VMax3F32Vop3::VMax3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_f32_e64_dpp" + : "v_max3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6287,7 +7433,15 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i32_e64_dpp" + : "v_max3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6340,7 +7494,15 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u32_e64_dpp" + : "v_max3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6393,7 +7555,15 @@ VMed3F32Vop3::VMed3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_f32_e64_dpp" + : "v_med3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6446,7 +7616,15 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i32_e64_dpp" + : "v_med3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6499,7 +7677,15 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u32_e64_dpp" + : "v_med3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6552,7 +7738,15 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u8_e64_dpp" + : "v_sad_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6605,7 +7799,15 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_hi_u8_e64_dpp" + : "v_sad_hi_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6658,7 +7860,15 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u16_e64_dpp" + : "v_sad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6711,7 +7921,15 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u32_e64_dpp" + : "v_sad_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6764,7 +7982,16 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u8_f32_e64_dpp" + : "v_cvt_pk_u8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6797,13 +8024,22 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f32_e64_dpp" + : "v_div_fixup_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6839,13 +8075,22 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f64_e64_dpp" + : "v_div_fixup_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6880,14 +8125,23 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F32 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f32_e64_dpp" + : "v_div_fmas_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6925,14 +8179,23 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f64_e64_dpp" + : "v_div_fmas_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6985,7 +8248,15 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_msad_u8_e64_dpp" + : "v_msad_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7020,13 +8291,22 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_QSAD_PK_U16_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_qsad_pk_u16_u8_e64_dpp" + : "v_qsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_QSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7061,13 +8341,22 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_PK_U16_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_pk_u16_u8_e64_dpp" + : "v_mqsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7097,13 +8386,22 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_U32_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_u32_u8_e64_dpp" + : "v_mqsad_u32_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7156,7 +8454,15 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor3_b32_e64_dpp" + : "v_xor3_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7221,7 +8527,15 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u16_e64_dpp" + : "v_mad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7280,7 +8594,15 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_b32_e64_dpp" + : "v_perm_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7333,7 +8655,15 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xad_u32_e64_dpp" + : "v_xad_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7386,7 +8716,16 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_add_u32_e64_dpp" + : "v_lshl_add_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7439,7 +8778,16 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_lshl_u32_e64_dpp" + : "v_add_lshl_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7504,7 +8852,15 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f16_e64_dpp" + : "v_fma_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7575,7 +8931,15 @@ VMin3F16Vop3::VMin3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_f16_e64_dpp" + : "v_min3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7646,7 +9010,15 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i16_e64_dpp" + : "v_min3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7717,7 +9089,15 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u16_e64_dpp" + : "v_min3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7788,7 +9168,15 @@ VMax3F16Vop3::VMax3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_f16_e64_dpp" + : "v_max3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7859,7 +9247,15 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i16_e64_dpp" + : "v_max3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7930,7 +9326,15 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u16_e64_dpp" + : "v_max3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8001,7 +9405,15 @@ VMed3F16Vop3::VMed3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_f16_e64_dpp" + : "v_med3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8072,7 +9484,15 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i16_e64_dpp" + : "v_med3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8143,7 +9563,15 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u16_e64_dpp" + : "v_med3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8214,7 +9642,15 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i16_e64_dpp" + : "v_mad_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8285,7 +9721,16 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f16_e64_dpp" + : "v_div_fixup_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8344,7 +9789,15 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add3_u32_e64_dpp" + : "v_add3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8397,7 +9850,15 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_or_b32_e64_dpp" + : "v_lshl_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8450,7 +9911,15 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_or_b32_e64_dpp" + : "v_and_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8503,7 +9972,15 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or3_b32_e64_dpp" + : "v_or3_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8564,7 +10041,15 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u16_e64_dpp" + : "v_mad_u32_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8625,7 +10110,15 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i16_e64_dpp" + : "v_mad_i32_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8654,13 +10147,22 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_b32_e64_dpp" + : "v_permlane16_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8689,13 +10191,22 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANEX16_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlanex16_b32_e64_dpp" + : "v_permlanex16_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANEX16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -8752,7 +10263,16 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b16_e64_dpp" + : "v_cndmask_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8811,7 +10331,15 @@ VMaxminF32Vop3::VMaxminF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_f32_e64_dpp" + : "v_maxmin_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8864,7 +10392,15 @@ VMinmaxF32Vop3::VMinmaxF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_f32_e64_dpp" + : "v_minmax_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8929,7 +10465,15 @@ VMaxminF16Vop3::VMaxminF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_f16_e64_dpp" + : "v_maxmin_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9000,7 +10544,15 @@ VMinmaxF16Vop3::VMinmaxF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_f16_e64_dpp" + : "v_minmax_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9059,7 +10611,15 @@ VMaxminU32Vop3::VMaxminU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_u32_e64_dpp" + : "v_maxmin_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9112,7 +10672,15 @@ VMinmaxU32Vop3::VMinmaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_u32_e64_dpp" + : "v_minmax_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9165,7 +10733,15 @@ VMaxminI32Vop3::VMaxminI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_i32_e64_dpp" + : "v_maxmin_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9218,7 +10794,15 @@ VMinmaxI32Vop3::VMinmaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_i32_e64_dpp" + : "v_minmax_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9275,7 +10859,16 @@ VDot2F16F16Vop3::VDot2F16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2F16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f16_f16_e64_dpp" + : "v_dot2_f16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9338,7 +10931,16 @@ VDot2Bf16Bf16Vop3::VDot2Bf16Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_bf16_bf16_e64_dpp" + : "v_dot2_bf16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9399,7 +11001,15 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u16_e64_dpp" + : "v_add_nc_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9460,7 +11070,15 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u16_e64_dpp" + : "v_sub_nc_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9521,7 +11139,15 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u16_e64_dpp" + : "v_mul_lo_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9574,7 +11200,16 @@ VCvtPkI16F32Vop3::VCvtPkI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_f32_e64_dpp" + : "v_cvt_pk_i16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9621,7 +11256,16 @@ VCvtPkU16F32Vop3::VCvtPkU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_f32_e64_dpp" + : "v_cvt_pk_u16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9676,7 +11320,15 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u16_e64_dpp" + : "v_max_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9737,7 +11389,15 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i16_e64_dpp" + : "v_max_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9798,7 +11458,15 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u16_e64_dpp" + : "v_min_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9859,7 +11527,15 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i16_e64_dpp" + : "v_min_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9920,7 +11596,15 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i16_e64_dpp" + : "v_add_nc_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9981,7 +11665,15 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i16_e64_dpp" + : "v_sub_nc_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10042,7 +11734,16 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pack_b32_f16_e64_dpp" + : "v_pack_b32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10097,7 +11798,16 @@ VCvtPkNormI16F16Vop3::VCvtPkNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f16_e64_dpp" + : "v_cvt_pk_norm_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10152,7 +11862,16 @@ VCvtPkNormU16F16Vop3::VCvtPkNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f16_e64_dpp" + : "v_cvt_pk_norm_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10199,7 +11918,15 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f32_e64_dpp" + : "v_ldexp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10246,7 +11973,15 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfm_b32_e64_dpp" + : "v_bfm_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10293,7 +12028,16 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bcnt_u32_b32_e64_dpp" + : "v_bcnt_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10340,7 +12084,16 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_lo_u32_b32_e64_dpp" + : "v_mbcnt_lo_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10387,7 +12140,16 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_hi_u32_b32_e64_dpp" + : "v_mbcnt_hi_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10434,7 +12196,16 @@ VCvtPkNormI16F32Vop3::VCvtPkNormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f32_e64_dpp" + : "v_cvt_pk_norm_i16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10481,7 +12252,16 @@ VCvtPkNormU16F32Vop3::VCvtPkNormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f32_e64_dpp" + : "v_cvt_pk_norm_u16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10528,7 +12308,16 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_u32_e64_dpp" + : "v_cvt_pk_u16_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10575,7 +12364,16 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_i32_e64_dpp" + : "v_cvt_pk_i16_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10622,7 +12420,15 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i32_e64_dpp" + : "v_sub_nc_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10669,7 +12475,15 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i32_e64_dpp" + : "v_add_nc_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10698,13 +12512,21 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f64_e64_dpp" + : "v_add_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10733,13 +12555,21 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f64_e64_dpp" + : "v_mul_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10768,13 +12598,21 @@ VMinF64Vop3::VMinF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMinF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_f64_e64_dpp" + : "v_min_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10803,13 +12641,21 @@ VMaxF64Vop3::VMaxF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMaxF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_f64_e64_dpp" + : "v_max_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10837,13 +12683,21 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LDEXP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f64_e64_dpp" + : "v_ldexp_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LDEXP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10870,13 +12724,21 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_LO_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u32_e64_dpp" + : "v_mul_lo_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_LO_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10903,13 +12765,21 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_e64_dpp" + : "v_mul_hi_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10936,13 +12806,21 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_e64_dpp" + : "v_mul_hi_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10970,13 +12848,22 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRIG_PREOP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trig_preop_f64_e64_dpp" + : "v_trig_preop_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRIG_PREOP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11031,7 +12918,16 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b16_e64_dpp" + : "v_lshlrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11092,7 +12988,16 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b16_e64_dpp" + : "v_lshrrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11153,7 +13058,16 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i16_e64_dpp" + : "v_ashrrev_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11187,13 +13101,22 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHLREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b64_e64_dpp" + : "v_lshlrev_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHLREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11221,13 +13144,22 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHRREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b64_e64_dpp" + : "v_lshrrev_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHRREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11255,13 +13187,22 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ASHRREV_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i64_e64_dpp" + : "v_ashrrev_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ASHRREV_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11280,13 +13221,22 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readlane_b32_e64_dpp" + : "v_readlane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11310,13 +13260,22 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WRITELANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_writelane_b32_e64_dpp" + : "v_writelane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_WRITELANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11371,7 +13330,15 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b16_e64_dpp" + : "v_and_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11432,7 +13399,15 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b16_e64_dpp" + : "v_or_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11493,7 +13468,15 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b16_e64_dpp" + : "v_xor_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11554,7 +13537,15 @@ VCmpFF16Vop3::VCmpFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f16_e64_dpp" + : "v_cmp_f_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11609,7 +13600,15 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_e64_dpp" + : "v_cmp_lt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11664,7 +13663,15 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_e64_dpp" + : "v_cmp_eq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11719,7 +13726,15 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_e64_dpp" + : "v_cmp_le_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11774,7 +13789,15 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_e64_dpp" + : "v_cmp_gt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11829,7 +13852,15 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_e64_dpp" + : "v_cmp_lg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11884,7 +13915,15 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_e64_dpp" + : "v_cmp_ge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11939,7 +13978,15 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_e64_dpp" + : "v_cmp_o_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11994,7 +14041,15 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_e64_dpp" + : "v_cmp_u_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12049,7 +14104,15 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_e64_dpp" + : "v_cmp_nge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12104,7 +14167,15 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_e64_dpp" + : "v_cmp_nlg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12159,7 +14230,15 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_e64_dpp" + : "v_cmp_ngt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12214,7 +14293,15 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_e64_dpp" + : "v_cmp_nle_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12269,7 +14356,15 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_e64_dpp" + : "v_cmp_neq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12324,7 +14419,15 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_e64_dpp" + : "v_cmp_nlt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12379,7 +14482,15 @@ VCmpTF16Vop3::VCmpTF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f16_e64_dpp" + : "v_cmp_t_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12426,7 +14537,15 @@ VCmpFF32Vop3::VCmpFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f32_e64_dpp" + : "v_cmp_f_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12473,7 +14592,15 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_e64_dpp" + : "v_cmp_lt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12520,7 +14647,15 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_e64_dpp" + : "v_cmp_eq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12567,7 +14702,15 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_e64_dpp" + : "v_cmp_le_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12614,7 +14757,15 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_e64_dpp" + : "v_cmp_gt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12661,7 +14812,15 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_e64_dpp" + : "v_cmp_lg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12708,7 +14867,15 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_e64_dpp" + : "v_cmp_ge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12755,7 +14922,15 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_e64_dpp" + : "v_cmp_o_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12802,7 +14977,15 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_e64_dpp" + : "v_cmp_u_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12849,7 +15032,15 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_e64_dpp" + : "v_cmp_nge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12896,7 +15087,15 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_e64_dpp" + : "v_cmp_nlg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12943,7 +15142,15 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_e64_dpp" + : "v_cmp_ngt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12990,7 +15197,15 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_e64_dpp" + : "v_cmp_nle_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13037,7 +15252,15 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_e64_dpp" + : "v_cmp_neq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13084,7 +15307,15 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_e64_dpp" + : "v_cmp_nlt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13131,7 +15362,15 @@ VCmpTF32Vop3::VCmpTF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f32_e64_dpp" + : "v_cmp_t_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13160,13 +15399,21 @@ VCmpFF64Vop3::VCmpFF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f64_e64_dpp" + : "v_cmp_f_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13195,13 +15442,21 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_e64_dpp" + : "v_cmp_lt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13230,13 +15485,21 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_e64_dpp" + : "v_cmp_eq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13265,13 +15528,21 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_e64_dpp" + : "v_cmp_le_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13300,13 +15571,21 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_e64_dpp" + : "v_cmp_gt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13335,13 +15614,21 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_e64_dpp" + : "v_cmp_lg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13370,13 +15657,21 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_e64_dpp" + : "v_cmp_ge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13405,13 +15700,21 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_e64_dpp" + : "v_cmp_o_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13440,13 +15743,21 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_e64_dpp" + : "v_cmp_u_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13475,13 +15786,21 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_e64_dpp" + : "v_cmp_nge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13510,13 +15829,21 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_e64_dpp" + : "v_cmp_nlg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13545,13 +15872,21 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_e64_dpp" + : "v_cmp_ngt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13580,13 +15915,21 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_e64_dpp" + : "v_cmp_nle_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13615,13 +15958,21 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_e64_dpp" + : "v_cmp_neq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13650,13 +16001,21 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_e64_dpp" + : "v_cmp_nlt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13685,13 +16044,21 @@ VCmpTF64Vop3::VCmpTF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpTF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f64_e64_dpp" + : "v_cmp_t_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -13746,7 +16113,15 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_e64_dpp" + : "v_cmp_lt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13801,7 +16176,15 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_e64_dpp" + : "v_cmp_eq_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13856,7 +16239,15 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_e64_dpp" + : "v_cmp_le_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13911,7 +16302,15 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_e64_dpp" + : "v_cmp_gt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13966,7 +16365,15 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_e64_dpp" + : "v_cmp_ne_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14021,7 +16428,15 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_e64_dpp" + : "v_cmp_ge_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14076,7 +16491,15 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_e64_dpp" + : "v_cmp_lt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14131,7 +16554,15 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_e64_dpp" + : "v_cmp_eq_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14186,7 +16617,15 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_e64_dpp" + : "v_cmp_le_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14241,7 +16680,15 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_e64_dpp" + : "v_cmp_gt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14296,7 +16743,15 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_e64_dpp" + : "v_cmp_ne_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14351,7 +16806,15 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_e64_dpp" + : "v_cmp_ge_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14398,7 +16861,15 @@ VCmpFI32Vop3::VCmpFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i32_e64_dpp" + : "v_cmp_f_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14445,7 +16916,15 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_e64_dpp" + : "v_cmp_lt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14492,7 +16971,15 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_e64_dpp" + : "v_cmp_eq_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14539,7 +17026,15 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_e64_dpp" + : "v_cmp_le_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14586,7 +17081,15 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_e64_dpp" + : "v_cmp_gt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14633,7 +17136,15 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_e64_dpp" + : "v_cmp_ne_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14680,7 +17191,15 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_e64_dpp" + : "v_cmp_ge_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14727,7 +17246,15 @@ VCmpTI32Vop3::VCmpTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i32_e64_dpp" + : "v_cmp_t_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14774,7 +17301,15 @@ VCmpFU32Vop3::VCmpFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u32_e64_dpp" + : "v_cmp_f_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14821,7 +17356,15 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_e64_dpp" + : "v_cmp_lt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14868,7 +17411,15 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_e64_dpp" + : "v_cmp_eq_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14915,7 +17466,15 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_e64_dpp" + : "v_cmp_le_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14962,7 +17521,15 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_e64_dpp" + : "v_cmp_gt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15009,7 +17576,15 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_e64_dpp" + : "v_cmp_ne_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15056,7 +17631,15 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_e64_dpp" + : "v_cmp_ge_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15103,7 +17686,15 @@ VCmpTU32Vop3::VCmpTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u32_e64_dpp" + : "v_cmp_t_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15132,13 +17723,21 @@ VCmpFI64Vop3::VCmpFI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i64_e64_dpp" + : "v_cmp_f_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15167,13 +17766,21 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_e64_dpp" + : "v_cmp_lt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15202,13 +17809,21 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_e64_dpp" + : "v_cmp_eq_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15237,13 +17852,21 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_e64_dpp" + : "v_cmp_le_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15272,13 +17895,21 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_e64_dpp" + : "v_cmp_gt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15307,13 +17938,21 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_e64_dpp" + : "v_cmp_ne_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15342,13 +17981,21 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_e64_dpp" + : "v_cmp_ge_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15377,13 +18024,21 @@ VCmpTI64Vop3::VCmpTI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i64_e64_dpp" + : "v_cmp_t_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15412,13 +18067,21 @@ VCmpFU64Vop3::VCmpFU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u64_e64_dpp" + : "v_cmp_f_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15447,13 +18110,21 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_e64_dpp" + : "v_cmp_lt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15482,13 +18153,21 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_e64_dpp" + : "v_cmp_eq_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15517,13 +18196,21 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_e64_dpp" + : "v_cmp_le_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15552,13 +18239,21 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_e64_dpp" + : "v_cmp_gt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15587,13 +18282,21 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_e64_dpp" + : "v_cmp_ne_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15622,13 +18325,21 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_e64_dpp" + : "v_cmp_ge_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15657,13 +18368,21 @@ VCmpTU64Vop3::VCmpTU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u64_e64_dpp" + : "v_cmp_t_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15718,7 +18437,16 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_e64_dpp" + : "v_cmp_class_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15765,7 +18493,16 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_e64_dpp" + : "v_cmp_class_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15793,13 +18530,22 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_e64_dpp" + : "v_cmp_class_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -15858,7 +18604,15 @@ VCmpxFF16Vop3::VCmpxFF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f16_e64_dpp" + : "v_cmpx_f_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15917,7 +18671,15 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_e64_dpp" + : "v_cmpx_lt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15976,7 +18738,15 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_e64_dpp" + : "v_cmpx_eq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16035,7 +18805,15 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_e64_dpp" + : "v_cmpx_le_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16094,7 +18872,15 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_e64_dpp" + : "v_cmpx_gt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16153,7 +18939,15 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_e64_dpp" + : "v_cmpx_lg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16212,7 +19006,15 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_e64_dpp" + : "v_cmpx_ge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16271,7 +19073,15 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_e64_dpp" + : "v_cmpx_o_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16330,7 +19140,15 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_e64_dpp" + : "v_cmpx_u_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16389,7 +19207,16 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_e64_dpp" + : "v_cmpx_nge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16448,7 +19275,16 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_e64_dpp" + : "v_cmpx_nlg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16507,7 +19343,16 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_e64_dpp" + : "v_cmpx_ngt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16566,7 +19411,16 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_e64_dpp" + : "v_cmpx_nle_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16625,7 +19479,16 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_e64_dpp" + : "v_cmpx_neq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16684,7 +19547,16 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_e64_dpp" + : "v_cmpx_nlt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16743,7 +19615,15 @@ VCmpxTF16Vop3::VCmpxTF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f16_e64_dpp" + : "v_cmpx_t_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16794,7 +19674,15 @@ VCmpxFF32Vop3::VCmpxFF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f32_e64_dpp" + : "v_cmpx_f_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16845,7 +19733,15 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_e64_dpp" + : "v_cmpx_lt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16896,7 +19792,15 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_e64_dpp" + : "v_cmpx_eq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16947,7 +19851,15 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_e64_dpp" + : "v_cmpx_le_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16998,7 +19910,15 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_e64_dpp" + : "v_cmpx_gt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17049,7 +19969,15 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_e64_dpp" + : "v_cmpx_lg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17100,7 +20028,15 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_e64_dpp" + : "v_cmpx_ge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17151,7 +20087,15 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_e64_dpp" + : "v_cmpx_o_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17202,7 +20146,15 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_e64_dpp" + : "v_cmpx_u_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17253,7 +20205,16 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_e64_dpp" + : "v_cmpx_nge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17304,7 +20265,16 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_e64_dpp" + : "v_cmpx_nlg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17355,7 +20325,16 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_e64_dpp" + : "v_cmpx_ngt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17406,7 +20385,16 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_e64_dpp" + : "v_cmpx_nle_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17457,7 +20445,16 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_e64_dpp" + : "v_cmpx_neq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17508,7 +20505,16 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_e64_dpp" + : "v_cmpx_nlt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17559,7 +20565,15 @@ VCmpxTF32Vop3::VCmpxTF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f32_e64_dpp" + : "v_cmpx_t_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17590,15 +20604,23 @@ VCmpxFF64Vop3::VCmpxFF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f64_e64_dpp" + : "v_cmpx_f_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17629,15 +20651,23 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_e64_dpp" + : "v_cmpx_lt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17668,15 +20698,23 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_e64_dpp" + : "v_cmpx_eq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17707,15 +20745,23 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_e64_dpp" + : "v_cmpx_le_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17746,15 +20792,23 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_e64_dpp" + : "v_cmpx_gt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17785,15 +20839,23 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_e64_dpp" + : "v_cmpx_lg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17824,15 +20886,23 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_e64_dpp" + : "v_cmpx_ge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17863,15 +20933,23 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_e64_dpp" + : "v_cmpx_o_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17902,15 +20980,23 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_e64_dpp" + : "v_cmpx_u_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17941,15 +21027,24 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_e64_dpp" + : "v_cmpx_nge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -17980,15 +21075,24 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_e64_dpp" + : "v_cmpx_nlg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18019,15 +21123,24 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_e64_dpp" + : "v_cmpx_ngt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18058,15 +21171,24 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_e64_dpp" + : "v_cmpx_nle_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18097,15 +21219,24 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_e64_dpp" + : "v_cmpx_neq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18136,15 +21267,24 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_e64_dpp" + : "v_cmpx_nlt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18175,15 +21315,23 @@ VCmpxTF64Vop3::VCmpxTF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f64_e64_dpp" + : "v_cmpx_t_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18242,7 +21390,15 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_e64_dpp" + : "v_cmpx_lt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18301,7 +21457,15 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_e64_dpp" + : "v_cmpx_eq_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18360,7 +21524,15 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_e64_dpp" + : "v_cmpx_le_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18419,7 +21591,15 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_e64_dpp" + : "v_cmpx_gt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18478,7 +21658,15 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_e64_dpp" + : "v_cmpx_ne_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18537,7 +21725,15 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_e64_dpp" + : "v_cmpx_ge_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18596,7 +21792,15 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_e64_dpp" + : "v_cmpx_lt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18655,7 +21859,15 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_e64_dpp" + : "v_cmpx_eq_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18714,7 +21926,15 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_e64_dpp" + : "v_cmpx_le_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18773,7 +21993,15 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_e64_dpp" + : "v_cmpx_gt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18832,7 +22060,15 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_e64_dpp" + : "v_cmpx_ne_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18891,7 +22127,15 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_e64_dpp" + : "v_cmpx_ge_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18942,7 +22186,15 @@ VCmpxFI32Vop3::VCmpxFI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i32_e64_dpp" + : "v_cmpx_f_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18993,7 +22245,15 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_e64_dpp" + : "v_cmpx_lt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19044,7 +22304,15 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_e64_dpp" + : "v_cmpx_eq_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19095,7 +22363,15 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_e64_dpp" + : "v_cmpx_le_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19146,7 +22422,15 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_e64_dpp" + : "v_cmpx_gt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19197,7 +22481,15 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_e64_dpp" + : "v_cmpx_ne_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19248,7 +22540,15 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_e64_dpp" + : "v_cmpx_ge_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19299,7 +22599,15 @@ VCmpxTI32Vop3::VCmpxTI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i32_e64_dpp" + : "v_cmpx_t_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19350,7 +22658,15 @@ VCmpxFU32Vop3::VCmpxFU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u32_e64_dpp" + : "v_cmpx_f_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19401,7 +22717,15 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_e64_dpp" + : "v_cmpx_lt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19452,7 +22776,15 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_e64_dpp" + : "v_cmpx_eq_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19503,7 +22835,15 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_e64_dpp" + : "v_cmpx_le_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19554,7 +22894,15 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_e64_dpp" + : "v_cmpx_gt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19605,7 +22953,15 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_e64_dpp" + : "v_cmpx_ne_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19656,7 +23012,15 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_e64_dpp" + : "v_cmpx_ge_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19707,7 +23071,15 @@ VCmpxTU32Vop3::VCmpxTU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u32_e64_dpp" + : "v_cmpx_t_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19738,15 +23110,23 @@ VCmpxFI64Vop3::VCmpxFI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i64_e64_dpp" + : "v_cmpx_f_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19777,15 +23157,23 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_e64_dpp" + : "v_cmpx_lt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19816,15 +23204,23 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_e64_dpp" + : "v_cmpx_eq_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19855,15 +23251,23 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_e64_dpp" + : "v_cmpx_le_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19894,15 +23298,23 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_e64_dpp" + : "v_cmpx_gt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19933,15 +23345,23 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_e64_dpp" + : "v_cmpx_ne_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -19972,15 +23392,23 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_e64_dpp" + : "v_cmpx_ge_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20011,15 +23439,23 @@ VCmpxTI64Vop3::VCmpxTI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i64_e64_dpp" + : "v_cmpx_t_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20050,15 +23486,23 @@ VCmpxFU64Vop3::VCmpxFU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u64_e64_dpp" + : "v_cmpx_f_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20089,15 +23533,23 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_e64_dpp" + : "v_cmpx_lt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20128,15 +23580,23 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_e64_dpp" + : "v_cmpx_eq_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20167,15 +23627,23 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_e64_dpp" + : "v_cmpx_le_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20206,15 +23674,23 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_e64_dpp" + : "v_cmpx_gt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20245,15 +23721,23 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_e64_dpp" + : "v_cmpx_ne_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20284,15 +23768,23 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_e64_dpp" + : "v_cmpx_ge_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20323,15 +23815,23 @@ VCmpxTU64Vop3::VCmpxTU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u64_e64_dpp" + : "v_cmpx_t_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20390,7 +23890,16 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_e64_dpp" + : "v_cmpx_class_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20441,7 +23950,16 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_e64_dpp" + : "v_cmpx_class_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20471,15 +23989,24 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_e64_dpp" + : "v_cmpx_class_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20530,7 +24057,16 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_e64_dpp" + : "v_add_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20581,7 +24117,16 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_e64_dpp" + : "v_sub_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20632,7 +24177,16 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_e64_dpp" + : "v_subrev_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20667,13 +24221,23 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) src2 = Operand(32, OperandType::OPR_SIMM32, static_cast( reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f32_e64_dpp" + : "v_div_scale_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20714,13 +24278,23 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f64_e64_dpp" + : "v_div_scale_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20757,13 +24331,23 @@ VMadU64U32Vop3SdstEnc::VMadU64U32Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_U64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u64_u32_e64_dpp" + : "v_mad_u64_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_U64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20800,13 +24384,23 @@ VMadI64I32Vop3SdstEnc::VMadI64I32Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_I64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i64_i32_e64_dpp" + : "v_mad_i64_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_I64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20855,7 +24449,16 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_u32_e64_dpp" + : "v_add_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20904,7 +24507,16 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_u32_e64_dpp" + : "v_sub_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20953,7 +24565,16 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_u32_e64_dpp" + : "v_subrev_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3p.cpp index 36c4e5bdecbe..491622a0a632 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,13 +40,22 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_i16_e64_dpp" + : "v_pk_mad_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -74,13 +82,23 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_LO_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_lo_u16_e64_dpp" + : "v_pk_mul_lo_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_LO_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -107,13 +125,22 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_i16_e64_dpp" + : "v_pk_add_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -140,13 +167,22 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_i16_e64_dpp" + : "v_pk_sub_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -173,13 +209,23 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHLREV_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshlrev_b16_e64_dpp" + : "v_pk_lshlrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHLREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -206,13 +252,23 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHRREV_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshrrev_b16_e64_dpp" + : "v_pk_lshrrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHRREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -239,13 +295,23 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ASHRREV_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_ashrrev_i16_e64_dpp" + : "v_pk_ashrrev_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ASHRREV_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -272,13 +338,22 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_i16_e64_dpp" + : "v_pk_max_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -305,13 +380,22 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_i16_e64_dpp" + : "v_pk_min_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -344,13 +428,22 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_u16_e64_dpp" + : "v_pk_mad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -377,13 +470,22 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_u16_e64_dpp" + : "v_pk_add_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -410,13 +512,22 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_u16_e64_dpp" + : "v_pk_sub_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -443,13 +554,22 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_u16_e64_dpp" + : "v_pk_max_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -476,13 +596,22 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_u16_e64_dpp" + : "v_pk_min_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -515,13 +644,22 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMA_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fma_f16_e64_dpp" + : "v_pk_fma_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_FMA_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -548,13 +686,22 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_f16_e64_dpp" + : "v_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -581,13 +728,22 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_f16_e64_dpp" + : "v_pk_mul_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -614,13 +770,22 @@ VPkMinF16Vop3p::VPkMinF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_f16_e64_dpp" + : "v_pk_min_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -647,13 +812,22 @@ VPkMaxF16Vop3p::VPkMaxF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_f16_e64_dpp" + : "v_pk_max_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -706,7 +880,16 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f32_f16_e64_dpp" + : "v_dot2_f32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,13 +922,23 @@ VDot4I32Iu8Vop3p::VDot4I32Iu8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_I32_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_i32_iu8_e64_dpp" + : "v_dot4_i32_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_I32_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -778,13 +971,23 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_U32_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_u32_u8_e64_dpp" + : "v_dot4_u32_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -817,13 +1020,23 @@ VDot8I32Iu4Vop3p::VDot8I32Iu4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_I32_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_i32_iu4_e64_dpp" + : "v_dot8_i32_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_I32_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -856,13 +1069,23 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_U32_U4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_u32_u4_e64_dpp" + : "v_dot8_u32_u4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_U32_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -915,7 +1138,16 @@ VDot2F32Bf16Vop3p::VDot2F32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f32_bf16_e64_dpp" + : "v_dot2_f32_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -968,7 +1200,16 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mix_f32_e64_dpp" + : "v_fma_mix_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1022,7 +1263,16 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixlo_f16_e64_dpp" + : "v_fma_mixlo_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1332,16 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixhi_f16_e64_dpp" + : "v_fma_mixhi_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,13 +1369,23 @@ VWmmaF3216x16x16F16Vop3p::VWmmaF3216x16x16F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_f16_e64_dpp" + : "v_wmma_f32_16x16x16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1138,13 +1407,23 @@ VWmmaF3216x16x16Bf16Vop3p::VWmmaF3216x16x16Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_bf16_e64_dpp" + : "v_wmma_f32_16x16x16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1166,13 +1445,23 @@ VWmmaF1616x16x16F16Vop3p::VWmmaF1616x16x16F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X16_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x16_f16_e64_dpp" + : "v_wmma_f16_16x16x16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X16_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1194,13 +1483,23 @@ VWmmaBf1616x16x16Bf16Vop3p::VWmmaBf1616x16x16Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_BF16_16X16X16_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_bf16_16x16x16_bf16_e64_dpp" + : "v_wmma_bf16_16x16x16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_BF16_16X16X16_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1222,13 +1521,23 @@ VWmmaI3216x16x16Iu8Vop3p::VWmmaI3216x16x16Iu8Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X16_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x16_iu8_e64_dpp" + : "v_wmma_i32_16x16x16_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X16_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1250,13 +1559,23 @@ VWmmaI3216x16x16Iu4Vop3p::VWmmaI3216x16x16Iu4Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X16_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x16_iu4_e64_dpp" + : "v_wmma_i32_16x16x16_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X16_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopc.cpp index 6104b8a5d000..8eb21236f891 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -55,7 +54,15 @@ VCmpFF16Vopc::VCmpFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f16_dpp" + : "v_cmp_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +109,15 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_dpp" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -149,7 +164,15 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_dpp" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -196,7 +219,15 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_dpp" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +274,15 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_dpp" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +329,15 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_dpp" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +384,15 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_dpp" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +439,15 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_dpp" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -431,7 +494,15 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_dpp" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +549,15 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_dpp" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,7 +604,15 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_dpp" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +659,15 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_dpp" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -619,7 +714,15 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_dpp" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +769,15 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_dpp" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -713,7 +824,15 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_dpp" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -760,7 +879,15 @@ VCmpTF16Vopc::VCmpTF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f16_dpp" + : "v_cmp_t_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -804,7 +931,15 @@ VCmpFF32Vopc::VCmpFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f32_dpp" + : "v_cmp_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -848,7 +983,15 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_dpp" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -892,7 +1035,15 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_dpp" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -936,7 +1087,15 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_dpp" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -980,7 +1139,15 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_dpp" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1024,7 +1191,15 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_dpp" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1068,7 +1243,15 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_dpp" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1295,15 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_dpp" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1156,7 +1347,15 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_dpp" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1200,7 +1399,15 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_dpp" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1244,7 +1451,15 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_dpp" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1288,7 +1503,15 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_dpp" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1332,7 +1555,15 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_dpp" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1376,7 +1607,15 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_dpp" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1420,7 +1659,15 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_dpp" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1464,7 +1711,15 @@ VCmpTF32Vopc::VCmpTF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f32_dpp" + : "v_cmp_t_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1488,14 +1743,22 @@ VCmpFF64Vopc::VCmpFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_f64_dpp" + : "v_cmp_f_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1519,14 +1782,22 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_dpp" + : "v_cmp_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1550,14 +1821,22 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_dpp" + : "v_cmp_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1581,14 +1860,22 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_dpp" + : "v_cmp_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1612,14 +1899,22 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_dpp" + : "v_cmp_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1643,14 +1938,22 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_dpp" + : "v_cmp_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1674,14 +1977,22 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_dpp" + : "v_cmp_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1705,14 +2016,22 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_dpp" + : "v_cmp_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1736,14 +2055,22 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_dpp" + : "v_cmp_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1767,14 +2094,22 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_dpp" + : "v_cmp_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1798,14 +2133,22 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_dpp" + : "v_cmp_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1829,14 +2172,22 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_dpp" + : "v_cmp_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1860,14 +2211,22 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_dpp" + : "v_cmp_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1891,14 +2250,22 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_dpp" + : "v_cmp_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1922,14 +2289,22 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_dpp" + : "v_cmp_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1953,14 +2328,22 @@ VCmpTF64Vopc::VCmpTF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_f64_dpp" + : "v_cmp_t_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2007,7 +2390,15 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_dpp" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2054,7 +2445,15 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_dpp" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2101,7 +2500,15 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_dpp" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2148,7 +2555,15 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_dpp" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2195,7 +2610,15 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_dpp" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2242,7 +2665,15 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_dpp" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2289,7 +2720,15 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_dpp" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2336,7 +2775,15 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_dpp" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2383,7 +2830,15 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_dpp" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2430,7 +2885,15 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_dpp" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2477,7 +2940,15 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_dpp" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2524,7 +2995,15 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_dpp" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2568,7 +3047,15 @@ VCmpFI32Vopc::VCmpFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i32_dpp" + : "v_cmp_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2612,7 +3099,15 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_dpp" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2656,7 +3151,15 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_dpp" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2700,7 +3203,15 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_dpp" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2744,7 +3255,15 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_dpp" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2788,7 +3307,15 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_dpp" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2832,7 +3359,15 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_dpp" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2876,7 +3411,15 @@ VCmpTI32Vopc::VCmpTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i32_dpp" + : "v_cmp_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2920,7 +3463,15 @@ VCmpFU32Vopc::VCmpFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u32_dpp" + : "v_cmp_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2964,7 +3515,15 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_dpp" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3008,7 +3567,15 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_dpp" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3052,7 +3619,15 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_dpp" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3096,7 +3671,15 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_dpp" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3140,7 +3723,15 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_dpp" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3184,7 +3775,15 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_dpp" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3228,7 +3827,15 @@ VCmpTU32Vopc::VCmpTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u32_dpp" + : "v_cmp_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3252,14 +3859,22 @@ VCmpFI64Vopc::VCmpFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_i64_dpp" + : "v_cmp_f_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3283,14 +3898,22 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_dpp" + : "v_cmp_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3314,14 +3937,22 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_dpp" + : "v_cmp_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3345,14 +3976,22 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_dpp" + : "v_cmp_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3376,14 +4015,22 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_dpp" + : "v_cmp_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3407,14 +4054,22 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_dpp" + : "v_cmp_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3438,14 +4093,22 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_dpp" + : "v_cmp_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3469,14 +4132,22 @@ VCmpTI64Vopc::VCmpTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_i64_dpp" + : "v_cmp_t_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3500,14 +4171,22 @@ VCmpFU64Vopc::VCmpFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_F_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_f_u64_dpp" + : "v_cmp_f_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3531,14 +4210,22 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_dpp" + : "v_cmp_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3562,14 +4249,22 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_dpp" + : "v_cmp_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3593,14 +4288,22 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_dpp" + : "v_cmp_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3624,14 +4327,22 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_dpp" + : "v_cmp_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3655,14 +4366,22 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_dpp" + : "v_cmp_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3686,14 +4405,22 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_dpp" + : "v_cmp_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3717,14 +4444,22 @@ VCmpTU64Vopc::VCmpTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_T_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_t_u64_dpp" + : "v_cmp_t_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3771,7 +4506,16 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_dpp" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3815,7 +4559,16 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_dpp" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3839,14 +4592,23 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_dpp" + : "v_cmp_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3897,7 +4659,15 @@ VCmpxFF16Vopc::VCmpxFF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f16_dpp" + : "v_cmpx_f_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3948,7 +4718,15 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_dpp" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3999,7 +4777,15 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_dpp" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4050,7 +4836,15 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_dpp" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4101,7 +4895,15 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_dpp" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4152,7 +4954,15 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_dpp" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4203,7 +5013,15 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_dpp" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4254,7 +5072,15 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_dpp" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4305,7 +5131,15 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_dpp" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4356,7 +5190,16 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_dpp" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4407,7 +5250,16 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_dpp" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4458,7 +5310,16 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_dpp" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4509,7 +5370,16 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_dpp" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4560,7 +5430,16 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_dpp" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4611,7 +5490,16 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_dpp" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4662,7 +5550,15 @@ VCmpxTF16Vopc::VCmpxTF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f16_dpp" + : "v_cmpx_t_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4710,7 +5606,15 @@ VCmpxFF32Vopc::VCmpxFF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f32_dpp" + : "v_cmpx_f_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4758,7 +5662,15 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_dpp" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4806,7 +5718,15 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_dpp" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4854,7 +5774,15 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_dpp" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4902,7 +5830,15 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_dpp" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4950,7 +5886,15 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_dpp" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4998,7 +5942,15 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_dpp" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5046,7 +5998,15 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_dpp" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5094,7 +6054,15 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_dpp" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5142,7 +6110,16 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_dpp" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5190,7 +6167,16 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_dpp" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5238,7 +6224,16 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_dpp" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5286,7 +6281,16 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_dpp" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5334,7 +6338,16 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_dpp" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5382,7 +6395,16 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_dpp" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5430,7 +6452,15 @@ VCmpxTF32Vopc::VCmpxTF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f32_dpp" + : "v_cmpx_t_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5456,16 +6486,24 @@ VCmpxFF64Vopc::VCmpxFF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_f64_dpp" + : "v_cmpx_f_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5491,16 +6529,24 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_dpp" + : "v_cmpx_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5526,16 +6572,24 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_dpp" + : "v_cmpx_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5561,16 +6615,24 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_dpp" + : "v_cmpx_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5596,16 +6658,24 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_dpp" + : "v_cmpx_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5631,16 +6701,24 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_dpp" + : "v_cmpx_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5666,16 +6744,24 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_dpp" + : "v_cmpx_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5701,16 +6787,24 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_dpp" + : "v_cmpx_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5736,16 +6830,24 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_dpp" + : "v_cmpx_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5771,16 +6873,25 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_dpp" + : "v_cmpx_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5806,16 +6917,25 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_dpp" + : "v_cmpx_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5841,16 +6961,25 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_dpp" + : "v_cmpx_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5876,16 +7005,25 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_dpp" + : "v_cmpx_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5911,16 +7049,25 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_dpp" + : "v_cmpx_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5946,16 +7093,25 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_dpp" + : "v_cmpx_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5981,16 +7137,24 @@ VCmpxTF64Vopc::VCmpxTF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_f64_dpp" + : "v_cmpx_t_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6041,7 +7205,15 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_dpp" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6092,7 +7264,15 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_dpp" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6143,7 +7323,15 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_dpp" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6194,7 +7382,15 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_dpp" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6245,7 +7441,15 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_dpp" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6296,7 +7500,15 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_dpp" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6347,7 +7559,15 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_dpp" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6398,7 +7618,15 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_dpp" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6449,7 +7677,15 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_dpp" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6500,7 +7736,15 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_dpp" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6551,7 +7795,15 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_dpp" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6602,7 +7854,15 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_dpp" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6650,7 +7910,15 @@ VCmpxFI32Vopc::VCmpxFI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i32_dpp" + : "v_cmpx_f_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6698,7 +7966,15 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_dpp" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6746,7 +8022,15 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_dpp" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6794,7 +8078,15 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_dpp" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6842,7 +8134,15 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_dpp" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6890,7 +8190,15 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_dpp" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6938,7 +8246,15 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_dpp" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6986,7 +8302,15 @@ VCmpxTI32Vopc::VCmpxTI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i32_dpp" + : "v_cmpx_t_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7034,7 +8358,15 @@ VCmpxFU32Vopc::VCmpxFU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxFU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u32_dpp" + : "v_cmpx_f_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7082,7 +8414,15 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_dpp" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7130,7 +8470,15 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_dpp" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7178,7 +8526,15 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_dpp" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7226,7 +8582,15 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_dpp" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7274,7 +8638,15 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_dpp" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7322,7 +8694,15 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_dpp" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7370,7 +8750,15 @@ VCmpxTU32Vopc::VCmpxTU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxTU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u32_dpp" + : "v_cmpx_t_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7396,16 +8784,24 @@ VCmpxFI64Vopc::VCmpxFI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_i64_dpp" + : "v_cmpx_f_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7431,16 +8827,24 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_dpp" + : "v_cmpx_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7466,16 +8870,24 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_dpp" + : "v_cmpx_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7501,16 +8913,24 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_dpp" + : "v_cmpx_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7536,16 +8956,24 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_dpp" + : "v_cmpx_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7571,16 +8999,24 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_dpp" + : "v_cmpx_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7606,16 +9042,24 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_dpp" + : "v_cmpx_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7641,16 +9085,24 @@ VCmpxTI64Vopc::VCmpxTI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_i64_dpp" + : "v_cmpx_t_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7676,16 +9128,24 @@ VCmpxFU64Vopc::VCmpxFU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_F_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxFU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxFU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_f_u64_dpp" + : "v_cmpx_f_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_F_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7711,16 +9171,24 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_dpp" + : "v_cmpx_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7746,16 +9214,24 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_dpp" + : "v_cmpx_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7781,16 +9257,24 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_dpp" + : "v_cmpx_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7816,16 +9300,24 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_dpp" + : "v_cmpx_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7851,16 +9343,24 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_dpp" + : "v_cmpx_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7886,16 +9386,24 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_dpp" + : "v_cmpx_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7921,16 +9429,24 @@ VCmpxTU64Vopc::VCmpxTU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_T_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxTU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxTU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_t_u64_dpp" + : "v_cmpx_t_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_T_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7981,7 +9497,16 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_dpp" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8029,7 +9554,16 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_dpp" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8055,16 +9589,25 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_dpp" + : "v_cmpx_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.cpp index 123b10c2fc69..e74cf1ffae76 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.cpp @@ -95,6 +95,24 @@ const char *Vopd::op_name(uint16_t op) { } } +Result Vopd::validate_encoding(const MachineInst *inst, const util::DiagnosticEmitter &emit_error) { + const auto *words = reinterpret_cast(inst); + const uint32_t word0 = words[0]; + const uint32_t word1 = words[1]; + + const uint16_t opx = static_cast((word0 >> 22) & 0xF); + const uint16_t opy = static_cast((word0 >> 17) & 0x1F); + if (!is_valid_opcode(opx, kVopdXOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD X opcode"; + if (!is_valid_opcode(opy, kVopdYOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcy0 == 254) [[unlikely]] + return emit_error.emit() << "VOPD does not support 64-bit literals"; + return Result::success(); +} + Vopd::Vopd(const MachineInst *inst) : IsaInstruction("vopd", selected_exec_fn(InstructionExecutionId::Vopd)), dstx_(32, OperandType::OPR_VGPR, 0), dsty_(32, OperandType::OPR_VGPR, 0), @@ -110,16 +128,10 @@ Vopd::Vopd(const MachineInst *inst) encoding_id_ = 0x32; opx_ = static_cast((word0_ >> 22) & 0xF); opy_ = static_cast((word0_ >> 17) & 0x1F); - if (!is_valid_opcode(opx_, kVopdXOpcodeMask)) - throw util::InvalidInst("invalid VOPD X opcode", ""); - if (!is_valid_opcode(opy_, kVopdYOpcodeMask)) - throw util::InvalidInst("invalid VOPD Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t vsrcx1 = static_cast((word0_ >> 9) & 0xFF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); uint16_t vsrcy1 = static_cast((word1_ >> 9) & 0xFF); - if (srcx0 == 254 || srcy0 == 254) - throw util::InvalidInst("VOPD does not support 64-bit literals", ""); uint16_t vdstx = static_cast((word1_ >> 24) & 0xFF); uint16_t vdsty_hi = static_cast((word1_ >> 17) & 0x7F); uint16_t vdsty = static_cast((vdsty_hi << 1) | ((~vdstx) & 1u)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.h index df398b6b609b..c6f049221aa6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/vopd.h @@ -9,6 +9,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/encodings.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.h" +#include "rocjitsu/isa/decode_result.h" #include #include @@ -18,6 +19,8 @@ namespace rdna3_5 { class Vopd : public IsaInstruction { public: explicit Vopd(const MachineInst *inst); + static Result validate_encoding(const MachineInst *inst, + const util::DiagnosticEmitter &emit_error); void execute_impl(amdgpu::Wavefront &wf); private: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.cpp index e07df1fb639e..bcd3b11d6670 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.h" -#include "util/except.h" #include #include #include @@ -16,1573 +15,2198 @@ namespace rocjitsu { namespace rdna4 { namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB128Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadB96Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiFormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadFormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadI8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferLoadU8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB128Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB32Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB64Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreB96Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreD16HiFormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeBufferStoreFormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeDsAddF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAddU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAndRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsAppendVds(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsBpermuteFiB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsBvhStackPush4Pop1RtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsBvhStackPush8Pop1RtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsBvhStackPush8Pop2RtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCondSubRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCondSubU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsConsumeVds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDecRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDecU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsDirectLoadVdsdir(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsIncU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadAddtidB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB128Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadB96Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8D16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadI8Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16D16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8D16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsLoadU8Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumRtnF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxNumRtnF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMaxU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumRtnF32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinNumRtnF64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnI64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMinU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsMskorRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsNopVds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsOrB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsOrRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsParamLoadVdsdir(const MachineInst *opcode); -std::unique_ptr decodeDsPermuteB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddBf16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddF16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnBf16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsPkAddRtnF16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsRsubU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStore2addrStride64B64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreAddtidB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB128Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB16Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8D16HiVds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB8Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStoreB96Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsStorexchgRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubClampRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubClampU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubRtnU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSubU64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsSwizzleB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorB64Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB32Vds(const MachineInst *opcode); -std::unique_ptr decodeDsXorRtnB64Vds(const MachineInst *opcode); -std::unique_ptr decodeExportVexport(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddF32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAddU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicAndB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicDecU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicIncU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinI64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicMinU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicOrB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSubU64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatAtomicXorB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB128Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadB96Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16B16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16I8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadD16U8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadI8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatLoadU8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB128Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB32Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB64Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB8Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreB96Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode); -std::unique_ptr decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicOrderedAddB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalInvVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadB96Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadBlockVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadI16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadI8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadTrB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadTrB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadU16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalLoadU8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB128Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB32Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB64Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreB96Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreBlockVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalWbVglobal(const MachineInst *opcode); -std::unique_ptr decodeGlobalWbinvVglobal(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddFltVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAddUintVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicAndVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicCmpswapVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicDecUintVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicIncUintVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicMaxFltVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicMaxIntVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicMaxUintVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicMinFltVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicMinIntVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicMinUintVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicOrVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicPkAddBf16Vimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicPkAddF16Vimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSubUintVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicSwapVimage(const MachineInst *opcode); -std::unique_ptr decodeImageAtomicXorVimage(const MachineInst *opcode); -std::unique_ptr decodeImageBvh64IntersectRayVimage(const MachineInst *opcode); -std::unique_ptr decodeImageBvh8IntersectRayVimage(const MachineInst *opcode); -std::unique_ptr decodeImageBvhDualIntersectRayVimage(const MachineInst *opcode); -std::unique_ptr decodeImageBvhIntersectRayVimage(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4BVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CBVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CLzVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4CVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4ClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4LzVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4OVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageGather4hVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGetLodVsample(const MachineInst *opcode); -std::unique_ptr decodeImageGetResinfoVimage(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckSgnVimage(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipPckVimage(const MachineInst *opcode); -std::unique_ptr decodeImageLoadMipVimage(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckSgnVimage(const MachineInst *opcode); -std::unique_ptr decodeImageLoadPckVimage(const MachineInst *opcode); -std::unique_ptr decodeImageLoadVimage(const MachineInst *opcode); -std::unique_ptr decodeImageMsaaLoadVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleBVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCBVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCDVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCLzVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleCVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDClVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOG16Vsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleDVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleLzVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleOVsample(const MachineInst *opcode); -std::unique_ptr decodeImageSampleVsample(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipPckVimage(const MachineInst *opcode); -std::unique_ptr decodeImageStoreMipVimage(const MachineInst *opcode); -std::unique_ptr decodeImageStorePckVimage(const MachineInst *opcode); -std::unique_ptr decodeImageStoreVimage(const MachineInst *opcode); -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddCoCiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddCoI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddCoU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddNcU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAddkCoI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSAllocVgprSop1(const MachineInst *opcode); -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode); -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode); -std::unique_ptr decodeSBarrierSignalSop1(const MachineInst *opcode); -std::unique_ptr decodeSBarrierWaitSopp(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode); -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadB96Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadI16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadI8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadU16Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferLoadU8Smem(const MachineInst *opcode); -std::unique_ptr decodeSBufferPrefetchDataSmem(const MachineInst *opcode); -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode); -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode); -std::unique_ptr decodeSCeilF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCeilF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode); -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNeqF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNeqF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgeF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgeF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgtF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNgtF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNleF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNleF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNlgF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNlgF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNltF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpNltF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpOF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpOF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpUF16Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCmpUF32Sopc(const MachineInst *opcode); -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode); -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF16F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32F16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32I32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtF32U32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtHiF32F16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtI32F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSCvtU32F32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode); -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode); -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode); -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode); -std::unique_ptr decodeSFloorF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFloorF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSFmaakF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmacF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmacF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSFmamkF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode); -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode); -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadB96Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadI16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadI8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadU16Smem(const MachineInst *opcode); -std::unique_ptr decodeSLoadU8Smem(const MachineInst *opcode); -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxNumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxNumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaximumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMaximumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinNumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinNumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinimumF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMinimumF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSMulF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNopSopp(const MachineInst *opcode); -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchDataPcRelSmem(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchDataSmem(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchInstPcRelSmem(const MachineInst *opcode); -std::unique_ptr decodeSPrefetchInstSmem(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRndneF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRndneF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode); -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode); -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode); -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode); -std::unique_ptr decodeSSleepVarSop1(const MachineInst *opcode); -std::unique_ptr decodeSSubCoCiU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubCoI32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubCoU32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubF16Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubF32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSubNcU64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode); -std::unique_ptr decodeSTruncF16Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTruncF32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode); -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode); -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode); -std::unique_ptr decodeSWaitAluSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitBvhcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitDscntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitEventSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitExpcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitKmcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitLoadcntDscntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitLoadcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitSamplecntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitStorecntDscntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitStorecntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode); -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode); -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode); -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB128Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB32Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB64Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadB96Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadBlockVscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16B16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16I8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadD16U8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadI16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadI8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadU16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchLoadU8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB128Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB32Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB64Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreB96Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreBlockVscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode); -std::unique_ptr decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferLoadFormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzVbuffer(const MachineInst *opcode); -std::unique_ptr decodeTbufferStoreFormatXyzwVbuffer(const MachineInst *opcode); -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2F16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4F32Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4F32Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4F32Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4F32Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10F16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3NumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3NumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxNumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximum3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximum3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumminimumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaximumminimumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3NumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3NumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3NumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3NumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinNumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimum3F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimum3F32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimumF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimummaximumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinimummaximumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxNumF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxNumF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode); -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode); -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNopVop1(const MachineInst *opcode); -std::unique_ptr decodeVNopVop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane16VarB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlane64B32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPermlanex16VarB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode); -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode); -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxNumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMaximumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinNumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMinimumF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSExpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSExpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSLogF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSLogF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRcpF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRcpF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRsqF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSRsqF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacBf1616x16x32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF1616x16x32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x32Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x32Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x32Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x32F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x32Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacF3216x16x32Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacI3216x16x32Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacI3216x16x32Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVSwmmacI3216x16x64Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode); -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode); -std::unique_ptr decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Bf8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Bf8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Fp8Bf8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaF3216x16x16Fp8Fp8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWmmaI3216x16x32Iu4Vop3p(const MachineInst *opcode); -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode); -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode); +DecodeResult decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferLoadU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreD16HiFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeBufferStoreFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAddU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAndRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsAppendVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBpermuteFiB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBvhStackPush4Pop1RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBvhStackPush8Pop1RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsBvhStackPush8Pop2RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondSubRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondSubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsConsumeVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDecU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsDirectLoadVdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsIncU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadI8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsLoadU8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMaxU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMinU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsMskorRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsNopVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsOrRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsParamLoadVdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPermuteB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddBf16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddF16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnBf16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsPkAddRtnF16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsRsubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStore2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStoreB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsStorexchgRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubClampRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubClampU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsSwizzleB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeDsXorRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeExportVexport(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAddU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicAndB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicDecU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicIncU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicMinU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicOrB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSubU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatAtomicXorB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16B16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16I8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadD16U8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadI8Vflat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatLoadU8Vflat(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicOrderedAddB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalInvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadI16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadTrB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadTrB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadU16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalLoadU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalWbVglobal(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeGlobalWbinvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddFltVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAddUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicAndVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicCmpswapVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicDecUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicIncUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicMaxFltVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicMaxIntVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicMaxUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicMinFltVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicMinIntVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicMinUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicOrVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicPkAddBf16Vimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicPkAddF16Vimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSubUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicSwapVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageAtomicXorVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvh64IntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvh8IntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvhDualIntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageBvhIntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4BVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CBVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CLzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4CVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4ClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4LzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4OVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGather4hVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetLodVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageGetResinfoVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckSgnVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipPckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadMipVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckSgnVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadPckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageLoadVimage(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageMsaaLoadVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleBVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCBVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCDVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCLzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleCVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleDVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleLzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageSampleVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipPckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreMipVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStorePckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeImageStoreVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddCoCiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAddkCoI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAllocVgprSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierSignalSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBarrierWaitSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadB96Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadI16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadI8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadU16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferLoadU8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSBufferPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCeilF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCeilF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNeqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNeqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNgtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNleF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNleF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNlgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNlgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNltF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpNltF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpOF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpOF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpUF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCmpUF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF16F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32F16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32I32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtF32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtHiF32F16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtI32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSCvtU32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFloorF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFloorF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmaakF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmacF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmacF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSFmamkF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadB96Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadI16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadI8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadU16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLoadU8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaximumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMaximumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinimumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMinimumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchDataPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchInstPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSPrefetchInstSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRndneF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRndneF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSleepVarSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubCoCiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSubNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTruncF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTruncF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitBvhcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitDscntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitEventSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitExpcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitKmcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitLoadcntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitLoadcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitSamplecntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitStorecntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitStorecntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16B16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16I8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadD16U8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadI16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadU16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchLoadU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferLoadFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeTbufferStoreFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4F32Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4F32Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4F32Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4F32Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3NumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3NumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumminimumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaximumminimumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3NumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3NumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3NumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3NumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimummaximumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinimummaximumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlane64B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPermlanex16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMaximumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMinimumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacBf1616x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF1616x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x32Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x32Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x32Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacF3216x16x32Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacI3216x16x32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacI3216x16x32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVSwmmacI3216x16x64Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaF3216x16x16Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWmmaI3216x16x32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); } // namespace detail struct DecoderImpl { public: - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); private: - using DecodeFunc = std::unique_ptr (*)(const MachineInst *); - static std::unique_ptr decodeInvalid(const MachineInst *opcode); - static std::unique_ptr decodeVopd(const MachineInst *opcode); - static std::unique_ptr subDecodeVopc(const MachineInst *opcode); - static std::unique_ptr subDecodeVop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSop1(const MachineInst *opcode); - static std::unique_ptr subDecodeSopc(const MachineInst *opcode); - static std::unique_ptr subDecodeSopp(const MachineInst *opcode); - static std::unique_ptr subDecodeVbuffer(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3p(const MachineInst *opcode); - static std::unique_ptr subDecodeVinterp(const MachineInst *opcode); - static std::unique_ptr subDecodeVdsdir(const MachineInst *opcode); - static std::unique_ptr subDecodeVimage(const MachineInst *opcode); - static std::unique_ptr subDecodeVop3(const MachineInst *opcode); - static std::unique_ptr subDecodeVds(const MachineInst *opcode); - static std::unique_ptr subDecodeVsample(const MachineInst *opcode); - static std::unique_ptr subDecodeVflat(const MachineInst *opcode); - static std::unique_ptr subDecodeVscratch(const MachineInst *opcode); - static std::unique_ptr subDecodeVglobal(const MachineInst *opcode); - static std::unique_ptr subDecodeSmem(const MachineInst *opcode); + using DecodeFunc = DecodeResult (*)(const MachineInst *, const DecodeErrorEmitter &); + static DecodeResult decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult decodeVopd(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); + static DecodeResult subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error); static const std::array primary_decode_table; static const std::array sub_decode_vopc; static const std::array sub_decode_vop1; @@ -1603,107 +2227,128 @@ struct DecoderImpl { static const std::array sub_decode_smem; }; -std::unique_ptr Decoder::decode(const MachineInst *opcode) { - return DecoderImpl::decode(opcode); +DecodeResult Decoder::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + return DecoderImpl::decode(opcode, emit_error); } -std::unique_ptr DecoderImpl::decode(const MachineInst *opcode) { +DecodeResult DecoderImpl::decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { Sop1MachineInst op = std::bit_cast(*opcode); - return primary_decode_table[op.encoding](opcode); + return primary_decode_table[op.encoding](opcode, emit_error); } -std::unique_ptr DecoderImpl::decodeInvalid(const MachineInst *opcode) { - throw util::InvalidInst(std::format("{:X}", *opcode)); - return nullptr; +DecodeResult DecoderImpl::decodeInvalid(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + return emit_error.emit() << "Invalid instruction opcode: " << std::format("{:X}", *opcode); } -std::unique_ptr DecoderImpl::decodeVopd(const MachineInst *opcode) { +DecodeResult DecoderImpl::decodeVopd(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vopd::validate_encoding(opcode, emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } -std::unique_ptr DecoderImpl::subDecodeVopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vopc[op.op](opcode); + return sub_decode_vopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop1[op.op](opcode); + return sub_decode_vop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSop1(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sop1::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sop1[op.op](opcode); + return sub_decode_sop1[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopc(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopc::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopc[op.op](opcode); + return sub_decode_sopc[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSopp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Sopp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_sopp[op.op](opcode); + return sub_decode_sopp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVbuffer(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vbuffer::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vbuffer[op.op](opcode); + return sub_decode_vbuffer[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3p(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3p::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3p[op.op](opcode); + return sub_decode_vop3p[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVinterp(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vinterp::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vinterp[op.op](opcode); + return sub_decode_vinterp[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVdsdir(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vdsdir::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vdsdir[op.op](opcode); + return sub_decode_vdsdir[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVimage(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vimage::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vimage[op.op](opcode); + return sub_decode_vimage[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVop3(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vop3::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vop3[op.op](opcode); + return sub_decode_vop3[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVds(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vds::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vds[op.op](opcode); + return sub_decode_vds[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVsample(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vsample::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vsample[op.op](opcode); + return sub_decode_vsample[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVflat(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vflat::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vflat[op.op](opcode); + return sub_decode_vflat[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVscratch(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vscratch::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vscratch[op.op](opcode); + return sub_decode_vscratch[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeVglobal(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Vglobal::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_vglobal[op.op](opcode); + return sub_decode_vglobal[op.op](opcode, emit_error); } -std::unique_ptr DecoderImpl::subDecodeSmem(const MachineInst *opcode) { +DecodeResult DecoderImpl::subDecodeSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { Smem::OpEncoding op = *reinterpret_cast(opcode); - return sub_decode_smem[op.op](opcode); + return sub_decode_smem[op.op](opcode, emit_error); } const std::array DecoderImpl::primary_decode_table = { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h index 66e82569097b..574c181efd1a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/decoder.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_ARCH_AMDGPU_RDNA4_DECODER_H_ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/machine_insts.h" +#include "rocjitsu/isa/decode_result.h" #include #include #include @@ -21,7 +22,7 @@ namespace rdna4 { class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 3; - static std::unique_ptr decode(const MachineInst *opcode); + static DecodeResult decode(const MachineInst *opcode, const DecodeErrorEmitter &emit_error); }; } // namespace rdna4 diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp index 53274ac419bf..f1cc0cb96af2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.cpp @@ -5,7 +5,6 @@ // See lib/python/amdisa/README.md for regeneration instructions. #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h" -#include "util/except.h" #include #include @@ -1197,9 +1196,6 @@ Vop3::Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exe raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -1303,9 +1299,6 @@ Vop3p::Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) @@ -1503,9 +1496,6 @@ Vop3SdstEnc::Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst raw_encoding_ = reinterpret_cast(&inst_); encoding_id_ = raw_encoding_[0] >> 23; opcode_ = inst_.op; - if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && - (has_encoded_literal32())) - throw util::InvalidInst("DPP and literal operands cannot be combined", ""); if (has_encoded_literal32()) size_ += sizeof(MachineInst); if (inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h index 76c34b62aef6..913f8736e693 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h @@ -10,6 +10,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/rdna4/isa.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include #include @@ -535,6 +536,15 @@ class Vop3 : public IsaInstruction { public: Vop3(std::string_view mnemonic, const Vop3MachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3MachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -561,6 +571,15 @@ class Vop3p : public IsaInstruction { public: Vop3p(std::string_view mnemonic, const Vop3pMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3pMachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); @@ -662,6 +681,15 @@ class Vop3SdstEnc : public IsaInstruction { public: Vop3SdstEnc(std::string_view mnemonic, const Vop3SdstEncMachineInst *inst, ExecuteFn exec_fn); bool has_encoded_literal32() const; + static Result validate_encoding([[maybe_unused]] std::string_view mnemonic, + const Vop3SdstEncMachineInst *inst, + const util::DiagnosticEmitter &emit_error) { + const auto &inst_ = *inst; + if ((inst_.src0 == amdgpu::SRC_DPP || amdgpu::dpp::is_src_dpp8(inst_.src0)) && + (inst_.src0 == 255 || inst_.src1 == 255 || inst_.src2 == 255)) [[unlikely]] + return emit_error.emit() << "DPP and literal operands cannot be combined"; + return Result::success(); + } void build_modifiers(std::string &out) const override; void implicit_uses(RegisterSet &uses) const override; bool has_lit_0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp index e01f15de4eea..4b2155a313fe 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.h" #include "rocjitsu/isa/arch/amdgpu/shared/scalar_static_resolve.h" -#include "util/except.h" #include #include #include diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem.cpp index efab9a807f10..814d90c879cb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/smem.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SLoadB32Smem::SLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB32Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -60,7 +63,11 @@ SLoadB64Smem::SLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB64Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -83,7 +90,11 @@ SLoadB128Smem::SLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB128Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -106,7 +117,11 @@ SLoadB256Smem::SLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB256Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +144,11 @@ SLoadB512Smem::SLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB512Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -152,7 +171,11 @@ SLoadB96Smem::SLoadB96Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadB96Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadB96Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +198,11 @@ SLoadI8Smem::SLoadI8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadI8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadI8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -198,7 +225,11 @@ SLoadU8Smem::SLoadU8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadU8Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadU8Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -221,7 +252,11 @@ SLoadI16Smem::SLoadI16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadI16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadI16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -244,7 +279,11 @@ SLoadU16Smem::SLoadU16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLoadU16Smem(const MachineInst *opcode) { +DecodeResult decodeSLoadU16Smem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -267,7 +306,12 @@ SBufferLoadB32Smem::SBufferLoadB32Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB32Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB32Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +334,12 @@ SBufferLoadB64Smem::SBufferLoadB64Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB64Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB64Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +362,12 @@ SBufferLoadB128Smem::SBufferLoadB128Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB128Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB128Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -336,7 +390,12 @@ SBufferLoadB256Smem::SBufferLoadB256Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB256Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB256Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b256", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -359,7 +418,12 @@ SBufferLoadB512Smem::SBufferLoadB512Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB512Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB512Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b512", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -382,7 +446,12 @@ SBufferLoadB96Smem::SBufferLoadB96Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadB96Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadB96Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -405,7 +474,12 @@ SBufferLoadI8Smem::SBufferLoadI8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadI8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadI8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +502,12 @@ SBufferLoadU8Smem::SBufferLoadU8Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadU8Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadU8Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -451,7 +530,12 @@ SBufferLoadI16Smem::SBufferLoadI16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadI16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadI16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -474,7 +558,12 @@ SBufferLoadU16Smem::SBufferLoadU16Smem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferLoadU16Smem(const MachineInst *opcode) { +DecodeResult decodeSBufferLoadU16Smem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +576,11 @@ SDcacheInvSmem::SDcacheInvSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDcacheInvSmem(const MachineInst *opcode) { +DecodeResult decodeSDcacheInvSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_dcache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -506,7 +599,11 @@ SAtcProbeSmem::SAtcProbeSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeSmem(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,7 +622,12 @@ SAtcProbeBufferSmem::SAtcProbeBufferSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAtcProbeBufferSmem(const MachineInst *opcode) { +DecodeResult decodeSAtcProbeBufferSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_atc_probe_buffer", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -546,7 +648,12 @@ SPrefetchInstSmem::SPrefetchInstSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchInstSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchInstSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_inst", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -565,7 +672,12 @@ SPrefetchInstPcRelSmem::SPrefetchInstPcRelSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchInstPcRelSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchInstPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_inst_pc_rel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +698,12 @@ SPrefetchDataSmem::SPrefetchDataSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchDataSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_data", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -607,7 +724,12 @@ SBufferPrefetchDataSmem::SBufferPrefetchDataSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBufferPrefetchDataSmem(const MachineInst *opcode) { +DecodeResult decodeSBufferPrefetchDataSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_buffer_prefetch_data", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +748,12 @@ SPrefetchDataPcRelSmem::SPrefetchDataPcRelSmem(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPrefetchDataPcRelSmem(const MachineInst *opcode) { +DecodeResult decodeSPrefetchDataPcRelSmem(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Smem::validate_encoding( + "s_prefetch_data_pc_rel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1.cpp index 61cf903b0413..73e5d8268013 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,11 @@ SMovB32Sop1::SMovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +55,11 @@ SMovB64Sop1::SMovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_mov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,7 +85,11 @@ SCmovB32Sop1::SCmovB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -105,7 +116,11 @@ SCmovB64Sop1::SCmovB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCmovB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cmov_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -126,7 +141,11 @@ SBrevB32Sop1::SBrevB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +167,11 @@ SBrevB64Sop1::SBrevB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBrevB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBrevB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_brev_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ SCtzI32B32Sop1::SCtzI32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +218,11 @@ SCtzI32B64Sop1::SCtzI32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCtzI32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSCtzI32B64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ctz_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -212,7 +243,11 @@ SClzI32U32Sop1::SClzI32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -234,7 +269,11 @@ SClzI32U64Sop1::SClzI32U64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClzI32U64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClzI32U64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_clz_i32_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -255,7 +294,11 @@ SClsI32Sop1::SClsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -277,7 +320,11 @@ SClsI32I64Sop1::SClsI32I64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClsI32I64Sop1(const MachineInst *opcode) { +DecodeResult decodeSClsI32I64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cls_i32_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -299,7 +346,11 @@ SSextI32I8Sop1::SSextI32I8Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I8Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I8Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -321,7 +372,12 @@ SSextI32I16Sop1::SSextI32I16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSextI32I16Sop1(const MachineInst *opcode) { +DecodeResult decodeSSextI32I16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sext_i32_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +399,12 @@ SBitset0B32Sop1::SBitset0B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +426,12 @@ SBitset0B64Sop1::SBitset0B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset0B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset0B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -387,7 +453,12 @@ SBitset1B32Sop1::SBitset1B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -409,7 +480,12 @@ SBitset1B64Sop1::SBitset1B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitset1B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitset1B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitset1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -430,7 +506,12 @@ SBitreplicateB64B32Sop1::SBitreplicateB64B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitreplicateB64B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBitreplicateB64B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bitreplicate_b64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -454,7 +535,11 @@ SAbsI32Sop1::SAbsI32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsI32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAbsI32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_abs_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +563,12 @@ SBcnt0I32B32Sop1::SBcnt0I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -503,7 +593,12 @@ SBcnt0I32B64Sop1::SBcnt0I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt0I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt0I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt0_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +622,12 @@ SBcnt1I32B32Sop1::SBcnt1I32B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -552,7 +652,12 @@ SBcnt1I32B64Sop1::SBcnt1I32B64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBcnt1I32B64Sop1(const MachineInst *opcode) { +DecodeResult decodeSBcnt1I32B64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_bcnt1_i32_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -576,7 +681,12 @@ SQuadmaskB32Sop1::SQuadmaskB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +711,12 @@ SQuadmaskB64Sop1::SQuadmaskB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSQuadmaskB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSQuadmaskB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_quadmask_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +740,11 @@ SWqmB32Sop1::SWqmB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +769,11 @@ SWqmB64Sop1::SWqmB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWqmB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSWqmB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_wqm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -674,7 +797,11 @@ SNotB32Sop1::SNotB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +826,11 @@ SNotB64Sop1::SNotB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNotB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNotB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_not_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -730,7 +861,12 @@ SAndSaveexecB32Sop1::SAndSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,7 +898,12 @@ SAndSaveexecB64Sop1::SAndSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -794,7 +935,12 @@ SOrSaveexecB32Sop1::SOrSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -827,7 +973,12 @@ SOrSaveexecB64Sop1::SOrSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -858,7 +1009,12 @@ SXorSaveexecB32Sop1::SXorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -890,7 +1046,12 @@ SXorSaveexecB64Sop1::SXorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -921,7 +1082,12 @@ SNandSaveexecB32Sop1::SNandSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -953,7 +1119,12 @@ SNandSaveexecB64Sop1::SNandSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNandSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nand_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -984,7 +1155,12 @@ SNorSaveexecB32Sop1::SNorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1192,12 @@ SNorSaveexecB64Sop1::SNorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSNorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_nor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1047,7 +1228,12 @@ SXnorSaveexecB32Sop1::SXnorSaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1079,7 +1265,12 @@ SXnorSaveexecB64Sop1::SXnorSaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorSaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSXnorSaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_xnor_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1110,7 +1301,12 @@ SAndNot0SaveexecB32Sop1::SAndNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1338,12 @@ SAndNot0SaveexecB64Sop1::SAndNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1173,7 +1374,12 @@ SOrNot0SaveexecB32Sop1::SOrNot0SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1205,7 +1411,12 @@ SOrNot0SaveexecB64Sop1::SOrNot0SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot0SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not0_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1236,7 +1447,12 @@ SAndNot1SaveexecB32Sop1::SAndNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1268,7 +1484,12 @@ SAndNot1SaveexecB64Sop1::SAndNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1299,7 +1520,12 @@ SOrNot1SaveexecB32Sop1::SOrNot1SaveexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,7 +1557,12 @@ SOrNot1SaveexecB64Sop1::SOrNot1SaveexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSOrNot1SaveexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_or_not1_saveexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1362,7 +1593,12 @@ SAndNot0WrexecB32Sop1::SAndNot0WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1394,7 +1630,12 @@ SAndNot0WrexecB64Sop1::SAndNot0WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot0WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not0_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1425,7 +1666,12 @@ SAndNot1WrexecB32Sop1::SAndNot1WrexecB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1457,7 +1703,12 @@ SAndNot1WrexecB64Sop1::SAndNot1WrexecB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSAndNot1WrexecB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_and_not1_wrexec_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1477,7 +1728,12 @@ SMovrelsB32Sop1::SMovrelsB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,7 +1753,12 @@ SMovrelsB64Sop1::SMovrelsB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrels_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1521,7 +1782,12 @@ SMovreldB32Sop1::SMovreldB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1546,7 +1812,12 @@ SMovreldB64Sop1::SMovreldB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovreldB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovreldB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movreld_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1566,7 +1837,12 @@ SMovrelsd2B32Sop1::SMovrelsd2B32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovrelsd2B32Sop1(const MachineInst *opcode) { +DecodeResult decodeSMovrelsd2B32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_movrelsd_2_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1860,11 @@ SGetpcB64Sop1::SGetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSGetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_getpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1603,7 +1883,11 @@ SSetpcB64Sop1::SSetpcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetpcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSetpcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_setpc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1626,7 +1910,11 @@ SSwappcB64Sop1::SSwappcB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSwappcB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSwappcB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_swappc_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1644,7 +1932,11 @@ SRfeB64Sop1::SRfeB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRfeB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSRfeB64Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rfe_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1661,7 +1953,12 @@ SSendmsgRtnB32Sop1::SSendmsgRtnB32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB32Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB32Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sendmsg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1678,7 +1975,12 @@ SSendmsgRtnB64Sop1::SSendmsgRtnB64Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgRtnB64Sop1(const MachineInst *opcode) { +DecodeResult decodeSSendmsgRtnB64Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sendmsg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1695,7 +1997,12 @@ SBarrierSignalSop1::SBarrierSignalSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSignalSop1(const MachineInst *opcode) { +DecodeResult decodeSBarrierSignalSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_barrier_signal", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1714,7 +2021,12 @@ SBarrierSignalIsfirstSop1::SBarrierSignalIsfirstSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode) { +DecodeResult decodeSBarrierSignalIsfirstSop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_barrier_signal_isfirst", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1736,7 +2048,11 @@ SAllocVgprSop1::SAllocVgprSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAllocVgprSop1(const MachineInst *opcode) { +DecodeResult decodeSAllocVgprSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_alloc_vgpr", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2071,11 @@ SSleepVarSop1::SSleepVarSop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepVarSop1(const MachineInst *opcode) { +DecodeResult decodeSSleepVarSop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_sleep_var", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2096,11 @@ SCeilF32Sop1::SCeilF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCeilF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCeilF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ceil_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2121,11 @@ SFloorF32Sop1::SFloorF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFloorF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSFloorF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_floor_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,7 +2146,11 @@ STruncF32Sop1::STruncF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTruncF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSTruncF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_trunc_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1839,7 +2171,11 @@ SRndneF32Sop1::SRndneF32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRndneF32Sop1(const MachineInst *opcode) { +DecodeResult decodeSRndneF32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rndne_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1860,7 +2196,11 @@ SCvtF32I32Sop1::SCvtF32I32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32I32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32I32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1881,7 +2221,11 @@ SCvtF32U32Sop1::SCvtF32U32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32U32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32U32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1902,7 +2246,11 @@ SCvtI32F32Sop1::SCvtI32F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtI32F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtI32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_i32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1923,7 +2271,11 @@ SCvtU32F32Sop1::SCvtU32F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtU32F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtU32F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_u32_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1944,7 +2296,11 @@ SCvtF16F32Sop1::SCvtF16F32Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF16F32Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF16F32Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1972,7 +2328,11 @@ SCvtF32F16Sop1::SCvtF32F16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtF32F16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtF32F16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1994,7 +2354,12 @@ SCvtHiF32F16Sop1::SCvtHiF32F16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtHiF32F16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCvtHiF32F16Sop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_cvt_hi_f32_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2016,7 +2381,11 @@ SCeilF16Sop1::SCeilF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCeilF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSCeilF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_ceil_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2044,7 +2413,11 @@ SFloorF16Sop1::SFloorF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFloorF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSFloorF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_floor_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2072,7 +2445,11 @@ STruncF16Sop1::STruncF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTruncF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSTruncF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_trunc_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2100,7 +2477,11 @@ SRndneF16Sop1::SRndneF16Sop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRndneF16Sop1(const MachineInst *opcode) { +DecodeResult decodeSRndneF16Sop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop1::validate_encoding( + "s_rndne_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop2.cpp index 299b60953f30..cb76b8c8a76e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop2.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/sop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,11 @@ SAddCoU32Sop2::SAddCoU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddCoU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +70,11 @@ SSubCoU32Sop2::SSubCoU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubCoU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubCoU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_co_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +104,11 @@ SAddCoI32Sop2::SAddCoI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddCoI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_co_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +138,11 @@ SSubCoI32Sop2::SSubCoI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubCoI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubCoI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_co_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -160,7 +175,12 @@ SAddCoCiU32Sop2::SAddCoCiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddCoCiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddCoCiU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -193,7 +213,12 @@ SSubCoCiU32Sop2::SSubCoCiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubCoCiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubCoCiU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_co_ci_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -223,7 +248,12 @@ SAbsdiffI32Sop2::SAbsdiffI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAbsdiffI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAbsdiffI32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_absdiff_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -253,7 +283,11 @@ SLshlB32Sop2::SLshlB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +318,11 @@ SLshlB64Sop2::SLshlB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshlB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshlB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -314,7 +352,11 @@ SLshrB32Sop2::SLshrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -345,7 +387,11 @@ SLshrB64Sop2::SLshrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +421,11 @@ SAshrI32Sop2::SAshrI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -406,7 +456,11 @@ SAshrI64Sop2::SAshrI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAshrI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAshrI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_ashr_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -436,7 +490,12 @@ SLshl1AddU32Sop2::SLshl1AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl1AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl1AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl1_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -466,7 +525,12 @@ SLshl2AddU32Sop2::SLshl2AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl2AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl2AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl2_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -496,7 +560,12 @@ SLshl3AddU32Sop2::SLshl3AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl3AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl3AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl3_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -526,7 +595,12 @@ SLshl4AddU32Sop2::SLshl4AddU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSLshl4AddU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSLshl4AddU32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_lshl4_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -556,7 +630,11 @@ SMinI32Sop2::SMinI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -586,7 +664,11 @@ SMinU32Sop2::SMinU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -616,7 +698,11 @@ SMaxI32Sop2::SMaxI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -646,7 +732,11 @@ SMaxU32Sop2::SMaxU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -676,7 +766,11 @@ SAndB32Sop2::SAndB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -708,7 +802,11 @@ SAndB64Sop2::SAndB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -739,7 +837,11 @@ SOrB32Sop2::SOrB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -772,7 +874,11 @@ SOrB64Sop2::SOrB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -802,7 +908,11 @@ SXorB32Sop2::SXorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -834,7 +944,11 @@ SXorB64Sop2::SXorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -864,7 +978,11 @@ SNandB32Sop2::SNandB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -896,7 +1014,11 @@ SNandB64Sop2::SNandB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNandB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNandB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nand_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -926,7 +1048,11 @@ SNorB32Sop2::SNorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1084,11 @@ SNorB64Sop2::SNorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSNorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_nor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -988,7 +1118,11 @@ SXnorB32Sop2::SXnorB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1020,7 +1154,11 @@ SXnorB64Sop2::SXnorB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSXnorB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSXnorB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_xnor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1050,7 +1188,12 @@ SAndNot1B32Sop2::SAndNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1082,7 +1225,12 @@ SAndNot1B64Sop2::SAndNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAndNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAndNot1B64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_and_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1260,11 @@ SOrNot1B32Sop2::SOrNot1B32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B32Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_not1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1144,7 +1296,11 @@ SOrNot1B64Sop2::SOrNot1B64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSOrNot1B64Sop2(const MachineInst *opcode) { +DecodeResult decodeSOrNot1B64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_or_not1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1174,7 +1330,11 @@ SBfeU32Sop2::SBfeU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1204,7 +1364,11 @@ SBfeI32Sop2::SBfeI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1235,7 +1399,11 @@ SBfeU64Sop2::SBfeU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1266,7 +1434,11 @@ SBfeI64Sop2::SBfeI64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfeI64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfeI64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfe_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,7 +1465,11 @@ SBfmB32Sop2::SBfmB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1320,7 +1496,11 @@ SBfmB64Sop2::SBfmB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBfmB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSBfmB64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_bfm_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1347,7 +1527,11 @@ SMulI32Sop2::SMulI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1374,7 +1558,11 @@ SMulHiU32Sop2::SMulHiU32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiU32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiU32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1401,7 +1589,11 @@ SMulHiI32Sop2::SMulHiI32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulHiI32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulHiI32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_hi_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1431,7 +1623,12 @@ SCselectB32Sop2::SCselectB32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1463,7 +1660,12 @@ SCselectB64Sop2::SCselectB64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCselectB64Sop2(const MachineInst *opcode) { +DecodeResult decodeSCselectB64Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cselect_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1492,7 +1694,12 @@ SPackLlB32B16Sop2::SPackLlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_ll_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1520,7 +1727,12 @@ SPackLhB32B16Sop2::SPackLhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackLhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackLhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_lh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1547,7 +1759,12 @@ SPackHhB32B16Sop2::SPackHhB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHhB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHhB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hh_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1575,7 +1792,12 @@ SPackHlB32B16Sop2::SPackHlB32B16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSPackHlB32B16Sop2(const MachineInst *opcode) { +DecodeResult decodeSPackHlB32B16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_pack_hl_b32_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1602,7 +1824,11 @@ SAddF32Sop2::SAddF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1629,7 +1855,11 @@ SSubF32Sop2::SSubF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1656,7 +1886,11 @@ SMinNumF32Sop2::SMinNumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinNumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1683,7 +1917,11 @@ SMaxNumF32Sop2::SMaxNumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxNumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxNumF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1710,7 +1948,11 @@ SMulF32Sop2::SMulF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1743,7 +1985,11 @@ SFmaakF32Sop2::SFmaakF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmaakF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmaakF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmaak_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1776,7 +2022,11 @@ SFmamkF32Sop2::SFmamkF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmamkF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmamkF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmamk_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2054,11 @@ SFmacF32Sop2::SFmacF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmacF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmacF32Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmac_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1831,7 +2085,12 @@ SCvtPkRtzF16F32Sop2::SCvtPkRtzF16F32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode) { +DecodeResult decodeSCvtPkRtzF16F32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_cvt_pk_rtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1866,7 +2125,11 @@ SAddF16Sop2::SAddF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1901,7 +2164,11 @@ SSubF16Sop2::SSubF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1936,7 +2203,11 @@ SMinNumF16Sop2::SMinNumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinNumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_min_num_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1971,7 +2242,11 @@ SMaxNumF16Sop2::SMaxNumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaxNumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaxNumF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_max_num_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2281,11 @@ SMulF16Sop2::SMulF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2042,7 +2321,11 @@ SFmacF16Sop2::SFmacF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSFmacF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSFmacF16Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_fmac_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2075,7 +2358,12 @@ SMinimumF32Sop2::SMinimumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinimumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinimumF32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_minimum_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2102,7 +2390,12 @@ SMaximumF32Sop2::SMaximumF32Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaximumF32Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaximumF32Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_maximum_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2131,7 +2424,12 @@ SMinimumF16Sop2::SMinimumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMinimumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMinimumF16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_minimum_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2166,7 +2464,12 @@ SMaximumF16Sop2::SMaximumF16Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMaximumF16Sop2(const MachineInst *opcode) { +DecodeResult decodeSMaximumF16Sop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_maximum_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2201,7 +2504,11 @@ SAddNcU64Sop2::SAddNcU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddNcU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSAddNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_add_nc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2230,7 +2537,11 @@ SSubNcU64Sop2::SSubNcU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSubNcU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSSubNcU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_sub_nc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2259,7 +2570,11 @@ SMulU64Sop2::SMulU64Sop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulU64Sop2(const MachineInst *opcode) { +DecodeResult decodeSMulU64Sop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sop2::validate_encoding( + "s_mul_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopc.cpp index 36357df12376..0d4f695d7cab 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopc.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/sopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ SCmpEqI32Sopc::SCmpEqI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -63,7 +66,11 @@ SCmpLgI32Sopc::SCmpLgI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +98,11 @@ SCmpGtI32Sopc::SCmpGtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -119,7 +130,11 @@ SCmpGeI32Sopc::SCmpGeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +162,11 @@ SCmpLtI32Sopc::SCmpLtI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -175,7 +194,11 @@ SCmpLeI32Sopc::SCmpLeI32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeI32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeI32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +226,11 @@ SCmpEqU32Sopc::SCmpEqU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -231,7 +258,11 @@ SCmpLgU32Sopc::SCmpLgU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +290,11 @@ SCmpGtU32Sopc::SCmpGtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -287,7 +322,11 @@ SCmpGeU32Sopc::SCmpGeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +354,11 @@ SCmpLtU32Sopc::SCmpLtU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -343,7 +386,11 @@ SCmpLeU32Sopc::SCmpLeU32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeU32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeU32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -371,7 +418,12 @@ SBitcmp0B32Sopc::SBitcmp0B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +451,12 @@ SBitcmp1B32Sopc::SBitcmp1B32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B32Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B32Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -428,7 +485,12 @@ SBitcmp0B64Sopc::SBitcmp0B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp0B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp0B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp0_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +519,12 @@ SBitcmp1B64Sopc::SBitcmp1B64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBitcmp1B64Sopc(const MachineInst *opcode) { +DecodeResult decodeSBitcmp1B64Sopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_bitcmp1_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -487,7 +554,11 @@ SCmpEqU64Sopc::SCmpEqU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -517,7 +588,11 @@ SCmpLgU64Sopc::SCmpLgU64Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgU64Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgU64Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +620,11 @@ SCmpLtF32Sopc::SCmpLtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -575,7 +654,11 @@ SCmpLtF16Sopc::SCmpLtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -603,7 +686,11 @@ SCmpEqF32Sopc::SCmpEqF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -633,7 +720,11 @@ SCmpEqF16Sopc::SCmpEqF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpEqF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpEqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_eq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -661,7 +752,11 @@ SCmpLeF32Sopc::SCmpLeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -691,7 +786,11 @@ SCmpLeF16Sopc::SCmpLeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_le_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -719,7 +818,11 @@ SCmpGtF32Sopc::SCmpGtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -749,7 +852,11 @@ SCmpGtF16Sopc::SCmpGtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_gt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -777,7 +884,11 @@ SCmpLgF32Sopc::SCmpLgF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -807,7 +918,11 @@ SCmpLgF16Sopc::SCmpLgF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpLgF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpLgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_lg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -835,7 +950,11 @@ SCmpGeF32Sopc::SCmpGeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -865,7 +984,11 @@ SCmpGeF16Sopc::SCmpGeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpGeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpGeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -893,7 +1016,11 @@ SCmpOF32Sopc::SCmpOF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpOF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpOF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_o_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1050,11 @@ SCmpOF16Sopc::SCmpOF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpOF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpOF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_o_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1082,11 @@ SCmpUF32Sopc::SCmpUF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpUF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpUF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_u_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -981,7 +1116,11 @@ SCmpUF16Sopc::SCmpUF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpUF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpUF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_u_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1009,7 +1148,11 @@ SCmpNgeF32Sopc::SCmpNgeF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgeF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgeF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nge_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1039,7 +1182,11 @@ SCmpNgeF16Sopc::SCmpNgeF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgeF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgeF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nge_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1214,11 @@ SCmpNlgF32Sopc::SCmpNlgF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNlgF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNlgF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlg_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1248,11 @@ SCmpNlgF16Sopc::SCmpNlgF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNlgF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNlgF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlg_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1125,7 +1280,11 @@ SCmpNgtF32Sopc::SCmpNgtF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgtF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgtF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ngt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1155,7 +1314,11 @@ SCmpNgtF16Sopc::SCmpNgtF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNgtF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNgtF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_ngt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1183,7 +1346,11 @@ SCmpNleF32Sopc::SCmpNleF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNleF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNleF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nle_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1213,7 +1380,11 @@ SCmpNleF16Sopc::SCmpNleF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNleF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNleF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nle_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1241,7 +1412,11 @@ SCmpNeqF32Sopc::SCmpNeqF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNeqF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNeqF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_neq_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1446,11 @@ SCmpNeqF16Sopc::SCmpNeqF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNeqF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNeqF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_neq_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1299,7 +1478,11 @@ SCmpNltF32Sopc::SCmpNltF32Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNltF32Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNltF32Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlt_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1329,7 +1512,11 @@ SCmpNltF16Sopc::SCmpNltF16Sopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmpNltF16Sopc(const MachineInst *opcode) { +DecodeResult decodeSCmpNltF16Sopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopc::validate_encoding( + "s_cmp_nlt_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopk.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopk.cpp index f22d64e7484c..5c5c7cf0f71f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopk.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopk.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/sopk.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,11 @@ SMovkI32Sopk::SMovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_movk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -39,7 +42,11 @@ SVersionSopk::SVersionSopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSVersionSopk(const MachineInst *opcode) { +DecodeResult decodeSVersionSopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_version", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -61,7 +68,11 @@ SCmovkI32Sopk::SCmovkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCmovkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSCmovkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_cmovk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,7 +93,11 @@ SAddkCoI32Sopk::SAddkCoI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSAddkCoI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSAddkCoI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_addk_co_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +115,11 @@ SMulkI32Sopk::SMulkI32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSMulkI32Sopk(const MachineInst *opcode) { +DecodeResult decodeSMulkI32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_mulk_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -117,7 +136,11 @@ SGetregB32Sopk::SGetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSGetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSGetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_getreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -134,7 +157,11 @@ SSetregB32Sopk::SSetregB32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregB32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregB32Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +186,12 @@ SSetregImm32B32Sopk::SSetregImm32B32Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetregImm32B32Sopk(const MachineInst *opcode) { +DecodeResult decodeSSetregImm32B32Sopk(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_setreg_imm32_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -188,7 +220,11 @@ SCallB64Sopk::SCallB64Sopk(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCallB64Sopk(const MachineInst *opcode) { +DecodeResult decodeSCallB64Sopk(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopk::validate_encoding( + "s_call_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp.cpp index 7fb461321aab..e3c18c1dcf1a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/sopp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -22,7 +21,11 @@ SNopSopp::SNopSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSNopSopp(const MachineInst *opcode) { +DecodeResult decodeSNopSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -37,7 +40,11 @@ SSetkillSopp::SSetkillSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetkillSopp(const MachineInst *opcode) { +DecodeResult decodeSSetkillSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setkill", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -52,7 +59,11 @@ SSethaltSopp::SSethaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSethaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSethaltSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sethalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +78,11 @@ SSleepSopp::SSleepSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSleepSopp(const MachineInst *opcode) { +DecodeResult decodeSSleepSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sleep", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,7 +97,11 @@ SClauseSopp::SClauseSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSClauseSopp(const MachineInst *opcode) { +DecodeResult decodeSClauseSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_clause", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -97,7 +116,11 @@ SDelayAluSopp::SDelayAluSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDelayAluSopp(const MachineInst *opcode) { +DecodeResult decodeSDelayAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_delay_alu", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -113,7 +136,11 @@ SWaitAluSopp::SWaitAluSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitAluSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitAluSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_alu", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -129,7 +156,11 @@ SWaitcntSopp::SWaitcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_waitcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -143,7 +174,11 @@ SWaitIdleSopp::SWaitIdleSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitIdleSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitIdleSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_idle", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +194,11 @@ SWaitEventSopp::SWaitEventSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitEventSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitEventSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_event", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +213,11 @@ STrapSopp::STrapSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTrapSopp(const MachineInst *opcode) { +DecodeResult decodeSTrapSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_trap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -189,7 +232,11 @@ SRoundModeSopp::SRoundModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSRoundModeSopp(const MachineInst *opcode) { +DecodeResult decodeSRoundModeSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_round_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -204,7 +251,12 @@ SDenormModeSopp::SDenormModeSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDenormModeSopp(const MachineInst *opcode) { +DecodeResult decodeSDenormModeSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_denorm_mode", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -220,7 +272,12 @@ SBarrierWaitSopp::SBarrierWaitSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBarrierWaitSopp(const MachineInst *opcode) { +DecodeResult decodeSBarrierWaitSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_barrier_wait", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +290,11 @@ SCodeEndSopp::SCodeEndSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCodeEndSopp(const MachineInst *opcode) { +DecodeResult decodeSCodeEndSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_code_end", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -250,7 +311,11 @@ SBranchSopp::SBranchSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSBranchSopp(const MachineInst *opcode) { +DecodeResult decodeSBranchSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_branch", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -275,7 +340,12 @@ SCbranchScc0Sopp::SCbranchScc0Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc0Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc0Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc0", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -300,7 +370,12 @@ SCbranchScc1Sopp::SCbranchScc1Sopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchScc1Sopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchScc1Sopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_scc1", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -325,7 +400,12 @@ SCbranchVcczSopp::SCbranchVcczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVcczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVcczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -350,7 +430,12 @@ SCbranchVccnzSopp::SCbranchVccnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchVccnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchVccnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_vccnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -375,7 +460,12 @@ SCbranchExeczSopp::SCbranchExeczSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExeczSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExeczSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -400,7 +490,12 @@ SCbranchExecnzSopp::SCbranchExecnzSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSCbranchExecnzSopp(const MachineInst *opcode) { +DecodeResult decodeSCbranchExecnzSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_cbranch_execnz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -419,7 +514,11 @@ SEndpgmSopp::SEndpgmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -433,7 +532,12 @@ SEndpgmSavedSopp::SEndpgmSavedSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSEndpgmSavedSopp(const MachineInst *opcode) { +DecodeResult decodeSEndpgmSavedSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_endpgm_saved", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -446,7 +550,11 @@ SWakeupSopp::SWakeupSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWakeupSopp(const MachineInst *opcode) { +DecodeResult decodeSWakeupSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wakeup", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -461,7 +569,11 @@ SSetprioSopp::SSetprioSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSetprioSopp(const MachineInst *opcode) { +DecodeResult decodeSSetprioSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_setprio", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -479,7 +591,11 @@ SSendmsgSopp::SSendmsgSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsgSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsgSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsg", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -497,7 +613,12 @@ SSendmsghaltSopp::SSendmsghaltSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSSendmsghaltSopp(const MachineInst *opcode) { +DecodeResult decodeSSendmsghaltSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_sendmsghalt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -512,7 +633,12 @@ SIncperflevelSopp::SIncperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIncperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSIncperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_incperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +653,12 @@ SDecperflevelSopp::SDecperflevelSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSDecperflevelSopp(const MachineInst *opcode) { +DecodeResult decodeSDecperflevelSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_decperflevel", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,7 +674,12 @@ STtracedataSopp::STtracedataSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -561,7 +697,12 @@ STtracedataImmSopp::STtracedataImmSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSTtracedataImmSopp(const MachineInst *opcode) { +DecodeResult decodeSTtracedataImmSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_ttracedata_imm", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -574,7 +715,11 @@ SIcacheInvSopp::SIcacheInvSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSIcacheInvSopp(const MachineInst *opcode) { +DecodeResult decodeSIcacheInvSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_icache_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -590,7 +735,12 @@ SWaitLoadcntSopp::SWaitLoadcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitLoadcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitLoadcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_loadcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -606,7 +756,12 @@ SWaitStorecntSopp::SWaitStorecntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitStorecntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitStorecntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_storecnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -622,7 +777,12 @@ SWaitSamplecntSopp::SWaitSamplecntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitSamplecntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitSamplecntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_samplecnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -638,7 +798,12 @@ SWaitBvhcntSopp::SWaitBvhcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitBvhcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitBvhcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_bvhcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -654,7 +819,12 @@ SWaitExpcntSopp::SWaitExpcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitExpcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitExpcntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_expcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -670,7 +840,11 @@ SWaitDscntSopp::SWaitDscntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitDscntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitDscntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_dscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -686,7 +860,11 @@ SWaitKmcntSopp::SWaitKmcntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitKmcntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitKmcntSopp(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_kmcnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -702,7 +880,12 @@ SWaitLoadcntDscntSopp::SWaitLoadcntDscntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitLoadcntDscntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitLoadcntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_loadcnt_dscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -718,7 +901,12 @@ SWaitStorecntDscntSopp::SWaitStorecntDscntSopp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeSWaitStorecntDscntSopp(const MachineInst *opcode) { +DecodeResult decodeSWaitStorecntDscntSopp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Sopp::validate_encoding( + "s_wait_storecnt_dscnt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vbuffer.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vbuffer.cpp index 12d77de5e6f2..5eaa181cf9c5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vbuffer.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vbuffer.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vbuffer.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -44,7 +43,12 @@ BufferLoadFormatXVbuffer::BufferLoadFormatXVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -70,7 +74,12 @@ BufferLoadFormatXyVbuffer::BufferLoadFormatXyVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -96,7 +105,12 @@ BufferLoadFormatXyzVbuffer::BufferLoadFormatXyzVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -122,7 +136,12 @@ BufferLoadFormatXyzwVbuffer::BufferLoadFormatXyzwVbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadFormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_format_xyzw", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -148,7 +167,12 @@ BufferStoreFormatXVbuffer::BufferStoreFormatXVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -174,7 +198,12 @@ BufferStoreFormatXyVbuffer::BufferStoreFormatXyVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -200,7 +229,12 @@ BufferStoreFormatXyzVbuffer::BufferStoreFormatXyzVbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -226,7 +260,13 @@ BufferStoreFormatXyzwVbuffer::BufferStoreFormatXyzwVbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreFormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_store_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -252,7 +292,13 @@ BufferLoadD16FormatXVbuffer::BufferLoadD16FormatXVbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_load_d16_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +330,13 @@ BufferLoadD16FormatXyVbuffer::BufferLoadD16FormatXyVbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_load_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -310,7 +362,13 @@ BufferLoadD16FormatXyzVbuffer::BufferLoadD16FormatXyzVbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_load_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -342,7 +400,13 @@ BufferLoadD16FormatXyzwVbuffer::BufferLoadD16FormatXyzwVbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeBufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_load_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -368,7 +432,13 @@ BufferStoreD16FormatXVbuffer::BufferStoreD16FormatXVbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_store_d16_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -394,7 +464,13 @@ BufferStoreD16FormatXyVbuffer::BufferStoreD16FormatXyVbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_store_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -420,7 +496,13 @@ BufferStoreD16FormatXyzVbuffer::BufferStoreD16FormatXyzVbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_store_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -446,7 +528,13 @@ BufferStoreD16FormatXyzwVbuffer::BufferStoreD16FormatXyzwVbuffer(const MachineIn } namespace detail { -std::unique_ptr decodeBufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_store_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -472,7 +560,12 @@ BufferLoadU8Vbuffer::BufferLoadU8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -498,7 +591,12 @@ BufferLoadI8Vbuffer::BufferLoadI8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -524,7 +622,12 @@ BufferLoadU16Vbuffer::BufferLoadU16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadU16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadU16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -550,7 +653,12 @@ BufferLoadI16Vbuffer::BufferLoadI16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadI16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadI16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -576,7 +684,12 @@ BufferLoadB32Vbuffer::BufferLoadB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -602,7 +715,12 @@ BufferLoadB64Vbuffer::BufferLoadB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -628,7 +746,12 @@ BufferLoadB96Vbuffer::BufferLoadB96Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB96Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -654,7 +777,12 @@ BufferLoadB128Vbuffer::BufferLoadB128Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadB128Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -680,7 +808,12 @@ BufferStoreB8Vbuffer::BufferStoreB8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -706,7 +839,12 @@ BufferStoreB16Vbuffer::BufferStoreB16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -732,7 +870,12 @@ BufferStoreB32Vbuffer::BufferStoreB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -758,7 +901,12 @@ BufferStoreB64Vbuffer::BufferStoreB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -784,7 +932,12 @@ BufferStoreB96Vbuffer::BufferStoreB96Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB96Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB96Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -810,7 +963,12 @@ BufferStoreB128Vbuffer::BufferStoreB128Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreB128Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreB128Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -836,7 +994,12 @@ BufferLoadD16U8Vbuffer::BufferLoadD16U8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16U8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -868,7 +1031,12 @@ BufferLoadD16I8Vbuffer::BufferLoadD16I8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16I8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -900,7 +1068,12 @@ BufferLoadD16B16Vbuffer::BufferLoadD16B16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16B16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -932,7 +1105,12 @@ BufferLoadD16HiU8Vbuffer::BufferLoadD16HiU8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiU8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -964,7 +1142,12 @@ BufferLoadD16HiI8Vbuffer::BufferLoadD16HiI8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiI8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -996,7 +1179,12 @@ BufferLoadD16HiB16Vbuffer::BufferLoadD16HiB16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1028,7 +1216,12 @@ BufferStoreD16HiB8Vbuffer::BufferStoreD16HiB8Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB8Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1054,7 +1247,12 @@ BufferStoreD16HiB16Vbuffer::BufferStoreD16HiB16Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiB16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1080,7 +1278,13 @@ BufferLoadD16HiFormatXVbuffer::BufferLoadD16HiFormatXVbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferLoadD16HiFormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferLoadD16HiFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_load_d16_hi_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1112,7 +1316,13 @@ BufferStoreD16HiFormatXVbuffer::BufferStoreD16HiFormatXVbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeBufferStoreD16HiFormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferStoreD16HiFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_store_d16_hi_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1142,7 +1352,12 @@ BufferAtomicSwapB32Vbuffer::BufferAtomicSwapB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1173,7 +1388,13 @@ BufferAtomicCmpswapB32Vbuffer::BufferAtomicCmpswapB32Vbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_cmpswap_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1203,7 +1424,12 @@ BufferAtomicAddU32Vbuffer::BufferAtomicAddU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1233,7 +1459,12 @@ BufferAtomicSubU32Vbuffer::BufferAtomicSubU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1263,7 +1494,13 @@ BufferAtomicSubClampU32Vbuffer::BufferAtomicSubClampU32Vbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubClampU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_sub_clamp_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1293,7 +1530,12 @@ BufferAtomicMinI32Vbuffer::BufferAtomicMinI32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1323,7 +1565,12 @@ BufferAtomicMinU32Vbuffer::BufferAtomicMinU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1353,7 +1600,12 @@ BufferAtomicMaxI32Vbuffer::BufferAtomicMaxI32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1383,7 +1635,12 @@ BufferAtomicMaxU32Vbuffer::BufferAtomicMaxU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1413,7 +1670,12 @@ BufferAtomicAndB32Vbuffer::BufferAtomicAndB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1443,7 +1705,12 @@ BufferAtomicOrB32Vbuffer::BufferAtomicOrB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1473,7 +1740,12 @@ BufferAtomicXorB32Vbuffer::BufferAtomicXorB32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,7 +1775,12 @@ BufferAtomicIncU32Vbuffer::BufferAtomicIncU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1533,7 +1810,12 @@ BufferAtomicDecU32Vbuffer::BufferAtomicDecU32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1563,7 +1845,12 @@ BufferAtomicSwapB64Vbuffer::BufferAtomicSwapB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSwapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1594,7 +1881,13 @@ BufferAtomicCmpswapB64Vbuffer::BufferAtomicCmpswapB64Vbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCmpswapB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_cmpswap_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1624,7 +1917,12 @@ BufferAtomicAddU64Vbuffer::BufferAtomicAddU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1654,7 +1952,12 @@ BufferAtomicSubU64Vbuffer::BufferAtomicSubU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicSubU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1684,7 +1987,12 @@ BufferAtomicMinI64Vbuffer::BufferAtomicMinI64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1714,7 +2022,12 @@ BufferAtomicMinU64Vbuffer::BufferAtomicMinU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1744,7 +2057,12 @@ BufferAtomicMaxI64Vbuffer::BufferAtomicMaxI64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxI64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1774,7 +2092,12 @@ BufferAtomicMaxU64Vbuffer::BufferAtomicMaxU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1804,7 +2127,12 @@ BufferAtomicAndB64Vbuffer::BufferAtomicAndB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAndB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1834,7 +2162,12 @@ BufferAtomicOrB64Vbuffer::BufferAtomicOrB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicOrB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1864,7 +2197,12 @@ BufferAtomicXorB64Vbuffer::BufferAtomicXorB64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicXorB64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1894,7 +2232,12 @@ BufferAtomicIncU64Vbuffer::BufferAtomicIncU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicIncU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1924,7 +2267,12 @@ BufferAtomicDecU64Vbuffer::BufferAtomicDecU64Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicDecU64Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1954,7 +2302,13 @@ BufferAtomicCondSubU32Vbuffer::BufferAtomicCondSubU32Vbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicCondSubU32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_cond_sub_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1984,7 +2338,13 @@ BufferAtomicMinNumF32Vbuffer::BufferAtomicMinNumF32Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMinNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_min_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2014,7 +2374,13 @@ BufferAtomicMaxNumF32Vbuffer::BufferAtomicMaxNumF32Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicMaxNumF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_max_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2044,7 +2410,12 @@ BufferAtomicAddF32Vbuffer::BufferAtomicAddF32Vbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicAddF32Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "buffer_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2074,7 +2445,13 @@ BufferAtomicPkAddF16Vbuffer::BufferAtomicPkAddF16Vbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddF16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2104,7 +2481,13 @@ BufferAtomicPkAddBf16Vbuffer::BufferAtomicPkAddBf16Vbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode) { +DecodeResult decodeBufferAtomicPkAddBf16Vbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("buffer_atomic_pk_add_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2129,7 +2512,12 @@ TbufferLoadFormatXVbuffer::TbufferLoadFormatXVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "tbuffer_load_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2154,7 +2542,12 @@ TbufferLoadFormatXyVbuffer::TbufferLoadFormatXyVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "tbuffer_load_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2179,7 +2572,12 @@ TbufferLoadFormatXyzVbuffer::TbufferLoadFormatXyzVbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "tbuffer_load_format_xyz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2204,7 +2602,13 @@ TbufferLoadFormatXyzwVbuffer::TbufferLoadFormatXyzwVbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadFormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_load_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2229,7 +2633,12 @@ TbufferStoreFormatXVbuffer::TbufferStoreFormatXVbuffer(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "tbuffer_store_format_x", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2254,7 +2663,12 @@ TbufferStoreFormatXyVbuffer::TbufferStoreFormatXyVbuffer(const MachineInst *inst } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vbuffer::validate_encoding( + "tbuffer_store_format_xy", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2279,7 +2693,13 @@ TbufferStoreFormatXyzVbuffer::TbufferStoreFormatXyzVbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_store_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2304,7 +2724,13 @@ TbufferStoreFormatXyzwVbuffer::TbufferStoreFormatXyzwVbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreFormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreFormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_store_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2330,7 +2756,13 @@ TbufferLoadD16FormatXVbuffer::TbufferLoadD16FormatXVbuffer(const MachineInst *in } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_load_d16_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2362,7 +2794,13 @@ TbufferLoadD16FormatXyVbuffer::TbufferLoadD16FormatXyVbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_load_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2388,7 +2826,13 @@ TbufferLoadD16FormatXyzVbuffer::TbufferLoadD16FormatXyzVbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_load_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2420,7 +2864,13 @@ TbufferLoadD16FormatXyzwVbuffer::TbufferLoadD16FormatXyzwVbuffer(const MachineIn } namespace detail { -std::unique_ptr decodeTbufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferLoadD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_load_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2446,7 +2896,13 @@ TbufferStoreD16FormatXVbuffer::TbufferStoreD16FormatXVbuffer(const MachineInst * } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_store_d16_format_x", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2472,7 +2928,13 @@ TbufferStoreD16FormatXyVbuffer::TbufferStoreD16FormatXyVbuffer(const MachineInst } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_store_d16_format_xy", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2498,7 +2960,13 @@ TbufferStoreD16FormatXyzVbuffer::TbufferStoreD16FormatXyzVbuffer(const MachineIn } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyzVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyzVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_store_d16_format_xyz", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2524,7 +2992,13 @@ TbufferStoreD16FormatXyzwVbuffer::TbufferStoreD16FormatXyzwVbuffer(const Machine } namespace detail { -std::unique_ptr decodeTbufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode) { +DecodeResult decodeTbufferStoreD16FormatXyzwVbuffer(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vbuffer::validate_encoding("tbuffer_store_d16_format_xyzw", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vds.cpp index ad3d19da5d64..9f2d276d2531 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vds.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vds.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,11 @@ DsAddU32Vds::DsAddU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +57,11 @@ DsSubU32Vds::DsSubU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +84,11 @@ DsRsubU32Vds::DsRsubU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +111,11 @@ DsIncU32Vds::DsIncU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +138,11 @@ DsDecU32Vds::DsDecU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +165,11 @@ DsMinI32Vds::DsMinI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +192,11 @@ DsMaxI32Vds::DsMaxI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +219,11 @@ DsMinU32Vds::DsMinU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +246,11 @@ DsMaxU32Vds::DsMaxU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +273,11 @@ DsAndB32Vds::DsAndB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +300,11 @@ DsOrB32Vds::DsOrB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +327,11 @@ DsXorB32Vds::DsXorB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -309,7 +356,11 @@ DsMskorB32Vds::DsMskorB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +381,11 @@ DsStoreB32Vds::DsStoreB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +408,12 @@ DsStore2addrB32Vds::DsStore2addrB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -376,7 +436,12 @@ DsStore2addrStride64B32Vds::DsStore2addrStride64B32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +466,12 @@ DsCmpstoreB32Vds::DsCmpstoreB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -424,7 +494,11 @@ DsMinNumF32Vds::DsMinNumF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -447,7 +521,11 @@ DsMaxNumF32Vds::DsMaxNumF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -460,7 +538,11 @@ DsNopVds::DsNopVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsNopVds(const MachineInst *opcode) { +DecodeResult decodeDsNopVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_nop", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -483,7 +565,11 @@ DsAddF32Vds::DsAddF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -504,7 +590,11 @@ DsStoreB8Vds::DsStoreB8Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,7 +615,11 @@ DsStoreB16Vds::DsStoreB16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -550,7 +644,11 @@ DsAddRtnU32Vds::DsAddRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -575,7 +673,11 @@ DsSubRtnU32Vds::DsSubRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -600,7 +702,12 @@ DsRsubRtnU32Vds::DsRsubRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -625,7 +732,11 @@ DsIncRtnU32Vds::DsIncRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -650,7 +761,11 @@ DsDecRtnU32Vds::DsDecRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -675,7 +790,11 @@ DsMinRtnI32Vds::DsMinRtnI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -700,7 +819,11 @@ DsMaxRtnI32Vds::DsMaxRtnI32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -725,7 +848,11 @@ DsMinRtnU32Vds::DsMinRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -750,7 +877,11 @@ DsMaxRtnU32Vds::DsMaxRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -775,7 +906,11 @@ DsAndRtnB32Vds::DsAndRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -800,7 +935,11 @@ DsOrRtnB32Vds::DsOrRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -825,7 +964,11 @@ DsXorRtnB32Vds::DsXorRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -852,7 +995,12 @@ DsMskorRtnB32Vds::DsMskorRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -877,7 +1025,12 @@ DsStorexchgRtnB32Vds::DsStorexchgRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -904,7 +1057,12 @@ DsStorexchg2addrRtnB32Vds::DsStorexchg2addrRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_2addr_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -931,7 +1089,13 @@ DsStorexchg2addrStride64RtnB32Vds::DsStorexchg2addrStride64RtnB32Vds(const Machi } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -958,7 +1122,12 @@ DsCmpstoreRtnB32Vds::DsCmpstoreRtnB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_rtn_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -983,7 +1152,12 @@ DsMinNumRtnF32Vds::DsMinNumRtnF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumRtnF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1008,7 +1182,12 @@ DsMaxNumRtnF32Vds::DsMaxNumRtnF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumRtnF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumRtnF32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1025,7 +1204,12 @@ DsSwizzleB32Vds::DsSwizzleB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSwizzleB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSwizzleB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_swizzle_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1046,7 +1230,11 @@ DsLoadB32Vds::DsLoadB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1067,7 +1255,12 @@ DsLoad2addrB32Vds::DsLoad2addrB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1088,7 +1281,12 @@ DsLoad2addrStride64B32Vds::DsLoad2addrStride64B32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_stride64_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1109,7 +1307,11 @@ DsLoadI8Vds::DsLoadI8Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1130,7 +1332,11 @@ DsLoadU8Vds::DsLoadU8Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1151,7 +1357,11 @@ DsLoadI16Vds::DsLoadI16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1172,7 +1382,11 @@ DsLoadU16Vds::DsLoadU16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1193,7 +1407,11 @@ DsConsumeVds::DsConsumeVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsConsumeVds(const MachineInst *opcode) { +DecodeResult decodeDsConsumeVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_consume", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1214,7 +1432,11 @@ DsAppendVds::DsAppendVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAppendVds(const MachineInst *opcode) { +DecodeResult decodeDsAppendVds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_append", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1237,7 +1459,11 @@ DsAddU64Vds::DsAddU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1260,7 +1486,11 @@ DsSubU64Vds::DsSubU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1283,7 +1513,11 @@ DsRsubU64Vds::DsRsubU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1306,7 +1540,11 @@ DsIncU64Vds::DsIncU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1329,7 +1567,11 @@ DsDecU64Vds::DsDecU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1352,7 +1594,11 @@ DsMinI64Vds::DsMinI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1375,7 +1621,11 @@ DsMaxI64Vds::DsMaxI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1398,7 +1648,11 @@ DsMinU64Vds::DsMinU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1421,7 +1675,11 @@ DsMaxU64Vds::DsMaxU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1444,7 +1702,11 @@ DsAndB64Vds::DsAndB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1467,7 +1729,11 @@ DsOrB64Vds::DsOrB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1490,7 +1756,11 @@ DsXorB64Vds::DsXorB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1515,7 +1785,11 @@ DsMskorB64Vds::DsMskorB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1536,7 +1810,11 @@ DsStoreB64Vds::DsStoreB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1559,7 +1837,12 @@ DsStore2addrB64Vds::DsStore2addrB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1582,7 +1865,12 @@ DsStore2addrStride64B64Vds::DsStore2addrStride64B64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStore2addrStride64B64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStore2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1607,7 +1895,12 @@ DsCmpstoreB64Vds::DsCmpstoreB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1630,7 +1923,11 @@ DsMinNumF64Vds::DsMinNumF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1653,7 +1950,11 @@ DsMaxNumF64Vds::DsMaxNumF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumF64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1678,7 +1979,11 @@ DsAddRtnU64Vds::DsAddRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1703,7 +2008,11 @@ DsSubRtnU64Vds::DsSubRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1728,7 +2037,12 @@ DsRsubRtnU64Vds::DsRsubRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsRsubRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsRsubRtnU64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_rsub_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1753,7 +2067,11 @@ DsIncRtnU64Vds::DsIncRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsIncRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsIncRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_inc_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1778,7 +2096,11 @@ DsDecRtnU64Vds::DsDecRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDecRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsDecRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_dec_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1803,7 +2125,11 @@ DsMinRtnI64Vds::DsMinRtnI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1828,7 +2154,11 @@ DsMaxRtnI64Vds::DsMaxRtnI64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnI64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnI64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1853,7 +2183,11 @@ DsMinRtnU64Vds::DsMinRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1878,7 +2212,11 @@ DsMaxRtnU64Vds::DsMaxRtnU64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxRtnU64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxRtnU64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_rtn_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1903,7 +2241,11 @@ DsAndRtnB64Vds::DsAndRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAndRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsAndRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_and_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1928,7 +2270,11 @@ DsOrRtnB64Vds::DsOrRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsOrRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsOrRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_or_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1953,7 +2299,11 @@ DsXorRtnB64Vds::DsXorRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsXorRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsXorRtnB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_xor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1980,7 +2330,12 @@ DsMskorRtnB64Vds::DsMskorRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMskorRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMskorRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_mskor_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2005,7 +2360,12 @@ DsStorexchgRtnB64Vds::DsStorexchgRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchgRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchgRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2032,7 +2392,12 @@ DsStorexchg2addrRtnB64Vds::DsStorexchg2addrRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_storexchg_2addr_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2059,7 +2424,13 @@ DsStorexchg2addrStride64RtnB64Vds::DsStorexchg2addrStride64RtnB64Vds(const Machi } namespace detail { -std::unique_ptr decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsStorexchg2addrStride64RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_storexchg_2addr_stride64_rtn_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2086,7 +2457,12 @@ DsCmpstoreRtnB64Vds::DsCmpstoreRtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsCmpstoreRtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cmpstore_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2111,7 +2487,12 @@ DsMinNumRtnF64Vds::DsMinNumRtnF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMinNumRtnF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMinNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_min_num_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2136,7 +2517,12 @@ DsMaxNumRtnF64Vds::DsMaxNumRtnF64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsMaxNumRtnF64Vds(const MachineInst *opcode) { +DecodeResult decodeDsMaxNumRtnF64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_max_num_rtn_f64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2157,7 +2543,11 @@ DsLoadB64Vds::DsLoadB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB64Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2178,7 +2568,12 @@ DsLoad2addrB64Vds::DsLoad2addrB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2199,7 +2594,12 @@ DsLoad2addrStride64B64Vds::DsLoad2addrStride64B64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoad2addrStride64B64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_2addr_stride64_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2224,7 +2624,11 @@ DsAddRtnF32Vds::DsAddRtnF32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsAddRtnF32Vds(const MachineInst *opcode) { +DecodeResult decodeDsAddRtnF32Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_add_rtn_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2249,7 +2653,12 @@ DsCondxchg32RtnB64Vds::DsCondxchg32RtnB64Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsCondxchg32RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_condxchg32_rtn_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2272,7 +2681,12 @@ DsCondSubU32Vds::DsCondSubU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondSubU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCondSubU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cond_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2295,7 +2709,12 @@ DsSubClampU32Vds::DsSubClampU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubClampU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubClampU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_clamp_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2318,7 +2737,11 @@ DsPkAddF16Vds::DsPkAddF16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddF16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddF16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2341,7 +2764,11 @@ DsPkAddBf16Vds::DsPkAddBf16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddBf16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddBf16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2362,7 +2789,12 @@ DsStoreB8D16HiVds::DsStoreB8D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB8D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2383,7 +2815,12 @@ DsStoreB16D16HiVds::DsStoreB16D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB16D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2404,7 +2841,11 @@ DsLoadU8D16Vds::DsLoadU8D16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2431,7 +2872,12 @@ DsLoadU8D16HiVds::DsLoadU8D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU8D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2458,7 +2904,11 @@ DsLoadI8D16Vds::DsLoadI8D16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i8_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2485,7 +2935,12 @@ DsLoadI8D16HiVds::DsLoadI8D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadI8D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsLoadI8D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_i8_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2512,7 +2967,12 @@ DsLoadU16D16Vds::DsLoadU16D16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u16_d16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2539,7 +2999,12 @@ DsLoadU16D16HiVds::DsLoadU16D16HiVds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadU16D16HiVds(const MachineInst *opcode) { +DecodeResult decodeDsLoadU16D16HiVds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_u16_d16_hi", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2570,7 +3035,12 @@ DsCondSubRtnU32Vds::DsCondSubRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsCondSubRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsCondSubRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_cond_sub_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2595,7 +3065,12 @@ DsSubClampRtnU32Vds::DsSubClampRtnU32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsSubClampRtnU32Vds(const MachineInst *opcode) { +DecodeResult decodeDsSubClampRtnU32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_sub_clamp_rtn_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2620,7 +3095,12 @@ DsPkAddRtnF16Vds::DsPkAddRtnF16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnF16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnF16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_rtn_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2645,7 +3125,12 @@ DsPkAddRtnBf16Vds::DsPkAddRtnBf16Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPkAddRtnBf16Vds(const MachineInst *opcode) { +DecodeResult decodeDsPkAddRtnBf16Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_pk_add_rtn_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2666,7 +3151,12 @@ DsStoreAddtidB32Vds::DsStoreAddtidB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreAddtidB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2687,7 +3177,12 @@ DsLoadAddtidB32Vds::DsLoadAddtidB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadAddtidB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadAddtidB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2706,7 +3201,12 @@ DsPermuteB32Vds::DsPermuteB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsPermuteB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsPermuteB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_permute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2725,7 +3225,12 @@ DsBpermuteB32Vds::DsBpermuteB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_bpermute_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2744,7 +3249,12 @@ DsBpermuteFiB32Vds::DsBpermuteFiB32Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsBpermuteFiB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsBpermuteFiB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_bpermute_fi_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2765,7 +3275,11 @@ DsStoreB96Vds::DsStoreB96Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB96Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2786,7 +3300,11 @@ DsStoreB128Vds::DsStoreB128Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsStoreB128Vds(const MachineInst *opcode) { +DecodeResult decodeDsStoreB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2808,7 +3326,13 @@ DsBvhStackPush4Pop1RtnB32Vds::DsBvhStackPush4Pop1RtnB32Vds(const MachineInst *in } namespace detail { -std::unique_ptr decodeDsBvhStackPush4Pop1RtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsBvhStackPush4Pop1RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_bvh_stack_push4_pop1_rtn_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2830,7 +3354,13 @@ DsBvhStackPush8Pop1RtnB32Vds::DsBvhStackPush8Pop1RtnB32Vds(const MachineInst *in } namespace detail { -std::unique_ptr decodeDsBvhStackPush8Pop1RtnB32Vds(const MachineInst *opcode) { +DecodeResult decodeDsBvhStackPush8Pop1RtnB32Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_bvh_stack_push8_pop1_rtn_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2852,7 +3382,13 @@ DsBvhStackPush8Pop2RtnB64Vds::DsBvhStackPush8Pop2RtnB64Vds(const MachineInst *in } namespace detail { -std::unique_ptr decodeDsBvhStackPush8Pop2RtnB64Vds(const MachineInst *opcode) { +DecodeResult decodeDsBvhStackPush8Pop2RtnB64Vds(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vds::validate_encoding("ds_bvh_stack_push8_pop2_rtn_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2873,7 +3409,11 @@ DsLoadB96Vds::DsLoadB96Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB96Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB96Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2894,7 +3434,11 @@ DsLoadB128Vds::DsLoadB128Vds(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsLoadB128Vds(const MachineInst *opcode) { +DecodeResult decodeDsLoadB128Vds(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vds::validate_encoding( + "ds_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vdsdir.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vdsdir.cpp index 55a66843f729..3df9ee92755f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vdsdir.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vdsdir.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vdsdir.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -29,7 +28,12 @@ DsParamLoadVdsdir::DsParamLoadVdsdir(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsParamLoadVdsdir(const MachineInst *opcode) { +DecodeResult decodeDsParamLoadVdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vdsdir::validate_encoding( + "ds_param_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ DsDirectLoadVdsdir::DsDirectLoadVdsdir(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeDsDirectLoadVdsdir(const MachineInst *opcode) { +DecodeResult decodeDsDirectLoadVdsdir(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vdsdir::validate_encoding( + "ds_direct_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vexport.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vexport.cpp index 37f02fad20bc..ded98200d1bc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vexport.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vexport.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vexport.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -35,7 +34,11 @@ ExportVexport::ExportVexport(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeExportVexport(const MachineInst *opcode) { +DecodeResult decodeExportVexport(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + Result validation = Vexport::validate_encoding( + "export", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vflat.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vflat.cpp index eeb896c267bc..80ff18677cc7 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vflat.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vflat.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vflat.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -37,7 +36,12 @@ FlatLoadU8Vflat::FlatLoadU8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -59,7 +63,12 @@ FlatLoadI8Vflat::FlatLoadI8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,7 +90,12 @@ FlatLoadU16Vflat::FlatLoadU16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadU16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadU16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -103,7 +117,12 @@ FlatLoadI16Vflat::FlatLoadI16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadI16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadI16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -125,7 +144,12 @@ FlatLoadB32Vflat::FlatLoadB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +171,12 @@ FlatLoadB64Vflat::FlatLoadB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +198,12 @@ FlatLoadB96Vflat::FlatLoadB96Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB96Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -191,7 +225,12 @@ FlatLoadB128Vflat::FlatLoadB128Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadB128Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -213,7 +252,12 @@ FlatStoreB8Vflat::FlatStoreB8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -235,7 +279,12 @@ FlatStoreB16Vflat::FlatStoreB16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -257,7 +306,12 @@ FlatStoreB32Vflat::FlatStoreB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -279,7 +333,12 @@ FlatStoreB64Vflat::FlatStoreB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -301,7 +360,12 @@ FlatStoreB96Vflat::FlatStoreB96Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB96Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB96Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -323,7 +387,12 @@ FlatStoreB128Vflat::FlatStoreB128Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreB128Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreB128Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -345,7 +414,12 @@ FlatLoadD16U8Vflat::FlatLoadD16U8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16U8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16U8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -373,7 +447,12 @@ FlatLoadD16I8Vflat::FlatLoadD16I8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16I8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16I8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +480,12 @@ FlatLoadD16B16Vflat::FlatLoadD16B16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16B16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16B16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -429,7 +513,12 @@ FlatLoadD16HiU8Vflat::FlatLoadD16HiU8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiU8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -457,7 +546,12 @@ FlatLoadD16HiI8Vflat::FlatLoadD16HiI8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiI8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -485,7 +579,12 @@ FlatLoadD16HiB16Vflat::FlatLoadD16HiB16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatLoadD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -513,7 +612,12 @@ FlatStoreD16HiB8Vflat::FlatStoreD16HiB8Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB8Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -535,7 +639,12 @@ FlatStoreD16HiB16Vflat::FlatStoreD16HiB16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatStoreD16HiB16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -562,7 +671,12 @@ FlatAtomicSwapB32Vflat::FlatAtomicSwapB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -589,7 +703,12 @@ FlatAtomicCmpswapB32Vflat::FlatAtomicCmpswapB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_cmpswap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -616,7 +735,12 @@ FlatAtomicAddU32Vflat::FlatAtomicAddU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -643,7 +767,12 @@ FlatAtomicSubU32Vflat::FlatAtomicSubU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -670,7 +799,12 @@ FlatAtomicSubClampU32Vflat::FlatAtomicSubClampU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubClampU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_sub_clamp_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -697,7 +831,12 @@ FlatAtomicMinI32Vflat::FlatAtomicMinI32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -724,7 +863,12 @@ FlatAtomicMinU32Vflat::FlatAtomicMinU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -751,7 +895,12 @@ FlatAtomicMaxI32Vflat::FlatAtomicMaxI32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -778,7 +927,12 @@ FlatAtomicMaxU32Vflat::FlatAtomicMaxU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -805,7 +959,12 @@ FlatAtomicAndB32Vflat::FlatAtomicAndB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -832,7 +991,12 @@ FlatAtomicOrB32Vflat::FlatAtomicOrB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -859,7 +1023,12 @@ FlatAtomicXorB32Vflat::FlatAtomicXorB32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -886,7 +1055,12 @@ FlatAtomicIncU32Vflat::FlatAtomicIncU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -913,7 +1087,12 @@ FlatAtomicDecU32Vflat::FlatAtomicDecU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -940,7 +1119,12 @@ FlatAtomicSwapB64Vflat::FlatAtomicSwapB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSwapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -967,7 +1151,12 @@ FlatAtomicCmpswapB64Vflat::FlatAtomicCmpswapB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCmpswapB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_cmpswap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -994,7 +1183,12 @@ FlatAtomicAddU64Vflat::FlatAtomicAddU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1021,7 +1215,12 @@ FlatAtomicSubU64Vflat::FlatAtomicSubU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicSubU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicSubU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1048,7 +1247,12 @@ FlatAtomicMinI64Vflat::FlatAtomicMinI64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinI64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1075,7 +1279,12 @@ FlatAtomicMinU64Vflat::FlatAtomicMinU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1102,7 +1311,12 @@ FlatAtomicMaxI64Vflat::FlatAtomicMaxI64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxI64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1129,7 +1343,12 @@ FlatAtomicMaxU64Vflat::FlatAtomicMaxU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1156,7 +1375,12 @@ FlatAtomicAndB64Vflat::FlatAtomicAndB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAndB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAndB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1183,7 +1407,12 @@ FlatAtomicOrB64Vflat::FlatAtomicOrB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicOrB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicOrB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1210,7 +1439,12 @@ FlatAtomicXorB64Vflat::FlatAtomicXorB64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicXorB64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicXorB64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1237,7 +1471,12 @@ FlatAtomicIncU64Vflat::FlatAtomicIncU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicIncU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicIncU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1264,7 +1503,12 @@ FlatAtomicDecU64Vflat::FlatAtomicDecU64Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicDecU64Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicDecU64Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1291,7 +1535,12 @@ FlatAtomicCondSubU32Vflat::FlatAtomicCondSubU32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicCondSubU32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_cond_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1318,7 +1567,12 @@ FlatAtomicMinNumF32Vflat::FlatAtomicMinNumF32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMinNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_min_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1345,7 +1599,12 @@ FlatAtomicMaxNumF32Vflat::FlatAtomicMaxNumF32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicMaxNumF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_max_num_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1372,7 +1631,12 @@ FlatAtomicAddF32Vflat::FlatAtomicAddF32Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicAddF32Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicAddF32Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1399,7 +1663,12 @@ FlatAtomicPkAddF16Vflat::FlatAtomicPkAddF16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddF16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1426,7 +1695,12 @@ FlatAtomicPkAddBf16Vflat::FlatAtomicPkAddBf16Vflat(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode) { +DecodeResult decodeFlatAtomicPkAddBf16Vflat(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vflat::validate_encoding( + "flat_atomic_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vglobal.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vglobal.cpp index 406734045484..d385dba939ec 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vglobal.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vglobal.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vglobal.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -40,7 +39,12 @@ GlobalLoadU8Vglobal::GlobalLoadU8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadU8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -65,7 +69,12 @@ GlobalLoadI8Vglobal::GlobalLoadI8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadI8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -90,7 +99,12 @@ GlobalLoadU16Vglobal::GlobalLoadU16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadU16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadU16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -115,7 +129,12 @@ GlobalLoadI16Vglobal::GlobalLoadI16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadI16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadI16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -140,7 +159,12 @@ GlobalLoadB32Vglobal::GlobalLoadB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -165,7 +189,12 @@ GlobalLoadB64Vglobal::GlobalLoadB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -190,7 +219,12 @@ GlobalLoadB96Vglobal::GlobalLoadB96Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB96Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +249,12 @@ GlobalLoadB128Vglobal::GlobalLoadB128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -240,7 +279,12 @@ GlobalStoreB8Vglobal::GlobalStoreB8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +309,12 @@ GlobalStoreB16Vglobal::GlobalStoreB16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +339,12 @@ GlobalStoreB32Vglobal::GlobalStoreB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -315,7 +369,12 @@ GlobalStoreB64Vglobal::GlobalStoreB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -340,7 +399,12 @@ GlobalStoreB96Vglobal::GlobalStoreB96Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB96Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB96Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -365,7 +429,12 @@ GlobalStoreB128Vglobal::GlobalStoreB128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -390,7 +459,12 @@ GlobalLoadD16U8Vglobal::GlobalLoadD16U8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16U8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -421,7 +495,12 @@ GlobalLoadD16I8Vglobal::GlobalLoadD16I8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16I8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -452,7 +531,12 @@ GlobalLoadD16B16Vglobal::GlobalLoadD16B16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16B16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -483,7 +567,12 @@ GlobalLoadD16HiU8Vglobal::GlobalLoadD16HiU8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16HiU8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -514,7 +603,12 @@ GlobalLoadD16HiI8Vglobal::GlobalLoadD16HiI8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16HiI8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +639,12 @@ GlobalLoadD16HiB16Vglobal::GlobalLoadD16HiB16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -576,7 +675,12 @@ GlobalStoreD16HiB8Vglobal::GlobalStoreD16HiB8Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreD16HiB8Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_d16_hi_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -601,7 +705,12 @@ GlobalStoreD16HiB16Vglobal::GlobalStoreD16HiB16Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreD16HiB16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_d16_hi_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -623,7 +732,12 @@ GlobalLoadAddtidB32Vglobal::GlobalLoadAddtidB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -645,7 +759,12 @@ GlobalStoreAddtidB32Vglobal::GlobalStoreAddtidB32Vglobal(const MachineInst *inst } namespace detail { -std::unique_ptr decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreAddtidB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_addtid_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -658,7 +777,12 @@ GlobalInvVglobal::GlobalInvVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalInvVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalInvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_inv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -671,7 +795,12 @@ GlobalWbVglobal::GlobalWbVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalWbVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalWbVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_wb", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -701,7 +830,12 @@ GlobalAtomicSwapB32Vglobal::GlobalAtomicSwapB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSwapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_swap_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -731,7 +865,13 @@ GlobalAtomicCmpswapB32Vglobal::GlobalAtomicCmpswapB32Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicCmpswapB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_cmpswap_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -761,7 +901,12 @@ GlobalAtomicAddU32Vglobal::GlobalAtomicAddU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -791,7 +936,12 @@ GlobalAtomicSubU32Vglobal::GlobalAtomicSubU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_sub_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -821,7 +971,13 @@ GlobalAtomicSubClampU32Vglobal::GlobalAtomicSubClampU32Vglobal(const MachineInst } namespace detail { -std::unique_ptr decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSubClampU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_sub_clamp_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -851,7 +1007,12 @@ GlobalAtomicMinI32Vglobal::GlobalAtomicMinI32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -881,7 +1042,12 @@ GlobalAtomicMinU32Vglobal::GlobalAtomicMinU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -911,7 +1077,12 @@ GlobalAtomicMaxI32Vglobal::GlobalAtomicMaxI32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxI32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_i32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -941,7 +1112,12 @@ GlobalAtomicMaxU32Vglobal::GlobalAtomicMaxU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -971,7 +1147,12 @@ GlobalAtomicAndB32Vglobal::GlobalAtomicAndB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAndB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_and_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1001,7 +1182,12 @@ GlobalAtomicOrB32Vglobal::GlobalAtomicOrB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicOrB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_or_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1031,7 +1217,12 @@ GlobalAtomicXorB32Vglobal::GlobalAtomicXorB32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicXorB32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_xor_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1252,12 @@ GlobalAtomicIncU32Vglobal::GlobalAtomicIncU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicIncU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_inc_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1091,7 +1287,12 @@ GlobalAtomicDecU32Vglobal::GlobalAtomicDecU32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicDecU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_dec_u32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1121,7 +1322,12 @@ GlobalAtomicSwapB64Vglobal::GlobalAtomicSwapB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSwapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_swap_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1151,7 +1357,13 @@ GlobalAtomicCmpswapB64Vglobal::GlobalAtomicCmpswapB64Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicCmpswapB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_cmpswap_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1181,7 +1393,12 @@ GlobalAtomicAddU64Vglobal::GlobalAtomicAddU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1211,7 +1428,12 @@ GlobalAtomicSubU64Vglobal::GlobalAtomicSubU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicSubU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_sub_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1241,7 +1463,12 @@ GlobalAtomicMinI64Vglobal::GlobalAtomicMinI64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1271,7 +1498,12 @@ GlobalAtomicMinU64Vglobal::GlobalAtomicMinU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_min_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1301,7 +1533,12 @@ GlobalAtomicMaxI64Vglobal::GlobalAtomicMaxI64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxI64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_i64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1331,7 +1568,12 @@ GlobalAtomicMaxU64Vglobal::GlobalAtomicMaxU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_max_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1361,7 +1603,12 @@ GlobalAtomicAndB64Vglobal::GlobalAtomicAndB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAndB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_and_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1391,7 +1638,12 @@ GlobalAtomicOrB64Vglobal::GlobalAtomicOrB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicOrB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_or_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1421,7 +1673,12 @@ GlobalAtomicXorB64Vglobal::GlobalAtomicXorB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicXorB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_xor_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1451,7 +1708,12 @@ GlobalAtomicIncU64Vglobal::GlobalAtomicIncU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicIncU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_inc_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1743,12 @@ GlobalAtomicDecU64Vglobal::GlobalAtomicDecU64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicDecU64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_dec_u64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1494,7 +1761,12 @@ GlobalWbinvVglobal::GlobalWbinvVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalWbinvVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalWbinvVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_wbinv", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1524,7 +1796,13 @@ GlobalAtomicCondSubU32Vglobal::GlobalAtomicCondSubU32Vglobal(const MachineInst * } namespace detail { -std::unique_ptr decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicCondSubU32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_cond_sub_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1554,7 +1832,13 @@ GlobalAtomicMinNumF32Vglobal::GlobalAtomicMinNumF32Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMinNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_min_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1584,7 +1868,13 @@ GlobalAtomicMaxNumF32Vglobal::GlobalAtomicMaxNumF32Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicMaxNumF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_max_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1611,7 +1901,12 @@ GlobalLoadBlockVglobal::GlobalLoadBlockVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadBlockVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1638,7 +1933,12 @@ GlobalStoreBlockVglobal::GlobalStoreBlockVglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalStoreBlockVglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalStoreBlockVglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_store_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1668,7 +1968,12 @@ GlobalAtomicAddF32Vglobal::GlobalAtomicAddF32Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicAddF32Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_atomic_add_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1693,7 +1998,12 @@ GlobalLoadTrB128Vglobal::GlobalLoadTrB128Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadTrB128Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadTrB128Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_tr_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1718,7 +2028,12 @@ GlobalLoadTrB64Vglobal::GlobalLoadTrB64Vglobal(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeGlobalLoadTrB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalLoadTrB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vglobal::validate_encoding( + "global_load_tr_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1748,7 +2063,13 @@ GlobalAtomicPkAddF16Vglobal::GlobalAtomicPkAddF16Vglobal(const MachineInst *inst } namespace detail { -std::unique_ptr decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicPkAddF16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1778,7 +2099,13 @@ GlobalAtomicPkAddBf16Vglobal::GlobalAtomicPkAddBf16Vglobal(const MachineInst *in } namespace detail { -std::unique_ptr decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicPkAddBf16Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_pk_add_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1808,7 +2135,13 @@ GlobalAtomicOrderedAddB64Vglobal::GlobalAtomicOrderedAddB64Vglobal(const Machine } namespace detail { -std::unique_ptr decodeGlobalAtomicOrderedAddB64Vglobal(const MachineInst *opcode) { +DecodeResult decodeGlobalAtomicOrderedAddB64Vglobal(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vglobal::validate_encoding("global_atomic_ordered_add_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vimage.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vimage.cpp index b32df9066840..24f026be9288 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vimage.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vimage.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vimage.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -27,7 +26,12 @@ ImageLoadVimage::ImageLoadVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadVimage(const MachineInst *opcode) { +DecodeResult decodeImageLoadVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -47,7 +51,12 @@ ImageLoadMipVimage::ImageLoadMipVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipVimage(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_load_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -67,7 +76,12 @@ ImageLoadPckVimage::ImageLoadPckVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckVimage(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_load_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -87,7 +101,12 @@ ImageLoadPckSgnVimage::ImageLoadPckSgnVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadPckSgnVimage(const MachineInst *opcode) { +DecodeResult decodeImageLoadPckSgnVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_load_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -107,7 +126,12 @@ ImageLoadMipPckVimage::ImageLoadMipPckVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckVimage(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_load_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -127,7 +151,12 @@ ImageLoadMipPckSgnVimage::ImageLoadMipPckSgnVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageLoadMipPckSgnVimage(const MachineInst *opcode) { +DecodeResult decodeImageLoadMipPckSgnVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_load_mip_pck_sgn", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -147,7 +176,12 @@ ImageStoreVimage::ImageStoreVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreVimage(const MachineInst *opcode) { +DecodeResult decodeImageStoreVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_store", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -167,7 +201,12 @@ ImageStoreMipVimage::ImageStoreMipVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipVimage(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_store_mip", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -187,7 +226,12 @@ ImageStorePckVimage::ImageStorePckVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStorePckVimage(const MachineInst *opcode) { +DecodeResult decodeImageStorePckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_store_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -207,7 +251,12 @@ ImageStoreMipPckVimage::ImageStoreMipPckVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageStoreMipPckVimage(const MachineInst *opcode) { +DecodeResult decodeImageStoreMipPckVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_store_mip_pck", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -233,7 +282,12 @@ ImageAtomicSwapVimage::ImageAtomicSwapVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSwapVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSwapVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_swap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -259,7 +313,12 @@ ImageAtomicCmpswapVimage::ImageAtomicCmpswapVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicCmpswapVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicCmpswapVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_cmpswap", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -285,7 +344,12 @@ ImageAtomicAddUintVimage::ImageAtomicAddUintVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddUintVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_add_uint", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -311,7 +375,12 @@ ImageAtomicSubUintVimage::ImageAtomicSubUintVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicSubUintVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicSubUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_sub_uint", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +406,12 @@ ImageAtomicMinIntVimage::ImageAtomicMinIntVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicMinIntVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicMinIntVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_min_int", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -363,7 +437,12 @@ ImageAtomicMinUintVimage::ImageAtomicMinUintVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicMinUintVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicMinUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_min_uint", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -389,7 +468,12 @@ ImageAtomicMaxIntVimage::ImageAtomicMaxIntVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicMaxIntVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicMaxIntVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_max_int", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -415,7 +499,12 @@ ImageAtomicMaxUintVimage::ImageAtomicMaxUintVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicMaxUintVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicMaxUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_max_uint", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -441,7 +530,12 @@ ImageAtomicAndVimage::ImageAtomicAndVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAndVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAndVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_and", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -467,7 +561,12 @@ ImageAtomicOrVimage::ImageAtomicOrVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicOrVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicOrVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_or", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -493,7 +592,12 @@ ImageAtomicXorVimage::ImageAtomicXorVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicXorVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicXorVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_xor", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -519,7 +623,12 @@ ImageAtomicIncUintVimage::ImageAtomicIncUintVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicIncUintVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicIncUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_inc_uint", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -545,7 +654,12 @@ ImageAtomicDecUintVimage::ImageAtomicDecUintVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicDecUintVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicDecUintVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_dec_uint", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -565,7 +679,12 @@ ImageGetResinfoVimage::ImageGetResinfoVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetResinfoVimage(const MachineInst *opcode) { +DecodeResult decodeImageGetResinfoVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_get_resinfo", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -585,7 +704,12 @@ ImageBvhIntersectRayVimage::ImageBvhIntersectRayVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageBvhIntersectRayVimage(const MachineInst *opcode) { +DecodeResult decodeImageBvhIntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_bvh_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -605,7 +729,13 @@ ImageBvh64IntersectRayVimage::ImageBvh64IntersectRayVimage(const MachineInst *in } namespace detail { -std::unique_ptr decodeImageBvh64IntersectRayVimage(const MachineInst *opcode) { +DecodeResult decodeImageBvh64IntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vimage::validate_encoding("image_bvh64_intersect_ray", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -626,7 +756,13 @@ ImageBvhDualIntersectRayVimage::ImageBvhDualIntersectRayVimage(const MachineInst } namespace detail { -std::unique_ptr decodeImageBvhDualIntersectRayVimage(const MachineInst *opcode) { +DecodeResult decodeImageBvhDualIntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vimage::validate_encoding("image_bvh_dual_intersect_ray", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -647,7 +783,12 @@ ImageBvh8IntersectRayVimage::ImageBvh8IntersectRayVimage(const MachineInst *inst } namespace detail { -std::unique_ptr decodeImageBvh8IntersectRayVimage(const MachineInst *opcode) { +DecodeResult decodeImageBvh8IntersectRayVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_bvh8_intersect_ray", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -673,7 +814,12 @@ ImageAtomicAddFltVimage::ImageAtomicAddFltVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicAddFltVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicAddFltVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_add_flt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +845,12 @@ ImageAtomicMinFltVimage::ImageAtomicMinFltVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicMinFltVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicMinFltVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_min_flt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -725,7 +876,12 @@ ImageAtomicMaxFltVimage::ImageAtomicMaxFltVimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicMaxFltVimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicMaxFltVimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_max_flt", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -751,7 +907,12 @@ ImageAtomicPkAddF16Vimage::ImageAtomicPkAddF16Vimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicPkAddF16Vimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicPkAddF16Vimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_pk_add_f16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -777,7 +938,12 @@ ImageAtomicPkAddBf16Vimage::ImageAtomicPkAddBf16Vimage(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageAtomicPkAddBf16Vimage(const MachineInst *opcode) { +DecodeResult decodeImageAtomicPkAddBf16Vimage(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vimage::validate_encoding( + "image_atomic_pk_add_bf16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vinterp.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vinterp.cpp index 7be490bbcb15..2bf52019a783 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vinterp.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vinterp.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vinterp.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -28,7 +27,12 @@ VInterpP10F32Vinterp::VInterpP10F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p10_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ VInterpP2F32Vinterp::VInterpP2F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -70,7 +79,12 @@ VInterpP10F16F32Vinterp::VInterpP10F16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10F16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p10_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -91,7 +105,12 @@ VInterpP2F16F32Vinterp::VInterpP2F16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2F16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2F16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -118,7 +137,13 @@ VInterpP10RtzF16F32Vinterp::VInterpP10RtzF16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP10RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vinterp::validate_encoding("v_interp_p10_rtz_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -139,7 +164,12 @@ VInterpP2RtzF16F32Vinterp::VInterpP2RtzF16F32Vinterp(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode) { +DecodeResult decodeVInterpP2RtzF16F32Vinterp(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vinterp::validate_encoding( + "v_interp_p2_rtz_f16_f32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop1.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop1.cpp index d71a2ebea259..1b736c0de350 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop1.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop1.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -23,7 +22,15 @@ VNopVop1::VNopVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop1(const MachineInst *opcode) { +DecodeResult decodeVNopVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_dpp" + : "v_nop_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -64,7 +71,15 @@ VMovB32Vop1::VMovB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_dpp" + : "v_mov_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -81,13 +96,22 @@ VReadfirstlaneB32Vop1::VReadfirstlaneB32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_dpp" + : "v_readfirstlane_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -109,13 +133,21 @@ VCvtI32F64Vop1::VCvtI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_dpp" + : "v_cvt_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -136,13 +168,21 @@ VCvtF64I32Vop1::VCvtF64I32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_dpp" + : "v_cvt_f64_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -183,7 +223,15 @@ VCvtF32I32Vop1::VCvtF32I32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_dpp" + : "v_cvt_f32_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -224,7 +272,15 @@ VCvtF32U32Vop1::VCvtF32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_dpp" + : "v_cvt_f32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -265,7 +321,15 @@ VCvtU32F32Vop1::VCvtU32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_dpp" + : "v_cvt_u32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -306,7 +370,15 @@ VCvtI32F32Vop1::VCvtI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_dpp" + : "v_cvt_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -349,7 +421,15 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_dpp" + : "v_cvt_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -398,7 +478,15 @@ VCvtF32F16Vop1::VCvtF32F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_dpp" + : "v_cvt_f32_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -439,7 +527,16 @@ VCvtNearestI32F32Vop1::VCvtNearestI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_dpp" + : "v_cvt_nearest_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -480,7 +577,16 @@ VCvtFloorI32F32Vop1::VCvtFloorI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_dpp" + : "v_cvt_floor_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -521,7 +627,16 @@ VCvtOffF32I4Vop1::VCvtOffF32I4Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_dpp" + : "v_cvt_off_f32_i4_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -543,13 +658,21 @@ VCvtF32F64Vop1::VCvtF32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_dpp" + : "v_cvt_f32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -570,13 +693,21 @@ VCvtF64F32Vop1::VCvtF64F32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_dpp" + : "v_cvt_f64_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -617,7 +748,16 @@ VCvtF32Ubyte0Vop1::VCvtF32Ubyte0Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_dpp" + : "v_cvt_f32_ubyte0_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -658,7 +798,16 @@ VCvtF32Ubyte1Vop1::VCvtF32Ubyte1Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_dpp" + : "v_cvt_f32_ubyte1_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -699,7 +848,16 @@ VCvtF32Ubyte2Vop1::VCvtF32Ubyte2Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_dpp" + : "v_cvt_f32_ubyte2_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -740,7 +898,16 @@ VCvtF32Ubyte3Vop1::VCvtF32Ubyte3Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_dpp" + : "v_cvt_f32_ubyte3_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -762,13 +929,21 @@ VCvtU32F64Vop1::VCvtU32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_dpp" + : "v_cvt_u32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -789,13 +964,21 @@ VCvtF64U32Vop1::VCvtF64U32Vop1(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_dpp" + : "v_cvt_f64_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -817,13 +1000,21 @@ VTruncF64Vop1::VTruncF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_dpp" + : "v_trunc_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -845,13 +1036,21 @@ VCeilF64Vop1::VCeilF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_dpp" + : "v_ceil_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -873,13 +1072,21 @@ VRndneF64Vop1::VRndneF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_dpp" + : "v_rndne_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -901,13 +1108,21 @@ VFloorF64Vop1::VFloorF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_dpp" + : "v_floor_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -923,7 +1138,15 @@ VPipeflushVop1::VPipeflushVop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop1(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_dpp" + : "v_pipeflush_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -968,7 +1191,15 @@ VMovB16Vop1::VMovB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_dpp" + : "v_mov_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1015,7 +1246,15 @@ VFractF32Vop1::VFractF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_dpp" + : "v_fract_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1056,7 +1295,15 @@ VTruncF32Vop1::VTruncF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_dpp" + : "v_trunc_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1097,7 +1344,15 @@ VCeilF32Vop1::VCeilF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_dpp" + : "v_ceil_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1138,7 +1393,15 @@ VRndneF32Vop1::VRndneF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_dpp" + : "v_rndne_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1179,7 +1442,15 @@ VFloorF32Vop1::VFloorF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_dpp" + : "v_floor_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1220,7 +1491,15 @@ VExpF32Vop1::VExpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_dpp" + : "v_exp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1261,7 +1540,15 @@ VLogF32Vop1::VLogF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_dpp" + : "v_log_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1302,7 +1589,15 @@ VRcpF32Vop1::VRcpF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_dpp" + : "v_rcp_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1343,7 +1638,16 @@ VRcpIflagF32Vop1::VRcpIflagF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_dpp" + : "v_rcp_iflag_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1384,7 +1688,15 @@ VRsqF32Vop1::VRsqF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_dpp" + : "v_rsq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1406,13 +1718,21 @@ VRcpF64Vop1::VRcpF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_dpp" + : "v_rcp_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1434,13 +1754,21 @@ VRsqF64Vop1::VRsqF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_dpp" + : "v_rsq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1481,7 +1809,15 @@ VSqrtF32Vop1::VSqrtF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_dpp" + : "v_sqrt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1503,13 +1839,21 @@ VSqrtF64Vop1::VSqrtF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_dpp" + : "v_sqrt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1550,7 +1894,15 @@ VSinF32Vop1::VSinF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_dpp" + : "v_sin_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1591,7 +1943,15 @@ VCosF32Vop1::VCosF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_dpp" + : "v_cos_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1632,7 +1992,15 @@ VNotB32Vop1::VNotB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_dpp" + : "v_not_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1673,7 +2041,15 @@ VBfrevB32Vop1::VBfrevB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_dpp" + : "v_bfrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1714,7 +2090,15 @@ VClzI32U32Vop1::VClzI32U32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_dpp" + : "v_clz_i32_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1755,7 +2139,15 @@ VCtzI32B32Vop1::VCtzI32B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_dpp" + : "v_ctz_i32_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1796,7 +2188,15 @@ VClsI32Vop1::VClsI32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop1(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_dpp" + : "v_cls_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1818,13 +2218,22 @@ VFrexpExpI32F64Vop1::VFrexpExpI32F64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_dpp" + : "v_frexp_exp_i32_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1846,13 +2255,22 @@ VFrexpMantF64Vop1::VFrexpMantF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_dpp" + : "v_frexp_mant_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1874,13 +2292,21 @@ VFractF64Vop1::VFractF64Vop1(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_dpp" + : "v_fract_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1921,7 +2347,16 @@ VFrexpExpI32F32Vop1::VFrexpExpI32F32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_dpp" + : "v_frexp_exp_i32_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1962,7 +2397,16 @@ VFrexpMantF32Vop1::VFrexpMantF32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_dpp" + : "v_frexp_mant_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2006,7 +2450,16 @@ VMovreldB32Vop1::VMovreldB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_dpp" + : "v_movreld_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2046,7 +2499,16 @@ VMovrelsB32Vop1::VMovrelsB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_dpp" + : "v_movrels_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2086,7 +2548,16 @@ VMovrelsdB32Vop1::VMovrelsdB32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_dpp" + : "v_movrelsd_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2126,7 +2597,16 @@ VMovrelsd2B32Vop1::VMovrelsd2B32Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_dpp" + : "v_movrelsd_2_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2171,7 +2651,15 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_dpp" + : "v_cvt_f16_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2222,7 +2710,15 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_dpp" + : "v_cvt_f16_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2273,7 +2769,15 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_dpp" + : "v_cvt_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2324,7 +2828,15 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_dpp" + : "v_cvt_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2375,7 +2887,15 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_dpp" + : "v_rcp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2426,7 +2946,15 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_dpp" + : "v_sqrt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2477,7 +3005,15 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_dpp" + : "v_rsq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2528,7 +3064,15 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_dpp" + : "v_log_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2579,7 +3123,15 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_dpp" + : "v_exp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2630,7 +3182,16 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_dpp" + : "v_frexp_mant_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2681,7 +3242,16 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_dpp" + : "v_frexp_exp_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2732,7 +3302,15 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_dpp" + : "v_floor_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2783,7 +3361,15 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_dpp" + : "v_ceil_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2834,7 +3420,15 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_dpp" + : "v_trunc_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2885,7 +3479,15 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_dpp" + : "v_rndne_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2936,7 +3538,15 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_dpp" + : "v_fract_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2987,7 +3597,15 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_dpp" + : "v_sin_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3038,7 +3656,15 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_dpp" + : "v_cos_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3087,7 +3713,16 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_dpp" + : "v_sat_pk_u8_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3138,7 +3773,16 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_dpp" + : "v_cvt_norm_i16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3189,7 +3833,16 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_dpp" + : "v_cvt_norm_u16_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3214,13 +3867,21 @@ VSwapB32Vop1::VSwapB32Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwapB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB32Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b32_dpp" + : "v_swap_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3242,13 +3903,21 @@ VSwapB16Vop1::VSwapB16Vop1(const MachineInst *inst) dst_operands_[1] = &src0; num_src_ = 2; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAP_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwapB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwapB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swap_b16_dpp" + : "v_swap_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAP_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3273,13 +3942,22 @@ VPermlane64B32Vop1::VPermlane64B32Vop1(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE64_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane64B32Vop1(const MachineInst *opcode) { +DecodeResult decodeVPermlane64B32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane64_b32_dpp" + : "v_permlane64_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE64_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3300,14 +3978,23 @@ VSwaprelB32Vop1::VSwaprelB32Vop1(const MachineInst *inst) src_operands_[2] = &m0; num_src_ = 3; num_dst_ = 2; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWAPREL_B32 does not support DPP", ""); m0.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVSwaprelB32Vop1(const MachineInst *opcode) { +DecodeResult decodeVSwaprelB32Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swaprel_b32_dpp" + : "v_swaprel_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SWAPREL_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3352,7 +4039,15 @@ VNotB16Vop1::VNotB16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop1(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_dpp" + : "v_not_b16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3401,7 +4096,15 @@ VCvtI32I16Vop1::VCvtI32I16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_dpp" + : "v_cvt_i32_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3444,7 +4147,15 @@ VCvtU32U16Vop1::VCvtU32U16Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_dpp" + : "v_cvt_u32_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3485,7 +4196,15 @@ VCvtF32Fp8Vop1::VCvtF32Fp8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_fp8_dpp" + : "v_cvt_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3526,7 +4245,15 @@ VCvtF32Bf8Vop1::VCvtF32Bf8Vop1(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop1(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_bf8_dpp" + : "v_cvt_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3549,13 +4276,22 @@ VCvtPkF32Fp8Vop1::VCvtPkF32Fp8Vop1(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_fp8_dpp" + : "v_cvt_pk_f32_fp8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3578,13 +4314,22 @@ VCvtPkF32Bf8Vop1::VCvtPkF32Bf8Vop1(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop1(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop1::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_bf8_dpp" + : "v_cvt_pk_f32_bf8_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop2.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop2.cpp index 9dba4ec60834..4e5aa91fe0e0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop2.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop2.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vop2.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -54,7 +53,16 @@ VCndmaskB32Vop2::VCndmaskB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_dpp" + : "v_cndmask_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -78,13 +86,21 @@ VAddF64Vop2::VAddF64Vop2(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAddF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f64_dpp" + : "v_add_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -127,7 +143,15 @@ VAddF32Vop2::VAddF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_dpp" + : "v_add_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -170,7 +194,15 @@ VSubF32Vop2::VSubF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_dpp" + : "v_sub_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -213,7 +245,15 @@ VSubrevF32Vop2::VSubrevF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_dpp" + : "v_subrev_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -237,13 +277,21 @@ VMulF64Vop2::VMulF64Vop2(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f64_dpp" + : "v_mul_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -286,7 +334,16 @@ VMulDx9ZeroF32Vop2::VMulDx9ZeroF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_dpp" + : "v_mul_dx9_zero_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -329,7 +386,15 @@ VMulF32Vop2::VMulF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_dpp" + : "v_mul_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -372,7 +437,15 @@ VMulI32I24Vop2::VMulI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_dpp" + : "v_mul_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -415,7 +488,16 @@ VMulHiI32I24Vop2::VMulHiI32I24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_dpp" + : "v_mul_hi_i32_i24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -458,7 +540,15 @@ VMulU32U24Vop2::VMulU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_dpp" + : "v_mul_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -501,7 +591,16 @@ VMulHiU32U24Vop2::VMulHiU32U24Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_dpp" + : "v_mul_hi_u32_u24_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,13 +624,21 @@ VMinNumF64Vop2::VMinNumF64Vop2(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_NUM_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMinNumF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f64_dpp" + : "v_min_num_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_NUM_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -555,13 +662,21 @@ VMaxNumF64Vop2::VMaxNumF64Vop2(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_NUM_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMaxNumF64Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF64Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f64_dpp" + : "v_max_num_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_NUM_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -604,7 +719,15 @@ VMinI32Vop2::VMinI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_dpp" + : "v_min_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -647,7 +770,15 @@ VMaxI32Vop2::VMaxI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_dpp" + : "v_max_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -690,7 +821,15 @@ VMinU32Vop2::VMinU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_dpp" + : "v_min_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -733,7 +872,15 @@ VMaxU32Vop2::VMaxU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_dpp" + : "v_max_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -776,7 +923,15 @@ VMinNumF32Vop2::VMinNumF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f32_dpp" + : "v_min_num_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -819,7 +974,15 @@ VMaxNumF32Vop2::VMaxNumF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f32_dpp" + : "v_max_num_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -862,7 +1025,16 @@ VLshlrevB32Vop2::VLshlrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_dpp" + : "v_lshlrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -905,7 +1077,16 @@ VLshrrevB32Vop2::VLshrrevB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_dpp" + : "v_lshrrev_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -948,7 +1129,16 @@ VAshrrevI32Vop2::VAshrrevI32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_dpp" + : "v_ashrrev_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -991,7 +1181,15 @@ VAndB32Vop2::VAndB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_dpp" + : "v_and_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1034,7 +1232,15 @@ VOrB32Vop2::VOrB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_dpp" + : "v_or_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1077,7 +1283,15 @@ VXorB32Vop2::VXorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_dpp" + : "v_xor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1120,7 +1334,15 @@ VXnorB32Vop2::VXnorB32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop2(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_dpp" + : "v_xnor_b32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1143,13 +1365,22 @@ VLshlrevB64Vop2::VLshlrevB64Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHLREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop2(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b64_dpp" + : "v_lshlrev_b64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHLREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1198,7 +1429,16 @@ VAddCoCiU32Vop2::VAddCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_dpp" + : "v_add_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1247,7 +1487,16 @@ VSubCoCiU32Vop2::VSubCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_dpp" + : "v_sub_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1296,7 +1545,16 @@ VSubrevCoCiU32Vop2::VSubrevCoCiU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_dpp" + : "v_subrev_co_ci_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1339,7 +1597,15 @@ VAddNcU32Vop2::VAddNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_dpp" + : "v_add_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1382,7 +1648,15 @@ VSubNcU32Vop2::VSubNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_dpp" + : "v_sub_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1425,7 +1699,16 @@ VSubrevNcU32Vop2::VSubrevNcU32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_dpp" + : "v_subrev_nc_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1469,7 +1752,15 @@ VFmacF32Vop2::VFmacF32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_dpp" + : "v_fmac_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1497,14 +1788,22 @@ VFmamkF32Vop2::VFmamkF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F32 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f32_dpp" + : "v_fmamk_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1532,14 +1831,22 @@ VFmaakF32Vop2::VFmaakF32Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F32 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF32Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF32Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f32_dpp" + : "v_fmaak_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1582,7 +1889,16 @@ VCvtPkRtzF16F32Vop2::VCvtPkRtzF16F32Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop2(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_dpp" + : "v_cvt_pk_rtz_f16_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1630,7 +1946,15 @@ VMinNumF16Vop2::VMinNumF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMinNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f16_dpp" + : "v_min_num_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1684,7 +2008,15 @@ VMaxNumF16Vop2::VMaxNumF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f16_dpp" + : "v_max_num_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1738,7 +2070,15 @@ VAddF16Vop2::VAddF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_dpp" + : "v_add_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1792,7 +2132,15 @@ VSubF16Vop2::VSubF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_dpp" + : "v_sub_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1846,7 +2194,15 @@ VSubrevF16Vop2::VSubrevF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_dpp" + : "v_subrev_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1900,7 +2256,15 @@ VMulF16Vop2::VMulF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_dpp" + : "v_mul_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1955,7 +2319,15 @@ VFmacF16Vop2::VFmacF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_dpp" + : "v_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1995,14 +2367,22 @@ VFmamkF16Vop2::VFmamkF16Vop2(const MachineInst *inst) Operand(16, OperandType::OPR_SIMM32, static_cast( (reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAMK_F16 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmamkF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmamkF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmamk_f16_dpp" + : "v_fmamk_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAMK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2041,14 +2421,22 @@ VFmaakF16Vop2::VFmaakF16Vop2(const MachineInst *inst) simm32 = Operand(32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMAAK_F16 does not support DPP", ""); simm32.apply_fieldless_caps(true, false, false); } namespace detail { -std::unique_ptr decodeVFmaakF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVFmaakF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmaak_f16_dpp" + : "v_fmaak_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMAAK_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2102,7 +2490,15 @@ VLdexpF16Vop2::VLdexpF16Vop2(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_dpp" + : "v_ldexp_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2132,13 +2528,21 @@ VPkFmacF16Vop2::VPkFmacF16Vop2(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMAC_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkFmacF16Vop2(const MachineInst *opcode) { +DecodeResult decodeVPkFmacF16Vop2(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop2::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fmac_f16_dpp" + : "v_pk_fmac_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PK_FMAC_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3.cpp index 1076fc85a138..4808fe37cb18 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -24,7 +23,15 @@ VNopVop3::VNopVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNopVop3(const MachineInst *opcode) { +DecodeResult decodeVNopVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_nop_e64_dpp" + : "v_nop", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -65,7 +72,15 @@ VMovB32Vop3::VMovB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b32_e64_dpp" + : "v_mov_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -82,13 +97,22 @@ VReadfirstlaneB32Vop3::VReadfirstlaneB32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READFIRSTLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadfirstlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadfirstlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readfirstlane_b32_e64_dpp" + : "v_readfirstlane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READFIRSTLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -110,13 +134,21 @@ VCvtI32F64Vop3::VCvtI32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f64_e64_dpp" + : "v_cvt_i32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -137,13 +169,21 @@ VCvtF64I32Vop3::VCvtF64I32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_i32_e64_dpp" + : "v_cvt_f64_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -184,7 +224,15 @@ VCvtF32I32Vop3::VCvtF32I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_i32_e64_dpp" + : "v_cvt_f32_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -225,7 +273,15 @@ VCvtF32U32Vop3::VCvtF32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_u32_e64_dpp" + : "v_cvt_f32_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -266,7 +322,15 @@ VCvtU32F32Vop3::VCvtU32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f32_e64_dpp" + : "v_cvt_u32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +371,15 @@ VCvtI32F32Vop3::VCvtI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_f32_e64_dpp" + : "v_cvt_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -348,7 +420,15 @@ VCvtF16F32Vop3::VCvtF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_f32_e64_dpp" + : "v_cvt_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -399,7 +479,15 @@ VCvtF32F16Vop3::VCvtF32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f16_e64_dpp" + : "v_cvt_f32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -440,7 +528,16 @@ VCvtNearestI32F32Vop3::VCvtNearestI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNearestI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNearestI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_nearest_i32_f32_e64_dpp" + : "v_cvt_nearest_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -481,7 +578,16 @@ VCvtFloorI32F32Vop3::VCvtFloorI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtFloorI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtFloorI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_floor_i32_f32_e64_dpp" + : "v_cvt_floor_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -522,7 +628,16 @@ VCvtOffF32I4Vop3::VCvtOffF32I4Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtOffF32I4Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtOffF32I4Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_off_f32_i4_e64_dpp" + : "v_cvt_off_f32_i4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -544,13 +659,21 @@ VCvtF32F64Vop3::VCvtF32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_f64_e64_dpp" + : "v_cvt_f32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -571,13 +694,21 @@ VCvtF64F32Vop3::VCvtF64F32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64F32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_f32_e64_dpp" + : "v_cvt_f64_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -618,7 +749,16 @@ VCvtF32Ubyte0Vop3::VCvtF32Ubyte0Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte0Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte0_e64_dpp" + : "v_cvt_f32_ubyte0", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -659,7 +799,16 @@ VCvtF32Ubyte1Vop3::VCvtF32Ubyte1Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte1Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte1_e64_dpp" + : "v_cvt_f32_ubyte1", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -700,7 +849,16 @@ VCvtF32Ubyte2Vop3::VCvtF32Ubyte2Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte2Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte2_e64_dpp" + : "v_cvt_f32_ubyte2", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -741,7 +899,16 @@ VCvtF32Ubyte3Vop3::VCvtF32Ubyte3Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Ubyte3Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_ubyte3_e64_dpp" + : "v_cvt_f32_ubyte3", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -763,13 +930,21 @@ VCvtU32F64Vop3::VCvtU32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_U32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtU32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32F64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_f64_e64_dpp" + : "v_cvt_u32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_U32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -790,13 +965,21 @@ VCvtF64U32Vop3::VCvtF64U32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_F64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtF64U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF64U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f64_u32_e64_dpp" + : "v_cvt_f64_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_F64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -818,13 +1001,21 @@ VTruncF64Vop3::VTruncF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRUNC_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTruncF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f64_e64_dpp" + : "v_trunc_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRUNC_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -846,13 +1037,21 @@ VCeilF64Vop3::VCeilF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CEIL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCeilF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f64_e64_dpp" + : "v_ceil_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CEIL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -874,13 +1073,21 @@ VRndneF64Vop3::VRndneF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RNDNE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRndneF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f64_e64_dpp" + : "v_rndne_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RNDNE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -902,13 +1109,21 @@ VFloorF64Vop3::VFloorF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FLOOR_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFloorF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f64_e64_dpp" + : "v_floor_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FLOOR_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -924,7 +1139,15 @@ VPipeflushVop3::VPipeflushVop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPipeflushVop3(const MachineInst *opcode) { +DecodeResult decodeVPipeflushVop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pipeflush_e64_dpp" + : "v_pipeflush", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -969,7 +1192,15 @@ VMovB16Vop3::VMovB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mov_b16_e64_dpp" + : "v_mov_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1016,7 +1247,15 @@ VFractF32Vop3::VFractF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f32_e64_dpp" + : "v_fract_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1057,7 +1296,15 @@ VTruncF32Vop3::VTruncF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f32_e64_dpp" + : "v_trunc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1098,7 +1345,15 @@ VCeilF32Vop3::VCeilF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f32_e64_dpp" + : "v_ceil_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1139,7 +1394,15 @@ VRndneF32Vop3::VRndneF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f32_e64_dpp" + : "v_rndne_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1180,7 +1443,15 @@ VFloorF32Vop3::VFloorF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f32_e64_dpp" + : "v_floor_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1221,7 +1492,15 @@ VExpF32Vop3::VExpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f32_e64_dpp" + : "v_exp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1262,7 +1541,15 @@ VLogF32Vop3::VLogF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f32_e64_dpp" + : "v_log_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1303,7 +1590,15 @@ VRcpF32Vop3::VRcpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f32_e64_dpp" + : "v_rcp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1344,7 +1639,16 @@ VRcpIflagF32Vop3::VRcpIflagF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpIflagF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpIflagF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_iflag_f32_e64_dpp" + : "v_rcp_iflag_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1385,7 +1689,15 @@ VRsqF32Vop3::VRsqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f32_e64_dpp" + : "v_rsq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1407,13 +1719,21 @@ VRcpF64Vop3::VRcpF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RCP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRcpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f64_e64_dpp" + : "v_rcp_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RCP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1435,13 +1755,21 @@ VRsqF64Vop3::VRsqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_RSQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVRsqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f64_e64_dpp" + : "v_rsq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_RSQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1482,7 +1810,15 @@ VSqrtF32Vop3::VSqrtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f32_e64_dpp" + : "v_sqrt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1504,13 +1840,21 @@ VSqrtF64Vop3::VSqrtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SQRT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSqrtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f64_e64_dpp" + : "v_sqrt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_SQRT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1551,7 +1895,15 @@ VSinF32Vop3::VSinF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f32_e64_dpp" + : "v_sin_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1592,7 +1944,15 @@ VCosF32Vop3::VCosF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f32_e64_dpp" + : "v_cos_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1633,7 +1993,15 @@ VNotB32Vop3::VNotB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b32_e64_dpp" + : "v_not_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1674,7 +2042,15 @@ VBfrevB32Vop3::VBfrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfrevB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfrev_b32_e64_dpp" + : "v_bfrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1715,7 +2091,15 @@ VClzI32U32Vop3::VClzI32U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClzI32U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClzI32U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_clz_i32_u32_e64_dpp" + : "v_clz_i32_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1756,7 +2140,15 @@ VCtzI32B32Vop3::VCtzI32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCtzI32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCtzI32B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ctz_i32_b32_e64_dpp" + : "v_ctz_i32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1797,7 +2189,15 @@ VClsI32Vop3::VClsI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVClsI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVClsI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cls_i32_e64_dpp" + : "v_cls_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1819,13 +2219,22 @@ VFrexpExpI32F64Vop3::VFrexpExpI32F64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_EXP_I32_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpExpI32F64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f64_e64_dpp" + : "v_frexp_exp_i32_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_EXP_I32_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1847,13 +2256,22 @@ VFrexpMantF64Vop3::VFrexpMantF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FREXP_MANT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFrexpMantF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f64_e64_dpp" + : "v_frexp_mant_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FREXP_MANT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1875,13 +2293,21 @@ VFractF64Vop3::VFractF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FRACT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFractF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f64_e64_dpp" + : "v_fract_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FRACT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1922,7 +2348,16 @@ VFrexpExpI32F32Vop3::VFrexpExpI32F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI32F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI32F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i32_f32_e64_dpp" + : "v_frexp_exp_i32_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1963,7 +2398,16 @@ VFrexpMantF32Vop3::VFrexpMantF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f32_e64_dpp" + : "v_frexp_mant_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2007,7 +2451,16 @@ VMovreldB32Vop3::VMovreldB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovreldB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovreldB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movreld_b32_e64_dpp" + : "v_movreld_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2047,7 +2500,16 @@ VMovrelsB32Vop3::VMovrelsB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrels_b32_e64_dpp" + : "v_movrels_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2087,7 +2549,16 @@ VMovrelsdB32Vop3::VMovrelsdB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsdB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsdB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_b32_e64_dpp" + : "v_movrelsd_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2127,7 +2598,16 @@ VMovrelsd2B32Vop3::VMovrelsd2B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMovrelsd2B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMovrelsd2B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_movrelsd_2_b32_e64_dpp" + : "v_movrelsd_2_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2172,7 +2652,15 @@ VCvtF16U16Vop3::VCvtF16U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_u16_e64_dpp" + : "v_cvt_f16_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2223,7 +2711,15 @@ VCvtF16I16Vop3::VCvtF16I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF16I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF16I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f16_i16_e64_dpp" + : "v_cvt_f16_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2274,7 +2770,15 @@ VCvtU16F16Vop3::VCvtU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u16_f16_e64_dpp" + : "v_cvt_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2325,7 +2829,15 @@ VCvtI16F16Vop3::VCvtI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI16F16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i16_f16_e64_dpp" + : "v_cvt_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2376,7 +2888,15 @@ VRcpF16Vop3::VRcpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rcp_f16_e64_dpp" + : "v_rcp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2427,7 +2947,15 @@ VSqrtF16Vop3::VSqrtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sqrt_f16_e64_dpp" + : "v_sqrt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2478,7 +3006,15 @@ VRsqF16Vop3::VRsqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rsq_f16_e64_dpp" + : "v_rsq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2529,7 +3065,15 @@ VLogF16Vop3::VLogF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_log_f16_e64_dpp" + : "v_log_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2580,7 +3124,15 @@ VExpF16Vop3::VExpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_exp_f16_e64_dpp" + : "v_exp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2631,7 +3183,16 @@ VFrexpMantF16Vop3::VFrexpMantF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpMantF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpMantF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_mant_f16_e64_dpp" + : "v_frexp_mant_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2682,7 +3243,16 @@ VFrexpExpI16F16Vop3::VFrexpExpI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFrexpExpI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFrexpExpI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_frexp_exp_i16_f16_e64_dpp" + : "v_frexp_exp_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2733,7 +3303,15 @@ VFloorF16Vop3::VFloorF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFloorF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFloorF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_floor_f16_e64_dpp" + : "v_floor_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2784,7 +3362,15 @@ VCeilF16Vop3::VCeilF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCeilF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCeilF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ceil_f16_e64_dpp" + : "v_ceil_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2835,7 +3421,15 @@ VTruncF16Vop3::VTruncF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVTruncF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVTruncF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trunc_f16_e64_dpp" + : "v_trunc_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2886,7 +3480,15 @@ VRndneF16Vop3::VRndneF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVRndneF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVRndneF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_rndne_f16_e64_dpp" + : "v_rndne_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2937,7 +3539,15 @@ VFractF16Vop3::VFractF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFractF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFractF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fract_f16_e64_dpp" + : "v_fract_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2988,7 +3598,15 @@ VSinF16Vop3::VSinF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSinF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSinF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sin_f16_e64_dpp" + : "v_sin_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3039,7 +3657,15 @@ VCosF16Vop3::VCosF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCosF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCosF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cos_f16_e64_dpp" + : "v_cos_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3086,7 +3712,16 @@ VSatPkU8I16Vop3::VSatPkU8I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSatPkU8I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSatPkU8I16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sat_pk_u8_i16_e64_dpp" + : "v_sat_pk_u8_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3137,7 +3772,16 @@ VCvtNormI16F16Vop3::VCvtNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_i16_f16_e64_dpp" + : "v_cvt_norm_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3188,7 +3832,16 @@ VCvtNormU16F16Vop3::VCvtNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_norm_u16_f16_e64_dpp" + : "v_cvt_norm_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3239,7 +3892,15 @@ VNotB16Vop3::VNotB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVNotB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVNotB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_not_b16_e64_dpp" + : "v_not_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3290,7 +3951,15 @@ VCvtI32I16Vop3::VCvtI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_i32_i16_e64_dpp" + : "v_cvt_i32_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3335,7 +4004,15 @@ VCvtU32U16Vop3::VCvtU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_u32_u16_e64_dpp" + : "v_cvt_u32_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3376,7 +4053,15 @@ VCvtF32Fp8Vop3::VCvtF32Fp8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Fp8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_fp8_e64_dpp" + : "v_cvt_f32_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3417,7 +4102,15 @@ VCvtF32Bf8Vop3::VCvtF32Bf8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtF32Bf8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_f32_bf8_e64_dpp" + : "v_cvt_f32_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3442,13 +4135,22 @@ VCvtPkF32Fp8Vop3::VCvtPkF32Fp8Vop3(const MachineInst *inst) (((amdgpu::vop3_opsel(inst_) >> 0) & 1u) * 16u)) & 0xFFFFu), true); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Fp8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_fp8_e64_dpp" + : "v_cvt_pk_f32_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3473,13 +4175,22 @@ VCvtPkF32Bf8Vop3::VCvtPkF32Bf8Vop3(const MachineInst *inst) (((amdgpu::vop3_opsel(inst_) >> 0) & 1u) * 16u)) & 0xFFFFu), true); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CVT_PK_F32_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkF32Bf8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_f32_bf8_e64_dpp" + : "v_cvt_pk_f32_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CVT_PK_F32_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3528,7 +4239,16 @@ VCndmaskB32Vop3::VCndmaskB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b32_e64_dpp" + : "v_cndmask_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3557,13 +4277,21 @@ VAddF64Vop3::VAddF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ADD_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAddF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f64_e64_dpp" + : "v_add_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ADD_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3610,7 +4338,15 @@ VAddF32Vop3::VAddF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f32_e64_dpp" + : "v_add_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3657,7 +4393,15 @@ VSubF32Vop3::VSubF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f32_e64_dpp" + : "v_sub_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3704,7 +4448,15 @@ VSubrevF32Vop3::VSubrevF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f32_e64_dpp" + : "v_subrev_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3733,13 +4485,21 @@ VMulF64Vop3::VMulF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f64_e64_dpp" + : "v_mul_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3786,7 +4546,16 @@ VMulDx9ZeroF32Vop3::VMulDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_dx9_zero_f32_e64_dpp" + : "v_mul_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3833,7 +4602,15 @@ VMulF32Vop3::VMulF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f32_e64_dpp" + : "v_mul_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3880,7 +4657,15 @@ VMulI32I24Vop3::VMulI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_i32_i24_e64_dpp" + : "v_mul_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3927,7 +4712,16 @@ VMulHiI32I24Vop3::VMulHiI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32I24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_i24_e64_dpp" + : "v_mul_hi_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3974,7 +4768,15 @@ VMulU32U24Vop3::VMulU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_u32_u24_e64_dpp" + : "v_mul_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4021,7 +4823,16 @@ VMulHiU32U24Vop3::VMulHiU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulHiU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32U24Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_u24_e64_dpp" + : "v_mul_hi_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4050,13 +4861,21 @@ VMinNumF64Vop3::VMinNumF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MIN_NUM_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMinNumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f64_e64_dpp" + : "v_min_num_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MIN_NUM_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4085,13 +4904,21 @@ VMaxNumF64Vop3::VMaxNumF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAX_NUM_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMaxNumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f64_e64_dpp" + : "v_max_num_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAX_NUM_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4138,7 +4965,15 @@ VMinI32Vop3::VMinI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i32_e64_dpp" + : "v_min_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4185,7 +5020,15 @@ VMaxI32Vop3::VMaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i32_e64_dpp" + : "v_max_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4232,7 +5075,15 @@ VMinU32Vop3::VMinU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u32_e64_dpp" + : "v_min_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4279,7 +5130,15 @@ VMaxU32Vop3::VMaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u32_e64_dpp" + : "v_max_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4326,7 +5185,15 @@ VMinNumF32Vop3::VMinNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f32_e64_dpp" + : "v_min_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4373,7 +5240,15 @@ VMaxNumF32Vop3::VMaxNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f32_e64_dpp" + : "v_max_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4420,7 +5295,16 @@ VLshlrevB32Vop3::VLshlrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b32_e64_dpp" + : "v_lshlrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4467,7 +5351,16 @@ VLshrrevB32Vop3::VLshrrevB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b32_e64_dpp" + : "v_lshrrev_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4514,7 +5407,16 @@ VAshrrevI32Vop3::VAshrrevI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i32_e64_dpp" + : "v_ashrrev_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4561,7 +5463,15 @@ VAndB32Vop3::VAndB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b32_e64_dpp" + : "v_and_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4608,7 +5518,15 @@ VOrB32Vop3::VOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b32_e64_dpp" + : "v_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4655,7 +5573,15 @@ VXorB32Vop3::VXorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b32_e64_dpp" + : "v_xor_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4702,7 +5628,15 @@ VXnorB32Vop3::VXnorB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXnorB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXnorB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xnor_b32_e64_dpp" + : "v_xnor_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4730,13 +5664,22 @@ VLshlrevB64Vop3::VLshlrevB64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHLREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshlrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b64_e64_dpp" + : "v_lshlrev_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHLREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4783,7 +5726,15 @@ VAddNcU32Vop3::VAddNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u32_e64_dpp" + : "v_add_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4830,7 +5781,15 @@ VSubNcU32Vop3::VSubNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u32_e64_dpp" + : "v_sub_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4877,7 +5836,16 @@ VSubrevNcU32Vop3::VSubrevNcU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevNcU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevNcU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_nc_u32_e64_dpp" + : "v_subrev_nc_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4925,7 +5893,15 @@ VFmacF32Vop3::VFmacF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f32_e64_dpp" + : "v_fmac_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4972,7 +5948,16 @@ VCvtPkRtzF16F32Vop3::VCvtPkRtzF16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkRtzF16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_rtz_f16_f32_e64_dpp" + : "v_cvt_pk_rtz_f16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5027,7 +6012,15 @@ VMinNumF16Vop3::VMinNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_num_f16_e64_dpp" + : "v_min_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5088,7 +6081,15 @@ VMaxNumF16Vop3::VMaxNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxNumF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_num_f16_e64_dpp" + : "v_max_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5149,7 +6150,15 @@ VAddF16Vop3::VAddF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_f16_e64_dpp" + : "v_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5210,7 +6219,15 @@ VSubF16Vop3::VSubF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_f16_e64_dpp" + : "v_sub_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5271,7 +6288,15 @@ VSubrevF16Vop3::VSubrevF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubrevF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_f16_e64_dpp" + : "v_subrev_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5332,7 +6357,15 @@ VMulF16Vop3::VMulF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_f16_e64_dpp" + : "v_mul_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5394,7 +6427,15 @@ VFmacF16Vop3::VFmacF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmacF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmacF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fmac_f16_e64_dpp" + : "v_fmac_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5455,7 +6496,15 @@ VLdexpF16Vop3::VLdexpF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f16_e64_dpp" + : "v_ldexp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5514,7 +6563,16 @@ VFmaDx9ZeroF32Vop3::VFmaDx9ZeroF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaDx9ZeroF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_dx9_zero_f32_e64_dpp" + : "v_fma_dx9_zero_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5567,7 +6625,15 @@ VMadI32I24Vop3::VMadI32I24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i24_e64_dpp" + : "v_mad_i32_i24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5620,7 +6686,15 @@ VMadU32U24Vop3::VMadU32U24Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U24Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U24Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u24_e64_dpp" + : "v_mad_u32_u24", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5673,7 +6747,15 @@ VCubeidF32Vop3::VCubeidF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubeidF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubeidF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubeid_f32_e64_dpp" + : "v_cubeid_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5726,7 +6808,15 @@ VCubescF32Vop3::VCubescF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubescF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubescF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubesc_f32_e64_dpp" + : "v_cubesc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5779,7 +6869,15 @@ VCubetcF32Vop3::VCubetcF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubetcF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubetcF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubetc_f32_e64_dpp" + : "v_cubetc_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5832,7 +6930,15 @@ VCubemaF32Vop3::VCubemaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCubemaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCubemaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cubema_f32_e64_dpp" + : "v_cubema_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5885,7 +6991,15 @@ VBfeU32Vop3::VBfeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_u32_e64_dpp" + : "v_bfe_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5938,7 +7052,15 @@ VBfeI32Vop3::VBfeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfe_i32_e64_dpp" + : "v_bfe_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5991,7 +7113,15 @@ VBfiB32Vop3::VBfiB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfiB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfiB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfi_b32_e64_dpp" + : "v_bfi_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6044,7 +7174,15 @@ VFmaF32Vop3::VFmaF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f32_e64_dpp" + : "v_fma_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6080,13 +7218,21 @@ VFmaF64Vop3::VFmaF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_FMA_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVFmaF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f64_e64_dpp" + : "v_fma_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_FMA_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6139,7 +7285,15 @@ VLerpU8Vop3::VLerpU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLerpU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVLerpU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lerp_u8_e64_dpp" + : "v_lerp_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6196,7 +7350,16 @@ VAlignbitB32Vop3::VAlignbitB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbitB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbitB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbit_b32_e64_dpp" + : "v_alignbit_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6253,7 +7416,16 @@ VAlignbyteB32Vop3::VAlignbyteB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAlignbyteB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAlignbyteB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_alignbyte_b32_e64_dpp" + : "v_alignbyte_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6306,7 +7478,15 @@ VMullitF32Vop3::VMullitF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMullitF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMullitF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mullit_f32_e64_dpp" + : "v_mullit_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6359,7 +7539,15 @@ VMin3I32Vop3::VMin3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i32_e64_dpp" + : "v_min3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6412,7 +7600,15 @@ VMin3U32Vop3::VMin3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u32_e64_dpp" + : "v_min3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6465,7 +7661,15 @@ VMax3I32Vop3::VMax3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i32_e64_dpp" + : "v_max3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6518,7 +7722,15 @@ VMax3U32Vop3::VMax3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u32_e64_dpp" + : "v_max3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6571,7 +7783,15 @@ VMed3I32Vop3::VMed3I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i32_e64_dpp" + : "v_med3_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6624,7 +7844,15 @@ VMed3U32Vop3::VMed3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u32_e64_dpp" + : "v_med3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6677,7 +7905,15 @@ VSadU8Vop3::VSadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u8_e64_dpp" + : "v_sad_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6730,7 +7966,15 @@ VSadHiU8Vop3::VSadHiU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadHiU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadHiU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_hi_u8_e64_dpp" + : "v_sad_hi_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6783,7 +8027,15 @@ VSadU16Vop3::VSadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u16_e64_dpp" + : "v_sad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6836,7 +8088,15 @@ VSadU32Vop3::VSadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sad_u32_e64_dpp" + : "v_sad_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6889,7 +8149,16 @@ VCvtPkU8F32Vop3::VCvtPkU8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u8_f32_e64_dpp" + : "v_cvt_pk_u8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6922,13 +8191,22 @@ VDivFixupF32Vop3::VDivFixupF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivFixupF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f32_e64_dpp" + : "v_div_fixup_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6964,13 +8242,22 @@ VDivFixupF64Vop3::VDivFixupF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FIXUP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivFixupF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f64_e64_dpp" + : "v_div_fixup_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FIXUP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7023,7 +8310,16 @@ VMin3NumF32Vop3::VMin3NumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3NumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3NumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_num_f32_e64_dpp" + : "v_min3_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7076,7 +8372,16 @@ VMax3NumF32Vop3::VMax3NumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3NumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3NumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_num_f32_e64_dpp" + : "v_max3_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7141,7 +8446,16 @@ VMin3NumF16Vop3::VMin3NumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3NumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3NumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_num_f16_e64_dpp" + : "v_min3_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7212,7 +8526,16 @@ VMax3NumF16Vop3::VMax3NumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3NumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3NumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_num_f16_e64_dpp" + : "v_max3_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7271,7 +8594,16 @@ VMinimum3F32Vop3::VMinimum3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimum3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum3_f32_e64_dpp" + : "v_minimum3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7324,7 +8656,16 @@ VMaximum3F32Vop3::VMaximum3F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximum3F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximum3F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum3_f32_e64_dpp" + : "v_maximum3_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7389,7 +8730,16 @@ VMinimum3F16Vop3::VMinimum3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimum3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum3_f16_e64_dpp" + : "v_minimum3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7460,7 +8810,16 @@ VMaximum3F16Vop3::VMaximum3F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximum3F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximum3F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum3_f16_e64_dpp" + : "v_maximum3_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7519,7 +8878,16 @@ VMed3NumF32Vop3::VMed3NumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3NumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3NumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_num_f32_e64_dpp" + : "v_med3_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7584,7 +8952,16 @@ VMed3NumF16Vop3::VMed3NumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3NumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3NumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_num_f16_e64_dpp" + : "v_med3_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7625,14 +9002,23 @@ VDivFmasF32Vop3::VDivFmasF32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F32 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVDivFmasF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f32_e64_dpp" + : "v_div_fmas_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7670,14 +9056,23 @@ VDivFmasF64Vop3::VDivFmasF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_FMAS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVDivFmasF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFmasF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fmas_f64_e64_dpp" + : "v_div_fmas_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_DIV_FMAS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7730,7 +9125,15 @@ VMsadU8Vop3::VMsadU8Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMsadU8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMsadU8Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_msad_u8_e64_dpp" + : "v_msad_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7765,13 +9168,22 @@ VQsadPkU16U8Vop3::VQsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_QSAD_PK_U16_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVQsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVQsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_qsad_pk_u16_u8_e64_dpp" + : "v_qsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_QSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7806,13 +9218,22 @@ VMqsadPkU16U8Vop3::VMqsadPkU16U8Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_PK_U16_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMqsadPkU16U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadPkU16U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_pk_u16_u8_e64_dpp" + : "v_mqsad_pk_u16_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_PK_U16_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7842,13 +9263,22 @@ VMqsadU32U8Vop3::VMqsadU32U8Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MQSAD_U32_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMqsadU32U8Vop3(const MachineInst *opcode) { +DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mqsad_u32_u8_e64_dpp" + : "v_mqsad_u32_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MQSAD_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -7901,7 +9331,15 @@ VXor3B32Vop3::VXor3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXor3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXor3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor3_b32_e64_dpp" + : "v_xor3_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -7966,7 +9404,15 @@ VMadU16Vop3::VMadU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u16_e64_dpp" + : "v_mad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8025,7 +9471,15 @@ VPermB32Vop3::VPermB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPermB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_perm_b32_e64_dpp" + : "v_perm_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8078,7 +9532,15 @@ VXadU32Vop3::VXadU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXadU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVXadU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xad_u32_e64_dpp" + : "v_xad_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8131,7 +9593,16 @@ VLshlAddU32Vop3::VLshlAddU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlAddU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlAddU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_add_u32_e64_dpp" + : "v_lshl_add_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8184,7 +9655,16 @@ VAddLshlU32Vop3::VAddLshlU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddLshlU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddLshlU32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_lshl_u32_e64_dpp" + : "v_add_lshl_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8249,7 +9729,15 @@ VFmaF16Vop3::VFmaF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVFmaF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_f16_e64_dpp" + : "v_fma_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8320,7 +9808,15 @@ VMin3I16Vop3::VMin3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_i16_e64_dpp" + : "v_min3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8391,7 +9887,15 @@ VMin3U16Vop3::VMin3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMin3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMin3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min3_u16_e64_dpp" + : "v_min3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8462,7 +9966,15 @@ VMax3I16Vop3::VMax3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_i16_e64_dpp" + : "v_max3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8533,7 +10045,15 @@ VMax3U16Vop3::VMax3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMax3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMax3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max3_u16_e64_dpp" + : "v_max3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8604,7 +10124,15 @@ VMed3I16Vop3::VMed3I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_i16_e64_dpp" + : "v_med3_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8675,7 +10203,15 @@ VMed3U16Vop3::VMed3U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMed3U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMed3U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_med3_u16_e64_dpp" + : "v_med3_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8746,7 +10282,15 @@ VMadI16Vop3::VMadI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i16_e64_dpp" + : "v_mad_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8817,7 +10361,16 @@ VDivFixupF16Vop3::VDivFixupF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDivFixupF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDivFixupF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_fixup_f16_e64_dpp" + : "v_div_fixup_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8876,7 +10429,15 @@ VAdd3U32Vop3::VAdd3U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAdd3U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAdd3U32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add3_u32_e64_dpp" + : "v_add3_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8929,7 +10490,15 @@ VLshlOrB32Vop3::VLshlOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshl_or_b32_e64_dpp" + : "v_lshl_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -8982,7 +10551,15 @@ VAndOrB32Vop3::VAndOrB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndOrB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndOrB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_or_b32_e64_dpp" + : "v_and_or_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9035,7 +10612,15 @@ VOr3B32Vop3::VOr3B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOr3B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVOr3B32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or3_b32_e64_dpp" + : "v_or3_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9096,7 +10681,15 @@ VMadU32U16Vop3::VMadU32U16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadU32U16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadU32U16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_u32_u16_e64_dpp" + : "v_mad_u32_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9157,7 +10750,15 @@ VMadI32I16Vop3::VMadI32I16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMadI32I16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMadI32I16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_i32_i16_e64_dpp" + : "v_mad_i32_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9186,13 +10787,22 @@ VPermlane16B32Vop3::VPermlane16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_b32_e64_dpp" + : "v_permlane16_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -9221,13 +10831,22 @@ VPermlanex16B32Vop3::VPermlanex16B32Vop3(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANEX16_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlanex16B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlanex16_b32_e64_dpp" + : "v_permlanex16_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANEX16_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -9284,7 +10903,16 @@ VCndmaskB16Vop3::VCndmaskB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCndmaskB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCndmaskB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cndmask_b16_e64_dpp" + : "v_cndmask_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9343,7 +10971,15 @@ VMaxminU32Vop3::VMaxminU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_u32_e64_dpp" + : "v_maxmin_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9396,7 +11032,15 @@ VMinmaxU32Vop3::VMinmaxU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_u32_e64_dpp" + : "v_minmax_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9449,7 +11093,15 @@ VMaxminI32Vop3::VMaxminI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_i32_e64_dpp" + : "v_maxmin_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9502,7 +11154,15 @@ VMinmaxI32Vop3::VMinmaxI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_i32_e64_dpp" + : "v_minmax_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9559,7 +11219,16 @@ VDot2F16F16Vop3::VDot2F16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2F16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f16_f16_e64_dpp" + : "v_dot2_f16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9622,7 +11291,16 @@ VDot2Bf16Bf16Vop3::VDot2Bf16Bf16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode) { +DecodeResult decodeVDot2Bf16Bf16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_bf16_bf16_e64_dpp" + : "v_dot2_bf16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9681,7 +11359,16 @@ VMinmaxNumF32Vop3::VMinmaxNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_num_f32_e64_dpp" + : "v_minmax_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9734,7 +11421,16 @@ VMaxminNumF32Vop3::VMaxminNumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminNumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminNumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_num_f32_e64_dpp" + : "v_maxmin_num_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9799,7 +11495,16 @@ VMinmaxNumF16Vop3::VMinmaxNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinmaxNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinmaxNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minmax_num_f16_e64_dpp" + : "v_minmax_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9870,7 +11575,16 @@ VMaxminNumF16Vop3::VMaxminNumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxminNumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxminNumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maxmin_num_f16_e64_dpp" + : "v_maxmin_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9929,7 +11643,16 @@ VMinimummaximumF32Vop3::VMinimummaximumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimummaximumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimummaximumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimummaximum_f32_e64_dpp" + : "v_minimummaximum_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -9982,7 +11705,16 @@ VMaximumminimumF32Vop3::VMaximumminimumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumminimumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumminimumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximumminimum_f32_e64_dpp" + : "v_maximumminimum_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10047,7 +11779,16 @@ VMinimummaximumF16Vop3::VMinimummaximumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimummaximumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimummaximumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimummaximum_f16_e64_dpp" + : "v_minimummaximum_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10118,7 +11859,16 @@ VMaximumminimumF16Vop3::VMaximumminimumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumminimumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumminimumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximumminimum_f16_e64_dpp" + : "v_maximumminimum_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10141,19 +11891,28 @@ VSExpF32Vop3::VSExpF32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_EXP_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_EXP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSExpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSExpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_exp_f32_e64_dpp" + : "v_s_exp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10170,20 +11929,29 @@ VSExpF16Vop3::VSExpF16Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_EXP_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_EXP_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSExpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSExpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_exp_f16_e64_dpp" + : "v_s_exp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_EXP_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10200,19 +11968,28 @@ VSLogF32Vop3::VSLogF32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_LOG_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_LOG_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSLogF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSLogF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_log_f32_e64_dpp" + : "v_s_log_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10229,20 +12006,29 @@ VSLogF16Vop3::VSLogF16Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_LOG_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_LOG_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSLogF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSLogF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_log_f16_e64_dpp" + : "v_s_log_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_LOG_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10259,19 +12045,28 @@ VSRcpF32Vop3::VSRcpF32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RCP_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RCP_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRcpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRcpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rcp_f32_e64_dpp" + : "v_s_rcp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10288,20 +12083,29 @@ VSRcpF16Vop3::VSRcpF16Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RCP_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RCP_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRcpF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRcpF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rcp_f16_e64_dpp" + : "v_s_rcp_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RCP_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10318,19 +12122,28 @@ VSRsqF32Vop3::VSRsqF32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RSQ_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RSQ_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRsqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRsqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rsq_f32_e64_dpp" + : "v_s_rsq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10347,20 +12160,29 @@ VSRsqF16Vop3::VSRsqF16Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_RSQ_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_RSQ_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSRsqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSRsqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_rsq_f16_e64_dpp" + : "v_s_rsq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_RSQ_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10377,19 +12199,28 @@ VSSqrtF32Vop3::VSSqrtF32Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_SQRT_F32 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_SQRT_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSSqrtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSSqrtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_sqrt_f32_e64_dpp" + : "v_s_sqrt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F32 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10406,20 +12237,29 @@ VSSqrtF16Vop3::VSSqrtF16Vop3(const MachineInst *inst) src_operands_[0] = &src0; num_src_ = 1; num_dst_ = 1; - if (reinterpret_cast(inst)->vdst >= OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) - throw util::InvalidInst("V_S_SQRT_F16 has an invalid SReg_32_XEXEC destination", ""); if (reinterpret_cast(inst)->src0 == 255) src0 = Operand(16, OperandType::OPR_SIMM32, static_cast(( reinterpret_cast(inst)->simm32 & 0xFFFFu))); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_S_SQRT_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSSqrtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSSqrtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_s_sqrt_f16_e64_dpp" + : "v_s_sqrt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->vdst >= + OpSelSdstExec::OPR_SDST_EXEC_EXEC_LO) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F16 has an invalid SReg_32_XEXEC destination"; + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_S_SQRT_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -10474,7 +12314,15 @@ VAddNcU16Vop3::VAddNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_u16_e64_dpp" + : "v_add_nc_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10535,7 +12383,15 @@ VSubNcU16Vop3::VSubNcU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_u16_e64_dpp" + : "v_sub_nc_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10596,7 +12452,15 @@ VMulLoU16Vop3::VMulLoU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMulLoU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u16_e64_dpp" + : "v_mul_lo_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10649,7 +12513,16 @@ VCvtPkI16F32Vop3::VCvtPkI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_f32_e64_dpp" + : "v_cvt_pk_i16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10696,7 +12569,16 @@ VCvtPkU16F32Vop3::VCvtPkU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_f32_e64_dpp" + : "v_cvt_pk_u16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10751,7 +12633,15 @@ VMaxU16Vop3::VMaxU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_u16_e64_dpp" + : "v_max_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10812,7 +12702,15 @@ VMaxI16Vop3::VMaxI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaxI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaxI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_max_i16_e64_dpp" + : "v_max_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10873,7 +12771,15 @@ VMinU16Vop3::VMinU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_u16_e64_dpp" + : "v_min_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10934,7 +12840,15 @@ VMinI16Vop3::VMinI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_min_i16_e64_dpp" + : "v_min_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -10995,7 +12909,15 @@ VAddNcI16Vop3::VAddNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i16_e64_dpp" + : "v_add_nc_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11056,7 +12978,15 @@ VSubNcI16Vop3::VSubNcI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i16_e64_dpp" + : "v_sub_nc_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11081,13 +13011,22 @@ VPermlane16VarB32Vop3::VPermlane16VarB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANE16_VAR_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlane16VarB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlane16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlane16_var_b32_e64_dpp" + : "v_permlane16_var_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANE16_VAR_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11106,13 +13045,22 @@ VPermlanex16VarB32Vop3::VPermlanex16VarB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PERMLANEX16_VAR_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPermlanex16VarB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVPermlanex16VarB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_permlanex16_var_b32_e64_dpp" + : "v_permlanex16_var_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_PERMLANEX16_VAR_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11167,7 +13115,16 @@ VPackB32F16Vop3::VPackB32F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVPackB32F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVPackB32F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pack_b32_f16_e64_dpp" + : "v_pack_b32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11222,7 +13179,16 @@ VCvtPkNormI16F16Vop3::VCvtPkNormI16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f16_e64_dpp" + : "v_cvt_pk_norm_i16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11277,7 +13243,16 @@ VCvtPkNormU16F16Vop3::VCvtPkNormU16F16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f16_e64_dpp" + : "v_cvt_pk_norm_u16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11324,7 +13299,15 @@ VLdexpF32Vop3::VLdexpF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLdexpF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f32_e64_dpp" + : "v_ldexp_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11371,7 +13354,15 @@ VBfmB32Vop3::VBfmB32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBfmB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bfm_b32_e64_dpp" + : "v_bfm_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11418,7 +13409,16 @@ VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVBcntU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bcnt_u32_b32_e64_dpp" + : "v_bcnt_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11465,7 +13465,16 @@ VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntLoU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntLoU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_lo_u32_b32_e64_dpp" + : "v_mbcnt_lo_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11512,7 +13521,16 @@ VMbcntHiU32B32Vop3::VMbcntHiU32B32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMbcntHiU32B32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMbcntHiU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mbcnt_hi_u32_b32_e64_dpp" + : "v_mbcnt_hi_u32_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11559,7 +13577,16 @@ VCvtPkNormI16F32Vop3::VCvtPkNormI16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormI16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_i16_f32_e64_dpp" + : "v_cvt_pk_norm_i16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11606,7 +13633,16 @@ VCvtPkNormU16F32Vop3::VCvtPkNormU16F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkNormU16F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_norm_u16_f32_e64_dpp" + : "v_cvt_pk_norm_u16_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11653,7 +13689,16 @@ VCvtPkU16U32Vop3::VCvtPkU16U32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkU16U32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkU16U32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_u16_u32_e64_dpp" + : "v_cvt_pk_u16_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11700,7 +13745,16 @@ VCvtPkI16I32Vop3::VCvtPkI16I32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkI16I32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkI16I32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_i16_i32_e64_dpp" + : "v_cvt_pk_i16_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11747,7 +13801,15 @@ VSubNcI32Vop3::VSubNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVSubNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_nc_i32_e64_dpp" + : "v_sub_nc_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11794,7 +13856,15 @@ VAddNcI32Vop3::VAddNcI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddNcI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVAddNcI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_nc_i32_e64_dpp" + : "v_add_nc_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -11822,13 +13892,21 @@ VLdexpF64Vop3::VLdexpF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LDEXP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLdexpF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLdexpF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ldexp_f64_e64_dpp" + : "v_ldexp_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LDEXP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11855,13 +13933,21 @@ VMulLoU32Vop3::VMulLoU32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_LO_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulLoU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulLoU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_lo_u32_e64_dpp" + : "v_mul_lo_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_LO_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11888,13 +13974,21 @@ VMulHiU32Vop3::VMulHiU32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulHiU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_u32_e64_dpp" + : "v_mul_hi_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11921,13 +14015,21 @@ VMulHiI32Vop3::VMulHiI32Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MUL_HI_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMulHiI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMulHiI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mul_hi_i32_e64_dpp" + : "v_mul_hi_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MUL_HI_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -11955,13 +14057,22 @@ VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_TRIG_PREOP_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVTrigPreopF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVTrigPreopF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_trig_preop_f64_e64_dpp" + : "v_trig_preop_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_TRIG_PREOP_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12016,7 +14127,16 @@ VLshlrevB16Vop3::VLshlrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshlrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshlrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshlrev_b16_e64_dpp" + : "v_lshlrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12077,7 +14197,16 @@ VLshrrevB16Vop3::VLshrrevB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVLshrrevB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b16_e64_dpp" + : "v_lshrrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12138,7 +14267,16 @@ VAshrrevI16Vop3::VAshrrevI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAshrrevI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i16_e64_dpp" + : "v_ashrrev_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12172,13 +14310,22 @@ VLshrrevB64Vop3::VLshrrevB64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_LSHRREV_B64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVLshrrevB64Vop3(const MachineInst *opcode) { +DecodeResult decodeVLshrrevB64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_lshrrev_b64_e64_dpp" + : "v_lshrrev_b64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_LSHRREV_B64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12206,13 +14353,22 @@ VAshrrevI64Vop3::VAshrrevI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_ASHRREV_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVAshrrevI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVAshrrevI64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_ashrrev_i64_e64_dpp" + : "v_ashrrev_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_ASHRREV_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12241,13 +14397,22 @@ VMinimumF64Vop3::VMinimumF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MINIMUM_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMinimumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimumF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum_f64_e64_dpp" + : "v_minimum_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MINIMUM_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12276,13 +14441,22 @@ VMaximumF64Vop3::VMaximumF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAXIMUM_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMaximumF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum_f64_e64_dpp" + : "v_maximum_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_MAXIMUM_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12301,13 +14475,22 @@ VReadlaneB32Vop3::VReadlaneB32Vop3(const MachineInst *inst) src_operands_[1] = &src1; num_src_ = 2; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_READLANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVReadlaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVReadlaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_readlane_b32_e64_dpp" + : "v_readlane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_READLANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12331,13 +14514,22 @@ VWritelaneB32Vop3::VWritelaneB32Vop3(const MachineInst *inst) src0 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WRITELANE_B32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWritelaneB32Vop3(const MachineInst *opcode) { +DecodeResult decodeVWritelaneB32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_writelane_b32_e64_dpp" + : "v_writelane_b32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_WRITELANE_B32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -12392,7 +14584,15 @@ VAndB16Vop3::VAndB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAndB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVAndB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_and_b16_e64_dpp" + : "v_and_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12453,7 +14653,15 @@ VOrB16Vop3::VOrB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVOrB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVOrB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_or_b16_e64_dpp" + : "v_or_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12514,7 +14722,15 @@ VXorB16Vop3::VXorB16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVXorB16Vop3(const MachineInst *opcode) { +DecodeResult decodeVXorB16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_xor_b16_e64_dpp" + : "v_xor_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12567,7 +14783,16 @@ VMinimumF32Vop3::VMinimumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum_f32_e64_dpp" + : "v_minimum_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12614,7 +14839,16 @@ VMaximumF32Vop3::VMaximumF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum_f32_e64_dpp" + : "v_maximum_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12669,7 +14903,16 @@ VMinimumF16Vop3::VMinimumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMinimumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMinimumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_minimum_f16_e64_dpp" + : "v_minimum_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12730,7 +14973,16 @@ VMaximumF16Vop3::VMaximumF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVMaximumF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVMaximumF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_maximum_f16_e64_dpp" + : "v_maximum_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12783,7 +15035,16 @@ VCvtPkFp8F32Vop3::VCvtPkFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_fp8_f32_e64_dpp" + : "v_cvt_pk_fp8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12836,7 +15097,16 @@ VCvtPkBf8F32Vop3::VCvtPkBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtPkBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtPkBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_pk_bf8_f32_e64_dpp" + : "v_cvt_pk_bf8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12890,7 +15160,16 @@ VCvtSrFp8F32Vop3::VCvtSrFp8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrFp8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrFp8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_fp8_f32_e64_dpp" + : "v_cvt_sr_fp8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -12944,7 +15223,16 @@ VCvtSrBf8F32Vop3::VCvtSrBf8F32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCvtSrBf8F32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCvtSrBf8F32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cvt_sr_bf8_f32_e64_dpp" + : "v_cvt_sr_bf8_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13005,7 +15293,15 @@ VCmpLtF16Vop3::VCmpLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_e64_dpp" + : "v_cmp_lt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13060,7 +15356,15 @@ VCmpEqF16Vop3::VCmpEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_e64_dpp" + : "v_cmp_eq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13115,7 +15419,15 @@ VCmpLeF16Vop3::VCmpLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_e64_dpp" + : "v_cmp_le_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13170,7 +15482,15 @@ VCmpGtF16Vop3::VCmpGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_e64_dpp" + : "v_cmp_gt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13225,7 +15545,15 @@ VCmpLgF16Vop3::VCmpLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_e64_dpp" + : "v_cmp_lg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13280,7 +15608,15 @@ VCmpGeF16Vop3::VCmpGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_e64_dpp" + : "v_cmp_ge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13335,7 +15671,15 @@ VCmpOF16Vop3::VCmpOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_e64_dpp" + : "v_cmp_o_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13390,7 +15734,15 @@ VCmpUF16Vop3::VCmpUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_e64_dpp" + : "v_cmp_u_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13445,7 +15797,15 @@ VCmpNgeF16Vop3::VCmpNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_e64_dpp" + : "v_cmp_nge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13500,7 +15860,15 @@ VCmpNlgF16Vop3::VCmpNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_e64_dpp" + : "v_cmp_nlg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13555,7 +15923,15 @@ VCmpNgtF16Vop3::VCmpNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_e64_dpp" + : "v_cmp_ngt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13610,7 +15986,15 @@ VCmpNleF16Vop3::VCmpNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_e64_dpp" + : "v_cmp_nle_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13665,7 +16049,15 @@ VCmpNeqF16Vop3::VCmpNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_e64_dpp" + : "v_cmp_neq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13720,7 +16112,15 @@ VCmpNltF16Vop3::VCmpNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_e64_dpp" + : "v_cmp_nlt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13767,7 +16167,15 @@ VCmpLtF32Vop3::VCmpLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_e64_dpp" + : "v_cmp_lt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13814,7 +16222,15 @@ VCmpEqF32Vop3::VCmpEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_e64_dpp" + : "v_cmp_eq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13861,7 +16277,15 @@ VCmpLeF32Vop3::VCmpLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_e64_dpp" + : "v_cmp_le_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13908,7 +16332,15 @@ VCmpGtF32Vop3::VCmpGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_e64_dpp" + : "v_cmp_gt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -13955,7 +16387,15 @@ VCmpLgF32Vop3::VCmpLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_e64_dpp" + : "v_cmp_lg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14002,7 +16442,15 @@ VCmpGeF32Vop3::VCmpGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_e64_dpp" + : "v_cmp_ge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14049,7 +16497,15 @@ VCmpOF32Vop3::VCmpOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_e64_dpp" + : "v_cmp_o_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14096,7 +16552,15 @@ VCmpUF32Vop3::VCmpUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_e64_dpp" + : "v_cmp_u_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14143,7 +16607,15 @@ VCmpNgeF32Vop3::VCmpNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_e64_dpp" + : "v_cmp_nge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14190,7 +16662,15 @@ VCmpNlgF32Vop3::VCmpNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_e64_dpp" + : "v_cmp_nlg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14237,7 +16717,15 @@ VCmpNgtF32Vop3::VCmpNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_e64_dpp" + : "v_cmp_ngt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14284,7 +16772,15 @@ VCmpNleF32Vop3::VCmpNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_e64_dpp" + : "v_cmp_nle_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14331,7 +16827,15 @@ VCmpNeqF32Vop3::VCmpNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_e64_dpp" + : "v_cmp_neq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14378,7 +16882,15 @@ VCmpNltF32Vop3::VCmpNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_e64_dpp" + : "v_cmp_nlt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14407,13 +16919,21 @@ VCmpLtF64Vop3::VCmpLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_e64_dpp" + : "v_cmp_lt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14442,13 +16962,21 @@ VCmpEqF64Vop3::VCmpEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_e64_dpp" + : "v_cmp_eq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14477,13 +17005,21 @@ VCmpLeF64Vop3::VCmpLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_e64_dpp" + : "v_cmp_le_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14512,13 +17048,21 @@ VCmpGtF64Vop3::VCmpGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_e64_dpp" + : "v_cmp_gt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14547,13 +17091,21 @@ VCmpLgF64Vop3::VCmpLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_e64_dpp" + : "v_cmp_lg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14582,13 +17134,21 @@ VCmpGeF64Vop3::VCmpGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_e64_dpp" + : "v_cmp_ge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14617,13 +17177,21 @@ VCmpOF64Vop3::VCmpOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_e64_dpp" + : "v_cmp_o_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14652,13 +17220,21 @@ VCmpUF64Vop3::VCmpUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_e64_dpp" + : "v_cmp_u_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14687,13 +17263,21 @@ VCmpNgeF64Vop3::VCmpNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_e64_dpp" + : "v_cmp_nge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14722,13 +17306,21 @@ VCmpNlgF64Vop3::VCmpNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_e64_dpp" + : "v_cmp_nlg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14757,13 +17349,21 @@ VCmpNgtF64Vop3::VCmpNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_e64_dpp" + : "v_cmp_ngt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14792,13 +17392,21 @@ VCmpNleF64Vop3::VCmpNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_e64_dpp" + : "v_cmp_nle_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14827,13 +17435,21 @@ VCmpNeqF64Vop3::VCmpNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_e64_dpp" + : "v_cmp_neq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14862,13 +17478,21 @@ VCmpNltF64Vop3::VCmpNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_e64_dpp" + : "v_cmp_nlt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -14923,7 +17547,15 @@ VCmpLtI16Vop3::VCmpLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_e64_dpp" + : "v_cmp_lt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -14978,7 +17610,15 @@ VCmpEqI16Vop3::VCmpEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_e64_dpp" + : "v_cmp_eq_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15033,7 +17673,15 @@ VCmpLeI16Vop3::VCmpLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_e64_dpp" + : "v_cmp_le_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15088,7 +17736,15 @@ VCmpGtI16Vop3::VCmpGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_e64_dpp" + : "v_cmp_gt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15143,7 +17799,15 @@ VCmpNeI16Vop3::VCmpNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_e64_dpp" + : "v_cmp_ne_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15198,7 +17862,15 @@ VCmpGeI16Vop3::VCmpGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_e64_dpp" + : "v_cmp_ge_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15253,7 +17925,15 @@ VCmpLtU16Vop3::VCmpLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_e64_dpp" + : "v_cmp_lt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15308,7 +17988,15 @@ VCmpEqU16Vop3::VCmpEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_e64_dpp" + : "v_cmp_eq_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15363,7 +18051,15 @@ VCmpLeU16Vop3::VCmpLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_e64_dpp" + : "v_cmp_le_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15418,7 +18114,15 @@ VCmpGtU16Vop3::VCmpGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_e64_dpp" + : "v_cmp_gt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15473,7 +18177,15 @@ VCmpNeU16Vop3::VCmpNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_e64_dpp" + : "v_cmp_ne_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15528,7 +18240,15 @@ VCmpGeU16Vop3::VCmpGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_e64_dpp" + : "v_cmp_ge_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15575,7 +18295,15 @@ VCmpLtI32Vop3::VCmpLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_e64_dpp" + : "v_cmp_lt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15622,7 +18350,15 @@ VCmpEqI32Vop3::VCmpEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_e64_dpp" + : "v_cmp_eq_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15669,7 +18405,15 @@ VCmpLeI32Vop3::VCmpLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_e64_dpp" + : "v_cmp_le_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15716,7 +18460,15 @@ VCmpGtI32Vop3::VCmpGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_e64_dpp" + : "v_cmp_gt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15763,7 +18515,15 @@ VCmpNeI32Vop3::VCmpNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_e64_dpp" + : "v_cmp_ne_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15810,7 +18570,15 @@ VCmpGeI32Vop3::VCmpGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_e64_dpp" + : "v_cmp_ge_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15857,7 +18625,15 @@ VCmpLtU32Vop3::VCmpLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_e64_dpp" + : "v_cmp_lt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15904,7 +18680,15 @@ VCmpEqU32Vop3::VCmpEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_e64_dpp" + : "v_cmp_eq_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15951,7 +18735,15 @@ VCmpLeU32Vop3::VCmpLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_e64_dpp" + : "v_cmp_le_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -15998,7 +18790,15 @@ VCmpGtU32Vop3::VCmpGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_e64_dpp" + : "v_cmp_gt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16045,7 +18845,15 @@ VCmpNeU32Vop3::VCmpNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_e64_dpp" + : "v_cmp_ne_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16092,7 +18900,15 @@ VCmpGeU32Vop3::VCmpGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_e64_dpp" + : "v_cmp_ge_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16121,13 +18937,21 @@ VCmpLtI64Vop3::VCmpLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_e64_dpp" + : "v_cmp_lt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16156,13 +18980,21 @@ VCmpEqI64Vop3::VCmpEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_e64_dpp" + : "v_cmp_eq_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16191,13 +19023,21 @@ VCmpLeI64Vop3::VCmpLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_e64_dpp" + : "v_cmp_le_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16226,13 +19066,21 @@ VCmpGtI64Vop3::VCmpGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_e64_dpp" + : "v_cmp_gt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16261,13 +19109,21 @@ VCmpNeI64Vop3::VCmpNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_e64_dpp" + : "v_cmp_ne_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16296,13 +19152,21 @@ VCmpGeI64Vop3::VCmpGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_e64_dpp" + : "v_cmp_ge_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16331,13 +19195,21 @@ VCmpLtU64Vop3::VCmpLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_e64_dpp" + : "v_cmp_lt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16366,13 +19238,21 @@ VCmpEqU64Vop3::VCmpEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_e64_dpp" + : "v_cmp_eq_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16401,13 +19281,21 @@ VCmpLeU64Vop3::VCmpLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_e64_dpp" + : "v_cmp_le_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16436,13 +19324,21 @@ VCmpGtU64Vop3::VCmpGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_e64_dpp" + : "v_cmp_gt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16471,13 +19367,21 @@ VCmpNeU64Vop3::VCmpNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_e64_dpp" + : "v_cmp_ne_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16506,13 +19410,21 @@ VCmpGeU64Vop3::VCmpGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_e64_dpp" + : "v_cmp_ge_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16567,7 +19479,16 @@ VCmpClassF16Vop3::VCmpClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_e64_dpp" + : "v_cmp_class_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16614,7 +19535,16 @@ VCmpClassF32Vop3::VCmpClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_e64_dpp" + : "v_cmp_class_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16642,13 +19572,22 @@ VCmpClassF64Vop3::VCmpClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_e64_dpp" + : "v_cmp_class_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -16707,7 +19646,15 @@ VCmpxLtF16Vop3::VCmpxLtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_e64_dpp" + : "v_cmpx_lt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16766,7 +19713,15 @@ VCmpxEqF16Vop3::VCmpxEqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_e64_dpp" + : "v_cmpx_eq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16825,7 +19780,15 @@ VCmpxLeF16Vop3::VCmpxLeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_e64_dpp" + : "v_cmpx_le_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16884,7 +19847,15 @@ VCmpxGtF16Vop3::VCmpxGtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_e64_dpp" + : "v_cmpx_gt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -16943,7 +19914,15 @@ VCmpxLgF16Vop3::VCmpxLgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_e64_dpp" + : "v_cmpx_lg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17002,7 +19981,15 @@ VCmpxGeF16Vop3::VCmpxGeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_e64_dpp" + : "v_cmpx_ge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17061,7 +20048,15 @@ VCmpxOF16Vop3::VCmpxOF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_e64_dpp" + : "v_cmpx_o_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17120,7 +20115,15 @@ VCmpxUF16Vop3::VCmpxUF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_e64_dpp" + : "v_cmpx_u_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17179,7 +20182,16 @@ VCmpxNgeF16Vop3::VCmpxNgeF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_e64_dpp" + : "v_cmpx_nge_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17238,7 +20250,16 @@ VCmpxNlgF16Vop3::VCmpxNlgF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_e64_dpp" + : "v_cmpx_nlg_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17297,7 +20318,16 @@ VCmpxNgtF16Vop3::VCmpxNgtF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_e64_dpp" + : "v_cmpx_ngt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17356,7 +20386,16 @@ VCmpxNleF16Vop3::VCmpxNleF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_e64_dpp" + : "v_cmpx_nle_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17415,7 +20454,16 @@ VCmpxNeqF16Vop3::VCmpxNeqF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_e64_dpp" + : "v_cmpx_neq_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17474,7 +20522,16 @@ VCmpxNltF16Vop3::VCmpxNltF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_e64_dpp" + : "v_cmpx_nlt_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17525,7 +20582,15 @@ VCmpxLtF32Vop3::VCmpxLtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_e64_dpp" + : "v_cmpx_lt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17576,7 +20641,15 @@ VCmpxEqF32Vop3::VCmpxEqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_e64_dpp" + : "v_cmpx_eq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17627,7 +20700,15 @@ VCmpxLeF32Vop3::VCmpxLeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_e64_dpp" + : "v_cmpx_le_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17678,7 +20759,15 @@ VCmpxGtF32Vop3::VCmpxGtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_e64_dpp" + : "v_cmpx_gt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17729,7 +20818,15 @@ VCmpxLgF32Vop3::VCmpxLgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_e64_dpp" + : "v_cmpx_lg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17780,7 +20877,15 @@ VCmpxGeF32Vop3::VCmpxGeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_e64_dpp" + : "v_cmpx_ge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17831,7 +20936,15 @@ VCmpxOF32Vop3::VCmpxOF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_e64_dpp" + : "v_cmpx_o_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17882,7 +20995,15 @@ VCmpxUF32Vop3::VCmpxUF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_e64_dpp" + : "v_cmpx_u_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17933,7 +21054,16 @@ VCmpxNgeF32Vop3::VCmpxNgeF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_e64_dpp" + : "v_cmpx_nge_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -17984,7 +21114,16 @@ VCmpxNlgF32Vop3::VCmpxNlgF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_e64_dpp" + : "v_cmpx_nlg_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18035,7 +21174,16 @@ VCmpxNgtF32Vop3::VCmpxNgtF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_e64_dpp" + : "v_cmpx_ngt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18086,7 +21234,16 @@ VCmpxNleF32Vop3::VCmpxNleF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_e64_dpp" + : "v_cmpx_nle_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18137,7 +21294,16 @@ VCmpxNeqF32Vop3::VCmpxNeqF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_e64_dpp" + : "v_cmpx_neq_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18188,7 +21354,16 @@ VCmpxNltF32Vop3::VCmpxNltF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_e64_dpp" + : "v_cmpx_nlt_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18219,15 +21394,23 @@ VCmpxLtF64Vop3::VCmpxLtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_e64_dpp" + : "v_cmpx_lt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18258,15 +21441,23 @@ VCmpxEqF64Vop3::VCmpxEqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_e64_dpp" + : "v_cmpx_eq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18297,15 +21488,23 @@ VCmpxLeF64Vop3::VCmpxLeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_e64_dpp" + : "v_cmpx_le_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18336,15 +21535,23 @@ VCmpxGtF64Vop3::VCmpxGtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_e64_dpp" + : "v_cmpx_gt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18375,15 +21582,23 @@ VCmpxLgF64Vop3::VCmpxLgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_e64_dpp" + : "v_cmpx_lg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18414,15 +21629,23 @@ VCmpxGeF64Vop3::VCmpxGeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_e64_dpp" + : "v_cmpx_ge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18453,15 +21676,23 @@ VCmpxOF64Vop3::VCmpxOF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_e64_dpp" + : "v_cmpx_o_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18492,15 +21723,23 @@ VCmpxUF64Vop3::VCmpxUF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_e64_dpp" + : "v_cmpx_u_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18531,15 +21770,24 @@ VCmpxNgeF64Vop3::VCmpxNgeF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_e64_dpp" + : "v_cmpx_nge_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18570,15 +21818,24 @@ VCmpxNlgF64Vop3::VCmpxNlgF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_e64_dpp" + : "v_cmpx_nlg_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18609,15 +21866,24 @@ VCmpxNgtF64Vop3::VCmpxNgtF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_e64_dpp" + : "v_cmpx_ngt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18648,15 +21914,24 @@ VCmpxNleF64Vop3::VCmpxNleF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_e64_dpp" + : "v_cmpx_nle_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18687,15 +21962,24 @@ VCmpxNeqF64Vop3::VCmpxNeqF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_e64_dpp" + : "v_cmpx_neq_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18726,15 +22010,24 @@ VCmpxNltF64Vop3::VCmpxNltF64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_e64_dpp" + : "v_cmpx_nlt_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -18793,7 +22086,15 @@ VCmpxLtI16Vop3::VCmpxLtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_e64_dpp" + : "v_cmpx_lt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18852,7 +22153,15 @@ VCmpxEqI16Vop3::VCmpxEqI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_e64_dpp" + : "v_cmpx_eq_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18911,7 +22220,15 @@ VCmpxLeI16Vop3::VCmpxLeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_e64_dpp" + : "v_cmpx_le_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -18970,7 +22287,15 @@ VCmpxGtI16Vop3::VCmpxGtI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_e64_dpp" + : "v_cmpx_gt_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19029,7 +22354,15 @@ VCmpxNeI16Vop3::VCmpxNeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_e64_dpp" + : "v_cmpx_ne_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19088,7 +22421,15 @@ VCmpxGeI16Vop3::VCmpxGeI16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_e64_dpp" + : "v_cmpx_ge_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19147,7 +22488,15 @@ VCmpxLtU16Vop3::VCmpxLtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_e64_dpp" + : "v_cmpx_lt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19206,7 +22555,15 @@ VCmpxEqU16Vop3::VCmpxEqU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_e64_dpp" + : "v_cmpx_eq_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19265,7 +22622,15 @@ VCmpxLeU16Vop3::VCmpxLeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_e64_dpp" + : "v_cmpx_le_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19324,7 +22689,15 @@ VCmpxGtU16Vop3::VCmpxGtU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_e64_dpp" + : "v_cmpx_gt_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19383,7 +22756,15 @@ VCmpxNeU16Vop3::VCmpxNeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_e64_dpp" + : "v_cmpx_ne_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19442,7 +22823,15 @@ VCmpxGeU16Vop3::VCmpxGeU16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_e64_dpp" + : "v_cmpx_ge_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19493,7 +22882,15 @@ VCmpxLtI32Vop3::VCmpxLtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_e64_dpp" + : "v_cmpx_lt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19544,7 +22941,15 @@ VCmpxEqI32Vop3::VCmpxEqI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_e64_dpp" + : "v_cmpx_eq_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19595,7 +23000,15 @@ VCmpxLeI32Vop3::VCmpxLeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_e64_dpp" + : "v_cmpx_le_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19646,7 +23059,15 @@ VCmpxGtI32Vop3::VCmpxGtI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_e64_dpp" + : "v_cmpx_gt_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19697,7 +23118,15 @@ VCmpxNeI32Vop3::VCmpxNeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_e64_dpp" + : "v_cmpx_ne_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19748,7 +23177,15 @@ VCmpxGeI32Vop3::VCmpxGeI32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_e64_dpp" + : "v_cmpx_ge_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19799,7 +23236,15 @@ VCmpxLtU32Vop3::VCmpxLtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_e64_dpp" + : "v_cmpx_lt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19850,7 +23295,15 @@ VCmpxEqU32Vop3::VCmpxEqU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_e64_dpp" + : "v_cmpx_eq_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19901,7 +23354,15 @@ VCmpxLeU32Vop3::VCmpxLeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_e64_dpp" + : "v_cmpx_le_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -19952,7 +23413,15 @@ VCmpxGtU32Vop3::VCmpxGtU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_e64_dpp" + : "v_cmpx_gt_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20003,7 +23472,15 @@ VCmpxNeU32Vop3::VCmpxNeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_e64_dpp" + : "v_cmpx_ne_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20054,7 +23531,15 @@ VCmpxGeU32Vop3::VCmpxGeU32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_e64_dpp" + : "v_cmpx_ge_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20085,15 +23570,23 @@ VCmpxLtI64Vop3::VCmpxLtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_e64_dpp" + : "v_cmpx_lt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20124,15 +23617,23 @@ VCmpxEqI64Vop3::VCmpxEqI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_e64_dpp" + : "v_cmpx_eq_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20163,15 +23664,23 @@ VCmpxLeI64Vop3::VCmpxLeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_e64_dpp" + : "v_cmpx_le_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20202,15 +23711,23 @@ VCmpxGtI64Vop3::VCmpxGtI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_e64_dpp" + : "v_cmpx_gt_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20241,15 +23758,23 @@ VCmpxNeI64Vop3::VCmpxNeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_e64_dpp" + : "v_cmpx_ne_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20280,15 +23805,23 @@ VCmpxGeI64Vop3::VCmpxGeI64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_e64_dpp" + : "v_cmpx_ge_i64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20319,15 +23852,23 @@ VCmpxLtU64Vop3::VCmpxLtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_e64_dpp" + : "v_cmpx_lt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20358,15 +23899,23 @@ VCmpxEqU64Vop3::VCmpxEqU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_e64_dpp" + : "v_cmpx_eq_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20397,15 +23946,23 @@ VCmpxLeU64Vop3::VCmpxLeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_e64_dpp" + : "v_cmpx_le_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20436,15 +23993,23 @@ VCmpxGtU64Vop3::VCmpxGtU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_e64_dpp" + : "v_cmpx_gt_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20475,15 +24040,23 @@ VCmpxNeU64Vop3::VCmpxNeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_e64_dpp" + : "v_cmpx_ne_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20514,15 +24087,23 @@ VCmpxGeU64Vop3::VCmpxGeU64Vop3(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vop3(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_e64_dpp" + : "v_cmpx_ge_u64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20581,7 +24162,16 @@ VCmpxClassF16Vop3::VCmpxClassF16Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_e64_dpp" + : "v_cmpx_class_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20632,7 +24222,16 @@ VCmpxClassF32Vop3::VCmpxClassF32Vop3(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_e64_dpp" + : "v_cmpx_class_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20662,15 +24261,24 @@ VCmpxClassF64Vop3::VCmpxClassF64Vop3(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vop3(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_e64_dpp" + : "v_cmpx_class_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20721,7 +24329,16 @@ VAddCoCiU32Vop3SdstEnc::VAddCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_ci_u32_e64_dpp" + : "v_add_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20772,7 +24389,16 @@ VSubCoCiU32Vop3SdstEnc::VSubCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_ci_u32_e64_dpp" + : "v_sub_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20823,7 +24449,16 @@ VSubrevCoCiU32Vop3SdstEnc::VSubrevCoCiU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoCiU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_ci_u32_e64_dpp" + : "v_subrev_co_ci_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -20858,13 +24493,23 @@ VDivScaleF32Vop3SdstEnc::VDivScaleF32Vop3SdstEnc(const MachineInst *inst) src2 = Operand(32, OperandType::OPR_SIMM32, static_cast( reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f32_e64_dpp" + : "v_div_scale_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20905,13 +24550,23 @@ VDivScaleF64Vop3SdstEnc::VDivScaleF64Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DIV_SCALE_F64 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVDivScaleF64Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_div_scale_f64_e64_dpp" + : "v_div_scale_f64", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DIV_SCALE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20948,13 +24603,23 @@ VMadCoU64U32Vop3SdstEnc::VMadCoU64U32Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_CO_U64_U32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadCoU64U32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_co_u64_u32_e64_dpp" + : "v_mad_co_u64_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_CO_U64_U32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -20991,13 +24656,23 @@ VMadCoI64I32Vop3SdstEnc::VMadCoI64I32Vop3SdstEnc(const MachineInst *inst) static_cast( reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_MAD_CO_I64_I32 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVMadCoI64I32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_mad_co_i64_i32_e64_dpp" + : "v_mad_co_i64_i32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_MAD_CO_I64_I32 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -21046,7 +24721,16 @@ VAddCoU32Vop3SdstEnc::VAddCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVAddCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_add_co_u32_e64_dpp" + : "v_add_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -21095,7 +24779,16 @@ VSubCoU32Vop3SdstEnc::VSubCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_sub_co_u32_e64_dpp" + : "v_sub_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -21144,7 +24837,16 @@ VSubrevCoU32Vop3SdstEnc::VSubrevCoU32Vop3SdstEnc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode) { +DecodeResult decodeVSubrevCoU32Vop3SdstEnc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3SdstEnc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_subrev_co_u32_e64_dpp" + : "v_subrev_co_u32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3p.cpp index 620604194021..a0aa66b2b26f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3p.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vop3p.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -41,13 +40,22 @@ VPkMadI16Vop3p::VPkMadI16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMadI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_i16_e64_dpp" + : "v_pk_mad_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -74,13 +82,23 @@ VPkMulLoU16Vop3p::VPkMulLoU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_LO_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMulLoU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulLoU16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_lo_u16_e64_dpp" + : "v_pk_mul_lo_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_LO_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -107,13 +125,22 @@ VPkAddI16Vop3p::VPkAddI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_i16_e64_dpp" + : "v_pk_add_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -140,13 +167,22 @@ VPkSubI16Vop3p::VPkSubI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkSubI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_i16_e64_dpp" + : "v_pk_sub_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -173,13 +209,23 @@ VPkLshlrevB16Vop3p::VPkLshlrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHLREV_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkLshlrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshlrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshlrev_b16_e64_dpp" + : "v_pk_lshlrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHLREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -206,13 +252,23 @@ VPkLshrrevB16Vop3p::VPkLshrrevB16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_LSHRREV_B16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkLshrrevB16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkLshrrevB16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_lshrrev_b16_e64_dpp" + : "v_pk_lshrrev_b16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_LSHRREV_B16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -239,13 +295,23 @@ VPkAshrrevI16Vop3p::VPkAshrrevI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ASHRREV_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAshrrevI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAshrrevI16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_ashrrev_i16_e64_dpp" + : "v_pk_ashrrev_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ASHRREV_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -272,13 +338,22 @@ VPkMaxI16Vop3p::VPkMaxI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_i16_e64_dpp" + : "v_pk_max_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -305,13 +380,22 @@ VPkMinI16Vop3p::VPkMinI16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_I16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinI16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinI16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_i16_e64_dpp" + : "v_pk_min_i16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_I16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -344,13 +428,22 @@ VPkMadU16Vop3p::VPkMadU16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAD_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMadU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMadU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mad_u16_e64_dpp" + : "v_pk_mad_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -377,13 +470,22 @@ VPkAddU16Vop3p::VPkAddU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_u16_e64_dpp" + : "v_pk_add_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -410,13 +512,22 @@ VPkSubU16Vop3p::VPkSubU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_SUB_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkSubU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkSubU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_sub_u16_e64_dpp" + : "v_pk_sub_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_SUB_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -443,13 +554,22 @@ VPkMaxU16Vop3p::VPkMaxU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_u16_e64_dpp" + : "v_pk_max_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -476,13 +596,22 @@ VPkMinU16Vop3p::VPkMinU16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_U16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinU16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinU16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_u16_e64_dpp" + : "v_pk_min_u16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_U16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -515,13 +644,22 @@ VPkFmaF16Vop3p::VPkFmaF16Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_FMA_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkFmaF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkFmaF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_fma_f16_e64_dpp" + : "v_pk_fma_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_FMA_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -548,13 +686,22 @@ VPkAddF16Vop3p::VPkAddF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_ADD_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkAddF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkAddF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_add_f16_e64_dpp" + : "v_pk_add_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_ADD_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -581,13 +728,22 @@ VPkMulF16Vop3p::VPkMulF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MUL_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMulF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMulF16Vop3p(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_mul_f16_e64_dpp" + : "v_pk_mul_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MUL_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -640,7 +796,16 @@ VDot2F32F16Vop3p::VDot2F32F16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f32_f16_e64_dpp" + : "v_dot2_f32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -673,13 +838,23 @@ VDot4I32Iu8Vop3p::VDot4I32Iu8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_I32_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4I32Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4I32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_i32_iu8_e64_dpp" + : "v_dot4_i32_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_I32_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -712,13 +887,23 @@ VDot4U32U8Vop3p::VDot4U32U8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_U32_U8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4U32U8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4U32U8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_u32_u8_e64_dpp" + : "v_dot4_u32_u8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_U32_U8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -751,13 +936,23 @@ VDot8I32Iu4Vop3p::VDot8I32Iu4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_I32_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot8I32Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8I32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_i32_iu4_e64_dpp" + : "v_dot8_i32_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_I32_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -790,13 +985,23 @@ VDot8U32U4Vop3p::VDot8U32U4Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT8_U32_U4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot8U32U4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot8U32U4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot8_u32_u4_e64_dpp" + : "v_dot8_u32_u4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT8_U32_U4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -849,7 +1054,16 @@ VDot2F32Bf16Vop3p::VDot2F32Bf16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVDot2F32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot2F32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot2_f32_bf16_e64_dpp" + : "v_dot2_f32_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -876,13 +1090,23 @@ VPkMinNumF16Vop3p::VPkMinNumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MIN_NUM_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinNumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_min_num_f16_e64_dpp" + : "v_pk_min_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MIN_NUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -909,13 +1133,23 @@ VPkMaxNumF16Vop3p::VPkMaxNumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAX_NUM_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaxNumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaxNumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_max_num_f16_e64_dpp" + : "v_pk_max_num_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAX_NUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -942,13 +1176,23 @@ VPkMinimumF16Vop3p::VPkMinimumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MINIMUM_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMinimumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMinimumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_minimum_f16_e64_dpp" + : "v_pk_minimum_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MINIMUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -975,13 +1219,23 @@ VPkMaximumF16Vop3p::VPkMaximumF16Vop3p(const MachineInst *inst) src1 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_PK_MAXIMUM_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVPkMaximumF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVPkMaximumF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_pk_maximum_f16_e64_dpp" + : "v_pk_maximum_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_PK_MAXIMUM_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1034,7 +1288,16 @@ VFmaMixF32Vop3p::VFmaMixF32Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixF32Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixF32Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mix_f32_e64_dpp" + : "v_fma_mix_f32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1088,7 +1351,16 @@ VFmaMixloF16Vop3p::VFmaMixloF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixloF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixloF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixlo_f16_e64_dpp" + : "v_fma_mixlo_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1148,7 +1420,16 @@ VFmaMixhiF16Vop3p::VFmaMixhiF16Vop3p(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVFmaMixhiF16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVFmaMixhiF16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_fma_mixhi_f16_e64_dpp" + : "v_fma_mixhi_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1187,13 +1468,23 @@ VDot4F32Fp8Bf8Vop3p::VDot4F32Fp8Bf8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_F32_FP8_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4F32Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4F32Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_f32_fp8_bf8_e64_dpp" + : "v_dot4_f32_fp8_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_F32_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1226,13 +1517,23 @@ VDot4F32Bf8Fp8Vop3p::VDot4F32Bf8Fp8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_F32_BF8_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4F32Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4F32Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_f32_bf8_fp8_e64_dpp" + : "v_dot4_f32_bf8_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_F32_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1265,13 +1566,23 @@ VDot4F32Fp8Fp8Vop3p::VDot4F32Fp8Fp8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_F32_FP8_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4F32Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4F32Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_f32_fp8_fp8_e64_dpp" + : "v_dot4_f32_fp8_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_F32_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1304,13 +1615,23 @@ VDot4F32Bf8Bf8Vop3p::VDot4F32Bf8Bf8Vop3p(const MachineInst *inst) src2 = Operand( 32, OperandType::OPR_SIMM32, static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_DOT4_F32_BF8_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVDot4F32Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVDot4F32Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_dot4_f32_bf8_bf8_e64_dpp" + : "v_dot4_f32_bf8_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_DOT4_F32_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1332,13 +1653,23 @@ VWmmaF3216x16x16F16Vop3p::VWmmaF3216x16x16F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_f16_e64_dpp" + : "v_wmma_f32_16x16x16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1360,13 +1691,23 @@ VWmmaF3216x16x16Bf16Vop3p::VWmmaF3216x16x16Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_bf16_e64_dpp" + : "v_wmma_f32_16x16x16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1388,13 +1729,23 @@ VWmmaF1616x16x16F16Vop3p::VWmmaF1616x16x16F16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F16_16X16X16_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF1616x16x16F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f16_16x16x16_f16_e64_dpp" + : "v_wmma_f16_16x16x16_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F16_16X16X16_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1416,13 +1767,23 @@ VWmmaBf1616x16x16Bf16Vop3p::VWmmaBf1616x16x16Bf16Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_BF16_16X16X16_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaBf1616x16x16Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_bf16_16x16x16_bf16_e64_dpp" + : "v_wmma_bf16_16x16x16_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_BF16_16X16X16_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1444,13 +1805,23 @@ VWmmaI3216x16x16Iu8Vop3p::VWmmaI3216x16x16Iu8Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X16_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x16Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x16_iu8_e64_dpp" + : "v_wmma_i32_16x16x16_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X16_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1472,13 +1843,23 @@ VWmmaI3216x16x16Iu4Vop3p::VWmmaI3216x16x16Iu4Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X16_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x16Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x16_iu4_e64_dpp" + : "v_wmma_i32_16x16x16_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X16_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1500,13 +1881,23 @@ VWmmaF3216x16x16Fp8Fp8Vop3p::VWmmaF3216x16x16Fp8Fp8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_FP8_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_fp8_fp8_e64_dpp" + : "v_wmma_f32_16x16x16_fp8_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1528,13 +1919,23 @@ VWmmaF3216x16x16Fp8Bf8Vop3p::VWmmaF3216x16x16Fp8Bf8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_FP8_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_fp8_bf8_e64_dpp" + : "v_wmma_f32_16x16x16_fp8_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1556,13 +1957,23 @@ VWmmaF3216x16x16Bf8Fp8Vop3p::VWmmaF3216x16x16Bf8Fp8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_BF8_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_bf8_fp8_e64_dpp" + : "v_wmma_f32_16x16x16_bf8_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1584,13 +1995,23 @@ VWmmaF3216x16x16Bf8Bf8Vop3p::VWmmaF3216x16x16Bf8Bf8Vop3p(const MachineInst *inst src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_F32_16X16X16_BF8_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaF3216x16x16Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaF3216x16x16Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_f32_16x16x16_bf8_bf8_e64_dpp" + : "v_wmma_f32_16x16x16_bf8_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_F32_16X16X16_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1612,13 +2033,23 @@ VWmmaI3216x16x32Iu4Vop3p::VWmmaI3216x16x32Iu4Vop3p(const MachineInst *inst) src_operands_[2] = &src2; num_src_ = 3; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_WMMA_I32_16X16X32_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVWmmaI3216x16x32Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVWmmaI3216x16x32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_wmma_i32_16x16x32_iu4_e64_dpp" + : "v_wmma_i32_16x16x32_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_WMMA_I32_16X16X32_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1640,13 +2071,23 @@ VSwmmacF3216x16x32F16Vop3p::VSwmmacF3216x16x32F16Vop3p(const MachineInst *inst) src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X32_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x32_f16_e64_dpp" + : "v_swmmac_f32_16x16x32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X32_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1668,13 +2109,23 @@ VSwmmacF3216x16x32Bf16Vop3p::VSwmmacF3216x16x32Bf16Vop3p(const MachineInst *inst src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X32_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x32_bf16_e64_dpp" + : "v_swmmac_f32_16x16x32_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X32_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1696,13 +2147,23 @@ VSwmmacF1616x16x32F16Vop3p::VSwmmacF1616x16x32F16Vop3p(const MachineInst *inst) src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F16_16X16X32_F16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF1616x16x32F16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF1616x16x32F16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f16_16x16x32_f16_e64_dpp" + : "v_swmmac_f16_16x16x32_f16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F16_16X16X32_F16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1724,13 +2185,23 @@ VSwmmacBf1616x16x32Bf16Vop3p::VSwmmacBf1616x16x32Bf16Vop3p(const MachineInst *in src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_BF16_16X16X32_BF16 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacBf1616x16x32Bf16Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacBf1616x16x32Bf16Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_bf16_16x16x32_bf16_e64_dpp" + : "v_swmmac_bf16_16x16x32_bf16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_BF16_16X16X32_BF16 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1752,13 +2223,23 @@ VSwmmacI3216x16x32Iu8Vop3p::VSwmmacI3216x16x32Iu8Vop3p(const MachineInst *inst) src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_I32_16X16X32_IU8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacI3216x16x32Iu8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacI3216x16x32Iu8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_i32_16x16x32_iu8_e64_dpp" + : "v_swmmac_i32_16x16x32_iu8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_I32_16X16X32_IU8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1780,13 +2261,23 @@ VSwmmacI3216x16x32Iu4Vop3p::VSwmmacI3216x16x32Iu4Vop3p(const MachineInst *inst) src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_I32_16X16X32_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacI3216x16x32Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacI3216x16x32Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_i32_16x16x32_iu4_e64_dpp" + : "v_swmmac_i32_16x16x32_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_I32_16X16X32_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1808,13 +2299,23 @@ VSwmmacI3216x16x64Iu4Vop3p::VSwmmacI3216x16x64Iu4Vop3p(const MachineInst *inst) src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_I32_16X16X64_IU4 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacI3216x16x64Iu4Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacI3216x16x64Iu4Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_i32_16x16x64_iu4_e64_dpp" + : "v_swmmac_i32_16x16x64_iu4", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_I32_16X16X64_IU4 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1836,13 +2337,23 @@ VSwmmacF3216x16x32Fp8Fp8Vop3p::VSwmmacF3216x16x32Fp8Fp8Vop3p(const MachineInst * src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X32_FP8_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x32Fp8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x32Fp8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x32_fp8_fp8_e64_dpp" + : "v_swmmac_f32_16x16x32_fp8_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X32_FP8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1864,13 +2375,23 @@ VSwmmacF3216x16x32Fp8Bf8Vop3p::VSwmmacF3216x16x32Fp8Bf8Vop3p(const MachineInst * src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X32_FP8_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x32Fp8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x32Fp8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x32_fp8_bf8_e64_dpp" + : "v_swmmac_f32_16x16x32_fp8_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X32_FP8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1892,13 +2413,23 @@ VSwmmacF3216x16x32Bf8Fp8Vop3p::VSwmmacF3216x16x32Bf8Fp8Vop3p(const MachineInst * src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X32_BF8_FP8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x32Bf8Fp8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x32Bf8Fp8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x32_bf8_fp8_e64_dpp" + : "v_swmmac_f32_16x16x32_bf8_fp8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X32_BF8_FP8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1920,13 +2451,23 @@ VSwmmacF3216x16x32Bf8Bf8Vop3p::VSwmmacF3216x16x32Bf8Bf8Vop3p(const MachineInst * src_operands_[3] = &src2; num_src_ = 4; num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_SWMMAC_F32_16X16X32_BF8_BF8 does not support DPP", ""); } namespace detail { -std::unique_ptr decodeVSwmmacF3216x16x32Bf8Bf8Vop3p(const MachineInst *opcode) { +DecodeResult decodeVSwmmacF3216x16x32Bf8Bf8Vop3p(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3p::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_swmmac_f32_16x16x32_bf8_bf8_e64_dpp" + : "v_swmmac_f32_16x16x32_bf8_bf8", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) + [[unlikely]] + return emit_error.emit() << "V_SWMMAC_F32_16X16X32_BF8_BF8 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopc.cpp index c20471dfd2d4..3ba43cd53814 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopc.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/instruction_encoding.h" -#include "util/except.h" #include namespace rocjitsu { @@ -55,7 +54,15 @@ VCmpLtF16Vopc::VCmpLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f16_dpp" + : "v_cmp_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -102,7 +109,15 @@ VCmpEqF16Vopc::VCmpEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f16_dpp" + : "v_cmp_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -149,7 +164,15 @@ VCmpLeF16Vopc::VCmpLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f16_dpp" + : "v_cmp_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -196,7 +219,15 @@ VCmpGtF16Vopc::VCmpGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f16_dpp" + : "v_cmp_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -243,7 +274,15 @@ VCmpLgF16Vopc::VCmpLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f16_dpp" + : "v_cmp_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -290,7 +329,15 @@ VCmpGeF16Vopc::VCmpGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f16_dpp" + : "v_cmp_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -337,7 +384,15 @@ VCmpOF16Vopc::VCmpOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f16_dpp" + : "v_cmp_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -384,7 +439,15 @@ VCmpUF16Vopc::VCmpUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f16_dpp" + : "v_cmp_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -431,7 +494,15 @@ VCmpNgeF16Vopc::VCmpNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f16_dpp" + : "v_cmp_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -478,7 +549,15 @@ VCmpNlgF16Vopc::VCmpNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f16_dpp" + : "v_cmp_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -525,7 +604,15 @@ VCmpNgtF16Vopc::VCmpNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f16_dpp" + : "v_cmp_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -572,7 +659,15 @@ VCmpNleF16Vopc::VCmpNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f16_dpp" + : "v_cmp_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -619,7 +714,15 @@ VCmpNeqF16Vopc::VCmpNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f16_dpp" + : "v_cmp_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -666,7 +769,15 @@ VCmpNltF16Vopc::VCmpNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f16_dpp" + : "v_cmp_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -710,7 +821,15 @@ VCmpLtF32Vopc::VCmpLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f32_dpp" + : "v_cmp_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -754,7 +873,15 @@ VCmpEqF32Vopc::VCmpEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f32_dpp" + : "v_cmp_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -798,7 +925,15 @@ VCmpLeF32Vopc::VCmpLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f32_dpp" + : "v_cmp_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -842,7 +977,15 @@ VCmpGtF32Vopc::VCmpGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f32_dpp" + : "v_cmp_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -886,7 +1029,15 @@ VCmpLgF32Vopc::VCmpLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f32_dpp" + : "v_cmp_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -930,7 +1081,15 @@ VCmpGeF32Vopc::VCmpGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f32_dpp" + : "v_cmp_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -974,7 +1133,15 @@ VCmpOF32Vopc::VCmpOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f32_dpp" + : "v_cmp_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1018,7 +1185,15 @@ VCmpUF32Vopc::VCmpUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f32_dpp" + : "v_cmp_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1062,7 +1237,15 @@ VCmpNgeF32Vopc::VCmpNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f32_dpp" + : "v_cmp_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1106,7 +1289,15 @@ VCmpNlgF32Vopc::VCmpNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f32_dpp" + : "v_cmp_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1150,7 +1341,15 @@ VCmpNgtF32Vopc::VCmpNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f32_dpp" + : "v_cmp_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1194,7 +1393,15 @@ VCmpNleF32Vopc::VCmpNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f32_dpp" + : "v_cmp_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1238,7 +1445,15 @@ VCmpNeqF32Vopc::VCmpNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f32_dpp" + : "v_cmp_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1282,7 +1497,15 @@ VCmpNltF32Vopc::VCmpNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f32_dpp" + : "v_cmp_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1306,14 +1529,22 @@ VCmpLtF64Vopc::VCmpLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_f64_dpp" + : "v_cmp_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1337,14 +1568,22 @@ VCmpEqF64Vopc::VCmpEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_f64_dpp" + : "v_cmp_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1368,14 +1607,22 @@ VCmpLeF64Vopc::VCmpLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_f64_dpp" + : "v_cmp_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1399,14 +1646,22 @@ VCmpGtF64Vopc::VCmpGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_f64_dpp" + : "v_cmp_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1430,14 +1685,22 @@ VCmpLgF64Vopc::VCmpLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lg_f64_dpp" + : "v_cmp_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1461,14 +1724,22 @@ VCmpGeF64Vopc::VCmpGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_f64_dpp" + : "v_cmp_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1492,14 +1763,22 @@ VCmpOF64Vopc::VCmpOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_O_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_o_f64_dpp" + : "v_cmp_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1523,14 +1802,22 @@ VCmpUF64Vopc::VCmpUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_U_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_u_f64_dpp" + : "v_cmp_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1554,14 +1841,22 @@ VCmpNgeF64Vopc::VCmpNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nge_f64_dpp" + : "v_cmp_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1585,14 +1880,22 @@ VCmpNlgF64Vopc::VCmpNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLG_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNlgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlg_f64_dpp" + : "v_cmp_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1616,14 +1919,22 @@ VCmpNgtF64Vopc::VCmpNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NGT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNgtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ngt_f64_dpp" + : "v_cmp_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1647,14 +1958,22 @@ VCmpNleF64Vopc::VCmpNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLE_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNleF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nle_f64_dpp" + : "v_cmp_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1678,14 +1997,22 @@ VCmpNeqF64Vopc::VCmpNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NEQ_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_neq_f64_dpp" + : "v_cmp_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1709,14 +2036,22 @@ VCmpNltF64Vopc::VCmpNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NLT_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNltF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_nlt_f64_dpp" + : "v_cmp_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -1763,7 +2098,15 @@ VCmpLtI16Vopc::VCmpLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i16_dpp" + : "v_cmp_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1810,7 +2153,15 @@ VCmpEqI16Vopc::VCmpEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i16_dpp" + : "v_cmp_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1857,7 +2208,15 @@ VCmpLeI16Vopc::VCmpLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i16_dpp" + : "v_cmp_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1904,7 +2263,15 @@ VCmpGtI16Vopc::VCmpGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i16_dpp" + : "v_cmp_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1951,7 +2318,15 @@ VCmpNeI16Vopc::VCmpNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i16_dpp" + : "v_cmp_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1998,7 +2373,15 @@ VCmpGeI16Vopc::VCmpGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i16_dpp" + : "v_cmp_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2045,7 +2428,15 @@ VCmpLtU16Vopc::VCmpLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u16_dpp" + : "v_cmp_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2092,7 +2483,15 @@ VCmpEqU16Vopc::VCmpEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u16_dpp" + : "v_cmp_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2139,7 +2538,15 @@ VCmpLeU16Vopc::VCmpLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u16_dpp" + : "v_cmp_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2186,7 +2593,15 @@ VCmpGtU16Vopc::VCmpGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u16_dpp" + : "v_cmp_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2233,7 +2648,15 @@ VCmpNeU16Vopc::VCmpNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u16_dpp" + : "v_cmp_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2280,7 +2703,15 @@ VCmpGeU16Vopc::VCmpGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u16_dpp" + : "v_cmp_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2324,7 +2755,15 @@ VCmpLtI32Vopc::VCmpLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i32_dpp" + : "v_cmp_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2368,7 +2807,15 @@ VCmpEqI32Vopc::VCmpEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i32_dpp" + : "v_cmp_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2412,7 +2859,15 @@ VCmpLeI32Vopc::VCmpLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i32_dpp" + : "v_cmp_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2456,7 +2911,15 @@ VCmpGtI32Vopc::VCmpGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i32_dpp" + : "v_cmp_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2500,7 +2963,15 @@ VCmpNeI32Vopc::VCmpNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i32_dpp" + : "v_cmp_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2544,7 +3015,15 @@ VCmpGeI32Vopc::VCmpGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i32_dpp" + : "v_cmp_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2588,7 +3067,15 @@ VCmpLtU32Vopc::VCmpLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u32_dpp" + : "v_cmp_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2632,7 +3119,15 @@ VCmpEqU32Vopc::VCmpEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u32_dpp" + : "v_cmp_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2676,7 +3171,15 @@ VCmpLeU32Vopc::VCmpLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u32_dpp" + : "v_cmp_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2720,7 +3223,15 @@ VCmpGtU32Vopc::VCmpGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u32_dpp" + : "v_cmp_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2764,7 +3275,15 @@ VCmpNeU32Vopc::VCmpNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u32_dpp" + : "v_cmp_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2808,7 +3327,15 @@ VCmpGeU32Vopc::VCmpGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u32_dpp" + : "v_cmp_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -2832,14 +3359,22 @@ VCmpLtI64Vopc::VCmpLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_i64_dpp" + : "v_cmp_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2863,14 +3398,22 @@ VCmpEqI64Vopc::VCmpEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_i64_dpp" + : "v_cmp_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2894,14 +3437,22 @@ VCmpLeI64Vopc::VCmpLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_i64_dpp" + : "v_cmp_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2925,14 +3476,22 @@ VCmpGtI64Vopc::VCmpGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_i64_dpp" + : "v_cmp_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2956,14 +3515,22 @@ VCmpNeI64Vopc::VCmpNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_i64_dpp" + : "v_cmp_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -2987,14 +3554,22 @@ VCmpGeI64Vopc::VCmpGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_I64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_i64_dpp" + : "v_cmp_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3018,14 +3593,22 @@ VCmpLtU64Vopc::VCmpLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_lt_u64_dpp" + : "v_cmp_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3049,14 +3632,22 @@ VCmpEqU64Vopc::VCmpEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_EQ_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_eq_u64_dpp" + : "v_cmp_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3080,14 +3671,22 @@ VCmpLeU64Vopc::VCmpLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_LE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_le_u64_dpp" + : "v_cmp_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3111,14 +3710,22 @@ VCmpGtU64Vopc::VCmpGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GT_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_gt_u64_dpp" + : "v_cmp_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3142,14 +3749,22 @@ VCmpNeU64Vopc::VCmpNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_NE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ne_u64_dpp" + : "v_cmp_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3173,14 +3788,22 @@ VCmpGeU64Vopc::VCmpGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_GE_U64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_ge_u64_dpp" + : "v_cmp_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3227,7 +3850,16 @@ VCmpClassF16Vopc::VCmpClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f16_dpp" + : "v_cmp_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3271,7 +3903,16 @@ VCmpClassF32Vopc::VCmpClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f32_dpp" + : "v_cmp_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3295,14 +3936,23 @@ VCmpClassF64Vopc::VCmpClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMP_CLASS_F64 does not support DPP", ""); vcc.apply_fieldless_caps(false, false, false); } namespace detail { -std::unique_ptr decodeVCmpClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmp_class_f64_dpp" + : "v_cmp_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMP_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -3353,7 +4003,15 @@ VCmpxLtF16Vopc::VCmpxLtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f16_dpp" + : "v_cmpx_lt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3404,7 +4062,15 @@ VCmpxEqF16Vopc::VCmpxEqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f16_dpp" + : "v_cmpx_eq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3455,7 +4121,15 @@ VCmpxLeF16Vopc::VCmpxLeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f16_dpp" + : "v_cmpx_le_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3506,7 +4180,15 @@ VCmpxGtF16Vopc::VCmpxGtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f16_dpp" + : "v_cmpx_gt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3557,7 +4239,15 @@ VCmpxLgF16Vopc::VCmpxLgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f16_dpp" + : "v_cmpx_lg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3608,7 +4298,15 @@ VCmpxGeF16Vopc::VCmpxGeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f16_dpp" + : "v_cmpx_ge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3659,7 +4357,15 @@ VCmpxOF16Vopc::VCmpxOF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f16_dpp" + : "v_cmpx_o_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3710,7 +4416,15 @@ VCmpxUF16Vopc::VCmpxUF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f16_dpp" + : "v_cmpx_u_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3761,7 +4475,16 @@ VCmpxNgeF16Vopc::VCmpxNgeF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f16_dpp" + : "v_cmpx_nge_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3812,7 +4535,16 @@ VCmpxNlgF16Vopc::VCmpxNlgF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f16_dpp" + : "v_cmpx_nlg_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3863,7 +4595,16 @@ VCmpxNgtF16Vopc::VCmpxNgtF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f16_dpp" + : "v_cmpx_ngt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3914,7 +4655,16 @@ VCmpxNleF16Vopc::VCmpxNleF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f16_dpp" + : "v_cmpx_nle_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -3965,7 +4715,16 @@ VCmpxNeqF16Vopc::VCmpxNeqF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f16_dpp" + : "v_cmpx_neq_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4016,7 +4775,16 @@ VCmpxNltF16Vopc::VCmpxNltF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f16_dpp" + : "v_cmpx_nlt_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4064,7 +4832,15 @@ VCmpxLtF32Vopc::VCmpxLtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f32_dpp" + : "v_cmpx_lt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4112,7 +4888,15 @@ VCmpxEqF32Vopc::VCmpxEqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f32_dpp" + : "v_cmpx_eq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4160,7 +4944,15 @@ VCmpxLeF32Vopc::VCmpxLeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f32_dpp" + : "v_cmpx_le_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4208,7 +5000,15 @@ VCmpxGtF32Vopc::VCmpxGtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f32_dpp" + : "v_cmpx_gt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4256,7 +5056,15 @@ VCmpxLgF32Vopc::VCmpxLgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f32_dpp" + : "v_cmpx_lg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4304,7 +5112,15 @@ VCmpxGeF32Vopc::VCmpxGeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f32_dpp" + : "v_cmpx_ge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4352,7 +5168,15 @@ VCmpxOF32Vopc::VCmpxOF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxOF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f32_dpp" + : "v_cmpx_o_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4400,7 +5224,15 @@ VCmpxUF32Vopc::VCmpxUF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxUF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f32_dpp" + : "v_cmpx_u_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4448,7 +5280,16 @@ VCmpxNgeF32Vopc::VCmpxNgeF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgeF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f32_dpp" + : "v_cmpx_nge_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4496,7 +5337,16 @@ VCmpxNlgF32Vopc::VCmpxNlgF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNlgF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f32_dpp" + : "v_cmpx_nlg_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4544,7 +5394,16 @@ VCmpxNgtF32Vopc::VCmpxNgtF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNgtF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f32_dpp" + : "v_cmpx_ngt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4592,7 +5451,16 @@ VCmpxNleF32Vopc::VCmpxNleF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNleF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f32_dpp" + : "v_cmpx_nle_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4640,7 +5508,16 @@ VCmpxNeqF32Vopc::VCmpxNeqF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeqF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f32_dpp" + : "v_cmpx_neq_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4688,7 +5565,16 @@ VCmpxNltF32Vopc::VCmpxNltF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNltF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f32_dpp" + : "v_cmpx_nlt_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -4714,16 +5600,24 @@ VCmpxLtF64Vopc::VCmpxLtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_f64_dpp" + : "v_cmpx_lt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4749,16 +5643,24 @@ VCmpxEqF64Vopc::VCmpxEqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_f64_dpp" + : "v_cmpx_eq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4784,16 +5686,24 @@ VCmpxLeF64Vopc::VCmpxLeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_f64_dpp" + : "v_cmpx_le_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4819,16 +5729,24 @@ VCmpxGtF64Vopc::VCmpxGtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_f64_dpp" + : "v_cmpx_gt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4854,16 +5772,24 @@ VCmpxLgF64Vopc::VCmpxLgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLgF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lg_f64_dpp" + : "v_cmpx_lg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4889,16 +5815,24 @@ VCmpxGeF64Vopc::VCmpxGeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_f64_dpp" + : "v_cmpx_ge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4924,16 +5858,24 @@ VCmpxOF64Vopc::VCmpxOF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_O_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxOF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxOF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_o_f64_dpp" + : "v_cmpx_o_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_O_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4959,16 +5901,24 @@ VCmpxUF64Vopc::VCmpxUF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_U_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxUF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxUF64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_u_f64_dpp" + : "v_cmpx_u_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_U_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -4994,16 +5944,25 @@ VCmpxNgeF64Vopc::VCmpxNgeF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgeF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgeF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nge_f64_dpp" + : "v_cmpx_nge_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5029,16 +5988,25 @@ VCmpxNlgF64Vopc::VCmpxNlgF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLG_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNlgF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNlgF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlg_f64_dpp" + : "v_cmpx_nlg_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLG_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5064,16 +6032,25 @@ VCmpxNgtF64Vopc::VCmpxNgtF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NGT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNgtF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNgtF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ngt_f64_dpp" + : "v_cmpx_ngt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NGT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5099,16 +6076,25 @@ VCmpxNleF64Vopc::VCmpxNleF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLE_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNleF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNleF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nle_f64_dpp" + : "v_cmpx_nle_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLE_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5134,16 +6120,25 @@ VCmpxNeqF64Vopc::VCmpxNeqF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NEQ_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeqF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeqF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_neq_f64_dpp" + : "v_cmpx_neq_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NEQ_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5169,16 +6164,25 @@ VCmpxNltF64Vopc::VCmpxNltF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NLT_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNltF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNltF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_nlt_f64_dpp" + : "v_cmpx_nlt_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NLT_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -5229,7 +6233,15 @@ VCmpxLtI16Vopc::VCmpxLtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i16_dpp" + : "v_cmpx_lt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5280,7 +6292,15 @@ VCmpxEqI16Vopc::VCmpxEqI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i16_dpp" + : "v_cmpx_eq_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5331,7 +6351,15 @@ VCmpxLeI16Vopc::VCmpxLeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i16_dpp" + : "v_cmpx_le_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5382,7 +6410,15 @@ VCmpxGtI16Vopc::VCmpxGtI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i16_dpp" + : "v_cmpx_gt_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5433,7 +6469,15 @@ VCmpxNeI16Vopc::VCmpxNeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i16_dpp" + : "v_cmpx_ne_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5484,7 +6528,15 @@ VCmpxGeI16Vopc::VCmpxGeI16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i16_dpp" + : "v_cmpx_ge_i16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5535,7 +6587,15 @@ VCmpxLtU16Vopc::VCmpxLtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u16_dpp" + : "v_cmpx_lt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5586,7 +6646,15 @@ VCmpxEqU16Vopc::VCmpxEqU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u16_dpp" + : "v_cmpx_eq_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5637,7 +6705,15 @@ VCmpxLeU16Vopc::VCmpxLeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u16_dpp" + : "v_cmpx_le_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5688,7 +6764,15 @@ VCmpxGtU16Vopc::VCmpxGtU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u16_dpp" + : "v_cmpx_gt_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5739,7 +6823,15 @@ VCmpxNeU16Vopc::VCmpxNeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u16_dpp" + : "v_cmpx_ne_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5790,7 +6882,15 @@ VCmpxGeU16Vopc::VCmpxGeU16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU16Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u16_dpp" + : "v_cmpx_ge_u16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5838,7 +6938,15 @@ VCmpxLtI32Vopc::VCmpxLtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i32_dpp" + : "v_cmpx_lt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5886,7 +6994,15 @@ VCmpxEqI32Vopc::VCmpxEqI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i32_dpp" + : "v_cmpx_eq_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5934,7 +7050,15 @@ VCmpxLeI32Vopc::VCmpxLeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i32_dpp" + : "v_cmpx_le_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -5982,7 +7106,15 @@ VCmpxGtI32Vopc::VCmpxGtI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i32_dpp" + : "v_cmpx_gt_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6030,7 +7162,15 @@ VCmpxNeI32Vopc::VCmpxNeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i32_dpp" + : "v_cmpx_ne_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6078,7 +7218,15 @@ VCmpxGeI32Vopc::VCmpxGeI32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeI32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i32_dpp" + : "v_cmpx_ge_i32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6126,7 +7274,15 @@ VCmpxLtU32Vopc::VCmpxLtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u32_dpp" + : "v_cmpx_lt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6174,7 +7330,15 @@ VCmpxEqU32Vopc::VCmpxEqU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxEqU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u32_dpp" + : "v_cmpx_eq_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6222,7 +7386,15 @@ VCmpxLeU32Vopc::VCmpxLeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxLeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u32_dpp" + : "v_cmpx_le_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6270,7 +7442,15 @@ VCmpxGtU32Vopc::VCmpxGtU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGtU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u32_dpp" + : "v_cmpx_gt_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6318,7 +7498,15 @@ VCmpxNeU32Vopc::VCmpxNeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxNeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u32_dpp" + : "v_cmpx_ne_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6366,7 +7554,15 @@ VCmpxGeU32Vopc::VCmpxGeU32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxGeU32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU32Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u32_dpp" + : "v_cmpx_ge_u32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6392,16 +7588,24 @@ VCmpxLtI64Vopc::VCmpxLtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_i64_dpp" + : "v_cmpx_lt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6427,16 +7631,24 @@ VCmpxEqI64Vopc::VCmpxEqI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_i64_dpp" + : "v_cmpx_eq_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6462,16 +7674,24 @@ VCmpxLeI64Vopc::VCmpxLeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_i64_dpp" + : "v_cmpx_le_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6497,16 +7717,24 @@ VCmpxGtI64Vopc::VCmpxGtI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_i64_dpp" + : "v_cmpx_gt_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6532,16 +7760,24 @@ VCmpxNeI64Vopc::VCmpxNeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_i64_dpp" + : "v_cmpx_ne_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6567,16 +7803,24 @@ VCmpxGeI64Vopc::VCmpxGeI64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::SignExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_I64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeI64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeI64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_i64_dpp" + : "v_cmpx_ge_i64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_I64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6602,16 +7846,24 @@ VCmpxLtU64Vopc::VCmpxLtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_lt_u64_dpp" + : "v_cmpx_lt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6637,16 +7889,24 @@ VCmpxEqU64Vopc::VCmpxEqU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_EQ_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxEqU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxEqU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_eq_u64_dpp" + : "v_cmpx_eq_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_EQ_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6672,16 +7932,24 @@ VCmpxLeU64Vopc::VCmpxLeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_LE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxLeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxLeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_le_u64_dpp" + : "v_cmpx_le_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_LE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6707,16 +7975,24 @@ VCmpxGtU64Vopc::VCmpxGtU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GT_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGtU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGtU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_gt_u64_dpp" + : "v_cmpx_gt_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GT_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6742,16 +8018,24 @@ VCmpxNeU64Vopc::VCmpxNeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_NE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxNeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxNeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ne_u64_dpp" + : "v_cmpx_ne_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_NE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6777,16 +8061,24 @@ VCmpxGeU64Vopc::VCmpxGeU64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::ZeroExtend); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_GE_U64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxGeU64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxGeU64Vopc(const MachineInst *opcode, const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_ge_u64_dpp" + : "v_cmpx_ge_u64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_GE_U64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail @@ -6837,7 +8129,16 @@ VCmpxClassF16Vopc::VCmpxClassF16Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF16Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF16Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f16_dpp" + : "v_cmpx_class_f16_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6885,7 +8186,16 @@ VCmpxClassF32Vopc::VCmpxClassF32Vopc(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeVCmpxClassF32Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF32Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f32_dpp" + : "v_cmpx_class_f32_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -6911,16 +8221,25 @@ VCmpxClassF64Vopc::VCmpxClassF64Vopc(const MachineInst *inst) 64, static_cast(reinterpret_cast(inst)->simm32), Operand::Literal32Widening::F64HighBits); - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) - throw util::InvalidInst("V_CMPX_CLASS_F64 does not support DPP", ""); exec.apply_fieldless_caps(false, false, false); sdst_exec.apply_fieldless_caps(false, false, false); flags_ |= WRITES_EXEC; } namespace detail { -std::unique_ptr decodeVCmpxClassF64Vopc(const MachineInst *opcode) { +DecodeResult decodeVCmpxClassF64Vopc(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vopc::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_cmpx_class_f64_dpp" + : "v_cmpx_class_f64_e32", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP || + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) [[unlikely]] + return emit_error.emit() << "V_CMPX_CLASS_F64 does not support DPP"; return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.cpp index a3845ffe7bf1..830af3bde6a8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.cpp @@ -95,6 +95,24 @@ const char *Vopd::op_name(uint16_t op) { } } +Result Vopd::validate_encoding(const MachineInst *inst, const util::DiagnosticEmitter &emit_error) { + const auto *words = reinterpret_cast(inst); + const uint32_t word0 = words[0]; + const uint32_t word1 = words[1]; + + const uint16_t opx = static_cast((word0 >> 22) & 0xF); + const uint16_t opy = static_cast((word0 >> 17) & 0x1F); + if (!is_valid_opcode(opx, kVopdXOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD X opcode"; + if (!is_valid_opcode(opy, kVopdYOpcodeMask)) [[unlikely]] + return emit_error.emit() << "invalid VOPD Y opcode"; + const uint16_t srcx0 = static_cast(word0 & 0x1FF); + const uint16_t srcy0 = static_cast(word1 & 0x1FF); + if (srcx0 == 254 || srcy0 == 254) [[unlikely]] + return emit_error.emit() << "VOPD does not support 64-bit literals"; + return Result::success(); +} + Vopd::Vopd(const MachineInst *inst) : IsaInstruction("vopd", selected_exec_fn(InstructionExecutionId::Vopd)), dstx_(32, OperandType::OPR_VGPR, 0), dsty_(32, OperandType::OPR_VGPR, 0), @@ -110,16 +128,10 @@ Vopd::Vopd(const MachineInst *inst) encoding_id_ = 0x32; opx_ = static_cast((word0_ >> 22) & 0xF); opy_ = static_cast((word0_ >> 17) & 0x1F); - if (!is_valid_opcode(opx_, kVopdXOpcodeMask)) - throw util::InvalidInst("invalid VOPD X opcode", ""); - if (!is_valid_opcode(opy_, kVopdYOpcodeMask)) - throw util::InvalidInst("invalid VOPD Y opcode", ""); uint16_t srcx0 = static_cast(word0_ & 0x1FF); uint16_t vsrcx1 = static_cast((word0_ >> 9) & 0xFF); uint16_t srcy0 = static_cast(word1_ & 0x1FF); uint16_t vsrcy1 = static_cast((word1_ >> 9) & 0xFF); - if (srcx0 == 254 || srcy0 == 254) - throw util::InvalidInst("VOPD does not support 64-bit literals", ""); uint16_t vdstx = static_cast((word1_ >> 24) & 0xFF); uint16_t vdsty_hi = static_cast((word1_ >> 17) & 0x7F); uint16_t vdsty = static_cast((vdsty_hi << 1) | ((~vdstx) & 1u)); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.h index 8b974aa1e445..4f9eb5c7b492 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vopd.h @@ -9,6 +9,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/encodings.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.h" +#include "rocjitsu/isa/decode_result.h" #include #include @@ -18,6 +19,8 @@ namespace rdna4 { class Vopd : public IsaInstruction { public: explicit Vopd(const MachineInst *inst); + static Result validate_encoding(const MachineInst *inst, + const util::DiagnosticEmitter &emit_error); void execute_impl(amdgpu::Wavefront &wf); private: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vsample.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vsample.cpp index 001cd21439b9..31fdae42bc8b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vsample.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vsample.cpp @@ -6,7 +6,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vsample.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" -#include "util/except.h" #include namespace rocjitsu { @@ -27,7 +26,12 @@ ImageMsaaLoadVsample::ImageMsaaLoadVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageMsaaLoadVsample(const MachineInst *opcode) { +DecodeResult decodeImageMsaaLoadVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_msaa_load", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -49,7 +53,12 @@ ImageSampleVsample::ImageSampleVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -71,7 +80,12 @@ ImageSampleDVsample::ImageSampleDVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -93,7 +107,12 @@ ImageSampleLVsample::ImageSampleLVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleLVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -115,7 +134,12 @@ ImageSampleBVsample::ImageSampleBVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleBVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -137,7 +161,12 @@ ImageSampleLzVsample::ImageSampleLzVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -159,7 +188,12 @@ ImageSampleCVsample::ImageSampleCVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -181,7 +215,12 @@ ImageSampleCDVsample::ImageSampleCDVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -203,7 +242,12 @@ ImageSampleCLVsample::ImageSampleCLVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -225,7 +269,12 @@ ImageSampleCBVsample::ImageSampleCBVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -247,7 +296,12 @@ ImageSampleCLzVsample::ImageSampleCLzVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -269,7 +323,12 @@ ImageSampleOVsample::ImageSampleOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -291,7 +350,12 @@ ImageSampleDOVsample::ImageSampleDOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -313,7 +377,12 @@ ImageSampleLOVsample::ImageSampleLOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleLOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -335,7 +404,12 @@ ImageSampleBOVsample::ImageSampleBOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleBOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -357,7 +431,12 @@ ImageSampleLzOVsample::ImageSampleLzOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleLzOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleLzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -379,7 +458,12 @@ ImageSampleCOVsample::ImageSampleCOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -401,7 +485,12 @@ ImageSampleCDOVsample::ImageSampleCDOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -423,7 +512,12 @@ ImageSampleCLOVsample::ImageSampleCLOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_l_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -445,7 +539,12 @@ ImageSampleCBOVsample::ImageSampleCBOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_b_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -467,7 +566,12 @@ ImageSampleCLzOVsample::ImageSampleCLzOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCLzOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCLzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -489,7 +593,12 @@ ImageGather4Vsample::ImageGather4Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4Vsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -511,7 +620,12 @@ ImageGather4LVsample::ImageGather4LVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4LVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -533,7 +647,12 @@ ImageGather4BVsample::ImageGather4BVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4BVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -555,7 +674,12 @@ ImageGather4LzVsample::ImageGather4LzVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -577,7 +701,12 @@ ImageGather4CVsample::ImageGather4CVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -599,7 +728,12 @@ ImageGather4CLzVsample::ImageGather4CLzVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c_lz", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -621,7 +755,12 @@ ImageGather4OVsample::ImageGather4OVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4OVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4OVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -643,7 +782,12 @@ ImageGather4LzOVsample::ImageGather4LzOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4LzOVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4LzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -665,7 +809,12 @@ ImageGather4CLzOVsample::ImageGather4CLzOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLzOVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLzOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c_lz_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -687,7 +836,12 @@ ImageGetLodVsample::ImageGetLodVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGetLodVsample(const MachineInst *opcode) { +DecodeResult decodeImageGetLodVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_get_lod", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -709,7 +863,12 @@ ImageSampleDG16Vsample::ImageSampleDG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -731,7 +890,12 @@ ImageSampleCDG16Vsample::ImageSampleCDG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -753,7 +917,12 @@ ImageSampleDOG16Vsample::ImageSampleDOG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDOG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -775,7 +944,12 @@ ImageSampleCDOG16Vsample::ImageSampleCDOG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDOG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -797,7 +971,12 @@ ImageSampleClVsample::ImageSampleClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -819,7 +998,12 @@ ImageSampleDClVsample::ImageSampleDClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -841,7 +1025,12 @@ ImageSampleBClVsample::ImageSampleBClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -863,7 +1052,12 @@ ImageSampleCClVsample::ImageSampleCClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -885,7 +1079,12 @@ ImageSampleCDClVsample::ImageSampleCDClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -907,7 +1106,12 @@ ImageSampleCBClVsample::ImageSampleCBClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -929,7 +1133,12 @@ ImageSampleClOVsample::ImageSampleClOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleClOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -951,7 +1160,12 @@ ImageSampleDClOVsample::ImageSampleDClOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -973,7 +1187,12 @@ ImageSampleBClOVsample::ImageSampleBClOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleBClOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleBClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -995,7 +1214,12 @@ ImageSampleCClOVsample::ImageSampleCClOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCClOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1017,7 +1241,12 @@ ImageSampleCDClOVsample::ImageSampleCDClOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1039,7 +1268,12 @@ ImageSampleCBClOVsample::ImageSampleCBClOVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCBClOVsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCBClOVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_b_cl_o", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1061,7 +1295,12 @@ ImageSampleCDClG16Vsample::ImageSampleCDClG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_c_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1083,7 +1322,12 @@ ImageSampleDClOG16Vsample::ImageSampleDClOG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClOG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_cl_o_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1105,7 +1349,13 @@ ImageSampleCDClOG16Vsample::ImageSampleCDClOG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleCDClOG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleCDClOG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = + Vsample::validate_encoding("image_sample_c_d_cl_o_g16", + reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1127,7 +1377,12 @@ ImageSampleDClG16Vsample::ImageSampleDClG16Vsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageSampleDClG16Vsample(const MachineInst *opcode) { +DecodeResult decodeImageSampleDClG16Vsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_sample_d_cl_g16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1149,7 +1404,12 @@ ImageGather4ClVsample::ImageGather4ClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4ClVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4ClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1171,7 +1431,12 @@ ImageGather4BClVsample::ImageGather4BClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4BClVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4BClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1193,7 +1458,12 @@ ImageGather4CClVsample::ImageGather4CClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CClVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1215,7 +1485,12 @@ ImageGather4CLVsample::ImageGather4CLVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CLVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CLVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c_l", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1237,7 +1512,12 @@ ImageGather4CBVsample::ImageGather4CBVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c_b", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1259,7 +1539,12 @@ ImageGather4CBClVsample::ImageGather4CBClVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4CBClVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4CBClVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4_c_b_cl", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -1281,7 +1566,12 @@ ImageGather4hVsample::ImageGather4hVsample(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeImageGather4hVsample(const MachineInst *opcode) { +DecodeResult decodeImageGather4hVsample(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vsample::validate_encoding( + "image_gather4h", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vscratch.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vscratch.cpp index d4cb7a9c2dc6..0dfd6e614d3f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vscratch.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/vscratch.cpp @@ -7,7 +7,6 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/vscratch.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/shared/gfx12_cache_flags.h" -#include "util/except.h" #include namespace rocjitsu { @@ -31,7 +30,12 @@ ScratchLoadU8Vscratch::ScratchLoadU8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadU8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -54,7 +58,12 @@ ScratchLoadI8Vscratch::ScratchLoadI8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadI8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -77,7 +86,12 @@ ScratchLoadU16Vscratch::ScratchLoadU16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadU16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadU16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_u16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -100,7 +114,12 @@ ScratchLoadI16Vscratch::ScratchLoadI16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadI16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadI16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_i16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -123,7 +142,12 @@ ScratchLoadB32Vscratch::ScratchLoadB32Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB32Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -146,7 +170,12 @@ ScratchLoadB64Vscratch::ScratchLoadB64Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB64Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -169,7 +198,12 @@ ScratchLoadB96Vscratch::ScratchLoadB96Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB96Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -192,7 +226,12 @@ ScratchLoadB128Vscratch::ScratchLoadB128Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadB128Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -215,7 +254,12 @@ ScratchStoreB8Vscratch::ScratchStoreB8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -238,7 +282,12 @@ ScratchStoreB16Vscratch::ScratchStoreB16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -261,7 +310,12 @@ ScratchStoreB32Vscratch::ScratchStoreB32Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB32Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB32Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b32", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -284,7 +338,12 @@ ScratchStoreB64Vscratch::ScratchStoreB64Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB64Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB64Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b64", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -307,7 +366,12 @@ ScratchStoreB96Vscratch::ScratchStoreB96Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB96Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB96Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b96", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -330,7 +394,12 @@ ScratchStoreB128Vscratch::ScratchStoreB128Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreB128Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreB128Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_b128", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -353,7 +422,12 @@ ScratchLoadD16U8Vscratch::ScratchLoadD16U8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16U8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16U8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -382,7 +456,12 @@ ScratchLoadD16I8Vscratch::ScratchLoadD16I8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16I8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16I8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -411,7 +490,12 @@ ScratchLoadD16B16Vscratch::ScratchLoadD16B16Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16B16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16B16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_b16", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -440,7 +524,12 @@ ScratchLoadD16HiU8Vscratch::ScratchLoadD16HiU8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16HiU8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_hi_u8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -469,7 +558,12 @@ ScratchLoadD16HiI8Vscratch::ScratchLoadD16HiI8Vscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16HiI8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_hi_i8", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -498,7 +592,13 @@ ScratchLoadD16HiB16Vscratch::ScratchLoadD16HiB16Vscratch(const MachineInst *inst } namespace detail { -std::unique_ptr decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_d16_hi_b16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -527,7 +627,13 @@ ScratchStoreD16HiB8Vscratch::ScratchStoreD16HiB8Vscratch(const MachineInst *inst } namespace detail { -std::unique_ptr decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreD16HiB8Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_d16_hi_b8", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -550,7 +656,13 @@ ScratchStoreD16HiB16Vscratch::ScratchStoreD16HiB16Vscratch(const MachineInst *in } namespace detail { -std::unique_ptr decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreD16HiB16Vscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_d16_hi_b16", reinterpret_cast(opcode), + emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -575,7 +687,12 @@ ScratchLoadBlockVscratch::ScratchLoadBlockVscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchLoadBlockVscratch(const MachineInst *opcode) { +DecodeResult decodeScratchLoadBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_load_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail @@ -600,7 +717,12 @@ ScratchStoreBlockVscratch::ScratchStoreBlockVscratch(const MachineInst *inst) } namespace detail { -std::unique_ptr decodeScratchStoreBlockVscratch(const MachineInst *opcode) { +DecodeResult decodeScratchStoreBlockVscratch(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + Result validation = Vscratch::validate_encoding( + "scratch_store_block", reinterpret_cast(opcode), emit_error); + if (validation.failed()) [[unlikely]] + return Result::failure(); return std::make_unique(opcode); } } // namespace detail diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h index a70babaa65f8..eefa0996cbb9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/risc_v/decoder.h @@ -4,6 +4,7 @@ #ifndef ROCJITSU_ISA_RISC_V_DECODER_H_ #define ROCJITSU_ISA_RISC_V_DECODER_H_ +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include @@ -19,8 +20,13 @@ class Decoder { public: static constexpr std::size_t kMaxInstructionWords = 1; static std::unique_ptr decode(uint32_t instr); - static std::unique_ptr decode(const uint32_t *instr) { - return instr == nullptr ? nullptr : decode(*instr); + static DecodeResult decode(const uint32_t *instr, const DecodeErrorEmitter &emit_error) { + if (instr == nullptr) + return emit_error.emit() << "Null instruction encoding"; + auto decoded = decode(*instr); + if (!decoded) + return emit_error.emit() << "Invalid instruction opcode"; + return decoded; } private: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decode_result.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decode_result.h new file mode 100644 index 000000000000..c9f73e7ce011 --- /dev/null +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decode_result.h @@ -0,0 +1,18 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#pragma once + +#include "rocjitsu/result.h" +#include "util/diagnostic.h" + +#include + +namespace rocjitsu { + +class Instruction; + +using DecodeResult = FailureOr>; +using DecodeErrorEmitter = util::DiagnosticEmitter; + +} // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp index 4b379bbdbd97..7b6e8bfa8834 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.cpp @@ -27,21 +27,11 @@ Decoder::~Decoder() { void Decoder::disable_pool() { Instruction::invalidate_allocator_pool(&pool_); } -void Decoder::validate_instruction_operands(const Instruction &inst) { - for (int index = 0; index < inst.num_src_operands(); ++index) { - if (const Operand *operand = inst.src_operand(index)) - operand->validate_encoding(); - } - for (int index = 0; index < inst.num_dst_operands(); ++index) { - if (const Operand *operand = inst.dst_operand(index)) - operand->validate_encoding(); - } -} - -Instruction *Decoder::decode(const rj_code_binary_inst_t *inst, uint64_t src_loc) { - Instruction *decoded = decode(inst); - if (decoded != nullptr) - decoded->src_loc_ = src_loc; +DecodeResult Decoder::decode(const rj_code_binary_inst_t *inst, uint64_t src_loc, + const DecodeErrorEmitter &emit_error) { + DecodeResult decoded = decode(inst, emit_error); + if (decoded.succeeded()) + decoded.value()->src_loc_ = src_loc; return decoded; } @@ -51,4 +41,19 @@ void Decoder::activate_pool(AllocFn alloc, DeallocFn dealloc, void *pool) { Instruction::alloc_pool_ = pool; } +Result Decoder::validate_instruction_operands(const Instruction &inst, + const DecodeErrorEmitter &emit_error) { + for (int index = 0; index < inst.num_src_operands(); ++index) { + if (const Operand *operand = inst.src_operand(index)) + if (operand->validate_encoding(emit_error).failed()) [[unlikely]] + return Result::failure(); + } + for (int index = 0; index < inst.num_dst_operands(); ++index) { + if (const Operand *operand = inst.dst_operand(index)) + if (operand->validate_encoding(emit_error).failed()) [[unlikely]] + return Result::failure(); + } + return Result::success(); +} + } // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h index 799fe3de5d05..98f33de4c547 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/decoder.h @@ -9,6 +9,7 @@ #include "rocjitsu/base/api.h" #include "rocjitsu/code/rj_code.h" +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/execution_backend.h" #include "util/arena_alloc.h" @@ -38,8 +39,15 @@ class Decoder { /// @brief Decode a binary instruction. /// @param[in] inst Pointer to the binary instruction encoding. - /// @returns Decoded Instruction pointer (pool or heap allocated). - virtual Instruction *decode(const rj_code_binary_inst_t *inst) = 0; + /// @param[in] emit_error Diagnostic destination for rejected encodings. + /// @returns A decoded instruction (pool or heap allocated), or failure. + virtual DecodeResult decode(const rj_code_binary_inst_t *inst, + const DecodeErrorEmitter &emit_error) = 0; + + /// @brief Decode silently, for expected speculative rejection. + DecodeResult decode(const rj_code_binary_inst_t *inst) { + return decode(inst, DecodeErrorEmitter{}); + } /// @brief Maximum encoded instruction width and decode lookahead, in 32-bit words. /// @returns A nonzero bound covering both every raw-pointer read and the size of every @@ -54,8 +62,10 @@ class Decoder { /// its location in a larger text stream. /// @param[in] inst Pointer to the binary instruction encoding. /// @param[in] src_loc Source byte offset in the decoded text stream. - /// @returns Decoded Instruction pointer (pool or heap allocated). - Instruction *decode(const rj_code_binary_inst_t *inst, uint64_t src_loc); + /// @param[in] emit_error Diagnostic destination for rejected encodings. + /// @returns A decoded instruction (pool or heap allocated), or failure. + DecodeResult decode(const rj_code_binary_inst_t *inst, uint64_t src_loc, + const DecodeErrorEmitter &emit_error = {}); /// @brief Create a decoder for the given architecture. static std::unique_ptr create(rj_code_arch_t arch); @@ -86,7 +96,8 @@ class Decoder { using DeallocFn = void (*)(void *, void *); static void activate_pool(AllocFn alloc, DeallocFn dealloc, void *pool); - static void validate_instruction_operands(const Instruction &inst); + static Result validate_instruction_operands(const Instruction &inst, + const DecodeErrorEmitter &emit_error); Pool pool_; }; @@ -99,12 +110,15 @@ template class IsaDecoder final : public Decoder { explicit IsaDecoder(const IsaExecutionBackend *execution_backend = nullptr) : execution_backend_(execution_backend) {} - Instruction *decode(const rj_code_binary_inst_t *inst) override { + DecodeResult decode(const rj_code_binary_inst_t *inst, + const DecodeErrorEmitter &emit_error) override { ScopedIsaExecutionBackend scope(execution_backend_); - auto result = Isa::Decoder::decode(inst); - if (result) - validate_instruction_operands(*result); - return result.release(); + DecodeResult result = Isa::Decoder::decode(inst, emit_error); + if (result.failed()) [[unlikely]] + return Result::failure(); + if (validate_instruction_operands(*result.value(), emit_error).failed()) [[unlikely]] + return Result::failure(); + return result; } std::size_t max_instruction_words() const override { return Isa::Decoder::kMaxInstructionWords; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h index 6cc5d4ea4521..b35281d08a9e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/instruction.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_INSTRUCTION_H_ #include "rocjitsu/isa/operand.h" +#include "rocjitsu/result.h" #include "util/intrusive_list.h" #include @@ -419,6 +420,12 @@ template class IsaInstruction : public Instruction { IsaInstruction(std::string_view mnemonic, ExecuteFn exec_fn, uint64_t src_loc = 0) : Instruction(mnemonic, exec_fn, src_loc) {} + /// @brief Accept encodings for formats without additional validation. + template + static constexpr Result validate_encoding([[maybe_unused]] Args &&...args) noexcept { + return Result::success(); + } + /// @brief Helper to create an execute dispatch trampoline for a concrete type. /// /// The returned function pointer casts the base ``Instruction&`` to the diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.cpp index f82fa516f59d..59a786ddee71 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.cpp @@ -3,30 +3,30 @@ #include "rocjitsu/isa/operand.h" #include "simdojo/components/vector_reg.h" -#include "util/except.h" #include #include namespace rocjitsu { -void Operand::validate_encoding() const { +Result Operand::emit_encoding_error(const util::DiagnosticEmitter &emit_error) const { switch (encoding_error_) { - case EncodingError::None: - return; case EncodingError::InvalidSelector: - throw util::InvalidInst("invalid operand selector", ""); + return emit_error.emit() << "invalid operand selector"; case EncodingError::InvalidScalarRegisterSelector: - throw util::InvalidInst("invalid scalar register selector", ""); + return emit_error.emit() << "invalid scalar register selector"; case EncodingError::InvalidLaneSelector: - throw util::InvalidInst("invalid lane selector", ""); + return emit_error.emit() << "invalid lane selector"; case EncodingError::InvalidExecSelector: - throw util::InvalidInst("invalid EXEC selector", ""); + return emit_error.emit() << "invalid EXEC selector"; case EncodingError::InvalidVgprSourceSelector: - throw util::InvalidInst("invalid VGPR source selector", ""); + return emit_error.emit() << "invalid VGPR source selector"; case EncodingError::InvalidScalarSourceSelector: - throw util::InvalidInst("invalid scalar source selector", ""); + return emit_error.emit() << "invalid scalar source selector"; + case EncodingError::None: + break; } + return emit_error.emit() << "unknown operand encoding failure"; } std::optional Operand::to_register_ref() const { return std::nullopt; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.h index 89f0d0be253b..9ebf8ebcef14 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/operand.h @@ -9,6 +9,8 @@ #include "rocjitsu/isa/arch/amdgpu/shared/vgpr_msb.h" #include "rocjitsu/isa/register_set.h" +#include "rocjitsu/result.h" +#include "util/diagnostic.h" #include #include @@ -88,7 +90,11 @@ class Operand { /// Validate encoding constraints deferred until the complete instruction is /// decoded. Literal sentinels may replace their provisional operands first. - void validate_encoding() const; + Result validate_encoding(const util::DiagnosticEmitter &emit_error = {}) const { + if (encoding_error_ == EncodingError::None) [[likely]] + return Result::success(); + return emit_encoding_error(emit_error); + } /// @brief Human-readable name for this operand (e.g. "v0", "s4", or a literal). virtual std::string name() const { return std::to_string(encoding_value_); } @@ -195,6 +201,8 @@ class Operand { } private: + Result emit_encoding_error(const util::DiagnosticEmitter &emit_error) const; + // Value access is intentionally private. Instruction implementations use // RegisterAccess; Operand remains the ISA-specific resolver/backend. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp index eef2f4ee7462..6437bdcc6015 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/rj_decode.cpp @@ -90,11 +90,11 @@ rj_status_t rj_code_decoder_decode(rj_code_decoder_t *decoder, try { Instruction::ScopedHeapAllocation heap_allocation; - std::unique_ptr decoded(decoder->decoder->decode(binary_inst)); - if (!decoded) + DecodeResult decoded = decoder->decoder->decode(binary_inst); + if (decoded.failed()) return ROCJITSU_STATUS_ERROR; - *inst = reinterpret_cast(decoded.release()); + *inst = reinterpret_cast(decoded.value().release()); return ROCJITSU_STATUS_SUCCESS; } catch (const std::bad_alloc &) { return ROCJITSU_STATUS_OUT_OF_RESOURCES; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp index fb0df2892df7..4b2d7f0424bc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp @@ -604,23 +604,16 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { active->trace_inst_count_++; - Instruction *inst = nullptr; - try { - inst = decoder_->decode(words); - } catch (const util::InvalidInst &e) { - util::Logger::vm("CU ", this->name(), ": wf", active->wf_id(), " HALT(InvalidInst) pc=0x", + util::StringDiagnostic decode_error; + DecodeResult decoded = decoder_->decode(words, decode_error.emitter()); + if (decoded.failed()) { + util::Logger::vm("CU ", this->name(), ": wf", active->wf_id(), " HALT(decode rejection) pc=0x", std::hex, active->pc, " words=[0x", words[0], ",0x", words[1], ",0x", words[2], - ",0x", words[3], "]", std::dec, " what=", e.what()); - active->halt(); - return; - } - if (!inst) { - util::Logger::vm("CU ", this->name(), ": wf", active->wf_id(), " HALT(null decode) pc=0x", - std::hex, active->pc, " words=[0x", words[0], ",0x", words[1], ",0x", words[2], - ",0x", words[3], "]", std::dec); + ",0x", words[3], "]", std::dec, " what=", decode_error.message()); active->halt(); return; } + Instruction *inst = decoded.value().release(); int inst_size_signed = inst->size(); assert(inst_size_signed > 0 && "instruction size must be positive"); diff --git a/emulation/rocjitsu/lib/util/include/util/result.h b/emulation/rocjitsu/lib/util/include/util/result.h index e3fc5df99eca..4d1d3bcfdd6c 100644 --- a/emulation/rocjitsu/lib/util/include/util/result.h +++ b/emulation/rocjitsu/lib/util/include/util/result.h @@ -167,4 +167,6 @@ template class [[nodiscard]] FailureOr { FailureOrStorage storage_; }; +template FailureOr(T) -> FailureOr; + } // namespace util diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 28880d95d410..5dd5426d682f 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -1,6 +1,7 @@ // Copyright (c) 2026 Advanced Micro Devices, Inc. // SPDX-License-Identifier: MIT +#include "decode_test_util.h" #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/analysis/exec_state.h" #include "rocjitsu/analysis/indirect_branch_discovery.h" @@ -203,7 +204,7 @@ class TestDecoder : public Decoder { public: std::size_t max_instruction_words() const override { return 1; } - Instruction *decode(const rj_code_binary_inst_t *inst) override { + DecodeResult decode(const rj_code_binary_inst_t *inst, const DecodeErrorEmitter &) override { auto op = static_cast(*inst); switch (op) { case TestOpcode::Nop: @@ -298,7 +299,7 @@ build_test_blocks(std::vector ops, std::span extra_l TestCodeObject co(std::move(words)); TestDecoder decoder; - return BasicBlock::build(co, decoder, ROCJITSU_CODE_ARCH_CDNA3, extra_leaders); + return build_valid_blocks(co, decoder, ROCJITSU_CODE_ARCH_CDNA3, extra_leaders); } bool has_predecessor(const BasicBlock &block, const BasicBlock *pred) { @@ -489,7 +490,7 @@ TEST(RegisterSetAnalysis, Cdna4WritelaneDestinationIsUseAndDef) { constexpr std::array kWritelaneV141S4Lane2 = {0xd28a008du, 0x00010404u}; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); - std::unique_ptr inst(decoder->decode(kWritelaneV141S4Lane2.data())); + std::unique_ptr inst(decode_valid(*decoder, kWritelaneV141S4Lane2.data())); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_writelane_b32"); @@ -535,7 +536,7 @@ TEST(CfgAnalysis, Gfx1250ZeroPaddingTerminatesFallthrough) { TestCodeObject co(test_case.words); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); EXPECT_EQ(blocks[0]->has_implicit_terminator(), test_case.has_implicit_terminator); @@ -552,7 +553,7 @@ TEST(CfgAnalysis, Gfx1250ConditionalBranchKeepsTakenEdgeWhenPaddingTerminatesFal TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 2u); EXPECT_TRUE(blocks[0]->has_implicit_terminator()); @@ -573,7 +574,7 @@ TEST(CfgAnalysis, DirectCallToImplicitNonreturningTargetDropsFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -606,7 +607,7 @@ TEST(CfgAnalysis, DirectCallToPaddingTerminatedBlockWithUnresolvedTakenTargetKee TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -672,7 +673,7 @@ TEST(CfgAnalysis, StandaloneInstructionHasNoDecodedNeighbors) { constexpr uint32_t kNop = 0xbf800000u; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(&kNop)); + std::unique_ptr instruction(decode_valid(*decoder, &kNop)); ASSERT_NE(instruction, nullptr); EXPECT_EQ(instruction->previous_instruction(), nullptr); @@ -758,7 +759,7 @@ TEST(CfgAnalysis, IndirectRecoveryPrefilterAdmitsSetPcConsumer) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{16}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); auto *builder = block_starting_at(blocks, 0); auto *consumer = block_starting_at(blocks, 16); @@ -797,7 +798,7 @@ TEST(CfgAnalysis, PcBuilderWithoutConsumerProducesNoRecoveredEdge) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); ASSERT_EQ(blocks.size(), 1u); EXPECT_TRUE(blocks[0]->static_indirect_call_fixups().empty()); @@ -831,7 +832,7 @@ TEST(CfgAnalysis, RecoversMultipleSgprPairsFromOneBlockEntry) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *first_consumer = block_starting_at(blocks, 36); auto *second_consumer = block_starting_at(blocks, 40); @@ -854,7 +855,7 @@ TEST(CfgAnalysis, OutOfRangeIndirectConsumersRemainUnresolved) { TestCodeObject co(std::vector{consumer}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); ASSERT_EQ(blocks.size(), 1u); EXPECT_TRUE(blocks[0]->static_indirect_call_fixups().empty()); @@ -885,7 +886,7 @@ TEST(CfgAnalysis, IgnoresUnconsumedPairWhileRecoveringPendingConsumer) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{20}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); auto *consumer = block_starting_at(blocks, 20); ASSERT_NE(consumer, nullptr); @@ -922,7 +923,7 @@ TEST(CfgAnalysis, IncompleteFactConsumerIsFlaggedIncomplete) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 28); ASSERT_NE(consumer, nullptr); @@ -955,7 +956,7 @@ TEST(CfgAnalysis, IncompleteSwappcTargetSetKeepsContinuation) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 28); auto *continuation = block_starting_at(blocks, 32); @@ -995,7 +996,7 @@ TEST(CfgAnalysis, IncompleteRecoveredSetpcInCalleeKeepsOuterContinuation) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1035,7 +1036,7 @@ TEST(CfgAnalysis, ReportsResolvedPcAddressBuilderForEveryProducer) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *builder_block = block_starting_at(blocks, 0); ASSERT_NE(builder_block, nullptr); @@ -1076,7 +1077,7 @@ TEST(CfgAnalysis, PcAddressBuilderWithGapInstructionIsReportedNonContiguous) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *builder_block = block_starting_at(blocks, 0); ASSERT_NE(builder_block, nullptr); @@ -1106,7 +1107,7 @@ TEST(CfgAnalysis, UnfollowedPcAddressBuilderIsReportedUnresolved) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *builder_block = block_starting_at(blocks, 0); ASSERT_NE(builder_block, nullptr); @@ -1144,7 +1145,7 @@ TEST(CfgAnalysis, DominatedPcBuilderRemainsCompleteAcrossCallLoopBackedge) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 20); ASSERT_NE(consumer, nullptr); @@ -1183,7 +1184,7 @@ TEST(CfgAnalysis, SeedsTextEntryWithLoopBackedgeForCrossBlockPcBuilder) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 24); ASSERT_NE(consumer, nullptr); @@ -1218,7 +1219,7 @@ TEST(CfgAnalysis, MultipleUnorderedExplicitEntriesMakeIncomingPcBuilderIncomplet auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{28, 24, 28}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); for (uint64_t consumer_offset : {uint64_t{24}, uint64_t{28}}) { auto *consumer = block_starting_at(blocks, consumer_offset); @@ -1253,7 +1254,7 @@ TEST(CfgAnalysis, RocrAbortTrapStopsTemporaryPcBuilderCfg) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{20}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); auto *consumer = block_starting_at(blocks, 20); ASSERT_NE(consumer, nullptr); @@ -1296,8 +1297,8 @@ TEST(CfgAnalysis, UnreachablePostRocrAbortBlockDoesNotPoisonPcBuilder) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, {}, - ExternalEntryPolicy::ExplicitOnly); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, {}, + ExternalEntryPolicy::ExplicitOnly); auto *consumer = block_starting_at(blocks, 32); ASSERT_NE(consumer, nullptr); @@ -1332,7 +1333,7 @@ TEST(CfgAnalysis, DefaultEntryPolicyRecoversPredecessorlessFunction) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 24); ASSERT_NE(consumer, nullptr); @@ -1357,7 +1358,7 @@ TEST(CfgAnalysis, DirectCallEdgeUsesTerminatorOffset) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 8); @@ -1390,7 +1391,7 @@ TEST(BinaryTranslatorInternal, ScopeRootsRejectRelocationTableCallee) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *callee = block_starting_at(blocks, 8); @@ -1430,7 +1431,7 @@ TEST(CfgAnalysis, DirectCallToNonreturningTargetDropsFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1459,7 +1460,7 @@ TEST(CfgAnalysis, DirectCallWithCopiedReturnPairKeepsFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1487,7 +1488,7 @@ TEST(CfgAnalysis, DirectCallWithUnrecoveredTailExitKeepsFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1517,7 +1518,7 @@ TEST(CfgAnalysis, DirectCallCrossingScopeBoundaryKeepsFallthrough) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{16}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1549,7 +1550,7 @@ TEST(CfgAnalysis, NestedReturningCallMayReturnThroughOuterPair) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *outer = block_starting_at(blocks, 0); auto *outer_continuation = block_starting_at(blocks, 4); @@ -1577,7 +1578,7 @@ TEST(CfgAnalysis, NestedNonreturningCallsDropBothFallthroughs) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *outer = block_starting_at(blocks, 0); auto *outer_continuation = block_starting_at(blocks, 4); @@ -1612,7 +1613,7 @@ TEST(CfgAnalysis, CyclicCallGraphKeepsConservativeFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1635,7 +1636,7 @@ TEST(CfgAnalysis, CallToInfiniteLoopDropsFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1660,7 +1661,7 @@ TEST(CfgAnalysis, ZeroDeltaCallToNonreturningTargetKeepsSingleEdge) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *caller = block_starting_at(blocks, 0); auto *target = block_starting_at(blocks, 4); @@ -1699,7 +1700,7 @@ TEST(CfgAnalysis, DirectCallKillsCarriedPcBuilderFacts) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *continuation = block_starting_at(blocks, 20); auto *stale_target = block_starting_at(blocks, 32); @@ -1746,7 +1747,7 @@ TEST(CfgAnalysis, EitherHalfKillPredecessorPreventsRecoveredConsumer) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{40}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, extra_leaders); auto *consumer = block_starting_at(blocks, 32); auto *target = block_starting_at(blocks, 40); @@ -1790,7 +1791,7 @@ TEST(CfgAnalysis, RecoversSignedDeltaTemplateConsumers) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *sub_consumer = block_starting_at(blocks, 32); auto *add_consumer = block_starting_at(blocks, 44); @@ -1837,7 +1838,7 @@ TEST(CfgAnalysis, KeepsDistinctBuildersReachingSameTarget) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 32); ASSERT_NE(consumer, nullptr); @@ -1871,7 +1872,7 @@ TEST(CfgAnalysis, RecoveredSwappcToNonreturningTargetDropsFallthrough) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 16); auto *continuation = block_starting_at(blocks, 20); @@ -1912,7 +1913,7 @@ TEST(CfgAnalysis, MixedSwappcTargetsKeepSharedContinuation) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); auto *consumer = block_starting_at(blocks, 32); auto *continuation = block_starting_at(blocks, 36); @@ -1988,7 +1989,7 @@ TEST(CfgAnalysis, Gfx1250RecoversSignedDeltaTemplateWithPrefetch) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *sub_consumer = block_starting_at(blocks, 44); auto *add_consumer = block_starting_at(blocks, 68); @@ -2064,7 +2065,7 @@ TEST(CfgAnalysis, Gfx1250RecoversSignedDeltaTemplateWithXcntWaitAndPrefetch) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *sub_consumer = block_starting_at(blocks, 44); auto *add_consumer = block_starting_at(blocks, 68); @@ -2145,7 +2146,7 @@ TEST(CfgAnalysis, Gfx1250SignedDeltaRejectsMoveClobberingTemporary) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); // Clobbering the temporary on the subtract half breaks that half of the paired // signed-delta template. Because the two halves cross-validate to the same static @@ -2186,7 +2187,7 @@ TEST(CfgAnalysis, IndirectRecoveryPrefilterAdmitsGfx1250LaneStashSwapPc) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 48); auto *target = block_starting_at(blocks, 56); @@ -2229,7 +2230,7 @@ TEST(CfgAnalysis, Gfx1250WideVgprWriteInvalidatesStashedLane) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); size_t total_fixups = 0; for (const auto &block : blocks) @@ -2273,7 +2274,7 @@ TEST(CfgAnalysis, Gfx1250ExplicitVgprWriteInvalidatesOnlyItsDestinationBank) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 68); ASSERT_NE(consumer, nullptr); @@ -2308,7 +2309,7 @@ TEST(CfgAnalysis, Gfx1250CarriesLaneStashAcrossProvenBlockBoundary) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 52); ASSERT_NE(consumer, nullptr); @@ -2355,8 +2356,8 @@ TEST(CfgAnalysis, Gfx1250UnreachablePostRocrAbortBlockDoesNotPoisonLaneStash) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, {}, - ExternalEntryPolicy::ExplicitOnly); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, {}, + ExternalEntryPolicy::ExplicitOnly); auto *consumer = block_starting_at(blocks, 64); ASSERT_NE(consumer, nullptr); @@ -2399,8 +2400,8 @@ TEST(CfgAnalysis, Gfx1250ExplicitOnlyRecoversLaneStashInRecoveredCallee) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, {}, - ExternalEntryPolicy::ExplicitOnly); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, {}, + ExternalEntryPolicy::ExplicitOnly); auto *outer_consumer = block_starting_at(blocks, 16); auto *inner_consumer = block_starting_at(blocks, 80); @@ -2444,7 +2445,7 @@ TEST(CfgAnalysis, Gfx1250DirectCallKillsCarriedLaneStash) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); size_t total_fixups = 0; for (const auto &block : blocks) @@ -2482,7 +2483,7 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryPreservesUnwrittenCallerSavedLaneStas TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2525,7 +2526,7 @@ TEST(CfgAnalysis, Gfx1250RelativeVgprDestinationDisablesExactCalleeSummary) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2570,7 +2571,7 @@ TEST(CfgAnalysis, Gfx1250GprIndexedVgprDestinationDisablesExactCalleeSummary) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2612,7 +2613,7 @@ TEST(CfgAnalysis, Gfx1250RelativeSgprDestinationDisablesExactCalleeSummary) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2653,7 +2654,7 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedLaneStashSurvivesDirectCall) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2709,7 +2710,7 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryPreservesBankedLaneStash) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2753,7 +2754,7 @@ TEST(CfgAnalysis, Gfx1250CalleeModeChangeInvalidatesContinuationBankSelection) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2811,7 +2812,7 @@ TEST(CfgAnalysis, Gfx1250IndirectCallKillsCarriedLaneStash) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); size_t total_fixups = 0; const IndirectCallFixup *call_fixup = nullptr; @@ -2876,7 +2877,7 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedLaneStashSurvivesIndirectCall) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2923,7 +2924,7 @@ TEST(CfgAnalysis, Gfx1250SeedsTextEntryWithLoopBackedgeForLaneStash) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 56); ASSERT_NE(consumer, nullptr); @@ -2964,7 +2965,7 @@ TEST(CfgAnalysis, Gfx1250ExplicitKernelEntryClearsIncomingLaneStash) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{40}; - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, extra_leaders); size_t total_fixups = 0; for (const auto &block : blocks) @@ -3001,7 +3002,7 @@ TEST(CfgAnalysis, Gfx1250A0UsesLowByteOfVgprMsb) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 56); ASSERT_NE(consumer, nullptr); @@ -3041,7 +3042,7 @@ TEST(CfgAnalysis, Gfx1250ImmediateModeWriteKeepsLaneStashBankKnown) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 60); ASSERT_NE(consumer, nullptr); @@ -3073,7 +3074,7 @@ TEST(CfgAnalysis, Gfx1250LaneRestoreReachesConsumerAcrossBranch) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 52); ASSERT_NE(consumer, nullptr); @@ -3104,7 +3105,7 @@ TEST(CfgAnalysis, Gfx1250PcPairCopyReachesConsumer) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *copied_call = nullptr; for (const auto &block : blocks) { @@ -3140,7 +3141,7 @@ TEST(CfgAnalysis, Gfx1250DirectCallOverwritesPcBuilderInReturnPair) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -3170,7 +3171,7 @@ TEST(CfgAnalysis, Gfx1250SwapPcOverwritesPcBuilderInReturnPair) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *first_call = nullptr; for (const auto &block : blocks) { @@ -3232,7 +3233,7 @@ TEST(CfgAnalysis, Gfx1250CalleeSummaryRejectsRepurposedReturnPair) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -3272,7 +3273,7 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryPreservesUnwrittenRestoredSgprs) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *fixup = nullptr; for (const auto &block : blocks) { @@ -3344,7 +3345,7 @@ TEST(CfgAnalysis, Gfx1250CalleeSummaryVariantLimitFallsBackConservatively) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); EXPECT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); return std::ranges::any_of(blocks, [&](const auto &block) { return std::ranges::any_of(block->static_indirect_call_fixups(), @@ -3389,7 +3390,7 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryDropsWrittenRestoredSgprs) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *fixup = nullptr; for (const auto &block : blocks) { @@ -3439,7 +3440,7 @@ TEST(CfgAnalysis, Gfx1250UnsupportedCalleeSummaryFallsBackToCallPreservedSgprs) TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *fixup = nullptr; for (const auto &block : blocks) { @@ -3498,7 +3499,7 @@ TEST(CfgAnalysis, Gfx1250RestashedLaneTargetRemainsRecoverable) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 80); ASSERT_NE(consumer, nullptr); @@ -3537,7 +3538,7 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedPcBuilderCanBeStashedAfterCall) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); const IndirectCallFixup *second_call = nullptr; for (const auto &block : blocks) { @@ -3585,7 +3586,7 @@ TEST(CfgAnalysis, Gfx1250DoesNotRecoverLaneStashWithDifferingRoleBanks) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); size_t total_fixups = 0; for (const auto &block : blocks) @@ -3626,7 +3627,7 @@ TEST(CfgAnalysis, Gfx1250InheritsBankAlongProvenCfgEdge) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto *consumer = block_starting_at(blocks, 56); ASSERT_NE(consumer, nullptr); @@ -3689,7 +3690,7 @@ TEST(CfgAnalysis, Gfx1250DoesNotReuseStashFromSkippedFallthroughPredecessor) { byte_offset += sizeof(uint32_t); continue; } - std::unique_ptr inst(decoder->decode(&inst_data[pc], byte_offset)); + std::unique_ptr inst(decode_valid(*decoder, &inst_data[pc], byte_offset)); ASSERT_NE(inst, nullptr); const uint32_t inst_words = static_cast(inst->size()) / sizeof(uint32_t); byte_offset += inst->size(); @@ -3734,7 +3735,7 @@ void run_indirect_discovery_for_test(std::vector words, byte_offset += sizeof(uint32_t); continue; } - std::unique_ptr inst(decoder->decode(&inst_data[pc], byte_offset)); + std::unique_ptr inst(decode_valid(*decoder, &inst_data[pc], byte_offset)); ASSERT_NE(inst, nullptr); const uint32_t inst_words = static_cast(inst->size()) / sizeof(uint32_t); byte_offset += inst->size(); @@ -3899,7 +3900,7 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbResolvesPhysicalRegisterBank) { TestCodeObject co({set_vgpr_msb[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -3936,7 +3937,7 @@ TEST(LivenessAnalysis, Gfx1250ImplicitVgprUseResolvesDestinationBank) { TestCodeObject co({set_dst_bank_two[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -3968,7 +3969,7 @@ TEST(LivenessAnalysis, Gfx1250D16LoadImplicitUseResolvesDestinationBank) { TestCodeObject co({set_dst_bank_two[0], load[0], load[1], load[2], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4001,7 +4002,7 @@ TEST(LivenessAnalysis, Gfx1250ImplicitVgprUseResolvesDespiteExplicitBank0Alias) TestCodeObject co({set_dst_bank_two[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4034,7 +4035,7 @@ TEST(LivenessAnalysis, Gfx1250SwapImplicitReadsResolvePerRole) { TestCodeObject co({set_banks[0], swap[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4087,7 +4088,7 @@ TEST(LivenessAnalysis, Gfx1250DppPreserveReadResolvesToDstBank) { TestCodeObject co({set_banks[0], kDppMovWord0, kDppWord1Partial, end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4121,7 +4122,7 @@ TEST(LivenessAnalysis, Gfx1250ImplicitVgprUseUnknownBankReadsEveryCandidate) { TestCodeObject co({setreg[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4155,7 +4156,7 @@ TEST(LivenessAnalysis, Gfx1250UnknownBankDefMakesEveryCandidateGloballyUsed) { TestCodeObject co({setreg[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4194,7 +4195,7 @@ TEST(LivenessAnalysis, Gfx1250RelativeVgprAccessDisablesGlobalUnusedQuery) { TestCodeObject co({move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4217,7 +4218,7 @@ TEST(LivenessAnalysis, Gfx1250SwaprelDisablesGlobalUnusedQuery) { TestCodeObject co({swap[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4245,7 +4246,7 @@ TEST(LivenessAnalysis, Gfx1250GprIndexModeWriteDisablesGlobalUnusedQuery) { TestCodeObject co({setreg[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4276,7 +4277,7 @@ TEST(LivenessAnalysis, Gfx1250ImmediateGprIndexModeWriteUsesLiteralValue) { TestCodeObject co({setreg[0], literal, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4309,7 +4310,7 @@ TEST(LivenessAnalysis, Cdna4DynamicGprIndexModeWriteDisablesGlobalUnusedQuery) { TestCodeObject co({setreg[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4339,7 +4340,7 @@ TEST(LivenessAnalysis, Cdna4ImmediateGprIndexModeWriteUsesLiteralValue) { TestCodeObject co({setreg[0], literal, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4371,7 +4372,7 @@ TEST(LivenessAnalysis, Gfx1250DynamicModeWriteConservativelyUsesEveryBank) { TestCodeObject co({setreg[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4406,7 +4407,7 @@ TEST(LivenessAnalysis, Gfx1250FullLiteralModeWriteRecoversKnownBank) { TestCodeObject co({dynamic_setreg[0], literal_setreg[0], 2u, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4446,7 +4447,7 @@ TEST(LivenessAnalysis, Gfx1250TruncatedLiteralModeWriteMarksBanksAmbiguous) { TestCodeObject co({set_bank_two[0], literal_setreg[0], 0xe4u, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4480,7 +4481,7 @@ TEST(LivenessAnalysis, Gfx1250PartialLiteralModeWritePreservesUntouchedBankBit) TestCodeObject co({set_bank_one[0], literal_setreg[0], 1u, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4511,7 +4512,7 @@ TEST(LivenessAnalysis, Gfx1250ImmediateModeWritePreservesBanksOutsideRequestedSl TestCodeObject co({set_bank_one[0], literal_setreg[0], 0u, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4540,7 +4541,7 @@ TEST(LivenessAnalysis, Gfx1250LiteralModeWriteTracksEveryRole) { TestCodeObject co({literal_setreg[0], kModeFields, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4570,7 +4571,7 @@ TEST(LivenessAnalysis, Gfx1250ImmediateNonModeWriteDoesNotChangeBanks) { TestCodeObject co({literal_setreg[0], 0x000ff000u, move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); @@ -4602,7 +4603,7 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbCfgJoinRequiresPredecessorsToAgree) { {branch_to_else[0], set_bank_two[0], branch_to_join[0], set_bank_zero[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto scope = block_scope(blocks); BasicBlock *join = block_starting_at(blocks, 16); ASSERT_NE(join, nullptr); @@ -4632,7 +4633,7 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbCfgJoinPreservesAgreeingBank) { {branch_to_else[0], set_bank_two[0], branch_to_join[0], set_bank_two[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto scope = block_scope(blocks); BasicBlock *join = block_starting_at(blocks, 16); ASSERT_NE(join, nullptr); @@ -4673,7 +4674,7 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbJoinExcludesUnreachablePredecessor) { TestCodeObject co({branch_over[0], set_bank_zero[0], set_bank_two[0], move[0], end[0]}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); auto scope = block_scope(blocks); LivenessAnalysisOptions options; @@ -4708,7 +4709,7 @@ std::vector insts_of(BasicBlock &block) { std::vector> build_cdna4_blocks(std::vector words) { TestCodeObject co(std::move(words)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); - return BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + return build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4); } // Full end-to-end on real decoded instructions: `s_mov_b64 exec, -1` makes EXEC @@ -5430,12 +5431,12 @@ constexpr uint32_t kVop1MovWord0Sdwa = (0x3Fu << 25) | (5u << 17) | (1u << 9) | std::unique_ptr decode_cdna4(const std::array &words) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); - return std::unique_ptr(decoder ? decoder->decode(words.data()) : nullptr); + return std::unique_ptr(decoder ? decode_valid(*decoder, words.data()) : nullptr); } std::unique_ptr decode_gfx1250(const std::array &words) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); - return std::unique_ptr(decoder ? decoder->decode(words.data()) : nullptr); + return std::unique_ptr(decoder ? decode_valid(*decoder, words.data()) : nullptr); } TEST(GeneratedInstDefUse, Gfx1250Vop3CompareDefinesOneSgpr) { @@ -5657,7 +5658,7 @@ std::unique_ptr decode_rdna4(std::initializer_list words) std::array buf{}; std::copy(words.begin(), words.end(), buf.begin()); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); - return std::unique_ptr(decoder ? decoder->decode(buf.data()) : nullptr); + return std::unique_ptr(decoder ? decode_valid(*decoder, buf.data()) : nullptr); } TEST(GeneratedInstDefUse, Vop3DppPartialRowMaskReadsVgprDestination) { @@ -5788,7 +5789,7 @@ TEST(GeneratedInstDefUse, WritelaneReadsDestinationGfx1250) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); std::array words{0xD7610005U, 0x00000404U, 0U, 0U}; - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_writelane_b32"); @@ -5882,7 +5883,7 @@ std::unique_ptr decode_cdna3(std::initializer_list words) std::array buf{}; std::copy(words.begin(), words.end(), buf.begin()); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); - return std::unique_ptr(decoder ? decoder->decode(buf.data()) : nullptr); + return std::unique_ptr(decoder ? decode_valid(*decoder, buf.data()) : nullptr); } TEST(GeneratedInstDefUse, D16TbufferLoadReadsDestination) { diff --git a/emulation/rocjitsu/tests/buffer_operand_test.cpp b/emulation/rocjitsu/tests/buffer_operand_test.cpp index 14e0b2679cb5..21af9d1df277 100644 --- a/emulation/rocjitsu/tests/buffer_operand_test.cpp +++ b/emulation/rocjitsu/tests/buffer_operand_test.cpp @@ -4,6 +4,7 @@ /// @file buffer_operand_test.cpp /// @brief Regression tests for semantic legacy buffer operands. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -46,7 +47,7 @@ TEST_P(BufferOperandTest, AddressModeAndResourceUsePhysicalRegisters) { // VADDR=63, VDATA=68, raw SRSRC=1 (descriptor s[4:7]), SOFFSET=128 (zero). const uint32_t words[] = {tc.encoding | (tc.address_mode_in_hi_word ? 0u : mode.fields << 12), 0x8001443fu | (tc.address_mode_in_hi_word ? mode.fields << 22 : 0u)}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr) << tc.label; ASSERT_EQ(inst->mnemonic(), tc.mnemonic) << tc.label; ASSERT_GE(inst->num_src_operands(), 2) << tc.label; @@ -83,7 +84,7 @@ TEST_P(BufferOperandTest, AddressModeAndResourceUsePhysicalRegisters) { // address components enabled to cover the acc fold together with VADDR // width and SRSRC scaling. const uint32_t words[] = {tc.encoding | (3u << 12), 0x8081443fu}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr) << tc.label; const auto vaddr = inst->src_operand(0)->to_register_ref(); diff --git a/emulation/rocjitsu/tests/cdna3_predicate_mask_test.cpp b/emulation/rocjitsu/tests/cdna3_predicate_mask_test.cpp index 287b23c94da7..20132f2f1970 100644 --- a/emulation/rocjitsu/tests/cdna3_predicate_mask_test.cpp +++ b/emulation/rocjitsu/tests/cdna3_predicate_mask_test.cpp @@ -4,6 +4,7 @@ /// @file cdna3_predicate_mask_test.cpp /// @brief CDNA3 predicate-mask semantics from hip-fpsan algebraic kernels. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -81,7 +82,7 @@ struct Fixture { } void execute(const std::array &words) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst.get(), *wf); } diff --git a/emulation/rocjitsu/tests/cdna5_architecture_test.cpp b/emulation/rocjitsu/tests/cdna5_architecture_test.cpp index 97e61491e7a2..3548d429b559 100644 --- a/emulation/rocjitsu/tests/cdna5_architecture_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_architecture_test.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: MIT #include "cdna5_sim_test_common.h" +#include "decode_test_util.h" namespace { @@ -135,7 +136,7 @@ TEST(Gfx1250CodeObjectTest, MachineFlagMapsToTarget) { ASSERT_NE(decoder, nullptr); const auto *text = co.text_sections()[0]; auto *words = reinterpret_cast(text->data()); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_endpgm"); } @@ -149,7 +150,7 @@ TEST(Gfx1250DecodeTest, SMovB64Literal64ConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_mov_b64"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -166,7 +167,7 @@ TEST(Gfx1250DecodeTest, ScalarSourceRejectsReservedSelector) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vop3LiteralConsumesThreeDwords) { @@ -178,7 +179,7 @@ TEST(Gfx1250DecodeTest, Vop3LiteralConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_and_or_b32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -192,7 +193,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsLiteral64Selector) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vop1RejectsUnsupportedLiteral32WithoutExtensionWord) { @@ -200,7 +201,7 @@ TEST(Gfx1250DecodeTest, Vop1RejectsUnsupportedLiteral32WithoutExtensionWord) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral32WithoutExtensionWord) { @@ -208,7 +209,7 @@ TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral32WithoutExtensionWord) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral64WithoutExtensionWords) { @@ -216,7 +217,7 @@ TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral64WithoutExtensionWords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } TEST(Gfx1250DecodeTest, SaluRejectsMixedLiteralWidths) { @@ -228,7 +229,7 @@ TEST(Gfx1250DecodeTest, SaluRejectsMixedLiteralWidths) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, SendmsgRtnSelectorsAreNotLiterals) { @@ -238,7 +239,7 @@ TEST(Gfx1250DecodeTest, SendmsgRtnSelectorsAreNotLiterals) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_sendmsg_rtn_b32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -253,7 +254,7 @@ TEST(Gfx1250DecodeTest, VopdRejectsLiteral64Selector) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vop3RejectsDppWithLiteral) { @@ -265,7 +266,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsDppWithLiteral) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vop3RejectsInvalidScalarDestination) { @@ -277,7 +278,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsInvalidScalarDestination) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vop3RejectsInvalidVgprSource) { @@ -288,7 +289,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsInvalidVgprSource) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vop3ReadlaneValidatesLaneSelector) { @@ -303,10 +304,10 @@ TEST(Gfx1250DecodeTest, Vop3ReadlaneValidatesLaneSelector) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr valid(decoder->decode(valid_words)); + std::unique_ptr valid(decode_valid(*decoder, valid_words)); ASSERT_NE(valid, nullptr); EXPECT_EQ(valid->disassemble(), "v_readlane_b32 s0, v215, 1"); - EXPECT_THROW(std::unique_ptr(decoder->decode(invalid_words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, invalid_words)); } TEST(Gfx1250DecodeTest, Vop3CmpxValidatesExecDestination) { @@ -321,10 +322,10 @@ TEST(Gfx1250DecodeTest, Vop3CmpxValidatesExecDestination) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr valid(decoder->decode(valid_words)); + std::unique_ptr valid(decode_valid(*decoder, valid_words)); ASSERT_NE(valid, nullptr); EXPECT_EQ(valid->disassemble(), "v_cmpx_ne_u32 exec, v0, v1"); - EXPECT_THROW(std::unique_ptr(decoder->decode(invalid_words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, invalid_words)); } TEST(Gfx1250DecodeTest, Vop3SdstLiteralConsumesThreeDwords) { @@ -336,7 +337,7 @@ TEST(Gfx1250DecodeTest, Vop3SdstLiteralConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_subrev_co_u32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -351,12 +352,12 @@ TEST(Gfx1250DecodeTest, VFmamkF64ImpliedLiteralConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr fmamk(decoder->decode(words)); + std::unique_ptr fmamk(decode_valid(*decoder, words)); ASSERT_NE(fmamk, nullptr); EXPECT_EQ(fmamk->mnemonic(), "v_fmamk_f64_e32"); EXPECT_EQ(fmamk->size(), 3 * sizeof(uint32_t)); - std::unique_ptr next(decoder->decode(words + 3)); + std::unique_ptr next(decode_valid(*decoder, words + 3)); ASSERT_NE(next, nullptr); EXPECT_EQ(next->mnemonic(), "v_cvt_u32_f64_e32"); } @@ -368,7 +369,7 @@ TEST(Gfx1250DecodeTest, SWaitXcntHasWaitcntMetadata) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_wait_xcnt"); EXPECT_TRUE(inst->is_waitcnt()); @@ -384,7 +385,7 @@ TEST(Gfx1250DecodeTest, BufferOffenUsesSingleVaddrRegister) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->mnemonic(), "buffer_load_b128"); ASSERT_EQ(inst->num_dst_operands(), 1); @@ -425,7 +426,7 @@ TEST(Gfx1250DecodeTest, BufferWithoutIdxenOffenDoesNotExposeVaddrRegister) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->mnemonic(), "buffer_load_b128"); ASSERT_EQ(inst->num_dst_operands(), 1); @@ -454,7 +455,7 @@ TEST(Gfx1250DecodeTest, WmmaF8f6f4UsesMatrixFormatOperandWidths) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->disassemble(), "v_wmma_f32_16x16x128_f8f6f4 v[16:23], v[0:7], v[8:15], v[16:23] " "matrix_a_fmt:MATRIX_FMT_FP4 matrix_b_fmt:MATRIX_FMT_FP4"); @@ -470,7 +471,7 @@ TEST(Gfx1250DecodeTest, WmmaScaleF8f6f4ConsumesVop3px2Pair) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_wmma_scale_f32_16x16x128_f8f6f4"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -491,7 +492,7 @@ TEST(Gfx1250DecodeTest, WmmaScalePairRejectsInvalidEmbeddedSourceSelectors) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } } @@ -505,7 +506,7 @@ TEST(Gfx1250DecodeTest, WmmaScale16F8f6f4ConsumesVop3px2Pair) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_wmma_scale16_f32_16x16x128_f8f6f4"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -524,7 +525,7 @@ TEST(Gfx1250DecodeTest, WmmaScaleF4_32x16x128ConsumesVop3px2Pair) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_wmma_scale_f32_32x16x128_f4"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -542,7 +543,7 @@ TEST(Gfx1250DecodeTest, WmmaScalePrefixRejectsNonWmmaSuffix) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(static_cast(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250ExecutionTest, WmmaRegularScaleInlineZeroMatchesNeutralScalarSources) { @@ -577,8 +578,8 @@ TEST(Gfx1250ExecutionTest, WmmaRegularScaleInlineZeroMatchesNeutralScalarSources auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr scalar_inst(decoder->decode(scalar_words.data())); - std::unique_ptr inline_inst(decoder->decode(inline_words.data())); + std::unique_ptr scalar_inst(decode_valid(*decoder, scalar_words.data())); + std::unique_ptr inline_inst(decode_valid(*decoder, inline_words.data())); ASSERT_NE(scalar_inst, nullptr); ASSERT_NE(inline_inst, nullptr); cu->execute_instruction(scalar_inst.get(), *wf); @@ -602,7 +603,7 @@ TEST(Gfx1250DecodeTest, SwmmacPrintsIndexKeyAndReuseModifiers) { 0xCC65081Au, 0x1C8E0112u, }; - std::unique_ptr index_key_inst(decoder->decode(index_key_words)); + std::unique_ptr index_key_inst(decode_valid(*decoder, index_key_words)); ASSERT_NE(index_key_inst, nullptr); EXPECT_EQ(index_key_inst->disassemble(), "v_swmmac_f32_16x16x64_f16 v[26:33], v[18:25], v[0:15], v35 index_key:1"); @@ -611,7 +612,7 @@ TEST(Gfx1250DecodeTest, SwmmacPrintsIndexKeyAndReuseModifiers) { 0xCC65201Au, 0x1C8E0112u, }; - std::unique_ptr matrix_a_reuse_inst(decoder->decode(matrix_a_reuse_words)); + std::unique_ptr matrix_a_reuse_inst(decode_valid(*decoder, matrix_a_reuse_words)); ASSERT_NE(matrix_a_reuse_inst, nullptr); EXPECT_EQ(matrix_a_reuse_inst->disassemble(), "v_swmmac_f32_16x16x64_f16 v[26:33], v[18:25], v[0:15], v35 matrix_a_reuse"); @@ -620,7 +621,7 @@ TEST(Gfx1250DecodeTest, SwmmacPrintsIndexKeyAndReuseModifiers) { 0xCC65401Au, 0x1C8E0112u, }; - std::unique_ptr matrix_b_reuse_inst(decoder->decode(matrix_b_reuse_words)); + std::unique_ptr matrix_b_reuse_inst(decode_valid(*decoder, matrix_b_reuse_words)); ASSERT_NE(matrix_b_reuse_inst, nullptr); EXPECT_EQ(matrix_b_reuse_inst->disassemble(), "v_swmmac_f32_16x16x64_f16 v[26:33], v[18:25], v[0:15], v35 matrix_b_reuse"); @@ -634,7 +635,7 @@ TEST(Gfx1250DecodeTest, VopdXyConsumesTwoDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_dual_cndmask_b32 :: v_dual_mov_b32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -651,7 +652,7 @@ TEST(Gfx1250DecodeTest, Vopd3ConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_dual_lshlrev_b32 :: v_dual_lshrrev_b32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -668,7 +669,7 @@ TEST(Gfx1250DecodeTest, Vopd3RejectsSrcX0Literal32Selector) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, Vopd3RejectsSrcY0Literal32Selector) { @@ -680,7 +681,7 @@ TEST(Gfx1250DecodeTest, Vopd3RejectsSrcY0Literal32Selector) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - EXPECT_THROW(std::unique_ptr(decoder->decode(words)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words)); } TEST(Gfx1250DecodeTest, VopdLiteralConsumesThreeDwords) { @@ -692,7 +693,7 @@ TEST(Gfx1250DecodeTest, VopdLiteralConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_dual_mul_f32 :: v_dual_mov_b32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -708,7 +709,7 @@ TEST(Gfx1250DecodeTest, VopdSourceOperandsFollowPrintedSlots) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_dual_lshlrev_b32 :: v_dual_mov_b32"); EXPECT_EQ(inst->num_src_operands(), 3); @@ -729,7 +730,7 @@ TEST(Gfx1250DecodeTest, VopdRejectsInvalidOpcodes) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); for (const auto &encoding : words) - EXPECT_THROW(static_cast(decoder->decode(encoding.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, encoding.data())); } TEST(Gfx1250DecodeTest, PublicDecoderReportsInvalidVopdEncoding) { @@ -759,7 +760,7 @@ TEST(Gfx1250DecodeTest, Vopd3RejectsOverlappingDestinations) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); for (const auto &encoding : words) - EXPECT_THROW(static_cast(decoder->decode(encoding.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, encoding.data())); } } // namespace diff --git a/emulation/rocjitsu/tests/cdna5_execution_test.cpp b/emulation/rocjitsu/tests/cdna5_execution_test.cpp index d53db192eac7..bf163213a2ec 100644 --- a/emulation/rocjitsu/tests/cdna5_execution_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_execution_test.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: MIT #include "cdna5_sim_test_common.h" +#include "decode_test_util.h" namespace { @@ -46,7 +47,7 @@ TEST(Gfx1250ExecutionTest, ScalarMovesTreatS102AndS103AsOrdinarySgprs) { 0, 0, }; - std::unique_ptr move64(decoder->decode(kMove64.data())); + std::unique_ptr move64(decode_valid(*decoder, kMove64.data())); ASSERT_NE(move64, nullptr); EXPECT_EQ(move64->mnemonic(), "s_mov_b64"); EXPECT_EQ(move64->size(), 4); @@ -66,7 +67,7 @@ TEST(Gfx1250ExecutionTest, ScalarMovesTreatS102AndS103AsOrdinarySgprs) { 0, }; for (const auto *words : {kWriteS102.data(), kWriteS103.data()}) { - std::unique_ptr move32(decoder->decode(words)); + std::unique_ptr move32(decode_valid(*decoder, words)); ASSERT_NE(move32, nullptr); EXPECT_EQ(move32->mnemonic(), "s_mov_b32"); EXPECT_EQ(move32->size(), 4); @@ -86,7 +87,7 @@ TEST(Gfx1250ExecutionTest, ScalarMovesTreatS102AndS103AsOrdinarySgprs) { 0, }; for (const auto *words : {kReadS102.data(), kReadS103.data()}) { - std::unique_ptr move32(decoder->decode(words)); + std::unique_ptr move32(decode_valid(*decoder, words)); ASSERT_NE(move32, nullptr); EXPECT_EQ(move32->mnemonic(), "s_mov_b32"); EXPECT_EQ(move32->size(), 4); @@ -100,7 +101,7 @@ TEST(Gfx1250ExecutionTest, ScalarMovesTreatS102AndS103AsOrdinarySgprs) { 0, 0, }; - std::unique_ptr read64(decoder->decode(kReadS102S103.data())); + std::unique_ptr read64(decode_valid(*decoder, kReadS102S103.data())); ASSERT_NE(read64, nullptr); EXPECT_EQ(read64->mnemonic(), "s_mov_b64"); EXPECT_EQ(read64->size(), 4); @@ -130,7 +131,7 @@ TEST(Gfx1250ExecutionTest, Wave32VectorComparePreservesVccHiScratch) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); constexpr auto kCompare = cdna5::build_vopc(cdna5::kVCmpGtI32Vopc, {.src0 = 28, .vsrc1 = 18}); - std::unique_ptr decoded(decoder->decode(kCompare.data())); + std::unique_ptr decoded(decode_valid(*decoder, kCompare.data())); ASSERT_NE(decoded, nullptr); EXPECT_EQ(decoded->mnemonic(), "v_cmp_gt_i32_e32"); decoded->execute(*decoded, wf); @@ -312,7 +313,7 @@ TEST(Gfx1250ExecutionTest, IreeF16ReductionTailKeepsLane31Sum) { }}; for (const auto &inst_words : words) { - std::unique_ptr inst(decoder->decode(inst_words.data())); + std::unique_ptr inst(decode_valid(*decoder, inst_words.data())); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst.get(), *wf); } @@ -416,7 +417,8 @@ TEST(Gfx1250LiteralOperandTest, SplitBackendPreservesSignedAndEncodingSemantics) const auto signed_mad_base = cdna5::build_vop3( cdna5::kVMadNcI64I32Vop3, {.vdst = 4, .src0 = 129, .src1 = 129, .src2 = 255}); const std::array signed_mad_words{signed_mad_base[0], signed_mad_base[1], literal}; - std::unique_ptr signed_mad_decoded(decoder->decode(signed_mad_words.data())); + std::unique_ptr signed_mad_decoded( + decode_valid(*decoder, signed_mad_words.data())); ASSERT_NE(signed_mad_decoded, nullptr); EXPECT_EQ(signed_mad_decoded->mnemonic(), "v_mad_nc_i64_i32"); EXPECT_EQ(signed_mad_decoded->size(), 12); @@ -435,7 +437,8 @@ TEST(Gfx1250LiteralOperandTest, SplitBackendPreservesSignedAndEncodingSemantics) const auto unsigned_mad_base = cdna5::build_vop3( cdna5::kVMadNcU64U32Vop3, {.vdst = 6, .src0 = 129, .src1 = 129, .src2 = 255}); const std::array unsigned_mad_words{unsigned_mad_base[0], unsigned_mad_base[1], literal}; - std::unique_ptr unsigned_mad_decoded(decoder->decode(unsigned_mad_words.data())); + std::unique_ptr unsigned_mad_decoded( + decode_valid(*decoder, unsigned_mad_words.data())); ASSERT_NE(unsigned_mad_decoded, nullptr); auto *unsigned_mad = dynamic_cast(unsigned_mad_decoded.get()); ASSERT_NE(unsigned_mad, nullptr); @@ -451,7 +454,7 @@ TEST(Gfx1250LiteralOperandTest, SplitBackendPreservesSignedAndEncodingSemantics) const auto scalar_base = cdna5::build_sop2(cdna5::kSAshrI64Sop2, {.ssrc0 = 255, .ssrc1 = 128, .sdst = 0}); const std::array scalar_words{scalar_base[0], literal}; - std::unique_ptr scalar_decoded(decoder->decode(scalar_words.data())); + std::unique_ptr scalar_decoded(decode_valid(*decoder, scalar_words.data())); ASSERT_NE(scalar_decoded, nullptr); EXPECT_EQ(scalar_decoded->mnemonic(), "s_ashr_i64"); EXPECT_EQ(scalar_decoded->size(), 8); @@ -468,7 +471,7 @@ TEST(Gfx1250LiteralOperandTest, SplitBackendPreservesSignedAndEncodingSemantics) const auto b64_base = cdna5::build_sop2(cdna5::kSAndB64Sop2, {.ssrc0 = 255, .ssrc1 = 193, .sdst = 2}); const std::array b64_words{b64_base[0], literal}; - std::unique_ptr b64_decoded(decoder->decode(b64_words.data())); + std::unique_ptr b64_decoded(decode_valid(*decoder, b64_words.data())); ASSERT_NE(b64_decoded, nullptr); auto *b64 = dynamic_cast(b64_decoded.get()); ASSERT_NE(b64, nullptr); @@ -505,7 +508,7 @@ TEST(Gfx1250LiteralOperandTest, NegativeI64CompareCoversScalarAndAvailableSimdPa const auto compare_base = cdna5::build_vop3(cdna5::kVCmpLtI64Vop3, {.vdst = 0, .src0 = 255, .src1 = 256}); const std::array compare_words{compare_base[0], compare_base[1], 0xffffffffu}; - std::unique_ptr compare(decoder->decode(compare_words.data())); + std::unique_ptr compare(decode_valid(*decoder, compare_words.data())); ASSERT_NE(compare, nullptr); EXPECT_EQ(compare->mnemonic(), "v_cmp_lt_i64"); EXPECT_EQ(compare->size(), 12); @@ -556,7 +559,7 @@ TEST(Gfx1250LiteralOperandTest, ScalarMaskOperandsRejectLiteralMarkers) { SCOPED_TRACE(test_case.name); SCOPED_TRACE(marker); const std::array words{test_case.encoding[0], test_case.encoding[1], 0xffffffffu, 0u}; - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } } } @@ -576,7 +579,7 @@ TEST(Gfx1250LiteralOperandTest, PkF32LiteralReplicatesAndUsesAvailableSimdPath) auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr add(decoder->decode(add_words.data())); + std::unique_ptr add(decode_valid(*decoder, add_words.data())); ASSERT_NE(add, nullptr); auto *typed_add = dynamic_cast(add.get()); ASSERT_NE(typed_add, nullptr); @@ -665,7 +668,7 @@ TEST(Gfx1250LiteralOperandTest, PkF32MixedLiteralVgprSourcesUseAvailableSimdPath const std::array words{base[0], base[1], kLiteral}; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); const Operand *literal_operand = instruction->src_operand(test_case.literal_source); @@ -723,7 +726,7 @@ TEST(Gfx1250LiteralOperandTest, PkF32MixedLiteralSourceSpecificSelectorFallsBack const std::array words{base[0], base[1], kLiteral}; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); auto *typed = dynamic_cast(instruction.get()); ASSERT_NE(typed, nullptr); @@ -771,7 +774,7 @@ TEST(Gfx1250ExecutionTest, PkF32AddMulSimdMatchesScalarWithPartialExec) { {.vdst = 4, .neg_hi = 2, .src0 = 256, .src1 = 258, .opsel_hi = 3, .neg = 1}); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); Gfx1250Sim sim; @@ -880,7 +883,7 @@ TEST(Gfx1250ExecutionTest, PkF32EveryNondefaultSelectorGateFallsBackToScalar) { words[0] |= uint32_t{1} << 14; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); Gfx1250Sim sim; @@ -951,7 +954,7 @@ TEST(Gfx1250ExecutionTest, PkFmaF32SimdMatchesScalarWithPartialExec) { words[0] |= uint32_t{1} << 14; // pad_14 is the src2 high-half selector. auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); auto *typed = dynamic_cast(instruction.get()); ASSERT_NE(typed, nullptr); @@ -1018,7 +1021,7 @@ TEST(Gfx1250DecodeTest, Vop3pRejectsLiteral64SelectorInEverySourcePosition) { cdna5::Vop3pBuilderFields{.src2 = 254}, }) { const auto words = cdna5::build_vop3p(cdna5::kVPkFmaF32Vop3p, fields); - EXPECT_THROW(static_cast(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } } @@ -1028,7 +1031,7 @@ TEST(Gfx1250DecodeTest, BinaryVop3pIgnoresLiteral64SelectorInUnusedSrc2) { for (const uint32_t opcode : {cdna5::kVPkAddF32Vop3p, cdna5::kVPkMulF32Vop3p}) { const auto words = cdna5::build_vop3p(opcode, {.src0 = 128, .src1 = 129, .src2 = 254}); - std::unique_ptr instruction(decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); EXPECT_EQ(instruction->size(), 8); EXPECT_EQ(instruction->num_src_operands(), 2); @@ -1074,7 +1077,7 @@ TEST(Gfx1250ExecutionTest, Wave32ScalarVccHiWritePreservesUpperHalf) { ASSERT_NE(decoder, nullptr); const uint32_t words[] = {0x8c6b7e6bu, 0}; // s_or_b32 vcc_hi, vcc_hi, exec_lo - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "s_or_b32"); cu->execute_instruction(inst.get(), *wf); diff --git a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp index fd4d1e6c6388..fa435d7aeea3 100644 --- a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: MIT #include "cdna5_sim_test_common.h" +#include "decode_test_util.h" namespace { @@ -83,8 +84,8 @@ TEST(Gfx1250SimulationTest, SAddPcI64WrapsAtUnsignedBoundaries) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr increment(decoder->decode(add_one.data())); - std::unique_ptr decrement(decoder->decode(add_minus_one.data())); + std::unique_ptr increment(decode_valid(*decoder, add_one.data())); + std::unique_ptr decrement(decode_valid(*decoder, add_minus_one.data())); ASSERT_NE(increment, nullptr); ASSERT_NE(decrement, nullptr); @@ -285,7 +286,7 @@ TEST(Gfx1250SimulationTest, NamedBarrierSignalIsfirstPreservesSccWithoutAllocati auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); const std::array signal_words = {0xBE804F7Du}; - std::unique_ptr signal(decoder->decode(signal_words.data())); + std::unique_ptr signal(decode_valid(*decoder, signal_words.data())); ASSERT_NE(signal, nullptr); wf->set_m0((2u << 16) | 1u); @@ -309,10 +310,10 @@ void expect_barrier_init_reads_implicit_m0(uint32_t init_encoding, uint32_t init const std::array join_words = {0xBE805281u}; // s_barrier_join 1 const std::array signal_words = {0xBE804F81u}; // s_barrier_signal_isfirst 1 const std::array state_words = {0xBE845081u}; // s_get_barrier_state s4, 1 - std::unique_ptr init(decoder->decode(init_words.data())); - std::unique_ptr join(decoder->decode(join_words.data())); - std::unique_ptr signal(decoder->decode(signal_words.data())); - std::unique_ptr state(decoder->decode(state_words.data())); + std::unique_ptr init(decode_valid(*decoder, init_words.data())); + std::unique_ptr join(decode_valid(*decoder, join_words.data())); + std::unique_ptr signal(decode_valid(*decoder, signal_words.data())); + std::unique_ptr state(decode_valid(*decoder, state_words.data())); ASSERT_NE(init, nullptr); ASSERT_NE(join, nullptr); ASSERT_NE(signal, nullptr); @@ -360,10 +361,10 @@ TEST(Gfx1250SimulationTest, NamedBarrierSynchronizesJoinedWavesAcrossPhases) { const std::array signal_words = {0xBE804F7Du}; const std::array wait_words = {0xBF940001u}; const std::array state_words = {0xBE84507Du}; - std::unique_ptr join(decoder->decode(join_words.data())); - std::unique_ptr signal(decoder->decode(signal_words.data())); - std::unique_ptr wait(decoder->decode(wait_words.data())); - std::unique_ptr state(decoder->decode(state_words.data())); + std::unique_ptr join(decode_valid(*decoder, join_words.data())); + std::unique_ptr signal(decode_valid(*decoder, signal_words.data())); + std::unique_ptr wait(decode_valid(*decoder, wait_words.data())); + std::unique_ptr state(decode_valid(*decoder, state_words.data())); ASSERT_NE(join, nullptr); ASSERT_NE(signal, nullptr); ASSERT_NE(wait, nullptr); @@ -496,7 +497,7 @@ TEST(Gfx1250SimulationTest, WorkgroupSignalIsfirstAcceptsNegativeInlineBarrierId auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); const std::array signal_words = {0xBE804FC1u}; // s_barrier_signal_isfirst -1 - std::unique_ptr signal(decoder->decode(signal_words.data())); + std::unique_ptr signal(decode_valid(*decoder, signal_words.data())); ASSERT_NE(signal, nullptr); cu->execute_instruction(signal.get(), *wf0); @@ -1429,7 +1430,7 @@ TEST(Gfx1250SimulationTest, VopdFmamkUsesSrc2HighBank) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dual_fmamk_f32 :: v_dual_mov_b32"); cu->execute_instruction(inst.get(), *wf); @@ -1574,7 +1575,7 @@ TEST(Gfx1250SimulationTest, DsAddtidLoadAndStoreUseM0ByteBaseAddresses) { const uint32_t expected1 = expected0 + sizeof(uint32_t); const uint32_t store_words[] = {0xDAC01234u, 0x00000500u}; - std::unique_ptr store(decoder->decode(store_words)); + std::unique_ptr store(decode_valid(*decoder, store_words)); ASSERT_NE(store, nullptr); ASSERT_EQ(std::string_view(store->mnemonic()), "ds_store_addtid_b32"); cu.execute_instruction(store.get(), *wf); @@ -1594,7 +1595,7 @@ TEST(Gfx1250SimulationTest, DsAddtidLoadAndStoreUseM0ByteBaseAddresses) { EXPECT_EQ(cu.lds().read32(expected1), kLane1Data); const uint32_t load_words[] = {0xDAC41234u, 0x08000000u}; - std::unique_ptr load(decoder->decode(load_words)); + std::unique_ptr load(decode_valid(*decoder, load_words)); ASSERT_NE(load, nullptr); ASSERT_EQ(std::string_view(load->mnemonic()), "ds_load_addtid_b32"); cu.execute_instruction(load.get(), *wf); @@ -1608,7 +1609,7 @@ TEST(Gfx1250SimulationTest, DsAddtidLoadAndStoreUseM0ByteBaseAddresses) { EXPECT_EQ(cu.read_vgpr(load_dst_base, 1), kLane1Data); wf->set_m0(0); - std::unique_ptr default_m0_store(decoder->decode(store_words)); + std::unique_ptr default_m0_store(decode_valid(*decoder, store_words)); ASSERT_NE(default_m0_store, nullptr); cu.execute_instruction(default_m0_store.get(), *wf); auto *default_m0_state = default_m0_store->data_as(); @@ -1731,7 +1732,7 @@ TEST(Gfx1250ExecutionTest, Vopd3CndmaskAppliesB32NegModifiers) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(cndmask.data())); + std::unique_ptr inst(decode_valid(*decoder, cndmask.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dual_cndmask_b32 :: v_dual_cndmask_b32"); diff --git a/emulation/rocjitsu/tests/cdna5_sim_test_common.h b/emulation/rocjitsu/tests/cdna5_sim_test_common.h index 5277fe3f3b07..47e5ae4506f0 100644 --- a/emulation/rocjitsu/tests/cdna5_sim_test_common.h +++ b/emulation/rocjitsu/tests/cdna5_sim_test_common.h @@ -4,6 +4,7 @@ #pragma once #include "aql_queue.h" +#include "decode_test_util.h" #include "halt_snapshot_plugin.h" #include "embedded_schema.h" @@ -328,7 +329,7 @@ inline std::unique_ptr decode_gfx1250(const std::array return nullptr; } - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); if (!inst) { ADD_FAILURE() << "decode() returned nullptr for gfx1250 instruction"; return nullptr; diff --git a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp index 02e860ab7691..69d370ac4b9e 100644 --- a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: MIT #include "cdna5_sim_test_common.h" +#include "decode_test_util.h" namespace { @@ -1125,7 +1126,7 @@ TEST(Gfx1250ExecutionTest, SBarrierWaitIsNoOpForSingleWaveWorkgroup) { ASSERT_NE(decoder, nullptr); const std::array wait_words = {0xBF94FFFFu, 0u}; - std::unique_ptr wait_inst(decoder->decode(wait_words.data())); + std::unique_ptr wait_inst(decode_valid(*decoder, wait_words.data())); ASSERT_NE(wait_inst, nullptr); ASSERT_EQ(std::string_view(wait_inst->mnemonic()), "s_barrier_wait"); @@ -1152,7 +1153,7 @@ TEST(Gfx1250ExecutionTest, SBarrierWaitReleasesOnlyAfterSignalQuorum) { ASSERT_NE(decoder, nullptr); const std::array wait_words = {0xBF94FFFFu, 0u}; - std::unique_ptr wait_inst(decoder->decode(wait_words.data())); + std::unique_ptr wait_inst(decode_valid(*decoder, wait_words.data())); ASSERT_NE(wait_inst, nullptr); ASSERT_EQ(std::string_view(wait_inst->mnemonic()), "s_barrier_wait"); diff --git a/emulation/rocjitsu/tests/check_model_only_symbols.cmake b/emulation/rocjitsu/tests/check_model_only_symbols.cmake index 70409801e8ff..829619fdd25b 100644 --- a/emulation/rocjitsu/tests/check_model_only_symbols.cmake +++ b/emulation/rocjitsu/tests/check_model_only_symbols.cmake @@ -53,7 +53,7 @@ if(REQUIRED_MODEL_ARCHES) endforeach() else() set(_required_symbol - "rocjitsu::cdna5::Decoder::decode(unsigned int const*)" + "rocjitsu::cdna5::Decoder::decode(unsigned int const*, util::DiagnosticEmitter const&)" ) string(FIND "${_symbols}" "${_required_symbol}" _match) if(_match EQUAL -1) diff --git a/emulation/rocjitsu/tests/check_narrow_registry_symbols.cmake b/emulation/rocjitsu/tests/check_narrow_registry_symbols.cmake index d4c57a8d382d..b1e28f8a7a90 100644 --- a/emulation/rocjitsu/tests/check_narrow_registry_symbols.cmake +++ b/emulation/rocjitsu/tests/check_narrow_registry_symbols.cmake @@ -17,7 +17,7 @@ endif() set(_required_symbols "rj_test_narrow_target_count" - "rocjitsu::cdna5::Decoder::decode(unsigned int const*)" + "rocjitsu::cdna5::Decoder::decode(unsigned int const*, util::DiagnosticEmitter const&)" ) foreach(_required IN LISTS _required_symbols) string(FIND "${_symbols}" "${_required}" _match) diff --git a/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp b/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp index c34ea1d5ff7d..8e711567c128 100644 --- a/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp +++ b/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp @@ -1,6 +1,7 @@ // Copyright (c) 2026 Advanced Micro Devices, Inc. // SPDX-License-Identifier: MIT +#include "decode_test_util.h" #include "rocjitsu/code/amdgpu_code_object.h" #include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/basic_block.h" @@ -538,7 +539,7 @@ TEST(RelocationFunctionTable, ResolvesDynamicDispatchThroughGotAndTableLoads) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); std::array leaders{40}; - const auto blocks = BasicBlock::build(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); const auto dispatches = analyze_relocation_pairs(blocks, tables, 0x1000).dispatches; ASSERT_EQ(dispatches.size(), 1u); EXPECT_EQ(dispatches[0].table_index, 0u); @@ -563,7 +564,7 @@ TEST(RelocationFunctionTable, ResolvesRcclDirectIndexedTableDispatch) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); std::array leaders{32}; - const auto blocks = BasicBlock::build(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); const auto analysis = analyze_relocation_pairs(blocks, tables, 0x1000); const auto &dispatches = analysis.dispatches; ASSERT_EQ(dispatches.size(), 1u); @@ -602,7 +603,7 @@ TEST(RelocationFunctionTable, RejectsChainedAddressAddDispatch) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); std::array leaders{44}; - const auto blocks = BasicBlock::build(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); const auto dispatches = analyze_relocation_pairs(blocks, tables, 0x1000).dispatches; // The base is built with two literal adds; only one add offset can be relocated, // so the dispatch must fail closed rather than resolve to a value whose first @@ -631,7 +632,7 @@ TEST(RelocationFunctionTable, ResolvesBackwardTableAddress) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); std::array leaders{32}; - const auto blocks = BasicBlock::build(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); const auto dispatches = analyze_relocation_pairs(blocks, tables, kAssumedTextVaddr).dispatches; ASSERT_EQ(dispatches.size(), 1u); EXPECT_EQ(dispatches[0].table_index, 0u); diff --git a/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_asm_test.cpp b/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_asm_test.cpp index c321fbbee1fc..f0def81e117a 100644 --- a/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_asm_test.cpp +++ b/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_asm_test.cpp @@ -75,7 +75,9 @@ class HsaDbiNopAsmFixture : public ::testing::Test { // TODO: instrument multiple instructions auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA2); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA2); + auto block_result = BasicBlock::build(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA2); + ASSERT_TRUE(block_result.succeeded()); + auto blocks = std::move(block_result).value(); ASSERT_FALSE(co->text_sections().empty()); const auto *text = co->text_sections().front(); @@ -178,7 +180,9 @@ TEST_F(HsaDbiNopAsmStatic, PatchedElfActuallyContainsInstrumentation) { for (uint64_t anchor_idx = 0; anchor_idx < anchor_count_; ++anchor_idx) { rj_code_binary_inst_t anchor_word = 0; std::memcpy(&anchor_word, text->data() + anchor_offsets_[anchor_idx], sizeof(anchor_word)); - std::unique_ptr decoded(decoder->decode(&anchor_word)); + auto decode_result = decoder->decode(&anchor_word); + ASSERT_TRUE(decode_result.succeeded()); + std::unique_ptr decoded = std::move(decode_result).value(); ASSERT_NE(decoded, nullptr); EXPECT_NE(decoded->mnemonic().find("s_branch"), std::string_view::npos) << "Anchor at offset " << anchor_offsets_[anchor_idx] diff --git a/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_probe_test.cpp b/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_probe_test.cpp index 656e5cb4104b..75add6821ec9 100644 --- a/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_probe_test.cpp +++ b/emulation/rocjitsu/tests/dbi/hsa_dbi_nop_probe_test.cpp @@ -70,9 +70,10 @@ bool decodes_mnemonic_within(Decoder &decoder, std::span text, ui rj_code_binary_inst_t word_buf[2] = {0, 0}; const size_t avail = std::min(sizeof(word_buf), text.size() - cur); std::memcpy(word_buf, text.data() + cur, avail); - std::unique_ptr inst(decoder.decode(word_buf)); - if (!inst) + auto decoded = decoder.decode(word_buf); + if (decoded.failed()) return false; + std::unique_ptr inst = std::move(decoded).value(); if (inst->mnemonic() == mnemonic) return true; cur += static_cast(inst->size()); @@ -127,7 +128,9 @@ class HsaDbiNopProbeFixture : public ::testing::Test { // test stays stable across compiler revisions. auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA2); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA2); + auto block_result = BasicBlock::build(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA2); + ASSERT_TRUE(block_result.succeeded()); + auto blocks = std::move(block_result).value(); ASSERT_FALSE(co->text_sections().empty()); const auto *text = co->text_sections().front(); const std::span text_bytes(reinterpret_cast(text->data()), @@ -236,7 +239,9 @@ TEST_F(HsaDbiNopProbeStatic, PatchedElfContainsProbeCallInstrumentation) { ASSERT_GT(text->size(), anchor_offset_ + sizeof(uint32_t)); rj_code_binary_inst_t anchor_word = 0; std::memcpy(&anchor_word, text->data() + anchor_offset_, sizeof(anchor_word)); - std::unique_ptr anchor_inst(decoder->decode(&anchor_word)); + auto decoded = decoder->decode(&anchor_word); + ASSERT_TRUE(decoded.succeeded()); + std::unique_ptr anchor_inst = std::move(decoded).value(); ASSERT_NE(anchor_inst, nullptr); EXPECT_NE(anchor_inst->mnemonic().find("s_branch"), std::string_view::npos) << "Anchor at offset " << anchor_offset_ << " should decode as s_branch; got " diff --git a/emulation/rocjitsu/tests/dbi/probe_fixture_test.cpp b/emulation/rocjitsu/tests/dbi/probe_fixture_test.cpp index bc566663dbf6..1604243771d6 100644 --- a/emulation/rocjitsu/tests/dbi/probe_fixture_test.cpp +++ b/emulation/rocjitsu/tests/dbi/probe_fixture_test.cpp @@ -63,7 +63,9 @@ TEST(ProbeFixture, NopProbeResolvesAndReturns) { std::string last_mnemonic; size_t w = 0; while (w < num_words) { - std::unique_ptr inst(decoder->decode(&body[w])); + auto decoded = decoder->decode(&body[w]); + ASSERT_TRUE(decoded.succeeded()); + std::unique_ptr inst = std::move(decoded).value(); ASSERT_NE(inst, nullptr); const int size = inst->size(); ASSERT_TRUE(size == 4 || size == 8) << "unexpected instruction size in probe body"; diff --git a/emulation/rocjitsu/tests/dbt/device_kernels_translate_tests.cpp b/emulation/rocjitsu/tests/dbt/device_kernels_translate_tests.cpp index 297c5ab435e7..d9cca37b70a1 100644 --- a/emulation/rocjitsu/tests/dbt/device_kernels_translate_tests.cpp +++ b/emulation/rocjitsu/tests/dbt/device_kernels_translate_tests.cpp @@ -9,6 +9,7 @@ #endif #include "../test_paths.h" +#include "decode_test_util.h" #include "rocjitsu/code/amdgpu_code_object.h" #include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/builders/instruction_builder.h" @@ -188,24 +189,17 @@ TEST(BinaryTranslatorE2E, TranslateVectorAddCdna4ToCdna3) { const size_t words = sec->size() / sizeof(uint32_t); size_t pc = 0; while (pc < words) { - try { - std::unique_ptr inst(decoder->decode(&data[pc])); - if (!inst) { - ++decode_failures; - ++pc; - continue; - } - const std::string_view mnemonic(inst->mnemonic()); - if (mnemonic.starts_with("v_add_")) - has_vector_add = true; - pc += inst->size() / 4; - ++inst_count; - } catch (const std::exception &e) { - std::cerr << " decode fail at 0x" << std::hex << pc * 4 << " word=0x" << data[pc] << ": " - << e.what() << "\n"; + std::unique_ptr inst(decode_valid(*decoder, &data[pc])); + if (!inst) { ++decode_failures; ++pc; + continue; } + const std::string_view mnemonic(inst->mnemonic()); + if (mnemonic.starts_with("v_add_")) + has_vector_add = true; + pc += inst->size() / 4; + ++inst_count; } } EXPECT_GT(inst_count, 0) << "Translated text section should contain instructions"; @@ -614,7 +608,7 @@ TEST(BinaryTranslatorE2E, ASSERT_LT(original_info->entry_text_offset, text->size()); std::unique_ptr original_entry( - decoder->decode(&words[original_info->entry_text_offset / sizeof(uint32_t)])); + decode_valid(*decoder, &words[original_info->entry_text_offset / sizeof(uint32_t)])); ASSERT_NE(original_entry, nullptr); EXPECT_NE(std::string_view(original_entry->mnemonic()), "s_branch") << "Original kernel entry should not be replaced by a prologue branch stub"; @@ -626,7 +620,7 @@ TEST(BinaryTranslatorE2E, const auto *redirected_words = reinterpret_cast(text->data()); std::unique_ptr redirected_entry( - decoder->decode(&redirected_words[redirected_section_offset / sizeof(uint32_t)])); + decode_valid(*decoder, &redirected_words[redirected_section_offset / sizeof(uint32_t)])); ASSERT_NE(redirected_entry, nullptr); EXPECT_EQ(std::string_view(redirected_entry->mnemonic()), "s_mov_b32") << "Redirected kernel entry should begin with the descriptor ABI prologue"; @@ -726,7 +720,7 @@ TEST(BinaryTranslatorE2E, OutputDecodesAsValidRdna4) { size_t pc = 0; while (pc < words) { try { - std::unique_ptr inst(decoder->decode(&data[pc])); + std::unique_ptr inst(decode_valid(*decoder, &data[pc])); if (!inst) { ++decode_failures; ++pc; @@ -768,7 +762,7 @@ TEST(BinaryTranslatorE2E, NoGfx9WaitcntInOutput) { size_t pc = 0; while (pc < words) { try { - std::unique_ptr inst(decoder->decode(&data[pc])); + std::unique_ptr inst(decode_valid(*decoder, &data[pc])); if (!inst) { ++pc; continue; @@ -852,7 +846,7 @@ TEST(BinaryTranslatorE2E, DumpTranslation) { printf("\n--- %s (%zu bytes, %zu words) ---\n", label, size, words); while (pc < words) { try { - std::unique_ptr inst(dec->decode(&data[pc])); + std::unique_ptr inst(decode_valid(*dec, &data[pc])); if (!inst) { printf(" 0x%04zx: ???\n", pc * 4); ++pc; diff --git a/emulation/rocjitsu/tests/dbt/multikernel_indirect_branch_test.cpp b/emulation/rocjitsu/tests/dbt/multikernel_indirect_branch_test.cpp index dc5c4edbaa90..6f6c4ae2b79a 100644 --- a/emulation/rocjitsu/tests/dbt/multikernel_indirect_branch_test.cpp +++ b/emulation/rocjitsu/tests/dbt/multikernel_indirect_branch_test.cpp @@ -8,6 +8,7 @@ #error "multikernel_indirect_branch_test.cpp requires HAS_DEVICE_KERNELS" #endif +#include "decode_test_util.h" #include "rocjitsu/code/amdgpu_code_object.h" #include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/basic_block.h" @@ -47,7 +48,7 @@ size_t count_text_mnemonic(const rocjitsu::AmdGpuCodeObject &co, rj_code_arch_t size_t word_offset = 0; while (word_offset < word_count) { std::unique_ptr inst( - decoder->decode(words + word_offset, word_offset * sizeof(rj_code_binary_inst_t))); + decode_valid(*decoder, words + word_offset, word_offset * sizeof(rj_code_binary_inst_t))); if (!inst) { ++word_offset; continue; @@ -177,7 +178,7 @@ cfg_block_counts_by_kernel(const rocjitsu::AmdGpuCodeObject &co, return counts; auto blocks = - rocjitsu::BasicBlock::build(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, kernel_entry_leaders); + rocjitsu::build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, kernel_entry_leaders); for (const char *name : kernel_names) { const auto *kernel = kernel_translation_by_name(source_kernels, co, name); @@ -283,7 +284,7 @@ TEST(BinaryTranslatorE2E, BuildsCfgForRealMultiKernelIndirectBranches) { auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); auto blocks = - rocjitsu::BasicBlock::build(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, kernel_entries); + rocjitsu::build_valid_blocks(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, kernel_entries); ASSERT_FALSE(blocks.empty()); size_t recovered_swappc_blocks = 0; @@ -367,7 +368,7 @@ TEST(BinaryTranslatorE2E, CountsRealMultiKernelIndirectBranchCfgBlocksPerKernel) auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); auto blocks = - rocjitsu::BasicBlock::build(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, kernel_entry_leaders); + rocjitsu::build_valid_blocks(*co, *decoder, ROCJITSU_CODE_ARCH_CDNA4, kernel_entry_leaders); ASSERT_FALSE(blocks.empty()); struct ExpectedKernelCfg { diff --git a/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp b/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp index be2407072ba4..df2e44dbfe96 100644 --- a/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp +++ b/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp @@ -8,6 +8,7 @@ #error "relocation_function_table_hip_test.cpp requires a gfx1250-capable device compiler" #endif +#include "decode_test_util.h" #include "rocjitsu/code/amdgpu_code_object.h" #include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/basic_block.h" @@ -98,7 +99,7 @@ TEST(RelocationFunctionTableHip, TranslatesEightWayDeviceDispatch) { auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); const auto blocks = - rocjitsu::BasicBlock::build(*source, *decoder, ROCJITSU_CODE_ARCH_GFX1250, source_targets); + rocjitsu::build_valid_blocks(*source, *decoder, ROCJITSU_CODE_ARCH_GFX1250, source_targets); const auto dispatches = rocjitsu::analyze_relocation_pairs(blocks, source_tables, source->text_sections()[0]->vaddr()) .dispatches; diff --git a/emulation/rocjitsu/tests/dbt/semantic_scratch_test.cpp b/emulation/rocjitsu/tests/dbt/semantic_scratch_test.cpp index 501854b8dc5d..24adabbafdb5 100644 --- a/emulation/rocjitsu/tests/dbt/semantic_scratch_test.cpp +++ b/emulation/rocjitsu/tests/dbt/semantic_scratch_test.cpp @@ -1,6 +1,7 @@ // Copyright (c) 2026 Advanced Micro Devices, Inc. // SPDX-License-Identifier: MIT +#include "decode_test_util.h" #include "rocjitsu/analysis/exec_state.h" #include "rocjitsu/analysis/liveness.h" #include "rocjitsu/code/basic_block.h" @@ -65,7 +66,7 @@ std::vector> build_scratch_test_blocks() { constexpr std::array words = {move[0], end[0]}; ScratchTestCodeObject code(words); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); - return BasicBlock::build(code, *decoder, ROCJITSU_CODE_ARCH_CDNA3); + return build_valid_blocks(code, *decoder, ROCJITSU_CODE_ARCH_CDNA3); } std::vector @@ -221,7 +222,7 @@ TEST(SemanticScratchAllocator, GprIndexModeWriteBypassesKernelUnusedTier) { ScratchTestCodeObject code(words); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - auto blocks = BasicBlock::build(code, *decoder, ROCJITSU_CODE_ARCH_CDNA4); + auto blocks = build_valid_blocks(code, *decoder, ROCJITSU_CODE_ARCH_CDNA4); ASSERT_EQ(blocks.size(), 1u); auto scope = scratch_test_scope(blocks); diff --git a/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp b/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp index 4f82253a89b8..ebc7211e9f0f 100644 --- a/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp +++ b/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp @@ -5,6 +5,7 @@ /// @brief Shared fixture implementations for CPU-only DBT translation tests. #include "translate_test_support.h" +#include "decode_test_util.h" #include "elf_test_support.h" #include "rocjitsu/code/amdgpu_code_object.h" @@ -321,7 +322,7 @@ std::unique_ptr decode_one(uint32_t word, rj_code_arch_t arch) { auto decoder = Decoder::create(arch); if (!decoder) return nullptr; - return std::unique_ptr(decoder->decode(&word)); + return std::unique_ptr(decode_valid(*decoder, &word)); } bool has_error_containing(const TranslatedCodeObject &result, DiagnosticKind kind, diff --git a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp index 2a02f4a2a177..86074f1464ae 100644 --- a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp @@ -4,6 +4,7 @@ /// @file translate_gfx1250_test.cpp /// @brief CPU-only tests for gfx1250 revision translation. +#include "decode_test_util.h" #include "rocjitsu/code/amdgpu_code_object.h" #include "rocjitsu/code/amdgpu_elf.h" #include "rocjitsu/code/builders/instruction_builder.h" @@ -1215,7 +1216,7 @@ void expect_cdna3_text_matches(const rocjitsu::Section &text, std::vector> actual; for (size_t pc = 0; pc < word_count;) { SCOPED_TRACE(pc); - auto inst = std::unique_ptr(decoder->decode(&words[pc])); + auto inst = std::unique_ptr(decode_valid(*decoder, &words[pc])); ASSERT_NE(inst, nullptr); ASSERT_GT(inst->size(), 0u); ASSERT_EQ(inst->size() % sizeof(uint32_t), 0u); @@ -1843,7 +1844,7 @@ decode_text_instructions(const rocjitsu::Section &text, rj_code_arch_t arch) { size_t word_offset = 0; while (word_offset < word_count) { std::unique_ptr inst( - decoder->decode(words + word_offset, word_offset * sizeof(rj_code_binary_inst_t))); + decode_valid(*decoder, words + word_offset, word_offset * sizeof(rj_code_binary_inst_t))); if (!inst) break; word_offset += static_cast(inst->size()) / sizeof(rj_code_binary_inst_t); @@ -7657,7 +7658,7 @@ run_gfx1250_e5m3_replacement(uint16_t opcode, uint8_t opsel, Gfx1250E5m3Operand opcode == cdna5::kVCvtPkFp8F32Vop3 ? "v_cvt_pk_fp8_f32" : "v_cvt_sr_fp8_f32"; bool borrowed_a_carrier = false; for (size_t index = 0; index < word_count;) { - std::unique_ptr inst(decoder->decode(text + index)); + std::unique_ptr inst(decode_valid(*decoder, text + index)); if (inst == nullptr) { ADD_FAILURE() << "undecodable replacement word at " << index; return std::nullopt; @@ -8748,7 +8749,9 @@ TEST(SemanticTranslator, Gfx1250ResidualChecksRecognizeEveryActionableSourceRule rocjitsu::ProcessorRevision::Gfx1250A0); for (size_t sample_index = 0; sample_index < samples.size(); ++sample_index) { SCOPED_TRACE(sample_index); - std::unique_ptr inst(decoder->decode(samples[sample_index].data(), 0)); + rocjitsu::DecodeResult decoded = decoder->decode(samples[sample_index].data(), 0); + ASSERT_TRUE(decoded.succeeded()); + std::unique_ptr inst = std::move(decoded).value(); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->encoding_id(), residual_rules[sample_index]->src_encoding_id); EXPECT_EQ(inst->opcode(), residual_rules[sample_index]->src_opcode); @@ -9351,7 +9354,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaLoweringMatchesUnloweredExecution) { std::vector body_words; for (size_t offset = 0; offset < text_word_count;) { - std::unique_ptr inst(decoder->decode(text_words + offset)); + std::unique_ptr inst(decode_valid(*decoder, text_words + offset)); ASSERT_NE(inst, nullptr) << "translated word " << offset << " failed to decode"; const std::string_view mnemonic(inst->mnemonic()); if (mnemonic == "s_endpgm") @@ -9449,7 +9452,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaLoweringMatchesUnloweredExecution) { auto run_source = [&] { const std::array words = {matrix[0], matrix[1]}; - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); EXPECT_NE(inst, nullptr); EXPECT_EQ(std::string_view(inst->mnemonic()), "v_wmma_f16_16x16x128_fp8_fp8"); cu->execute_instruction(inst.get(), *wf); @@ -9457,7 +9460,8 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaLoweringMatchesUnloweredExecution) { auto run_lowered = [&] { for (size_t offset = 0; offset < body_words.size();) { - std::unique_ptr inst(decoder->decode(body_words.data() + offset)); + std::unique_ptr inst( + decode_valid(*decoder, body_words.data() + offset)); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst.get(), *wf); offset += static_cast(inst->size()) / sizeof(uint32_t); @@ -12891,7 +12895,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4SplitMatchesUnsplitExecution) // Collect the translated body, stopping at the terminator. std::vector body_words; for (size_t offset = 0; offset < text_word_count;) { - std::unique_ptr inst(decoder->decode(text_words + offset)); + std::unique_ptr inst(decode_valid(*decoder, text_words + offset)); ASSERT_NE(inst, nullptr) << "translated word " << offset << " failed to decode"; if (std::string_view(inst->mnemonic()) == "s_endpgm") break; @@ -12979,7 +12983,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4SplitMatchesUnsplitExecution) zero_destination(); { const std::array words = {matrix[0], matrix[1]}; - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_wmma_f32_32x16x128_f4"); cu->execute_instruction(inst.get(), *wf); @@ -13001,7 +13005,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4SplitMatchesUnsplitExecution) zero_destination(); size_t executed = 0; for (size_t offset = 0; offset < body_words.size();) { - std::unique_ptr inst(decoder->decode(body_words.data() + offset)); + std::unique_ptr inst(decode_valid(*decoder, body_words.data() + offset)); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst.get(), *wf); offset += static_cast(inst->size()) / sizeof(uint32_t); @@ -14325,7 +14329,7 @@ TEST(BinaryTranslatorE2E, Gfx1250StagesFlatScratchBaseInDestinationWhenSgprsAreL ASSERT_NE(decoder, nullptr); bool found_rewritten_add = false; for (size_t offset = 0; offset < out_words;) { - std::unique_ptr inst(decoder->decode(out + offset)); + std::unique_ptr inst(decode_valid(*decoder, out + offset)); ASSERT_NE(inst, nullptr) << "translated word " << offset << " failed to decode"; if (std::string_view(inst->mnemonic()) == "v_add_nc_u64") { ASSERT_NE(inst->raw_encoding(), nullptr); @@ -14394,7 +14398,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DestinationStagingExecutesInMatchingNonzeroBank auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); for (size_t offset = 0; offset < translated_count;) { - std::unique_ptr inst(decoder->decode(translated_words + offset)); + std::unique_ptr inst(decode_valid(*decoder, translated_words + offset)); ASSERT_NE(inst, nullptr) << "translated word " << offset << " failed to decode"; if (std::string_view(inst->mnemonic()) == "s_endpgm") break; diff --git a/emulation/rocjitsu/tests/dbt/translate_test.cpp b/emulation/rocjitsu/tests/dbt/translate_test.cpp index 1dfd038c7cf5..f8266eb35ea2 100644 --- a/emulation/rocjitsu/tests/dbt/translate_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_test.cpp @@ -1030,15 +1030,20 @@ class RewriteDischargeBoundTestInstruction final : public Instruction { class RewriteDischargeBoundTestDecoder final : public Decoder { public: - RewriteDischargeBoundTestDecoder(size_t max_instruction_words, size_t decoded_words) - : max_instruction_words_(max_instruction_words), decoded_words_(decoded_words) {} + RewriteDischargeBoundTestDecoder(size_t max_instruction_words, size_t decoded_words, + bool reject = false) + : max_instruction_words_(max_instruction_words), decoded_words_(decoded_words), + reject_(reject) {} std::size_t max_instruction_words() const override { return max_instruction_words_; } - Instruction *decode(const rj_code_binary_inst_t *words) override { + DecodeResult decode(const rj_code_binary_inst_t *words, + const DecodeErrorEmitter &emit_error) override { ++decode_calls; observed_words.assign(words, words + max_instruction_words_); - return new RewriteDischargeBoundTestInstruction(decoded_words_); + if (reject_) + return emit_error.emit() << "test decoder rejected encoding"; + return std::make_unique(decoded_words_); } size_t decode_calls = 0; @@ -1047,6 +1052,7 @@ class RewriteDischargeBoundTestDecoder final : public Decoder { private: size_t max_instruction_words_; size_t decoded_words_; + bool reject_; }; TEST(BinaryTranslatorInternal, RewriteDischargeDecodeRejectsWidthBeyondDecoderMaximum) { @@ -1081,6 +1087,22 @@ TEST(BinaryTranslatorInternal, RewriteDischargeDecodeRejectsZeroBoundWithoutDeco EXPECT_EQ(decoder.decode_calls, 0u); } +TEST(BinaryTranslatorInternal, RewriteDischargeDecodeReportsRejectedEncoding) { + RewriteDischargeBoundTestDecoder decoder(/*max_instruction_words=*/1, /*decoded_words=*/1, + /*reject=*/true); + internal::RewriteDischargeInstructionDecoder bounded_decoder(decoder); + constexpr std::array words = {0x11111111u}; + const auto bytes = + std::span(reinterpret_cast(words.data()), sizeof(words)); + std::unique_ptr instruction; + util::StringDiagnostic decode_error; + + EXPECT_EQ(bounded_decoder.decode(bytes, /*source_offset=*/8, instruction, decode_error.emitter()), + internal::RewriteDischargeDecodeStatus::InvalidEncoding); + EXPECT_EQ(instruction, nullptr); + EXPECT_EQ(decode_error.message(), "test decoder rejected encoding"); +} + TEST(BinaryTranslatorInternal, RewriteDischargeDecodeClearsUnusedWordsAcrossCalls) { RewriteDischargeBoundTestDecoder decoder(/*max_instruction_words=*/2, /*decoded_words=*/1); internal::RewriteDischargeInstructionDecoder bounded_decoder(decoder); diff --git a/emulation/rocjitsu/tests/decode_execute_benchmark.cpp b/emulation/rocjitsu/tests/decode_execute_benchmark.cpp index 38c921bd5032..851394034040 100644 --- a/emulation/rocjitsu/tests/decode_execute_benchmark.cpp +++ b/emulation/rocjitsu/tests/decode_execute_benchmark.cpp @@ -11,6 +11,7 @@ /// This benchmark is NOT a pass/fail gate — it reports numbers for tracking /// performance regressions across changesets. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -95,7 +96,7 @@ std::vector build_corpus(const TestEncEntry *encodings, size_t num_ // Try decode — skip if the synthesized encoding doesn't decode. try { - auto *inst = decoder.decode(te.words.data()); + auto *inst = decode_valid(decoder, te.words.data()); if (inst) { corpus.push_back({te.mnemonic, te.words, cat}); delete inst; @@ -177,7 +178,7 @@ void run_benchmark(rj_code_arch_t arch, std::string_view arch_name, const TestEn auto decode_start = Clock::now(); for (int iter = 0; iter < ITERATIONS; ++iter) { for (const auto &entry : corpus) { - auto *inst = decoder->decode(entry.words.data()); + auto *inst = decode_valid(*decoder, entry.words.data()); delete inst; } } @@ -194,7 +195,7 @@ void run_benchmark(rj_code_arch_t arch, std::string_view arch_name, const TestEn auto full_start = Clock::now(); for (int iter = 0; iter < ITERATIONS; ++iter) { for (const auto *entry : executable) { - auto *inst = decoder->decode(entry->words.data()); + auto *inst = decode_valid(*decoder, entry->words.data()); if (inst) { try { cu->execute_instruction(inst, *wf); diff --git a/emulation/rocjitsu/tests/decode_smoke_test.cpp b/emulation/rocjitsu/tests/decode_smoke_test.cpp index 77956361b1ea..12d2568a01ec 100644 --- a/emulation/rocjitsu/tests/decode_smoke_test.cpp +++ b/emulation/rocjitsu/tests/decode_smoke_test.cpp @@ -22,6 +22,7 @@ /// 0xBFB00000 = s_endpgm (op = 48) — RDNA3/3.5/4 /// (GFX11/12: op=1 is s_setkill; s_endpgm moved to op=48) +#include "decode_test_util.h" #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/builders.h" @@ -54,7 +55,6 @@ #include "rocjitsu/vm/amdgpu/l2_cache.h" #include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" -#include "util/except.h" #include @@ -65,6 +65,7 @@ #include #include #include +#include namespace { @@ -115,13 +116,62 @@ struct DecodeCase { class DecoderSmokeTest : public ::testing::TestWithParam {}; +TEST(DecoderDiagnosticTest, ValidEncodingEmitsNothingAndKeepsLocation) { + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + + DecodeResult decoded = decoder->decode(&S_NOP, 24, DecodeErrorEmitter(collect)); + + ASSERT_TRUE(decoded.succeeded()); + EXPECT_EQ(decoded.value()->src_loc(), 24u); + EXPECT_TRUE(messages.empty()); +} + +TEST(DecoderDiagnosticTest, InvalidOpcodeEmitsExactlyOneDiagnostic) { + constexpr uint32_t invalid_opcode = 0xffffffffu; + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + + DecodeResult decoded = decoder->decode(&invalid_opcode, DecodeErrorEmitter(collect)); + + EXPECT_TRUE(decoded.failed()); + ASSERT_EQ(messages.size(), 1u); + EXPECT_EQ(messages.front(), "Invalid instruction opcode: FFFFFFFF"); +} + +TEST(DecoderDiagnosticTest, InvalidOperandEmitsExactlyOneDiagnostic) { + constexpr auto words = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 209, .vdst = 0}); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + std::vector messages; + auto collect = [&](std::string_view message) { messages.emplace_back(message); }; + + DecodeResult decoded = decoder->decode(words.data(), DecodeErrorEmitter(collect)); + + EXPECT_TRUE(decoded.failed()); + ASSERT_EQ(messages.size(), 1u); + EXPECT_EQ(messages.front(), "invalid operand selector"); +} + +TEST(DecoderDiagnosticTest, NoOpEmitterStillRejectsInvalidOpcode) { + constexpr uint32_t invalid_opcode = 0xffffffffu; + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + ASSERT_NE(decoder, nullptr); + + EXPECT_TRUE(decoder->decode(&invalid_opcode).failed()); +} + TEST_P(DecoderSmokeTest, DecodesCorrectly) { const DecodeCase &tc = GetParam(); auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr) << "Decoder::create() returned nullptr for arch=" << tc.arch_name; - std::unique_ptr inst(decoder->decode(&tc.word)); + std::unique_ptr inst(decode_valid(*decoder, &tc.word)); ASSERT_NE(inst, nullptr) << "decode() returned nullptr for arch=" << tc.arch_name << " word=0x" << std::hex << tc.word; @@ -137,7 +187,7 @@ TEST(Gfx1250DecodeTest, DisassemblesDpp8Selectors) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->size(), 8); EXPECT_EQ(inst->mnemonic(), "v_fract_f32_dpp"); @@ -200,14 +250,14 @@ TEST(ScalarRegisterSelectorDecodeTest, Rdna1AndRdna2RejectReservedHole) { for (const auto &[words, expected_selector] : {std::pair{&lower, 123}, std::pair{&upper, 125}}) { std::unique_ptr inst; - ASSERT_NO_THROW(inst.reset(decoder->decode(words->data()))); + inst.reset(decode_valid(*decoder, words->data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->num_dst_operands(), 1); ASSERT_NE(inst->dst_operand(0), nullptr); EXPECT_EQ(inst->dst_operand(0)->encoding_value(), expected_selector); } - EXPECT_THROW(std::unique_ptr(decoder->decode(hole.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, hole.data())); }; validate(ROCJITSU_CODE_ARCH_RDNA1, "rdna1", rdna1_lower, rdna1_hole, rdna1_upper); @@ -223,36 +273,35 @@ TEST(OperandSelectorDecodeTest, Cdna1SdstRejectsReservedHole) { ASSERT_NE(decoder, nullptr); for (const auto &[word, expected_selector] : {std::pair{lower, 124}, std::pair{upper, 126}}) { std::unique_ptr inst; - ASSERT_NO_THROW(inst.reset(decoder->decode(&word))); + inst.reset(decode_valid(*decoder, &word)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->num_dst_operands(), 1); ASSERT_NE(inst->dst_operand(0), nullptr); EXPECT_EQ(inst->dst_operand(0)->encoding_value(), expected_selector); } - EXPECT_THROW(std::unique_ptr(decoder->decode(&hole)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, &hole)); } TEST(OperandSelectorDecodeTest, Cdna1RestrictedScalarSourceRejectsLiteralSelector) { cdna1::Operand valid(32, cdna1::OperandType::OPR_SSRC_NOLIT, 253); - EXPECT_NO_THROW(valid.validate_encoding()); + EXPECT_TRUE(valid.validate_encoding().succeeded()); cdna1::Operand invalid(32, cdna1::OperandType::OPR_SSRC_NOLIT, 255); - EXPECT_THROW(invalid.validate_encoding(), util::InvalidInst); + EXPECT_TRUE(invalid.validate_encoding().failed()); } TEST(OperandSelectorDecodeTest, DirectSourceAndSmemOffsetRejectReservedSelectors) { constexpr auto vop1 = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 209, .vdst = 0}); auto gfx1250_decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(gfx1250_decoder, nullptr); - EXPECT_THROW(std::unique_ptr(gfx1250_decoder->decode(vop1.data())), - util::InvalidInst); + EXPECT_TRUE(decode_fails(*gfx1250_decoder, vop1.data())); constexpr auto smem = cdna1::build_smem(cdna1::kSLoadDwordSmem, {.soffset_en = 1, .soffset = 125}); auto cdna1_decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA1); ASSERT_NE(cdna1_decoder, nullptr); - EXPECT_THROW(std::unique_ptr(cdna1_decoder->decode(smem.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*cdna1_decoder, smem.data())); } TEST(OperandSelectorDecodeTest, RestrictedVectorAndLaneOperandsRejectLiteralMarkers) { @@ -265,7 +314,7 @@ TEST(OperandSelectorDecodeTest, RestrictedVectorAndLaneOperandsRejectLiteralMark words[i] = encoding[i]; words[encoding.size()] = 7; words[encoding.size() + 1] = 0; - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); }; for (const uint16_t marker : {uint16_t{254}, uint16_t{255}}) { @@ -290,7 +339,7 @@ TEST(OperandSelectorDecodeTest, Gfx1250WmmaSrc2ValidatesVgprOrInlineSelector) { SCOPED_TRACE(selector); const auto words = words_for(selector); std::unique_ptr inst; - ASSERT_NO_THROW(inst.reset(decoder->decode(words.data()))); + inst.reset(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->num_src_operands(), 3); ASSERT_NE(inst->src_operand(2), nullptr); @@ -302,7 +351,7 @@ TEST(OperandSelectorDecodeTest, Gfx1250WmmaSrc2ValidatesVgprOrInlineSelector) { {uint16_t{209}, uint16_t{239}, uint16_t{249}, uint16_t{253}, uint16_t{255}}) { SCOPED_TRACE(selector); const auto words = words_for(selector); - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } for (const uint16_t selector : {uint16_t{0}, uint16_t{8}, uint16_t{129}, uint16_t{256}}) { @@ -312,7 +361,7 @@ TEST(OperandSelectorDecodeTest, Gfx1250WmmaSrc2ValidatesVgprOrInlineSelector) { {.vdst = 0, .src0 = 256, .src1 = 256, .src2 = selector}); const std::array words{encoding[0], encoding[1], 0, 0}; std::unique_ptr inst; - ASSERT_NO_THROW(inst.reset(decoder->decode(words.data()))); + inst.reset(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_NE(inst->src_operand(2), nullptr); EXPECT_EQ(inst->src_operand(2)->encoding_value(), selector); @@ -330,7 +379,7 @@ TEST(OperandSelectorDecodeTest, Gfx1250AndRdna4ValidateBarrierIdSelectors) { SCOPED_TRACE(static_cast(selector)); const auto words = build(selector); std::unique_ptr inst; - ASSERT_NO_THROW(inst.reset(decoder->decode(words.data()))); + inst.reset(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->num_src_operands(), 1); ASSERT_NE(inst->src_operand(0), nullptr); @@ -340,14 +389,14 @@ TEST(OperandSelectorDecodeTest, Gfx1250AndRdna4ValidateBarrierIdSelectors) { for (const uint8_t selector : std::array{0, 126, 160, 192}) { SCOPED_TRACE(static_cast(selector)); const auto words = build(selector); - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } for (const uint8_t marker : {uint8_t{254}, uint8_t{255}}) { SCOPED_TRACE(static_cast(marker)); const auto base = build(marker); const std::array words = {base[0], 7, 0}; - EXPECT_THROW(std::unique_ptr(decoder->decode(words.data())), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } }; @@ -392,7 +441,7 @@ TEST(RawEncodingTest, PreservesScalarLiteralWordsAcrossAmdgpuIsas) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr) << tc.arch_name; std::unique_ptr inst; - ASSERT_NO_THROW(inst.reset(decoder->decode(words))) << tc.arch_name; + inst.reset(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr) << tc.arch_name; ASSERT_EQ(inst->size(), sizeof(words)) << tc.arch_name; ASSERT_NE(inst->raw_encoding(), nullptr) << tc.arch_name; @@ -406,7 +455,7 @@ TEST(SendmsgReturnDecodeTest, Rdna3Selector255DoesNotConsumeLiteral) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(&word)); + std::unique_ptr inst(decode_valid(*decoder, &word)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_sendmsg_rtn_b32"); EXPECT_EQ(inst->size(), sizeof(word)); @@ -422,7 +471,7 @@ TEST(FieldlessOperandDecodeTest, SaveexecExposesInertExecAndSccOperands) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->mnemonic(), "s_and_saveexec_b64"); ASSERT_EQ(inst->num_dst_operands(), 3); @@ -570,7 +619,7 @@ TEST(Rdna4WaitcntDecodeSmokeTest, FormatsCompatWaitcntWithGfx11Layout) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(&s_waitcnt_vmcnt1)); + std::unique_ptr inst(decode_valid(*decoder, &s_waitcnt_vmcnt1)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_waitcnt"); EXPECT_EQ(inst->disassemble(), "s_waitcnt vmcnt(1) expcnt(0) lgkmcnt(0)"); @@ -598,7 +647,7 @@ TEST(CdnaF16DeclaredLiteralDecodeTest, MasksExtensionToDeclaredOperandWidth) { }; auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->mnemonic(), tc.mnemonic); @@ -751,7 +800,7 @@ TEST(Rdna3DecodeTest, GlobalFlatAllOnesSaddrIsNull) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "global_load_b64"); // vaddr + the fieldless OPR_GPUMEM memory operand (saddr is null, so it @@ -806,7 +855,7 @@ TEST_P(RdnaVopdDecodeSmokeTest, DecodesDualSlotForms) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr) << tc.arch_name; - std::unique_ptr inst(decoder->decode(tc.words.data())); + std::unique_ptr inst(decode_valid(*decoder, tc.words.data())); ASSERT_NE(inst, nullptr) << tc.arch_name << " " << tc.case_name; EXPECT_EQ(inst->mnemonic(), tc.expected_mnemonic); EXPECT_EQ(inst->size(), tc.expected_size_bytes); @@ -887,8 +936,7 @@ TEST_P(InvalidVopdSlotDecodeTest, RejectsOpcodeOutsideProfileSlot) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr) << tc.arch_name; - EXPECT_THROW(static_cast(decoder->decode(tc.words.data())), util::InvalidInst) - << tc.arch_name << " " << tc.case_name; + EXPECT_TRUE(decode_fails(*decoder, tc.words.data())) << tc.arch_name << " " << tc.case_name; } INSTANTIATE_TEST_SUITE_P( @@ -929,7 +977,7 @@ TEST_P(RdnaInvalidVopdDecodeSmokeTest, DoesNotClaimVopd3Encoding) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr) << tc.arch_name; - EXPECT_THROW(static_cast(decoder->decode(tc.words.data())), util::InvalidInst) + EXPECT_TRUE(decode_fails(*decoder, tc.words.data())) << tc.arch_name << " should reserve the 0xCF VOPD3 prefix"; } @@ -993,7 +1041,7 @@ TEST_P(RdnaVopdExecutionSmokeTest, PreservesFpRoundingAndDx9ZeroSemantics) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); const uint32_t vb = wf->vgpr_alloc().base; @@ -1049,7 +1097,7 @@ TEST_P(RdnaVopdExecutionSmokeTest, DualCndmaskConsumesVccLo) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(kWords.data())); + std::unique_ptr inst(decode_valid(*decoder, kWords.data())); ASSERT_NE(inst, nullptr); const uint32_t vb = wf->vgpr_alloc().base; @@ -1127,7 +1175,7 @@ TEST_P(RdnaVopdExecutionSmokeTest, DualCndmaskAfterScalarVccMerge) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr); const auto execute = [&](const std::array &inst_words) { - std::unique_ptr inst(decoder->decode(inst_words.data())); + std::unique_ptr inst(decode_valid(*decoder, inst_words.data())); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst.get(), *wf); }; @@ -1333,7 +1381,7 @@ TEST_P(MubufLdsModifierTest, LdsModifierInDisassembly) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(tc.words)); + std::unique_ptr inst(decode_valid(*decoder, tc.words)); ASSERT_NE(inst, nullptr) << "decode() returned nullptr for " << tc.arch_name; EXPECT_EQ(inst->mnemonic(), "buffer_load_dword"); @@ -1372,7 +1420,7 @@ TEST(Cdna3DecodeTest, DsRead2st64AccDestinationUsesAccumulatorRegisterClass) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "ds_read2st64_b32"); EXPECT_EQ(inst->disassemble(), "ds_read2st64_b32 acc[62:63], v243"); @@ -1391,7 +1439,7 @@ TEST(Cdna3DecodeTest, MfmaAccCdUsesAccumulatorRegisterClassForCAndD) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_mfma_f32_32x32x8_bf16"); EXPECT_EQ(inst->disassemble(), @@ -1421,7 +1469,7 @@ TEST(Cdna3DecodeTest, MfmaAccBitsSelectIndependentMultiplicandBanks) { ASSERT_NE(decoder, nullptr); for (const auto &tc : cases) { const uint32_t words[] = {0xD3E08088u, tc.high_word}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->mnemonic(), "v_mfma_f32_32x32x8_bf16"); @@ -1439,7 +1487,7 @@ TEST(Cdna3DecodeTest, MfmaAccCdPreservesInlineConstantSrc2) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_mfma_f32_32x32x8_bf16"); EXPECT_EQ(inst->disassemble(), "v_mfma_f32_32x32x8_bf16 acc[136:151], acc[84:85], acc[82:83], 0"); @@ -1461,14 +1509,14 @@ TEST(Cdna2DecodeTest, MemoryAccBitSelectsAccumulatorDestination) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA2); ASSERT_NE(decoder, nullptr); for (const auto &tc : cases) { - std::unique_ptr vgpr_inst(decoder->decode(tc.vgpr_words.data())); + std::unique_ptr vgpr_inst(decode_valid(*decoder, tc.vgpr_words.data())); ASSERT_NE(vgpr_inst, nullptr) << tc.mnemonic; ASSERT_EQ(vgpr_inst->mnemonic(), tc.mnemonic); const auto vgpr_dst = vgpr_inst->dst_operand(0)->to_register_ref(); ASSERT_TRUE(vgpr_dst.has_value()) << vgpr_inst->disassemble(); EXPECT_EQ(*vgpr_dst, (RegisterRef{RegClass::VGPR, 5, tc.width})) << vgpr_inst->disassemble(); - std::unique_ptr accvgpr_inst(decoder->decode(tc.accvgpr_words.data())); + std::unique_ptr accvgpr_inst(decode_valid(*decoder, tc.accvgpr_words.data())); ASSERT_NE(accvgpr_inst, nullptr) << tc.mnemonic; ASSERT_EQ(accvgpr_inst->mnemonic(), tc.mnemonic); const auto accvgpr_dst = accvgpr_inst->dst_operand(0)->to_register_ref(); @@ -1487,7 +1535,7 @@ TEST(Gfx1250DecodeTest, FmamkF64ConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_fmamk_f64_e32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -1505,7 +1553,7 @@ TEST(Gfx1250DecodeTest, FmaakF64ConsumesThreeDwords) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_fmaak_f64_e32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -1521,7 +1569,7 @@ TEST(Gfx1250DecodeTest, Vop3True16DestinationUsesFullEightBitVgprIndex) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_and_b16"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -1545,7 +1593,7 @@ TEST(Gfx1250DecodeTest, FlatVaddrWidthFollowsSaddrMode) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr saddr_inst(decoder->decode(saddr_words)); + std::unique_ptr saddr_inst(decode_valid(*decoder, saddr_words)); ASSERT_NE(saddr_inst, nullptr); EXPECT_EQ(saddr_inst->mnemonic(), "flat_load_b64"); EXPECT_EQ(saddr_inst->disassemble(), "flat_load_b64 v[2:3], v1, s[6:7]"); @@ -1566,7 +1614,7 @@ TEST(Gfx1250DecodeTest, FlatVaddrWidthFollowsSaddrMode) { EXPECT_FALSE(saddr_def_use.uses.contains({RegClass::VGPR, 1, 2})); EXPECT_TRUE(saddr_def_use.uses.contains({RegClass::SGPR, 6, 2})); - std::unique_ptr vector_only_inst(decoder->decode(vector_only_words)); + std::unique_ptr vector_only_inst(decode_valid(*decoder, vector_only_words)); ASSERT_NE(vector_only_inst, nullptr); EXPECT_EQ(vector_only_inst->mnemonic(), "flat_load_b64"); EXPECT_EQ(vector_only_inst->num_src_operands(), 2); // vaddr + gpumem @@ -1593,7 +1641,7 @@ TEST(Gfx1250DecodeTest, GlobalVaddrWidthFollowsSaddrMode) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr saddr_inst(decoder->decode(saddr_words)); + std::unique_ptr saddr_inst(decode_valid(*decoder, saddr_words)); ASSERT_NE(saddr_inst, nullptr); EXPECT_EQ(saddr_inst->mnemonic(), "global_load_b64"); EXPECT_EQ(saddr_inst->disassemble(), "global_load_b64 v[2:3], v10, s[6:7]"); @@ -1614,7 +1662,7 @@ TEST(Gfx1250DecodeTest, GlobalVaddrWidthFollowsSaddrMode) { EXPECT_FALSE(saddr_def_use.uses.contains({RegClass::VGPR, 10, 2})); EXPECT_TRUE(saddr_def_use.uses.contains({RegClass::SGPR, 6, 2})); - std::unique_ptr vector_only_inst(decoder->decode(vector_only_words)); + std::unique_ptr vector_only_inst(decode_valid(*decoder, vector_only_words)); ASSERT_NE(vector_only_inst, nullptr); EXPECT_EQ(vector_only_inst->mnemonic(), "global_load_b64"); EXPECT_EQ(vector_only_inst->num_src_operands(), 2); // vaddr + gpumem @@ -1634,7 +1682,7 @@ TEST(Gfx1250DecodeTest, GlobalStoreUsesScalarOffsetVaddrWidth) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "global_store_b64"); EXPECT_EQ(inst->disassemble(), "global_store_b64 v10, v[2:3], s[6:7]"); @@ -1651,7 +1699,7 @@ TEST(Gfx1250DecodeTest, Vop3CompareWritesSingleScalarMaskRegister) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_cmp_gt_u32"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -1673,7 +1721,7 @@ TEST(Cdna4DecodeTest, MfmaF8f6f4DecodesStandaloneVop3pSuffix) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_mfma_f32_16x16x128_f8f6f4"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -1701,7 +1749,7 @@ TEST(Cdna4DecodeTest, MfmaF8f6f4SourceWidthsFollowFormatSelectors) { 0xD3AD0024u | (format << 8), 0x00024100u | (format << 29), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(inst->mnemonic(), "v_mfma_f32_16x16x128_f8f6f4"); @@ -1725,7 +1773,7 @@ TEST(Cdna4DecodeTest, MfmaScaleF8f6f4ConsumesVop3px2Prefix) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_mfma_f32_16x16x128_f8f6f4"); EXPECT_EQ(inst->size(), sizeof(words)); @@ -1744,7 +1792,7 @@ TEST(AccVgprSrcCanonicalizationTest, MalformedRawSrcBelow256StaysInUnifiedRange) ASSERT_NE(decoder, nullptr); for (uint32_t raw : {0u, 5u, 128u, 255u}) { const uint32_t words[] = {0xD3D84003u, 0x18000000u | raw}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_accvgpr_read"); ASSERT_EQ(inst->num_src_operands(), 1); @@ -1765,7 +1813,7 @@ TEST(AccVgprSrcCanonicalizationTest, LegalRawSrcResolvesToUnifiedAccIndex) { ASSERT_NE(decoder, nullptr); for (uint32_t n : {0u, 1u, 63u}) { const uint32_t words[] = {0xD3D84003u, 0x18000000u | (256u + n)}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_accvgpr_read"); ASSERT_EQ(inst->num_src_operands(), 1); @@ -1786,7 +1834,7 @@ TEST(Cdna4DecodeTest, RejectsVop3px2PrefixWithoutMfmaSuffix) { 0xD3AC0000u, 0x00000000u, }; - EXPECT_THROW(static_cast(decoder->decode(unrelated_opcode)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, unrelated_opcode)); const uint32_t wrong_encoding[] = { 0xD3AC0000u, @@ -1794,7 +1842,7 @@ TEST(Cdna4DecodeTest, RejectsVop3px2PrefixWithoutMfmaSuffix) { 0xD32D0000u, 0x00000000u, }; - EXPECT_THROW(static_cast(decoder->decode(wrong_encoding)), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, wrong_encoding)); } TEST(Cdna4DecodeTest, MfmaScaleF8f6f4AcceptsSecondVop3px2Suffix) { @@ -1807,7 +1855,7 @@ TEST(Cdna4DecodeTest, MfmaScaleF8f6f4AcceptsSecondVop3px2Suffix) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_mfma_f32_32x32x64_f8f6f4"); EXPECT_EQ(inst->size(), sizeof(words)); diff --git a/emulation/rocjitsu/tests/decode_test_util.h b/emulation/rocjitsu/tests/decode_test_util.h new file mode 100644 index 000000000000..65592ba7cc2b --- /dev/null +++ b/emulation/rocjitsu/tests/decode_test_util.h @@ -0,0 +1,58 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#ifndef ROCJITSU_TESTS_DECODE_TEST_UTIL_H_ +#define ROCJITSU_TESTS_DECODE_TEST_UTIL_H_ + +#include "rocjitsu/code/basic_block.h" +#include "rocjitsu/isa/decoder.h" + +#include + +#include +#include + +namespace rocjitsu { + +/// Decode an instruction encoding expected to be valid by the surrounding test. +/// +/// Returning nullptr preserves the existing assertion style at valid-decode +/// call sites while rejection-specific tests inspect DecodeResult directly. +inline Instruction *decode_valid(Decoder &decoder, const rj_code_binary_inst_t *inst) { + DecodeResult result = decoder.decode(inst); + if (result.failed()) + return nullptr; + return result.value().release(); +} + +inline Instruction *decode_valid(Decoder &decoder, const rj_code_binary_inst_t *inst, + uint64_t src_loc) { + DecodeResult result = decoder.decode(inst, src_loc); + if (result.failed()) + return nullptr; + return result.value().release(); +} + +inline bool decode_fails(Decoder &decoder, const rj_code_binary_inst_t *inst) { + return decoder.decode(inst).failed(); +} + +/// Unwrap a block build expected to succeed by the surrounding test. +inline std::vector> +build_valid_blocks(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, + std::span extra_leaders = {}, + ExternalEntryPolicy entry_policy = ExternalEntryPolicy::InferPredecessorless, + std::span extra_split_points = {}) { + util::StringDiagnostic decode_error; + auto result = BasicBlock::build(co, decoder, arch, decode_error.emitter(), extra_leaders, + entry_policy, extra_split_points); + if (result.failed()) { + ADD_FAILURE() << "failed to build expected-valid blocks: " << decode_error.message(); + return {}; + } + return std::move(result).value(); +} + +} // namespace rocjitsu + +#endif // ROCJITSU_TESTS_DECODE_TEST_UTIL_H_ diff --git a/emulation/rocjitsu/tests/decoder_c_api_test.cpp b/emulation/rocjitsu/tests/decoder_c_api_test.cpp index 15eda922d849..7f35941c367a 100644 --- a/emulation/rocjitsu/tests/decoder_c_api_test.cpp +++ b/emulation/rocjitsu/tests/decoder_c_api_test.cpp @@ -1,6 +1,7 @@ // Copyright (c) 2026 Advanced Micro Devices, Inc. // SPDX-License-Identifier: MIT +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -132,7 +133,7 @@ TEST(DecoderCApiTest, HeapAllocationScopeForgetsDestroyedPool) { auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA3); ASSERT_NE(decoder, nullptr); - std::unique_ptr instruction(decoder->decode(&kCdnaSEndpgm)); + std::unique_ptr instruction(decode_valid(*decoder, &kCdnaSEndpgm)); ASSERT_NE(instruction, nullptr); EXPECT_EQ(instruction->mnemonic(), "s_endpgm"); } diff --git a/emulation/rocjitsu/tests/execution_plugin_test.cpp b/emulation/rocjitsu/tests/execution_plugin_test.cpp index 10f661968e98..3fa6a3b695ca 100644 --- a/emulation/rocjitsu/tests/execution_plugin_test.cpp +++ b/emulation/rocjitsu/tests/execution_plugin_test.cpp @@ -10,6 +10,7 @@ /// Machine-level preservation below RegisterAccess must not add callbacks. #include "aql_queue.h" +#include "decode_test_util.h" #include "embedded_schema.h" #include "rocjitsu/code/amdgpu_elf.h" @@ -1063,7 +1064,7 @@ TEST(ExecutionPluginTest, ValuSimdReadObservationUsesActiveExecMask) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); uint32_t words[4] = {vop2_encode(/*opcode=*/52, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256), 0u, 0u, 0u}; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst, *wf); delete inst; @@ -1095,7 +1096,7 @@ TEST(ExecutionPluginTest, ValuSimdWriteObservationUsesActiveExecMask) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); uint32_t words[4] = {vop2_encode(/*opcode=*/52, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256), 0u, 0u, 0u}; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst, *wf); delete inst; @@ -1142,7 +1143,7 @@ TEST(ExecutionPluginTest, DppObservationReportsExactSourceAndDestinationLanes) { vop1_encode(/*opcode=*/1, kDst, amdgpu::SRC_DPP), vop1_dpp_word(kSrc, /*dpp_ctrl=*/0, /*row_mask=*/0x1, /*bank_mask=*/0x5), }; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst, *wf); @@ -1191,7 +1192,7 @@ TEST(ExecutionPluginTest, DppOutOfBoundsObservationHonorsBoundCtrl) { vop1_dpp_word(kSrc, amdgpu::dpp::ROW_SHR1, /*row_mask=*/0xF, /*bank_mask=*/0xF, bound_ctrl), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst.get(), *wf); @@ -1238,7 +1239,7 @@ TEST(ExecutionPluginTest, DppSourceDestinationAliasStagesBeforeWriting) { vop1_dpp_word(kReg, /*quad_perm:[1,0,3,2]=*/0xB1, /*row_mask=*/0x1, /*bank_mask=*/0x1, /*bound_ctrl=*/true), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst.get(), *wf); @@ -1283,7 +1284,7 @@ TEST(ExecutionPluginTest, Dpp8FetchInactiveControlsSourceObservation) { vop1_encode(/*v_mov_b32 opcode=*/1, kDst, src_marker), kSrc | (lane_sel << 8u), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); plugin->events.clear(); f.cu->execute_instruction(inst.get(), *wf); @@ -1342,7 +1343,7 @@ TEST(ExecutionPluginTest, True16InstructionsReportSelectedSourceAndDestinationHa f.cu->write_vgpr(vb + 1, 0, 0xAAAA5555u); f.cu->write_vgpr(vb + 129, 0, 0xDEADBEEFu); - std::unique_ptr inst(decoder->decode(&test_case.word)); + std::unique_ptr inst(decode_valid(*decoder, &test_case.word)); ASSERT_NE(inst, nullptr); plugin->events.clear(); f.cu->execute_instruction(inst.get(), *wf); @@ -1387,7 +1388,7 @@ TEST(ExecutionPluginTest, Gfx1250Simd64BitWriteReportsBothDestinationRegisters) vop1_encode(/*v_mov_b64 opcode=*/29, kDst, /*generic VGPR source=*/256 + kSrc); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(&word)); + std::unique_ptr inst(decode_valid(*decoder, &word)); ASSERT_NE(inst, nullptr); plugin->events.clear(); f.cu->execute_instruction(inst.get(), *wf); @@ -1671,7 +1672,7 @@ TEST(ExecutionPluginTest, SdwaFloatingModifiersUseSemanticSourceWidth) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); std::unique_ptr f32_inst( - decoder->decode(reinterpret_cast(&add_f32))); + decode_valid(*decoder, reinterpret_cast(&add_f32))); ASSERT_NE(f32_inst, nullptr); cu->write_vgpr(vb + kSrc0, 0, std::bit_cast(-2.0f)); cu->write_vgpr(vb + kSrc1, 0, std::bit_cast(0.5f)); @@ -1690,7 +1691,7 @@ TEST(ExecutionPluginTest, SdwaFloatingModifiersUseSemanticSourceWidth) { cvt_bf16.dst_unused = amdgpu::sdwa::UNUSED_PAD; std::unique_ptr bf16_inst( - decoder->decode(reinterpret_cast(&cvt_bf16))); + decode_valid(*decoder, reinterpret_cast(&cvt_bf16))); ASSERT_NE(bf16_inst, nullptr); ASSERT_EQ(std::string_view(bf16_inst->mnemonic()), "v_cvt_f32_bf16_sdwa"); cu->write_vgpr(vb + kSrc0, 0, 0xCAFE'C000u); @@ -1712,7 +1713,7 @@ TEST(ExecutionPluginTest, SdwaFloatingModifiersUseSemanticSourceWidth) { add_f16.dst_unused = amdgpu::sdwa::UNUSED_PAD; std::unique_ptr f16_inst( - decoder->decode(reinterpret_cast(&add_f16))); + decode_valid(*decoder, reinterpret_cast(&add_f16))); ASSERT_NE(f16_inst, nullptr); const uint32_t shift = selection == amdgpu::sdwa::WORD_1 ? 16u : 0u; const uint32_t selected_word_mask = uint32_t{0xFFFF} << shift; @@ -1755,7 +1756,8 @@ TEST(ExecutionPluginTest, SdwaVop2Src1SelectorReportsExactBytes) { raw.dst_unused = amdgpu::sdwa::UNUSED_PAD; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); - std::unique_ptr inst(decoder->decode(reinterpret_cast(&raw))); + std::unique_ptr inst( + decode_valid(*decoder, reinterpret_cast(&raw))); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst.get(), *wf); @@ -1809,7 +1811,8 @@ TEST(ExecutionPluginTest, SdwaVop2ScalarSelectorsUseSgprs) { raw.dst_unused = amdgpu::sdwa::UNUSED_PAD; auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); - std::unique_ptr inst(decoder->decode(reinterpret_cast(&raw))); + std::unique_ptr inst( + decode_valid(*decoder, reinterpret_cast(&raw))); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst.get(), *wf); @@ -1891,7 +1894,7 @@ TEST(ExecutionPluginTest, SdwaObservationReportsExactSourceAndDestinationBytes) vop1_encode(/*opcode=*/1, kDst, amdgpu::SRC_SDWA), vop1_sdwa_word(kSrc, test_case.dst_sel, test_case.dst_unused, test_case.src0_sel), }; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst, *wf); @@ -1947,7 +1950,7 @@ TEST(ExecutionPluginTest, SdwaClampIsAppliedInsideArchitecturalDestinationWrite) vop1_sdwa_word(kSrc, amdgpu::sdwa::DWORD, amdgpu::sdwa::UNUSED_PAD, amdgpu::sdwa::DWORD, /*clamp=*/true), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst.get(), *wf); @@ -1984,7 +1987,7 @@ TEST(ExecutionPluginTest, SdwaClampHonorsDx10ClampMode) { vop1_sdwa_word(kSrc, amdgpu::sdwa::DWORD, amdgpu::sdwa::UNUSED_PAD, amdgpu::sdwa::DWORD, /*clamp=*/true), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); struct Case { @@ -2028,7 +2031,7 @@ TEST(ExecutionPluginTest, SdwaPartialPreserveClampReportsFullDwordWrite) { vop1_sdwa_word(kSrc, amdgpu::sdwa::BYTE_1, amdgpu::sdwa::UNUSED_PRESERVE, amdgpu::sdwa::DWORD, /*clamp=*/true), }; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); plugin->events.clear(); cu->execute_instruction(inst.get(), *wf); @@ -2145,7 +2148,7 @@ TEST(ExecutionPluginTest, F64SimdSourceReadObservationReportsBothHalves) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); uint32_t words[4] = {vop2_encode(/*opcode=*/4, /*vdst=*/4, /*vsrc1=*/2, /*src0=*/256), 0u, 0u, 0u}; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst, *wf); delete inst; @@ -2177,7 +2180,7 @@ TEST(ExecutionPluginTest, Vop3FmacSimdReadObservationReportsAccumulator) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(/*opcode=*/315, /*vdst=*/4, /*src0=*/256, /*src1=*/257, words); - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst, *wf); delete inst; diff --git a/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h b/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h index 837540daa5e5..57afe953bb55 100644 --- a/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h +++ b/emulation/rocjitsu/tests/fixtures/downstream_isa_fixture.h @@ -6,6 +6,7 @@ #pragma once +#include "rocjitsu/isa/decode_result.h" #include "rocjitsu/isa/instruction.h" #include @@ -28,7 +29,7 @@ class DownstreamIsa { public: // Source-integrated decoders publish their maximum encoded width and raw lookahead. static constexpr std::size_t kMaxInstructionWords = 1; - static std::unique_ptr decode(const rj_code_binary_inst_t *raw) { + static DecodeResult decode(const rj_code_binary_inst_t *raw, const DecodeErrorEmitter &) { return std::make_unique(raw); } }; diff --git a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp index cc9419c6906a..21e62c9ce852 100644 --- a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp +++ b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp @@ -9,6 +9,7 @@ /// rejected, and UnimplementedInst results must exactly match the explicit /// expectation for that ISA. +#include "decode_test_util.h" #include "rocjitsu/base/rj_compiler.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/arch/amdgpu/cdna5/isa.h" @@ -309,16 +310,7 @@ void run_execution_harness(rj_code_arch_t arch, std::string_view arch_name, } // Decode the instruction. - std::unique_ptr inst; - try { - inst.reset(decoder->decode(te.words.data())); - } catch (const util::InvalidInst &) { - decode_fail_list.emplace_back(te.mnemonic); - continue; - } catch (...) { - decode_fail_list.emplace_back(te.mnemonic); - continue; - } + std::unique_ptr inst(decode_valid(*decoder, te.words.data())); if (!inst) { decode_fail_list.emplace_back(te.mnemonic); continue; @@ -446,7 +438,7 @@ TEST(Rdna4ExecMaskTest, Wave32ExecHiRemainsAvailableAsScalarScratch) { for (size_t i = 0; i < sequence.size(); ++i) { const uint32_t words[] = {sequence[i].first, 0}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), sequence[i].second); cu->execute_instruction(inst.get(), *wf); @@ -465,7 +457,7 @@ TEST(Rdna4ExecMaskTest, Wave32ExecHiRemainsAvailableAsScalarScratch) { wf->set_exec_raw(0xdeadbeef'ffffffffULL); const auto mov_b64 = encode_sop1(/*s_mov_b64=*/1, /*exec=*/126, /*s0=*/0); - std::unique_ptr inst(decoder->decode(mov_b64.data())); + std::unique_ptr inst(decode_valid(*decoder, mov_b64.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "s_mov_b64"); cu->execute_instruction(inst.get(), *wf); @@ -513,7 +505,7 @@ TEST(Gfx1250MemoryExecutionHarness, ExecutesRepresentativeValidAddressStores) { // global_store_b32 v0, v1, s[4:5] const uint32_t global_store_words[] = {0xEE068004u, 0x00800000u, 0x00000000u}; - std::unique_ptr global_store(decoder->decode(global_store_words)); + std::unique_ptr global_store(decode_valid(*decoder, global_store_words)); ASSERT_NE(global_store, nullptr); ASSERT_EQ(std::string_view(global_store->mnemonic()), "global_store_b32"); cu.execute_and_route(global_store.release(), *wf); @@ -537,7 +529,7 @@ TEST(Gfx1250MemoryExecutionHarness, ExecutesRepresentativeValidAddressStores) { // buffer_store_b32 v0, v5, s[4:7], m0 offen const uint32_t buffer_store_words[] = {0xC406807Du, 0x40800800u, 0x00000005u}; - std::unique_ptr buffer_store(decoder->decode(buffer_store_words)); + std::unique_ptr buffer_store(decode_valid(*decoder, buffer_store_words)); ASSERT_NE(buffer_store, nullptr); ASSERT_EQ(std::string_view(buffer_store->mnemonic()), "buffer_store_b32"); cu.execute_and_route(buffer_store.release(), *wf); @@ -575,7 +567,7 @@ TEST(Rdna4ScalarSccTest, AddSubCoI32UseSignedOverflow) { const uint32_t sb = wf->sgpr_alloc().base; auto run = [&](const std::array &words, std::string_view mnemonic, uint32_t lhs, uint32_t rhs, uint32_t expected_result, bool expected_scc) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); @@ -634,7 +626,7 @@ void run_scalar_cvt_preserves_scc(rj_code_arch_t arch, std::string_view arch_nam const auto &tc = cases[i]; const auto words = encode_sop1(tc.op, /*sdst=*/1, /*ssrc0=*/0); for (bool initial_scc : std::array{false, true}) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), tc.mnemonic) << arch_name; @@ -742,7 +734,7 @@ TEST(Cdna4Vop3Test, CmpClassF16WritesWave64UpperMaskDword) { // CDNA4 v_cmp_class_f16 s0, v0, v1. const uint32_t words[] = {0xD0140000U, 0x00020300U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_class_f16"); cu->execute_instruction(inst.get(), *wf); @@ -796,7 +788,7 @@ TEST(CdnaVop3True16Test, B16I16U16OpsUseOpSelAndCdnaDestinationPolicy) { const uint32_t vb = wf->vgpr_alloc().base; auto execute = [&](const std::array &words, std::string_view mnemonic) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr) << arch.name << " " << mnemonic; ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic) << arch.name; cu->execute_instruction(inst.get(), *wf); @@ -879,7 +871,7 @@ TEST(Rdna3Dot2ExecutionTest, Vop2Dot2accF32F16AccumulatesDst) { cu->write_vgpr(vb + 2, 0, std::bit_cast(5.0f)); const auto words = encode_vop2(/*op=*/2, /*vdst=*/2, /*src0=*/256, /*vsrc1=*/1); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dot2acc_f32_f16_e32"); cu->execute_instruction(inst.get(), *wf); @@ -920,7 +912,7 @@ TEST(Rdna4Dot2True16ExecutionTest, F16AppliesVop3ModifiersAndSelectedHalves) { const auto words = encode_vop3(/*op=*/0x266, /*vdst=*/3, /*src0=*/256, /*src1=*/257, /*src2=*/258, /*abs=*/0x1, /*opsel=*/0xCu, /*clamp=*/1, /*omod=*/3, /*neg=*/0x2); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dot2_f16_f16"); cu->execute_instruction(inst.get(), *wf); @@ -960,7 +952,7 @@ TEST(Rdna4Dot2True16ExecutionTest, Bf16UsesSelectedAccumulatorAndDestinationHalf const auto words = encode_vop3(/*op=*/0x267, /*vdst=*/3, /*src0=*/256, /*src1=*/257, /*src2=*/258, /*abs=*/0, /*opsel=*/0x4u); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dot2_bf16_bf16"); cu->execute_instruction(inst.get(), *wf); @@ -1012,7 +1004,7 @@ void run_cdna4_dot2_f32_bf16(bool force_scalar) { .src1 = static_cast(257), .src2 = static_cast(258), .op_sel_hi = 3}); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dot2_f32_bf16"); cu->execute_instruction(inst.get(), *wf); @@ -1073,7 +1065,7 @@ TEST(Cdna4Permlane16SwapExecutionTest, Wave64SwapsAllFourGroups) { const auto words = cdna4::build_vop1( cdna4::kVPermlane16SwapB32Vop1, {.src0 = static_cast(256 + vsrc_reg), .vdst = static_cast(vdst_reg)}); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_permlane16_swap_b32_e32"); cu->execute_instruction(inst.get(), *wf); @@ -1222,7 +1214,7 @@ TEST(Gfx1250WmmaTest, F16Fp8K64MatchesReferenceLayout) { 0xCC6E0000U | 40u, (256u + 10u) | ((256u + 20u) << 9u) | ((256u + 30u) << 18u), }; - std::unique_ptr inst(decoder->decode(wmma_words)); + std::unique_ptr inst(decode_valid(*decoder, wmma_words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_wmma_f16_16x16x64_fp8_fp8"); cu->execute_instruction(inst.get(), *wf); @@ -1364,7 +1356,7 @@ TEST(Gfx1250Dpp8Test, Vop2AddF16UsesPermutedSourceLanes) { 0x64000000u | amdgpu::SRC_DPP8_FI_0 | (kSrc1 << 9u) | (kDst << 17u), kSrc0 | (lane_sel << 8u), }; - std::unique_ptr inst(decoder->decode(add_f16_dpp8_words)); + std::unique_ptr inst(decode_valid(*decoder, add_f16_dpp8_words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_add_f16_dpp"); EXPECT_EQ(inst->disassemble(), "v_add_f16_dpp v4.l, v2, v3.l dpp8:[7,0,3,2,5,4,1,6]"); @@ -1406,7 +1398,7 @@ TEST(Gfx1250ExecMaskTest, CmpxNeqAndScalarOrRestoreExec) { // s_mov_b32 s1, exec_lo const uint32_t save_exec_words[] = {0xBE81007EU, 0}; - std::unique_ptr save_exec(decoder->decode(save_exec_words)); + std::unique_ptr save_exec(decode_valid(*decoder, save_exec_words)); ASSERT_NE(save_exec, nullptr); ASSERT_EQ(std::string_view(save_exec->mnemonic()), "s_mov_b32"); cu->execute_instruction(save_exec.get(), *wf); @@ -1420,7 +1412,7 @@ TEST(Gfx1250ExecMaskTest, CmpxNeqAndScalarOrRestoreExec) { // v_cmpx_neq_f32_e32 0, v4 const uint32_t mask_zero_lane_words[] = {0x7D3A0880U, 0}; - std::unique_ptr mask_zero_lane(decoder->decode(mask_zero_lane_words)); + std::unique_ptr mask_zero_lane(decode_valid(*decoder, mask_zero_lane_words)); ASSERT_NE(mask_zero_lane, nullptr); ASSERT_EQ(std::string_view(mask_zero_lane->mnemonic()), "v_cmpx_neq_f32_e32"); cu->execute_instruction(mask_zero_lane.get(), *wf); @@ -1428,7 +1420,7 @@ TEST(Gfx1250ExecMaskTest, CmpxNeqAndScalarOrRestoreExec) { // s_or_b32 exec_lo, exec_lo, s1 const uint32_t restore_exec_words[] = {0x8C7E017EU, 0}; - std::unique_ptr restore_exec(decoder->decode(restore_exec_words)); + std::unique_ptr restore_exec(decode_valid(*decoder, restore_exec_words)); ASSERT_NE(restore_exec, nullptr); ASSERT_EQ(std::string_view(restore_exec->mnemonic()), "s_or_b32"); cu->execute_instruction(restore_exec.get(), *wf); @@ -1468,7 +1460,7 @@ TEST(Gfx1250ExecMaskTest, Vop3CmpxGtI32KeepsInRangeLanesActive) { // v_cmpx_gt_i32_e64 s3, v2 const uint32_t in_range_words[] = {0xD4C4007EU, 0x02020403U}; - std::unique_ptr in_range(decoder->decode(in_range_words)); + std::unique_ptr in_range(decode_valid(*decoder, in_range_words)); ASSERT_NE(in_range, nullptr); ASSERT_EQ(std::string_view(in_range->mnemonic()), "v_cmpx_gt_i32"); cu->execute_instruction(in_range.get(), *wf); @@ -1512,7 +1504,7 @@ TEST(Gfx1250ExecMaskTest, Vop3CmpF32PreservesHighMaskSgprOnWave32) { // v_cmp_eq_f32_e64 s0, 0, v4 const uint32_t compare_words[] = {0xD4120000U, 0x02020880U}; - std::unique_ptr compare(decoder->decode(compare_words)); + std::unique_ptr compare(decode_valid(*decoder, compare_words)); ASSERT_NE(compare, nullptr); ASSERT_EQ(std::string_view(compare->mnemonic()), "v_cmp_eq_f32"); cu->execute_instruction(compare.get(), *wf); @@ -1554,7 +1546,7 @@ TEST(Gfx1250True16Vop3Test, SelectedHalfArithmeticPreservesDestinationHalf) { } auto execute = [&](const uint32_t(&words)[2], std::string_view mnemonic) { - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); cu->execute_instruction(inst.get(), *wf); @@ -1626,7 +1618,7 @@ TEST(Gfx1250True16Vop2Test, AddF16UsesSelectedHighVsrc1AndPreservesLowDestinatio // v_add_f16_e32 v2.h, v0.h, v1.h const uint32_t words[] = {0x65050380U, 0x00000000U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_add_f16_e32"); EXPECT_NE(inst->disassemble().find("v2.h"), std::string::npos); @@ -1668,7 +1660,7 @@ TEST(Gfx1250True16Vop2Test, FmacF16HighDestinationUsesSelectedAccumulatorHalf) { // v_fmac_f16_e32 v0.h, v1.h, v2.h const uint32_t words[] = {0x6D010581U, 0x00000000U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_fmac_f16_e32"); EXPECT_NE(inst->disassemble().find("v0.h"), std::string::npos); @@ -1709,7 +1701,7 @@ TEST(Gfx1250True16Vop3Test, MulLoU16UsesSelectedHighSourceHalf) { // v_mul_lo_u16 v2.l, 0x12b3, v0.h op_sel:[0,1,0] const uint32_t words[] = {0xD7051002U, 0x020200FFU, 0x000012B3U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_mul_lo_u16"); cu->execute_instruction(inst.get(), *wf); @@ -1750,7 +1742,7 @@ TEST(Gfx1250True16Vop3Test, CmpLtI16UsesSelectedHighSourceHalf) { // v_cmp_lt_i16 s0, -1, v0.h op_sel:[0,1,0] const uint32_t words[] = {0xD4311000U, 0x020200C1U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_lt_i16"); cu->execute_instruction(inst.get(), *wf); @@ -1797,7 +1789,7 @@ TEST(Gfx1250True16Vop3Test, CmpClassF16UsesSelectedMaskHalf) { constexpr auto words = encode_vop3(/*op=*/125, /*vdst=*/0, /*src0=*/256, /*src1=*/256, /*src2=*/0, /*abs=*/0, /*opsel=*/0x2); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_class_f16"); cu->execute_instruction(inst.get(), *wf); @@ -1843,7 +1835,7 @@ TEST(Gfx1250True16Vop3Test, CmpxClassF16UsesSelectedMaskHalf) { constexpr auto words = encode_vop3(/*op=*/253, /*vdst=*/126, /*src0=*/256, /*src1=*/256, /*src2=*/0, /*abs=*/0, /*opsel=*/0x2); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmpx_class_f16"); cu->execute_instruction(inst.get(), *wf); @@ -1884,7 +1876,7 @@ TEST(Gfx1250True16Vop3Test, SpecialVop3OpsUseSelectedHalves) { const uint32_t vb = wf->vgpr_alloc().base; auto execute = [&](const std::array &words, std::string_view mnemonic) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); cu->execute_instruction(inst.get(), *wf); @@ -1968,7 +1960,7 @@ TEST(Gfx1250True16VopcTest, CmpLtI16ReadsPackedHighVsrc1) { // v_cmp_lt_i16_e32 vcc_lo, -1, v0.h const uint32_t words[] = {0x7C6300C1U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_lt_i16_e32"); cu->execute_instruction(inst.get(), *wf); @@ -2014,7 +2006,7 @@ TEST(Rdna4True16Vop3Test, CmpGeF16UsesSelectedHighSourceHalf) { // v_cmp_ge_f16_e64 s0, |v0.h|, 0.5 op_sel:[1,0,0] const uint32_t words[] = {0xD4060900U, 0x0201E100U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_ge_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2062,7 +2054,7 @@ TEST(Rdna4True16Vop3Test, CmpClassF16UsesSelectedMaskHalf) { constexpr auto words = encode_vop3(/*op=*/125, /*vdst=*/0, /*src0=*/256, /*src1=*/256, /*src2=*/0, /*abs=*/0, /*opsel=*/0x2); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_class_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2109,7 +2101,7 @@ TEST(Rdna4True16Vop3Test, CmpClassF16InlineConstantUsesF16Broadcast) { constexpr auto words = encode_vop3(/*op=*/125, /*vdst=*/0, /*src0=*/242, /*src1=*/4, /*src2=*/0, /*abs=*/0, /*opsel=*/0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_class_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2155,7 +2147,7 @@ TEST(Rdna4True16Vop3Test, CmpxClassF16UsesSelectedMaskHalf) { constexpr auto words = encode_vop3(/*op=*/253, /*vdst=*/126, /*src0=*/256, /*src1=*/256, /*src2=*/0, /*abs=*/0, /*opsel=*/0x2); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmpx_class_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2224,13 +2216,13 @@ TEST(Rdna4True16Vop3Test, ClassF16HelperSequenceMovesMaskIntoSelectedHighHalf) { const uint32_t mov_words[] = {0x7F003901U, 0}; const uint32_t cmp_words[] = {0xD47D1000U, 0x02020100U}; const uint32_t select_words[] = {0xD5010000U, 0x00010280U}; - std::unique_ptr mov(decoder->decode(mov_words)); + std::unique_ptr mov(decode_valid(*decoder, mov_words)); ASSERT_NE(mov, nullptr); ASSERT_EQ(std::string_view(mov->mnemonic()), "v_mov_b16_e32"); - std::unique_ptr cmp(decoder->decode(cmp_words)); + std::unique_ptr cmp(decode_valid(*decoder, cmp_words)); ASSERT_NE(cmp, nullptr); ASSERT_EQ(std::string_view(cmp->mnemonic()), "v_cmp_class_f16"); - std::unique_ptr select(decoder->decode(select_words)); + std::unique_ptr select(decode_valid(*decoder, select_words)); ASSERT_NE(select, nullptr); ASSERT_EQ(std::string_view(select->mnemonic()), "v_cndmask_b32"); @@ -2297,7 +2289,7 @@ TEST(Rdna4True16Vop3Test, RcpF16WritesSelectedHighDestinationHalf) { // v_rcp_f16_e64 v0.h, -v0.l op_sel:[0,1] const uint32_t words[] = {0xD5D44000U, 0x22010100U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_rcp_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2339,7 +2331,7 @@ TEST(Rdna4True16Vop3Test, CvtF32F16AppliesAbsToSelectedSourceHalf) { // v_cvt_f32_f16_e64 v4, |v2.l| const uint32_t words[] = {0xD58B0104U, 0x02010102U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_f32_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2389,7 +2381,7 @@ TEST(Rdna4True16Vop3Test, AddF16UsesSelectedHalvesAndPreservesDestinationHalf) { constexpr auto words = encode_vop3(/*op=*/0x132, /*vdst=*/2, /*src0=*/256, /*src1=*/257, /*src2=*/0, /*abs=*/0, /*opsel=*/0xB); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_add_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2524,7 +2516,8 @@ TEST(Rdna4True16Vop3Test, UnaryDpp16ScalarAndSimdMatchMaskedLaneRouting) { static_assert(sizeof(raw) == 3 * sizeof(uint32_t)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); - std::unique_ptr inst(decoder->decode(reinterpret_cast(&raw))); + std::unique_ptr inst( + decode_valid(*decoder, reinterpret_cast(&raw))); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_rcp_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2612,7 +2605,8 @@ TEST(Rdna4True16Vop3Test, VopcDpp16ScalarAndSimdMatchMaskedLaneRouting) { static_assert(sizeof(raw) == 3 * sizeof(uint32_t)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); - std::unique_ptr inst(decoder->decode(reinterpret_cast(&raw))); + std::unique_ptr inst( + decode_valid(*decoder, reinterpret_cast(&raw))); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cmp_ge_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2699,7 +2693,8 @@ TEST(Rdna4True16Vop3Test, UnaryDpp8ScalarAndSimdMatchPermutedLanes) { static_assert(sizeof(raw) == 3 * sizeof(uint32_t)); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); - std::unique_ptr inst(decoder->decode(reinterpret_cast(&raw))); + std::unique_ptr inst( + decode_valid(*decoder, reinterpret_cast(&raw))); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_rcp_f16_e64_dpp"); EXPECT_EQ(inst->disassemble(), "v_rcp_f16_e64_dpp v2, v0 dpp8:[7,0,5,2,3,6,1,4] fi:1"); @@ -2761,7 +2756,7 @@ TEST(Rdna4True16Vop3Test, FmacF16UsesSelectedAccumulatorHalfAndPreservesDestinat constexpr auto words = encode_vop3(/*op=*/0x136, /*vdst=*/3, /*src0=*/256, /*src1=*/257, /*src2=*/0, /*abs=*/0, /*opsel=*/0xB); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_fmac_f16"); cu->execute_instruction(inst.get(), *wf); @@ -2813,7 +2808,7 @@ TEST(Rdna4True16Vop3Test, TernaryI16U16UsesSelectedHalvesAndPreservesDestination std::string_view mnemonic, uint16_t expected_high) { cu->write_vgpr(vb + dst, 0, pack16(static_cast(0xA000u | dst), 0xCAFEu)); const auto words = encode_vop3(op, dst, src0, src1, src2, /*abs=*/0, /*opsel=*/0xF); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); cu->execute_instruction(inst.get(), *wf); @@ -2864,7 +2859,7 @@ TEST(Rdna4True16Vop3Test, SpecialVop3OpsUseSelectedHalves) { const uint32_t vb = wf->vgpr_alloc().base; auto execute = [&](const std::array &words, std::string_view mnemonic) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); cu->execute_instruction(inst.get(), *wf); @@ -2957,7 +2952,7 @@ TEST(Rdna4Vop3CndmaskTest, B32AppliesNegModifierBeforeSelect) { // v_cndmask_b32 v2, -v0, v1, s[0:1] const uint32_t words[] = {0xD5010002U, 0x20020300U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cndmask_b32"); cu->execute_instruction(inst.get(), *wf); @@ -3003,7 +2998,7 @@ TEST(Rdna4Atan2F16Test, SignedHalfCompareFeedsQuadrantSelect) { // v_cmp_gt_i16_e32 vcc_lo, 0, v2.l const uint32_t i16_cmp_words[] = {0x7C680480U, 0}; - std::unique_ptr i16_cmp(decoder->decode(i16_cmp_words)); + std::unique_ptr i16_cmp(decode_valid(*decoder, i16_cmp_words)); ASSERT_NE(i16_cmp, nullptr); ASSERT_EQ(std::string_view(i16_cmp->mnemonic()), "v_cmp_gt_i16_e32"); cu->execute_instruction(i16_cmp.get(), *wf); @@ -3011,7 +3006,7 @@ TEST(Rdna4Atan2F16Test, SignedHalfCompareFeedsQuadrantSelect) { // v_cndmask_b32_e64 v6, 0, 0x40490fdb, vcc_lo const uint32_t pi_select_words[] = {0xD5010006U, 0x01A9FE80U, 0x40490FDBU}; - std::unique_ptr pi_select(decoder->decode(pi_select_words)); + std::unique_ptr pi_select(decode_valid(*decoder, pi_select_words)); ASSERT_NE(pi_select, nullptr); ASSERT_EQ(std::string_view(pi_select->mnemonic()), "v_cndmask_b32"); cu->execute_instruction(pi_select.get(), *wf); @@ -3020,7 +3015,7 @@ TEST(Rdna4Atan2F16Test, SignedHalfCompareFeedsQuadrantSelect) { // v_cmp_gt_f16_e32 vcc_lo, 0, v2.l const uint32_t f16_cmp_words[] = {0x7C080480U, 0}; - std::unique_ptr f16_cmp(decoder->decode(f16_cmp_words)); + std::unique_ptr f16_cmp(decode_valid(*decoder, f16_cmp_words)); ASSERT_NE(f16_cmp, nullptr); ASSERT_EQ(std::string_view(f16_cmp->mnemonic()), "v_cmp_gt_f16_e32"); cu->execute_instruction(f16_cmp.get(), *wf); @@ -3062,7 +3057,7 @@ TEST(Rdna4Atan2F16Test, DualCndmaskReadsOldPairedSlotSource) { // v_dual_cndmask_b32 v4, v4, v5 :: v_dual_mov_b32 v5, 0x4016cbe4 const uint32_t words[] = {0xCA500B04U, 0x040400FFU, 0x4016CBE4U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_dual_cndmask_b32 :: v_dual_mov_b32"); cu->execute_instruction(inst.get(), *wf); @@ -3125,7 +3120,7 @@ TEST(Rdna4Atan2F16Test, TailSequenceKeepsNegativeXQuadrant) { }}; for (const auto &words : program) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); cu->execute_instruction(inst.get(), *wf); } @@ -3169,7 +3164,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mix_f32 v0, |v3|, s0, neg(0) op_sel_hi:[1,0,0] const uint32_t abs_src0_words[] = {0xCC200100U, 0x8A000103U}; - std::unique_ptr abs_src0_inst(decoder->decode(abs_src0_words)); + std::unique_ptr abs_src0_inst(decode_valid(*decoder, abs_src0_words)); ASSERT_NE(abs_src0_inst, nullptr); ASSERT_EQ(std::string_view(abs_src0_inst->mnemonic()), "v_fma_mix_f32"); cu->execute_instruction(abs_src0_inst.get(), *wf); @@ -3182,7 +3177,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mix_f32 v0, v4, s0, |v3| op_sel_hi:[0,0,1] const uint32_t abs_src2_words[] = {0xCC204400U, 0x040C0104U}; - std::unique_ptr abs_src2_inst(decoder->decode(abs_src2_words)); + std::unique_ptr abs_src2_inst(decode_valid(*decoder, abs_src2_words)); ASSERT_NE(abs_src2_inst, nullptr); ASSERT_EQ(std::string_view(abs_src2_inst->mnemonic()), "v_fma_mix_f32"); cu->execute_instruction(abs_src2_inst.get(), *wf); @@ -3193,7 +3188,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mix_f32 v0, v2, 1.0, v0 op_sel_hi:[1,1,0] const uint32_t inline_one_f32_words[] = {0xCC200000U, 0x1C01E502U}; - std::unique_ptr inline_one_f32_inst(decoder->decode(inline_one_f32_words)); + std::unique_ptr inline_one_f32_inst(decode_valid(*decoder, inline_one_f32_words)); ASSERT_NE(inline_one_f32_inst, nullptr); ASSERT_EQ(std::string_view(inline_one_f32_inst->mnemonic()), "v_fma_mix_f32"); cu->execute_instruction(inline_one_f32_inst.get(), *wf); @@ -3204,7 +3199,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mixlo_f16 v0, v2, 1.0, 0 op_sel_hi:[1,1,0] const uint32_t inline_one_f16_words[] = {0xCC210000U, 0x1A01E502U}; - std::unique_ptr inline_one_f16_inst(decoder->decode(inline_one_f16_words)); + std::unique_ptr inline_one_f16_inst(decode_valid(*decoder, inline_one_f16_words)); ASSERT_NE(inline_one_f16_inst, nullptr); ASSERT_EQ(std::string_view(inline_one_f16_inst->mnemonic()), "v_fma_mixlo_f16"); cu->execute_instruction(inline_one_f16_inst.get(), *wf); @@ -3216,7 +3211,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mix_f32 v0, |v2|, -1.0, s0 op_sel_hi:[1,1,0] const uint32_t atanh_den_words[] = {0xCC200100U, 0x1801E702U}; - std::unique_ptr atanh_den_inst(decoder->decode(atanh_den_words)); + std::unique_ptr atanh_den_inst(decode_valid(*decoder, atanh_den_words)); ASSERT_NE(atanh_den_inst, nullptr); ASSERT_EQ(std::string_view(atanh_den_inst->mnemonic()), "v_fma_mix_f32"); cu->execute_instruction(atanh_den_inst.get(), *wf); @@ -3226,7 +3221,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mix_f32 v3, |v2|, 1.0, s0 op_sel_hi:[1,1,0] const uint32_t atanh_num_words[] = {0xCC200103U, 0x1801E502U}; - std::unique_ptr atanh_num_inst(decoder->decode(atanh_num_words)); + std::unique_ptr atanh_num_inst(decode_valid(*decoder, atanh_num_words)); ASSERT_NE(atanh_num_inst, nullptr); ASSERT_EQ(std::string_view(atanh_num_inst->mnemonic()), "v_fma_mix_f32"); cu->execute_instruction(atanh_num_inst.get(), *wf); @@ -3238,7 +3233,7 @@ TEST(Rdna4Vop3pFmaMixTest, F32AppliesAbsModifiersFromNegHi) { // v_fma_mixhi_f16 v0, v3, s0, 0 const uint32_t atanh_scale_words[] = {0xCC220000U, 0x02000103U}; - std::unique_ptr atanh_scale_inst(decoder->decode(atanh_scale_words)); + std::unique_ptr atanh_scale_inst(decode_valid(*decoder, atanh_scale_words)); ASSERT_NE(atanh_scale_inst, nullptr); ASSERT_EQ(std::string_view(atanh_scale_inst->mnemonic()), "v_fma_mixhi_f16"); cu->execute_instruction(atanh_scale_inst.get(), *wf); @@ -3281,7 +3276,7 @@ TEST(Rdna4True16Vop3Test, B16BitwiseLiteralPreservesInputSignBit) { // v_and_b16 v1.l, 0x8000, v3.l const uint32_t and_words[] = {0xD7620001U, 0x020206FFU, 0xFFFF8000U}; - std::unique_ptr and_inst(decoder->decode(and_words)); + std::unique_ptr and_inst(decode_valid(*decoder, and_words)); ASSERT_NE(and_inst, nullptr); ASSERT_EQ(std::string_view(and_inst->mnemonic()), "v_and_b16"); ASSERT_NE(and_inst->src_operand(0), nullptr); @@ -3296,7 +3291,7 @@ TEST(Rdna4True16Vop3Test, B16BitwiseLiteralPreservesInputSignBit) { // v_and_b16 v1.l, 0x8000, v3.l op_sel:[1,0,0] const uint32_t and_high_words[] = {0xD7620801U, 0x020206FFU, 0x80000000U}; - std::unique_ptr and_high_inst(decoder->decode(and_high_words)); + std::unique_ptr and_high_inst(decode_valid(*decoder, and_high_words)); ASSERT_NE(and_high_inst, nullptr); ASSERT_EQ(std::string_view(and_high_inst->mnemonic()), "v_and_b16"); ASSERT_NE(and_high_inst->src_operand(0), nullptr); @@ -3311,7 +3306,7 @@ TEST(Rdna4True16Vop3Test, B16BitwiseLiteralPreservesInputSignBit) { // v_and_b16 v1.l, v3.l, 0x8000 op_sel:[0,1,0] const uint32_t and_src1_high_words[] = {0xD7621001U, 0x0201FF03U, 0x80000000U}; - std::unique_ptr and_src1_high_inst(decoder->decode(and_src1_high_words)); + std::unique_ptr and_src1_high_inst(decode_valid(*decoder, and_src1_high_words)); ASSERT_NE(and_src1_high_inst, nullptr); ASSERT_EQ(std::string_view(and_src1_high_inst->mnemonic()), "v_and_b16"); ASSERT_NE(and_src1_high_inst->src_operand(1), nullptr); @@ -3325,7 +3320,7 @@ TEST(Rdna4True16Vop3Test, B16BitwiseLiteralPreservesInputSignBit) { // v_xor_b16 v0.l, v1.l, v0.l const uint32_t xor_words[] = {0xD7640000U, 0x02020101U}; - std::unique_ptr xor_inst(decoder->decode(xor_words)); + std::unique_ptr xor_inst(decode_valid(*decoder, xor_words)); ASSERT_NE(xor_inst, nullptr); ASSERT_EQ(std::string_view(xor_inst->mnemonic()), "v_xor_b16"); cu->execute_instruction(xor_inst.get(), *wf); @@ -3370,7 +3365,7 @@ TEST(Gfx1250True16Vop3Test, CndmaskB16UsesSelectedSourceHalfAndPreservesDestinat // v_cndmask_b16 v2.h, v0.l, v1.h, s[0:1] op_sel:[0,1,0,1] const uint32_t words[] = {0xD65D5002U, 0x00020300U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cndmask_b16"); cu->execute_instruction(inst.get(), *wf); @@ -3410,7 +3405,7 @@ TEST(Gfx1250True16Vop3Test, LshrrevB16UsesSelectedSourceHalfAndPreservesDestinat // v_lshrrev_b16 v16.h, 8, v17.l op_sel:[0,0,1] const uint32_t words[] = {0xD7394010U, 0x02022288U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_lshrrev_b16"); cu->execute_instruction(inst.get(), *wf); @@ -3453,7 +3448,7 @@ TEST(Gfx1250True16Vop3Test, Bitop3B16UsesSelectedSourceHalfAndPreservesDestinati } auto execute = [&](const uint32_t(&words)[2], std::string_view mnemonic) { - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); cu->execute_instruction(inst.get(), *wf); @@ -3512,7 +3507,7 @@ TEST(Gfx1250True16Vop1Test, MovB16HighDestinationPreservesLowHalf) { // v_mov_b16_e32 v2.h, v0.l const uint32_t words[] = {0x7F043900U, 0x00000000U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_mov_b16_e32"); EXPECT_NE(inst->disassemble().find("v2.h"), std::string::npos); @@ -3551,7 +3546,7 @@ TEST(Rdna3True16Vop1Test, MovB16HighDestinationPreservesLowHalf) { // v_mov_b16_e32 v2.h, v0.l const uint32_t words[] = {0x7F043900U, 0x00000000U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_mov_b16_e32"); EXPECT_NE(inst->disassemble().find("v2.h"), std::string::npos); @@ -3603,7 +3598,7 @@ TEST(Rdna3DppTest, VAddF32RowShrMatchesWaveReduceSequence) { cu->write_vgpr(vb + 3, lane, std::bit_cast(input[lane])); for (const auto &words : dpp_adds) { - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_add_f32_e32"); cu->execute_instruction(inst.get(), *wf); @@ -3613,14 +3608,14 @@ TEST(Rdna3DppTest, VAddF32RowShrMatchesWaveReduceSequence) { EXPECT_EQ(cu->read_vgpr(vb + 3, 31), std::bit_cast(2.0f)); const uint32_t swizzle_words[] = {0xD8D401E0U, 0x04000003U}; - std::unique_ptr swizzle_inst(decoder->decode(swizzle_words)); + std::unique_ptr swizzle_inst(decode_valid(*decoder, swizzle_words)); ASSERT_NE(swizzle_inst, nullptr); ASSERT_EQ(std::string_view(swizzle_inst->mnemonic()), "ds_swizzle_b32"); cu->execute_instruction(swizzle_inst.get(), *wf); EXPECT_EQ(cu->read_vgpr(vb + 4, 31), std::bit_cast(-4.0f)); const uint32_t final_add_words[] = {0xD5030003U, 0x02020903U}; - std::unique_ptr final_add_inst(decoder->decode(final_add_words)); + std::unique_ptr final_add_inst(decode_valid(*decoder, final_add_words)); ASSERT_NE(final_add_inst, nullptr); ASSERT_EQ(std::string_view(final_add_inst->mnemonic()), "v_add_f32"); cu->execute_instruction(final_add_inst.get(), *wf); @@ -3663,7 +3658,7 @@ TEST(Rdna3ScalarOperandTest, NullSdstDoesNotClobberM0) { // v_add_co_ci_u32_e64 v5, null, 0, 0, s9 const uint32_t words[] = {0xD5207C05U, 0x00250080U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_add_co_ci_u32"); EXPECT_NE(inst->disassemble().find("null"), std::string::npos); @@ -3705,7 +3700,7 @@ TEST(Gfx1250True16Vop1Test, CvtF16F32HighDestinationPreservesLowHalf) { // v_cvt_f16_f32_e32 v0.h, v2 const uint32_t words[] = {0x7F001502U, 0x00000000U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_f16_f32_e32"); EXPECT_NE(inst->disassemble().find("v0.h"), std::string::npos); @@ -3744,7 +3739,7 @@ TEST(Gfx1250CvtFp8Test, F16DecodeVop3UsesSelectedByte) { // v_cvt_f16_fp8 v1.l, v0 byte_sel:2 const uint32_t fp8_words[] = {0xD5F70801U, 0x00000100U}; - std::unique_ptr fp8_inst(decoder->decode(fp8_words)); + std::unique_ptr fp8_inst(decode_valid(*decoder, fp8_words)); ASSERT_NE(fp8_inst, nullptr); ASSERT_EQ(std::string_view(fp8_inst->mnemonic()), "v_cvt_f16_fp8"); cu->execute_instruction(fp8_inst.get(), *wf); @@ -3755,7 +3750,7 @@ TEST(Gfx1250CvtFp8Test, F16DecodeVop3UsesSelectedByte) { // v_cvt_f16_bf8 v1.l, v0 byte_sel:3 const uint32_t bf8_words[] = {0xD5F81801U, 0x00000100U}; - std::unique_ptr bf8_inst(decoder->decode(bf8_words)); + std::unique_ptr bf8_inst(decode_valid(*decoder, bf8_words)); ASSERT_NE(bf8_inst, nullptr); ASSERT_EQ(std::string_view(bf8_inst->mnemonic()), "v_cvt_f16_bf8"); cu->execute_instruction(bf8_inst.get(), *wf); @@ -3792,7 +3787,7 @@ TEST(Gfx1250CvtFp8Test, F16E5M3OverflowHonorsFp16OvflMode) { // v_cvt_f16_fp8 v1.l, v0 byte_sel:2 clamp. On gfx1250, clamp selects the // unsigned E5M3 FP8 decode; 0xFE is finite but overflows FP16. const uint32_t fp8_words[] = {0xD5F78801U, 0x00000100U}; - std::unique_ptr fp8_inst(decoder->decode(fp8_words)); + std::unique_ptr fp8_inst(decode_valid(*decoder, fp8_words)); ASSERT_NE(fp8_inst, nullptr); ASSERT_EQ(std::string_view(fp8_inst->mnemonic()), "v_cvt_f16_fp8"); @@ -3808,7 +3803,7 @@ TEST(Gfx1250CvtFp8Test, F16E5M3OverflowHonorsFp16OvflMode) { // Same conversion with OPSEL[3]=1 writes the high destination half. const uint32_t fp8_high_words[] = {0xD5F7C801U, 0x00000100U}; - std::unique_ptr fp8_high_inst(decoder->decode(fp8_high_words)); + std::unique_ptr fp8_high_inst(decode_valid(*decoder, fp8_high_words)); ASSERT_NE(fp8_high_inst, nullptr); ASSERT_EQ(std::string_view(fp8_high_inst->mnemonic()), "v_cvt_f16_fp8"); cu->write_vgpr(vb + 1, 0, 0x5555BEEFu); @@ -3845,7 +3840,7 @@ TEST(Gfx1250CvtFp8Test, F32DecodeVop3UsesSelectedByte) { // v_cvt_f32_fp8 v1, v0 byte_sel:2 const uint32_t fp8_words[] = {0xD5EC0801U, 0x00000100U}; - std::unique_ptr fp8_inst(decoder->decode(fp8_words)); + std::unique_ptr fp8_inst(decode_valid(*decoder, fp8_words)); ASSERT_NE(fp8_inst, nullptr); ASSERT_EQ(std::string_view(fp8_inst->mnemonic()), "v_cvt_f32_fp8"); cu->execute_instruction(fp8_inst.get(), *wf); @@ -3855,7 +3850,7 @@ TEST(Gfx1250CvtFp8Test, F32DecodeVop3UsesSelectedByte) { // v_cvt_f32_bf8 v1, v0 byte_sel:3 const uint32_t bf8_words[] = {0xD5ED1801U, 0x00000100U}; - std::unique_ptr bf8_inst(decoder->decode(bf8_words)); + std::unique_ptr bf8_inst(decode_valid(*decoder, bf8_words)); ASSERT_NE(bf8_inst, nullptr); ASSERT_EQ(std::string_view(bf8_inst->mnemonic()), "v_cvt_f32_bf8"); cu->execute_instruction(bf8_inst.get(), *wf); @@ -3893,7 +3888,7 @@ TEST(Gfx1250CvtFp8Test, E4M3OverflowHonorsFp16OvflMode) { // v_cvt_pk_fp8_f32 v2.l, v5, v6 const auto words = encode_vop3(cdna5::kVCvtPkFp8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_pk_fp8_f32"); cu->execute_instruction(inst.get(), *wf); @@ -3936,7 +3931,7 @@ TEST(Gfx1250CvtFp8Test, Bf8OverflowHonorsFp16OvflMode) { // v_cvt_pk_bf8_f32 v2.l, v5, v6 const auto words = encode_vop3(cdna5::kVCvtPkBf8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_pk_bf8_f32"); cu->execute_instruction(inst.get(), *wf); @@ -3970,7 +3965,7 @@ TEST(Gfx1250CvtF16Test, SrPackedF16ConsumesAdvancedSeedAndFp16OvflMode) { const auto words = encode_vop3(cdna5::kVCvtSrPkF16F32Vop3, 2, vgpr_src(5), vgpr_src(6), vgpr_src(7)); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_sr_pk_f16_f32"); @@ -4034,7 +4029,7 @@ TEST(Rdna4CvtFp8Test, E4M3OverflowHonorsFp16OvflMode) { // v_cvt_pk_fp8_f32 v2.l, v5, v6 const auto words = encode_vop3(rdna4::kVCvtPkFp8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_pk_fp8_f32"); cu->execute_instruction(inst.get(), *wf); @@ -4077,7 +4072,7 @@ TEST(Rdna4CvtFp8Test, Bf8OverflowHonorsFp16OvflMode) { // v_cvt_pk_bf8_f32 v2.l, v5, v6 const auto packed_words = encode_vop3(rdna4::kVCvtPkBf8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr packed_inst(decoder->decode(packed_words.data())); + std::unique_ptr packed_inst(decode_valid(*decoder, packed_words.data())); ASSERT_NE(packed_inst, nullptr); ASSERT_EQ(std::string_view(packed_inst->mnemonic()), "v_cvt_pk_bf8_f32"); @@ -4095,7 +4090,7 @@ TEST(Rdna4CvtFp8Test, Bf8OverflowHonorsFp16OvflMode) { // v_cvt_sr_bf8_f32 v2, v5, v6 byte_sel:0 const auto sr_words = encode_vop3(rdna4::kVCvtSrBf8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr sr_inst(decoder->decode(sr_words.data())); + std::unique_ptr sr_inst(decode_valid(*decoder, sr_words.data())); ASSERT_NE(sr_inst, nullptr); ASSERT_EQ(std::string_view(sr_inst->mnemonic()), "v_cvt_sr_bf8_f32"); @@ -4139,7 +4134,7 @@ TEST(Rdna4CvtF16Test, F32OverflowHonorsFp16OvflMode) { // v_cvt_f16_f32 v2.l, v5 const auto words = encode_vop3(rdna4::kVCvtF16F32Vop3, 2, vgpr_src(5), 0, 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_f16_f32"); cu->execute_instruction(inst.get(), *wf); @@ -4186,7 +4181,7 @@ TEST(Rdna4CvtF16Test, U16OverflowHonorsFp16OvflModeInScalarAndSimdPaths) { // v_cvt_f16_u16 v2.l, v5 const auto words = encode_vop3(rdna4::kVCvtF16U16Vop3, 2, vgpr_src(5), 0, 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_f16_u16"); cu->execute_instruction(inst.get(), *wf); @@ -4234,7 +4229,7 @@ TEST(Rdna4Fp16ValuTest, AddOverflowHonorsFp16OvflModeInScalarAndSimdPaths) { cu->write_vgpr(vb + 2, 0, 0xA5A5BEEFu); const auto words = encode_vop3(rdna4::kVAddF16Vop3, 2, vgpr_src(0), vgpr_src(1), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_add_f16"); cu->execute_instruction(inst.get(), *wf); @@ -4268,25 +4263,25 @@ TEST(Cdna4CvtSrTest, SingleResultF16Bf16ConsumesSeedAndFp16OvflMode) { ASSERT_NE(decoder, nullptr); const auto f16_words = encode_cdna_vop3(cdna4::kVCvtSrF16F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr f16_inst(decoder->decode(f16_words.data())); + std::unique_ptr f16_inst(decode_valid(*decoder, f16_words.data())); ASSERT_NE(f16_inst, nullptr); ASSERT_EQ(std::string_view(f16_inst->mnemonic()), "v_cvt_sr_f16_f32"); const auto f16_hi_words = encode_cdna_vop3(cdna4::kVCvtSrF16F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0, 0x8); - std::unique_ptr f16_hi_inst(decoder->decode(f16_hi_words.data())); + std::unique_ptr f16_hi_inst(decode_valid(*decoder, f16_hi_words.data())); ASSERT_NE(f16_hi_inst, nullptr); ASSERT_EQ(std::string_view(f16_hi_inst->mnemonic()), "v_cvt_sr_f16_f32"); const auto bf16_words = encode_cdna_vop3(cdna4::kVCvtSrBf16F32Vop3, 3, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr bf16_inst(decoder->decode(bf16_words.data())); + std::unique_ptr bf16_inst(decode_valid(*decoder, bf16_words.data())); ASSERT_NE(bf16_inst, nullptr); ASSERT_EQ(std::string_view(bf16_inst->mnemonic()), "v_cvt_sr_bf16_f32"); const auto bf16_hi_words = encode_cdna_vop3(cdna4::kVCvtSrBf16F32Vop3, 3, vgpr_src(5), vgpr_src(6), 0, 0x8); - std::unique_ptr bf16_hi_inst(decoder->decode(bf16_hi_words.data())); + std::unique_ptr bf16_hi_inst(decode_valid(*decoder, bf16_hi_words.data())); ASSERT_NE(bf16_hi_inst, nullptr); ASSERT_EQ(std::string_view(bf16_hi_inst->mnemonic()), "v_cvt_sr_bf16_f32"); @@ -4401,7 +4396,7 @@ TEST(Cdna4CvtPkTest, F16Bf16F32OverflowHonorsFp16OvflMode) { // v_cvt_pk_f16_f32 v2, v5, v6 const auto f16_words = encode_cdna_vop3(cdna4::kVCvtPkF16F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr f16_inst(decoder->decode(f16_words.data())); + std::unique_ptr f16_inst(decode_valid(*decoder, f16_words.data())); ASSERT_NE(f16_inst, nullptr); ASSERT_EQ(std::string_view(f16_inst->mnemonic()), "v_cvt_pk_f16_f32"); @@ -4419,7 +4414,7 @@ TEST(Cdna4CvtPkTest, F16Bf16F32OverflowHonorsFp16OvflMode) { // v_cvt_pk_bf16_f32 v2, v5, v6 const auto bf16_words = encode_cdna_vop3(cdna4::kVCvtPkBf16F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr bf16_inst(decoder->decode(bf16_words.data())); + std::unique_ptr bf16_inst(decode_valid(*decoder, bf16_words.data())); ASSERT_NE(bf16_inst, nullptr); ASSERT_EQ(std::string_view(bf16_inst->mnemonic()), "v_cvt_pk_bf16_f32"); @@ -4482,13 +4477,13 @@ TEST(CdnaLegacyCvtF16Test, SetregImm32ModeControlsOverflowingF32ToF16) { cu->write_vgpr(vb + 5, 0, std::bit_cast(70000.0f)); const auto cvt_words = encode_cdna_vop3(arch_case.cvt_op, 2, vgpr_src(5), 0, 0); - std::unique_ptr cvt_inst(decoder->decode(cvt_words.data())); + std::unique_ptr cvt_inst(decode_valid(*decoder, cvt_words.data())); ASSERT_NE(cvt_inst, nullptr); ASSERT_EQ(std::string_view(cvt_inst->mnemonic()), "v_cvt_f16_f32"); constexpr uint32_t kHwregFp16Ovfl = encode_hwreg(1, 23, 1); const auto setreg_words = encode_sopk(arch_case.setreg_imm_op, 0, kHwregFp16Ovfl, 1); - std::unique_ptr setreg_inst(decoder->decode(setreg_words.data())); + std::unique_ptr setreg_inst(decode_valid(*decoder, setreg_words.data())); ASSERT_NE(setreg_inst, nullptr); ASSERT_EQ(std::string_view(setreg_inst->mnemonic()), "s_setreg_imm32_b32"); @@ -4532,7 +4527,7 @@ TEST(Rdna4ScalarF16Test, AddDoesNotConsumeFp16OvflMode) { cu->write_sgpr(sb + 1, util::f32_to_f16(65504.0f)); const auto words = encode_sop2(rdna4::kSAddF16Sop2, 2, 0, 1); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "s_add_f16"); @@ -4568,7 +4563,7 @@ TEST(Rdna4ScalarF16Test, CvtF16F32ConsumesFp16OvflMode) { cu->write_sgpr(sb + 0, std::bit_cast(70000.0f)); const auto words = encode_sop1(rdna4::kSCvtF16F32Sop1, 2, 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "s_cvt_f16_f32"); @@ -4612,13 +4607,13 @@ TEST(Cdna3CvtFp8Test, SetregImm32ModeChangeRecomputesFp16OvflRounding) { // v_cvt_pk_fp8_f32 v2.l, v5, v6. CDNA3 uses FNUZ FP8 encodings. const auto words = encode_cdna_vop3(cdna3::kVCvtPkFp8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_pk_fp8_f32"); constexpr uint32_t kHwregFp16Ovfl = encode_hwreg(1, 23, 1); const auto setreg_words = encode_sopk(cdna3::kSSetregImm32B32Sopk, 0, kHwregFp16Ovfl, 1); - std::unique_ptr setreg_inst(decoder->decode(setreg_words.data())); + std::unique_ptr setreg_inst(decode_valid(*decoder, setreg_words.data())); ASSERT_NE(setreg_inst, nullptr); ASSERT_EQ(std::string_view(setreg_inst->mnemonic()), "s_setreg_imm32_b32"); @@ -4668,7 +4663,7 @@ TEST(Gfx1250CvtFp8Test, F16SourceFp8Bf8ConversionsIgnoreFp16OvflMode) { auto run_packed_case = [&](uint32_t op, std::string_view mnemonic, uint32_t src, uint32_t expected) { const auto words = encode_vop3(op, 2, vgpr_src(5), 0, 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); @@ -4687,7 +4682,7 @@ TEST(Gfx1250CvtFp8Test, F16SourceFp8Bf8ConversionsIgnoreFp16OvflMode) { auto run_sr_case = [&](uint32_t op, std::string_view mnemonic, uint32_t src, uint32_t seed, uint32_t expected_byte) { const auto words = encode_vop3(op, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); @@ -4742,7 +4737,7 @@ TEST(Cdna3CvtFp8Test, Bf8AndStochasticPathsHonorFp16OvflMode) { // v_cvt_pk_bf8_f32 v2.l, v5, v6 const auto bf8_words = encode_cdna_vop3(cdna3::kVCvtPkBf8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr bf8_inst(decoder->decode(bf8_words.data())); + std::unique_ptr bf8_inst(decode_valid(*decoder, bf8_words.data())); ASSERT_NE(bf8_inst, nullptr); ASSERT_EQ(std::string_view(bf8_inst->mnemonic()), "v_cvt_pk_bf8_f32"); @@ -4762,7 +4757,7 @@ TEST(Cdna3CvtFp8Test, Bf8AndStochasticPathsHonorFp16OvflMode) { // v_cvt_sr_fp8_f32 v2, v5, v6 byte_sel:0 const auto sr_fp8_words = encode_cdna_vop3(cdna3::kVCvtSrFp8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr sr_fp8_inst(decoder->decode(sr_fp8_words.data())); + std::unique_ptr sr_fp8_inst(decode_valid(*decoder, sr_fp8_words.data())); ASSERT_NE(sr_fp8_inst, nullptr); ASSERT_EQ(std::string_view(sr_fp8_inst->mnemonic()), "v_cvt_sr_fp8_f32"); @@ -4782,7 +4777,7 @@ TEST(Cdna3CvtFp8Test, Bf8AndStochasticPathsHonorFp16OvflMode) { // v_cvt_sr_bf8_f32 v2, v5, v6 byte_sel:0 const auto sr_bf8_words = encode_cdna_vop3(cdna3::kVCvtSrBf8F32Vop3, 2, vgpr_src(5), vgpr_src(6), 0); - std::unique_ptr sr_bf8_inst(decoder->decode(sr_bf8_words.data())); + std::unique_ptr sr_bf8_inst(decode_valid(*decoder, sr_bf8_words.data())); ASSERT_NE(sr_bf8_inst, nullptr); ASSERT_EQ(std::string_view(sr_bf8_inst->mnemonic()), "v_cvt_sr_bf8_f32"); @@ -4830,7 +4825,7 @@ TEST(Cdna4CvtScaleTest, ScaledFp8Bf8OverflowHonorsFp16OvflMode) { // v_cvt_scalef32_pk_fp8_f32 v2.l, v5, v6, v7 const auto scaled_fp8_words = encode_cdna_vop3(cdna4::kVCvtScalef32PkFp8F32Vop3, 2, vgpr_src(5), vgpr_src(6), vgpr_src(7)); - std::unique_ptr scaled_fp8_inst(decoder->decode(scaled_fp8_words.data())); + std::unique_ptr scaled_fp8_inst(decode_valid(*decoder, scaled_fp8_words.data())); ASSERT_NE(scaled_fp8_inst, nullptr); ASSERT_EQ(std::string_view(scaled_fp8_inst->mnemonic()), "v_cvt_scalef32_pk_fp8_f32"); @@ -4851,7 +4846,7 @@ TEST(Cdna4CvtScaleTest, ScaledFp8Bf8OverflowHonorsFp16OvflMode) { // v_cvt_scalef32_pk_bf8_f32 v2.l, v5, v6, v7 const auto scaled_bf8_words = encode_cdna_vop3(cdna4::kVCvtScalef32PkBf8F32Vop3, 2, vgpr_src(5), vgpr_src(6), vgpr_src(7)); - std::unique_ptr scaled_bf8_inst(decoder->decode(scaled_bf8_words.data())); + std::unique_ptr scaled_bf8_inst(decode_valid(*decoder, scaled_bf8_words.data())); ASSERT_NE(scaled_bf8_inst, nullptr); ASSERT_EQ(std::string_view(scaled_bf8_inst->mnemonic()), "v_cvt_scalef32_pk_bf8_f32"); @@ -4867,12 +4862,12 @@ TEST(Cdna4CvtScaleTest, ScaledFp8Bf8OverflowHonorsFp16OvflMode) { auto run_scaled_f16_dst_case = [&](uint32_t op, std::string_view mnemonic, uint32_t packed_src, float scale) { const auto low_words = encode_cdna_vop3(op, 2, vgpr_src(5), vgpr_src(7), 0); - std::unique_ptr low_inst(decoder->decode(low_words.data())); + std::unique_ptr low_inst(decode_valid(*decoder, low_words.data())); ASSERT_NE(low_inst, nullptr); ASSERT_EQ(std::string_view(low_inst->mnemonic()), mnemonic); const auto high_words = encode_cdna_vop3(op, 2, vgpr_src(5), vgpr_src(7), 0, 0x8); - std::unique_ptr high_inst(decoder->decode(high_words.data())); + std::unique_ptr high_inst(decode_valid(*decoder, high_words.data())); ASSERT_NE(high_inst, nullptr); ASSERT_EQ(std::string_view(high_inst->mnemonic()), mnemonic); @@ -4902,7 +4897,7 @@ TEST(Cdna4CvtScaleTest, ScaledFp8Bf8OverflowHonorsFp16OvflMode) { auto run_scaled_packed_case = [&](uint32_t op, std::string_view mnemonic, uint32_t packed_src, uint32_t expected_clear, uint32_t expected_set) { const auto words = encode_cdna_vop3(op, 2, vgpr_src(5), vgpr_src(7), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic); @@ -4975,7 +4970,7 @@ TEST(Cdna4CvtScaleTest, WideFp6ToF16ConsumesFp16OvflMode) { // v_cvt_scalef32_pk32_f16_fp6 v[2:17], v[20:25], v30 const auto words = encode_cdna_vop3(cdna4::kVCvtScalef32Pk32F16Fp6Vop3, 2, vgpr_src(20), vgpr_src(30), 0); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "v_cvt_scalef32_pk32_f16_fp6"); @@ -5023,7 +5018,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { // v_cvt_f32_fp8 v1, v0 byte_sel:2 clamp const uint32_t decode_words[] = {0xD5EC8801U, 0x00000100U}; - std::unique_ptr decode_inst(decoder->decode(decode_words)); + std::unique_ptr decode_inst(decode_valid(*decoder, decode_words)); ASSERT_NE(decode_inst, nullptr); ASSERT_EQ(std::string_view(decode_inst->mnemonic()), "v_cvt_f32_fp8"); cu->execute_instruction(decode_inst.get(), *wf); @@ -5035,7 +5030,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { // v_cvt_pk_fp8_f32 v2.l, s5, s6 clamp const uint32_t pack_lo_words[] = {0xD7698002U, 0x02000C05U}; - std::unique_ptr pack_lo_inst(decoder->decode(pack_lo_words)); + std::unique_ptr pack_lo_inst(decode_valid(*decoder, pack_lo_words)); ASSERT_NE(pack_lo_inst, nullptr); ASSERT_EQ(std::string_view(pack_lo_inst->mnemonic()), "v_cvt_pk_fp8_f32"); cu->execute_instruction(pack_lo_inst.get(), *wf); @@ -5045,7 +5040,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { // v_cvt_pk_fp8_f32 v2.h, s5, s6 op_sel:[0,0,1] clamp const uint32_t pack_hi_words[] = {0xD769C002U, 0x02000C05U}; - std::unique_ptr pack_hi_inst(decoder->decode(pack_hi_words)); + std::unique_ptr pack_hi_inst(decode_valid(*decoder, pack_hi_words)); ASSERT_NE(pack_hi_inst, nullptr); ASSERT_EQ(std::string_view(pack_hi_inst->mnemonic()), "v_cvt_pk_fp8_f32"); cu->execute_instruction(pack_hi_inst.get(), *wf); @@ -5055,7 +5050,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { // v_cvt_sr_fp8_f32 v2, s5, s6 byte_sel:2 clamp const uint32_t sr_words[] = {0xD76BC002U, 0x02000C05U}; - std::unique_ptr sr_inst(decoder->decode(sr_words)); + std::unique_ptr sr_inst(decode_valid(*decoder, sr_words)); ASSERT_NE(sr_inst, nullptr); ASSERT_EQ(std::string_view(sr_inst->mnemonic()), "v_cvt_sr_fp8_f32"); cu->execute_instruction(sr_inst.get(), *wf); @@ -5067,7 +5062,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { // v_cvt_sr_fp8_f16 v2, s5, s6 byte_sel:2 clamp const uint32_t sr_f16_words[] = {0xD774C002U, 0x02000C05U}; - std::unique_ptr sr_f16_inst(decoder->decode(sr_f16_words)); + std::unique_ptr sr_f16_inst(decode_valid(*decoder, sr_f16_words)); ASSERT_NE(sr_f16_inst, nullptr); ASSERT_EQ(std::string_view(sr_f16_inst->mnemonic()), "v_cvt_sr_fp8_f16"); cu->execute_instruction(sr_f16_inst.get(), *wf); @@ -5107,7 +5102,7 @@ TEST(Gfx1250CvtScaleTest, UnpackUsesSelectedE8M0ScaleByte) { // v_cvt_scale_pk8_f32_fp8 v[2:9], v[0:1], v10 scale_sel:2 const uint32_t pk8_words[] = {0xD6AA1002U, 0x02021500U}; - std::unique_ptr pk8_inst(decoder->decode(pk8_words)); + std::unique_ptr pk8_inst(decode_valid(*decoder, pk8_words)); ASSERT_NE(pk8_inst, nullptr); ASSERT_EQ(std::string_view(pk8_inst->mnemonic()), "v_cvt_scale_pk8_f32_fp8"); cu->execute_instruction(pk8_inst.get(), *wf); @@ -5121,7 +5116,7 @@ TEST(Gfx1250CvtScaleTest, UnpackUsesSelectedE8M0ScaleByte) { // v_cvt_scale_pk16_f32_fp6 v[18:33], v[0:2], v10 scale_sel:1 const uint32_t pk16_words[] = {0xD6C90812U, 0x02021500U}; - std::unique_ptr pk16_inst(decoder->decode(pk16_words)); + std::unique_ptr pk16_inst(decode_valid(*decoder, pk16_words)); ASSERT_NE(pk16_inst, nullptr); ASSERT_EQ(std::string_view(pk16_inst->mnemonic()), "v_cvt_scale_pk16_f32_fp6"); cu->execute_instruction(pk16_inst.get(), *wf); @@ -5164,7 +5159,7 @@ TEST(Gfx1250DsSwizzleTest, VdsBroadcastReadsAddrSource) { // ds_swizzle_b32 v2, v1 offset:swizzle(BROADCAST,32,15) // gfx1250 encodes this as VDS, where the sole source VGPR is the addr field. const uint32_t swizzle_words[] = {0xD8D401E0U, 0x02000001U}; - std::unique_ptr swizzle_inst(decoder->decode(swizzle_words)); + std::unique_ptr swizzle_inst(decode_valid(*decoder, swizzle_words)); ASSERT_NE(swizzle_inst, nullptr); ASSERT_EQ(std::string_view(swizzle_inst->mnemonic()), "ds_swizzle_b32"); cu->execute_instruction(swizzle_inst.get(), *wf); @@ -5177,7 +5172,7 @@ TEST(Gfx1250DsSwizzleTest, VdsBroadcastReadsAddrSource) { // ds_swizzle_b32 v2, v1 offset:0x80b1, QDMode quad permutation (1, 0, 3, 2) const uint32_t quad_perm_words[] = {0xD8D480B1U, 0x02000001U}; - std::unique_ptr quad_perm_inst(decoder->decode(quad_perm_words)); + std::unique_ptr quad_perm_inst(decode_valid(*decoder, quad_perm_words)); ASSERT_NE(quad_perm_inst, nullptr); ASSERT_EQ(std::string_view(quad_perm_inst->mnemonic()), "ds_swizzle_b32"); cu->execute_instruction(quad_perm_inst.get(), *wf); @@ -5223,7 +5218,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddF32ReturnsOldValue) { // global_atomic_add_f32 v0, v2, v1, s[4:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV const uint32_t words[] = {0xEE158004U, 0x00980000U, 0x00000002U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "global_atomic_add_f32"); cu.execute_and_route(inst.release(), *wf); @@ -5266,7 +5261,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddF32AllowsDstSrcAlias) { // global_atomic_add_f32 v1, v2, v1, s[4:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV const uint32_t words[] = {0xEE158004U, 0x00980001U, 0x00000002U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "global_atomic_add_f32"); cu.execute_and_route(inst.release(), *wf); @@ -5310,7 +5305,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddU64CopiesHighSourceDword) { // global_atomic_add_u64 v2, v[0:1], s[4:5] scope:SCOPE_DEV const uint32_t words[] = {0xEE10C004U, 0x00080000U, 0x00000002U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "global_atomic_add_u64"); cu.execute_and_route(inst.release(), *wf); @@ -5353,7 +5348,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicCmpswapB32ReturnsOldValue) { // global_atomic_cmpswap_b32 v0, v2, v[4:5], s[4:5] th:TH_ATOMIC_RETURN scope:SCOPE_DEV const uint32_t words[] = {0xEE0D0004U, 0x02180000U, 0x00000002U}; - std::unique_ptr inst(decoder->decode(words)); + std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), "global_atomic_cmpswap_b32"); cu.execute_and_route(inst.release(), *wf); @@ -5393,13 +5388,13 @@ TEST(HwregTest, GetregReadsModeAndStatusTargetIds) { const std::array unknown_words = encode_sopk(arch_case.getreg_op, 6, kHwregUnknown32); - std::unique_ptr mode_inst(decoder->decode(mode_words.data())); + std::unique_ptr mode_inst(decode_valid(*decoder, mode_words.data())); ASSERT_NE(mode_inst, nullptr); EXPECT_EQ(std::string_view(mode_inst->mnemonic()), "s_getreg_b32"); - std::unique_ptr status_inst(decoder->decode(status_words.data())); + std::unique_ptr status_inst(decode_valid(*decoder, status_words.data())); ASSERT_NE(status_inst, nullptr); EXPECT_EQ(std::string_view(status_inst->mnemonic()), "s_getreg_b32"); - std::unique_ptr unknown_inst(decoder->decode(unknown_words.data())); + std::unique_ptr unknown_inst(decode_valid(*decoder, unknown_words.data())); ASSERT_NE(unknown_inst, nullptr); EXPECT_EQ(std::string_view(unknown_inst->mnemonic()), "s_getreg_b32"); @@ -5836,10 +5831,10 @@ TEST(HwregTest, GetregExtractsPartialModeAndStatusFields) { const std::array status_words = encode_sopk(arch_case.getreg_op, 5, kHwregStatusNibble); - std::unique_ptr mode_inst(decoder->decode(mode_words.data())); + std::unique_ptr mode_inst(decode_valid(*decoder, mode_words.data())); ASSERT_NE(mode_inst, nullptr); EXPECT_EQ(std::string_view(mode_inst->mnemonic()), "s_getreg_b32"); - std::unique_ptr status_inst(decoder->decode(status_words.data())); + std::unique_ptr status_inst(decode_valid(*decoder, status_words.data())); ASSERT_NE(status_inst, nullptr); EXPECT_EQ(std::string_view(status_inst->mnemonic()), "s_getreg_b32"); @@ -5887,7 +5882,7 @@ TEST(HwregTest, SetregImm32StatusIsReadOnly) { const std::array words = encode_sopk(arch_case.setreg_imm_op, 0, kHwregStatus32, kImm32Value); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr) << "Failed to decode s_setreg_imm32_b32"; EXPECT_EQ(std::string_view(inst->mnemonic()).substr(0, 16), "s_setreg_imm32_b"); @@ -5929,7 +5924,7 @@ TEST(HwregTest, SetregImm32WritesModeFp16Ovfl) { const std::array words = encode_sopk(arch_case.setreg_imm_op, 0, kHwregMode32, kImm32Value); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr) << "Failed to decode s_setreg_imm32_b32"; auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5968,7 +5963,7 @@ TEST(HwregTest, SetregB32WritesModeFp16OvflFromSgpr) { constexpr uint32_t kHwregMode32 = encode_hwreg(1); const std::array words = encode_sopk(arch_case.setreg_op, 4, kHwregMode32); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr) << "Failed to decode s_setreg_b32"; EXPECT_EQ(std::string_view(inst->mnemonic()), "s_setreg_b32"); @@ -6014,7 +6009,7 @@ TEST(HwregTest, SetregImm32PartialBitfield) { constexpr uint32_t kImm32 = 0xFFFFFFFF; const std::array words = encode_sopk(arch_case.setreg_imm_op, 0, kHwreg, kImm32); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -6069,7 +6064,7 @@ TEST(D16FormatExecution, PackedFormatD16LoadStoreThrowUnimplemented) { // reused across cases without any reset. for (const auto &c : cases) { SCOPED_TRACE(c.mnemonic); - std::unique_ptr inst(decoder->decode(c.words.data())); + std::unique_ptr inst(decode_valid(*decoder, c.words.data())); ASSERT_NE(inst, nullptr); ASSERT_EQ(std::string_view(inst->mnemonic()), c.mnemonic); EXPECT_TRUE(inst->is_memory_op()) << c.mnemonic; diff --git a/emulation/rocjitsu/tests/isa_registry_composition_test.cpp b/emulation/rocjitsu/tests/isa_registry_composition_test.cpp index 62d34cc7de0a..2d69523bdda6 100644 --- a/emulation/rocjitsu/tests/isa_registry_composition_test.cpp +++ b/emulation/rocjitsu/tests/isa_registry_composition_test.cpp @@ -4,6 +4,7 @@ /// @file isa_registry_composition_test.cpp /// @brief Multi-component static ISA registry composition tests. +#include "decode_test_util.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" #include "rocjitsu/isa/target_registry.h" @@ -32,7 +33,7 @@ TEST(IsaRegistryCompositionTest, ComponentsKeepIndependentStaticSubsets) { constexpr uint32_t kSNop = 0xBF800000u; std::unique_ptr full_decoder = Decoder::create(full, "gfx1250"); ASSERT_NE(full_decoder, nullptr); - std::unique_ptr full_instruction(full_decoder->decode(&kSNop)); + std::unique_ptr full_instruction(decode_valid(*full_decoder, &kSNop)); ASSERT_NE(full_instruction, nullptr); EXPECT_NE(full_instruction->execute, nullptr); diff --git a/emulation/rocjitsu/tests/isa_target_registry_test.cpp b/emulation/rocjitsu/tests/isa_target_registry_test.cpp index 6e886dc0cd25..e32f6cc3f989 100644 --- a/emulation/rocjitsu/tests/isa_target_registry_test.cpp +++ b/emulation/rocjitsu/tests/isa_target_registry_test.cpp @@ -1,6 +1,7 @@ // Copyright (c) 2026 Advanced Micro Devices, Inc. // SPDX-License-Identifier: MIT +#include "decode_test_util.h" #include "rocjitsu/isa/arch/amdgpu/cdna1/target_provider.h" #include "rocjitsu/isa/arch/amdgpu/cdna2/target_provider.h" #include "rocjitsu/isa/arch/amdgpu/rdna4/target_provider.h" @@ -23,8 +24,11 @@ namespace { class FixtureDecoder final : public Decoder { public: - Instruction *decode(const rj_code_binary_inst_t *) override { return nullptr; } std::size_t max_instruction_words() const override { return 1; } + + DecodeResult decode(const rj_code_binary_inst_t *, const DecodeErrorEmitter &) override { + return Result::failure(); + } }; std::unique_ptr create_fixture_decoder() { return std::make_unique(); } @@ -354,9 +358,15 @@ TEST(IsaTargetRegistryTest, BuiltinRegistryUsesDescriptorOwnedPublicEnumBindings std::unique_ptr risc_v_decoder = Decoder::create(registry, ROCJITSU_CODE_ARCH_RV64I); ASSERT_NE(risc_v_decoder, nullptr); constexpr rj_code_binary_inst_t kAddiX1X0One = 0x00100093; - std::unique_ptr risc_v_instruction(risc_v_decoder->decode(&kAddiX1X0One)); + std::unique_ptr risc_v_instruction(decode_valid(*risc_v_decoder, &kAddiX1X0One)); ASSERT_NE(risc_v_instruction, nullptr); EXPECT_NE(risc_v_instruction->execute, nullptr); + + constexpr rj_code_binary_inst_t kInvalidRiscV = 0xffffffffu; + std::vector diagnostics; + auto collect = [&](std::string_view message) { diagnostics.emplace_back(message); }; + EXPECT_TRUE(risc_v_decoder->decode(&kInvalidRiscV, DecodeErrorEmitter(collect)).failed()); + EXPECT_EQ(diagnostics, std::vector{"Invalid instruction opcode"}); } TEST(IsaTargetRegistryTest, PublicCEntryPointAcceptsCanonicalTargetIds) { diff --git a/emulation/rocjitsu/tests/matmul_test.cpp b/emulation/rocjitsu/tests/matmul_test.cpp index 46767a753538..6b858abb2eb5 100644 --- a/emulation/rocjitsu/tests/matmul_test.cpp +++ b/emulation/rocjitsu/tests/matmul_test.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: MIT #include "aql_queue.h" +#include "decode_test_util.h" #include "test_paths.h" #include "embedded_schema.h" @@ -74,7 +75,7 @@ std::vector> decode_all(const CodeObject &co) { size_t words = sec->size() / sizeof(uint32_t); size_t pc = 0; while (pc < words) { - std::unique_ptr inst(decoder->decode(&data[pc])); + std::unique_ptr inst(decode_valid(*decoder, &data[pc])); EXPECT_NE(inst, nullptr); ++pc; if (inst && inst->size() == 8) diff --git a/emulation/rocjitsu/tests/model_only_isa_test.cpp b/emulation/rocjitsu/tests/model_only_isa_test.cpp index 46d45d4380bc..cfff2d9de4e8 100644 --- a/emulation/rocjitsu/tests/model_only_isa_test.cpp +++ b/emulation/rocjitsu/tests/model_only_isa_test.cpp @@ -4,6 +4,7 @@ /// @file model_only_isa_test.cpp /// @brief Link and decode smoke test for the narrow model-only ISA boundary. +#include "decode_test_util.h" #include "rocjitsu/isa/arch/amdgpu/cdna5/isa.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -30,12 +31,12 @@ TEST(ModelOnlyIsaTest, DecodesWithoutExecutionCallback) { ASSERT_NE(decoder, nullptr); EXPECT_EQ(Decoder::create(registry, ROCJITSU_CODE_ARCH_RDNA4), nullptr); - std::unique_ptr inst(decoder->decode(&kSNop)); + std::unique_ptr inst(decode_valid(*decoder, &kSNop)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "s_nop"); EXPECT_EQ(inst->execute, nullptr); - inst.reset(decoder->decode(&kVMovB32V0V1)); + inst.reset(decode_valid(*decoder, &kVMovB32V0V1)); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->mnemonic(), "v_mov_b32_e32"); ASSERT_EQ(inst->num_src_operands(), 1); diff --git a/emulation/rocjitsu/tests/patch/instrumentor_test.cpp b/emulation/rocjitsu/tests/patch/instrumentor_test.cpp index 3668c7e3158e..4e5622349032 100644 --- a/emulation/rocjitsu/tests/patch/instrumentor_test.cpp +++ b/emulation/rocjitsu/tests/patch/instrumentor_test.cpp @@ -1,6 +1,7 @@ // Copyright (c) 2025-2026 Advanced Micro Devices, Inc. // SPDX-License-Identifier: MIT +#include "decode_test_util.h" #include "rocjitsu/code/patch/instrumentor.h" #include "rocjitsu/code/amdgpu_code_object.h" @@ -892,7 +893,7 @@ TEST(InstrumentorPatch, PatchesEightByteAnchorEndToEnd) { auto decode_at = [&](uint64_t off) { std::array w{}; std::memcpy(w.data(), text->data() + off, w.size() * sizeof(rj_code_binary_inst_t)); - return std::unique_ptr(decoder->decode(w.data())); + return std::unique_ptr(decode_valid(*decoder, w.data())); }; // Patched anchor decodes as a forward s_branch. @@ -1186,7 +1187,7 @@ class InstrumentorPatchDecoded : public ::testing::Test { std::unique_ptr decode_word(const Section *section, size_t byte_offset) { rj_code_binary_inst_t word = 0; std::memcpy(&word, section->data() + byte_offset, sizeof(word)); - return std::unique_ptr(decoder_->decode(&word)); + return std::unique_ptr(decode_valid(*decoder_, &word)); } // Byte size of the original .text before instrumentation. The trampoline cave diff --git a/emulation/rocjitsu/tests/patch/probe_callable_test.cpp b/emulation/rocjitsu/tests/patch/probe_callable_test.cpp index 854c942a7fb1..af81892f45e6 100644 --- a/emulation/rocjitsu/tests/patch/probe_callable_test.cpp +++ b/emulation/rocjitsu/tests/patch/probe_callable_test.cpp @@ -165,6 +165,18 @@ TEST(ProbeCallableTest, BuildsNopProbe) { EXPECT_EQ(callable->output_text_offset, 0u); // assigned by a later layout step. } +TEST(ProbeCallableTest, ReportsRejectedEncodingAndWordOffset) { + const std::vector body{0xffffffffu, kSSetpcS30S31}; + const auto image = make_elf(body); + AmdGpuCodeObject obj(image.data(), image.size()); + + std::string err; + EXPECT_FALSE(build_probe_callable(obj, whole_body_symbol(body), ROCJITSU_CODE_ARCH_CDNA2, &err) + .has_value()); + EXPECT_NE(err.find("word 0"), std::string::npos) << err; + EXPECT_NE(err.find("Invalid instruction opcode"), std::string::npos) << err; +} + TEST(ProbeCallableTest, RejectsBodyWithCall) { const std::vector body{kSSwappcS30S31, kSSetpcS30S31}; const auto image = make_elf(body); diff --git a/emulation/rocjitsu/tests/patch/probe_clobber_test.cpp b/emulation/rocjitsu/tests/patch/probe_clobber_test.cpp index 26aaac81c6db..f9464ddc4076 100644 --- a/emulation/rocjitsu/tests/patch/probe_clobber_test.cpp +++ b/emulation/rocjitsu/tests/patch/probe_clobber_test.cpp @@ -74,6 +74,14 @@ TEST(ProbeClobber, NopProbeSummaryIsEmpty) { EXPECT_FALSE(summary->uses_private_segment); } +TEST(ProbeClobber, ReportsRejectedEncodingAndWordOffset) { + const auto callable = make_callable({0xffffffffu, kSSetpcS30S31}); + std::string err; + EXPECT_FALSE(build_probe_clobber_summary(callable, &err).has_value()); + EXPECT_NE(err.find("word 0"), std::string::npos) << err; + EXPECT_NE(err.find("Invalid instruction opcode"), std::string::npos) << err; +} + // The summary is decode-derived, not declared: a body that writes s5 reports s5 // (and only s5) as an ordinary clobber. TEST(ProbeClobber, DerivesOrdinaryClobberFromBody) { diff --git a/emulation/rocjitsu/tests/patch/spill_manager_test.cpp b/emulation/rocjitsu/tests/patch/spill_manager_test.cpp index 6f3acb291436..06ca7d80b55b 100644 --- a/emulation/rocjitsu/tests/patch/spill_manager_test.cpp +++ b/emulation/rocjitsu/tests/patch/spill_manager_test.cpp @@ -3,6 +3,7 @@ #include "rocjitsu/code/patch/spill_manager.h" +#include "decode_test_util.h" #include "rocjitsu/analysis/exec_state.h" #include "rocjitsu/analysis/liveness.h" #include "rocjitsu/code/basic_block.h" @@ -111,7 +112,7 @@ class IntegDecoder : public Decoder { public: std::size_t max_instruction_words() const override { return 1; } - Instruction *decode(const rj_code_binary_inst_t *inst) override { + DecodeResult decode(const rj_code_binary_inst_t *inst, const DecodeErrorEmitter &) override { auto op = static_cast(*inst); switch (op) { case IntegOpcode::Def_Vgpr0_Sgpr4: @@ -535,7 +536,7 @@ TEST(SpillManager, IntegrationFromLiveBefore) { }; TestCodeObject co(std::move(words)); IntegDecoder decoder; - auto blocks = BasicBlock::build(co, decoder, ROCJITSU_CODE_ARCH_CDNA3); + auto blocks = build_valid_blocks(co, decoder, ROCJITSU_CODE_ARCH_CDNA3); ASSERT_FALSE(blocks.empty()); // Pick the probe-site instruction by mnemonic match. diff --git a/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp b/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp index a88c6b7ab81b..a2661fb28686 100644 --- a/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp +++ b/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp @@ -4,6 +4,7 @@ /// @file pseudo_scalar_exec_test.cpp /// @brief Cross-architecture pseudo-scalar transcendental execution tests. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/test_encodings.h" @@ -701,7 +702,7 @@ TEST_P(PseudoScalarExecTest, ExecutesAtExecZeroWithDestinationOpselZeroAndUsesLo encode_vop3(profile, test_case.mnemonic, kDestinationSgpr, kSourceSgpr, {.source_opsel = test_case.set_source_opsel}); ASSERT_EQ(words[0] & kDestinationOpselBit, 0u) << "OPSEL[3] must select the low destination half"; - std::unique_ptr instruction(fixture.decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*fixture.decoder, words.data())); ASSERT_NE(instruction, nullptr) << profile.name << " " << test_case.mnemonic; ASSERT_EQ(std::string_view(instruction->mnemonic()), test_case.mnemonic) << profile.name; EXPECT_EQ(instruction->size(), 8u); @@ -730,7 +731,7 @@ TEST_P(PseudoScalarExecTest, ExecutesWithVccAsSourceAndDestination) { const InstructionWords words = encode_vop3(profile, test_case.mnemonic, selector, selector, {.source_opsel = test_case.set_source_opsel}); - std::unique_ptr instruction(fixture.decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*fixture.decoder, words.data())); ASSERT_NE(instruction, nullptr); const uint64_t source = selector == kVccSelectors[0] @@ -759,7 +760,7 @@ TEST(PseudoScalarDecodeTest, RejectsOutOfClassDestinations) { SCOPED_TRACE(selector); const InstructionWords words = encode_vop3(profile, test_case.mnemonic, selector, kSourceSgpr); - EXPECT_THROW((void)decoder->decode(words.data()), util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); } } } @@ -774,10 +775,7 @@ TEST(PseudoScalarDecodeTest, RejectsDppAndDpp8Sources) { ASSERT_NE(decoder, nullptr) << profile.name; for (const uint32_t source : kUnsupportedSources) { const InstructionWords words = encode_vop3(profile, "v_s_sqrt_f32", kDestinationSgpr, source); - EXPECT_THROW( - { std::unique_ptr instruction(decoder->decode(words.data())); }, - util::InvalidInst) - << profile.name << " source=" << source; + EXPECT_TRUE(decode_fails(*decoder, words.data())) << profile.name << " source=" << source; } } } @@ -890,7 +888,7 @@ TEST_P(PseudoScalarSpecialExecTest, CoversLiteralModifierAndModeBehavior) { const InstructionWords words = encode_vop3(profile, test_case.mnemonic, kDestinationSgpr, kSourceSgpr, test_case.encoding); - std::unique_ptr instruction(fixture.decoder->decode(words.data())); + std::unique_ptr instruction(decode_valid(*fixture.decoder, words.data())); ASSERT_NE(instruction, nullptr) << profile.name << " " << test_case.mnemonic; ASSERT_EQ(std::string_view(instruction->mnemonic()), test_case.mnemonic) << profile.name; EXPECT_EQ(instruction->size(), test_case.encoding.use_literal ? 12u : 8u); @@ -930,13 +928,13 @@ TEST(PseudoScalarModeIntegrationTest, SetregInstructionsUpdateModesConsumedByPse const BaseEncodingWords set_round_words = encode_sopk(profile.setreg_op, kModeSgpr, encode_hwreg(kModeHwreg)); - std::unique_ptr set_round(fixture.decoder->decode(set_round_words.data())); + std::unique_ptr set_round(decode_valid(*fixture.decoder, set_round_words.data())); ASSERT_NE(set_round, nullptr); ASSERT_EQ(std::string_view(set_round->mnemonic()), "s_setreg_b32"); const InstructionWords exp_words = encode_vop3(profile, "v_s_exp_f32", kDestinationSgpr, kSourceSgpr); - std::unique_ptr exp(fixture.decoder->decode(exp_words.data())); + std::unique_ptr exp(decode_valid(*fixture.decoder, exp_words.data())); ASSERT_NE(exp, nullptr); fixture.wavefront->set_mode_raw(0); @@ -949,13 +947,14 @@ TEST(PseudoScalarModeIntegrationTest, SetregInstructionsUpdateModesConsumedByPse const BaseEncodingWords set_denorm_words = encode_sopk(profile.setreg_imm_op, 0, encode_hwreg(kModeHwreg, 6, 2), 1u); - std::unique_ptr set_denorm(fixture.decoder->decode(set_denorm_words.data())); + std::unique_ptr set_denorm( + decode_valid(*fixture.decoder, set_denorm_words.data())); ASSERT_NE(set_denorm, nullptr); ASSERT_EQ(std::string_view(set_denorm->mnemonic()), "s_setreg_imm32_b32"); const InstructionWords log_words = encode_vop3(profile, "v_s_log_f16", kDestinationSgpr, kSourceSgpr, {.source_opsel = true}); - std::unique_ptr log(fixture.decoder->decode(log_words.data())); + std::unique_ptr log(decode_valid(*fixture.decoder, log_words.data())); ASSERT_NE(log, nullptr); fixture.wavefront->set_mode_raw(0); diff --git a/emulation/rocjitsu/tests/scalar_scc_test.cpp b/emulation/rocjitsu/tests/scalar_scc_test.cpp index 022feff2008c..49f7e4b992b5 100644 --- a/emulation/rocjitsu/tests/scalar_scc_test.cpp +++ b/emulation/rocjitsu/tests/scalar_scc_test.cpp @@ -4,6 +4,7 @@ /// @file scalar_scc_test.cpp /// @brief Cross-architecture scalar SCC execution and preservation tests. +#include "decode_test_util.h" #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" @@ -211,7 +212,7 @@ class ScalarSccFixture { std::unique_ptr decode(const EncodingWords &words, std::string_view expected_mnemonic) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); if (inst) { EXPECT_EQ(std::string_view(inst->mnemonic()), expected_mnemonic) << profile.name; } @@ -278,7 +279,7 @@ void expect_wrexec_def_use(const ScalarSccProfile &profile, const WrexecPair &pa const uint8_t width = pair.is_b64 ? 2 : 1; for (const auto mnemonic : {pair.first, pair.second}) { const auto words = encode_sop1(profile, mnemonic, kDestSgpr, kSourceSgpr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr) << profile.name << " " << mnemonic; ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic) << profile.name; @@ -684,7 +685,7 @@ TEST(ScalarSccTest, AddkAndMulkRegisterDestinationRead) { const std::array mnemonics{addk_mnemonic(profile), std::string_view{"s_mulk_i32"}}; for (const auto mnemonic : mnemonics) { const auto words = encode_sopk(profile, mnemonic, /*sdst=*/4, /*simm16=*/1); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr) << profile.name << " " << mnemonic; ASSERT_EQ(std::string_view(inst->mnemonic()), mnemonic) << profile.name; diff --git a/emulation/rocjitsu/tests/shared_infra_test.cpp b/emulation/rocjitsu/tests/shared_infra_test.cpp index aabb0efcc9db..fb8af3de139d 100644 --- a/emulation/rocjitsu/tests/shared_infra_test.cpp +++ b/emulation/rocjitsu/tests/shared_infra_test.cpp @@ -4,6 +4,7 @@ /// @file shared_infra_test.cpp /// @brief Phase B unit tests: addr_calc, MMA execution, wavefront context, CU factory. +#include "decode_test_util.h" #include "rocjitsu/isa/arch/amdgpu/cdna1/isa.h" #include "rocjitsu/isa/arch/amdgpu/cdna2/isa.h" #include "rocjitsu/isa/arch/amdgpu/cdna3/isa.h" @@ -12,14 +13,17 @@ #include "rocjitsu/isa/arch/amdgpu/cdna5/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/machine_insts.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna1/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/machine_insts.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna2/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/machine_insts.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna3/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/execution_backend.h" @@ -35,10 +39,12 @@ #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/machine_insts.h" +#include "rocjitsu/isa/arch/amdgpu/generated/rdna1/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/execution_backend.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/machine_insts.h" +#include "rocjitsu/isa/arch/amdgpu/generated/rdna2/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vop1.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/vopc.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/execution_backend.h" @@ -2309,6 +2315,7 @@ TEST(DppPermuteTest, WriteMaskHonorsBoundCtrlAndBroadcastValidity) { struct Cdna1DppTraits { static constexpr const char *name = "cdna1"; static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA1; + static constexpr uint16_t vopc_opcode = cdna1::kVCmpEqU32Vopc; static const IsaExecutionBackend &backend() { return cdna1::execution_backend(); } using MachineInst = cdna1::MachineInst; using Vop1VopDppMachineInst = cdna1::Vop1VopDppMachineInst; @@ -2320,6 +2327,7 @@ struct Cdna1DppTraits { struct Cdna2DppTraits { static constexpr const char *name = "cdna2"; static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA2; + static constexpr uint16_t vopc_opcode = cdna2::kVCmpEqU32Vopc; static const IsaExecutionBackend &backend() { return cdna2::execution_backend(); } static constexpr uint32_t wf_size = 64; using MachineInst = cdna2::MachineInst; @@ -2334,6 +2342,7 @@ struct Cdna2DppTraits { struct Cdna3DppTraits { static constexpr const char *name = "cdna3"; static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA3; + static constexpr uint16_t vopc_opcode = cdna3::kVCmpEqU32Vopc; static const IsaExecutionBackend &backend() { return cdna3::execution_backend(); } static constexpr uint32_t wf_size = 64; using MachineInst = cdna3::MachineInst; @@ -2348,6 +2357,7 @@ struct Cdna3DppTraits { struct Cdna4DppTraits { static constexpr const char *name = "cdna4"; static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA4; + static constexpr uint16_t vopc_opcode = cdna4::kVCmpEqU32Vopc; static const IsaExecutionBackend &backend() { return cdna4::execution_backend(); } static constexpr uint32_t wf_size = 64; using MachineInst = cdna4::MachineInst; @@ -2362,6 +2372,7 @@ struct Cdna4DppTraits { struct Rdna1DppTraits { static constexpr const char *name = "rdna1"; static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_RDNA1; + static constexpr uint16_t vopc_opcode = rdna1::kVCmpEqU32Vopc; static const IsaExecutionBackend &backend() { return rdna1::execution_backend(); } using MachineInst = rdna1::MachineInst; using VopcMachineInst = rdna1::VopcMachineInst; @@ -2375,6 +2386,7 @@ struct Rdna1DppTraits { struct Rdna2DppTraits { static constexpr const char *name = "rdna2"; static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_RDNA2; + static constexpr uint16_t vopc_opcode = rdna2::kVCmpEqU32Vopc; static const IsaExecutionBackend &backend() { return rdna2::execution_backend(); } using MachineInst = rdna2::MachineInst; using VopcMachineInst = rdna2::VopcMachineInst; @@ -3149,32 +3161,34 @@ template void wave32_generated_vcmpx_preserves_exec_hi() { EXPECT_EQ(wf->exec_raw(), 0xA5A55A5A0F0F0F0FULL); } -template void unsupported_rdna_vopc_dpp_throws() { +template void unsupported_rdna_vopc_dpp_rejects() { SCOPED_TRACE(Traits::name); - auto expect_throws = [](uint32_t src0) { + auto decoder = Decoder::create(Traits::arch); + ASSERT_NE(decoder, nullptr); + auto expect_rejection = [&](uint32_t src0) { typename Traits::Vop1VopDpp16MachineInst raw{}; raw.src0 = src0; - - EXPECT_THROW(typename Traits::VCmpEqU32Vopc( - reinterpret_cast(&raw)), - util::InvalidInst); + raw.op = Traits::vopc_opcode; + raw.encoding = 62; + EXPECT_TRUE(decode_fails(*decoder, reinterpret_cast(&raw))); }; - expect_throws(amdgpu::SRC_DPP); - expect_throws(amdgpu::SRC_DPP8_FI_0); - expect_throws(amdgpu::SRC_DPP8_FI_1); + expect_rejection(amdgpu::SRC_DPP); + expect_rejection(amdgpu::SRC_DPP8_FI_0); + expect_rejection(amdgpu::SRC_DPP8_FI_1); } -template void unsupported_cdna_vopc_dpp_throws() { +template void unsupported_cdna_vopc_dpp_rejects() { SCOPED_TRACE(Traits::name); typename Traits::Vop1VopDppMachineInst raw{}; raw.src0 = amdgpu::SRC_DPP; - - EXPECT_THROW( - typename Traits::VCmpEqU32Vopc(reinterpret_cast(&raw)), - util::InvalidInst); + raw.op = Traits::vopc_opcode; + raw.encoding = 62; + auto decoder = Decoder::create(Traits::arch); + ASSERT_NE(decoder, nullptr); + EXPECT_TRUE(decode_fails(*decoder, reinterpret_cast(&raw))); } void cdna4_vop1_sdwa_availability_is_instruction_specific() { @@ -3186,9 +3200,13 @@ void cdna4_vop1_sdwa_availability_is_instruction_specific() { raw.dst_sel = amdgpu::sdwa::DWORD; raw.dst_unused = amdgpu::sdwa::UNUSED_PAD; - EXPECT_NO_THROW(cdna4::VMovB32Vop1(reinterpret_cast(&raw))); - EXPECT_THROW(cdna4::VCvtF64I32Vop1(reinterpret_cast(&raw)), - util::InvalidInst); + raw.encoding = cdna4::encoding::kVop1 >> 2; + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + raw.op = cdna4::kVMovB32Vop1; + EXPECT_FALSE(decode_fails(*decoder, reinterpret_cast(&raw))); + raw.op = cdna4::kVCvtF64I32Vop1; + EXPECT_TRUE(decode_fails(*decoder, reinterpret_cast(&raw))); } TEST(SdwaTest, Cdna4DisassemblesDestinationAndSourceAttributes) { @@ -3207,7 +3225,7 @@ TEST(SdwaTest, Cdna4DisassemblesDestinationAndSourceAttributes) { const auto words = std::bit_cast>(raw); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->disassemble(), "v_floor_f32_sdwa v0, v92 clamp div:2 dst_sel:BYTE_0 " "dst_unused:UNUSED_PAD src0_sel:BYTE_0"); @@ -3231,7 +3249,7 @@ TEST(SdwaTest, Cdna4DisassemblesCompareDestinationAndSourceModifiers) { const auto words = std::bit_cast>(raw); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->disassemble(), "v_cmp_eq_f32_sdwa s[4:5], -|v0|, -v1 src0_sel:BYTE_0 src1_sel:DWORD"); @@ -3253,7 +3271,7 @@ TEST(SdwaTest, Cdna4DisassemblesImplicitCompareDestination) { const auto words = std::bit_cast>(raw); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->disassemble(), "v_cmp_eq_f32_sdwa vcc, v0, v1 src0_sel:DWORD src1_sel:DWORD"); } @@ -3277,7 +3295,7 @@ TEST(SdwaTest, Cdna4DisassemblesBothVop2Sources) { const auto words = std::bit_cast>(raw); auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); EXPECT_EQ(inst->disassemble(), "v_add_f32_sdwa v5, -|v2|, -v3 dst_sel:DWORD dst_unused:UNUSED_PAD " @@ -3299,7 +3317,7 @@ TEST(DecodeSizeTest, Cdna4UsesOpcodeOperandCapabilitiesForLiteralSelectors) { set_gpr_idx.op = cdna4::kSSetGprIdxOnSopc; set_gpr_idx.encoding = cdna4::encoding::kSopc; const auto set_gpr_idx_words = std::bit_cast>(set_gpr_idx); - std::unique_ptr set_gpr_idx_inst(decoder->decode(set_gpr_idx_words.data())); + std::unique_ptr set_gpr_idx_inst(decode_valid(*decoder, set_gpr_idx_words.data())); ASSERT_NE(set_gpr_idx_inst, nullptr); EXPECT_EQ(set_gpr_idx_inst->size(), sizeof(uint32_t)); @@ -3309,7 +3327,7 @@ TEST(DecodeSizeTest, Cdna4UsesOpcodeOperandCapabilitiesForLiteralSelectors) { get_pc.sdst = 0; get_pc.encoding = cdna4::encoding::kSop1; const auto get_pc_words = std::bit_cast>(get_pc); - std::unique_ptr get_pc_inst(decoder->decode(get_pc_words.data())); + std::unique_ptr get_pc_inst(decode_valid(*decoder, get_pc_words.data())); ASSERT_NE(get_pc_inst, nullptr); EXPECT_EQ(get_pc_inst->size(), sizeof(uint32_t)); @@ -3319,16 +3337,14 @@ TEST(DecodeSizeTest, Cdna4UsesOpcodeOperandCapabilitiesForLiteralSelectors) { fork.op = cdna4::kSCbranchGForkSop2; fork.encoding = cdna4::encoding::kSop2 >> 7; const auto fork_words = std::bit_cast>(fork); - EXPECT_THROW( - { std::unique_ptr fork_inst(decoder->decode(fork_words.data())); }, - util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, fork_words.data())); cdna4::Vop1MachineInst v_nop{}; v_nop.src0 = 255; v_nop.op = cdna4::kVNopVop1; v_nop.encoding = cdna4::encoding::kVop1 >> 2; const auto v_nop_words = std::bit_cast>(v_nop); - std::unique_ptr v_nop_inst(decoder->decode(v_nop_words.data())); + std::unique_ptr v_nop_inst(decode_valid(*decoder, v_nop_words.data())); ASSERT_NE(v_nop_inst, nullptr); EXPECT_EQ(v_nop_inst->size(), sizeof(uint32_t)); @@ -3339,7 +3355,8 @@ TEST(DecodeSizeTest, Cdna4UsesOpcodeOperandCapabilitiesForLiteralSelectors) { scalar_literal.encoding = cdna4::encoding::kSop1; const std::array scalar_literal_words = {std::bit_cast(scalar_literal), 0x12345678u}; - std::unique_ptr scalar_literal_inst(decoder->decode(scalar_literal_words.data())); + std::unique_ptr scalar_literal_inst( + decode_valid(*decoder, scalar_literal_words.data())); ASSERT_NE(scalar_literal_inst, nullptr); EXPECT_EQ(scalar_literal_inst->size(), sizeof(scalar_literal_words)); } @@ -3361,8 +3378,7 @@ void cdna4_unsupported_sdwa_decode_halts_wave() { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); ASSERT_NE(decoder, nullptr); - EXPECT_THROW( - { std::unique_ptr inst(decoder->decode(words.data())); }, util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, words.data())); amdgpu::GpuMemory mem("cdna4_unsupported_sdwa_mem"); amdgpu::L2Cache l2("cdna4_unsupported_sdwa_l2"); @@ -3393,10 +3409,11 @@ template void rdna4_vop3_dpp_marker_is_instruction_specific(uint3 raw.src1 = 5; raw.vdst = 8; - EXPECT_NO_THROW(rdna4::VAddF32Vop3(reinterpret_cast(&raw))); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); + ASSERT_NE(decoder, nullptr); + EXPECT_FALSE(decode_fails(*decoder, reinterpret_cast(&raw))); raw.op = rdna4::kVAddF64Vop3; - EXPECT_THROW(rdna4::VAddF64Vop3(reinterpret_cast(&raw)), - util::InvalidInst); + EXPECT_TRUE(decode_fails(*decoder, reinterpret_cast(&raw))); } template void rdna4_vop3p_dpp_marker_is_unsupported(uint32_t marker) { @@ -3407,8 +3424,9 @@ template void rdna4_vop3p_dpp_marker_is_unsupported(uint32_t mark raw.vsrc0 = 4; raw.src1 = 5; raw.vdst = 8; - EXPECT_THROW(rdna4::VPkAddF16Vop3p(reinterpret_cast(&raw)), - util::InvalidInst); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA4); + ASSERT_NE(decoder, nullptr); + EXPECT_TRUE(decode_fails(*decoder, reinterpret_cast(&raw))); } void rdna4_vop3_dpp_availability_is_instruction_specific() { @@ -3433,11 +3451,11 @@ TEST(DppPermuteTest, CdnaGeneratedVop1DppWriteMaskHonorsBoundCtrl) { cdna_generated_vop1_dpp_write_mask_honors_bound_ctrl(); } -TEST(DppPermuteTest, CdnaVopcDppThrowsUnsupported) { - unsupported_cdna_vopc_dpp_throws(); - unsupported_cdna_vopc_dpp_throws(); - unsupported_cdna_vopc_dpp_throws(); - unsupported_cdna_vopc_dpp_throws(); +TEST(DppPermuteTest, CdnaVopcDppRejectsUnsupported) { + unsupported_cdna_vopc_dpp_rejects(); + unsupported_cdna_vopc_dpp_rejects(); + unsupported_cdna_vopc_dpp_rejects(); + unsupported_cdna_vopc_dpp_rejects(); } TEST(DppPermuteTest, Cdna4Vop1SdwaAvailabilityIsInstructionSpecific) { @@ -3554,12 +3572,12 @@ TEST(ExecMaskTest, RdnaGeneratedVcmpxWave32PreservesExecHi) { wave32_generated_vcmpx_preserves_exec_hi(); } -TEST(DppPermuteTest, Rdna1VopcDppThrowsUnsupported) { - unsupported_rdna_vopc_dpp_throws(); +TEST(DppPermuteTest, Rdna1VopcDppRejectsUnsupported) { + unsupported_rdna_vopc_dpp_rejects(); } -TEST(DppPermuteTest, Rdna2VopcDppThrowsUnsupported) { - unsupported_rdna_vopc_dpp_throws(); +TEST(DppPermuteTest, Rdna2VopcDppRejectsUnsupported) { + unsupported_rdna_vopc_dpp_rejects(); } // --------------------------------------------------------------------------- @@ -3837,7 +3855,7 @@ TEST(RdnaScratchExecutionTest, Rdna3B128StoreFeedsB32LoadsWithVectorOffsets) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_RDNA3); ASSERT_NE(decoder, nullptr); auto execute_mem = [&](std::array words) { - std::unique_ptr inst(decoder->decode(words.data())); + std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); cu->execute_and_route(inst.release(), *wf); }; @@ -4380,7 +4398,7 @@ void expect_vector_lane_reads_use_own_wave_vgprs(rj_code_arch_t arch) { for (uint32_t i = 0; i < wfs.size(); ++i) { const uint32_t sbase = wfs[i]->sgpr_alloc().base; - std::unique_ptr inst(decoder->decode(kReadfirstlaneS24V1.data())); + std::unique_ptr inst(decode_valid(*decoder, kReadfirstlaneS24V1.data())); ASSERT_NE(inst, nullptr); cu->write_sgpr(sbase + 24, 0); cu->execute_instruction(inst.get(), *wfs[i]); @@ -4389,7 +4407,7 @@ void expect_vector_lane_reads_use_own_wave_vgprs(rj_code_arch_t arch) { for (uint32_t i = 0; i < wfs.size(); ++i) { const uint32_t sbase = wfs[i]->sgpr_alloc().base; - std::unique_ptr inst(decoder->decode(kReadlaneS4V141Lane2.data())); + std::unique_ptr inst(decode_valid(*decoder, kReadlaneS4V141Lane2.data())); ASSERT_NE(inst, nullptr); cu->write_sgpr(sbase + 2, 0); cu->write_sgpr(sbase + 4, 0); @@ -4399,7 +4417,7 @@ void expect_vector_lane_reads_use_own_wave_vgprs(rj_code_arch_t arch) { for (uint32_t i = 0; i < wfs.size(); ++i) { const uint32_t sbase = wfs[i]->sgpr_alloc().base; - std::unique_ptr inst(decoder->decode(kReadlaneS4V4Lane31.data())); + std::unique_ptr inst(decode_valid(*decoder, kReadlaneS4V4Lane31.data())); ASSERT_NE(inst, nullptr); cu->write_sgpr(sbase + 4, 0); cu->write_sgpr(sbase + 31, 0); @@ -4409,7 +4427,7 @@ void expect_vector_lane_reads_use_own_wave_vgprs(rj_code_arch_t arch) { for (uint32_t i = 0; i < wfs.size(); ++i) { const uint32_t sbase = wfs[i]->sgpr_alloc().base; - std::unique_ptr inst(decoder->decode(kReadlaneS4V141S2.data())); + std::unique_ptr inst(decode_valid(*decoder, kReadlaneS4V141S2.data())); ASSERT_NE(inst, nullptr); cu->write_sgpr(sbase + 2, 31); cu->write_sgpr(sbase + 4, 0); @@ -4420,7 +4438,7 @@ void expect_vector_lane_reads_use_own_wave_vgprs(rj_code_arch_t arch) { for (uint32_t i = 0; i < wfs.size(); ++i) { const uint32_t sbase = wfs[i]->sgpr_alloc().base; const uint32_t vbase = wfs[i]->vgpr_alloc().base; - std::unique_ptr inst(decoder->decode(kWritelaneV141S4S2.data())); + std::unique_ptr inst(decode_valid(*decoder, kWritelaneV141S4S2.data())); ASSERT_NE(inst, nullptr); cu->write_sgpr(sbase + 2, 31); cu->write_sgpr(sbase + 4, 0x500u + i); diff --git a/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_scalar_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_scalar_correctness_test.cpp index 76a7a7ddd973..58e9b492867a 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_scalar_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_scalar_correctness_test.cpp @@ -15,6 +15,7 @@ /// a visibly wrong result. No SIMD is involved (these ops are not on the SIMD /// fast path); this exercises the plain decode+execute scalar path. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -81,7 +82,7 @@ struct Fixture { write64(vb + 2, 0, 0xA5A5A5A5A5A5A5A5ull); // sentinel in dst pair uint32_t enc = vop1_encode(op, /*vdst=*/2, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); EXPECT_NE(inst, nullptr); cu->execute_instruction(inst, *wf); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_simd_correctness_test.cpp index 18be5c413f36..cb3584766160 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f64_simd_correctness_test.cpp @@ -22,6 +22,7 @@ /// conversions are exact (NaN->0 and the saturating clamp are deterministic), /// compared with no carve-out. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -205,7 +206,7 @@ void check_case(const CvtCase &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop1_encode(c.opcode, /*vdst=*/2, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f8_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f8_simd_correctness_test.cpp index 81e3b615fc0c..189c7841e569 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f8_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop1_cvt_f8_simd_correctness_test.cpp @@ -13,6 +13,7 @@ /// equal with EXPECT_EQ (util::set_force_scalar_for_testing flips the gate /// in-process). In-process inactive lanes must keep the DST sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -126,7 +127,7 @@ void check_words(const std::string &label, const uint32_t words[4], uint64_t exe Fixture fx; EXPECT_NE(fx.cu, nullptr); EXPECT_NE(fx.wf, nullptr); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << label << " decode failed"; auto out = fx.run(inst, block, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop1_f64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop1_f64_simd_correctness_test.cpp index 11062d1daac5..2916d5a0f94b 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop1_f64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop1_f64_simd_correctness_test.cpp @@ -19,6 +19,7 @@ /// inputs, so both runs skip the same lanes. v_mov_b64 is a pure bit copy and is /// compared exactly (no NaN carve-out). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -165,7 +166,7 @@ void check_case(const F64UnaryCase &c, uint64_t exec) { // src0 = v0:v1 (enc 256), vdst = v2:v3. uint32_t enc = vop1_encode(c.opcode, /*vdst=*/2, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop1_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop1_simd_correctness_test.cpp index 17bac464dec3..76943c24537d 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop1_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop1_simd_correctness_test.cpp @@ -16,6 +16,7 @@ /// raw random with explicit edge lanes injected (0, ±0, ±Inf, NaN, denormal, /// INT32 extremes) rather than sanitized to finite normals. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -221,7 +222,7 @@ void check_case(const Vop1Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop1_encode(c.opcode, /*vdst=*/2, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; auto out = fx.run(inst, seed, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_carry_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_carry_simd_correctness_test.cpp index a34179a3269d..c5c68f99e854 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_carry_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_carry_simd_correctness_test.cpp @@ -17,6 +17,7 @@ /// lanes — random-only inputs hide these corners. Inactive-lane carry-out VCC /// bits are zeroed under full and partial EXEC masks. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -166,7 +167,7 @@ void check_case(const CarryCase &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop2_encode(c.opcode, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; auto out = fx.run(inst, SEED, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_cndmask_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_cndmask_simd_correctness_test.cpp index 0fb3953b549b..cfa63d6e6a4c 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_cndmask_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_cndmask_simd_correctness_test.cpp @@ -12,6 +12,7 @@ /// (util::set_force_scalar_for_testing flips the gate in-process). /// In-process inactive EXEC lanes must keep the dst sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -115,7 +116,7 @@ void check_case(uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop2_encode(/*opcode=*/0, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_cndmask_b32: decode failed"; auto out = fx.run(inst, SEED, exec, vcc); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f16_rdna_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f16_rdna_simd_correctness_test.cpp index 68aeb77e21b8..5a6d38142987 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f16_rdna_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f16_rdna_simd_correctness_test.cpp @@ -17,6 +17,7 @@ /// through the packed vs scalar FMA (accepted), so lanes with a NaN input are /// excluded identically in both runs (the skip is input-derived). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -163,7 +164,7 @@ void check_case(const FmaCase &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop2_encode(c.opcode, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256); uint32_t words[4] = {enc, kLiteral, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; fx.seed_inputs(SEED, exec, &nan_lane); fx.cu->execute_instruction(inst, *fx.wf); diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f64_simd_correctness_test.cpp index 9ea4d9def037..5948c6013af3 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_fma_f64_simd_correctness_test.cpp @@ -18,6 +18,7 @@ /// those lanes are excluded from the comparison — NaN-ness of the result is /// deterministic from the inputs, so both runs skip the same lanes. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -192,7 +193,7 @@ void check_fmac_literal_src0(bool force_scalar) { uint32_t enc = vop2_encode(/*opcode=*/4, /*vdst=*/4, /*vsrc1=*/2, /*src0=*/255); uint32_t words[4] = {enc, kLiteralHighWord, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); ASSERT_NE(inst, nullptr) << "v_fmac_f64 literal decode failed"; fx.cu->execute_instruction(inst, *fx.wf); delete inst; @@ -217,7 +218,7 @@ void check_fmac(uint64_t exec) { // v_fmac_f64 = VOP2 op 4. src0 = v0:v1 (enc 256), vsrc1 = v2:v3, vdst = v4:v5. uint32_t enc = vop2_encode(/*opcode=*/4, /*vdst=*/4, /*vsrc1=*/2, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_fmac_f64 decode failed"; auto out = fx.run(inst, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_fma_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_fma_simd_correctness_test.cpp index 34160f35288b..d0204c58c3c3 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_fma_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_fma_simd_correctness_test.cpp @@ -22,6 +22,7 @@ /// equal per active, non-skipped lane (util::set_force_scalar_for_testing flips /// the gate in-process). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -188,7 +189,7 @@ void check_case(const FmaCase &c, uint64_t exec) { // f16 constant 0x3E00 = 1.5h (high bits ignored by the op). const uint32_t literal = c.is_f16 ? 0x00003E00u : 0x3FC00000u; uint32_t words[4] = {enc, c.has_literal ? literal : 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; seeded = fx.seed_inputs(SEED, c.is_f16, exec, &nan_lane); fx.cu->execute_instruction(inst, *fx.wf); diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_minmax_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_minmax_simd_correctness_test.cpp index 323de1242a66..9d36d1254f3c 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_minmax_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_minmax_simd_correctness_test.cpp @@ -18,6 +18,7 @@ /// ±0 and NaN in both operand orders on the low lanes — the corner cases the /// earlier (reverted) f16 min/max shipped without and silently diverged on. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -194,7 +195,7 @@ void check_case(const MinMaxCase &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop2_encode(c.opcode, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; nan_lane = fx.seed_inputs(SEED, c.is_f16, exec); fx.cu->execute_instruction(inst, *fx.wf); diff --git a/emulation/rocjitsu/tests/simd_correctness/vop2_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop2_simd_correctness_test.cpp index 4b40d9a07c37..6ec14c5258d8 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop2_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop2_simd_correctness_test.cpp @@ -11,6 +11,7 @@ /// here). In-process the test also checks inactive-lane preservation under full /// and partial EXEC masks. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -188,7 +189,7 @@ void check_case(const Vop2Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t enc = vop2_encode(c.opcode, /*vdst=*/2, /*vsrc1=*/1, /*src0=*/256); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; auto out = fx.run(inst, SEED, c.is_float, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_b16_rdna_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_b16_rdna_simd_correctness_test.cpp index b249a261b25b..07b505b013b6 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_b16_rdna_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_b16_rdna_simd_correctness_test.cpp @@ -19,6 +19,7 @@ /// — the high 16 bits of the destination VGPR are zeroed. The CU and decoder /// are built for RDNA3; encoding marker is 0x35<<26. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -174,7 +175,7 @@ void check_binary(const BinCase &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(c.opcode, kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/0, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; @@ -210,7 +211,7 @@ void check_not_b16(uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(/*op=*/489, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/0, /*src2=*/0, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_not_b16_vop3 decode failed"; auto out = fx.run(inst, 0, exec); delete inst; @@ -246,7 +247,7 @@ void check_cndmask_b16(uint64_t exec, uint64_t sel) { uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(/*op=*/605, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/sb, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_cndmask_b16_vop3 decode failed"; auto out = fx.run(inst, rot, exec); delete inst; @@ -335,7 +336,7 @@ void check_mov_b16(uint64_t exec, uint32_t omod, uint32_t clamp) { uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode_mod(/*op=*/412, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/0, /*src2=*/0, clamp, omod, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_mov_b16_vop3 decode failed"; auto out = fx.run(inst, 0, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_binary_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_binary_simd_correctness_test.cpp index c40b98752487..5d113cf64566 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_binary_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_binary_simd_correctness_test.cpp @@ -13,6 +13,7 @@ /// with EXPECT_EQ (util::set_force_scalar_for_testing flips the gate in-process). /// In-process inactive lanes must stay preserved under full and partial EXEC. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -258,7 +259,7 @@ void check(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32_t cl uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c.kind, exec); delete inst; @@ -346,7 +347,7 @@ void check_f16(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32_ uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c.kind, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp index 0266f7682118..f9b1dd60fa0d 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp @@ -19,6 +19,7 @@ /// lanes must keep the sentinel. Inputs deliberately seed the 32-bit /// carry/borrow boundary on the low lanes. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -246,7 +247,7 @@ void check_case(const char *mem_label, const char *l2_label, const char *cu_labe uint32_t words[2] = {0u, 0u}; vop3_sdstenc_encode(c.opcode, /*vdst=*/2, /*sdst=*/sb, /*src0=*/256, /*src1=*/257, /*src2=*/src2_field, encoding_marker, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.label << ": decode failed"; auto out = fx.run(inst, SEED, exec, vcc_in, SDST_SEED, sb, cin_word, cin_pair); delete inst; @@ -325,7 +326,7 @@ void check_rdna4_wave64_carry_in_oracle() { uint32_t words[2] = {0u, 0u}; vop3_sdstenc_encode(/*op=*/288, /*vdst=*/2, /*sdst=*/sb, /*src0=*/256, /*src1=*/257, /*src2=*/cin_pair, kRdna3Encoding, words); - std::unique_ptr inst(fx.decoder->decode(words)); + std::unique_ptr inst(decode_valid(*fx.decoder, words)); ASSERT_NE(inst, nullptr); const uint32_t vbase = fx.wf->vgpr_alloc().base; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_cndmask_pack_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_cndmask_pack_simd_correctness_test.cpp index 576f36ee4fe1..4e5cb65d1a1a 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_cndmask_pack_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_cndmask_pack_simd_correctness_test.cpp @@ -15,6 +15,7 @@ /// - v_pack_b32_f16_vop3: pack the OPSEL-selected 16-bit halves of src0/src1 /// into a b32 dst. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -181,7 +182,7 @@ void check_cndmask_one(uint64_t exec, uint64_t sel) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(/*op=*/256, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/sb, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_cndmask_b32_vop3 decode failed"; auto out = fx.run(inst, rot, exec); delete inst; @@ -220,7 +221,7 @@ void check_pack_one(uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_bin_encode(/*op=*/672, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_pack_b32_f16_vop3 decode failed"; auto out = fx.run(inst, rot, exec); delete inst; @@ -259,7 +260,7 @@ void check_pack_opsel_high_halves(uint64_t exec) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_bin_encode(/*op=*/672, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, words, kOpSelSrc0Src1High); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_pack_b32_f16_vop3 decode failed"; auto out = fx.run(inst, kRot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_f64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_f64_simd_correctness_test.cpp index 42068aea6d5b..4287de9b4a0e 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_f64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_f64_simd_correctness_test.cpp @@ -21,6 +21,7 @@ /// both runs skip the same words. The int conversions are exact (NaN -> 0, /// saturating clamp), compared with no carve-out. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -180,7 +181,7 @@ void check_case(const CvtCase &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/2, /*src0=*/256, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_pk_f32_rdna_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_pk_f32_rdna_correctness_test.cpp index 9287047f3b1c..a80dbb77e1b1 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_pk_f32_rdna_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_cvt_pk_f32_rdna_correctness_test.cpp @@ -26,6 +26,7 @@ /// any future re-introduction of a mismatched SIMD functor is caught. The CU and /// decoder are built for RDNA3; VOP3 encoding marker is 0x35<<26. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -195,7 +196,7 @@ void check_op(uint32_t opcode, bool is_u16, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(opcode, kDstVgpr, /*src0=*/256, /*src1=*/257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << name << " decode failed"; auto out = fx.run(inst, exec); delete inst; @@ -254,7 +255,7 @@ TEST(Vop3CvtPkF32RdnaCorrectness, BugMarker_40000) { auto exec_op = [&](uint32_t opcode) -> uint32_t { uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(opcode, kDstVgpr, 256, 257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr); fx.cu->execute_instruction(inst, *fx.wf); uint32_t r = fx.cu->read_vgpr(vb + kDstVgpr, 0); @@ -291,7 +292,7 @@ void check_cvt_pk_norm_i16(uint64_t exec) { fx.wf->set_exec(exec); uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(kOpCvtPkNormI16F32, kDstVgpr, /*src0=*/256, /*src1=*/257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << name << " decode failed"; fx.cu->execute_instruction(inst, *fx.wf); std::array out{}; @@ -344,7 +345,7 @@ TEST(Vop3CvtPkF32RdnaCorrectness, NormI16_SignedMarker) { uint32_t words[4] = {0u, 0u, 0u, 0u}; rdna3_vop3_encode(kOpCvtPkNormI16F32, kDstVgpr, 256, 257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); ASSERT_NE(inst, nullptr); fx.cu->execute_instruction(inst, *fx.wf); const uint32_t lane0 = fx.cu->read_vgpr(vb + kDstVgpr, 0); diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_div_helpers_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_div_helpers_simd_correctness_test.cpp index 7e758dd888e0..9213b25380df 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_div_helpers_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_div_helpers_simd_correctness_test.cpp @@ -23,6 +23,7 @@ /// FMA quiets a different NaN operand vs scalar std::fma — accepted /// divergence shared with the rest of the ternary fp suite). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -208,7 +209,7 @@ void check_div_fixup_f32(uint64_t exec) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(opcode, /*vdst=*/kDstVgpr32, /*src0=*/256, /*src1=*/257, /*src2=*/258, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << name << " decode failed"; auto out = fx.run32(inst, 0, r1, r2, exec, /*vcc=*/0); delete inst; @@ -249,7 +250,7 @@ std::array run_div_fixup_f16_opsel(bool force_scalar, uint32_ uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(opcode, /*vdst=*/kDstVgpr32, /*src0=*/256, /*src1=*/257, /*src2=*/258, words, op_sel); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_div_fixup_f16-family decode failed"; const uint32_t vb = fx.wf->vgpr_alloc().base; @@ -283,7 +284,7 @@ void check_div_fixup_f64(uint64_t exec) { // src2=v4:v5; vdst = kDstVgpr64:kDstVgpr64+1. vop3_tern_encode(/*op=*/479, /*vdst=*/kDstVgpr64, /*src0=*/256, /*src1=*/258, /*src2=*/260, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_div_fixup_f64_vop3 decode failed"; auto out = fx.run64(inst, 0, r1, r2, exec, /*vcc=*/0); delete inst; @@ -320,7 +321,7 @@ std::array run_div_fixup_f32_nan_precedence(bool force_scalar EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(opcode, /*vdst=*/kDstVgpr32, /*src0=*/256, /*src1=*/257, /*src2=*/258, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_div_fixup_f32-family decode failed"; constexpr uint32_t kP = 0x3F800000u; @@ -352,7 +353,7 @@ std::array run_div_fixup_f64_nan_precedence(bool force_scalar uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(/*op=*/479, /*vdst=*/kDstVgpr64, /*src0=*/256, /*src1=*/258, /*src2=*/260, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_div_fixup_f64_vop3 decode failed"; constexpr uint64_t kP = 0x3FF0000000000000ULL; @@ -394,7 +395,7 @@ void check_div_fmas_f32(uint64_t exec) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(/*op=*/482, /*vdst=*/kDstVgpr32, /*src0=*/256, /*src1=*/257, /*src2=*/258, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_div_fmas_f32_vop3 decode failed"; auto out = fx.run32(inst, 0, r1, 2 * r1, exec, vcc); delete inst; @@ -438,7 +439,7 @@ void check_div_fmas_f64(uint64_t exec) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(/*op=*/483, /*vdst=*/kDstVgpr64, /*src0=*/256, /*src1=*/258, /*src2=*/260, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_div_fmas_f64_vop3 decode failed"; auto out = fx.run64(inst, 0, r1, 2 * r1, exec, vcc); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_fmac_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_fmac_simd_correctness_test.cpp index 221ad2a3814a..0ee49608c4d3 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_fmac_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_fmac_simd_correctness_test.cpp @@ -19,6 +19,7 @@ /// These ops are NOT benched: looping the same instruction creates a loop- /// carried RAW dep on the accumulator that serializes both modes to ~1x. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -225,7 +226,7 @@ void check_case(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32 uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kAccVgpr, /*src0=*/256, /*src1=*/256 + src1_v, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c.kind, rot, exec); delete inst; @@ -292,7 +293,7 @@ TEST(Vop3FmacSimdCorrectness, VMacF16LowDstZeroesHighHalf) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(/*op=*/291, /*vdst=*/kAccVgpr, /*src0=*/256, /*src1=*/257, /*abs=*/0, /*neg=*/0, /*omod=*/0, /*clamp=*/0, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_mac_f16_vop3 decode failed"; auto out = fx.run(inst, Kind::F16, /*rot=*/0, /*exec=*/~0ULL); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_transcendental_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_transcendental_simd_correctness_test.cpp index a4d7b1142291..7c69159aa542 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_transcendental_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_transcendental_simd_correctness_test.cpp @@ -16,6 +16,7 @@ /// comparison — NaN-ness is deterministic from the inputs, so both runs skip the /// same lanes. In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -152,7 +153,7 @@ void check_case(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32 EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, exec, lane_input); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_unary_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_unary_simd_correctness_test.cpp index a9d612068b71..e645949ce015 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_unary_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_fp16_unary_simd_correctness_test.cpp @@ -16,6 +16,7 @@ /// so both runs skip the same lanes. In-process inactive lanes must keep the /// sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -150,7 +151,7 @@ void check_case(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32 EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_fp64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_fp64_simd_correctness_test.cpp index 6745672a2731..28bc30720536 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_fp64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_fp64_simd_correctness_test.cpp @@ -16,6 +16,7 @@ /// from the comparison so both runs skip the same lanes. In-process inactive /// lanes must stay preserved. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -165,7 +166,7 @@ void check_case(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32 uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/258, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_int_binary_extra_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_int_binary_extra_simd_correctness_test.cpp index ddec98c1b3f4..eba93b542988 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_int_binary_extra_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_int_binary_extra_simd_correctness_test.cpp @@ -13,6 +13,7 @@ /// equal with EXPECT_EQ (util::set_force_scalar_for_testing flips the gate /// in-process). In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -145,7 +146,7 @@ void check_case(const Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_bin_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_int_widening_ternary_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_int_widening_ternary_simd_correctness_test.cpp index df778131ac36..eb399a4236ef 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_int_widening_ternary_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_int_widening_ternary_simd_correctness_test.cpp @@ -15,6 +15,7 @@ /// equal with EXPECT_EQ (util::set_force_scalar_for_testing flips the gate /// in-process). In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -150,7 +151,7 @@ void check_case(const Case &c, uint64_t exec) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/(c.ternary ? 258u : 0u), words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; @@ -199,7 +200,7 @@ void check_mad_u32_u16_opsel_high_halves(uint64_t exec) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(/*op=*/497, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/258, words, kOpSelSrc0Src1High); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_mad_u32_u16_vop3 decode failed"; fx.cu->execute_instruction(inst, *fx.wf); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_ldexp_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_ldexp_simd_correctness_test.cpp index 35ca1b8acd92..eaf160723b01 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_ldexp_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_ldexp_simd_correctness_test.cpp @@ -11,6 +11,7 @@ /// identical inputs/EXEC -- and the result arrays are asserted equal with /// EXPECT_EQ (util::set_force_scalar_for_testing flips the gate in-process). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -165,7 +166,7 @@ void check_case(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32 uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/4, /*src0=*/256, /*src1=*/256 + src1_v, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c.f64, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_scalar_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_scalar_correctness_test.cpp index b1090694c344..23d25a7b66ce 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_scalar_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_scalar_correctness_test.cpp @@ -25,6 +25,7 @@ /// low-word-only read or a high-word-dropping write is visible. No SIMD is /// involved; this exercises the plain decode+execute scalar path. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -105,7 +106,7 @@ struct Fixture { } wf->set_exec(~0ULL); uint32_t words[4] = {w.w0, w.w1, 0u, 0u}; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); ASSERT_NE(inst, nullptr) << "decode failed for " << expect_mnemonic; EXPECT_EQ(inst->mnemonic(), expect_mnemonic) << "decoded wrong op"; cu->execute_instruction(inst, *wf); diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_simd_correctness_test.cpp index 1a6526b971ff..c5bc04c3d37b 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_shift64_simd_correctness_test.cpp @@ -15,6 +15,7 @@ /// The wide MAD cases also compare the explicit SGPR-pair carry/overflow mask. /// In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -151,7 +152,7 @@ void check_revshift(const char *name, uint32_t op, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[2] = {0u, 0u}; vop3_encode(op, kDstVgpr, /*src0=*/256, /*src1=*/258, /*src2=*/0, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << name << " decode failed"; uint32_t vb = fx.wf->vgpr_alloc().base; for (uint32_t lane = 0; lane < WF_SIZE; ++lane) { @@ -187,7 +188,7 @@ void check_lshl_add(uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[2] = {0u, 0u}; vop3_encode(/*op=*/520, kDstVgpr, /*src0=*/256, /*src1=*/258, /*src2=*/260, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_lshl_add_u64 decode failed"; uint32_t vb = fx.wf->vgpr_alloc().base; for (uint32_t lane = 0; lane < WF_SIZE; ++lane) { @@ -269,7 +270,7 @@ void check_mad64(const char *name, uint32_t op, bool is_signed, uint64_t exec) { EXPECT_EQ(sb % 2u, 0u) << name << ": sgpr_alloc base not pair-aligned"; uint32_t words[2] = {0u, 0u}; vop3_sdstenc_encode(op, kDstVgpr, sb, /*src0=*/256, /*src1=*/258, /*src2=*/260, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << name << " decode failed"; uint32_t vb = fx.wf->vgpr_alloc().base; for (uint32_t lane = 0; lane < WF_SIZE; ++lane) { diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_fp_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_fp_simd_correctness_test.cpp index ec2c9845a7cc..a8775cef8771 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_fp_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_fp_simd_correctness_test.cpp @@ -19,6 +19,7 @@ /// initialize src0+src1+vdst (the third FMA arg comes from vdst, no src2 /// member), so they need a separate accumulate-form glue path. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -244,7 +245,7 @@ void check_case(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32 uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, vdst, /*src0=*/256, /*src1=*/256 + src1_v, /*src2=*/256 + src2_v, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c.kind, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_int_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_int_simd_correctness_test.cpp index 56c75fbecc2e..bdcd4468adc9 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_int_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_ternary_int_simd_correctness_test.cpp @@ -12,6 +12,7 @@ /// with EXPECT_EQ (util::set_force_scalar_for_testing flips the gate in-process). /// In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -169,7 +170,7 @@ void check_case(const Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_tern_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/258, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_unary_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_unary_simd_correctness_test.cpp index 1fbd2a926a48..3edc00b32a2f 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_unary_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_unary_simd_correctness_test.cpp @@ -13,6 +13,7 @@ /// (util::set_force_scalar_for_testing flips the gate in-process). In-process /// inactive lanes must stay preserved under full/partial EXEC. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -180,7 +181,7 @@ void check(const Case &c, uint32_t abs, uint32_t neg, uint32_t omod, uint32_t cl EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kDstVgpr, /*src0=*/256, abs, neg, omod, clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, c.kind, exec); delete inst; @@ -276,7 +277,7 @@ TEST(Vop3UnarySimdCorrectness, MovB32_PreservesBits) { uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(/*op=v_mov_b32=*/321, /*vdst=*/kDstVgpr, /*src0=*/256, s.abs, s.neg, s.omod, s.clamp, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); ASSERT_NE(inst, nullptr); uint32_t vb = fx.wf->vgpr_alloc().base; for (uint32_t lane = 0; lane < WF_SIZE; ++lane) diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3p_dot_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3p_dot_simd_correctness_test.cpp index 6687de225b12..64dfde70bb85 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3p_dot_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3p_dot_simd_correctness_test.cpp @@ -25,6 +25,7 @@ /// payload divergence, same carve-out as the pk_fma slices). Default packing /// (op_sel = 0, op_sel_hi = 3) only — non-default modes bail to scalar. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -135,7 +136,7 @@ void check_int_case(const IntCase &c, uint64_t exec, uint32_t clamp) { uint32_t words[2] = {0u, 0u}; vop3p_encode_dot(c.opcode, kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/258, /*neg=*/0, /*neg_hi=*/0, clamp, words); - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; uint32_t vb = wf->vgpr_alloc().base; @@ -245,7 +246,7 @@ void check_f16_case(uint64_t exec, uint32_t neg, uint32_t neg_hi, uint32_t clamp uint32_t words[2] = {0u, 0u}; vop3p_encode_dot(/*op=*/35, kDstVgpr, /*src0=*/256, /*src1=*/257, /*src2=*/258, neg, neg_hi, clamp, words); - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); EXPECT_NE(inst, nullptr) << "v_dot2_f32_f16 decode failed"; uint32_t vb = wf->vgpr_alloc().base; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3p_fma_mix_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3p_fma_mix_simd_correctness_test.cpp index 79899b731932..2d3405fa020c 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3p_fma_mix_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3p_fma_mix_simd_correctness_test.cpp @@ -33,6 +33,7 @@ /// different payloads (accepted divergence, mirroring the existing VOP3 /// ternary tests). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -351,7 +352,7 @@ void check_combo(uint32_t opcode, const ModCombo &mc, uint64_t exec, uint32_t ds vop3p_encode_cdna4(opcode, kDstVgpr, /*neg_hi=*/mc.abs, mc.op_sel, mc.op_sel_hi_2, mc.clamp, /*src0=*/256, /*src1=*/257, /*src2=*/258, mc.op_sel_hi, mc.neg, words); } - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << label << " decode failed"; auto out = fx.run(inst, rot, widen0, widen1, widen2, exec, dst_seed); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3p_mov_b32_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3p_mov_b32_simd_correctness_test.cpp index 35ed79d0733a..6fdda89b0eee 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3p_mov_b32_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3p_mov_b32_simd_correctness_test.cpp @@ -12,6 +12,7 @@ /// mixed SGPR-pair/VGPR-pair case covers the legal scalar source encoding. /// In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -213,7 +214,7 @@ void check(uint64_t exec) { uint32_t words[2] = {0u, 0u}; // src0 = VGPR 256 (pair v0:v1), src1 = VGPR 258 (pair v2:v3). vop3p_encode(/*op=*/51, kDstVgpr, /*src0=*/256, /*src1=*/258, op_sel, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "v_pk_mov_b32_vop3p decode failed"; auto out = force_scalar ? fx.run(inst, rot, exec) : fx.run_simd_probe(inst, arch, rot, exec, op_sel); @@ -287,7 +288,7 @@ TEST(Vop3pMovB32SimdCorrectness, ProductionSimdDispatchGolden) { ASSERT_NE(fx.wf, nullptr); uint32_t words[2] = {0u, 0u}; vop3p_encode(/*op=*/51, kDstVgpr, /*src0=*/256, /*src1=*/258, kOpSel, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); ASSERT_NE(inst, nullptr) << arch.name << " v_pk_mov_b32_vop3p decode failed"; const auto out = fx.run(inst, kRot, kExec); delete inst; @@ -324,7 +325,7 @@ TEST(Vop3pMovB32SimdCorrectness, MixedSgprPairAndVgprPairGolden) { EXPECT_NE(fx.wf, nullptr); uint32_t words[2] = {0u, 0u}; vop3p_encode(/*op=*/51, kDstVgpr, test_case.src0, test_case.src1, test_case.op_sel, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << arch.name << " " << test_case.name << " v_pk_mov_b32_vop3p decode failed"; auto out = force_scalar diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_fp16_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_fp16_simd_correctness_test.cpp index b93dbd6a42a7..5eeb26fb2f21 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_fp16_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_fp16_simd_correctness_test.cpp @@ -18,6 +18,7 @@ /// computed from the inputs, identical in both runs, so both skip the same /// lanes. In-process inactive lanes must keep the sentinel. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -181,7 +182,7 @@ void check_case(const Case &c, uint64_t exec, uint32_t neg, uint32_t neg_hi) { neg, words); else vop3p_encode_binary(c.opcode, kDstVgpr, neg_hi, /*src0=*/256, /*src1=*/257, neg, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_int_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_int_simd_correctness_test.cpp index 6ab2c75c69f5..6163e7133966 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_int_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3p_pk_binary_int_simd_correctness_test.cpp @@ -21,6 +21,7 @@ /// shift-saturation, and identical-pair cases on both halves /// independently. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -172,7 +173,7 @@ void check_case(const Case &c, uint64_t exec) { words); else vop3p_encode_default_binary(c.opcode, kDstVgpr, /*src0=*/256, /*src1=*/257, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; auto out = fx.run(inst, rot, exec); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop_alias_rdna_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop_alias_rdna_simd_correctness_test.cpp index 41d2f62c9f59..08a774e840ec 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop_alias_rdna_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop_alias_rdna_simd_correctness_test.cpp @@ -26,6 +26,7 @@ /// modifiers — verified inline in the regen for this slice) + 2 ints /// missing from CDNA4 (v_minmax / v_maxmin u32/i32 are RDNA3+ only). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -226,7 +227,7 @@ void check_case(const VopCase &c, uint64_t exec) { vop3_encode(c.opcode, kDstVgpr, SRC0_VGPR, SRC1_VGPR, SRC2_VGPR, words); break; } - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << ": decode failed"; auto out = fx.run(inst, rot, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_scalar_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_scalar_correctness_test.cpp index 9077a4c8966e..639c7fa17187 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_scalar_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_scalar_correctness_test.cpp @@ -16,6 +16,7 @@ /// either direction is caught. f64 patterns all have a nonzero high word, so a /// low-word-only read or f32-precision classify fails the +normal/-normal rows. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" #include "rocjitsu/isa/instruction.h" @@ -83,7 +84,7 @@ struct Fixture { cu->write_vgpr(vb + 2, 0, mask); uint32_t enc = vopc_encode(op, /*src0=*/256, /*vsrc1=*/2); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = decoder->decode(words); + Instruction *inst = decode_valid(*decoder, words); EXPECT_NE(inst, nullptr); cu->execute_instruction(inst, *wf); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_simd_correctness_test.cpp index db8e0709c043..230f58e5cd0f 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_cmp_class_simd_correctness_test.cpp @@ -18,6 +18,7 @@ /// outcomes for every input incl. NaN payload), so the compare is bit-exact with /// no carve-out. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -221,7 +222,7 @@ void check_all(uint64_t exec) { uint32_t vsrc1 = (c.kind == Kind::F64) ? 2u : 1u; // f64 src0 spans v0:v1 uint32_t enc = vopc_encode(c.opcode, /*src0=*/256, vsrc1); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; uint64_t vcc = fx.run(inst, c.kind, rot, exec, vcc_in); delete inst; @@ -273,7 +274,7 @@ void check_all_vop3(uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_encode(c.opcode, /*vdst=*/kVccSdst, /*src0=*/256, src1, abs, neg, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; uint64_t vcc = fx.run(inst, c.kind, rot, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_simd_correctness_test.cpp index d9d6c15625a4..7199372b9b7b 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_simd_correctness_test.cpp @@ -15,6 +15,7 @@ /// split lo/hi VGPR-pair read path. Inputs seed NaN/±Inf/±0/denorm (floats) and /// signed/extreme boundaries (ints); float compares are bit-exact in both modes. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -180,7 +181,7 @@ void check_all(uint64_t exec) { uint32_t vsrc1 = is_64bit(c.kind) ? 2u : 1u; uint32_t enc = vopc_encode(c.opcode, /*src0=*/256, vsrc1); uint32_t words[4] = {enc, 0u, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << "VOPC opcode " << c.opcode << " decode failed"; uint64_t vcc = fx.run(inst, c.kind, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp16_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp16_simd_correctness_test.cpp index 592ed5b6743f..0d772227d9e2 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp16_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp16_simd_correctness_test.cpp @@ -14,6 +14,7 @@ /// EXPECT_EQ (util::set_force_scalar_for_testing flips the gate in-process). /// In-process inactive SGPR-pair bits must be zeroed. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -149,7 +150,7 @@ void check_case(const Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_cmp_encode(c.opcode, /*vdst=*/kVccSdst, /*src0=*/256, /*src1=*/257, abs, neg, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed (abs=" << abs << " neg=" << neg << ")"; uint64_t vcc = fx.run(inst, rot, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp32_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp32_simd_correctness_test.cpp index aec26bd36b02..ed34b9c1ea8a 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp32_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp32_simd_correctness_test.cpp @@ -14,6 +14,7 @@ /// equal with EXPECT_EQ (util::set_force_scalar_for_testing flips the gate /// in-process). In-process inactive SGPR-pair bits must be zeroed. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -157,7 +158,7 @@ void check_case(const Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_cmp_encode(c.opcode, /*vdst=*/kVccSdst, /*src0=*/256, /*src1=*/257, abs, neg, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed (abs=" << abs << " neg=" << neg << ")"; uint64_t vcc = fx.run(inst, rot, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp64_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp64_simd_correctness_test.cpp index 15ecf16908f0..440806752b54 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp64_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_fp64_simd_correctness_test.cpp @@ -14,6 +14,7 @@ /// EXPECT_EQ (util::set_force_scalar_for_testing flips the gate in-process). /// In-process inactive SGPR-pair bits must be zeroed. +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -154,7 +155,7 @@ void check_case(const Case &c, uint64_t exec) { EXPECT_NE(fx.wf, nullptr); uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_cmp_encode(c.opcode, /*vdst=*/kVccSdst, /*src0=*/256, /*src1=*/258, abs, neg, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed (abs=" << abs << " neg=" << neg << ")"; uint64_t vcc = fx.run(inst, rot, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_int_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_int_simd_correctness_test.cpp index a4de587a0644..5cb80150cc1d 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_int_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vopc_vop3_int_simd_correctness_test.cpp @@ -19,6 +19,7 @@ /// over the test loop so eq/lt/gt/le/ge/ne all fire on real boundary cases (incl. /// signed-negative vs unsigned wrap). +#include "decode_test_util.h" #include "util/simd_test_hooks.h" #include "rocjitsu/code/rj_code.h" @@ -232,7 +233,7 @@ void check_case(const Case &c, uint64_t exec) { const uint32_t src1_vgpr = (c.width == Width::B64) ? 2u : 2u; // v2:v3 / v2 uint32_t words[4] = {0u, 0u, 0u, 0u}; vop3_cmp_encode(c.opcode, /*vdst=*/kVccSdst, /*src0=*/256u, /*src1=*/256u + src1_vgpr, words); - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); EXPECT_NE(inst, nullptr) << c.name << " decode failed"; uint64_t vcc = fx.run(inst, c.width, rot, exec, vcc_in); delete inst; diff --git a/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp b/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp index d918981faf8c..6447f9074268 100644 --- a/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp +++ b/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp @@ -26,6 +26,7 @@ /// - s_store_dwordx2: store family, where sdata is also a source so SBASE is /// not the first source operand. +#include "decode_test_util.h" #include "rocjitsu/analysis/def_use_chain.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/decoder.h" @@ -94,7 +95,7 @@ TEST_P(SmemSbaseOperandTest, SbaseResolvesToScaledSgpr) { auto decoder = Decoder::create(tc.arch); ASSERT_NE(decoder, nullptr) << "Decoder::create() failed for " << tc.label; - std::unique_ptr inst(decoder->decode(tc.word.data())); + std::unique_ptr inst(decode_valid(*decoder, tc.word.data())); ASSERT_NE(inst, nullptr) << "decode() returned nullptr for " << tc.label; ASSERT_EQ(inst->mnemonic(), tc.mnemonic) << "unexpected mnemonic for " << tc.label; diff --git a/emulation/rocjitsu/tests/util_result_test.cpp b/emulation/rocjitsu/tests/util_result_test.cpp index e240c1aa3412..0cc028401b6a 100644 --- a/emulation/rocjitsu/tests/util_result_test.cpp +++ b/emulation/rocjitsu/tests/util_result_test.cpp @@ -135,6 +135,17 @@ TEST(FailureOrTest, RepresentsValueOrFailureWithoutThrowing) { static_assert(std::is_same_v, IntResult>); } +TEST(FailureOrTest, DeducesValueType) { + constexpr auto int_result = util::FailureOr(42); + auto pointer_result = util::FailureOr(std::make_unique(42)); + + static_assert(std::is_same_v, util::FailureOr>); + static_assert(std::is_same_v>>); + static_assert(int_result.succeeded() && int_result.value() == 42); + ASSERT_TRUE(pointer_result.succeeded()); + EXPECT_EQ(*pointer_result.value(), 42); +} + TEST(FailureOrTest, RejectsSuccessfulResult) { EXPECT_DEBUG_DEATH( { [[maybe_unused]] util::FailureOr result(util::Result::success()); }, ""); diff --git a/emulation/rocjitsu/tests/v_add_simd_benchmark.cpp b/emulation/rocjitsu/tests/v_add_simd_benchmark.cpp index 8a19b2aec846..81fecb2abd6d 100644 --- a/emulation/rocjitsu/tests/v_add_simd_benchmark.cpp +++ b/emulation/rocjitsu/tests/v_add_simd_benchmark.cpp @@ -9,6 +9,7 @@ /// then unset (SIMD). Scalar-vs-SIMD bit-equivalence is verified separately by /// the *SimdCorrectness* suites (in-process double-run + EXPECT_EQ), not here. +#include "decode_test_util.h" #include "rocjitsu/code/rj_code.h" #include "rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h" #include "rocjitsu/isa/decoder.h" @@ -189,7 +190,7 @@ void run_words(const char *label, uint32_t w0, uint32_t w1, bool sanitize_finite ASSERT_NE(fx.wf, nullptr); uint32_t words[4] = {w0, w1, 0u, 0u}; - Instruction *inst = fx.decoder->decode(words); + Instruction *inst = decode_valid(*fx.decoder, words); ASSERT_NE(inst, nullptr) << label << ": decode failed"; constexpr uint64_t SEED = 0xC0FFEE'1234'5678ULL; diff --git a/emulation/rocjitsu/tests/vector_add_test.cpp b/emulation/rocjitsu/tests/vector_add_test.cpp index a4298250f479..6cfbab03f192 100644 --- a/emulation/rocjitsu/tests/vector_add_test.cpp +++ b/emulation/rocjitsu/tests/vector_add_test.cpp @@ -9,6 +9,7 @@ /// CPU golden reference. #include "aql_queue.h" +#include "decode_test_util.h" #include "test_paths.h" #include "embedded_schema.h" @@ -216,7 +217,7 @@ TEST(VectorAddCodeObjectTest, LoadsAndDecodes) { auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); const auto *text = co->text_sections()[0]; const auto *data = reinterpret_cast(text->data()); - std::unique_ptr inst(decoder->decode(data)); + std::unique_ptr inst(decode_valid(*decoder, data)); EXPECT_NE(inst, nullptr) << "Failed to decode first instruction"; } diff --git a/emulation/rocjitsu/tools/CMakeLists.txt b/emulation/rocjitsu/tools/CMakeLists.txt index d63b1ec08b91..8fbc04636edc 100644 --- a/emulation/rocjitsu/tools/CMakeLists.txt +++ b/emulation/rocjitsu/tools/CMakeLists.txt @@ -33,6 +33,13 @@ add_executable(rj_dbt_translate rj_dbt_translate_main.cpp) target_link_libraries(rj_dbt_translate PRIVATE rocjitsu_translate_cli) rj_configure_target(rj_dbt_translate TOOL) +add_executable(rj_decode_benchmark rj_decode_benchmark.cpp) +target_link_libraries( + rj_decode_benchmark + PRIVATE ${RJ_TOOL_OBJECT_LIBS} util flatbuffers Threads::Threads +) +rj_configure_target(rj_decode_benchmark TOOL) + # Ahead-of-time population of the shared translation tier. # # Deliberately narrow: the fixed-profile translator, the store, and nothing else diff --git a/emulation/rocjitsu/tools/dbt_translate.cpp b/emulation/rocjitsu/tools/dbt_translate.cpp index ea4e9287a25d..a1de9e73be7a 100644 --- a/emulation/rocjitsu/tools/dbt_translate.cpp +++ b/emulation/rocjitsu/tools/dbt_translate.cpp @@ -95,17 +95,19 @@ void record_decode_failure(CodeSectionReport §ion_report, size_t byte_offset continue; } try { - std::unique_ptr inst(decoder->decode(&words[pc])); - if (!inst) { - record_decode_failure(section_report, pc * sizeof(uint32_t), "decode returned null"); + util::StringDiagnostic decode_error; + DecodeResult decoded = decoder->decode(&words[pc], decode_error.emitter()); + if (decoded.failed()) { + record_decode_failure(section_report, pc * sizeof(uint32_t), decode_error.message()); if (include_disassembly) { os << " 0x" << std::hex << std::setw(4) << std::setfill('0') << pc * 4 - << ": \n" + << ": \n" << std::dec << std::setfill(' '); } ++pc; continue; } + std::unique_ptr inst = std::move(decoded).value(); const uint32_t inst_words = inst->size() / sizeof(uint32_t); ++section_report.instruction_count; @@ -317,14 +319,11 @@ collect_executable_sections(const AmdGpuCodeObject &object) { return ""; const auto *words = reinterpret_cast(text->data()); - try { - std::unique_ptr inst(decoder->decode(&words[offset / sizeof(uint32_t)])); - if (!inst) - return ""; - return inst->disassemble(); - } catch (const std::exception &e) { - return std::string(""; - } + util::StringDiagnostic decode_error; + DecodeResult decoded = decoder->decode(&words[offset / sizeof(uint32_t)], decode_error.emitter()); + if (decoded.failed()) + return std::string(""; + return decoded.value()->disassemble(); } [[nodiscard]] std::vector disassemble_words(std::span words, @@ -338,21 +337,18 @@ collect_executable_sections(const AmdGpuCodeObject &object) { size_t pc = 0; while (pc < words.size()) { - try { - std::unique_ptr inst(decoder->decode(&words[pc])); - if (!inst) { - lines.push_back(""); - ++pc; - continue; - } - - lines.push_back(inst->disassemble()); - const uint32_t inst_words = inst->size() / sizeof(uint32_t); - pc += inst_words == 0 ? 1 : inst_words; - } catch (const std::exception &e) { - lines.push_back(std::string(""); + util::StringDiagnostic decode_error; + DecodeResult decoded = decoder->decode(&words[pc], decode_error.emitter()); + if (decoded.failed()) { + lines.push_back(std::string(""); ++pc; + continue; } + + const std::unique_ptr &inst = decoded.value(); + lines.push_back(inst->disassemble()); + const uint32_t inst_words = inst->size() / sizeof(uint32_t); + pc += inst_words == 0 ? 1 : inst_words; } return lines; diff --git a/emulation/rocjitsu/tools/rj_decode_benchmark.cpp b/emulation/rocjitsu/tools/rj_decode_benchmark.cpp new file mode 100644 index 000000000000..d642eef7b21a --- /dev/null +++ b/emulation/rocjitsu/tools/rj_decode_benchmark.cpp @@ -0,0 +1,310 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file rj_decode_benchmark.cpp +/// @brief Measure decoder throughput over the text of a real code object. + +#include "rocjitsu/code/amdgpu_code_object.h" +#include "rocjitsu/isa/decoder.h" +#include "rocjitsu/isa/instruction.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace { + +using namespace rocjitsu; +using Clock = std::chrono::steady_clock; + +constexpr std::size_t kLookaheadWords = 4; +constexpr std::size_t kDefaultInvalidLimit = 65536; + +struct TextRange { + std::size_t begin; + std::size_t word_count; +}; + +struct DecodeCorpus { + std::vector words; + std::vector ranges; + std::vector valid_offsets; + std::vector> invalid_encodings; + std::size_t text_bytes = 0; + std::size_t scan_rejections = 0; +}; + +struct Options { + std::string input; + std::optional arch; + std::size_t iterations = 1; + std::size_t invalid_limit = kDefaultInvalidLimit; +}; + +struct Measurement { + std::size_t attempts = 0; + std::size_t unexpected = 0; + uint64_t checksum = 0; + std::chrono::nanoseconds elapsed{}; +}; + +void print_usage(std::ostream &os) { + os << "Usage: rj_decode_benchmark INPUT [--target TARGET] [--iterations N] " + "[--invalid-limit N]\n" + "Targets: gfx942, gfx950, gfx1200, gfx1201, gfx1250\n"; +} + +[[nodiscard]] std::optional parse_target(std::string_view value) { + if (value == "gfx942") + return ROCJITSU_CODE_ARCH_CDNA3; + if (value == "gfx950") + return ROCJITSU_CODE_ARCH_CDNA4; + if (value == "gfx1200" || value == "gfx1201") + return ROCJITSU_CODE_ARCH_RDNA4; + if (value == "gfx1250") + return ROCJITSU_CODE_ARCH_GFX1250; + return std::nullopt; +} + +[[nodiscard]] std::optional arch_for_target(rj_code_target_id_t target) { + switch (target) { + case ROCJITSU_CODE_TARGET_GFX942: + return ROCJITSU_CODE_ARCH_CDNA3; + case ROCJITSU_CODE_TARGET_GFX950: + return ROCJITSU_CODE_ARCH_CDNA4; + case ROCJITSU_CODE_TARGET_GFX1200: + case ROCJITSU_CODE_TARGET_GFX1201: + return ROCJITSU_CODE_ARCH_RDNA4; + case ROCJITSU_CODE_TARGET_GFX1250: + return ROCJITSU_CODE_ARCH_GFX1250; + default: + return std::nullopt; + } +} + +[[nodiscard]] bool parse_size(std::string_view text, std::size_t &value) { + auto [ptr, error] = std::from_chars(text.data(), text.data() + text.size(), value); + return error == std::errc{} && ptr == text.data() + text.size(); +} + +[[nodiscard]] std::optional parse_options(int argc, char **argv) { + Options options; + for (int index = 1; index < argc; ++index) { + const std::string_view arg(argv[index]); + if (arg == "--help") { + print_usage(std::cout); + return std::nullopt; + } + if (arg == "--target" && index + 1 < argc) { + options.arch = parse_target(argv[++index]); + if (!options.arch) { + std::cerr << "Unsupported target: " << argv[index] << '\n'; + return std::nullopt; + } + continue; + } + if (arg == "--iterations" && index + 1 < argc) { + if (!parse_size(argv[++index], options.iterations) || options.iterations == 0) { + std::cerr << "Iterations must be a positive integer\n"; + return std::nullopt; + } + continue; + } + if (arg == "--invalid-limit" && index + 1 < argc) { + if (!parse_size(argv[++index], options.invalid_limit)) { + std::cerr << "Invalid limit must be a non-negative integer\n"; + return std::nullopt; + } + continue; + } + if (!arg.starts_with("--") && options.input.empty()) { + options.input = arg; + continue; + } + std::cerr << "Unexpected argument: " << arg << '\n'; + return std::nullopt; + } + if (options.input.empty()) { + print_usage(std::cerr); + return std::nullopt; + } + return options; +} + +void copy_encoding(std::span words, std::size_t offset, + std::array ©) { + copy.fill(0); + const std::size_t available = std::min(copy.size(), words.size() - offset); + std::copy_n(words.begin() + static_cast(offset), available, copy.begin()); +} + +[[nodiscard]] bool collect_corpus(const AmdGpuCodeObject &object, Decoder &decoder, + std::size_t invalid_limit, DecodeCorpus &corpus, + std::string &error) { + for (const Section *section : object.text_sections()) { + const std::size_t word_count = section->size() / sizeof(uint32_t); + const std::size_t begin = corpus.words.size(); + corpus.words.resize(begin + word_count + kLookaheadWords, 0); + std::memcpy(corpus.words.data() + begin, section->data(), word_count * sizeof(uint32_t)); + corpus.ranges.push_back({begin, word_count}); + corpus.text_bytes += word_count * sizeof(uint32_t); + } + + for (const TextRange range : corpus.ranges) { + std::size_t relative_offset = 0; + while (relative_offset < range.word_count) { + const std::size_t offset = range.begin + relative_offset; + DecodeResult decoded = decoder.decode(corpus.words.data() + offset); + if (decoded.failed()) { + ++corpus.scan_rejections; + if (corpus.invalid_encodings.size() < invalid_limit) { + std::array encoding; + copy_encoding(corpus.words, offset, encoding); + corpus.invalid_encodings.push_back(encoding); + } + ++relative_offset; + continue; + } + + const std::size_t byte_size = decoded.value()->size(); + if (byte_size == 0 || byte_size % sizeof(uint32_t) != 0) { + error = "decoder returned an invalid instruction size"; + return false; + } + const std::size_t instruction_words = byte_size / sizeof(uint32_t); + if (instruction_words > range.word_count - relative_offset) { + error = "decoded instruction crosses a text-section boundary"; + return false; + } + corpus.valid_offsets.push_back(offset); + relative_offset += instruction_words; + } + } + + static constexpr std::array kMutationMasks = {0xffffffffu, 0xff800000u, 0x007fffffu, + 0x9e3779b9u}; + for (std::size_t offset : corpus.valid_offsets) { + if (corpus.invalid_encodings.size() >= invalid_limit) + break; + std::array encoding; + copy_encoding(corpus.words, offset, encoding); + const uint32_t original = encoding[0]; + for (uint32_t mask : kMutationMasks) { + encoding[0] = original ^ mask; + if (decoder.decode(encoding.data()).failed()) { + corpus.invalid_encodings.push_back(encoding); + break; + } + } + } + return true; +} + +[[nodiscard]] Measurement measure_valid(const DecodeCorpus &corpus, Decoder &decoder, + std::size_t iterations) { + Measurement measurement; + measurement.attempts = corpus.valid_offsets.size() * iterations; + const auto start = Clock::now(); + for (std::size_t iteration = 0; iteration < iterations; ++iteration) { + for (std::size_t offset : corpus.valid_offsets) { + DecodeResult decoded = decoder.decode(corpus.words.data() + offset); + if (decoded.failed()) { + ++measurement.unexpected; + continue; + } + measurement.checksum += decoded.value()->size(); + } + } + measurement.elapsed = std::chrono::duration_cast(Clock::now() - start); + return measurement; +} + +[[nodiscard]] Measurement measure_invalid(const DecodeCorpus &corpus, Decoder &decoder, + std::size_t iterations) { + Measurement measurement; + measurement.attempts = corpus.invalid_encodings.size() * iterations; + const auto start = Clock::now(); + for (std::size_t iteration = 0; iteration < iterations; ++iteration) { + for (const auto &encoding : corpus.invalid_encodings) { + DecodeResult decoded = decoder.decode(encoding.data()); + if (decoded.succeeded()) { + ++measurement.unexpected; + measurement.checksum += decoded.value()->size(); + } + } + } + measurement.elapsed = std::chrono::duration_cast(Clock::now() - start); + return measurement; +} + +void print_measurement(std::string_view name, const Measurement &measurement) { + const double elapsed_ns = static_cast(measurement.elapsed.count()); + const double ns_per_attempt = measurement.attempts == 0 ? 0.0 : elapsed_ns / measurement.attempts; + const double mips = elapsed_ns == 0.0 ? 0.0 : measurement.attempts / (elapsed_ns / 1e9) / 1e6; + std::cout << name << ": " << measurement.attempts << " attempts, " << std::fixed + << std::setprecision(2) << ns_per_attempt << " ns/attempt, " << mips << " MIPS, " + << measurement.unexpected << " unexpected, checksum " << measurement.checksum << '\n'; +} + +} // namespace + +int main(int argc, char **argv) { + const std::optional options = parse_options(argc, argv); + if (!options) + return argc > 1 && std::string_view(argv[1]) == "--help" ? 0 : 1; + + try { + AmdGpuCodeObject object(options->input); + if (!object.is_valid()) { + std::cerr << "Failed to parse input code object\n"; + return 2; + } + const std::optional arch = + options->arch ? options->arch : arch_for_target(object.target_id()); + if (!arch) { + std::cerr << "Cannot infer decoder target; pass --target\n"; + return 2; + } + std::unique_ptr decoder = Decoder::create(*arch); + if (!decoder) { + std::cerr << "No decoder is available for the selected target\n"; + return 2; + } + + DecodeCorpus corpus; + std::string error; + if (!collect_corpus(object, *decoder, options->invalid_limit, corpus, error)) { + std::cerr << error << '\n'; + return 2; + } + if (corpus.valid_offsets.empty()) { + std::cerr << "No valid instruction encodings found in text sections\n"; + return 2; + } + + std::cout << "text: " << corpus.text_bytes << " bytes, " << corpus.valid_offsets.size() + << " valid instructions, " << corpus.scan_rejections << " rejected words, " + << corpus.invalid_encodings.size() << " invalid samples\n"; + const Measurement valid = measure_valid(corpus, *decoder, options->iterations); + print_measurement("valid", valid); + if (!corpus.invalid_encodings.empty()) { + const Measurement invalid = measure_invalid(corpus, *decoder, options->iterations); + print_measurement("invalid", invalid); + } + return valid.unexpected == 0 ? 0 : 3; + } catch (const std::exception &error) { + std::cerr << "Benchmark failed: " << error.what() << '\n'; + return 2; + } +} From 8cf750d23faefe1f34eae2773e4fbe1d356b00d6 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 18 Aug 2026 23:38:31 -0400 Subject: [PATCH 18/27] [rocjitsu] Dispatch operand validation by type (#10371) Generated operand constructors validated each encoding by walking every operand-type predicate. Operand construction is the largest decoder hot-path cost, and common operand types appeared late in that linear chain. Emit a switch over OperandType so construction evaluates only the matching selector ranges while preserving deferred diagnostics. Delegate the literal16 constructor to the primary constructor so each generated translation unit contains one validation switch, regenerate all ten AMDGPU models, and extend the generator profile gates for the shared structure. On the pinned large-object benchmark, median valid-decode throughput improves 25.1%, cycles fall 19.7%, and instructions fall 35.6% across nine alternating CPU-pinned pairs with identical corpus results and checksums. (cherry picked from commit f2e878694e885dca623160102630b642b097087b) --- .../lib/python/amdisa/codegen/_generator.py | 27 +- .../tests/test_generator_profile_gates.py | 66 ++-- .../arch/amdgpu/generated/cdna1/operand.cpp | 312 ++++++++---------- .../arch/amdgpu/generated/cdna2/operand.cpp | 282 +++++++--------- .../arch/amdgpu/generated/cdna3/operand.cpp | 282 +++++++--------- .../arch/amdgpu/generated/cdna4/operand.cpp | 290 +++++++--------- .../arch/amdgpu/generated/cdna5/operand.cpp | 267 +++++++-------- .../arch/amdgpu/generated/rdna1/operand.cpp | 300 ++++++++--------- .../arch/amdgpu/generated/rdna2/operand.cpp | 289 +++++++--------- .../arch/amdgpu/generated/rdna3/operand.cpp | 233 ++++++------- .../arch/amdgpu/generated/rdna3_5/operand.cpp | 233 ++++++------- .../arch/amdgpu/generated/rdna4/operand.cpp | 256 +++++++------- 12 files changed, 1270 insertions(+), 1567 deletions(-) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 16a7c6c6c9bb..f61092935625 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -11410,7 +11410,7 @@ def gen_operand(self) -> None: if uses_packed_16bit_sources else '' ) - selector_validation = '' + selector_validation_cases = [] for selector in sorted( self.isa_spec.opnd_selectors, key=lambda item: item.operand_type ): @@ -11438,11 +11438,19 @@ def gen_operand(self) -> None: f'(encoding_value >= {lo} && encoding_value <= {hi})' for lo, hi in intervals ) - selector_validation += ( - f' if (opr_type == OperandType::{operand_type} && ' - f'!({valid_expr}))\n' - f' defer_encoding_error(EncodingError::{error});\n' + selector_validation_cases.append( + f' case OperandType::{operand_type}:\n' + f' if (!({valid_expr}))\n' + f' defer_encoding_error(EncodingError::{error});\n' + f' break;\n' ) + selector_validation = ( + ' switch (opr_type) {\n' + + ''.join(selector_validation_cases) + + ' default:\n' + + ' break;\n' + + ' }\n' + ) packed_16bit_ctor_impl = [] if uses_packed_16bit_sources: packed_16bit_ctor_impl.append( @@ -11492,12 +11500,9 @@ def gen_operand(self) -> None: cgen.Line( 'Operand::Operand(int size_bits, OperandType opr_type, int encoding_value,\n' ' uint16_t literal16_display_value, bool has_literal16_display)\n' - f' : {operand_base_init}(size_bits, opr_type, encoding_value)' - f'{execution_backend_ctor_init},\n' - ' literal16_display_value_(literal16_display_value),\n' - ' has_literal16_display_(has_literal16_display) {\n' - f'{selector_validation}' - ' is_vgpr_ = is_vgpr_operand_type(opr_type);\n' + ' : Operand(size_bits, opr_type, encoding_value) {\n' + ' literal16_display_value_ = literal16_display_value;\n' + ' has_literal16_display_ = has_literal16_display;\n' '}' ), cgen.Line( diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index 6bc03367d018..fd8b7041b5d5 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -2173,8 +2173,8 @@ def test_generated_operand_validates_scalar_register_selector_intervals( (amdgpu_generated_root / arch / 'operand.cpp').read_text().split() ) assert ( - 'opr_type==OperandType::OPR_SREG&&' - '!((encoding_value>=0&&encoding_value<=123)||' + 'caseOperandType::OPR_SREG:' + 'if(!((encoding_value>=0&&encoding_value<=123)||' '(encoding_value>=125&&encoding_value<=125))' in operand ) assert ( @@ -2189,12 +2189,12 @@ def test_generated_operand_validates_scalar_register_selector_variants( gfx1250_operand = ''.join( (gfx1250_generated_root / 'operand.cpp').read_text().split() ) - assert 'opr_type==OperandType::OPR_SREG_M0&&' in gfx1250_operand + assert 'caseOperandType::OPR_SREG_M0:' in gfx1250_operand rdna4_operand = ''.join((rdna4_generated_root / 'operand.cpp').read_text().split()) assert ( - 'opr_type==OperandType::OPR_SREG_LITERAL&&' - '!((encoding_value>=0&&encoding_value<=124)||' + 'caseOperandType::OPR_SREG_LITERAL:' + 'if(!((encoding_value>=0&&encoding_value<=124)||' '(encoding_value>=255&&encoding_value<=255))' in rdna4_operand ) @@ -2207,13 +2207,13 @@ def test_generated_operand_validates_scalar_selector_families( ) assert ( - 'opr_type==OperandType::OPR_SDST&&' - '!((encoding_value>=0&&encoding_value<=124)||' + 'caseOperandType::OPR_SDST:' + 'if(!((encoding_value>=0&&encoding_value<=124)||' '(encoding_value>=126&&encoding_value<=127))' in operand ) assert ( - 'opr_type==OperandType::OPR_SSRC_NOLIT&&' - '!((encoding_value>=0&&encoding_value<=124)||' + 'caseOperandType::OPR_SSRC_NOLIT:' + 'if(!((encoding_value>=0&&encoding_value<=124)||' '(encoding_value>=126&&encoding_value<=208)||' '(encoding_value>=235&&encoding_value<=248)||' '(encoding_value>=251&&encoding_value<=253))' in operand @@ -2232,7 +2232,7 @@ def test_generated_operand_validates_barrier_id_selectors( (rdna4_generated_root, 194), ): operand = ''.join((root / 'operand.cpp').read_text().split()) - assert 'opr_type==OperandType::OPR_SSRC_BARRIER_ID&&' in operand + assert 'caseOperandType::OPR_SSRC_BARRIER_ID:' in operand assert '(encoding_value>=125&&encoding_value<=125)' in operand assert '(encoding_value>=128&&encoding_value<=159)' in operand assert f'(encoding_value>=193&&encoding_value<={negative_max})' in operand @@ -2261,9 +2261,9 @@ def test_generated_operand_validates_direct_selector_namespaces( gfx1250_operand = ''.join( (gfx1250_generated_root / 'operand.cpp').read_text().split() ) - assert 'opr_type==OperandType::OPR_SRC&&' in gfx1250_operand + assert 'caseOperandType::OPR_SRC:' in gfx1250_operand assert '(encoding_value>=209&&encoding_value<=229)' not in gfx1250_operand - assert 'opr_type==OperandType::OPR_SRC_VGPR_OR_INLINE&&' in gfx1250_operand + assert 'caseOperandType::OPR_SRC_VGPR_OR_INLINE:' in gfx1250_operand assert '(encoding_value>=128&&encoding_value<=208)' in gfx1250_operand assert '(encoding_value>=240&&encoding_value<=248)' in gfx1250_operand assert '(encoding_value>=256&&encoding_value<=511)' in gfx1250_operand @@ -2272,8 +2272,8 @@ def test_generated_operand_validates_direct_selector_namespaces( (amdgpu_generated_root / 'cdna1' / 'operand.cpp').read_text().split() ) assert ( - 'opr_type==OperandType::OPR_SMEM_OFFSET&&' - '!((encoding_value>=0&&encoding_value<=124))' in cdna1_operand + 'caseOperandType::OPR_SMEM_OFFSET:' + 'if(!((encoding_value>=0&&encoding_value<=124))' in cdna1_operand ) @@ -2324,7 +2324,7 @@ def test_gfx1250_generated_operand_validates_lane_selectors( assert 'OPR_SSRC_LANESEL_POS_INT_MAX = 191' in operand_types assert '#include "util/except.h"' not in operand - assert 'opr_type == OperandType::OPR_SSRC_LANESEL' in operand + assert 'case OperandType::OPR_SSRC_LANESEL:' in operand assert 'EncodingError::InvalidLaneSelector' in operand @@ -2333,7 +2333,7 @@ def test_gfx1250_generated_operand_rejects_invalid_exec_selector( ): operand = (gfx1250_generated_root / 'operand.cpp').read_text() assert '#include "util/except.h"' not in operand - assert 'opr_type == OperandType::OPR_EXEC' in operand + assert 'case OperandType::OPR_EXEC:' in operand assert '(encoding_value >= 126 && encoding_value <= 126)' in operand assert 'EncodingError::InvalidExecSelector' in operand @@ -3346,7 +3346,7 @@ def test_gfx1250_generated_operand_rejects_reserved_scalar_source_selectors( ): operand = (gfx1250_generated_root / 'operand.cpp').read_text() - assert 'opr_type == OperandType::OPR_SSRC' in operand + assert 'case OperandType::OPR_SSRC:' in operand assert '(encoding_value >= 209 && encoding_value <= 229)' not in operand assert 'EncodingError::InvalidScalarSourceSelector' in operand @@ -4289,9 +4289,10 @@ def test_generated_operands_validate_vgpr_source_selectors( amdgpu_generated_root: Path, ): validation = ( - 'if (opr_type == OperandType::OPR_SRC_VGPR && ' - '!((encoding_value >= 256 && encoding_value <= 511)))\n' - ' defer_encoding_error(EncodingError::InvalidVgprSourceSelector);' + 'case OperandType::OPR_SRC_VGPR:\n' + ' if (!((encoding_value >= 256 && encoding_value <= 511)))\n' + ' defer_encoding_error(EncodingError::InvalidVgprSourceSelector);\n' + ' break;' ) for arch in ( 'cdna1', @@ -4309,6 +4310,31 @@ def test_generated_operands_validate_vgpr_source_selectors( assert validation in operand +def test_generated_operand_validation_switch_is_shared_by_constructors( + amdgpu_generated_root: Path, +): + literal16_constructor = ( + 'Operand::Operand(int size_bits, OperandType opr_type, int encoding_value,\n' + ' uint16_t literal16_display_value, bool has_literal16_display)\n' + ' : Operand(size_bits, opr_type, encoding_value) {' + ) + for arch in ( + 'cdna1', + 'cdna2', + 'cdna3', + 'cdna4', + 'cdna5', + 'rdna1', + 'rdna2', + 'rdna3', + 'rdna3_5', + 'rdna4', + ): + operand = (amdgpu_generated_root / arch / 'operand.cpp').read_text() + assert operand.count('switch (opr_type) {') == 1 + assert literal16_constructor in operand + + def test_cdna4_mfma_f8f6f4_accepts_standalone_and_prefixed_encodings( amdgpu_generated_root: Path, ): diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp index abfb63d927ec..764ae67cb277 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/operand.cpp @@ -27,188 +27,146 @@ std::string reg_name(const char *prefix, int reg_num, int size_bits) { Operand::Operand(int size_bits, OperandType opr_type, int encoding_value) : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 768 && encoding_value <= 1023))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PARAM && !((encoding_value >= 0 && encoding_value <= 2))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 9) || - (encoding_value >= 12 && encoding_value <= 15) || - (encoding_value >= 32 && encoding_value <= 63))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 254 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ACCVGPR: + if (!((encoding_value >= 768 && encoding_value <= 1023))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_ATTR: + if (!((encoding_value >= 0 && encoding_value <= 32))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PARAM: + if (!((encoding_value >= 0 && encoding_value <= 2))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 254) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_NOVCC: + if (!((encoding_value >= 0 && encoding_value <= 105) || + (encoding_value >= 108 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_TGT: + if (!((encoding_value >= 0 && encoding_value <= 9) || + (encoding_value >= 12 && encoding_value <= 15) || + (encoding_value >= 32 && encoding_value <= 63))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR_OR_LDS: + if (!((encoding_value >= 254 && encoding_value <= 254) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 768 && encoding_value <= 1023))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PARAM && !((encoding_value >= 0 && encoding_value <= 2))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 9) || - (encoding_value >= 12 && encoding_value <= 15) || - (encoding_value >= 32 && encoding_value <= 63))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 254 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp index fb72c2f73467..de3ada442ecd 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/operand.cpp @@ -27,172 +27,132 @@ std::string reg_name(const char *prefix, int reg_num, int size_bits) { Operand::Operand(int size_bits, OperandType opr_type, int encoding_value) : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 512 && encoding_value <= 767))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ACCVGPR: + if (!((encoding_value >= 512 && encoding_value <= 767))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_NOVCC: + if (!((encoding_value >= 0 && encoding_value <= 105) || + (encoding_value >= 108 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR_OR_LDS: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 512 && encoding_value <= 767))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp index c80a52b2cce8..57d8e97287b0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/operand.cpp @@ -27,172 +27,132 @@ std::string reg_name(const char *prefix, int reg_num, int size_bits) { Operand::Operand(int size_bits, OperandType opr_type, int encoding_value) : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 512 && encoding_value <= 767))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ACCVGPR: + if (!((encoding_value >= 512 && encoding_value <= 767))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_NOVCC: + if (!((encoding_value >= 0 && encoding_value <= 105) || + (encoding_value >= 108 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR_OR_LDS: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 512 && encoding_value <= 767))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp index 3ca0381cdcde..660301983ca6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/operand.cpp @@ -27,176 +27,136 @@ std::string reg_name(const char *prefix, int reg_num, int size_bits) { Operand::Operand(int size_bits, OperandType opr_type, int encoding_value) : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 512 && encoding_value <= 767))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_GPUMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ACCVGPR: + if (!((encoding_value >= 512 && encoding_value <= 767))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_GPUMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_NOVCC: + if (!((encoding_value >= 0 && encoding_value <= 105) || + (encoding_value >= 108 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_NOLIT: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 126 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR_OR_LDS: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ACCVGPR && !((encoding_value >= 512 && encoding_value <= 767))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_GPUMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NOVCC && - !((encoding_value >= 0 && encoding_value <= 105) || - (encoding_value >= 108 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLIT && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 126 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp index d5d6482fa9ca..e5880bca7851 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.cpp @@ -64,78 +64,121 @@ Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, bool p : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())), packed_16bit_source_(packed_16bit_source), packed_16bit_dst_(packed_16bit_dst) { - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_GPUMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SGPR && !((encoding_value >= 0 && encoding_value <= 105))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET_NOK && - !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 230 && encoding_value <= 231) || - (encoding_value >= 235 && encoding_value <= 236) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOINLINE && - !((encoding_value >= 0 && encoding_value <= 127) || - (encoding_value >= 254 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 230 && encoding_value <= 231) || - (encoding_value >= 235 && encoding_value <= 236) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0 && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 230 && encoding_value <= 231) || - (encoding_value >= 235 && encoding_value <= 236) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_BARRIER_ID && - !((encoding_value >= 125 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 159) || - (encoding_value >= 193 && encoding_value <= 196))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 126))) + defer_encoding_error(EncodingError::InvalidExecSelector); + break; + case OperandType::OPR_GPUMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 125 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SGPR: + if (!((encoding_value >= 0 && encoding_value <= 105))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET_NOK: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 230 && encoding_value <= 231) || + (encoding_value >= 235 && encoding_value <= 236) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOINLINE: + if (!((encoding_value >= 0 && encoding_value <= 127) || + (encoding_value >= 254 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 230 && encoding_value <= 231) || + (encoding_value >= 235 && encoding_value <= 236) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SRC_VGPR_OR_INLINE: + if (!((encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_M0: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 230 && encoding_value <= 231) || + (encoding_value >= 235 && encoding_value <= 236) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_BARRIER_ID: + if (!((encoding_value >= 125 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 159) || + (encoding_value >= 193 && encoding_value <= 196))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 106 && encoding_value <= 106))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } @@ -146,83 +189,9 @@ Operand::Operand(int size_bits, OperandType opr_type, unsigned short encoding_va Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_GPUMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SGPR && !((encoding_value >= 0 && encoding_value <= 105))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET_NOK && - !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 230 && encoding_value <= 231) || - (encoding_value >= 235 && encoding_value <= 236) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOINLINE && - !((encoding_value >= 0 && encoding_value <= 127) || - (encoding_value >= 254 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 230 && encoding_value <= 231) || - (encoding_value >= 235 && encoding_value <= 236) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0 && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 230 && encoding_value <= 231) || - (encoding_value >= 235 && encoding_value <= 236) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_BARRIER_ID && - !((encoding_value >= 125 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 159) || - (encoding_value >= 193 && encoding_value <= 196))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp index 2b114c0e17c9..dbc56ccab061 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/operand.cpp @@ -27,178 +27,144 @@ std::string reg_name(const char *prefix, int reg_num, int size_bits) { Operand::Operand(int size_bits, OperandType opr_type, int encoding_value) : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PARAM && !((encoding_value >= 0 && encoding_value <= 2))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SIMM8 && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123) || - (encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NONULL && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 9) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 20) || - (encoding_value >= 32 && encoding_value <= 63))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 254 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ATTR: + if (!((encoding_value >= 0 && encoding_value <= 32))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 126))) + defer_encoding_error(EncodingError::InvalidExecSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PARAM: + if (!((encoding_value >= 0 && encoding_value <= 2))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SIMM8: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 123) || + (encoding_value >= 125 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_M0_INL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_NONULL: + if (!((encoding_value >= 0 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_TGT: + if (!((encoding_value >= 0 && encoding_value <= 9) || + (encoding_value >= 12 && encoding_value <= 16) || + (encoding_value >= 20 && encoding_value <= 20) || + (encoding_value >= 32 && encoding_value <= 63))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 106 && encoding_value <= 106))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR_OR_LDS: + if (!((encoding_value >= 254 && encoding_value <= 254) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PARAM && !((encoding_value >= 0 && encoding_value <= 2))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SIMM8 && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123) || - (encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NONULL && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 9) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 20) || - (encoding_value >= 32 && encoding_value <= 63))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 254 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp index c14eba407f4c..ef0b8a2cd1ff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/operand.cpp @@ -27,172 +27,139 @@ std::string reg_name(const char *prefix, int reg_num, int size_bits) { Operand::Operand(int size_bits, OperandType opr_type, int encoding_value) : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PARAM && !((encoding_value >= 0 && encoding_value <= 2))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123) || - (encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NONULL && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 9) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 20) || - (encoding_value >= 32 && encoding_value <= 63))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 254 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ATTR: + if (!((encoding_value >= 0 && encoding_value <= 32))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 126))) + defer_encoding_error(EncodingError::InvalidExecSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PARAM: + if (!((encoding_value >= 0 && encoding_value <= 2))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_SIMPLE: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 123) || + (encoding_value >= 125 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_M0_INL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_NONULL: + if (!((encoding_value >= 0 && encoding_value <= 123))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_NOLDS: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 248) || + (encoding_value >= 251 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_TGT: + if (!((encoding_value >= 0 && encoding_value <= 9) || + (encoding_value >= 12 && encoding_value <= 16) || + (encoding_value >= 20 && encoding_value <= 20) || + (encoding_value >= 32 && encoding_value <= 63))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 106 && encoding_value <= 106))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR_OR_LDS: + if (!((encoding_value >= 254 && encoding_value <= 254) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PARAM && !((encoding_value >= 0 && encoding_value <= 2))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_SIMPLE && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 123) || - (encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_NONULL && !((encoding_value >= 0 && encoding_value <= 123))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_NOLDS && - !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 248) || - (encoding_value >= 251 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 9) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 20) || - (encoding_value >= 32 && encoding_value <= 63))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR_OR_LDS && - !((encoding_value >= 254 && encoding_value <= 254) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp index f95491279f3b..6f945163422e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/operand.cpp @@ -64,67 +64,109 @@ Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, bool p : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())), packed_16bit_source_(packed_16bit_source), packed_16bit_dst_(packed_16bit_dst) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_NULL && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 8) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 22))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ATTR: + if (!((encoding_value >= 0 && encoding_value <= 32))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 126))) + defer_encoding_error(EncodingError::InvalidExecSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 125 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_NULL: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 238) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SRC_VGPR_OR_INLINE: + if (!((encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_M0_INL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 238) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_TGT: + if (!((encoding_value >= 0 && encoding_value <= 8) || + (encoding_value >= 12 && encoding_value <= 16) || + (encoding_value >= 20 && encoding_value <= 22))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 106 && encoding_value <= 106))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } @@ -135,72 +177,9 @@ Operand::Operand(int size_bits, OperandType opr_type, unsigned short encoding_va Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_NULL && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 8) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 22))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp index 7b404b5fc71d..15db82c04344 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand.cpp @@ -64,67 +64,109 @@ Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, bool p : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())), packed_16bit_source_(packed_16bit_source), packed_16bit_dst_(packed_16bit_dst) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_NULL && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 8) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 22))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ATTR: + if (!((encoding_value >= 0 && encoding_value <= 32))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 126))) + defer_encoding_error(EncodingError::InvalidExecSelector); + break; + case OperandType::OPR_FLAT_SCRATCH: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 125 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_NULL: + if (!((encoding_value >= 124 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 238) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SRC_VGPR_OR_INLINE: + if (!((encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_M0_INL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 238) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_TGT: + if (!((encoding_value >= 0 && encoding_value <= 8) || + (encoding_value >= 12 && encoding_value <= 16) || + (encoding_value >= 20 && encoding_value <= 22))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 106 && encoding_value <= 106))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } @@ -135,72 +177,9 @@ Operand::Operand(int size_bits, OperandType opr_type, unsigned short encoding_va Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_FLAT_SCRATCH && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_NULL && !((encoding_value >= 124 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0_INL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 8) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 22))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp index 4b2155a313fe..8003dac47a7a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/operand.cpp @@ -64,74 +64,118 @@ Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, bool p : IsaOperand(size_bits, opr_type, encoding_value), execution_backend_(static_cast(current_isa_operand_backend())), packed_16bit_source_(packed_16bit_source), packed_16bit_dst_(packed_16bit_dst) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_GPUMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET_NOK && - !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_LITERAL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0 && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_BARRIER_ID && - !((encoding_value >= 125 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 159) || - (encoding_value >= 193 && encoding_value <= 194))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 8) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 22))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); + switch (opr_type) { + case OperandType::OPR_ATTR: + if (!((encoding_value >= 0 && encoding_value <= 32))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_DSMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 126))) + defer_encoding_error(EncodingError::InvalidExecSelector); + break; + case OperandType::OPR_GPUMEM: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_PC: + if (!((encoding_value >= 0 && encoding_value <= 0))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST: + if (!((encoding_value >= 0 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_EXEC: + if (!((encoding_value >= 126 && encoding_value <= 127))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SDST_M0: + if (!((encoding_value >= 125 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SMEM_OFFSET_NOK: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 238) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SRC_VGPR: + if (!((encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidVgprSourceSelector); + break; + case OperandType::OPR_SRC_VGPR_OR_INLINE: + if (!((encoding_value >= 128 && encoding_value <= 208) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 256 && encoding_value <= 511))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_SREG: + if (!((encoding_value >= 0 && encoding_value <= 124))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_LITERAL: + if (!((encoding_value >= 0 && encoding_value <= 124) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SREG_M0: + if (!((encoding_value >= 0 && encoding_value <= 125))) + defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); + break; + case OperandType::OPR_SSRC: + if (!((encoding_value >= 0 && encoding_value <= 208) || + (encoding_value >= 235 && encoding_value <= 238) || + (encoding_value >= 240 && encoding_value <= 248) || + (encoding_value >= 253 && encoding_value <= 253) || + (encoding_value >= 255 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_BARRIER_ID: + if (!((encoding_value >= 125 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 159) || + (encoding_value >= 193 && encoding_value <= 194))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_SSRC_LANESEL: + if (!((encoding_value >= 0 && encoding_value <= 125) || + (encoding_value >= 128 && encoding_value <= 191))) + defer_encoding_error(EncodingError::InvalidLaneSelector); + break; + case OperandType::OPR_SSRC_SPECIAL_SCC: + if (!((encoding_value >= 253 && encoding_value <= 253))) + defer_encoding_error(EncodingError::InvalidScalarSourceSelector); + break; + case OperandType::OPR_TGT: + if (!((encoding_value >= 0 && encoding_value <= 8) || + (encoding_value >= 12 && encoding_value <= 16) || + (encoding_value >= 20 && encoding_value <= 22))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VCC: + if (!((encoding_value >= 106 && encoding_value <= 106))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + case OperandType::OPR_VGPR: + if (!((encoding_value >= 0 && encoding_value <= 255))) + defer_encoding_error(EncodingError::InvalidSelector); + break; + default: + break; + } is_vgpr_ = is_vgpr_operand_type(opr_type); } @@ -142,79 +186,9 @@ Operand::Operand(int size_bits, OperandType opr_type, unsigned short encoding_va Operand::Operand(int size_bits, OperandType opr_type, int encoding_value, uint16_t literal16_display_value, bool has_literal16_display) - : IsaOperand(size_bits, opr_type, encoding_value), - execution_backend_(static_cast(current_isa_operand_backend())), - literal16_display_value_(literal16_display_value), - has_literal16_display_(has_literal16_display) { - if (opr_type == OperandType::OPR_ATTR && !((encoding_value >= 0 && encoding_value <= 32))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_DSMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_EXEC && !((encoding_value >= 126 && encoding_value <= 126))) - defer_encoding_error(EncodingError::InvalidExecSelector); - if (opr_type == OperandType::OPR_GPUMEM && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_PC && !((encoding_value >= 0 && encoding_value <= 0))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST && !((encoding_value >= 0 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_EXEC && !((encoding_value >= 126 && encoding_value <= 127))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SDST_M0 && !((encoding_value >= 125 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SMEM_OFFSET_NOK && - !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SRC_VGPR && !((encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidVgprSourceSelector); - if (opr_type == OperandType::OPR_SRC_VGPR_OR_INLINE && - !((encoding_value >= 128 && encoding_value <= 208) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 256 && encoding_value <= 511))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_SREG && !((encoding_value >= 0 && encoding_value <= 124))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_LITERAL && - !((encoding_value >= 0 && encoding_value <= 124) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SREG_M0 && !((encoding_value >= 0 && encoding_value <= 125))) - defer_encoding_error(EncodingError::InvalidScalarRegisterSelector); - if (opr_type == OperandType::OPR_SSRC && !((encoding_value >= 0 && encoding_value <= 208) || - (encoding_value >= 235 && encoding_value <= 238) || - (encoding_value >= 240 && encoding_value <= 248) || - (encoding_value >= 253 && encoding_value <= 253) || - (encoding_value >= 255 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_BARRIER_ID && - !((encoding_value >= 125 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 159) || - (encoding_value >= 193 && encoding_value <= 194))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_SSRC_LANESEL && - !((encoding_value >= 0 && encoding_value <= 125) || - (encoding_value >= 128 && encoding_value <= 191))) - defer_encoding_error(EncodingError::InvalidLaneSelector); - if (opr_type == OperandType::OPR_SSRC_SPECIAL_SCC && - !((encoding_value >= 253 && encoding_value <= 253))) - defer_encoding_error(EncodingError::InvalidScalarSourceSelector); - if (opr_type == OperandType::OPR_TGT && !((encoding_value >= 0 && encoding_value <= 8) || - (encoding_value >= 12 && encoding_value <= 16) || - (encoding_value >= 20 && encoding_value <= 22))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VCC && !((encoding_value >= 106 && encoding_value <= 106))) - defer_encoding_error(EncodingError::InvalidSelector); - if (opr_type == OperandType::OPR_VGPR && !((encoding_value >= 0 && encoding_value <= 255))) - defer_encoding_error(EncodingError::InvalidSelector); - is_vgpr_ = is_vgpr_operand_type(opr_type); + : Operand(size_bits, opr_type, encoding_value) { + literal16_display_value_ = literal16_display_value; + has_literal16_display_ = has_literal16_display; } Operand::Operand(int size_bits, OperandType opr_type, uint64_t literal64_value, bool is_literal64) From 1a612c47c07c703493f2d87bbd631b83dcf4d480 Mon Sep 17 00:00:00 2001 From: James Newling Date: Wed, 19 Aug 2026 09:08:56 -0700 Subject: [PATCH 19/27] fix(rocjitsu): respect same-wave LDS ordering (#9735) ## Summary This PR fixes a general misunderstanding I had about same-wave LDS synchronization on our GPUs.. I previously assumed that sequences such as: ```asm ds_write_b8 v2, v0 # write to LDS at address in v2 ds_read_u8 v14, v2 ``` and the reverse: ```asm ds_read_u8 v14, v2 ds_write_b8 v2, v0 ``` were racy unless an `s_waitcnt lgkmcnt(0)` appeared between the two instructions. That is true for consuming the result of an LDS read. For example, this is racy: ```asm ds_read_u8 v14, v2 v_and_b32_e32 v5, 1, v14 ``` The read may not have returned its result to `v14` yet. This requires a wait: ```asm ds_read_u8 v14, v2 s_waitcnt lgkmcnt(0) v_and_b32_e32 v5, 1, v14 ``` However, ordinary DS operations issued by the same wave are ordered with respect to each other. They may be in flight at the same time, but a later DS instruction **does not overtake an earlier one** in the LDS pipeline. Consequently: - A same-wave DS write followed by a DS read observes the write. - A same-wave DS read followed by a DS write observes the value from before the write. - The destination VGPR of an LDS read still requires the appropriate wait before it can be consumed or overwritten. An agent confirmed this experimentally on a gfx1151 GPU using both same-lane and cross-lane byte accesses. Repeated no-wait write/read and read/write sequences completed without a single value mismatch. The issue originally surfaced as an LDS race report in hipBLASLt's HPL initialization kernel. LLVM had promoted a private Boolean temporary to per-workitem LDS storage and generated: ```asm ds_write_b8 ... ds_read_u8 ... s_waitcnt lgkmcnt(0) ``` The plugin incorrectly reported the read as racing with the earlier same-wave write. ## Changes The race detector now: - Treats ordinary same-wave DS write-to-read and read-to-write accesses as ordered. - Continues tracking an LDS read's destination VGPR until `lgkmcnt` permits its use. - Continues reporting overlapping cross-wave LDS accesses without the required barrier. - Continues requiring `vmcnt` before the owning wave consumes data written through a direct-to-LDS VMEM operation. The tests now include focused same-lane and cross-lane RAW/WAR unit coverage, plus one gfx950 end-to-end ordering test. ## Testing New ones added, incorrect ones fixed. ## Issue Tracking Related: #9577 (cherry picked from commit dd619bed77b8c9d2ca9775ef676780fd29360dd6) --- emulation/rocjitsu/docs/race-detector.md | 14 ++- .../race_detector/core/race_detector.cpp | 17 ++- .../vm/plugins/race_detector/core/types.h | 6 +- .../tests/race-detector/CMakeLists.txt | 1 + .../race-detector/hip_race_gfx950_test.hip | 82 ++++++++++++++ .../race-detector/race_detector_tests.cpp | 105 +++++++++++------- .../tests/race-detector/race_test_builder.h | 11 +- 7 files changed, 176 insertions(+), 60 deletions(-) diff --git a/emulation/rocjitsu/docs/race-detector.md b/emulation/rocjitsu/docs/race-detector.md index 8c6e8bdf1d80..152f845a69dc 100644 --- a/emulation/rocjitsu/docs/race-detector.md +++ b/emulation/rocjitsu/docs/race-detector.md @@ -150,8 +150,12 @@ races. Some examples: `s_waitcnt lgkmcnt` insufficient). - **SGPR races**: a scalar register is read before a pending scalar load has completed (`s_waitcnt lgkmcnt` insufficient). -- **LDS races**: an LDS byte is read or written by one wave while another wave - has an outstanding write to the same byte, without an intervening `s_barrier`. +- **LDS races**: an LDS byte is read by one wave while another wave has an + outstanding write to the same byte, or written by one wave while another + wave has an outstanding read of the same byte, without an intervening + `s_barrier`; + or a wave reads bytes targeted by its own outstanding direct-to-LDS operation + before the required `s_waitcnt vmcnt`. Detection is at byte granularity: D16 (half-register) loads only flag races on the affected bytes, and LDS races are tracked per byte. @@ -161,7 +165,11 @@ the affected bytes, and LDS races are tracked per byte. Every in-flight memory operation has an **event** that goes through the following lifecycle: -1. **ACTIVE** — the operation is in flight. +1. **ACTIVE** — the operation is in flight. Ordinary DS operations issued by + the same wave remain ordered with respect to each other, so a later + same-wave DS read or write does not race solely because the earlier DS event + is still active. Direct-to-LDS VMEM writes still require the owning wave to + wait for `vmcnt` before reading the destination bytes. 1. **WAVE_COMPLETE** — `s_waitcnt` has retired the event for the owning wave. This means the event is no longer in flight from the perspective of the wave that issued the operation, but is still in flight from the perspective of diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/race_detector.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/race_detector.cpp index 63a7e9d475cc..cfb47afa6620 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/race_detector.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/race_detector.cpp @@ -77,8 +77,15 @@ void RaceDetector::validateRead(int addr, WaveId wave, int lane, int nBytes) con } for (EventId eventId : ldsWriteEvents) { - if (wave == events_.waveId(eventId) && events_.status(eventId) == EventStatus::WAVE_COMPLETE) { - continue; + if (wave == events_.waveId(eventId)) { + // Ordinary DS operations from one wave are ordered by the LDS pipeline, + // so a later DS read cannot overtake this wave's earlier DS write. A + // direct-to-LDS VMEM operation is different: a same-wave DS read of its + // destination bytes must wait for vmcnt. + if (events_.type(eventId) == MemoryEventType::VGPR_TO_LDS || + events_.status(eventId) == EventStatus::WAVE_COMPLETE) { + continue; + } } if (events_.ldsIntervals(eventId).overlapsRange(addr, addr + nBytes)) { raceHandler({RaceViolation::Space::LDS, addr, wave.value, lane, false, workgroupId, eventId}); @@ -102,7 +109,11 @@ void RaceDetector::validateWrite(int addr, WaveId wave, int lane, int nBytes) co } for (EventId eventId : ldsReadEvents) { - if (wave == events_.waveId(eventId) && events_.status(eventId) == EventStatus::WAVE_COMPLETE) { + // A later ordinary DS write from the same wave cannot overtake an earlier + // DS read. The read's destination VGPR remains independently protected by + // lgkmcnt until it is safe to consume or overwrite. This WAR check does + // not cover LDS write/write ordering, which is not currently checked. + if (wave == events_.waveId(eventId)) { continue; } if (events_.ldsIntervals(eventId).overlapsRange(addr, addr + nBytes)) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/types.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/types.h index ab0206bbe1fc..7205ac604559 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/types.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/plugins/race_detector/core/types.h @@ -56,9 +56,9 @@ inline void removeFromUnorderedList(std::vector &list, EventId eventId) /// Status of a memory event in the race detection lifecycle. enum class EventStatus { - ACTIVE, // Pending. Unsafe for everyone. - WAVE_COMPLETE, // s_waitcnt passed. Safe for owning wave, unsafe for others. - RETIRED // Fully retired (s_barrier). No longer referenced. + ACTIVE, // Pending; in flight. + WAVE_COMPLETE, // Owning-wave wait passed; retained until retirement if needed. + RETIRED // Fully retired; no longer referenced. }; /// Describes a detected race condition. Used by the race detection layer diff --git a/emulation/rocjitsu/tests/race-detector/CMakeLists.txt b/emulation/rocjitsu/tests/race-detector/CMakeLists.txt index a07fe409d632..ce2db2484a7f 100644 --- a/emulation/rocjitsu/tests/race-detector/CMakeLists.txt +++ b/emulation/rocjitsu/tests/race-detector/CMakeLists.txt @@ -120,6 +120,7 @@ rj_add_gfx950_race_test_case(sgpr_waitcnt) rj_add_gfx950_race_test_case(sgpr_waitcnt_race) rj_add_gfx950_race_test_case(lds_cross_wave) rj_add_gfx950_race_test_case(lds_cross_wave_race) +rj_add_gfx950_race_test_case(lds_same_wave_order) rj_add_gfx950_race_test_case(global_to_lds_buffer) rj_add_gfx950_race_test_case(global_to_lds_buffer_race) rj_add_gfx950_race_test_case(partial_vmcnt_race) diff --git a/emulation/rocjitsu/tests/race-detector/hip_race_gfx950_test.hip b/emulation/rocjitsu/tests/race-detector/hip_race_gfx950_test.hip index 564028410e2e..e0f524c7921d 100644 --- a/emulation/rocjitsu/tests/race-detector/hip_race_gfx950_test.hip +++ b/emulation/rocjitsu/tests/race-detector/hip_race_gfx950_test.hip @@ -373,6 +373,88 @@ TEST_F(Gfx950RaceTest, lds_cross_wave_race) { EXPECT_NE(t.mark1.find("ds_read_b32"), npos) << "mark1: " << t.mark1; } +// --- LDS same-wave instruction ordering --- + +__attribute__((amdgpu_flat_work_group_size(64, 64))) +__global__ void lds_same_wave_write_read_order_kernel(uint32_t *out) { + uint32_t lane = threadIdx.x; + uint32_t read_lane = (lane + 1) & 63; + uint32_t value = lane + 1; + uint32_t observed; + asm volatile( + "ds_write_b8 %1, %2\n" + "ds_read_u8 %0, %3\n" + "s_waitcnt lgkmcnt(0)\n" + : "=&v"(observed) + : "v"(lane), "v"(value), "v"(read_lane) + : "memory" + ); + out[lane] = observed; +} + +__attribute__((amdgpu_flat_work_group_size(64, 64))) +__global__ void lds_same_wave_read_write_order_kernel(uint32_t *out) { + uint32_t lane = threadIdx.x; + uint32_t read_lane = (lane + 1) & 63; + uint32_t old_value = lane + 1; + uint32_t new_value = old_value ^ 0xff; + uint32_t observed_old; + uint32_t observed_new; + + // Establish the old value, then test that the following same-wave DS read + // completes logically before the later DS write to the overlapping bytes. + asm volatile( + "ds_write_b8 %0, %1\n" + "s_waitcnt lgkmcnt(0)\n" + : + : "v"(lane), "v"(old_value) + : "memory" + ); + asm volatile( + "ds_read_u8 %0, %2\n" + "ds_write_b8 %1, %3\n" + "s_waitcnt lgkmcnt(0)\n" + : "=&v"(observed_old) + : "v"(lane), "v"(read_lane), "v"(new_value) + : "memory" + ); + asm volatile( + "ds_read_u8 %0, %1\n" + "s_waitcnt lgkmcnt(0)\n" + : "=v"(observed_new) + : "v"(lane) + : "memory" + ); + + out[2 * lane] = observed_old; + out[2 * lane + 1] = observed_new; +} + +TEST_F(Gfx950RaceTest, lds_same_wave_order) { + auto *write_read_out = alloc(64); + lds_same_wave_write_read_order_kernel<<<1, 64, 64>>>(write_read_out); + sync(); + + std::vector write_read_host(64); + (void)hipMemcpy(write_read_host.data(), write_read_out, + write_read_host.size() * sizeof(uint32_t), hipMemcpyDeviceToHost); + for (uint32_t lane = 0; lane < write_read_host.size(); ++lane) + EXPECT_EQ(write_read_host[lane], ((lane + 1) & 63) + 1); + + auto *read_write_out = alloc(128); + lds_same_wave_read_write_order_kernel<<<1, 64, 64>>>(read_write_out); + sync(); + + std::vector read_write_host(128); + (void)hipMemcpy(read_write_host.data(), read_write_out, + read_write_host.size() * sizeof(uint32_t), hipMemcpyDeviceToHost); + for (uint32_t lane = 0; lane < 64; ++lane) { + EXPECT_EQ(read_write_host[2 * lane], ((lane + 1) & 63) + 1); + EXPECT_EQ(read_write_host[2 * lane + 1], (lane + 1) ^ 0xff); + } + ExpectNoRace(); +} + // --- Global-to-LDS buffer --- // These kernels use buffer_load_dword with the LDS flag to load data from // global memory directly into LDS (bypassing VGPRs). Designed for 128-thread diff --git a/emulation/rocjitsu/tests/race-detector/race_detector_tests.cpp b/emulation/rocjitsu/tests/race-detector/race_detector_tests.cpp index 1ff697bbb9c2..0ef08a3439f8 100644 --- a/emulation/rocjitsu/tests/race-detector/race_detector_tests.cpp +++ b/emulation/rocjitsu/tests/race-detector/race_detector_tests.cpp @@ -10,7 +10,7 @@ // Vgpr_* — VGPR races from global loads (vmcnt) // Sgpr_* — SGPR races from scalar loads (lgkmcnt) // LdsCrossWave_* — cross-wave LDS races (missing barrier) -// LdsSameWave_* — same-wave LDS races (missing waitcnt) +// LdsSameWave_* — same-wave LDS instruction ordering // SameWave_* — same-wave VGPR races via LDS loads // DeepStack_* — multiple outstanding loads with partial waitcnt // D16_* — byte-level VGPR tracking (half-register loads) @@ -155,7 +155,7 @@ TEST(RaceDetector, LdsCrossWave_WarNoOverlap) { EXPECT_FALSE(b.hasRace()); } -// ---- LDS same-wave races ---- +// ---- LDS same-wave ordering ---- TEST(RaceDetector, LdsSameWave_WriteWriteOk) { // Two writes to same address, same wave → not a race. @@ -178,25 +178,36 @@ TEST(RaceDetector, LdsSameWave_ReadReadOk) { EXPECT_FALSE(b.hasRace()); } -TEST(RaceDetector, LdsSameWave_WriteReadRace) { - // Write then read same address, same wave, no waitcnt → RACE. +TEST(RaceDetector, LdsSameWave_WriteReadSameLaneOk) { RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); - // no waitcnt b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); - EXPECT_TRUE(b.hasLdsRace(0)); + EXPECT_FALSE(b.hasRace()); } -TEST(RaceDetector, LdsSameWave_InsufficientLgkm) { - // Two LDS writes, waitcnt lgkmcnt(1) drains oldest only. +TEST(RaceDetector, LdsSameWave_WriteReadCrossLaneOk) { + // DS instructions are wave-wide, so a later lane 1 read cannot overtake + // lane 0's write from the earlier instruction. RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); - b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); // oldest - b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/64, /*bytes=*/4); // newest - b.waitcnt(/*wave=*/0, /*vmcnt=*/-1, /*lgkmcnt=*/1); // drain oldest - b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); // safe - EXPECT_FALSE(b.hasLdsRace(0)); - b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/64, /*bytes=*/4); // RACE - EXPECT_TRUE(b.hasLdsRace(64)); + b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); + b.checkLdsRead(/*wave=*/0, /*lane=*/1, /*addr=*/0, /*bytes=*/4); + EXPECT_FALSE(b.hasRace()); +} + +TEST(RaceDetector, LdsSameWave_ReadWriteSameLaneOk) { + RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); + b.ldsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4, /*vgprDst=*/2); + b.checkLdsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); + EXPECT_FALSE(b.hasRace()); +} + +TEST(RaceDetector, LdsSameWave_ReadWriteCrossLaneOk) { + // A later lane 1 write cannot overtake lane 0's read from the earlier + // wave-wide DS instruction. + RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); + b.ldsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4, /*vgprDst=*/2); + b.checkLdsWrite(/*wave=*/0, /*lane=*/1, /*addr=*/0, /*bytes=*/4); + EXPECT_FALSE(b.hasRace()); } // ---- Same-wave VGPR via LDS load ---- @@ -454,39 +465,49 @@ TEST(RaceDetector, Dtl_CrossWaveSafe) { EXPECT_FALSE(b.hasRace()); } -// ---- Exec mask ---- - -TEST(RaceDetector, Exec_PartialWriteFullRead) { - // Only lane 0 writes LDS, then full-exec read → RACE (write still ACTIVE). - RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); - b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4, /*exec=*/1); +TEST(RaceDetector, Dtl_SameWaveMissingVmcntRace) { + // Direct-to-LDS arrives through VMEM, so unlike an ordinary DS write the + // owning wave must wait for vmcnt before reading the LDS bytes. + RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/4, /*sgprs=*/4); + b.globalToLds(/*wave=*/0, /*ldsAddrs=*/{0}, /*bytesPerLane=*/4); b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); EXPECT_TRUE(b.hasLdsRace(0)); } -TEST(RaceDetector, Exec_PartialWriteWaitcntOk) { - // Lane 0 writes, waitcnt, then read → safe (same wave, WAVE_COMPLETE). - RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); - b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4, /*exec=*/1); - b.waitcnt(/*wave=*/0, /*vmcnt=*/-1, /*lgkmcnt=*/0); +TEST(RaceDetector, Dtl_SameWaveWithVmcntSafe) { + RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/4, /*sgprs=*/4); + b.globalToLds(/*wave=*/0, /*ldsAddrs=*/{0}, /*bytesPerLane=*/4); + b.waitcnt(/*wave=*/0, /*vmcnt=*/0); b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); EXPECT_FALSE(b.hasRace()); } -TEST(RaceDetector, Exec_DisjointLanesOverlap) { - // Lane 0 writes LDS[0], lane 1 reads LDS[0] without barrier → RACE. - RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); - b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4, /*exec=*/1); - b.checkLdsRead(/*wave=*/0, /*lane=*/1, /*addr=*/0, /*bytes=*/4); // RACE - EXPECT_TRUE(b.hasLdsRace(0)); +TEST(RaceDetector, Dtl_SameWavePartialVmcntRetiresOldest) { + RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/4, /*sgprs=*/4); + b.globalToLds(/*wave=*/0, /*ldsAddrs=*/{16}, /*bytesPerLane=*/4, /*exec=*/1); + b.globalToLds(/*wave=*/0, /*ldsAddrs=*/{64}, /*bytesPerLane=*/4, /*exec=*/1); + b.waitcnt(/*wave=*/0, /*vmcnt=*/1); + + b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/16, /*bytes=*/4); + EXPECT_FALSE(b.hasRace()); + + b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/64, /*bytes=*/4); + EXPECT_TRUE(b.hasLdsRace(64)); } -TEST(RaceDetector, Exec_DisjointLanesDisjoint) { - // Lane 0 and lane 1 write different LDS addresses → safe. +// ---- Exec mask ---- + +TEST(RaceDetector, Exec_DirectToLdsTracksOnlyActiveLaneIntervals) { RaceTestBuilder b(/*numWaves=*/1, /*vgprs=*/8, /*sgprs=*/8); - b.ldsWrite(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4, /*exec=*/1); - b.ldsWrite(/*wave=*/0, /*lane=*/1, /*addr=*/64, /*bytes=*/4, /*exec=*/2); + b.globalToLds(/*wave=*/0, /*ldsAddrs=*/{16}, /*bytesPerLane=*/4, /*exec=*/1); + + // globalToLds pads inactive lane addresses with zero. The explicit one-lane + // exec mask must keep that padding out of the tracked LDS intervals. + b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/0, /*bytes=*/4); EXPECT_FALSE(b.hasRace()); + + b.checkLdsRead(/*wave=*/0, /*lane=*/0, /*addr=*/16, /*bytes=*/4); + EXPECT_TRUE(b.hasLdsRace(16)); } // ---- Multi-workgroup ---- @@ -852,15 +873,15 @@ TEST(RaceDetector, Dtl_MultiLane_CrossWaveSafeWithBarrier) { // ---- Dual-offset LDS ---- -TEST(RaceDetector, DualOffset_Race) { +TEST(RaceDetector, DualOffset_CrossWaveRace) { // registerDualOffsetLdsEvent: each lane writes TWO 8-byte intervals. // Lane 0 base=100: [100, 108) (offset0=0) and [116, 124) (offset1=2). - // Read from either interval without waitcnt → RACE. + // Another wave reading either interval without a barrier → RACE. // // Uses RaceDetector/WaveRaceState directly since the builder doesn't // expose registerDualOffsetLdsEvent. std::vector violations; - RaceDetector detector(/*nWaves=*/1, /*vgprCount=*/4, + RaceDetector detector(/*nWaves=*/2, /*vgprCount=*/4, /*sgprCount=*/4, Dim3d(0), [&](RaceViolation v) { violations.push_back(v); }); auto &rs = detector.getWaveRaceState(0); @@ -871,12 +892,12 @@ TEST(RaceDetector, DualOffset_Race) { /*execMask=*/1, /*waveSize=*/64, ldsAddrs, /*offset0=*/0, /*offset1=*/2); // Lane 0 wrote: [100, 108) and [116, 124) - detector.validateRead(/*addr=*/100, WaveId{0}, /*lane=*/0, /*nBytes=*/4); + detector.validateRead(/*addr=*/100, WaveId{1}, /*lane=*/0, /*nBytes=*/4); EXPECT_EQ(violations.size(), 1u); // first interval - detector.validateRead(/*addr=*/116, WaveId{0}, /*lane=*/0, /*nBytes=*/4); + detector.validateRead(/*addr=*/116, WaveId{1}, /*lane=*/0, /*nBytes=*/4); EXPECT_EQ(violations.size(), 2u); // second interval // Outside both intervals: no race - detector.validateRead(/*addr=*/108, WaveId{0}, /*lane=*/0, /*nBytes=*/4); + detector.validateRead(/*addr=*/108, WaveId{1}, /*lane=*/0, /*nBytes=*/4); EXPECT_EQ(violations.size(), 2u); // still 2 } diff --git a/emulation/rocjitsu/tests/race-detector/race_test_builder.h b/emulation/rocjitsu/tests/race-detector/race_test_builder.h index 26b788b37a10..9d010b19eee7 100644 --- a/emulation/rocjitsu/tests/race-detector/race_test_builder.h +++ b/emulation/rocjitsu/tests/race-detector/race_test_builder.h @@ -75,10 +75,7 @@ class RaceTestBuilder { } /// Register an LDS write and validate against outstanding reads. - void ldsWrite(int wave, int lane, int addr, int bytes, uint64_t exec = 0) { - if (!exec) { - exec = defaultExec_; - } + void ldsWrite(int wave, int lane, int addr, int bytes) { detector_->validateWrite(addr, WaveId{wave}, lane, bytes); std::vector ldsAddrs(waveSize_, 0); ldsAddrs[lane] = addr; @@ -90,11 +87,7 @@ class RaceTestBuilder { /// Register an LDS read and validate against outstanding writes. /// byteMask: which bytes of the destination VGPR are written by this load /// (0xF=full, 0x3=lo D16, 0xC=hi D16). Used for byte-level race tracking. - void ldsRead(int wave, int lane, int addr, int bytes, int vgprDst, uint8_t byteMask = 0xF, - uint64_t exec = 0) { - if (!exec) { - exec = defaultExec_; - } + void ldsRead(int wave, int lane, int addr, int bytes, int vgprDst, uint8_t byteMask = 0xF) { detector_->validateRead(addr, WaveId{wave}, lane, bytes); std::vector ldsAddrs(waveSize_, 0); ldsAddrs[lane] = addr; From 4360c4b9787a7e63bd46e579e1ccd6a3755977d1 Mon Sep 17 00:00:00 2001 From: Erick Ochoa Lopez Date: Wed, 19 Aug 2026 13:26:54 -0400 Subject: [PATCH 20/27] [rocjitsu] Rename gfx1250 to cdna5 for enums, configs, amdisa codegen helpers and generated symbols. (NFC) (#10137) ## Motivation Migrate architecture-level GFX1250 identifiers to the logical CDNA5 architecture identity. This separates the reusable architecture identity from concrete GFX1250 hardware and target-specific concepts. ## Technical Details * Replaces ROCJITSU_CODE_ARCH_GFX1250 with ROCJITSU_CODE_ARCH_CDNA5 across ISA dispatch, builders, code processing, configuration, VM, analysis, DBT, hooks, tools, and tests. * Makes cdna5 the canonical ISA provider and amdisa profile key. * Renames the simulator configuration to gfx1250_cdna5.json and updates its consumers. * Renames the Python ISA profile and CDNA5-specific code-generation helpers. * Renames generated matrix/WMMA helper symbols through cdna5_scaled_wmma_src1_size_bits. * Regenerates affected amdisa output. * Adapts tests split by the intervening CDNA5 simulator-test reorganization. This PR is limited to the logical CDNA5 architecture migration, including enum usage, provider/profile/config names, amdisa code-generation helpers, and generated matrix/WMMA symbols. ## Issue Tracking N/A ## Test Plan * Build the rocjitsu_tests target from build-nosan-debug. * Run focused CTest coverage for: * OperandSelectorDecodeTest * BinaryTranslatorE2E * Gfx1250ExecutionTest * Verify no tracked source references remain to the removed ROCJITSU_CODE_ARCH_GFX1250 enum. ## Test Result All good. ## Submission Checklist - [X] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit c5fae8d2b206d0e8f1281c1d6d7224660721982f) --- .github/workflows/rocjitsu-corpus-tests.yml | 2 +- emulation/mirage/builtin/src/agents.rs | 8 +- .../{gfx1250.json => gfx1250_mi455x.json} | 2 +- emulation/rocjitsu/docs/codegen.md | 16 +- emulation/rocjitsu/docs/configuration.md | 2 +- .../rocjitsu/lib/python/amdisa/__init__.py | 4 +- .../rocjitsu/lib/python/amdisa/__main__.py | 6 +- .../lib/python/amdisa/codegen/_generator.py | 138 ++-- .../python/amdisa/codegen/execute/__init__.py | 20 +- .../python/amdisa/codegen/execute/matrix.py | 14 +- .../python/amdisa/codegen/execute/packed.py | 52 +- .../amdisa/codegen/execute/vector_special.py | 4 +- .../rocjitsu/lib/python/amdisa/isa_profile.py | 10 +- .../python/amdisa/isa_properties_codegen.py | 2 +- .../rocjitsu/lib/python/amdisa/parser.py | 2 +- .../tests/test_generator_profile_gates.py | 152 ++-- .../amdisa/tests/test_literal_codegen.py | 12 +- .../amdisa/tests/test_packed_codegen.py | 10 +- .../amdisa/tests/test_profile_properties.py | 44 +- .../python/amdisa/tests/test_sema_derive.py | 4 +- .../tests/test_vector_special_codegen.py | 12 +- .../rocjitsu/include/rocjitsu/code/rj_code.h | 5 +- .../analysis/indirect_branch_discovery.cpp | 12 +- .../src/rocjitsu/analysis/liveness.cpp | 2 +- .../rocjitsu/src/rocjitsu/code/amdgpu_elf.h | 4 +- .../src/rocjitsu/code/basic_block.cpp | 6 +- .../code/builders/instruction_builder.cpp | 4 +- .../code/builders/instruction_builder.h | 32 +- .../rocjitsu/code/dbt/binary_translator.cpp | 10 +- .../code/dbt/gfx1250_b0_to_a0_library.cpp | 2 +- .../code/dbt/kernel_descriptor_translator.cpp | 12 +- .../semantic/cdna4_to_cdna3_virtual_lds.cpp | 2 +- .../rocjitsu/code/dbt/semantic_translator.cpp | 2 +- .../rocjitsu/code/kernel_descriptor_scan.cpp | 8 +- .../code/patch/code_object_patcher.cpp | 8 +- .../src/rocjitsu/code/patch/instrumentor.cpp | 5 +- .../src/rocjitsu/config/config_loader.cpp | 12 +- .../src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp | 4 +- .../src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h | 4 +- .../isa/arch/amdgpu/cdna5/target_descriptor.h | 6 +- .../isa/arch/amdgpu/generated/cdna5/vop3p.cpp | 78 +- .../amdgpu/generated/shared/isa_properties.h | 2 +- .../rocjitsu/src/rocjitsu/isa/isa_traits.h | 30 +- .../rocjitsu/vm/amdgpu/command_processor.cpp | 10 +- .../src/rocjitsu/vm/amdgpu/compute_unit.cpp | 2 +- .../rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp | 2 +- emulation/rocjitsu/scripts/generate-amdisa.sh | 4 +- emulation/rocjitsu/tests/amdgpu_vm_test.cpp | 8 +- .../rocjitsu/tests/analysis/liveness_test.cpp | 725 +++++++++-------- .../tests/cdna5_architecture_test.cpp | 82 +- .../rocjitsu/tests/cdna5_cluster_test.cpp | 2 +- .../rocjitsu/tests/cdna5_execution_test.cpp | 32 +- .../rocjitsu/tests/cdna5_instruction_test.cpp | 16 +- .../rocjitsu/tests/cdna5_sim_test_common.h | 4 +- .../rocjitsu/tests/cdna5_tensor_dma_test.cpp | 4 +- .../code/kernel_descriptor_scan_test.cpp | 4 +- .../code/relocation_function_table_test.cpp | 16 +- emulation/rocjitsu/tests/config_test.cpp | 4 +- .../rocjitsu/tests/corpus/run-corpus-tests.sh | 2 +- .../relocation_function_table_hip_test.cpp | 8 +- .../tests/dbt/translate_gfx1250_test.cpp | 757 +++++++++--------- .../rocjitsu/tests/dbt/translate_test.cpp | 90 +-- .../tests/decode_execute_benchmark.cpp | 2 +- .../rocjitsu/tests/decode_smoke_test.cpp | 44 +- .../rocjitsu/tests/decoder_c_api_test.cpp | 2 +- .../rocjitsu/tests/execution_plugin_test.cpp | 12 +- .../instruction_execution_harness_test.cpp | 154 ++-- .../tests/isa_target_registry_test.cpp | 7 +- .../rocjitsu/tests/model_only_isa_test.cpp | 4 +- .../tests/patch/instruction_builder_test.cpp | 26 +- .../tests/pseudo_scalar_exec_test.cpp | 2 +- .../rocjitsu/tests/register_access_test.cpp | 2 +- emulation/rocjitsu/tests/scalar_scc_test.cpp | 2 +- .../rocjitsu/tests/shared_infra_test.cpp | 27 +- .../vop3_carry_simd_correctness_test.cpp | 3 +- .../simd_correctness/wmma_simd_exact_test.cpp | 2 +- .../tests/smem_sbase_operand_test.cpp | 2 +- .../tools/rj_dbt_translate_smoke_test.cpp | 4 +- .../rocjitsu/tests/vgpr_redispatch_test.cpp | 2 +- .../rocjitsu/tests/wmma_simd_benchmark.cpp | 2 +- emulation/rocjitsu/tools/dbt_translate.cpp | 18 +- .../rocjitsu/tools/dbt_translate_cli.cpp | 2 +- .../rocjitsu/tools/rj_decode_benchmark.cpp | 4 +- 83 files changed, 1437 insertions(+), 1424 deletions(-) rename emulation/rocjitsu/configs/{gfx1250.json => gfx1250_mi455x.json} (99%) diff --git a/.github/workflows/rocjitsu-corpus-tests.yml b/.github/workflows/rocjitsu-corpus-tests.yml index d477508ab69b..e554f7a566a1 100644 --- a/.github/workflows/rocjitsu-corpus-tests.yml +++ b/.github/workflows/rocjitsu-corpus-tests.yml @@ -360,7 +360,7 @@ jobs: ROCM_PATH="$(rocm-sdk path --root)" export ROCM_PATH LAUNCHER="${ROCJITSU_BUILD_DIR}/tools/rocjitsu/rocjitsu" - CONFIG="${ROCJITSU_SOURCE_DIR}/configs/gfx1250.json" + CONFIG="${ROCJITSU_SOURCE_DIR}/configs/gfx1250_mi455x.json" HOTSWAP="${ROCJITSU_BUILD_DIR}/lib/rocjitsu/src/rocjitsu/hooks/libhsa_hotswap_rocjitsu.so" test -f "${HOTSWAP}" # Disable ROCr's built-in mechanism in both legs. Load the branch-built diff --git a/emulation/mirage/builtin/src/agents.rs b/emulation/mirage/builtin/src/agents.rs index dc3b04a9b955..4656e342b536 100644 --- a/emulation/mirage/builtin/src/agents.rs +++ b/emulation/mirage/builtin/src/agents.rs @@ -2,7 +2,7 @@ //! //! Each agent mirrors one of the rocjitsu `configs/*.json` files: //! `MI300X` follows `gfx942_cdna3.json`, `MI350X` follows -//! `gfx950_cdna4.json`, and `MI450X` follows `gfx1250.json`. +//! `gfx950_cdna4.json`, and `MI450X` follows `gfx1250_mi455x.json`. //! All three share the same `soc -> {vram, iod, xcd -> {l2, cp, //! se -> cu}}` component tree and six link patterns; they differ //! only in their device identity, the IOD fan-out, and the per-CU @@ -127,12 +127,12 @@ pub fn mi350x() -> AgentDef { } /// `MI450X` builtin agent (registry key `MI450X`), mirroring the -/// rocjitsu `gfx1250.json` config: `arch = gfx1250`, an +/// rocjitsu `gfx1250_mi455x.json` config: `arch = cdna5`, an /// 8-XCD / 4-SE / 8-CU shader fabric and a 2-IOD memory tier. pub fn mi450x() -> AgentDef { AgentDef { vm: VirtualMachineConfig { - arch: "gfx1250".to_string(), + arch: "cdna5".to_string(), gpu: AmdgpuConfig { num_xcds: 0, num_iods: 0, @@ -336,7 +336,7 @@ mod tests { #[test] fn mi450x_identity() { let a = mi450x(); - assert_eq!(a.vm.arch, "gfx1250"); + assert_eq!(a.vm.arch, "cdna5"); assert_eq!(a.vm.gpu.device.marketing_name, "gfx1250"); assert_eq!(a.vm.gpu.device.gfx_target_version, 120500); assert_eq!(a.topology.links.len(), 6); diff --git a/emulation/rocjitsu/configs/gfx1250.json b/emulation/rocjitsu/configs/gfx1250_mi455x.json similarity index 99% rename from emulation/rocjitsu/configs/gfx1250.json rename to emulation/rocjitsu/configs/gfx1250_mi455x.json index d7980a2ead1d..ff6a8336b913 100644 --- a/emulation/rocjitsu/configs/gfx1250.json +++ b/emulation/rocjitsu/configs/gfx1250_mi455x.json @@ -3,7 +3,7 @@ "num_threads": 1, "exec_mode": "functional", "vm": { - "arch": "gfx1250", + "arch": "cdna5", "gpu": { "device": { "gpu_id": 1250, diff --git a/emulation/rocjitsu/docs/codegen.md b/emulation/rocjitsu/docs/codegen.md index 9fbf6b95e9d1..8008bbdb0207 100644 --- a/emulation/rocjitsu/docs/codegen.md +++ b/emulation/rocjitsu/docs/codegen.md @@ -48,8 +48,9 @@ rocm-systems/shared/machine-readable-isa/isa/ | Cross-ISA legalization tables | `lib/rocjitsu/src/rocjitsu/code/dbt/generated/` | `legalization_codegen.py` | | Encoding decode/encode functions | `lib/rocjitsu/src/rocjitsu/code/dbt/generated/` | `encoding_translator_codegen.py` | -CDNA5's MR ISA name, logical architecture key, runtime target, ELF identity, -configuration, and public DBT target identity remain `gfx1250`. Its filesystem +CDNA5's logical generator key and configuration architecture are `cdna5`. Its +MR ISA name and filename, concrete GPU/runtime target, ELF identity, and public +DBT target identity intentionally remain `gfx1250`. Its filesystem directories, generated and hand-written C++ namespace (`rocjitsu::cdna5`), and internal CMake provider targets use `cdna5`. @@ -88,8 +89,9 @@ generated. ## Regenerating everything The repository helper derives the repository, shared MR ISA, and generated -output directories from its own location. Its argument is the CDNA5 MR ISA XML, -whose concrete GPU filename and logical architecture key remain `gfx1250`. +output directories from its own location. Its argument is the CDNA5 MR ISA XML +with the concrete filename `amdgpu_isa_gfx1250.xml`; the logical generator key +used by the command is `cdna5`. Activate a Python virtual environment containing the generator dependencies and `pre-commit`, then run this command from the `rocm-systems` repository root: @@ -122,7 +124,7 @@ python -m amdisa \ rdna3:$MRISA/amdgpu_isa_rdna3.xml \ rdna3_5:$MRISA/amdgpu_isa_rdna3_5.xml \ rdna4:$MRISA/amdgpu_isa_rdna4.xml \ - gfx1250:$CDNA5_MRISA/amdgpu_isa_gfx1250.xml \ + cdna5:$CDNA5_MRISA/amdgpu_isa_gfx1250.xml \ --isa-output lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated \ --dbt-output lib/rocjitsu/src/rocjitsu/code/dbt/generated @@ -144,7 +146,7 @@ python -m amdisa \ rdna3:$MRISA/amdgpu_isa_rdna3.xml \ rdna3_5:$MRISA/amdgpu_isa_rdna3_5.xml \ rdna4:$MRISA/amdgpu_isa_rdna4.xml \ - gfx1250:$CDNA5_MRISA/amdgpu_isa_gfx1250.xml \ + cdna5:$CDNA5_MRISA/amdgpu_isa_gfx1250.xml \ --gen-isas \ --isa-output lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated @@ -166,7 +168,7 @@ python -m amdisa \ rdna3:$MRISA/amdgpu_isa_rdna3.xml \ rdna3_5:$MRISA/amdgpu_isa_rdna3_5.xml \ rdna4:$MRISA/amdgpu_isa_rdna4.xml \ - gfx1250:$CDNA5_MRISA/amdgpu_isa_gfx1250.xml \ + cdna5:$CDNA5_MRISA/amdgpu_isa_gfx1250.xml \ --gen-dbt \ --dbt-output lib/rocjitsu/src/rocjitsu/code/dbt/generated diff --git a/emulation/rocjitsu/docs/configuration.md b/emulation/rocjitsu/docs/configuration.md index aa82b127c8f3..aab177c5d7c1 100644 --- a/emulation/rocjitsu/docs/configuration.md +++ b/emulation/rocjitsu/docs/configuration.md @@ -15,7 +15,7 @@ Pre-built simulator configs are in `configs/`: | `gfx950_cdna4.json` | Single CDNA4 GPU (standalone simulation) | | `gfx950_cdna4_kmd.json` | Single CDNA4 GPU (daemon/KFD mode) | | `gfx950_cdna4_kmd_2gpu.json` | Two CDNA4 GPUs (multi-GPU daemon mode) | -| `gfx1250.json` | Single gfx1250 GPU (standalone simulation, no KMD) | +| `gfx1250_mi455x.json` | Single CDNA5 GPU (standalone simulation, no KMD) | | `gfx1100_w7900.json` | Single RDNA3 GPU (standalone simulation) | | `gfx1151.json` | Single RDNA3.5 GPU (standalone simulation) | | `gfx1201_r9700.json` | Single RDNA4 GPU (standalone simulation) | diff --git a/emulation/rocjitsu/lib/python/amdisa/__init__.py b/emulation/rocjitsu/lib/python/amdisa/__init__.py index ffdb9545b593..27db316766bb 100644 --- a/emulation/rocjitsu/lib/python/amdisa/__init__.py +++ b/emulation/rocjitsu/lib/python/amdisa/__init__.py @@ -15,7 +15,7 @@ Cdna2Profile, CdnaProfile, EncodingModifier, - Gfx1250Profile, + Cdna5Profile, IsaProfile, MemoryCoherencyModel, MnemonicRule, @@ -47,7 +47,7 @@ 'CodeGenerator', 'CppFile', 'EncodingModifier', - 'Gfx1250Profile', + 'Cdna5Profile', 'InstEncoding', 'Instruction', 'IsaProfile', diff --git a/emulation/rocjitsu/lib/python/amdisa/__main__.py b/emulation/rocjitsu/lib/python/amdisa/__main__.py index b1129064e03b..8832c273942c 100644 --- a/emulation/rocjitsu/lib/python/amdisa/__main__.py +++ b/emulation/rocjitsu/lib/python/amdisa/__main__.py @@ -15,7 +15,7 @@ CdnaProfile, CodegenConfig, CodeGenerator, - Gfx1250Profile, + Cdna5Profile, Parser, Rdna1Profile, Rdna2Profile, @@ -51,7 +51,7 @@ 'rdna3': Rdna3Profile, 'rdna3.5': Rdna3_5Profile, 'rdna4': Rdna4Profile, - 'gfx1250': Gfx1250Profile, + 'cdna5': Cdna5Profile, } @@ -118,7 +118,7 @@ def _detect_profile(isa_xml: str) -> str: # TODO: Remove this filename override once the gfx1250 XML carries a # finalized architecture name that can be detected through the normal path. if 'gfx1250' in Path(isa_xml).stem: - return 'gfx1250' + return 'cdna5' root = elem_tree.parse(isa_xml).getroot() isa_node = xs.get_node(root, xs.ISA) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index f61092935625..457eaa36e047 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -872,7 +872,7 @@ def _uses_generic_wmma_accumulator_selector( self, inst_sem: InstructionSemantics | None, opnd: Operand ) -> bool: return ( - getattr(self.isa_spec, 'arch_name', None) == 'gfx1250' + getattr(self.isa_spec, 'arch_name', None) == 'cdna5' and inst_sem is not None and inst_sem.name in self._GENERIC_WMMA_ACCUMULATOR_INSTRUCTIONS and opnd.name == 'src2' @@ -2703,7 +2703,7 @@ def _max_instruction_word_count(self) -> int: if self._supports_generated_vopd(): maximum = max(maximum, 3) if ( - self._supports_gfx1250_scaled_wmma_vop3px2() + self._supports_cdna5_scaled_wmma_vop3px2() or self._supports_cdna_mfma_f8f6f4_vop3px2() ): maximum = max(maximum, 4) @@ -2736,7 +2736,7 @@ def gen_encodings(self) -> None: inst_enc.enc_name ) supports_fixed_size_embedding = ( - self._supports_gfx1250_scaled_wmma_vop3px2() + self._supports_cdna5_scaled_wmma_vop3px2() and inst_enc.fmt_enc_name == 'Vop3p' ) dpp_struct, dpp8_struct = self._vop_dpp_struct_names(inst_enc.enc_name) @@ -3932,9 +3932,9 @@ def _fixed_vgpr_msb_role( return None - def _supports_gfx1250_scaled_wmma_vop3px2(self) -> bool: + def _supports_cdna5_scaled_wmma_vop3px2(self) -> bool: return ( - self.isa_spec.arch_name.lower() == 'gfx1250' + self.isa_spec.arch_name.lower() == 'cdna5' and self.isa_spec.profile.generate_scaled_wmma_vop3px2 ) @@ -3947,10 +3947,10 @@ def _is_cdna_mfma_f8f6f4_vop3px2_suffix(self, inst: Instruction) -> bool: and inst.name in self.isa_spec.profile.inst_size_overrides ) - def _gfx1250_f8f6f4_wmma_shape( + def _cdna5_f8f6f4_wmma_shape( self, inst: Instruction ) -> tuple[int, int, int] | None: - if self.isa_spec.arch_name != 'gfx1250' or not inst.name.startswith('V_WMMA_'): + if self.isa_spec.arch_name != 'cdna5' or not inst.name.startswith('V_WMMA_'): return None m = re.match( r'V_WMMA_(?:F32|F16|BF16|I32)_(\d+)X(\d+)X(\d+)_?F8F6F4$', @@ -3970,12 +3970,10 @@ def _cdna4_f8f6f4_mfma_shape( return None return tuple(int(x) for x in m.groups()) - def _gfx1250_swmmac_has_modifiers(self, inst: Instruction) -> bool: - return self.isa_spec.arch_name == 'gfx1250' and inst.name.startswith( - 'V_SWMMAC_' - ) + def _cdna5_swmmac_has_modifiers(self, inst: Instruction) -> bool: + return self.isa_spec.arch_name == 'cdna5' and inst.name.startswith('V_SWMMAC_') - def _gfx1250_matrix_fmt_operand_size_expr( + def _cdna5_matrix_fmt_operand_size_expr( self, shape: tuple[int, int, int] | None, opnd_name: str ) -> str | None: if shape is None or opnd_name not in ('src0', 'src1'): @@ -3989,7 +3987,7 @@ def _gfx1250_matrix_fmt_operand_size_expr( '((reinterpret_cast(inst)->pad_14 << 2) | ' 'reinterpret_cast(inst)->opsel_hi)' ) - return f'gfx1250_matrix_fmt_operand_size_bits({fmt_expr}, {dim}, {k})' + return f'cdna5_matrix_fmt_operand_size_bits({fmt_expr}, {dim}, {k})' @staticmethod def _cdna4_matrix_fmt_operand_size_expr( @@ -4096,7 +4094,7 @@ def _emit_cdna4_matrix_fmt_helpers() -> str: } // namespace''') @staticmethod - def _emit_gfx1250_matrix_fmt_helpers() -> _ImplOutputs: + def _emit_cdna5_matrix_fmt_helpers() -> _ImplOutputs: """Emit C++ helpers for gfx1250 VOP3P packed and matrix quirks.""" execution = textwrap.dedent('''\ namespace { @@ -4118,7 +4116,7 @@ def _emit_gfx1250_matrix_fmt_helpers() -> _ImplOutputs: model = ( 'namespace {\n\n' + ( - 'const char *gfx1250_matrix_fmt_name(uint32_t fmt) {\n' + 'const char *cdna5_matrix_fmt_name(uint32_t fmt) {\n' ' switch (fmt) {\n' ' case 0:\n' ' return "MATRIX_FMT_FP8";\n' @@ -4135,7 +4133,7 @@ def _emit_gfx1250_matrix_fmt_helpers() -> _ImplOutputs: ' }\n' '}\n' '\n' - 'const char *gfx1250_matrix_scale_fmt_name(uint32_t fmt) {\n' + 'const char *cdna5_matrix_scale_fmt_name(uint32_t fmt) {\n' ' switch (fmt) {\n' ' case 0:\n' ' return "MATRIX_SCALE_FMT_E8";\n' @@ -4148,7 +4146,7 @@ def _emit_gfx1250_matrix_fmt_helpers() -> _ImplOutputs: ' }\n' '}\n' '\n' - 'uint32_t gfx1250_matrix_fmt_element_bits(uint32_t fmt) {\n' + 'uint32_t cdna5_matrix_fmt_element_bits(uint32_t fmt) {\n' ' switch (fmt) {\n' ' case 2:\n' ' case 3:\n' @@ -4160,46 +4158,46 @@ def _emit_gfx1250_matrix_fmt_helpers() -> _ImplOutputs: ' }\n' '}\n' '\n' - 'int gfx1250_matrix_fmt_operand_size_bits(uint32_t fmt, uint32_t dim, uint32_t k) {\n' - ' return static_cast((dim * k * gfx1250_matrix_fmt_element_bits(fmt)) / 32);\n' + 'int cdna5_matrix_fmt_operand_size_bits(uint32_t fmt, uint32_t dim, uint32_t k) {\n' + ' return static_cast((dim * k * cdna5_matrix_fmt_element_bits(fmt)) / 32);\n' '}\n' '\n' - 'bool gfx1250_scaled_wmma_is_scale16(const MachineInst *inst) {\n' + 'bool cdna5_scaled_wmma_is_scale16(const MachineInst *inst) {\n' ' return reinterpret_cast(inst)->op == 0x3a;\n' '}\n' '\n' - 'bool gfx1250_scaled_wmma_is_f4_32x16x128(const MachineInst *inst) {\n' + 'bool cdna5_scaled_wmma_is_f4_32x16x128(const MachineInst *inst) {\n' ' return reinterpret_cast(inst + 2)->op == 0x88;\n' '}\n' '\n' - 'const char *gfx1250_scaled_wmma_mnemonic(const MachineInst *inst) {\n' - ' if (gfx1250_scaled_wmma_is_f4_32x16x128(inst))\n' - ' return gfx1250_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_32x16x128_f4"\n' + 'const char *cdna5_scaled_wmma_mnemonic(const MachineInst *inst) {\n' + ' if (cdna5_scaled_wmma_is_f4_32x16x128(inst))\n' + ' return cdna5_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_32x16x128_f4"\n' ' : "v_wmma_scale_f32_32x16x128_f4";\n' - ' return gfx1250_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_16x16x128_f8f6f4"\n' + ' return cdna5_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_16x16x128_f8f6f4"\n' ' : "v_wmma_scale_f32_16x16x128_f8f6f4";\n' '}\n' '\n' - 'int gfx1250_scale_operand_size_bits(const MachineInst *inst) {\n' - ' return gfx1250_scaled_wmma_is_scale16(inst) ? 64 : 32;\n' + 'int cdna5_scale_operand_size_bits(const MachineInst *inst) {\n' + ' return cdna5_scaled_wmma_is_scale16(inst) ? 64 : 32;\n' '}\n' '\n' - 'int gfx1250_scaled_wmma_dst_size_bits(const MachineInst *inst) {\n' - ' return gfx1250_scaled_wmma_is_f4_32x16x128(inst) ? 512 : 256;\n' + 'int cdna5_scaled_wmma_dst_size_bits(const MachineInst *inst) {\n' + ' return cdna5_scaled_wmma_is_f4_32x16x128(inst) ? 512 : 256;\n' '}\n' '\n' - 'int gfx1250_scaled_wmma_src0_size_bits(const MachineInst *inst) {\n' + 'int cdna5_scaled_wmma_src0_size_bits(const MachineInst *inst) {\n' ' const auto *high = reinterpret_cast(inst + 2);\n' - ' if (gfx1250_scaled_wmma_is_f4_32x16x128(inst))\n' + ' if (cdna5_scaled_wmma_is_f4_32x16x128(inst))\n' ' return 512;\n' - ' return gfx1250_matrix_fmt_operand_size_bits(high->opsel, 16, 128);\n' + ' return cdna5_matrix_fmt_operand_size_bits(high->opsel, 16, 128);\n' '}\n' '\n' - 'int gfx1250_scaled_wmma_src1_size_bits(const MachineInst *inst) {\n' + 'int cdna5_scaled_wmma_src1_size_bits(const MachineInst *inst) {\n' ' const auto *high = reinterpret_cast(inst + 2);\n' - ' if (gfx1250_scaled_wmma_is_f4_32x16x128(inst))\n' + ' if (cdna5_scaled_wmma_is_f4_32x16x128(inst))\n' ' return 256;\n' - ' return gfx1250_matrix_fmt_operand_size_bits((high->pad_14 << 2) | high->opsel_hi, 16, 128);\n' + ' return cdna5_matrix_fmt_operand_size_bits((high->pad_14 << 2) | high->opsel_hi, 16, 128);\n' '}\n' ) + '\n} // namespace' @@ -4265,7 +4263,7 @@ def _emit_gfx1250_matrix_fmt_helpers() -> _ImplOutputs: return _ImplOutputs(model=[model], execution=[execution]) @staticmethod - def _emit_gfx1250_scaled_wmma_vop3px2_class() -> str: + def _emit_cdna5_scaled_wmma_vop3px2_class() -> str: return textwrap.dedent('''\ class VWmmaScaleF32Vop3px2 : public Vop3p { public: @@ -4284,23 +4282,23 @@ class VWmmaScaleF32Vop3px2 : public Vop3p { }; ''') - def _emit_gfx1250_scaled_wmma_vop3px2_impls(self) -> _ImplOutputs: + def _emit_cdna5_scaled_wmma_vop3px2_impls(self) -> _ImplOutputs: exec_fn = self._split_execute_expr('VWmmaScaleF32Vop3px2') model = textwrap.dedent('''\ VWmmaScaleF32Vop3px2::VWmmaScaleF32Vop3px2(const MachineInst *inst) - : Vop3p(gfx1250_scaled_wmma_mnemonic(inst), reinterpret_cast(inst + 2), + : Vop3p(cdna5_scaled_wmma_mnemonic(inst), reinterpret_cast(inst + 2), @EXEC_FN@, Vop3p::ExtensionDecodePolicy::Skip), - vdst(gfx1250_scaled_wmma_dst_size_bits(inst), OperandType::OPR_VGPR, + vdst(cdna5_scaled_wmma_dst_size_bits(inst), OperandType::OPR_VGPR, reinterpret_cast(inst + 2)->vdst), - src0(gfx1250_scaled_wmma_src0_size_bits(inst), OperandType::OPR_SRC_VGPR, + src0(cdna5_scaled_wmma_src0_size_bits(inst), OperandType::OPR_SRC_VGPR, reinterpret_cast(inst + 2)->src0), - src1(gfx1250_scaled_wmma_src1_size_bits(inst), OperandType::OPR_SRC_VGPR, + src1(cdna5_scaled_wmma_src1_size_bits(inst), OperandType::OPR_SRC_VGPR, reinterpret_cast(inst + 2)->src1), - src2(gfx1250_scaled_wmma_dst_size_bits(inst), OperandType::OPR_SRC_VGPR_OR_INLINE, + src2(cdna5_scaled_wmma_dst_size_bits(inst), OperandType::OPR_SRC_VGPR_OR_INLINE, reinterpret_cast(inst + 2)->src2), - scale_src0(gfx1250_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, + scale_src0(cdna5_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, reinterpret_cast(inst)->src0), - scale_src1(gfx1250_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, + scale_src1(cdna5_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, reinterpret_cast(inst)->src1), scale_inst_(*reinterpret_cast(inst)) { raw_words_ = {inst[0], inst[1], inst[2], inst[3]}; @@ -4329,11 +4327,11 @@ def _emit_gfx1250_scaled_wmma_vop3px2_impls(self) -> _ImplOutputs: const uint32_t matrix_b_fmt = (inst_.pad_14 << 2) | inst_.opsel_hi; if (matrix_a_fmt != 0) { out += " matrix_a_fmt:"; - out += gfx1250_matrix_fmt_name(matrix_a_fmt); + out += cdna5_matrix_fmt_name(matrix_a_fmt); } if (matrix_b_fmt != 0) { out += " matrix_b_fmt:"; - out += gfx1250_matrix_fmt_name(matrix_b_fmt); + out += cdna5_matrix_fmt_name(matrix_b_fmt); } } if (scale_inst_.opsel & 0x1u) @@ -4344,11 +4342,11 @@ def _emit_gfx1250_scaled_wmma_vop3px2_impls(self) -> _ImplOutputs: const uint32_t matrix_b_scale_fmt = scale_inst_.neg_hi & 0x3u; if (matrix_a_scale_fmt != 0) { out += " matrix_a_scale_fmt:"; - out += gfx1250_matrix_scale_fmt_name(matrix_a_scale_fmt); + out += cdna5_matrix_scale_fmt_name(matrix_a_scale_fmt); } if (matrix_b_scale_fmt != 0) { out += " matrix_b_scale_fmt:"; - out += gfx1250_matrix_scale_fmt_name(matrix_b_scale_fmt); + out += cdna5_matrix_scale_fmt_name(matrix_b_scale_fmt); } if ((scale_inst_.opsel >> 2) & 0x1u) out += " matrix_a_reuse"; @@ -4431,7 +4429,7 @@ def _emit_gfx1250_scaled_wmma_vop3px2_impls(self) -> _ImplOutputs: return _ImplOutputs(model=[model], execution=[execution]) @staticmethod - def _emit_gfx1250_scaled_wmma_vop3px2_decoder_helpers() -> str: + def _emit_cdna5_scaled_wmma_vop3px2_decoder_helpers() -> str: return textwrap.dedent('''\ namespace { @@ -5483,7 +5481,7 @@ def _semantic_reg_class(opnd: Operand) -> RegClass: or cls == 'vector_cvt_sr_fp8_f16' ) and is_vop3 - and self.isa_spec.arch_name.lower() == 'gfx1250' + and self.isa_spec.arch_name.lower() == 'cdna5' else None ) return gen_vector_cvt_pk( @@ -6324,7 +6322,7 @@ def _append_global_addtid_addresses(self, L: list[str]) -> None: L.append(' uint64_t base = amdgpu::RegisterAccess(wf).read_scalar64(saddr);') offset_expr = ( 'signed_ioffset(inst_.ioffset)' - if self.isa_spec.arch_name == 'gfx1250' + if self.isa_spec.arch_name == 'cdna5' else 'static_cast(inst_.ioffset << 8) >> 8' ) L.append(f' int64_t offset = static_cast({offset_expr});') @@ -7857,19 +7855,17 @@ def gen_insts(self) -> None: d16_partial_reg_offset = d16_vgpr_count - 1 # These gfx1250-only WMMA source-format fields derive the # src0/src1 operand sizes from the instruction shape. - gfx1250_f8f6f4_shape = self._gfx1250_f8f6f4_wmma_shape(inst) + cdna5_f8f6f4_shape = self._cdna5_f8f6f4_wmma_shape(inst) cdna4_f8f6f4_shape = self._cdna4_f8f6f4_mfma_shape(inst) - gfx1250_swmmac_has_modifiers = self._gfx1250_swmmac_has_modifiers( - inst - ) + cdna5_swmmac_has_modifiers = self._cdna5_swmmac_has_modifiers(inst) operand_size_exprs: dict[str, str] = {} for opnd in inst.operands: opnd_size_expr = self._operand_size_override( enc.enc_name, opnd, inst_sem ) if opnd_size_expr is None: - opnd_size_expr = self._gfx1250_matrix_fmt_operand_size_expr( - gfx1250_f8f6f4_shape, opnd.name + opnd_size_expr = self._cdna5_matrix_fmt_operand_size_expr( + cdna5_f8f6f4_shape, opnd.name ) if opnd_size_expr is None: opnd_size_expr = self._cdna4_matrix_fmt_operand_size_expr( @@ -7892,7 +7888,7 @@ def gen_insts(self) -> None: # here makes def/use and liveness falsely clobber the # following SGPR. if ( - self.isa_spec.arch_name == 'gfx1250' + self.isa_spec.arch_name == 'cdna5' and inst_sem is not None and inst_sem.semantic_class in ('vector_cmp', 'vector_cmp_class') @@ -8196,7 +8192,7 @@ def gen_insts(self) -> None: 'void implicit_uses(RegisterSet &uses) const override' ) ) - if gfx1250_f8f6f4_shape is not None or gfx1250_swmmac_has_modifiers: + if cdna5_f8f6f4_shape is not None or cdna5_swmmac_has_modifiers: public_members.append( cgen.Statement( 'void build_modifiers(std::string &out) const override' @@ -9501,18 +9497,18 @@ def _dpp_write_mask_lines( '} // namespace detail' ) ) - if gfx1250_f8f6f4_shape is not None: + if cdna5_f8f6f4_shape is not None: inst_impls.append( cgen.Line( f'void {inst.fmt_name}::build_modifiers(std::string &out) const {{\n' f' out += " matrix_a_fmt:";\n' - f' out += gfx1250_matrix_fmt_name(inst_.opsel);\n' + f' out += cdna5_matrix_fmt_name(inst_.opsel);\n' f' out += " matrix_b_fmt:";\n' - f' out += gfx1250_matrix_fmt_name((inst_.pad_14 << 2) | inst_.opsel_hi);\n' + f' out += cdna5_matrix_fmt_name((inst_.pad_14 << 2) | inst_.opsel_hi);\n' f'}}' ) ) - elif gfx1250_swmmac_has_modifiers: + elif cdna5_swmmac_has_modifiers: inst_impls.append( cgen.Line( f'void {inst.fmt_name}::build_modifiers(std::string &out) const {{\n' @@ -9871,16 +9867,16 @@ def _delegates_to_shared(i: Instruction) -> bool: if _has_size_overrides: h_includes.append(('array', True)) if ( - self._supports_gfx1250_scaled_wmma_vop3px2() + self._supports_cdna5_scaled_wmma_vop3px2() and enc.enc_name.upper() == 'ENC_VOP3P' ): if not _has_size_overrides: h_includes.append(('array', True)) cpp_includes.append(('array', True)) inst_classes.append( - cgen.Line(self._emit_gfx1250_scaled_wmma_vop3px2_class()) + cgen.Line(self._emit_cdna5_scaled_wmma_vop3px2_class()) ) - scaled_outputs = self._emit_gfx1250_scaled_wmma_vop3px2_impls() + scaled_outputs = self._emit_cdna5_scaled_wmma_vop3px2_impls() class_func_impls.model.extend( cgen.Line(impl) for impl in scaled_outputs.model ) @@ -9903,10 +9899,10 @@ def _delegates_to_shared(i: Instruction) -> bool: # from data_types.h (included via cpp_includes when has_sem). if ( - self.isa_spec.arch_name.lower() == 'gfx1250' + self.isa_spec.arch_name.lower() == 'cdna5' and enc.enc_name.upper() == 'ENC_VOP3P' ): - matrix_outputs = self._emit_gfx1250_matrix_fmt_helpers() + matrix_outputs = self._emit_cdna5_matrix_fmt_helpers() class_func_impls.model[0:0] = [ cgen.Line(impl) for impl in matrix_outputs.model ] @@ -12679,9 +12675,9 @@ def gen_decoder(self) -> None: ), ] decode_body = [] - if self._supports_gfx1250_scaled_wmma_vop3px2(): + if self._supports_cdna5_scaled_wmma_vop3px2(): class_impl.append( - cgen.Line(self._emit_gfx1250_scaled_wmma_vop3px2_decoder_helpers()) + cgen.Line(self._emit_cdna5_scaled_wmma_vop3px2_decoder_helpers()) ) decode_body.extend( [ @@ -12773,7 +12769,7 @@ def _reserve_primary_prefix(prefix: int, prefix_bits: int, fn: str) -> None: ] ) - if self._supports_gfx1250_scaled_wmma_vop3px2(): + if self._supports_cdna5_scaled_wmma_vop3px2(): for _dte in self.isa_spec.primary_decode_table: if ( _dte is not None diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py index 0bd380c35560..9ab84a3c002c 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py @@ -179,7 +179,7 @@ def _register_handlers() -> None: c.dtype, ( c.opsel_exprs[0] - if c.arch_name == 'gfx1250' and c.is_vop3 and c.dtype == 'b16' + if c.arch_name == 'cdna5' and c.is_vop3 and c.dtype == 'b16' else None ), ) @@ -221,7 +221,7 @@ def _register_handlers() -> None: if c.cls == 'vector_cvt_pk' and c.op in ('fp8_f32', 'fp8_f16') and c.is_vop3 - and c.arch_name == 'gfx1250' + and c.arch_name == 'cdna5' else None ), arch_name=c.arch_name, @@ -249,7 +249,7 @@ def _register_handlers() -> None: c.src_ops, c.op, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['pk_ternary_f32'] = lambda c: gen_pk_ternary_f32( c.dst_ops, @@ -257,7 +257,7 @@ def _register_handlers() -> None: c.op, op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['pk_mov_b32'] = lambda c: gen_pk_mov_b32( c.dst_ops, @@ -269,7 +269,7 @@ def _register_handlers() -> None: c.src_ops, op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['mad_mixlo_f16'] = lambda c: gen_mad_mix_lo_hi( c.dst_ops, @@ -277,7 +277,7 @@ def _register_handlers() -> None: is_lo=True, op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['mad_mixhi_f16'] = lambda c: gen_mad_mix_lo_hi( c.dst_ops, @@ -285,7 +285,7 @@ def _register_handlers() -> None: is_lo=False, op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['mad_mix_f32_bf16'] = lambda c: gen_mad_mix_bf16( c.dst_ops, @@ -293,7 +293,7 @@ def _register_handlers() -> None: result='f32', op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['mad_mixlo_bf16'] = lambda c: gen_mad_mix_bf16( c.dst_ops, @@ -301,7 +301,7 @@ def _register_handlers() -> None: result='lo', op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['mad_mixhi_bf16'] = lambda c: gen_mad_mix_bf16( c.dst_ops, @@ -309,7 +309,7 @@ def _register_handlers() -> None: result='hi', op_sel_hi_2_expr=c.op_sel_hi_2_expr, opsel_exprs=c.opsel_exprs, - use_gfx1250_helpers=c.arch_name == 'gfx1250', + use_cdna5_helpers=c.arch_name == 'cdna5', ) DISPATCH['dot2'] = lambda c: gen_dot2( c.dst_ops, c.src_ops, c.cls, opsel_exprs=c.opsel_exprs diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/matrix.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/matrix.py index 712e4823ac07..5f9b6a754f1e 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/matrix.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/matrix.py @@ -38,7 +38,7 @@ def _f8_bools(input_type: str) -> tuple[str, str]: ) -def _gfx1250_wmma_spec( +def _cdna5_wmma_spec( result_type: str, input_type: str, M: int, N: int, K: int ) -> str | None: """Specialized gfx1250 (wave32) dense-WMMA kernel name for a given shape, @@ -265,7 +265,7 @@ def gen_mfma( uses_gfx11_wmma_layout = arch in ('rdna3', 'rdna3_5') and is_dense_wmma uses_gfx12_wmma_layout = arch == 'rdna4' and is_dense_wmma swmmac_index_entries = 32 if is_swmmac and K >= 128 and in_bits <= 8 else 16 - if arch == 'gfx1250': + if arch == 'cdna5': L.append( f' uint32_t dst = vb + *Isa::resolved_vgpr_offset(wf, {d}.opr_type_, ' f'{d}.encoding_value_, {d}.vgpr_msb_role());' @@ -332,7 +332,7 @@ def gen_mfma( if result_type == 'F64': L.append(f' amdgpu::exec_f64(cu, {M}, {N}, {K}, {B}, dst,') - if arch == 'gfx1250': + if arch == 'cdna5': L.append(f' src0_base,') L.append(f' src1_base,') else: @@ -360,7 +360,7 @@ def append_signed_extractors(suffix: str) -> None: ) L.append(f' }};') - if arch == 'gfx1250': + if arch == 'cdna5': # LLVM's gfx1250 IU WMMA convention overloads neg_lo: bit set means # signed extension, bit clear means unsigned. if is_swmmac: @@ -478,7 +478,7 @@ def append_signed_extractors(suffix: str) -> None: else: # F32, F16, and BF16 matrix results accumulate in f32. gfx1250 WMMA # uses a wave32 layout; CDNA MFMA uses the GFX9 MFMA layout helpers. - if arch == 'gfx1250' and input_type in ('F8_F6_F4', 'F8F6F4'): + if arch == 'cdna5' and input_type in ('F8_F6_F4', 'F8F6F4'): L.append(f' uint32_t matrix_a_fmt = inst_.opsel;') L.append(f' uint32_t matrix_b_fmt = (inst_.pad_14 << 2) | inst_.opsel_hi;') L.append( @@ -507,7 +507,7 @@ def append_signed_extractors(suffix: str) -> None: # CDNA1-4 VOP3P_MFMA encoding has cbsz/abid/blgp fields for # A-matrix broadcast and B-matrix lane permutation. RDNA does # not have MFMA (only WMMA), so these fields don't exist. - if arch == 'gfx1250': + if arch == 'cdna5': if is_swmmac: if result_type == 'F16': exec_fn = 'exec_swmmac_f16' @@ -523,7 +523,7 @@ def append_signed_extractors(suffix: str) -> None: else: # Dense WMMA: a specialized wave32 kernel where one exists, else # the generic exec_wmma_* runtime path. - spec = _gfx1250_wmma_spec(result_type, input_type, M, N, K) + spec = _cdna5_wmma_spec(result_type, input_type, M, N, K) if spec is not None: if result_type in ('F32', 'BF16F32'): L.append( diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/packed.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/packed.py index f4832f4ac889..fd627b53c2c5 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/packed.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/packed.py @@ -17,10 +17,10 @@ def _append_pk_f32_pair_read( - L: list[str], var: str, src: str, use_gfx1250_helpers: bool = False + L: list[str], var: str, src: str, use_cdna5_helpers: bool = False ) -> None: """Read a packed F32 operand as a pair of 32-bit words.""" - if use_gfx1250_helpers: + if use_cdna5_helpers: L.append(f' const auto {var} = read_pk_f32_words({src}, wf, lane);') return L.append( @@ -38,8 +38,8 @@ def _append_pk_f32_pair_read( L.append(' }') -def _pk_f32_word_expr(var: str, half: str, use_gfx1250_helpers: bool = False) -> str: - if use_gfx1250_helpers: +def _pk_f32_word_expr(var: str, half: str, use_cdna5_helpers: bool = False) -> str: + if use_cdna5_helpers: return f'{var}.{half}' return f'{var}_{half}_w' @@ -402,7 +402,7 @@ def gen_pk_binop_f32( src: list[str], op: str | None, opsel_exprs: tuple[str, str] = ('', ''), - use_gfx1250_helpers: bool = False, + use_cdna5_helpers: bool = False, ) -> str: """Generate packed F32 binary op (V_PK_ADD_F32, V_PK_MUL_F32). @@ -417,15 +417,15 @@ def gen_pk_binop_f32( L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') for var, src in [('s0', s0), ('s1', s1)]: - _append_pk_f32_pair_read(L, var, src, use_gfx1250_helpers) + _append_pk_f32_pair_read(L, var, src, use_cdna5_helpers) L.append(f' bool sel0_lo = ({opsel} >> 0) & 1;') L.append(f' bool sel1_lo = ({opsel} >> 1) & 1;') L.append(f' bool sel0_hi = ({opsel_hi} >> 0) & 1;') L.append(f' bool sel1_hi = ({opsel_hi} >> 1) & 1;') - s0_lo = _pk_f32_word_expr('s0', 'lo', use_gfx1250_helpers) - s0_hi = _pk_f32_word_expr('s0', 'hi', use_gfx1250_helpers) - s1_lo = _pk_f32_word_expr('s1', 'lo', use_gfx1250_helpers) - s1_hi = _pk_f32_word_expr('s1', 'hi', use_gfx1250_helpers) + s0_lo = _pk_f32_word_expr('s0', 'lo', use_cdna5_helpers) + s0_hi = _pk_f32_word_expr('s0', 'hi', use_cdna5_helpers) + s1_lo = _pk_f32_word_expr('s1', 'lo', use_cdna5_helpers) + s1_hi = _pk_f32_word_expr('s1', 'hi', use_cdna5_helpers) L.append(f' float a_lo = std::bit_cast(sel0_lo ? {s0_hi} : {s0_lo});') L.append(f' float a_hi = std::bit_cast(sel0_hi ? {s0_hi} : {s0_lo});') L.append(f' float b_lo = std::bit_cast(sel1_lo ? {s1_hi} : {s1_lo});') @@ -454,7 +454,7 @@ def gen_pk_ternary_f32( op: str | None, op_sel_hi_2_expr: str = '', opsel_exprs: tuple[str, str] = ('', ''), - use_gfx1250_helpers: bool = False, + use_cdna5_helpers: bool = False, ) -> str: """Generate packed F32 ternary op (V_PK_FMA_F32). @@ -469,19 +469,19 @@ def gen_pk_ternary_f32( L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') for var, src in [('s0', s0), ('s1', s1), ('s2', s2)]: - _append_pk_f32_pair_read(L, var, src, use_gfx1250_helpers) + _append_pk_f32_pair_read(L, var, src, use_cdna5_helpers) L.append(f' bool sel0_lo = ({opsel} >> 0) & 1;') L.append(f' bool sel1_lo = ({opsel} >> 1) & 1;') L.append(f' bool sel2_lo = ({opsel} >> 2) & 1;') L.append(f' bool sel0_hi = ({opsel_hi} >> 0) & 1;') L.append(f' bool sel1_hi = ({opsel_hi} >> 1) & 1;') L.append(f' bool sel2_hi = {opsel_hi_2};') - s0_lo = _pk_f32_word_expr('s0', 'lo', use_gfx1250_helpers) - s0_hi = _pk_f32_word_expr('s0', 'hi', use_gfx1250_helpers) - s1_lo = _pk_f32_word_expr('s1', 'lo', use_gfx1250_helpers) - s1_hi = _pk_f32_word_expr('s1', 'hi', use_gfx1250_helpers) - s2_lo = _pk_f32_word_expr('s2', 'lo', use_gfx1250_helpers) - s2_hi = _pk_f32_word_expr('s2', 'hi', use_gfx1250_helpers) + s0_lo = _pk_f32_word_expr('s0', 'lo', use_cdna5_helpers) + s0_hi = _pk_f32_word_expr('s0', 'hi', use_cdna5_helpers) + s1_lo = _pk_f32_word_expr('s1', 'lo', use_cdna5_helpers) + s1_hi = _pk_f32_word_expr('s1', 'hi', use_cdna5_helpers) + s2_lo = _pk_f32_word_expr('s2', 'lo', use_cdna5_helpers) + s2_hi = _pk_f32_word_expr('s2', 'hi', use_cdna5_helpers) L.append(f' float a_lo = std::bit_cast(sel0_lo ? {s0_hi} : {s0_lo});') L.append(f' float a_hi = std::bit_cast(sel0_hi ? {s0_hi} : {s0_lo});') L.append(f' float b_lo = std::bit_cast(sel1_lo ? {s1_hi} : {s1_lo});') @@ -541,7 +541,7 @@ def gen_mad_mix_f32( src: list[str], op_sel_hi_2_expr: str = '', opsel_exprs: tuple[str, str] = ('', ''), - use_gfx1250_helpers: bool = False, + use_cdna5_helpers: bool = False, ) -> str: """Generate V_MAD_MIX_F32: mixed-precision FMA with op_sel selecting f16/f32 per src.""" d, s0, s1, s2 = dst[0], src[0], src[1], src[2] @@ -549,7 +549,7 @@ def gen_mad_mix_f32( L.append(' uint64_t exec = wf.exec();') L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') - if use_gfx1250_helpers: + if use_cdna5_helpers: L.append( f' float a = read_fma_mix_source_f32({s0}, wf, lane, inst_.src0, inst_.opsel_hi & 1, inst_.opsel & 1);' ) @@ -600,7 +600,7 @@ def gen_mad_mix_f32( L.append(' if (inst_.neg & 2) b = -b;') L.append(' if (inst_.neg & 4) c = -c;') L.append( - f' float result = {"std::fma(a, b, c)" if use_gfx1250_helpers else "a * b + c"};' + f' float result = {"std::fma(a, b, c)" if use_cdna5_helpers else "a * b + c"};' ) L.append(' if (inst_.clamp) result = std::clamp(result, 0.0f, 1.0f);') L.append( @@ -616,7 +616,7 @@ def gen_mad_mix_lo_hi( is_lo: bool, op_sel_hi_2_expr: str = '', opsel_exprs: tuple[str, str] = ('', ''), - use_gfx1250_helpers: bool = False, + use_cdna5_helpers: bool = False, ) -> str: """Generate V_MAD_MIXLO_F16 / V_MAD_MIXHI_F16.""" d, s0, s1, s2 = dst[0], src[0], src[1], src[2] @@ -624,7 +624,7 @@ def gen_mad_mix_lo_hi( L.append(' uint64_t exec = wf.exec();') L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') - if use_gfx1250_helpers: + if use_cdna5_helpers: L.append( f' float a = read_fma_mix_source_f32({s0}, wf, lane, inst_.src0, inst_.opsel_hi & 1, inst_.opsel & 1);' ) @@ -675,7 +675,7 @@ def gen_mad_mix_lo_hi( L.append(' if (inst_.neg & 2) b = -b;') L.append(' if (inst_.neg & 4) c = -c;') L.append( - f' float result = {"std::fma(a, b, c)" if use_gfx1250_helpers else "a * b + c"};' + f' float result = {"std::fma(a, b, c)" if use_cdna5_helpers else "a * b + c"};' ) L.append(' if (inst_.clamp) result = std::clamp(result, 0.0f, 1.0f);') L.append(f' uint16_t h = util::f32_to_f16_mode(result, wf.fp16_ovfl());') @@ -697,7 +697,7 @@ def gen_mad_mix_bf16( result: str, op_sel_hi_2_expr: str = '', opsel_exprs: tuple[str, str] = ('', ''), - use_gfx1250_helpers: bool = False, + use_cdna5_helpers: bool = False, ) -> str: """Generate gfx1250 BF16 FMA_MIX variants.""" d, s0, s1, s2 = dst[0], src[0], src[1], src[2] @@ -705,7 +705,7 @@ def gen_mad_mix_bf16( L.append(' uint64_t exec = wf.exec();') L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') L.append(' if (!(exec & (1ULL << lane))) continue;') - if use_gfx1250_helpers: + if use_cdna5_helpers: L.append( f' float a = read_fma_mix_bf16_source_f32({s0}, wf, lane, inst_.src0, inst_.opsel_hi & 1, inst_.opsel & 1);' ) diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py index 44eccdbbb637..e1479c7bc876 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py @@ -1655,9 +1655,7 @@ def gen_cvt_fp8(ctx) -> str: src = ctx.src_ops is_vop3 = ctx.is_vop3 opsel = _opsel_field(ctx) if is_vop3 else '0u' - fp8_format_select = ( - 'inst_.clamp' if is_vop3 and ctx.arch_name == 'gfx1250' else None - ) + fp8_format_select = 'inst_.clamp' if is_vop3 and ctx.arch_name == 'cdna5' else None L = [] L.append(' uint64_t exec = wf.exec();') diff --git a/emulation/rocjitsu/lib/python/amdisa/isa_profile.py b/emulation/rocjitsu/lib/python/amdisa/isa_profile.py index a1c631e3ad18..045c8e3c2bf8 100644 --- a/emulation/rocjitsu/lib/python/amdisa/isa_profile.py +++ b/emulation/rocjitsu/lib/python/amdisa/isa_profile.py @@ -155,7 +155,7 @@ class VopdEncodingPrefix: VopdSlotOp('VopdAndB32', 18, 'v_dual_and_b32'), ) -_GFX1250_VOPD_SLOT_OPS = _VOPD_COMMON_F32_SLOT_OPS + ( +_CDNA5_VOPD_SLOT_OPS = _VOPD_COMMON_F32_SLOT_OPS + ( VopdSlotOp('VopdMaxNumF32', 10, 'v_dual_max_num_f32'), VopdSlotOp('VopdMinNumF32', 11, 'v_dual_min_num_f32'), VopdSlotOp('VopdAddNcU32', 16, 'v_dual_add_nc_u32'), @@ -1716,17 +1716,17 @@ def encoding_modifiers(self, enc_name: str) -> list[EncodingModifier]: return [] -class Gfx1250Profile(Rdna4Profile): +class Cdna5Profile(Rdna4Profile): """ISA profile for gfx1250. - The gfx1250 encoding model is RDNA4/GFX12-like. Keep ``gfx1250`` as the + The gfx1250 encoding model is RDNA4/GFX12-like. Use ``cdna5`` as the logical target used by parser/codegen rules while generated and handwritten C++ lives under ``amdgpu/cdna5`` in the ``cdna5`` namespace. """ @property def generated_arch_name(self) -> str | None: - return 'gfx1250' + return 'cdna5' @property def generated_dir_name(self) -> str | None: @@ -1843,7 +1843,7 @@ def vopd_encoding_prefixes(self) -> tuple[VopdEncodingPrefix, ...]: @property def vopd_slot_ops(self) -> tuple[VopdSlotOp, ...]: - return _GFX1250_VOPD_SLOT_OPS + return _CDNA5_VOPD_SLOT_OPS @property def vopd_x_slot_opcodes(self) -> frozenset[int]: diff --git a/emulation/rocjitsu/lib/python/amdisa/isa_properties_codegen.py b/emulation/rocjitsu/lib/python/amdisa/isa_properties_codegen.py index 9544c324304a..3fc0d958c258 100644 --- a/emulation/rocjitsu/lib/python/amdisa/isa_properties_codegen.py +++ b/emulation/rocjitsu/lib/python/amdisa/isa_properties_codegen.py @@ -15,7 +15,7 @@ 'rdna3', 'rdna3_5', 'rdna4', - 'gfx1250', + 'cdna5', ) diff --git a/emulation/rocjitsu/lib/python/amdisa/parser.py b/emulation/rocjitsu/lib/python/amdisa/parser.py index ef3bea0fe8f1..d9c12413f741 100644 --- a/emulation/rocjitsu/lib/python/amdisa/parser.py +++ b/emulation/rocjitsu/lib/python/amdisa/parser.py @@ -433,7 +433,7 @@ def _collect_fieldless_operand_types(self) -> None: def _inject_compat_insts(self) -> None: """Add instructions accepted by LLVM but missing from selected XML specs.""" - if self.isa_spec.arch_name not in {'rdna4', 'gfx1250'}: + if self.isa_spec.arch_name not in {'rdna4', 'cdna5'}: return # The RDNA4/GFX12 XML only lists split S_WAIT_* instructions, but LLVM diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py index fd8b7041b5d5..5dcd572afb90 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_generator_profile_gates.py @@ -38,7 +38,7 @@ Cdna1Profile, Cdna2Profile, CdnaProfile, - Gfx1250Profile, + Cdna5Profile, Rdna1Profile, Rdna2Profile, Rdna3_5Profile, @@ -93,13 +93,13 @@ def execute_shared_path(amdgpu_generated_root: Path) -> Path: @pytest.fixture def gfx1250_generated_root(amdgpu_generated_root: Path) -> Path: - profile = Gfx1250Profile() + profile = Cdna5Profile() assert profile.generated_arch_name is not None return amdgpu_generated_root / _generated_dir_name(profile.generated_arch_name) def _generated_dir_name(arch_name: str) -> str: - profile = Gfx1250Profile() + profile = Cdna5Profile() if arch_name == profile.generated_arch_name: assert profile.generated_dir_name is not None return profile.generated_dir_name @@ -117,7 +117,7 @@ def _profile_for_arch(arch_name: str): 'rdna3': Rdna3Profile, 'rdna3_5': Rdna3_5Profile, 'rdna4': Rdna4Profile, - 'gfx1250': Gfx1250Profile, + 'cdna5': Cdna5Profile, } return profile_types[arch_name]() @@ -201,8 +201,8 @@ def semantics_for(profile): ) return derive_all_semantics(spec) - gfx1250 = semantics_for(Gfx1250Profile()) - assert Gfx1250Profile().ds_addtid_uses_m0_byte_base + gfx1250 = semantics_for(Cdna5Profile()) + assert Cdna5Profile().ds_addtid_uses_m0_byte_base assert gfx1250['DS_STORE_ADDTID_B32'].semantic_class == 'ds_write_addtid' for name in names[1:]: assert gfx1250[name].semantic_class == 'ds_atomic2' @@ -400,7 +400,7 @@ def cpp_namespace(self) -> str: ('rdna3', Rdna3Profile), ('rdna3_5', Rdna3_5Profile), ('rdna4', Rdna4Profile), - ('gfx1250', Gfx1250Profile), + ('gfx1250', Cdna5Profile), ], ) def test_generated_scc_accesses_match_mrisa(isa_name, profile_type): @@ -805,7 +805,7 @@ def _fake_sopp_parser(arch_name: str, *, sub_decode_funcs: list[str | None] | No def test_gfx1250_parser_injects_s_waitcnt_compat_once_in_opcode_order(): - parser, sopp, dte = _fake_sopp_parser('gfx1250', sub_decode_funcs=[None] * 16) + parser, sopp, dte = _fake_sopp_parser('cdna5', sub_decode_funcs=[None] * 16) parser._inject_compat_insts() parser._inject_compat_insts() @@ -1085,12 +1085,30 @@ def test_true16_vop3_cmpx_hoists_opsel(): def test_gfx1250_wmma_f32_passes_c_modifier_to_accumulator_helper(): inst = Instruction('V_WMMA_F32_16X16X32_F16', 'ENC_VOP3P', 0, []) - body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'gfx1250') + body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'cdna5') assert 'amdgpu::exec_wmma_f32_16x16x32_f16(' in body assert 'amdgpu::wmma_c_modifier(inst_.neg, inst_.neg_hi)' in body +@pytest.mark.parametrize( + ('arch_name', 'expected'), + [('cdna5', True), ('gfx1250', False)], +) +def test_generic_wmma_accumulator_selector_uses_cdna5_logical_key( + arch_name: str, expected: bool +) -> None: + generator = CodeGenerator(SimpleNamespace(arch_name=arch_name), '') + inst_sem = InstructionSemantics('V_WMMA_F32_16X16X128_FP8_FP8', 'vector_wmma') + operand = Operand( + 'src2', 256, 'OPR_SRC_VGPR_OR_INLINE', True, False, False, False, 3 + ) + + assert ( + generator._uses_generic_wmma_accumulator_selector(inst_sem, operand) is expected + ) + + @pytest.mark.parametrize('k', [64, 128]) @pytest.mark.parametrize( ('input_type', 'a_fp8', 'b_fp8'), @@ -1105,7 +1123,7 @@ def test_gfx1250_wmma_f16_f8_passes_fp16_overflow_mode( k: int, input_type: str, a_fp8: str, b_fp8: str ) -> None: inst = Instruction(f'V_WMMA_F16_16X16X{k}_{input_type}', 'ENC_VOP3P', 0, []) - body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'gfx1250') + body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'cdna5') assert f'amdgpu::exec_wmma_f16_f8_spec<16, 16, {k}, {a_fp8}, {b_fp8}>(' in body assert 'const_acc, wf.fp16_ovfl());' in body @@ -1113,7 +1131,7 @@ def test_gfx1250_wmma_f16_f8_passes_fp16_overflow_mode( def test_gfx1250_wmma_f16_overflow_mode_is_scoped_to_f8_helper() -> None: inst = Instruction('V_WMMA_F16_16X16X32_F16', 'ENC_VOP3P', 0, []) - body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'gfx1250') + body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'cdna5') assert 'amdgpu::exec_wmma_f16_spec<16, 16, 32>(' in body assert 's2, const_acc);' in body @@ -1217,7 +1235,7 @@ def test_rdna_wmma_f16_bf16_use_arch_specific_wave32_dispatch(): def test_gfx1250_wmma_i32_iu4_emits_executor(): inst = Instruction('V_WMMA_I32_16X16X16_IU4', 'ENC_VOP3P', 0, []) - body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'gfx1250') + body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], 'cdna5') assert '(inst_.neg & 0x1u) ? amdgpu::extract_i4(cu, base, loc)' in body assert 'amdgpu::exec_wmma_i32(cu, 16, 16, 16, 4, dst, src0_base,' in body @@ -1354,7 +1372,7 @@ def test_cdna_f64_mfma_uses_blgp_as_neg_immediate(): body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], arch) assert 's2, const_acc, inst_.blgp);' in body - for arch in ('rdna3', 'rdna4', 'gfx1250'): + for arch in ('rdna3', 'rdna4', 'cdna5'): body = gen_mfma(inst, ['vdst'], ['src0', 'src1', 'src2'], arch) assert 's2, const_acc, 0u);' in body @@ -1369,7 +1387,7 @@ def test_div_scale_uses_signed_tiny_exponent_threshold(): def test_gfx1250_profile_enables_generator_backed_quirks(): - profile = Gfx1250Profile() + profile = Cdna5Profile() assert profile.uses_packed_16bit_e32_source_selectors assert profile.uses_true16_vop3_opsel @@ -1429,7 +1447,7 @@ def test_rdna4_profile_enables_gfx12_true16_and_mode_hwregs_only(): def test_gfx1250_vop3_compare_sdst_uses_wave32_mask_size(): codegen = object.__new__(CodeGenerator) - codegen.isa_spec = SimpleNamespace(profile=Gfx1250Profile()) + codegen.isa_spec = SimpleNamespace(profile=Cdna5Profile()) sem = SimpleNamespace(semantic_class='vector_cmp') dst = SimpleNamespace(is_output=True, name='vdst', operand_type='OPR_SREG') @@ -1445,7 +1463,7 @@ def test_gfx1250_vop3_compare_sdst_uses_wave32_mask_size(): def test_gfx1250_vop3_cndmask_selector_uses_wave32_mask_size(): codegen = object.__new__(CodeGenerator) - codegen.isa_spec = SimpleNamespace(profile=Gfx1250Profile()) + codegen.isa_spec = SimpleNamespace(profile=Cdna5Profile()) sem = SimpleNamespace(semantic_class='vector_cndmask') selector = SimpleNamespace(is_output=False, name='src2', operand_type='OPR_SREG') @@ -1457,7 +1475,7 @@ def test_gfx1250_vop3_cndmask_selector_uses_wave32_mask_size(): def test_gfx1250_vop3_carry_operands_use_wave32_mask_size(): codegen = object.__new__(CodeGenerator) - codegen.isa_spec = SimpleNamespace(profile=Gfx1250Profile()) + codegen.isa_spec = SimpleNamespace(profile=Cdna5Profile()) sem = SimpleNamespace(semantic_class='vector_add_co') carry_out = SimpleNamespace(is_output=True, name='sdst', operand_type='OPR_SREG') @@ -1473,7 +1491,7 @@ def test_gfx1250_vop3_carry_operands_use_wave32_mask_size(): @pytest.mark.parametrize('semantic_class', ['vector_div_scale', 'vector_mad_64_32']) def test_gfx1250_vop3_auxiliary_mask_outputs_use_wave32_size(semantic_class): codegen = object.__new__(CodeGenerator) - codegen.isa_spec = SimpleNamespace(profile=Gfx1250Profile()) + codegen.isa_spec = SimpleNamespace(profile=Cdna5Profile()) sem = SimpleNamespace(semantic_class=semantic_class) mask_out = SimpleNamespace(is_output=True, name='sdst', operand_type='OPR_SREG') @@ -1488,8 +1506,8 @@ def test_ds_swizzle_generator_uses_addr_source_for_ds_and_vds(): def body_for(enc_name: str) -> str: codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), inst_encodings=[], encoding_map={}, ) @@ -1519,7 +1537,7 @@ def body_for(enc_name: str) -> str: def test_packed_16bit_source_gate_is_limited_to_e32_16bit_sources(): codegen = object.__new__(CodeGenerator) - codegen.isa_spec = SimpleNamespace(profile=Gfx1250Profile()) + codegen.isa_spec = SimpleNamespace(profile=Cdna5Profile()) packed_src = SimpleNamespace( is_input=True, is_output=False, size=16, operand_type='OPR_SRC' @@ -2399,7 +2417,7 @@ def test_noop_format_validation_is_inherited(amdgpu_generated_root: Path): def test_generated_dpp8_disassembly_uses_encoding_state( amdgpu_generated_root: Path, ) -> None: - for arch in ('rdna1', 'rdna2', 'rdna3', 'rdna3_5', 'rdna4', 'gfx1250'): + for arch in ('rdna1', 'rdna2', 'rdna3', 'rdna3_5', 'rdna4', 'cdna5'): arch_root = amdgpu_generated_root / _generated_dir_name(arch) encodings_cpp = (arch_root / 'encodings.cpp').read_text() encodings_h = (arch_root / 'encodings.h').read_text() @@ -2473,7 +2491,7 @@ def test_gfx1250_generated_literal_validation(gfx1250_generated_root: Path): assert 'VOPD3 does not support literal selectors' in vopd -@pytest.mark.parametrize('arch', ['rdna3', 'gfx1250']) +@pytest.mark.parametrize('arch', ['rdna3', 'cdna5']) def test_generated_sendmsg_return_selectors_are_not_literals( amdgpu_generated_root: Path, arch: str, @@ -2494,7 +2512,7 @@ def test_generated_sendmsg_return_selectors_are_not_literals( sendmsg_ctor = _generated_constructor_body(sop1, class_name) assert 'OperandType::OPR_SIMM32' not in sendmsg_ctor assert 'OperandType::OPR_SIMM64' not in sendmsg_ctor - if arch == 'gfx1250': + if arch == 'cdna5': sendmsg_decode = _generated_decode_body(sop1, class_name) assert 'LiteralSupport::None, 0' in sendmsg_decode @@ -2613,7 +2631,7 @@ def test_generated_operandless_vop_does_not_stage_missing_source( ('rdna3', ('Vop1', 'Vopc', 'Vop2', 'Vop3', 'Vop3p', 'Vop3SdstEnc')), ('rdna3_5', ('Vop1', 'Vopc', 'Vop2', 'Vop3', 'Vop3p', 'Vop3SdstEnc')), ('rdna4', ('Vop1', 'Vopc', 'Vop2', 'Vop3', 'Vop3p', 'Vop3SdstEnc')), - ('gfx1250', ('Vop1', 'Vopc', 'Vop2', 'Vop3', 'Vop3p', 'Vop3SdstEnc')), + ('cdna5', ('Vop1', 'Vopc', 'Vop2', 'Vop3', 'Vop3p', 'Vop3SdstEnc')), ], ) def test_generated_dpp_encodings_own_extension_words( @@ -2667,7 +2685,7 @@ def test_generated_dpp_encodings_own_extension_words( 'rdna3', 'rdna3_5', 'rdna4', - 'gfx1250', + 'cdna5', ], ) def test_generated_scalar_literals_own_extension_words( @@ -2678,10 +2696,10 @@ def test_generated_scalar_literals_own_extension_words( encodings_h = (arch_root / 'encodings.h').read_text() encodings_cpp = (arch_root / 'encodings.cpp').read_text() raw_word_counts = { - 'Sop1': 3 if arch == 'gfx1250' else 2, - 'Sopc': 3 if arch == 'gfx1250' else 2, + 'Sop1': 3 if arch == 'cdna5' else 2, + 'Sopc': 3 if arch == 'cdna5' else 2, 'Sopk': 2, - 'Sop2': 3 if arch == 'gfx1250' else 2, + 'Sop2': 3 if arch == 'cdna5' else 2, } for class_name, raw_word_count in raw_word_counts.items(): @@ -2971,7 +2989,7 @@ def test_generated_vop_execution_has_no_instruction_storage_bypass( 'rdna3', 'rdna3_5', 'rdna4', - 'gfx1250', + 'cdna5', ) for path in (amdgpu_generated_root / _generated_dir_name(arch)).glob('vop*.cpp') if '_exec' not in path.stem @@ -3001,13 +3019,13 @@ def test_generated_dpp_execution_uses_effective_lane_mask_for_dpp16( 'rdna3', 'rdna3_5', 'rdna4', - 'gfx1250', + 'cdna5', ) vopc_names = { 'rdna3': 'vopc.cpp', 'rdna3_5': 'vopc.cpp', 'rdna4': 'vopc.cpp', - 'gfx1250': 'vopc_cmp.cpp', + 'cdna5': 'vopc_cmp.cpp', } shared_execute = (amdgpu_generated_root / 'shared' / 'execute_shared.h').read_text() @@ -3061,8 +3079,8 @@ def test_generated_cmpx_dpp_cleanup_preserves_exec(amdgpu_generated_root: Path): 'rdna3': amdgpu_generated_root / 'rdna3' / 'vopc.cpp', 'rdna3_5': amdgpu_generated_root / 'rdna3_5' / 'vopc.cpp', 'rdna4': amdgpu_generated_root / 'rdna4' / 'vopc.cpp', - 'gfx1250': ( - amdgpu_generated_root / _generated_dir_name('gfx1250') / 'vopc_cmpx.cpp' + 'cdna5': ( + amdgpu_generated_root / _generated_dir_name('cdna5') / 'vopc_cmpx.cpp' ), } @@ -3390,14 +3408,14 @@ def test_gfx1250_helper_blocks_emit_scaled_wmma_table_decoder( ): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) - assert codegen._supports_gfx1250_scaled_wmma_vop3px2() - assert 'VWmmaScaleF32Vop3px2' in (codegen._emit_gfx1250_scaled_wmma_vop3px2_class()) + assert codegen._supports_cdna5_scaled_wmma_vop3px2() + assert 'VWmmaScaleF32Vop3px2' in (codegen._emit_cdna5_scaled_wmma_vop3px2_class()) model_impl = ' '.join( - codegen._emit_gfx1250_scaled_wmma_vop3px2_impls().model[0].split() + codegen._emit_cdna5_scaled_wmma_vop3px2_impls().model[0].split() ) assert ( 'reinterpret_cast(inst + 2), ' @@ -3405,7 +3423,7 @@ def test_gfx1250_helper_blocks_emit_scaled_wmma_table_decoder( 'Vop3p::ExtensionDecodePolicy::Skip),' ) in model_impl - helpers = codegen._emit_gfx1250_scaled_wmma_vop3px2_decoder_helpers() + helpers = codegen._emit_cdna5_scaled_wmma_vop3px2_decoder_helpers() assert 'isVop3pOp' in helpers assert 'isWmmaScaleF32Vop3px2' not in helpers @@ -3450,7 +3468,7 @@ def test_generated_decoders_publish_instruction_lookahead_bounds( ('cdna2', Cdna2Profile, 4), ('cdna3', CdnaProfile, 4), ('cdna4', CdnaProfile, 4), - ('gfx1250', Gfx1250Profile, 4), + ('cdna5', Cdna5Profile, 4), ('rdna1', Rdna1Profile, 3), ('rdna2', Rdna2Profile, 3), ('rdna3', Rdna3Profile, 3), @@ -3537,9 +3555,7 @@ def generator_for( assert generator_for(has_vopd=True)._max_instruction_word_count() == 3 assert generator_for(arch_name='cdna4')._max_instruction_word_count() == 4 assert ( - generator_for( - arch_name='gfx1250', scaled_wmma=True - )._max_instruction_word_count() + generator_for(arch_name='cdna5', scaled_wmma=True)._max_instruction_word_count() == 4 ) @@ -3567,7 +3583,7 @@ def test_cdna4_vop3px2_prefix_decoder_validates_suffix(cdna4_generated_root: Pat ('rdna3', set(range(0x190, 0x198))), ('rdna3_5', set(range(0x190, 0x198))), ('rdna4', set(range(0x190, 0x198))), - ('gfx1250', set(range(0x190, 0x198)) | set(range(0x19E, 0x1A0))), + ('cdna5', set(range(0x190, 0x198)) | set(range(0x19E, 0x1A0))), ], ) def test_vopd_dispatch_uses_primary_decode_table( @@ -3614,7 +3630,7 @@ def test_decoder_header_keeps_dispatch_details_private( 'cdna2', 'cdna3', 'cdna4', - 'gfx1250', + 'cdna5', 'rdna1', 'rdna2', 'rdna3', @@ -3806,10 +3822,10 @@ def test_hwreg_descriptor_tables_cover_checked_in_xml( def test_gfx1250_vopd_template_uses_dx9_zero_and_fma(tmp_path): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', + arch_name='cdna5', generated_dir_name='cdna5', cpp_namespace='cdna5', - profile=Gfx1250Profile(), + profile=Cdna5Profile(), operand_types={'OPR_SRC_SIMPLE'}, ) codegen.out_path = str(tmp_path) @@ -3951,10 +3967,10 @@ def test_rdna3_and_rdna35_vopd_generation_matches_common_profile(tmp_path): def test_gfx1250_vopd_uses_plain_src_when_simple_src_operand_is_absent(tmp_path): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', + arch_name='cdna5', generated_dir_name='cdna5', cpp_namespace='cdna5', - profile=Gfx1250Profile(), + profile=Cdna5Profile(), operand_types={'OPR_SRC'}, ) codegen.out_path = str(tmp_path) @@ -4005,8 +4021,8 @@ def test_addk_and_mulk_register_their_read_write_destination_as_a_source(): def test_gfx1250_ds_atomic_routes_data_through_vgpr_resolver(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) expr = codegen._vgpr_base_expr('data0', role='Src1') @@ -4033,8 +4049,8 @@ def test_rdna4_ds_atomic_uses_raw_encoding(): def test_gfx1250_flat_cmpswap_payload_width_is_independent_of_element_width(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) b32 = SimpleNamespace( @@ -4064,8 +4080,8 @@ def test_gfx1250_flat_cmpswap_payload_width_is_independent_of_element_width(): def test_gfx1250_flat_u64_atomic_payload_width_uses_two_dwords(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) u64 = SimpleNamespace( @@ -4083,8 +4099,8 @@ def test_gfx1250_flat_u64_atomic_payload_width_uses_two_dwords(): def test_gfx1250_cluster_load_generators_force_request_l1_bypass(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) cluster = SimpleNamespace( @@ -4129,8 +4145,8 @@ def test_gfx1250_cluster_load_generators_force_request_l1_bypass(): def test_gfx1250_async_lds_generators_apply_signed_ioffset(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) expected_load_address = ( @@ -4211,8 +4227,8 @@ def test_gfx1250_async_lds_generators_apply_signed_ioffset(): def test_gfx1250_buffer_cmpswap_payload_width_is_independent_of_element_width(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) b64 = SimpleNamespace( @@ -4231,8 +4247,8 @@ def test_gfx1250_buffer_cmpswap_payload_width_is_independent_of_element_width(): def test_gfx1250_buffer_u64_atomic_payload_width_uses_two_dwords(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) u64 = SimpleNamespace( @@ -4263,7 +4279,7 @@ def test_ev124_125_arch_gating_in_generated_operand( 'rdna3': 125, 'rdna3_5': 125, 'rdna4': 125, - 'gfx1250': 125, + 'cdna5': 125, } for arch, encoding in expected_m0_encoding.items(): arch_root = amdgpu_generated_root / _generated_dir_name(arch) @@ -4391,7 +4407,7 @@ def test_generated_atomic_def_use_follows_return_control( assert 'dst_operands_[num_dst_++] = &vdst;' in cdna4_add gfx1250_buffer = ( - amdgpu_generated_root / _generated_dir_name('gfx1250') / 'vbuffer.cpp' + amdgpu_generated_root / _generated_dir_name('cdna5') / 'vbuffer.cpp' ).read_text() gfx1250_add = gfx1250_buffer.split( 'BufferAtomicAddU32Vbuffer::BufferAtomicAddU32Vbuffer' @@ -4423,7 +4439,7 @@ def test_generated_flat_saddr_null_selector_follows_encoding( assert 'inst_.saddr != 0x7F' in rdna3_flat assert 'inst_.saddr != OPR_SREG_NULL' not in rdna3_flat - gfx1250_root = amdgpu_generated_root / _generated_dir_name('gfx1250') + gfx1250_root = amdgpu_generated_root / _generated_dir_name('cdna5') gfx1250_vflat = (gfx1250_root / 'vflat.cpp').read_text() gfx1250_vglobal = (gfx1250_root / 'vglobal.cpp').read_text() assert 'inst_.saddr != OPR_SREG_NULL' in gfx1250_vflat @@ -4522,7 +4538,7 @@ def test_only_gfx1250_generates_implicit_use_operands_overrides( """ gfx1250_hits = sum( path.read_text().count('implicit_use_operands') - for path in (amdgpu_generated_root / _generated_dir_name('gfx1250')).rglob('*') + for path in (amdgpu_generated_root / _generated_dir_name('cdna5')).rglob('*') if path.is_file() and path.suffix in ('.h', '.cpp') ) assert gfx1250_hits > 0, 'gfx1250 must still emit the operand-backed hook' diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py index 48392e06e613..25bb7d297546 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_literal_codegen.py @@ -14,7 +14,7 @@ ) from amdisa.cross_isa import SharedInstInfo, SharedInstructionPlan from amdisa.gpuisa import InstEncoding, Instruction, Operand -from amdisa.isa_profile import Gfx1250Profile, Rdna4Profile +from amdisa.isa_profile import Cdna5Profile, Rdna4Profile from amdisa.parser import Parser, _uniquify_fieldless_names from amdisa.semantics import InstructionSemantics @@ -151,7 +151,7 @@ def test_vop3p_literal64_rejection_uses_complete_encoding_capability(): def test_gfx1250_packed_f32_reader_has_no_unreachable_literal64_branch(): - source = CodeGenerator._emit_gfx1250_matrix_fmt_helpers().execution[0] + source = CodeGenerator._emit_cdna5_matrix_fmt_helpers().execution[0] reader_start = source.index('PkF32Words read_pk_f32_words') reader_end = source.index('\n}', reader_start) @@ -745,8 +745,8 @@ def test_scalar_mul_u64_generated_execute_reads_full_source_pairs(): def test_scalar_addpc_generated_execute_uses_unsigned_pc_addition(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), inst_encodings=[], encoding_map={}, ) @@ -779,9 +779,7 @@ def test_literal_fma_can_share_with_matching_operand_layouts_only(): rdna_codegen.config = SimpleNamespace(unshared_execute_keys=frozenset()) gfx_codegen = object.__new__(CodeGenerator) - gfx_codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', profile=Gfx1250Profile() - ) + gfx_codegen.isa_spec = SimpleNamespace(arch_name='cdna5', profile=Cdna5Profile()) gfx_codegen.shared_plan = plan gfx_codegen.config = SimpleNamespace(unshared_execute_keys=frozenset()) diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_packed_codegen.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_packed_codegen.py index 08baf04a1e66..c74e7242463b 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_packed_codegen.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_packed_codegen.py @@ -38,7 +38,7 @@ def test_gfx1250_pk_f32_uses_literal_aware_pair_helper(): ['src0', 'src1'], 'add', opsel_exprs=('inst_.opsel', 'inst_.opsel_hi'), - use_gfx1250_helpers=True, + use_cdna5_helpers=True, ) assert 'const auto s0 = read_pk_f32_words(src0, wf, lane)' in cpp @@ -88,7 +88,7 @@ def test_gfx1250_mad_mix_f32_uses_helper_and_fma(): ['src0', 'src1', 'src2'], op_sel_hi_2_expr='inst_.pad_14', opsel_exprs=('inst_.opsel', 'inst_.opsel_hi'), - use_gfx1250_helpers=True, + use_cdna5_helpers=True, ) assert 'read_fma_mix_source_f32(src0, wf, lane' in cpp @@ -119,7 +119,7 @@ def test_gfx1250_mad_mixlo_f16_uses_helper_and_fma(): is_lo=True, op_sel_hi_2_expr='inst_.pad_14', opsel_exprs=('inst_.opsel', 'inst_.opsel_hi'), - use_gfx1250_helpers=True, + use_cdna5_helpers=True, ) assert 'read_fma_mix_source_f32(src0, wf, lane' in cpp @@ -160,7 +160,7 @@ def test_gfx1250_bf16_mad_mix_variants_use_bf16_helper(): result='f32', op_sel_hi_2_expr='inst_.pad_14', opsel_exprs=('inst_.opsel', 'inst_.opsel_hi'), - use_gfx1250_helpers=True, + use_cdna5_helpers=True, ) cpp_lo = gen_mad_mix_bf16( ['vdst'], @@ -168,7 +168,7 @@ def test_gfx1250_bf16_mad_mix_variants_use_bf16_helper(): result='lo', op_sel_hi_2_expr='inst_.pad_14', opsel_exprs=('inst_.opsel', 'inst_.opsel_hi'), - use_gfx1250_helpers=True, + use_cdna5_helpers=True, ) assert 'read_fma_mix_bf16_source_f32(src0, wf, lane' in cpp_f32 diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_profile_properties.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_profile_properties.py index 14d67a9aa957..622671d384e1 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_profile_properties.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_profile_properties.py @@ -21,7 +21,7 @@ Cdna1Profile, Cdna2Profile, CdnaProfile, - Gfx1250Profile, + Cdna5Profile, MemoryCoherencyModel, Rdna1Profile, Rdna2Profile, @@ -38,7 +38,7 @@ (Rdna1Profile(), True), (Rdna3Profile(), True), (Rdna4Profile(), True), - (Gfx1250Profile(), False), + (Cdna5Profile(), False), ], ) def test_supports_wgp_mode(profile, expected): @@ -50,7 +50,7 @@ def test_supports_wgp_mode(profile, expected): [ (CdnaProfile(), False, False), (Rdna4Profile(), True, False), - (Gfx1250Profile(), True, True), + (Cdna5Profile(), True, True), ], ) def test_ttmp_workgroup_id_properties(profile, uses_ttmp, uses_cluster_ttmp): @@ -65,7 +65,7 @@ def test_ttmp_workgroup_id_properties(profile, uses_ttmp, uses_cluster_ttmp): (Rdna1Profile(), False), (Rdna3Profile(), False), (Rdna4Profile(), False), - (Gfx1250Profile(), False), + (Cdna5Profile(), False), ], ) def test_descriptor_sgpr_count_encoded(profile, expected): @@ -77,7 +77,7 @@ def test_descriptor_sgpr_count_encoded(profile, expected): [ (CdnaProfile(), 256), (Rdna4Profile(), 256), - (Gfx1250Profile(), 1024), + (Cdna5Profile(), 1024), ], ) def test_max_addressable_vgprs_per_wf(profile, expected): @@ -95,7 +95,7 @@ def test_max_addressable_vgprs_per_wf(profile, expected): (Rdna3Profile(), 8, 4), (Rdna3_5Profile(), 8, 4), (Rdna4Profile(), 8, 4), - (Gfx1250Profile(), 16, 0), + (Cdna5Profile(), 16, 0), ], ) def test_descriptor_vgpr_count_granule(profile, expected_wave32, expected_wave64): @@ -114,7 +114,7 @@ def test_descriptor_vgpr_count_granule(profile, expected_wave32, expected_wave64 Rdna3Profile(), Rdna3_5Profile(), Rdna4Profile(), - Gfx1250Profile(), + Cdna5Profile(), ], ) def test_amdgpu_profiles_split_execution_sources(profile): @@ -157,8 +157,8 @@ def split_execution_sources(self): (Rdna3Profile(), 'ENC_FLAT', '0x7F'), (Rdna4Profile(), 'ENC_VFLAT', 'OPR_SREG_NULL'), (Rdna4Profile(), 'ENC_VGLOBAL', 'OPR_SREG_NULL'), - (Gfx1250Profile(), 'ENC_VFLAT', 'OPR_SREG_NULL'), - (Gfx1250Profile(), 'ENC_VGLOBAL', 'OPR_SREG_NULL'), + (Cdna5Profile(), 'ENC_VFLAT', 'OPR_SREG_NULL'), + (Cdna5Profile(), 'ENC_VGLOBAL', 'OPR_SREG_NULL'), ], ) def test_saddr_null_selector_is_encoding_specific(profile, enc_name, expected): @@ -174,7 +174,7 @@ def test_isa_properties_codegen_uses_profile_values(tmp_path): specs = [ ('cdna3', SimpleNamespace(profile=CdnaProfile()), None), ('rdna4', SimpleNamespace(profile=Rdna4Profile()), None), - ('gfx1250', SimpleNamespace(profile=Gfx1250Profile()), None), + ('cdna5', SimpleNamespace(profile=Cdna5Profile()), None), ] output = emit_isa_properties(str(tmp_path), specs).read_text() @@ -214,7 +214,7 @@ def test_isa_properties_codegen_uses_profile_values(tmp_path): ' };' ) in output assert ( - 'case ROCJITSU_CODE_ARCH_GFX1250:\n' + 'case ROCJITSU_CODE_ARCH_CDNA5:\n' ' return {\n' ' .supports_wgp_mode = false,\n' ' .descriptor_sgpr_count_encoded = false,\n' @@ -240,7 +240,7 @@ def test_checked_in_isa_properties_matches_all_profiles(tmp_path): ('rdna3', Rdna3Profile()), ('rdna3_5', Rdna3_5Profile()), ('rdna4', Rdna4Profile()), - ('gfx1250', Gfx1250Profile()), + ('cdna5', Cdna5Profile()), ] specs = [ (name, SimpleNamespace(profile=profile), None) for name, profile in profiles @@ -258,12 +258,12 @@ def test_checked_in_isa_properties_matches_all_profiles(tmp_path): def test_gfx1250_operand_execution_backend_uses_separate_source(tmp_path): generator = CodeGenerator( SimpleNamespace( - arch_name='gfx1250', + arch_name='cdna5', generated_dir_name='cdna5', cpp_namespace='cdna5', opnd_selectors=[], operand_types=['OPR_SIMM16', 'OPR_SIMM32', 'OPR_VGPR'], - profile=Gfx1250Profile(), + profile=Cdna5Profile(), ), str(tmp_path), ) @@ -304,10 +304,10 @@ def test_gfx1250_instruction_execution_backend_is_dense_and_scoped(tmp_path): generator = object.__new__(CodeGenerator) generator.out_path = str(tmp_path) generator.isa_spec = SimpleNamespace( - arch_name='gfx1250', + arch_name='cdna5', generated_dir_name='cdna5', cpp_namespace='cdna5', - profile=Gfx1250Profile(), + profile=Cdna5Profile(), ) generator.config = CodegenConfig() generator._split_execution_classes = ['FirstInstruction', 'SecondInstruction'] @@ -594,9 +594,9 @@ def test_has_vopd3_false(self): assert self.p.has_vopd3 is False -class TestGfx1250Profile: +class TestCdna5Profile: def setup_method(self): - self.p = Gfx1250Profile() + self.p = Cdna5Profile() def test_supported_versions(self): assert self.p.supported_versions == ['1.2.0'] @@ -620,7 +620,7 @@ def test_vopd_slot_opcodes(self): ) def test_generated_identities(self): - assert self.p.generated_arch_name == 'gfx1250' + assert self.p.generated_arch_name == 'cdna5' assert self.p.generated_dir_name == 'cdna5' assert self.p.cpp_namespace == 'cdna5' @@ -795,7 +795,7 @@ def test_logical_source_chunks_reject_duplicate_filenames(self): def test_detect_profile_uses_filename_override(self, tmp_path): xml = tmp_path / 'amdgpu_isa_gfx1250.xml' xml.write_text('') - assert _detect_profile(str(xml)) == 'gfx1250' + assert _detect_profile(str(xml)) == 'cdna5' def test_test_encoding_uses_primary_decode_key(self): generator = object.__new__(CodeGenerator) @@ -824,12 +824,12 @@ def test_test_encoding_uses_primary_decode_key(self): def test_operand_read_lane64_preserves_literal64(self, tmp_path): generator = CodeGenerator( SimpleNamespace( - arch_name='gfx1250', + arch_name='cdna5', generated_dir_name='cdna5', cpp_namespace='cdna5', opnd_selectors=[], operand_types=['OPR_SIMM32', 'OPR_SIMM64', 'OPR_VGPR'], - profile=Gfx1250Profile(), + profile=Cdna5Profile(), ), str(tmp_path), ) diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py index a2f6e762e368..33e89ca1f32d 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_sema_derive.py @@ -1129,7 +1129,7 @@ def test_gfx1250_cvt_sr_fp8_clamp_selects_e5m3_encoder(self): enc_field_names={'opsel'}, encoding_map=None, enc_name='', - arch_name='gfx1250', + arch_name='cdna5', ) cpp = gen_cvt_fp8(ctx) @@ -1456,7 +1456,7 @@ def test_gfx1250_cvt_scalef32_pack_fp8_threads_fp16_ovfl(self): ['src0', 'src1'], sem.semantic_class, sem.operation, - arch_name='gfx1250', + arch_name='cdna5', ) assert 'util::f32_to_fp8_e4m3_rne_mode(value, wf.fp16_ovfl())' in cpp diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_vector_special_codegen.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_vector_special_codegen.py index f5579e5e7997..eb6d7f361ef1 100644 --- a/emulation/rocjitsu/lib/python/amdisa/tests/test_vector_special_codegen.py +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_vector_special_codegen.py @@ -15,7 +15,7 @@ ) from amdisa.codegen._generator import CodeGenerator from amdisa.gpuisa import Instruction, Operand -from amdisa.isa_profile import Gfx1250Profile, Rdna3Profile, Rdna4Profile +from amdisa.isa_profile import Cdna5Profile, Rdna3Profile, Rdna4Profile def test_permlane_uses_opsel_fi_and_bound_ctrl_bits(): @@ -131,8 +131,8 @@ def test_true16_vop3_simd_probe_leaves_unsupported_b16_scalar(): def test_gfx1250_true16_execute_bodies_are_arch_local(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) mov_b16 = Instruction( 'V_MOV_B16', @@ -195,8 +195,8 @@ def test_gfx1250_true16_execute_bodies_are_arch_local(): def test_gfx1250_non_true16_simd_probe_can_still_be_shared(): codegen = object.__new__(CodeGenerator) codegen.isa_spec = SimpleNamespace( - arch_name='gfx1250', - profile=Gfx1250Profile(), + arch_name='cdna5', + profile=Cdna5Profile(), ) mov_b32 = Instruction( 'V_MOV_B32', @@ -214,7 +214,7 @@ def test_gfx1250_non_true16_simd_probe_can_still_be_shared(): def test_gfx1250_true16_e32_dst_reg_uses_physical_vgpr(): codegen = object.__new__(CodeGenerator) - codegen.isa_spec = SimpleNamespace(arch_name='gfx1250', profile=Gfx1250Profile()) + codegen.isa_spec = SimpleNamespace(arch_name='cdna5', profile=Cdna5Profile()) fmac_f16 = Instruction( 'V_FMAC_F16', 'ENC_VOP2', diff --git a/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h b/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h index 0f0d93990e81..a9f3f30d91f2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h +++ b/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/code/rj_code.h @@ -43,8 +43,9 @@ typedef enum rj_code_arch_e { ROCJITSU_CODE_ARCH_RV32I = 9, /// @brief RISC-V 64-bit integer base ISA. ROCJITSU_CODE_ARCH_RV64I = 10, - /// @brief gfx1250 ISA architecture. - ROCJITSU_CODE_ARCH_GFX1250 = 11, + /// @brief Compute Data Network Architecture 5 (CDNA5). + /// @note Keep this at the former GFX1250 value for C API compatibility. + ROCJITSU_CODE_ARCH_CDNA5 = 11, // \NPI new ISA family: add its public architecture identifier here and wire // its closed-world semantics through the ISA traits, properties, and users. /// @brief Number of named, built-in architectures. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp index 8145c0f2e7be..4750f91b1b82 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp @@ -660,7 +660,7 @@ class BlockState { case ROCJITSU_CODE_ARCH_RDNA3: case ROCJITSU_CODE_ARCH_RDNA3_5: case ROCJITSU_CODE_ARCH_RDNA4: - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return add_base(0x47); case ROCJITSU_CODE_ARCH_RV32I: case ROCJITSU_CODE_ARCH_RV64I: @@ -697,7 +697,7 @@ class BlockState { return std::nullopt; } return std::nullopt; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: switch (op) { case ScalarSop2Op::AddU32: return 0; @@ -1145,7 +1145,7 @@ instruction_index_for_offset(std::span insts, uint64_t // // Match only the self-update literal forms. Register addends would require a // separate constant-propagation proof and must continue to fail closed. - if (arch != ROCJITSU_CODE_ARCH_GFX1250 || inst.mnemonic() != "s_add_nc_u64" || + if (arch != ROCJITSU_CODE_ARCH_CDNA5 || inst.mnemonic() != "s_add_nc_u64" || inst.num_dst_operands() != 1 || inst.num_src_operands() != 2) return false; @@ -1558,7 +1558,7 @@ std::optional try_apply_temp_delta_pattern(AnalysisContext &ctx, const A return std::nullopt; const auto is_gfx1250_padding = [&](size_t index) { - if (ctx.arch != ROCJITSU_CODE_ARCH_GFX1250) + if (ctx.arch != ROCJITSU_CODE_ARCH_CDNA5) return false; const Instruction &inst = *ctx.insts[index]; // The gfx1250 sequence drains XCNT before an instruction prefetch. The @@ -1643,7 +1643,7 @@ match_signed_delta_sub_consumer(const AnalysisContext &ctx, const AnalysisBlock return std::nullopt; const auto is_gfx1250_padding = [&](size_t index) { - if (ctx.arch != ROCJITSU_CODE_ARCH_GFX1250) + if (ctx.arch != ROCJITSU_CODE_ARCH_CDNA5) return false; const Instruction &inst = *ctx.insts[index]; if (inst.mnemonic() == "s_wait_xcnt" || inst.mnemonic() == "s_prefetch_inst_pc_rel") @@ -2536,7 +2536,7 @@ void recover_vector_lane_stashed_pcs(AnalysisContext &ctx, const std::vector( deferred_scope, options.entry_block, deferred_extra_edges_, options.text, options.additional_entry_blocks); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h index 9cca6213ea3c..30c3fe73b5c9 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/amdgpu_elf.h @@ -90,7 +90,7 @@ inline constexpr uint32_t elf_mach_for_arch(rj_code_arch_t arch) { return EF_AMDGPU_MACH_AMDGCN_GFX1150; case ROCJITSU_CODE_ARCH_RDNA4: return EF_AMDGPU_MACH_AMDGCN_GFX1200; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return EF_AMDGPU_MACH_AMDGCN_GFX1250; default: return EF_AMDGPU_MACH_NONE; @@ -126,7 +126,7 @@ inline constexpr rj_code_arch_t arch_for_elf_mach(uint32_t mach) { case EF_AMDGPU_MACH_AMDGCN_GFX1201: return ROCJITSU_CODE_ARCH_RDNA4; case EF_AMDGPU_MACH_AMDGCN_GFX1250: - return ROCJITSU_CODE_ARCH_GFX1250; + return ROCJITSU_CODE_ARCH_CDNA5; default: return ROCJITSU_CODE_ARCH_INVALID; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp index fa83d4aa8dd3..4cfb6c5c067f 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/basic_block.cpp @@ -163,7 +163,7 @@ BasicBlock::build(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, // gfx1250 code objects use zero-filled alignment between function bodies. // Zero is not an instruction; block construction below treats sequential // fallthrough into it as an implicit unreachable boundary. - if (arch == ROCJITSU_CODE_ARCH_GFX1250 && inst_data[pc] == 0) { + if (arch == ROCJITSU_CODE_ARCH_CDNA5 && inst_data[pc] == 0) { ++pc; byte_offset += sizeof(uint32_t); continue; @@ -275,7 +275,7 @@ BasicBlock::build(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, const bool can_fall_through = !is_program_path_terminator(last) && !is_unconditional_branch(last) && (last.flags() & INDIRECT_BRANCH) == 0; - const bool reaches_gfx1250_zero = decode_gap && arch == ROCJITSU_CODE_ARCH_GFX1250 && + const bool reaches_gfx1250_zero = decode_gap && arch == ROCJITSU_CODE_ARCH_CDNA5 && next_offset < section_end && inst_data[next_offset / sizeof(uint32_t)] == 0; // Running off the end of `.text` is the same boundary as running into padding: there is no @@ -283,7 +283,7 @@ BasicBlock::build(const CodeObject &co, Decoder &decoder, rj_code_arch_t arch, // depend on whether the linker happened to align the section, so an unterminated tail // would be translated verbatim in one build and given a terminator in the next. const bool reaches_section_end = - arch == ROCJITSU_CODE_ARCH_GFX1250 && i >= decoded.size() && next_offset >= section_end; + arch == ROCJITSU_CODE_ARCH_CDNA5 && i >= decoded.size() && next_offset >= section_end; if (can_fall_through && (reaches_gfx1250_zero || reaches_section_end)) { current->has_terminator_ = true; current->has_implicit_terminator_ = true; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.cpp index fb72aac7f474..b307af70df22 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.cpp @@ -50,7 +50,7 @@ enum class ScalarSop2Op { return std::nullopt; } return std::nullopt; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: // gfx1250 retains the legacy 32-bit arithmetic opcodes and adds the // SCC-neutral 64-bit scalar add used by its canonical PC builders. switch (op) { @@ -148,7 +148,7 @@ bool append_pc_delta_builder(std::vector &words, rj_code_arch_t arch, constexpr uint16_t kLiteral64Operand = 254; constexpr uint16_t kInlineInt0 = 128; - if (arch == ROCJITSU_CODE_ARCH_GFX1250) { + if (arch == ROCJITSU_CODE_ARCH_CDNA5) { // gfx1250's SCC-neutral s_add_nc_u64 is both the compiler's canonical PC // materialization and the smallest safe relocation replacement. Positive // 32-bit deltas need one literal word; negative or wider deltas use the diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.h index 30effcb076c1..3368b7c16491 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/builders/instruction_builder.h @@ -136,7 +136,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::build_sopp(op, {.simm16 = simm16})[0]; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::build_sopp(op, {.simm16 = simm16})[0]; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::build_sopp(op, {.simm16 = simm16})[0]; default: throw util::UnimplementedInst("SOPP builder for target architecture"); @@ -174,7 +174,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::build_sop1( op, {.ssrc0 = static_cast(ssrc0), .sdst = static_cast(sdst)})[0]; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::build_sop1( op, {.ssrc0 = static_cast(ssrc0), .sdst = static_cast(sdst)})[0]; default: @@ -223,7 +223,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna4::build_sop2(op, {.ssrc0 = static_cast(ssrc0), .ssrc1 = static_cast(ssrc1), .sdst = static_cast(sdst)})[0]; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::build_sop2(op, {.ssrc0 = static_cast(ssrc0), .ssrc1 = static_cast(ssrc1), .sdst = static_cast(sdst)})[0]; @@ -271,7 +271,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::build_sopc( op, {.ssrc0 = static_cast(ssrc0), .ssrc1 = static_cast(ssrc1)})[0]; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::build_sopc( op, {.ssrc0 = static_cast(ssrc0), .ssrc1 = static_cast(ssrc1)})[0]; default: @@ -308,7 +308,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; ROCJITSU_BUILD_SOPK(rdna3_5); case ROCJITSU_CODE_ARCH_RDNA4: ROCJITSU_BUILD_SOPK(rdna4); - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: ROCJITSU_BUILD_SOPK(cdna5); default: throw util::UnimplementedInst("SOPK builder for target architecture"); @@ -346,7 +346,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::OPR_SDST_M0; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::OPR_SDST_M0; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::OPR_SDST_M0; default: throw util::UnimplementedInst("M0 operand code for target architecture"); @@ -378,7 +378,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::OPR_SDST_VCC_LO; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::OPR_SDST_VCC_LO; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::OPR_SDST_VCC_LO; default: throw util::UnimplementedInst("VCC_LO operand code for target architecture"); @@ -410,7 +410,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::OPR_SDST_EXEC_LO; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::OPR_SDST_EXEC_LO; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::OPR_SDST_EXEC_LO; default: throw util::UnimplementedInst("EXEC_LO operand code for target architecture"); @@ -442,7 +442,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::OPR_SRC_NEG_INT_MIN; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::OPR_SRC_NEG_INT_MIN; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::OPR_SRC_NEG_INT_MIN; default: throw util::UnimplementedInst("inline -1 source code for target architecture"); @@ -505,7 +505,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::opcode; \ case ROCJITSU_CODE_ARCH_RDNA4: \ return rdna4::opcode; \ - case ROCJITSU_CODE_ARCH_GFX1250: \ + case ROCJITSU_CODE_ARCH_CDNA5: \ return cdna5::opcode /// @brief Get the s_branch opcode for a target ISA. @@ -565,7 +565,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::kSGetPcB64Sop1; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::kSGetPcB64Sop1; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::kSGetPcI64Sop1; default: throw util::UnimplementedInst("s_getpc for target architecture"); @@ -593,7 +593,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::kSSetPcB64Sop1; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::kSSetPcB64Sop1; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::kSSetPcI64Sop1; default: throw util::UnimplementedInst("s_setpc for target architecture"); @@ -621,7 +621,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::kSSwapPcB64Sop1; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::kSSwapPcB64Sop1; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::kSSwapPcI64Sop1; default: throw util::UnimplementedInst("s_swappc for target architecture"); @@ -649,7 +649,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::kSCallB64Sopk; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::kSCallB64Sopk; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::kSCallI64Sopk; default: throw util::UnimplementedInst("s_call_b64 for target architecture"); @@ -683,7 +683,7 @@ inline constexpr uint16_t kDelayAluSaluDep1 = 9; return rdna3_5::kSDelayAluSopp; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::kSDelayAluSopp; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::kSDelayAluSopp; default: throw util::UnimplementedInst("s_delay_alu for target architecture"); @@ -824,7 +824,7 @@ build_s_nop(uint16_t cycles = 0, rj_code_arch_t arch = ROCJITSU_CODE_ARCH_RDNA4) /// @returns std::nullopt on an ISA that has no XCNT counter, where nothing can /// have required the drain in the first place. [[nodiscard]] inline constexpr std::optional build_s_wait_xcnt(rj_code_arch_t arch) { - if (arch != ROCJITSU_CODE_ARCH_GFX1250) + if (arch != ROCJITSU_CODE_ARCH_CDNA5) return std::nullopt; return build_sopp_encoding(arch, cdna5::kSWaitXcntSopp, 0); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp index 94077a785f04..97b29abf8d3e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp @@ -455,7 +455,7 @@ translation_refusal(const CodeObjectPatcher &patcher, rj_code_arch_t guest_arch, // A same-architecture gfx1250 translation is direction-specific: A0 and B0 share an ELF machine // ID, so both revisions must be given. Enforce this here as well as in the C API. - if (guest_arch == ROCJITSU_CODE_ARCH_GFX1250 && host_arch == ROCJITSU_CODE_ARCH_GFX1250) { + if (guest_arch == ROCJITSU_CODE_ARCH_CDNA5 && host_arch == ROCJITSU_CODE_ARCH_CDNA5) { if (options.input_revision == ProcessorRevision::Unspecified || options.output_revision == ProcessorRevision::Unspecified) { return error(DiagnosticKind::Legalization, @@ -2051,7 +2051,7 @@ BinaryTranslator::BinaryTranslator(rj_code_arch_t guest_arch, rj_code_arch_t hos guest_arch, host_arch, options.input_revision, options.output_revision)) {} bool BinaryTranslator::is_gfx1250_b0_to_a0() const { - return guest_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && host_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && + return guest_arch_ == ROCJITSU_CODE_ARCH_CDNA5 && host_arch_ == ROCJITSU_CODE_ARCH_CDNA5 && options_.input_revision == ProcessorRevision::Gfx1250B0 && options_.output_revision == ProcessorRevision::Gfx1250A0; } @@ -2178,7 +2178,7 @@ void BinaryTranslator::verify_rewrite_discharge(TranslatedCodeObject &result) co uint32_t first_word = 0; std::memcpy(&first_word, text_bytes.data() + instruction_offset, sizeof(first_word)); - if (host_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && first_word == 0) { + if (host_arch_ == ROCJITSU_CODE_ARCH_CDNA5 && first_word == 0) { ++instruction_word_index; instruction_offset += sizeof(uint32_t); continue; @@ -2333,7 +2333,7 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob // A same-architecture gfx1250 translation is direction-specific: A0 and B0 // share an ELF machine ID, so both revisions must be given. Enforce this here // as well as in the C API. - if (guest_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && host_arch_ == ROCJITSU_CODE_ARCH_GFX1250) { + if (guest_arch_ == ROCJITSU_CODE_ARCH_CDNA5 && host_arch_ == ROCJITSU_CODE_ARCH_CDNA5) { if (options_.input_revision == ProcessorRevision::Unspecified || options_.output_revision == ProcessorRevision::Unspecified) { append_error(result.diagnostics, DiagnosticKind::Legalization, @@ -2430,7 +2430,7 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob if (descriptor_translations.empty()) { const bool descriptorless_gfx1250_b0_to_a0 = - guest_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && host_arch_ == ROCJITSU_CODE_ARCH_GFX1250 && + guest_arch_ == ROCJITSU_CODE_ARCH_CDNA5 && host_arch_ == ROCJITSU_CODE_ARCH_CDNA5 && options_.input_revision == ProcessorRevision::Gfx1250B0 && options_.output_revision == ProcessorRevision::Gfx1250A0; if (!descriptorless_gfx1250_b0_to_a0) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp index 12d03bf6ce0d..7c805f227c15 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/gfx1250_b0_to_a0_library.cpp @@ -161,7 +161,7 @@ rj_gfx1250_b0_to_a0_translate(const void *source_elf, size_t source_size, uint8_ rocjitsu::BinaryTranslatorOptions options; options.input_revision = rocjitsu::ProcessorRevision::Gfx1250B0; options.output_revision = rocjitsu::ProcessorRevision::Gfx1250A0; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); translator.set_trace_callback([&](const rocjitsu::TranslationTraceEvent &trace) { if (trace.changed) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp index 1f7aecad8910..afd91e3582fe 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/kernel_descriptor_translator.cpp @@ -76,7 +76,7 @@ constexpr uint16_t kTtmpRdna4GridX = 9; return supports_wave_size(wf); case ROCJITSU_CODE_ARCH_RDNA4: return supports_wave_size(wf); - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return supports_wave_size(wf); default: return false; @@ -103,7 +103,7 @@ constexpr uint16_t kTtmpRdna4GridX = 9; return rdna3_5::Isa::WF_SIZE; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::Isa::WF_SIZE; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return cdna5::Isa::WF_SIZE; default: return 64; @@ -130,7 +130,7 @@ constexpr uint16_t kTtmpRdna4GridX = 9; return rdna3_5::Isa::MAX_VGPRS_PER_WF; case ROCJITSU_CODE_ARCH_RDNA4: return rdna4::Isa::MAX_VGPRS_PER_WF; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: // gfx1250 extends each encoded VGPR operand with dynamic high-bank bits. // Descriptor validation must allow the complete addressable register // range even though its inherited RDNA base describes one 256-VGPR bank. @@ -160,7 +160,7 @@ constexpr uint16_t kTtmpRdna4GridX = 9; return HasAccVgpr; case ROCJITSU_CODE_ARCH_RDNA4: return HasAccVgpr; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return HasAccVgpr; default: return false; @@ -423,7 +423,7 @@ build_kernel_entry_prologue(const KD &src, rj_code_arch_t guest_arch, rj_code_ar // - Scratch/private-segment initialization is descriptor-driven today. If a // future target needs SGPR-based scratch setup, it should be appended here // and represented in KdTranslation::prologue_words, not hidden in the patcher. - if (arch_is_cdna(guest_arch) && host_arch == ROCJITSU_CODE_ARCH_RDNA4) + if (arch_is_cdna_4_or_lower(guest_arch) && host_arch == ROCJITSU_CODE_ARCH_RDNA4) append_rdna4_workgroup_grid_prologue(words, src, host_arch); return words; @@ -834,7 +834,7 @@ Rsrc3Layout rsrc3_layout(rj_code_arch_t arch) { return Rsrc3Layout::Gfx11; case ROCJITSU_CODE_ARCH_RDNA4: return Rsrc3Layout::Gfx120; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return Rsrc3Layout::Gfx125; default: return Rsrc3Layout::Incompatible; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3_virtual_lds.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3_virtual_lds.cpp index 400e469300f6..928544438e56 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3_virtual_lds.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3_virtual_lds.cpp @@ -566,7 +566,7 @@ void emit_virtual_lds_copy_temp_to_acc_range(std::vector &words, [[nodiscard]] std::optional reserve_cdna3_virtual_lds_base_sgpr_pair(TranslationContext &context, KernelBlockScope blocks, const KdTranslation &translation, rj_code_arch_t arch) { - if (!arch_is_cdna(arch)) + if (!arch_is_cdna_4_or_lower(arch)) return std::nullopt; auto note_sgpr_ref = [](uint32_t &count, RegisterRef ref) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp index 799c0f802d58..54db81f2f2cc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic_translator.cpp @@ -30,7 +30,7 @@ namespace { return {semantic_expand_rules_cdna4_to_cdna3(), {}}; // gfx1250 A0 and B0 share one architectural target ID. Select the B0-to-A0 // profile only for that explicit revision pair. - if (guest == ROCJITSU_CODE_ARCH_GFX1250 && host == ROCJITSU_CODE_ARCH_GFX1250 && + if (guest == ROCJITSU_CODE_ARCH_CDNA5 && host == ROCJITSU_CODE_ARCH_CDNA5 && input_revision == ProcessorRevision::Gfx1250B0 && output_revision == ProcessorRevision::Gfx1250A0) return rewrite_registry_gfx1250_b0_to_a0(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp index 25a659378387..e379b2741318 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/kernel_descriptor_scan.cpp @@ -173,13 +173,13 @@ scan_kernel_descriptors(std::span image, uint64_t text_offset, ui uint8_t kernel_wavefront_size(rj_code_arch_t arch, const KD &desc) { // CDNA kernels are Wave64 in the code objects currently handled here. - if (arch_is_cdna(arch)) + if (arch_is_cdna_4_or_lower(arch)) return 64; // gfx1250 is Wave32-only. Do not interpret a missing legacy descriptor bit // as Wave64: older producers may omit the bit even though the hardware has // no Wave64 launch mode. - if (arch == ROCJITSU_CODE_ARCH_GFX1250) + if (arch == ROCJITSU_CODE_ARCH_CDNA5) return 32; // RDNA descriptors opt into Wave32 with ENABLE_WAVEFRONT_SIZE32. If the bit is @@ -207,12 +207,12 @@ uint32_t descriptor_vgpr_granularity_for_wavefront(rj_code_arch_t arch, uint32_t // occupancy would mix two different hardware contracts. if (arch == ROCJITSU_CODE_ARCH_CDNA1) return 4; - if (arch_is_cdna(arch)) + if (arch_is_cdna_4_or_lower(arch)) return 8; // gfx1250 exposes four 256-VGPR banks selected by WAVE_MODE.VGPR_MSB. Its // AMDHSA descriptor allocates that combined Wave32 namespace in blocks of // 16 VGPRs, unlike the 8-VGPR Wave32 granule used by generic RDNA targets. - if (arch == ROCJITSU_CODE_ARCH_GFX1250) + if (arch == ROCJITSU_CODE_ARCH_CDNA5) return 16; if (arch_is_rdna(arch)) return wavefront_size == 32 ? 8 : 4; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp index 97b48c0bbe7b..846a0c5523c5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/code_object_patcher.cpp @@ -168,13 +168,13 @@ void insert_file_bytes(std::vector &image, Elf64_Ehdr &ehdr, [[nodiscard]] bool target_supports_wave32(rj_code_arch_t arch) { return arch == ROCJITSU_CODE_ARCH_RDNA1 || arch == ROCJITSU_CODE_ARCH_RDNA2 || arch == ROCJITSU_CODE_ARCH_RDNA3 || arch == ROCJITSU_CODE_ARCH_RDNA3_5 || - arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_GFX1250; + arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_CDNA5; } [[nodiscard]] bool target_uses_gfx10_plus_mode_bits(rj_code_arch_t arch) { return arch == ROCJITSU_CODE_ARCH_RDNA1 || arch == ROCJITSU_CODE_ARCH_RDNA2 || arch == ROCJITSU_CODE_ARCH_RDNA3 || arch == ROCJITSU_CODE_ARCH_RDNA3_5 || - arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_GFX1250; + arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_CDNA5; } [[nodiscard]] bool target_uses_wgp_mode(rj_code_arch_t arch) { @@ -191,12 +191,12 @@ void insert_file_bytes(std::vector &image, Elf64_Ehdr &ehdr, [[nodiscard]] bool target_clears_rsrc1_mode_bits(rj_code_arch_t arch) { // DX10_CLAMP and IEEE_MODE are deprecated on GFX12. Preserve them for GFX10 // and GFX11 targets where they still affect floating-point behavior. - return arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_GFX1250; + return arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_CDNA5; } [[nodiscard]] uint32_t target_default_inst_pref_size(rj_code_arch_t arch) { return arch == ROCJITSU_CODE_ARCH_RDNA3 || arch == ROCJITSU_CODE_ARCH_RDNA3_5 || - arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_GFX1250 + arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_CDNA5 ? 2 : 0; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp index 30a01dd2ccf5..f2365fd47122 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/instrumentor.cpp @@ -130,7 +130,8 @@ uint32_t max_scratch_offset_bytes(rj_code_arch_t arch) { // TODO: these two arch predicates duplicate logic that also lives in DBT // (kernel_descriptor_translator.cpp's arch_has_accvgpr / uses_gfx90a_accum_offset) // and code_object_patcher.cpp (target_uses_gfx90a_accum_offset). They should be -// consolidated into isa/isa_traits.h alongside arch_is_cdna/arch_is_rdna, but the +// consolidated into isa/isa_traits.h alongside arch_is_cdna_4_or_lower/arch_is_rdna, +// but the // arch_has_accvgpr copies disagree on CDNA1 (this one follows the physical AGPR file; // DBT's follows the HasAccVgpr trait, which models CDNA1 as zero), so unifying needs a // deliberate CDNA1-semantics decision. Kept DBI-local until then. @@ -165,7 +166,7 @@ bool arch_has_unified_vgpr_allocation(rj_code_arch_t arch) { case ROCJITSU_CODE_ARCH_RDNA3: case ROCJITSU_CODE_ARCH_RDNA3_5: case ROCJITSU_CODE_ARCH_RDNA4: - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return false; default: throw util::UnimplementedInst("unified VGPR allocation for target architecture"); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_loader.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_loader.cpp index 8deff84ebbee..ab9007afae69 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_loader.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_loader.cpp @@ -59,13 +59,13 @@ uint32_t config_u32(const std::unordered_map &cfg, con } uint32_t default_sgprs_per_wf(rj_code_arch_t arch) { - if (arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_GFX1250) + if (arch == ROCJITSU_CODE_ARCH_RDNA4 || arch == ROCJITSU_CODE_ARCH_CDNA5) return 128; return 112; } uint32_t default_vgprs_per_wf(rj_code_arch_t arch) { - if (arch == ROCJITSU_CODE_ARCH_GFX1250) + if (arch == ROCJITSU_CODE_ARCH_CDNA5) return 1024; return 256; } @@ -714,8 +714,8 @@ rj_code_arch_t parse_arch(const std::string &arch_str) { return ROCJITSU_CODE_ARCH_RDNA3_5; if (arch_str == "rdna4") return ROCJITSU_CODE_ARCH_RDNA4; - if (arch_str == "gfx1250") - return ROCJITSU_CODE_ARCH_GFX1250; + if (arch_str == "cdna5") + return ROCJITSU_CODE_ARCH_CDNA5; if (arch_str == "rv32i") return ROCJITSU_CODE_ARCH_RV32I; if (arch_str == "rv64i") @@ -743,8 +743,8 @@ const char *arch_to_string(rj_code_arch_t arch) { return "rdna3_5"; case ROCJITSU_CODE_ARCH_RDNA4: return "rdna4"; - case ROCJITSU_CODE_ARCH_GFX1250: - return "gfx1250"; + case ROCJITSU_CODE_ARCH_CDNA5: + return "cdna5"; case ROCJITSU_CODE_ARCH_RV32I: return "rv32i"; case ROCJITSU_CODE_ARCH_RV64I: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp index ad12dd542b06..0412950e5f34 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/hooks/rj_hsa_dbt_hooks.cpp @@ -4253,8 +4253,8 @@ hsa_status_t HSA_API rj_executable_load_agent_code_object( // gfx1250 A0 and B0 share an ELF machine ID, so a same-arch/same-mach match // does not identify the revision. When both revisions are configured, use the // selected same-ISA translation profile. Otherwise fail closed. - const bool gfx1250_same_target = source_target.arch == ROCJITSU_CODE_ARCH_GFX1250 && - config->target.arch == ROCJITSU_CODE_ARCH_GFX1250 && + const bool gfx1250_same_target = source_target.arch == ROCJITSU_CODE_ARCH_CDNA5 && + config->target.arch == ROCJITSU_CODE_ARCH_CDNA5 && source_target.mach == config->target.mach; const bool have_gfx1250_revisions = config->guest_revision != ProcessorRevision::Unspecified && config->host_revision != ProcessorRevision::Unspecified; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h index d7e46239dd77..6bbf449c512a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/isa.h @@ -75,7 +75,7 @@ struct Isa : amdgpu::RdnaIsaBase { // high-bank indexing rather than RDNA4 DISABLE_PERF. static constexpr bool MODE_HAS_GPR_IDX_EN = true; static constexpr uint32_t MAX_ADDRESSABLE_VGPRS_PER_WF = - isa_properties(ROCJITSU_CODE_ARCH_GFX1250).max_addressable_vgprs_per_wf; + isa_properties(ROCJITSU_CODE_ARCH_CDNA5).max_addressable_vgprs_per_wf; static std::optional resolved_vgpr_offset(OperandType opr_type, int ev); static std::optional resolved_vgpr_offset(const amdgpu::Wavefront &wf, @@ -89,7 +89,7 @@ struct Isa : amdgpu::RdnaIsaBase { namespace rocjitsu { -template <> struct IsaTrait { +template <> struct IsaTrait { using type = cdna5::Isa; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/target_descriptor.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/target_descriptor.h index bd19d3d7b1cd..0cc2f7d68c53 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/target_descriptor.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/target_descriptor.h @@ -10,6 +10,7 @@ namespace rocjitsu::cdna5 { +inline constexpr std::array kTargetAliases{"gfx1250"}; inline constexpr std::array kGpuTargets{{ {ROCJITSU_CODE_TARGET_GFX1250, "gfx1250", EF_AMDGPU_MACH_AMDGCN_GFX1250}, }}; @@ -18,8 +19,9 @@ constexpr IsaTargetDescriptor make_target_descriptor(bool supports_execution, IsaTargetDescriptor::DecoderFactory decoder_factory) { return { - .id = "gfx1250", - .architecture_id = ROCJITSU_CODE_ARCH_GFX1250, + .id = "cdna5", + .aliases = kTargetAliases, + .architecture_id = ROCJITSU_CODE_ARCH_CDNA5, .gpu_targets = kGpuTargets, .decoder_factory = decoder_factory, .supports_execution = supports_execution, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp index 578abd3f40db..f59df653c9b6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3p.cpp @@ -14,7 +14,7 @@ namespace cdna5 { namespace { -const char *gfx1250_matrix_fmt_name(uint32_t fmt) { +const char *cdna5_matrix_fmt_name(uint32_t fmt) { switch (fmt) { case 0: return "MATRIX_FMT_FP8"; @@ -31,7 +31,7 @@ const char *gfx1250_matrix_fmt_name(uint32_t fmt) { } } -const char *gfx1250_matrix_scale_fmt_name(uint32_t fmt) { +const char *cdna5_matrix_scale_fmt_name(uint32_t fmt) { switch (fmt) { case 0: return "MATRIX_SCALE_FMT_E8"; @@ -44,7 +44,7 @@ const char *gfx1250_matrix_scale_fmt_name(uint32_t fmt) { } } -uint32_t gfx1250_matrix_fmt_element_bits(uint32_t fmt) { +uint32_t cdna5_matrix_fmt_element_bits(uint32_t fmt) { switch (fmt) { case 2: case 3: @@ -56,46 +56,46 @@ uint32_t gfx1250_matrix_fmt_element_bits(uint32_t fmt) { } } -int gfx1250_matrix_fmt_operand_size_bits(uint32_t fmt, uint32_t dim, uint32_t k) { - return static_cast((dim * k * gfx1250_matrix_fmt_element_bits(fmt)) / 32); +int cdna5_matrix_fmt_operand_size_bits(uint32_t fmt, uint32_t dim, uint32_t k) { + return static_cast((dim * k * cdna5_matrix_fmt_element_bits(fmt)) / 32); } -bool gfx1250_scaled_wmma_is_scale16(const MachineInst *inst) { +bool cdna5_scaled_wmma_is_scale16(const MachineInst *inst) { return reinterpret_cast(inst)->op == 0x3a; } -bool gfx1250_scaled_wmma_is_f4_32x16x128(const MachineInst *inst) { +bool cdna5_scaled_wmma_is_f4_32x16x128(const MachineInst *inst) { return reinterpret_cast(inst + 2)->op == 0x88; } -const char *gfx1250_scaled_wmma_mnemonic(const MachineInst *inst) { - if (gfx1250_scaled_wmma_is_f4_32x16x128(inst)) - return gfx1250_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_32x16x128_f4" - : "v_wmma_scale_f32_32x16x128_f4"; - return gfx1250_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_16x16x128_f8f6f4" - : "v_wmma_scale_f32_16x16x128_f8f6f4"; +const char *cdna5_scaled_wmma_mnemonic(const MachineInst *inst) { + if (cdna5_scaled_wmma_is_f4_32x16x128(inst)) + return cdna5_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_32x16x128_f4" + : "v_wmma_scale_f32_32x16x128_f4"; + return cdna5_scaled_wmma_is_scale16(inst) ? "v_wmma_scale16_f32_16x16x128_f8f6f4" + : "v_wmma_scale_f32_16x16x128_f8f6f4"; } -int gfx1250_scale_operand_size_bits(const MachineInst *inst) { - return gfx1250_scaled_wmma_is_scale16(inst) ? 64 : 32; +int cdna5_scale_operand_size_bits(const MachineInst *inst) { + return cdna5_scaled_wmma_is_scale16(inst) ? 64 : 32; } -int gfx1250_scaled_wmma_dst_size_bits(const MachineInst *inst) { - return gfx1250_scaled_wmma_is_f4_32x16x128(inst) ? 512 : 256; +int cdna5_scaled_wmma_dst_size_bits(const MachineInst *inst) { + return cdna5_scaled_wmma_is_f4_32x16x128(inst) ? 512 : 256; } -int gfx1250_scaled_wmma_src0_size_bits(const MachineInst *inst) { +int cdna5_scaled_wmma_src0_size_bits(const MachineInst *inst) { const auto *high = reinterpret_cast(inst + 2); - if (gfx1250_scaled_wmma_is_f4_32x16x128(inst)) + if (cdna5_scaled_wmma_is_f4_32x16x128(inst)) return 512; - return gfx1250_matrix_fmt_operand_size_bits(high->opsel, 16, 128); + return cdna5_matrix_fmt_operand_size_bits(high->opsel, 16, 128); } -int gfx1250_scaled_wmma_src1_size_bits(const MachineInst *inst) { +int cdna5_scaled_wmma_src1_size_bits(const MachineInst *inst) { const auto *high = reinterpret_cast(inst + 2); - if (gfx1250_scaled_wmma_is_f4_32x16x128(inst)) + if (cdna5_scaled_wmma_is_f4_32x16x128(inst)) return 256; - return gfx1250_matrix_fmt_operand_size_bits((high->pad_14 << 2) | high->opsel_hi, 16, 128); + return cdna5_matrix_fmt_operand_size_bits((high->pad_14 << 2) | high->opsel_hi, 16, 128); } } // namespace @@ -2353,10 +2353,10 @@ VWmmaF3216x16x128F8f6f4Vop3p::VWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *in reinterpret_cast(inst), selected_exec_fn(InstructionExecutionId::VWmmaF3216x16x128F8f6f4Vop3p)), vdst(256, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), - src0(gfx1250_matrix_fmt_operand_size_bits(reinterpret_cast(inst)->opsel, - 16, 128), + src0(cdna5_matrix_fmt_operand_size_bits(reinterpret_cast(inst)->opsel, 16, + 128), OperandType::OPR_SRC_VGPR, reinterpret_cast(inst)->src0), - src1(gfx1250_matrix_fmt_operand_size_bits( + src1(cdna5_matrix_fmt_operand_size_bits( ((reinterpret_cast(inst)->pad_14 << 2) | reinterpret_cast(inst)->opsel_hi), 16, 128), @@ -2396,9 +2396,9 @@ DecodeResult decodeVWmmaF3216x16x128F8f6f4Vop3p(const MachineInst *opcode, void VWmmaF3216x16x128F8f6f4Vop3p::build_modifiers(std::string &out) const { out += " matrix_a_fmt:"; - out += gfx1250_matrix_fmt_name(inst_.opsel); + out += cdna5_matrix_fmt_name(inst_.opsel); out += " matrix_b_fmt:"; - out += gfx1250_matrix_fmt_name((inst_.pad_14 << 2) | inst_.opsel_hi); + out += cdna5_matrix_fmt_name((inst_.pad_14 << 2) | inst_.opsel_hi); } VPkMinimum3F16Vop3p::VPkMinimum3F16Vop3p(const MachineInst *inst) @@ -4612,20 +4612,20 @@ DecodeResult decodeVWmmaF3232x16x128F4Vop3p(const MachineInst *opcode, } // namespace detail VWmmaScaleF32Vop3px2::VWmmaScaleF32Vop3px2(const MachineInst *inst) - : Vop3p(gfx1250_scaled_wmma_mnemonic(inst), reinterpret_cast(inst + 2), + : Vop3p(cdna5_scaled_wmma_mnemonic(inst), reinterpret_cast(inst + 2), selected_exec_fn(InstructionExecutionId::VWmmaScaleF32Vop3px2), Vop3p::ExtensionDecodePolicy::Skip), - vdst(gfx1250_scaled_wmma_dst_size_bits(inst), OperandType::OPR_VGPR, + vdst(cdna5_scaled_wmma_dst_size_bits(inst), OperandType::OPR_VGPR, reinterpret_cast(inst + 2)->vdst), - src0(gfx1250_scaled_wmma_src0_size_bits(inst), OperandType::OPR_SRC_VGPR, + src0(cdna5_scaled_wmma_src0_size_bits(inst), OperandType::OPR_SRC_VGPR, reinterpret_cast(inst + 2)->src0), - src1(gfx1250_scaled_wmma_src1_size_bits(inst), OperandType::OPR_SRC_VGPR, + src1(cdna5_scaled_wmma_src1_size_bits(inst), OperandType::OPR_SRC_VGPR, reinterpret_cast(inst + 2)->src1), - src2(gfx1250_scaled_wmma_dst_size_bits(inst), OperandType::OPR_SRC_VGPR_OR_INLINE, + src2(cdna5_scaled_wmma_dst_size_bits(inst), OperandType::OPR_SRC_VGPR_OR_INLINE, reinterpret_cast(inst + 2)->src2), - scale_src0(gfx1250_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, + scale_src0(cdna5_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, reinterpret_cast(inst)->src0), - scale_src1(gfx1250_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, + scale_src1(cdna5_scale_operand_size_bits(inst), OperandType::OPR_SRC_SIMPLE, reinterpret_cast(inst)->src1), scale_inst_(*reinterpret_cast(inst)) { raw_words_ = {inst[0], inst[1], inst[2], inst[3]}; @@ -4654,11 +4654,11 @@ void VWmmaScaleF32Vop3px2::build_modifiers(std::string &out) const { const uint32_t matrix_b_fmt = (inst_.pad_14 << 2) | inst_.opsel_hi; if (matrix_a_fmt != 0) { out += " matrix_a_fmt:"; - out += gfx1250_matrix_fmt_name(matrix_a_fmt); + out += cdna5_matrix_fmt_name(matrix_a_fmt); } if (matrix_b_fmt != 0) { out += " matrix_b_fmt:"; - out += gfx1250_matrix_fmt_name(matrix_b_fmt); + out += cdna5_matrix_fmt_name(matrix_b_fmt); } } if (scale_inst_.opsel & 0x1u) @@ -4669,11 +4669,11 @@ void VWmmaScaleF32Vop3px2::build_modifiers(std::string &out) const { const uint32_t matrix_b_scale_fmt = scale_inst_.neg_hi & 0x3u; if (matrix_a_scale_fmt != 0) { out += " matrix_a_scale_fmt:"; - out += gfx1250_matrix_scale_fmt_name(matrix_a_scale_fmt); + out += cdna5_matrix_scale_fmt_name(matrix_a_scale_fmt); } if (matrix_b_scale_fmt != 0) { out += " matrix_b_scale_fmt:"; - out += gfx1250_matrix_scale_fmt_name(matrix_b_scale_fmt); + out += cdna5_matrix_scale_fmt_name(matrix_b_scale_fmt); } if ((scale_inst_.opsel >> 2) & 0x1u) out += " matrix_a_reuse"; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/isa_properties.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/isa_properties.h index db56f7bce523..b82989557c79 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/isa_properties.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/isa_properties.h @@ -138,7 +138,7 @@ inline constexpr uint32_t MAX_SUPPORTED_ADDRESSABLE_VGPRS_PER_WF = 1024; .descriptor_vgpr_count_granule_wave32 = 8, .descriptor_vgpr_count_granule_wave64 = 4, }; - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return { .supports_wgp_mode = false, .descriptor_sgpr_count_encoded = false, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h index de30b049a31f..3e67cc6923f2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/isa_traits.h @@ -83,11 +83,15 @@ template inline constexpr bool supports_wave_size(uint32_t wf) { return (wf == 32 || wf == 64) && wf >= Isa::WF_SIZE && wf <= Isa::WF_SIZE_MAX; } -/// @brief Return true when @p arch belongs to the CDNA ISA family. +/// @brief Return true when @p arch is CDNA1 through CDNA4. /// -/// @details Keep architecture-family policy near the ISA trait declarations so -/// DBT call sites do not grow their own partial CDNA/RDNA switch statements. -[[nodiscard]] inline constexpr bool arch_is_cdna(rj_code_arch_t arch) { +/// @details This predicate represents the CDNA1-4 descriptor and wavefront +/// policy boundary, not the entire CDNA family. Rocjitsu models CDNA5, which +/// originated as gfx1250, with RDNA4-derived descriptor and wavefront +/// properties. Adding CDNA5 here would silently change those decisions in +/// callers. Keep this policy near the ISA trait declarations so DBT call sites +/// do not grow their own partial architecture switch statements. +[[nodiscard]] inline constexpr bool arch_is_cdna_4_or_lower(rj_code_arch_t arch) { return arch == ROCJITSU_CODE_ARCH_CDNA1 || arch == ROCJITSU_CODE_ARCH_CDNA2 || arch == ROCJITSU_CODE_ARCH_CDNA3 || arch == ROCJITSU_CODE_ARCH_CDNA4; } @@ -116,7 +120,7 @@ template inline constexpr bool supports_wave_size(uint32_t wf) { case ROCJITSU_CODE_ARCH_RDNA3: case ROCJITSU_CODE_ARCH_RDNA3_5: case ROCJITSU_CODE_ARCH_RDNA4: - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: default: return false; } @@ -138,7 +142,7 @@ template inline constexpr bool supports_wave_size(uint32_t wf) { /// the granule-0 encoding rather than a budget any caller depends on. Only where the field is /// live can an SGPR requirement above the decoded count under-provision anyone. [[nodiscard]] inline constexpr bool arch_descriptor_encodes_sgpr_allocation(rj_code_arch_t arch) { - return !(arch_is_rdna(arch) || arch == ROCJITSU_CODE_ARCH_GFX1250); + return !(arch_is_rdna(arch) || arch == ROCJITSU_CODE_ARCH_CDNA5); } [[nodiscard]] inline constexpr uint32_t arch_descriptor_sgpr_allocation_limit(rj_code_arch_t arch) { @@ -147,9 +151,9 @@ template inline constexpr bool supports_wave_size(uint32_t wf) { // scratch range in CdnaIsaBase), so they are named here rather than derived. constexpr uint32_t kCdnaDescriptorSgprLimit = 112; constexpr uint32_t kRdnaDescriptorSgprLimit = 106; - if (arch_is_cdna(arch)) + if (arch_is_cdna_4_or_lower(arch)) return kCdnaDescriptorSgprLimit; - if (arch_is_rdna(arch) || arch == ROCJITSU_CODE_ARCH_GFX1250) + if (arch_is_rdna(arch) || arch == ROCJITSU_CODE_ARCH_CDNA5) return kRdnaDescriptorSgprLimit; return 0; } @@ -167,17 +171,17 @@ template inline constexpr bool supports_wave_size(uint32_t wf) { return 64u * 1024u; case ROCJITSU_CODE_ARCH_CDNA4: return 160u * 1024u; + case ROCJITSU_CODE_ARCH_CDNA5: + // gfx1250 can allocate up to 320 KiB to one workgroup. This is distinct + // from the configurable LDS/vector-cache partition sizes reported for a + // TCP, which must not be used as the descriptor allocation ceiling. + return 320u * 1024u; case ROCJITSU_CODE_ARCH_RDNA1: case ROCJITSU_CODE_ARCH_RDNA2: case ROCJITSU_CODE_ARCH_RDNA3: case ROCJITSU_CODE_ARCH_RDNA3_5: case ROCJITSU_CODE_ARCH_RDNA4: return 64u * 1024u; - case ROCJITSU_CODE_ARCH_GFX1250: - // gfx1250 can allocate up to 320 KiB to one workgroup. This is distinct - // from the configurable LDS/vector-cache partition sizes reported for a - // TCP, which must not be used as the descriptor allocation ceiling. - return 320u * 1024u; default: return 0; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp index b8bbfaf39ef2..28723c0d9d4e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp @@ -49,10 +49,10 @@ void CommandProcessor::configure_for_arch(rj_code_arch_t arch) { packed_tid_ = arch == ROCJITSU_CODE_ARCH_CDNA2 || arch == ROCJITSU_CODE_ARCH_CDNA3 || arch == ROCJITSU_CODE_ARCH_CDNA4 || arch == ROCJITSU_CODE_ARCH_RDNA3 || arch == ROCJITSU_CODE_ARCH_RDNA3_5 || arch == ROCJITSU_CODE_ARCH_RDNA4 || - arch == ROCJITSU_CODE_ARCH_GFX1250; + arch == ROCJITSU_CODE_ARCH_CDNA5; sdma_packet_dialect_ = SdmaPacketDialect::Legacy; - if (arch == ROCJITSU_CODE_ARCH_GFX1250) + if (arch == ROCJITSU_CODE_ARCH_CDNA5) sdma_packet_dialect_ = SdmaPacketDialect::Gfx1250; else if (arch == ROCJITSU_CODE_ARCH_RDNA3 || arch == ROCJITSU_CODE_ARCH_RDNA3_5 || arch == ROCJITSU_CODE_ARCH_RDNA4) @@ -224,7 +224,7 @@ bool compute_pgm_rsrc1_mode_preserves_dx10_ieee(rj_code_arch_t arch) { case ROCJITSU_CODE_ARCH_RDNA3_5: return true; case ROCJITSU_CODE_ARCH_RDNA4: - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: case ROCJITSU_CODE_ARCH_RV32I: case ROCJITSU_CODE_ARCH_RV64I: case ROCJITSU_CODE_ARCH_NUM_ARCHS: @@ -246,7 +246,7 @@ bool compute_pgm_rsrc1_mode_has_debug_field(rj_code_arch_t arch) { case ROCJITSU_CODE_ARCH_RDNA3_5: return true; case ROCJITSU_CODE_ARCH_RDNA4: - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: case ROCJITSU_CODE_ARCH_RV32I: case ROCJITSU_CODE_ARCH_RV64I: case ROCJITSU_CODE_ARCH_NUM_ARCHS: @@ -1506,7 +1506,7 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.kernarg_size = kd.kernarg_size; dp.num_user_sgprs = user_sgprs; dp.kernel_code_properties = kd.kernel_code_properties; - if (arch == ROCJITSU_CODE_ARCH_GFX1250) { + if (arch == ROCJITSU_CODE_ARCH_CDNA5) { const uint32_t named_barrier_blocks = AMDHSA_BITS_GET(kd.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT); dp.num_named_barriers = std::min(named_barrier_blocks * 4u, ComputeUnitCore::kMaxNamedBarriers); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp index 4b2d7f0424bc..71530a3a7094 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp @@ -119,7 +119,7 @@ std::unique_ptr ComputeUnitCore::create(std::string name, const ROCJITSU_CU_CASE(ROCJITSU_CODE_ARCH_RDNA3, rdna3::Isa); ROCJITSU_CU_CASE(ROCJITSU_CODE_ARCH_RDNA3_5, rdna3_5::Isa); ROCJITSU_CU_CASE(ROCJITSU_CODE_ARCH_RDNA4, rdna4::Isa); - ROCJITSU_CU_CASE(ROCJITSU_CODE_ARCH_GFX1250, cdna5::Isa); + ROCJITSU_CU_CASE(ROCJITSU_CODE_ARCH_CDNA5, cdna5::Isa); default: break; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp index ceb9332eef6d..4ef756d358b3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp @@ -337,7 +337,7 @@ HwregTable table_for_arch(rj_code_arch_t arch) { return make_table(RDNA3_HWREGS); case ROCJITSU_CODE_ARCH_RDNA4: return make_table(RDNA4_HWREGS); - case ROCJITSU_CODE_ARCH_GFX1250: + case ROCJITSU_CODE_ARCH_CDNA5: return make_table(GFX1250_HWREGS); default: return {nullptr, 0}; diff --git a/emulation/rocjitsu/scripts/generate-amdisa.sh b/emulation/rocjitsu/scripts/generate-amdisa.sh index 2675d751376f..1df9f4585b83 100755 --- a/emulation/rocjitsu/scripts/generate-amdisa.sh +++ b/emulation/rocjitsu/scripts/generate-amdisa.sh @@ -79,8 +79,8 @@ isa_entries=( "rdna3:$isa_xml/amdgpu_isa_rdna3.xml" "rdna3_5:$isa_xml/amdgpu_isa_rdna3_5.xml" "rdna4:$isa_xml/amdgpu_isa_rdna4.xml" - # CDNA5 retains gfx1250 as its MR ISA and logical architecture key. - "gfx1250:$cdna5_xml" + # CDNA5 retains gfx1250 as its MR ISA target identifier. + "cdna5:$cdna5_xml" ) for dir in "$repo" "$rocjitsu" "$isa_out" "$dbt_out" "$venv"; do diff --git a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp index c773c96e4c4d..eb56357cfee3 100644 --- a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp +++ b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp @@ -419,7 +419,7 @@ TEST(AqlDispatchTest, InitializesModeFromComputePgmRsrc1) { {"rdna3", kGfx11Endpgm, common_mode | (1u << 8) | (1u << 9) | (1u << 11)}, {"rdna3_5", kGfx11Endpgm, common_mode | (1u << 8) | (1u << 9) | (1u << 11)}, {"rdna4", kGfx11Endpgm, common_mode}, - {"gfx1250", kGfx11Endpgm, common_mode}, + {"cdna5", kGfx11Endpgm, common_mode}, }; for (const ModeInitCase &mode_case : cases) { @@ -442,7 +442,7 @@ TEST(AqlDispatchTest, InitializesModeFromComputePgmRsrc1) { TEST(RdnaDispatchTest, Gfx1250DoesNotEnableWgpMode) { const uint32_t code[] = {SOPP_S_ENDPGM}; - VmFixture f("gfx1250", 2, 10, /*lds_size_kb=*/64, /*sgprs_per_wf=*/128); + VmFixture f("cdna5", 2, 10, /*lds_size_kb=*/64, /*sgprs_per_wf=*/128); uint64_t ko = f.write_kernel(0x1000, code, sizeof(code), 104, 64, 2, 128 * 1024, /*wgp_mode=*/true); test::AqlQueue queue(f.mem(), f.cp()); @@ -1909,7 +1909,7 @@ TEST_P(IsaTest, VendorSpecificRejectsUnsupportedFormats) { } TEST(ClusterDispatchTest, RejectsClusterThatCannotFitWithoutSpinning) { - VmFixture f("gfx1250", 1, 1); + VmFixture f("cdna5", 1, 1); const uint32_t code[] = {0xBFB00000u}; // s_endpgm uint64_t ko = f.write_kernel(0x1000, code, sizeof(code)); @@ -1926,7 +1926,7 @@ TEST(ClusterDispatchTest, RejectsClusterThatCannotFitWithoutSpinning) { } TEST(ClusterDispatchTest, AccountsForPerWorkgroupLdsAlignmentWhenPlanningCluster) { - VmFixture f("gfx1250", 1, 3, /*lds_size_kb=*/1); + VmFixture f("cdna5", 1, 3, /*lds_size_kb=*/1); const uint32_t code[] = {0xBFB00000u}; // s_endpgm uint64_t ko = f.write_kernel(0x1000, code, sizeof(code)); diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 5dd5426d682f..3abc68e015ba 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -520,23 +520,22 @@ TEST(CfgAnalysis, Gfx1250ZeroPaddingTerminatesFallthrough) { Case{"setup sequence followed by padding", {0xee174000u, 0x00040000u, 0, 0x7e000000u, 0xb9800641u, 1u, 0}, true}, - Case{"ordinary fallthrough into padding", - {build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), 0}, - true}, + Case{ + "ordinary fallthrough into padding", {build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), 0}, true}, Case{"architectural terminator followed by padding", - {build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), 0}, + {build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), 0}, false}, Case{"unconditional branch followed by padding", - {build_s_branch(-1, ROCJITSU_CODE_ARCH_GFX1250), 0}, + {build_s_branch(-1, ROCJITSU_CODE_ARCH_CDNA5), 0}, false}, }; for (const auto &test_case : cases) { SCOPED_TRACE(test_case.name); TestCodeObject co(test_case.words); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); EXPECT_EQ(blocks[0]->has_implicit_terminator(), test_case.has_implicit_terminator); @@ -548,12 +547,12 @@ TEST(CfgAnalysis, Gfx1250ConditionalBranchKeepsTakenEdgeWhenPaddingTerminatesFal std::vector words = { kSCbranchScc0PlusOne, // 0x00 -> 0x08; fallthrough reaches padding at 0x04. 0, - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 2u); EXPECT_TRUE(blocks[0]->has_implicit_terminator()); @@ -564,17 +563,17 @@ TEST(CfgAnalysis, Gfx1250ConditionalBranchKeepsTakenEdgeWhenPaddingTerminatesFal TEST(CfgAnalysis, DirectCallToImplicitNonreturningTargetDropsFallthrough) { constexpr uint16_t kReturnSreg = 30; std::vector words = { - rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_GFX1250), - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x04 continuation. + rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_CDNA5), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x04 continuation. 0xb9800641u, 1u, 0, // 0x08 clang unreachable-stub target followed by padding. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -598,16 +597,16 @@ TEST(CfgAnalysis, DirectCallToPaddingTerminatedBlockWithUnresolvedTakenTargetKee constexpr uint16_t kReturnSreg = 30; constexpr uint32_t kSCbranchScc0FarOutOfSection = 0xbfa11000u; std::vector words = { - rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_GFX1250), - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x04 continuation. - kSCbranchScc0FarOutOfSection, // 0x08 callee: taken target is not in .text. - 0, // 0x0c padding terminates the fallthrough. + rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_CDNA5), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x04 continuation. + kSCbranchScc0FarOutOfSection, // 0x08 callee: taken target is not in .text. + 0, // 0x0c padding terminates the fallthrough. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *caller = block_starting_at(blocks, 0); auto *continuation = block_starting_at(blocks, 4); @@ -1982,14 +1981,14 @@ TEST(CfgAnalysis, Gfx1250RecoversSignedDeltaTemplateWithPrefetch) { // 0x40: s_add_co_ci_u32. cdna5::build_sop1(cdna5::kSSetPcI64Sop1, {.ssrc0 = kPcSreg, .sdst = 0})[0], // 0x44: s_set_pc_i64. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x48: not a target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: shared target. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: not a target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: shared target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *sub_consumer = block_starting_at(blocks, 44); auto *add_consumer = block_starting_at(blocks, 68); @@ -2058,14 +2057,14 @@ TEST(CfgAnalysis, Gfx1250RecoversSignedDeltaTemplateWithXcntWaitAndPrefetch) { // 0x40: s_add_co_ci_u32. cdna5::build_sop1(cdna5::kSSetPcI64Sop1, {.ssrc0 = kPcSreg, .sdst = 0})[0], // 0x44: add consumer. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x48: not a target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: shared target. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: not a target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: shared target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *sub_consumer = block_starting_at(blocks, 44); auto *add_consumer = block_starting_at(blocks, 68); @@ -2139,14 +2138,14 @@ TEST(CfgAnalysis, Gfx1250SignedDeltaRejectsMoveClobberingTemporary) { // 0x40: s_add_co_ci_u32. cdna5::build_sop1(cdna5::kSSetPcI64Sop1, {.ssrc0 = kPcSreg, .sdst = 0})[0], // 0x44: s_set_pc_i64. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x48: not a target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: shared target. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: not a target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: shared target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); // Clobbering the temporary on the subtract half breaks that half of the paired // signed-delta template. Because the two halves cross-validate to the same static @@ -2178,16 +2177,16 @@ TEST(CfgAnalysis, IndirectRecoveryPrefilterAdmitsGfx1250LaneStashSwapPc) { 0xD7600000u, 0x0201012Cu, // 0x20: v_readlane_b32 s0, v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x28: v_readlane_b32 s1, v44, 1. - 0xBE9E4900u, // 0x30: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x34: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: target. + 0x0201032Cu, // 0x28: v_readlane_b32 s1, v44, 1. + 0xBE9E4900u, // 0x30: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x34: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 48); auto *target = block_starting_at(blocks, 56); @@ -2221,16 +2220,16 @@ TEST(CfgAnalysis, Gfx1250WideVgprWriteInvalidatesStashedLane) { 0xD7600000u, 0x0201012Cu, // 0x28: v_readlane_b32 s0, v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x30: v_readlane_b32 s1, v44, 1. - 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: would-be target. + 0x0201032Cu, // 0x30: v_readlane_b32 s1, v44, 1. + 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: would-be target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); size_t total_fixups = 0; for (const auto &block : blocks) @@ -2265,16 +2264,16 @@ TEST(CfgAnalysis, Gfx1250ExplicitVgprWriteInvalidatesOnlyItsDestinationBank) { 0xD7600000u, 0x02010100u, // 0x34: v_readlane_b32 s0, physical v256, 0. 0xD7600001u, - 0x02010300u, // 0x3c: s1 <- physical v256 lane 1. - 0xBE9E4900u, // 0x44: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x48: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: target. + 0x02010300u, // 0x3c: s1 <- physical v256 lane 1. + 0xBE9E4900u, // 0x44: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x48: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 68); ASSERT_NE(consumer, nullptr); @@ -2300,16 +2299,16 @@ TEST(CfgAnalysis, Gfx1250CarriesLaneStashAcrossProvenBlockBoundary) { 0xD7600000u, 0x0201012Cu, // 0x24: v_readlane_b32 s0, v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x2c: v_readlane_b32 s1, v44, 1. - 0xBE9E4900u, // 0x34: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: would-be target. + 0x0201032Cu, // 0x2c: v_readlane_b32 s1, v44, 1. + 0xBE9E4900u, // 0x34: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: would-be target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 52); ASSERT_NE(consumer, nullptr); @@ -2339,24 +2338,24 @@ TEST(CfgAnalysis, Gfx1250UnreachablePostRocrAbortBlockDoesNotPoisonLaneStash) { 0xD761002Cu, 0x02010000u, // 0x10: v_writelane_b32 v44, s0, 0. 0xD761002Cu, - 0x02010201u, // 0x18: lane 1 <- s1. - live_branch[0], // 0x20: -> join at 0x30. - build_s_trap(ROCJITSU_CODE_ARCH_GFX1250, 2), // 0x24: abort terminator. - dead_branch[0], // 0x28: dead edge -> 0x30. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x2c: dead padding. + 0x02010201u, // 0x18: lane 1 <- s1. + live_branch[0], // 0x20: -> join at 0x30. + build_s_trap(ROCJITSU_CODE_ARCH_CDNA5, 2), // 0x24: abort terminator. + dead_branch[0], // 0x28: dead edge -> 0x30. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x2c: dead padding. 0xD7600000u, 0x0201012Cu, // 0x30: v_readlane_b32 s0, v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x38: lane 1 -> s1. - call[0], // 0x40: s_swap_pc_i64. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x44: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x48: target. + 0x0201032Cu, // 0x38: lane 1 -> s1. + call[0], // 0x40: s_swap_pc_i64. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x44: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x48: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, {}, + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5, {}, ExternalEntryPolicy::ExplicitOnly); auto *consumer = block_starting_at(blocks, 64); @@ -2375,10 +2374,10 @@ TEST(CfgAnalysis, Gfx1250ExplicitOnlyRecoversLaneStashInRecoveredCallee) { 0xBE804700u, // 0x00: s_get_pc_i64 s[0:1]. 0xA980FE00u, 20u, - 0u, // 0x04: s_add_nc_u64 ..., lit64(20) -> helper 0x18. - 0xBE9E4900u, // 0x10: outer s_swap_pc_i64 -> 0x18. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x14: outer continuation. - 0xBE804700u, // 0x18: helper s_get_pc_i64. + 0u, // 0x04: s_add_nc_u64 ..., lit64(20) -> helper 0x18. + 0xBE9E4900u, // 0x10: outer s_swap_pc_i64 -> 0x18. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x14: outer continuation. + 0xBE804700u, // 0x18: helper s_get_pc_i64. 0xA980FE00u, 60u, 0u, // 0x1c: s_add_nc_u64 ..., lit64(60) -> target 0x58. @@ -2389,18 +2388,18 @@ TEST(CfgAnalysis, Gfx1250ExplicitOnlyRecoversLaneStashInRecoveredCallee) { 0xD7600000u, 0x0201012Cu, // 0x38: v_readlane_b32 s0, v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x40: lane 1 -> s1. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x48: padding. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: padding. - 0xBE9E4900u, // 0x50: inner call -> 0x58. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x54: inner continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x58: inner target. + 0x0201032Cu, // 0x40: lane 1 -> s1. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: padding. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: padding. + 0xBE9E4900u, // 0x50: inner call -> 0x58. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x54: inner continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x58: inner target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, {}, + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5, {}, ExternalEntryPolicy::ExplicitOnly); auto *outer_consumer = block_starting_at(blocks, 16); @@ -2428,24 +2427,24 @@ TEST(CfgAnalysis, Gfx1250DirectCallKillsCarriedLaneStash) { 0x02010000u, // 0x10: v_writelane_b32 v48, s0, 0. 0xD7610030u, 0x02010201u, // 0x18: v_writelane_b32 v48, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x20: direct call -> callee at 0x40. 0xD7600000u, 0x02010130u, // 0x24: continuation reads the pre-call low half. 0xD7600001u, - 0x02010330u, // 0x2c: continuation reads the high half. - 0xBE9E4900u, // 0x34: stale s_swap_pc_i64. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: stale target. - clobber[0], // 0x40: callee clobbers v48. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x02010330u, // 0x2c: continuation reads the high half. + 0xBE9E4900u, // 0x34: stale s_swap_pc_i64. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: stale target. + clobber[0], // 0x40: callee clobbers v48. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x44: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); size_t total_fixups = 0; for (const auto &block : blocks) @@ -2466,24 +2465,24 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryPreservesUnwrittenCallerSavedLaneStas 0x02010000u, // 0x10: v_writelane_b32 stash_vgpr, s0, 0. 0xD7610000u | stash_vgpr, 0x02010201u, // 0x18: v_writelane_b32 stash_vgpr, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x20: direct call -> callee at 0x40. 0xD7600000u, 0x02010100u | stash_vgpr, // 0x24: continuation reads the low half. 0xD7600001u, - 0x02010300u | stash_vgpr, // 0x2c: reads the high half. - 0xBE9E4900u, // 0x34: recovered s_swap_pc_i64. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: stashed target. - unrelated_write[0], // 0x40: callee writes only v2. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x02010300u | stash_vgpr, // 0x2c: reads the high half. + 0xBE9E4900u, // 0x34: recovered s_swap_pc_i64. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: stashed target. + unrelated_write[0], // 0x40: callee writes only v2. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x44: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2509,24 +2508,24 @@ TEST(CfgAnalysis, Gfx1250RelativeVgprDestinationDisablesExactCalleeSummary) { 0x02010000u, // 0x10: v_writelane_b32 v48, s0, 0. 0xD7610030u, 0x02010201u, // 0x18: v_writelane_b32 v48, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x20: direct call -> callee at 0x40. 0xD7600000u, 0x02010130u, // 0x24: continuation reads the low half. 0xD7600001u, - 0x02010330u, // 0x2c: reads the high half. - 0xBE9E4900u, // 0x34: must not use a stale target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: stale target. - relative_write[0], // 0x40: runtime-selected VGPR destination. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x02010330u, // 0x2c: reads the high half. + 0xBE9E4900u, // 0x34: must not use a stale target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: stale target. + relative_write[0], // 0x40: runtime-selected VGPR destination. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x44: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2555,23 +2554,23 @@ TEST(CfgAnalysis, Gfx1250GprIndexedVgprDestinationDisablesExactCalleeSummary) { 0x02010000u, // 0x10: v_writelane_b32 v48, s0, 0. 0xD7610030u, 0x02010201u, // 0x18: v_writelane_b32 v48, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x20: direct call -> callee at 0x40. 0xD7600000u, 0x02010130u, // 0x24: continuation reads the low half. 0xD7600001u, - 0x02010330u, // 0x2c: reads the high half. - 0xBE9E4900u, // 0x34: must not use a stale target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: stale target. + 0x02010330u, // 0x2c: reads the high half. + 0xBE9E4900u, // 0x34: must not use a stale target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: stale target. }; words.insert(words.end(), callee.begin(), callee.end()); - words.push_back(rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250)); + words.push_back(rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5)); TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2598,22 +2597,22 @@ TEST(CfgAnalysis, Gfx1250RelativeSgprDestinationDisablesExactCalleeSummary) { 0x0201012Cu, // 0x20: v_readlane_b32 s20, v44, 0. 0xD7600000u | static_cast(kRestoredPair + 1), 0x0201032Cu, // 0x28: v_readlane_b32 s21, v44, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_CDNA5), // 0x30: direct call -> callee at 0x44. - rocjitsu::build_s_swappc_b64(kReturnSreg, kRestoredPair, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, kRestoredPair, ROCJITSU_CODE_ARCH_CDNA5), // 0x34: must not use a possibly overwritten restored pair. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: padding. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: padding. - relative_write[0], // 0x44: runtime-selected SGPR destination. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: padding. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: padding. + relative_write[0], // 0x44: runtime-selected SGPR destination. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2637,24 +2636,24 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedLaneStashSurvivesDirectCall) { 0x02010000u, // 0x10: v_writelane_b32 v44, s0, 0. 0xD761002Cu, 0x02010201u, // 0x18: v_writelane_b32 v44, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x20: direct call -> callee at 0x40. 0xD7600000u, 0x0201012Cu, // 0x24: continuation reads the surviving low half. 0xD7600001u, - 0x0201032Cu, // 0x2c: reads the high half. - 0xBE9E4900u, // 0x34: recovered s_swap_pc_i64. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: stashed target. - clobber[0], // 0x40: callee clobbers caller-saved v48. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x0201032Cu, // 0x2c: reads the high half. + 0xBE9E4900u, // 0x34: recovered s_swap_pc_i64. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: stashed target. + clobber[0], // 0x40: callee clobbers caller-saved v48. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x44: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2691,26 +2690,26 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryPreservesBankedLaneStash) { 0x02010000u, // 0x14: v_writelane_b32 physical v300, s0, 0. 0xD761002Cu, 0x02010201u, // 0x1c: v_writelane_b32 physical v300, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x24: direct call -> callee at 0x44. 0xD7600000u, 0x0201012Cu, // 0x28: continuation reads physical v300 lane 0. 0xD7600001u, - 0x0201032Cu, // 0x30: reads physical v300 lane 1. - 0xBE9E4900u, // 0x38: recovered from physical v300. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: stale target. - set_all_banks_zero[0], // 0x44: callee selects physical v44, not v300. - clobber_bank_zero[0], // 0x48: same low selector in a different bank. - set_dst_src0_bank_one[0], // 0x4c: restore the caller's bank selectors. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x0201032Cu, // 0x30: reads physical v300 lane 1. + 0xBE9E4900u, // 0x38: recovered from physical v300. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: stale target. + set_all_banks_zero[0], // 0x44: callee selects physical v44, not v300. + clobber_bank_zero[0], // 0x48: same low selector in a different bank. + set_dst_src0_bank_one[0], // 0x4c: restore the caller's bank selectors. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x50: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2737,24 +2736,24 @@ TEST(CfgAnalysis, Gfx1250CalleeModeChangeInvalidatesContinuationBankSelection) { 0x02010000u, // 0x14: stash low half in physical v300. 0xD761002Cu, 0x02010201u, // 0x1c: stash high half in physical v300. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x24: direct call -> callee at 0x44. 0xD7600000u, 0x0201012Cu, // 0x28: MODE now maps this read to physical v44. 0xD7600001u, - 0x0201032Cu, // 0x30: reads physical v44, not the stash. - 0xBE9E4900u, // 0x38: must not recover a stale target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: would-be target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: continuation. - set_all_banks_zero[0], // 0x44: persistent MODE change in callee. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x0201032Cu, // 0x30: reads physical v44, not the stash. + 0xBE9E4900u, // 0x38: must not recover a stale target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: would-be target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: continuation. + set_all_banks_zero[0], // 0x44: persistent MODE change in callee. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: callee return without restoring MODE. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -2800,19 +2799,19 @@ TEST(CfgAnalysis, Gfx1250IndirectCallKillsCarriedLaneStash) { 0xD7600000u, 0x02010130u, // 0x34: continuation reads the pre-call low half. 0xD7600001u, - 0x02010330u, // 0x3c: reads the high half. - stale_call[0], // 0x44: stale indirect call. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x48: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: stale target. - clobber[0], // 0x50: callee clobbers v48. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x02010330u, // 0x3c: reads the high half. + stale_call[0], // 0x44: stale indirect call. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x48: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: stale target. + clobber[0], // 0x50: callee clobbers v48. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x54: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); size_t total_fixups = 0; const IndirectCallFixup *call_fixup = nullptr; @@ -2865,19 +2864,19 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedLaneStashSurvivesIndirectCall) { 0xD7600000u, 0x0201012Cu, // 0x34: continuation reads the surviving low half. 0xD7600001u, - 0x0201032Cu, // 0x3c: reads the high half. - stale_call[0], // 0x44: continuation indirect call. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x48: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x4c: stashed target. - clobber[0], // 0x50: callee clobbers caller-saved v48. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + 0x0201032Cu, // 0x3c: reads the high half. + stale_call[0], // 0x44: continuation indirect call. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x48: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x4c: stashed target. + clobber[0], // 0x50: callee clobbers caller-saved v48. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x54: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *continuation_fixup = nullptr; for (const auto &block : blocks) { @@ -2915,16 +2914,16 @@ TEST(CfgAnalysis, Gfx1250SeedsTextEntryWithLoopBackedgeForLaneStash) { 0xD7600000u, 0x0201012Cu, // 0x28: v_readlane_b32 s0, v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x30: v_readlane_b32 s1, v44, 1. - call[0], // 0x38: cross-block consumer. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: target. + 0x0201032Cu, // 0x30: v_readlane_b32 s1, v44, 1. + call[0], // 0x38: cross-block consumer. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 56); ASSERT_NE(consumer, nullptr); @@ -2950,22 +2949,22 @@ TEST(CfgAnalysis, Gfx1250ExplicitKernelEntryClearsIncomingLaneStash) { 0xD761002Cu, 0x02010201u, // 0x18: v_writelane_b32 v44, s1, 1. branch[0], // 0x20: -> independently launchable entry B at 0x28. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x24: skipped. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x24: skipped. 0xD7600000u, 0x0201012Cu, // 0x28: entry B reads v44 lane 0. 0xD7600001u, - 0x0201032Cu, // 0x30: reads v44 lane 1. - call[0], // 0x38: must remain dynamic. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x40: padding. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x44: A's target. + 0x0201032Cu, // 0x30: reads v44 lane 1. + call[0], // 0x38: must remain dynamic. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x40: padding. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x44: A's target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); constexpr std::array extra_leaders{40}; - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250, extra_leaders); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5, extra_leaders); size_t total_fixups = 0; for (const auto &block : blocks) @@ -2994,15 +2993,15 @@ TEST(CfgAnalysis, Gfx1250A0UsesLowByteOfVgprMsb) { 0xD7600000u, 0x0201012Cu, // 0x28: v_readlane_b32 s0, physical v44, 0. 0xD7600001u, - 0x0201032Cu, // 0x30: v_readlane_b32 s1, physical v44, 1. - 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: target/continuation. + 0x0201032Cu, // 0x30: v_readlane_b32 s1, physical v44, 1. + 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: target/continuation. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 56); ASSERT_NE(consumer, nullptr); @@ -3034,15 +3033,15 @@ TEST(CfgAnalysis, Gfx1250ImmediateModeWriteKeepsLaneStashBankKnown) { 0xD7600000u, 0x0201012Cu, // 0x2c: v_readlane_b32 s0, physical v300, 0. 0xD7600001u, - 0x0201032Cu, // 0x34: v_readlane_b32 s1, physical v300, 1. - 0xBE9E4900u, // 0x3c: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: target/continuation. + 0x0201032Cu, // 0x34: v_readlane_b32 s1, physical v300, 1. + 0xBE9E4900u, // 0x3c: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: target/continuation. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 60); ASSERT_NE(consumer, nullptr); @@ -3064,17 +3063,17 @@ TEST(CfgAnalysis, Gfx1250LaneRestoreReachesConsumerAcrossBranch) { 0xD7600014u, 0x0201012Cu, // 0x20: v_readlane_b32 s20, v44, 0. 0xD7600015u, - 0x0201032Cu, // 0x28: v_readlane_b32 s21, v44, 1. - branch[0], // 0x30: split the restore and consumer blocks. - 0xBE9E4914u, // 0x34: s_swap_pc_i64 s[30:31], s[20:21]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: target. + 0x0201032Cu, // 0x28: v_readlane_b32 s21, v44, 1. + branch[0], // 0x30: split the restore and consumer blocks. + 0xBE9E4914u, // 0x34: s_swap_pc_i64 s[30:31], s[20:21]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 52); ASSERT_NE(consumer, nullptr); @@ -3096,16 +3095,16 @@ TEST(CfgAnalysis, Gfx1250PcPairCopyReachesConsumer) { add[0], 24u, 0u, // 0x04: s_add_nc_u64 ..., lit64(24) -> target 0x1c. copy[0], // 0x10: s_mov_b64 s[54:55], s[20:21]. - rocjitsu::build_s_swappc_b64(kReturnSreg, kCopiedSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, kCopiedSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x14: call through the copied pair. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x18: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x1c: target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x18: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x1c: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *copied_call = nullptr; for (const auto &block : blocks) { @@ -3127,21 +3126,21 @@ TEST(CfgAnalysis, Gfx1250DirectCallOverwritesPcBuilderInReturnPair) { getpc[0], // 0x00: s_get_pc_i64 s[30:31]. add[0], 32u, 0u, // 0x04: s_add_nc_u64 ..., lit64(32) -> stale target 0x24. - rocjitsu::build_s_call_b64(kReturnSreg, 2, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 2, ROCJITSU_CODE_ARCH_CDNA5), // 0x10: direct call overwrites s[30:31] and enters 0x1c. - rocjitsu::build_s_swappc_b64(40, kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(40, kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x14: s[30:31] contains the return PC, not the old builder. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x18: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x1c: callee body. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x18: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x1c: callee body. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x20: callee return. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x24: stale target. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x24: stale target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -3159,19 +3158,19 @@ TEST(CfgAnalysis, Gfx1250SwapPcOverwritesPcBuilderInReturnPair) { getpc[0], // 0x00: s_get_pc_i64 s[0:1]. add[0], 24u, 0u, // 0x04: s_add_nc_u64 ..., lit64(24) -> callee at 0x1c. - rocjitsu::build_s_swappc_b64(kTargetSreg, kTargetSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kTargetSreg, kTargetSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x10: call through s[0:1], then overwrite it with return PC 0x14. - rocjitsu::build_s_swappc_b64(30, kTargetSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(30, kTargetSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x14: must not reuse the pre-call target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x18: continuation. - rocjitsu::build_s_setpc_b64(kTargetSreg, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x18: continuation. + rocjitsu::build_s_setpc_b64(kTargetSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x1c: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *first_call = nullptr; for (const auto &block : blocks) { @@ -3209,31 +3208,31 @@ TEST(CfgAnalysis, Gfx1250CalleeSummaryRejectsRepurposedReturnPair) { 0x02010000u, // 0x14: v_writelane_b32 v192, s0, 0. 0xD76100C0u, 0x02010201u, // 0x1c: v_writelane_b32 v192, s1, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 7, ROCJITSU_CODE_ARCH_CDNA5), // 0x24: direct call -> thunk at 0x44. 0xD7600000u, 0x020101C0u, // 0x28: restore the low half after the call. 0xD7600001u, 0x020103C0u, // 0x30: restore the high half after the call. - rocjitsu::build_s_swappc_b64(kReturnSreg, kTargetSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, kTargetSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x38: must not recover the stash clobbered by the tail target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: stashed target. - save_return[0], // 0x44: save caller return in s[32:33]. - get_tail_target[0], // 0x48: rebuild s[30:31]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: stashed target. + save_return[0], // 0x44: save caller return in s[32:33]. + get_tail_target[0], // 0x48: rebuild s[30:31]. add_tail_target[0], 16u, 0u, // 0x4c: s_add_nc_u64 ..., lit64(16) -> tail target 0x5c. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x58: tail transfer through the repurposed pair. clobber_stash[0], // 0x5c: tail target clobbers v192. - rocjitsu::build_s_setpc_b64(kSavedReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kSavedReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x60: return through the saved pair. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); for (const auto &block : blocks) { EXPECT_TRUE(std::ranges::none_of( @@ -3258,22 +3257,22 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryPreservesUnwrittenRestoredSgprs) { 0x0201012Cu, // 0x20: v_readlane_b32 restored_pair, v44, 0. 0xD7600000u | static_cast(restored_pair + 1), 0x0201032Cu, // 0x28: v_readlane_b32 restored_pair+1, v44, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_CDNA5), // 0x30: direct call -> callee at 0x44. - rocjitsu::build_s_swappc_b64(kReturnSreg, restored_pair, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, restored_pair, ROCJITSU_CODE_ARCH_CDNA5), // 0x34: restored target consumer after the call returns. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: padding. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: stashed target. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x44: callee body. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: padding. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: stashed target. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x44: callee body. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *fixup = nullptr; for (const auto &block : blocks) { @@ -3322,13 +3321,13 @@ TEST(CfgAnalysis, Gfx1250CalleeSummaryVariantLimitFallsBackConservatively) { words.push_back(0x02010300u | kStashVgpr); // v_readlane_b32 s1, v48, 1. const uint64_t consumer_offset = words.size() * sizeof(uint32_t); words.push_back( - rocjitsu::build_s_swappc_b64(kReturnSreg, kTargetSreg, ROCJITSU_CODE_ARCH_GFX1250)); - words.push_back(build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_swappc_b64(kReturnSreg, kTargetSreg, ROCJITSU_CODE_ARCH_CDNA5)); + words.push_back(build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5)); const uint64_t stashed_target_offset = words.size() * sizeof(uint32_t); - words.push_back(build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250)); + words.push_back(build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5)); const uint64_t callee_offset = words.size() * sizeof(uint32_t); - words.push_back(build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250)); - words.push_back(rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250)); + words.push_back(build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5)); + words.push_back(rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5)); // S_GET_PC_I64 at byte offset 4 materializes byte offset 8. Its following // literal add therefore needs target-8. Each S_CALL immediate is measured in @@ -3339,13 +3338,13 @@ TEST(CfgAnalysis, Gfx1250CalleeSummaryVariantLimitFallsBackConservatively) { static_cast((call_index + 1) * sizeof(uint32_t)); EXPECT_EQ(delta % static_cast(sizeof(uint32_t)), 0); words[call_index] = rocjitsu::build_s_call_b64( - kReturnSreg, static_cast(delta / sizeof(uint32_t)), ROCJITSU_CODE_ARCH_GFX1250); + kReturnSreg, static_cast(delta / sizeof(uint32_t)), ROCJITSU_CODE_ARCH_CDNA5); } TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); EXPECT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); return std::ranges::any_of(blocks, [&](const auto &block) { return std::ranges::any_of(block->static_indirect_call_fixups(), @@ -3375,22 +3374,22 @@ TEST(CfgAnalysis, Gfx1250ExactCalleeSummaryDropsWrittenRestoredSgprs) { 0x0201012Cu, // 0x20: v_readlane_b32 restored_pair, v44, 0. 0xD7600000u | static_cast(restored_pair + 1), 0x0201032Cu, // 0x28: v_readlane_b32 restored_pair+1, v44, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_CDNA5), // 0x30: direct call -> callee at 0x44. - rocjitsu::build_s_swappc_b64(kReturnSreg, restored_pair, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, restored_pair, ROCJITSU_CODE_ARCH_CDNA5), // 0x34: restored target consumer after the call returns. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: padding. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x40: padding. - 0xBE800080u, // 0x44: callee writes caller-saved s0. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: padding. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x40: padding. + 0xBE800080u, // 0x44: callee writes caller-saved s0. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *fixup = nullptr; for (const auto &block : blocks) { @@ -3424,23 +3423,23 @@ TEST(CfgAnalysis, Gfx1250UnsupportedCalleeSummaryFallsBackToCallPreservedSgprs) 0x0201012Cu, // 0x20: v_readlane_b32 restored_pair, v44, 0. 0xD7600000u | static_cast(restored_pair + 1), 0x0201032Cu, // 0x28: v_readlane_b32 restored_pair+1, v44, 1. - rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 4, ROCJITSU_CODE_ARCH_CDNA5), // 0x30: direct call -> callee at 0x44. - rocjitsu::build_s_swappc_b64(kReturnSreg, restored_pair, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, restored_pair, ROCJITSU_CODE_ARCH_CDNA5), // 0x34: restored target consumer after the call returns. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: padding. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x40: padding. - rocjitsu::build_s_swappc_b64(kReturnSreg, 2, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: padding. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x40: padding. + rocjitsu::build_s_swappc_b64(kReturnSreg, 2, ROCJITSU_CODE_ARCH_CDNA5), // 0x44: unresolved nested call prevents an exact summary. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x48: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *fixup = nullptr; for (const auto &block : blocks) { @@ -3490,16 +3489,16 @@ TEST(CfgAnalysis, Gfx1250RestashedLaneTargetRemainsRecoverable) { 0xD7600000u, 0x02010130u, // 0x40: v_readlane_b32 s0, v48, 0. 0xD7600001u, - 0x02010330u, // 0x48: v_readlane_b32 s1, v48, 1. - 0xBE9E4900u, // 0x50: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x54: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x58: target. + 0x02010330u, // 0x48: v_readlane_b32 s1, v48, 1. + 0xBE9E4900u, // 0x50: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x54: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x58: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 80); ASSERT_NE(consumer, nullptr); @@ -3517,7 +3516,7 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedPcBuilderCanBeStashedAfterCall) { getpc[0], // 0x00: s_get_pc_i64 s[14:15]. add[0], 56u, 0u, // 0x04: s_add_nc_u64 ..., lit64(56) -> callee at 0x3c. - rocjitsu::build_s_swappc_b64(kReturnSreg, kTargetSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, kTargetSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x10: first call through s[14:15]. 0xD7610030u, 0x0201000Eu, // 0x14: v_writelane_b32 v48, s14, 0. @@ -3527,18 +3526,18 @@ TEST(CfgAnalysis, Gfx1250CalleeSavedPcBuilderCanBeStashedAfterCall) { 0x02010130u, // 0x24: v_readlane_b32 s0, v48, 0. 0xD7600001u, 0x02010330u, // 0x2c: v_readlane_b32 s1, v48, 1. - rocjitsu::build_s_swappc_b64(kReturnSreg, 0, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_swappc_b64(kReturnSreg, 0, ROCJITSU_CODE_ARCH_CDNA5), // 0x34: second call through the re-stashed target. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: callee body. - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: callee body. + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // 0x40: callee return. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); const IndirectCallFixup *second_call = nullptr; for (const auto &block : blocks) { @@ -3577,16 +3576,16 @@ TEST(CfgAnalysis, Gfx1250DoesNotRecoverLaneStashWithDifferingRoleBanks) { 0xD7600000u, 0x0201012Cu, // 0x24: v_readlane_b32 s0, v44, 0 (physical v44 under SRC0 bank 0). 0xD7600001u, - 0x0201032Cu, // 0x2c: v_readlane_b32 s1, v44, 1. - 0xBE9E4900u, // 0x34: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x38: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: would-be target. + 0x0201032Cu, // 0x2c: v_readlane_b32 s1, v44, 1. + 0xBE9E4900u, // 0x34: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x38: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: would-be target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); size_t total_fixups = 0; for (const auto &block : blocks) @@ -3619,15 +3618,15 @@ TEST(CfgAnalysis, Gfx1250InheritsBankAlongProvenCfgEdge) { 0x0201012Cu, 0xD7600001u, // 0x30: v_readlane_b32 s1, v44, 1. 0x0201032Cu, - 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: continuation. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x40: target. + 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: continuation. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x40: target. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto *consumer = block_starting_at(blocks, 56); ASSERT_NE(consumer, nullptr); @@ -3670,12 +3669,12 @@ TEST(CfgAnalysis, Gfx1250DoesNotReuseStashFromSkippedFallthroughPredecessor) { 0x0201012Cu, 0xD7600001u, // 0x30: v_readlane_b32 s1, v44, 1. 0x0201032Cu, - 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. - build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), // 0x3c: would-be target / continuation. + 0xBE9E4900u, // 0x38: s_swap_pc_i64 s[30:31], s[0:1]. + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), // 0x3c: would-be target / continuation. }; TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); // Assert on the recovery pass output directly: the must-reaching-definition @@ -3706,7 +3705,7 @@ TEST(CfgAnalysis, Gfx1250DoesNotReuseStashFromSkippedFallthroughPredecessor) { const auto fixups = discover_indirect_branch_edges( std::span(decoded_insts.data(), decoded_insts.size()), text, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); EXPECT_TRUE(fixups.empty()) << "must-dataflow must not reuse a skipped-path stash"; } @@ -3722,7 +3721,7 @@ TEST(CfgAnalysis, Gfx1250DoesNotReuseStashFromSkippedFallthroughPredecessor) { void run_indirect_discovery_for_test(std::vector words, std::vector *builders) { TestCodeObject co(std::move(words)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto *sec = co.text_sections().front(); @@ -3751,13 +3750,13 @@ void run_indirect_discovery_for_test(std::vector words, (void)discover_indirect_branch_edges( std::span(decoded_insts.data(), decoded_insts.size()), text, - ROCJITSU_CODE_ARCH_GFX1250, {}, ExternalEntryPolicy::InferPredecessorless, builders); + ROCJITSU_CODE_ARCH_CDNA5, {}, ExternalEntryPolicy::InferPredecessorless, builders); } TEST(IndirectBranchDiscovery, ReusedPairPublishesTheCompletedBuilderItReplaces) { constexpr uint16_t kPair = 0; constexpr uint16_t kLiteral = 255; - constexpr rj_code_arch_t kArch = ROCJITSU_CODE_ARCH_GFX1250; + constexpr rj_code_arch_t kArch = ROCJITSU_CODE_ARCH_CDNA5; std::vector words = { build_s_getpc_b64(kPair, kArch), build_s_add_u32(kPair, kPair, kLiteral, kArch), @@ -3788,7 +3787,7 @@ TEST(IndirectBranchDiscovery, ReusedPairPublishesTheCompletedBuilderItReplaces) TEST(IndirectBranchDiscovery, ReusedPairPoisonsAnAbandonedHalfBuiltBuilder) { constexpr uint16_t kPair = 0; constexpr uint16_t kLiteral = 255; - constexpr rj_code_arch_t kArch = ROCJITSU_CODE_ARCH_GFX1250; + constexpr rj_code_arch_t kArch = ROCJITSU_CODE_ARCH_CDNA5; std::vector words = { build_s_getpc_b64(kPair, kArch), build_s_add_u32(kPair, kPair, kLiteral, kArch), // low half only -- no s_addc_u32 @@ -3898,14 +3897,14 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbResolvesPhysicalRegisterBank) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_vgpr_msb[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -3935,14 +3934,14 @@ TEST(LivenessAnalysis, Gfx1250ImplicitVgprUseResolvesDestinationBank) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB16Vop1, {.src0 = 128, .vdst = 1}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_dst_bank_two[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -3967,14 +3966,14 @@ TEST(LivenessAnalysis, Gfx1250D16LoadImplicitUseResolvesDestinationBank) { constexpr auto load = cdna5::build_vflat(cdna5::kFlatLoadD16U8Vflat, {.vdst = 1}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_dst_bank_two[0], load[0], load[1], load[2], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); LivenessAnalysis liveness(KernelBlockScope(scope), nullptr, options); @@ -4000,14 +3999,14 @@ TEST(LivenessAnalysis, Gfx1250ImplicitVgprUseResolvesDespiteExplicitBank0Alias) constexpr auto move = cdna5::build_vop1(cdna5::kVMovB16Vop1, {.src0 = 256 + 1, .vdst = 1}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_dst_bank_two[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4033,14 +4032,14 @@ TEST(LivenessAnalysis, Gfx1250SwapImplicitReadsResolvePerRole) { constexpr auto swap = cdna5::build_vop1(cdna5::kVSwapB16Vop1, {.src0 = 256 + 2, .vdst = 1}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_banks[0], swap[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4086,14 +4085,14 @@ TEST(LivenessAnalysis, Gfx1250DppPreserveReadResolvesToDstBank) { constexpr uint32_t kDppWord1Partial = (0x7u << 28) | (0xFu << 24) | 2u; constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_banks[0], kDppMovWord0, kDppWord1Partial, end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4120,14 +4119,14 @@ TEST(LivenessAnalysis, Gfx1250ImplicitVgprUseUnknownBankReadsEveryCandidate) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB16Vop1, {.src0 = 128, .vdst = 1}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({setreg[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4154,14 +4153,14 @@ TEST(LivenessAnalysis, Gfx1250UnknownBankDefMakesEveryCandidateGloballyUsed) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 128, .vdst = 1}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({setreg[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4193,14 +4192,14 @@ TEST(LivenessAnalysis, Gfx1250RelativeVgprAccessDisablesGlobalUnusedQuery) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovrelsB32Vop1, {.src0 = 256, .vdst = 2}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4216,14 +4215,14 @@ TEST(LivenessAnalysis, Gfx1250SwaprelDisablesGlobalUnusedQuery) { constexpr auto swap = cdna5::build_vop1(cdna5::kVSwaprelB32Vop1, {.src0 = 256, .vdst = 2}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({swap[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4244,14 +4243,14 @@ TEST(LivenessAnalysis, Gfx1250GprIndexModeWriteDisablesGlobalUnusedQuery) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 256, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({setreg[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4275,14 +4274,14 @@ TEST(LivenessAnalysis, Gfx1250ImmediateGprIndexModeWriteUsesLiteralValue) { for (uint32_t literal : {0u, 1u}) { SCOPED_TRACE(literal); TestCodeObject co({setreg[0], literal, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4370,14 +4369,14 @@ TEST(LivenessAnalysis, Gfx1250DynamicModeWriteConservativelyUsesEveryBank) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({setreg[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4405,14 +4404,14 @@ TEST(LivenessAnalysis, Gfx1250FullLiteralModeWriteRecoversKnownBank) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({dynamic_setreg[0], literal_setreg[0], 2u, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4445,14 +4444,14 @@ TEST(LivenessAnalysis, Gfx1250TruncatedLiteralModeWriteMarksBanksAmbiguous) { // told the text ends right after the setreg encoding word at offset 4 (its // literal at offset 8 is out of range). TestCodeObject co({set_bank_two[0], literal_setreg[0], 0xe4u, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); // Truncate the text span to 8 bytes: the setreg (at offset 4) has no readable // literal at offset 8. @@ -4479,14 +4478,14 @@ TEST(LivenessAnalysis, Gfx1250PartialLiteralModeWritePreservesUntouchedBankBit) constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_bank_one[0], literal_setreg[0], 1u, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4510,14 +4509,14 @@ TEST(LivenessAnalysis, Gfx1250ImmediateModeWritePreservesBanksOutsideRequestedSl constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({set_bank_one[0], literal_setreg[0], 0u, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4539,14 +4538,14 @@ TEST(LivenessAnalysis, Gfx1250LiteralModeWriteTracksEveryRole) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({literal_setreg[0], kModeFields, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4569,14 +4568,14 @@ TEST(LivenessAnalysis, Gfx1250ImmediateNonModeWriteDoesNotChangeBanks) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({literal_setreg[0], 0x000ff000u, move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(blocks.size(), 1u); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4601,15 +4600,15 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbCfgJoinRequiresPredecessorsToAgree) { constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co( {branch_to_else[0], set_bank_two[0], branch_to_join[0], set_bank_zero[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto scope = block_scope(blocks); BasicBlock *join = block_starting_at(blocks, 16); ASSERT_NE(join, nullptr); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4631,15 +4630,15 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbCfgJoinPreservesAgreeingBank) { constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co( {branch_to_else[0], set_bank_two[0], branch_to_join[0], set_bank_two[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto scope = block_scope(blocks); BasicBlock *join = block_starting_at(blocks, 16); ASSERT_NE(join, nullptr); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -4672,13 +4671,13 @@ TEST(LivenessAnalysis, Gfx1250VgprMsbJoinExcludesUnreachablePredecessor) { constexpr auto move = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 257, .vdst = 0}); constexpr auto end = cdna5::build_sopp(cdna5::kSEndpgmSopp); TestCodeObject co({branch_over[0], set_bank_zero[0], set_bank_two[0], move[0], end[0]}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_GFX1250); + auto blocks = build_valid_blocks(co, *decoder, ROCJITSU_CODE_ARCH_CDNA5); auto scope = block_scope(blocks); LivenessAnalysisOptions options; - options.arch = ROCJITSU_CODE_ARCH_GFX1250; + options.arch = ROCJITSU_CODE_ARCH_CDNA5; options.entry_block = scope.front(); options.text = text_span(co); const ExecMaskAnalysis exec(KernelBlockScope(scope), /*wave_size=*/64); @@ -5435,7 +5434,7 @@ std::unique_ptr decode_cdna4(const std::array &words) } std::unique_ptr decode_gfx1250(const std::array &words) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); return std::unique_ptr(decoder ? decode_valid(*decoder, words.data()) : nullptr); } @@ -5786,7 +5785,7 @@ TEST(GeneratedInstDefUse, D16HiLoadReadsDestination) { } TEST(GeneratedInstDefUse, WritelaneReadsDestinationGfx1250) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::array words{0xD7610005U, 0x00000404U, 0U, 0U}; std::unique_ptr inst(decode_valid(*decoder, words.data())); diff --git a/emulation/rocjitsu/tests/cdna5_architecture_test.cpp b/emulation/rocjitsu/tests/cdna5_architecture_test.cpp index 3548d429b559..fac6cb0ea62f 100644 --- a/emulation/rocjitsu/tests/cdna5_architecture_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_architecture_test.cpp @@ -76,9 +76,9 @@ TEST(Gfx1250ConfigTest, ConfigLoadsTopology) { auto loaded = config::load_config(kGfx1250ConfigPath, rocjitsu::kEmbeddedSchema); auto *soc = loaded.soc(); ASSERT_NE(soc, nullptr); - EXPECT_EQ(soc->arch(), ROCJITSU_CODE_ARCH_GFX1250); - EXPECT_EQ(config::parse_arch("gfx1250"), ROCJITSU_CODE_ARCH_GFX1250); - EXPECT_STREQ(config::arch_to_string(ROCJITSU_CODE_ARCH_GFX1250), "gfx1250"); + EXPECT_EQ(soc->arch(), ROCJITSU_CODE_ARCH_CDNA5); + EXPECT_EQ(config::parse_arch("cdna5"), ROCJITSU_CODE_ARCH_CDNA5); + EXPECT_STREQ(config::arch_to_string(ROCJITSU_CODE_ARCH_CDNA5), "cdna5"); EXPECT_TRUE(loaded.device.present); EXPECT_EQ(loaded.device.gfx_target_version, 120500u); @@ -132,7 +132,7 @@ TEST(Gfx1250CodeObjectTest, MachineFlagMapsToTarget) { EXPECT_EQ(co.target_id(), ROCJITSU_CODE_TARGET_GFX1250); ASSERT_EQ(co.text_sections().size(), 1u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto *text = co.text_sections()[0]; auto *words = reinterpret_cast(text->data()); @@ -148,7 +148,7 @@ TEST(Gfx1250DecodeTest, SMovB64Literal64ConsumesThreeDwords) { 0xFFFFFFFFu, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -165,7 +165,7 @@ TEST(Gfx1250DecodeTest, ScalarSourceRejectsReservedSelector) { 0x8C9000E2u, // s_or_b64 s[16:17], reserved selector 226, s0 }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -177,7 +177,7 @@ TEST(Gfx1250DecodeTest, Vop3LiteralConsumesThreeDwords) { 0x000000F8u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -191,7 +191,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsLiteral64Selector) { 0x000000FEu, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -199,7 +199,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsLiteral64Selector) { TEST(Gfx1250DecodeTest, Vop1RejectsUnsupportedLiteral32WithoutExtensionWord) { const auto words = cdna5::build_vop1(cdna5::kVReadfirstlaneB32Vop1, {.src0 = 255}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words.data())); } @@ -207,7 +207,7 @@ TEST(Gfx1250DecodeTest, Vop1RejectsUnsupportedLiteral32WithoutExtensionWord) { TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral32WithoutExtensionWord) { const auto words = cdna5::build_vop2(cdna5::kVFmamkF64Vop2, {.src0 = 255}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words.data())); } @@ -215,7 +215,7 @@ TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral32WithoutExtensionWord) { TEST(Gfx1250DecodeTest, Vop2RejectsUnsupportedLiteral64WithoutExtensionWords) { const auto words = cdna5::build_vop2(cdna5::kVFmamkF32Vop2, {.src0 = 254}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words.data())); } @@ -227,7 +227,7 @@ TEST(Gfx1250DecodeTest, SaluRejectsMixedLiteralWidths) { 0x00000000u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -237,7 +237,7 @@ TEST(Gfx1250DecodeTest, SendmsgRtnSelectorsAreNotLiterals) { 0xBE804CFFu, // s_sendmsg_rtn_b32 s0, 255 }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -252,7 +252,7 @@ TEST(Gfx1250DecodeTest, VopdRejectsLiteral64Selector) { 0xFFFFFCFEu, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -264,7 +264,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsDppWithLiteral) { 0x00001500u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -276,7 +276,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsInvalidScalarDestination) { 0x00000000u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -287,7 +287,7 @@ TEST(Gfx1250DecodeTest, Vop3RejectsInvalidVgprSource) { 0x0000F8D7u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -302,7 +302,7 @@ TEST(Gfx1250DecodeTest, Vop3ReadlaneValidatesLaneSelector) { 0x0003D7D7u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr valid(decode_valid(*decoder, valid_words)); ASSERT_NE(valid, nullptr); @@ -320,7 +320,7 @@ TEST(Gfx1250DecodeTest, Vop3CmpxValidatesExecDestination) { 0x00020300u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr valid(decode_valid(*decoder, valid_words)); ASSERT_NE(valid, nullptr); @@ -335,7 +335,7 @@ TEST(Gfx1250DecodeTest, Vop3SdstLiteralConsumesThreeDwords) { 0x00000060u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -350,7 +350,7 @@ TEST(Gfx1250DecodeTest, VFmamkF64ImpliedLiteralConsumesThreeDwords) { 0x7E042B02u, // v_cvt_u32_f64_e32 v2, v[2:3] }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr fmamk(decode_valid(*decoder, words)); ASSERT_NE(fmamk, nullptr); @@ -367,7 +367,7 @@ TEST(Gfx1250DecodeTest, SWaitXcntHasWaitcntMetadata) { 0xBFC50000u, // s_wait_xcnt 0 }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -383,7 +383,7 @@ TEST(Gfx1250DecodeTest, BufferOffenUsesSingleVaddrRegister) { 0x00000007u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -424,7 +424,7 @@ TEST(Gfx1250DecodeTest, BufferWithoutIdxenOffenDoesNotExposeVaddrRegister) { 0x00000007u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -453,7 +453,7 @@ TEST(Gfx1250DecodeTest, WmmaF8f6f4UsesMatrixFormatOperandWidths) { 0x04421100u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -469,7 +469,7 @@ TEST(Gfx1250DecodeTest, WmmaScaleF8f6f4ConsumesVop3px2Pair) { 0x02026912u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -490,7 +490,7 @@ TEST(Gfx1250DecodeTest, WmmaScalePairRejectsInvalidEmbeddedSourceSelectors) { 0xD600D400u | embedded_src0, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -504,7 +504,7 @@ TEST(Gfx1250DecodeTest, WmmaScale16F8f6f4ConsumesVop3px2Pair) { 0x02021502u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -523,7 +523,7 @@ TEST(Gfx1250DecodeTest, WmmaScaleF4_32x16x128ConsumesVop3px2Pair) { 0x1A024110u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -541,7 +541,7 @@ TEST(Gfx1250DecodeTest, WmmaScalePrefixRejectsNonWmmaSuffix) { 0x02026912u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -576,7 +576,7 @@ TEST(Gfx1250ExecutionTest, WmmaRegularScaleInlineZeroMatchesNeutralScalarSources for (uint32_t lane = 0; lane < wf->wf_size(); ++lane) cu->write_vgpr(vgpr_base + reg, lane, 0x38383838u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr scalar_inst(decode_valid(*decoder, scalar_words.data())); std::unique_ptr inline_inst(decode_valid(*decoder, inline_words.data())); @@ -596,7 +596,7 @@ TEST(Gfx1250ExecutionTest, WmmaRegularScaleInlineZeroMatchesNeutralScalarSources } TEST(Gfx1250DecodeTest, SwmmacPrintsIndexKeyAndReuseModifiers) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const uint32_t index_key_words[] = { @@ -633,7 +633,7 @@ TEST(Gfx1250DecodeTest, VopdXyConsumesTwoDwords) { 0x02000080u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -650,7 +650,7 @@ TEST(Gfx1250DecodeTest, Vopd3ConsumesThreeDwords) { 0x0A000001u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -667,7 +667,7 @@ TEST(Gfx1250DecodeTest, Vopd3RejectsSrcX0Literal32Selector) { 0x0A000001u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -679,7 +679,7 @@ TEST(Gfx1250DecodeTest, Vopd3RejectsSrcY0Literal32Selector) { 0x0A000001u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decode_fails(*decoder, words)); } @@ -691,7 +691,7 @@ TEST(Gfx1250DecodeTest, VopdLiteralConsumesThreeDwords) { 0x4F7FFFFEu, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -707,7 +707,7 @@ TEST(Gfx1250DecodeTest, VopdSourceOperandsFollowPrintedSlots) { 0x09000011u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -727,7 +727,7 @@ TEST(Gfx1250DecodeTest, VopdRejectsInvalidOpcodes) { {0xCF000000u | (3u << 18) | (32u << 12), 0, 0}, }}; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (const auto &encoding : words) EXPECT_TRUE(decode_fails(*decoder, encoding.data())); @@ -740,7 +740,7 @@ TEST(Gfx1250DecodeTest, PublicDecoderReportsInvalidVopdEncoding) { }; rj_code_decoder_t *decoder = nullptr; - ASSERT_EQ(rj_code_decoder_create(ROCJITSU_CODE_ARCH_GFX1250, &decoder), ROCJITSU_STATUS_SUCCESS); + ASSERT_EQ(rj_code_decoder_create(ROCJITSU_CODE_ARCH_CDNA5, &decoder), ROCJITSU_STATUS_SUCCESS); ASSERT_NE(decoder, nullptr); auto *inst = reinterpret_cast(static_cast(1)); @@ -757,7 +757,7 @@ TEST(Gfx1250DecodeTest, Vopd3RejectsOverlappingDestinations) { {.op = VopdOp::MulF32, .src0 = 0, .src1 = 1, .src2 = 2, .dst = 11}), }}; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (const auto &encoding : words) EXPECT_TRUE(decode_fails(*decoder, encoding.data())); diff --git a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp index 5ec5f1954f2f..2fdb186e9a2f 100644 --- a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp @@ -44,7 +44,7 @@ std::string make_single_se_gfx1250_config(uint32_t num_cus) { std::to_string(i) + R"(","latency":1,"weight":10})"; } - return R"({"max_ticks":10000,"num_threads":1,"vm":{"arch":"gfx1250"},)" + return R"({"max_ticks":10000,"num_threads":1,"vm":{"arch":"cdna5"},)" R"("topology":{"root":{"name":"soc","type":"soc","children":[)" R"({"name":"vram","type":"gpu_memory"},)" R"({"name":"xcd0","type":"xcd","children":[)" diff --git a/emulation/rocjitsu/tests/cdna5_execution_test.cpp b/emulation/rocjitsu/tests/cdna5_execution_test.cpp index bf163213a2ec..a01e2ac36194 100644 --- a/emulation/rocjitsu/tests/cdna5_execution_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_execution_test.cpp @@ -19,7 +19,7 @@ class ForceScalarGuard { }; TEST(Gfx1250ExecutionTest, TargetProvidesImmutableExecutionBackend) { - const IsaTargetDescriptor *target = default_isa_target_registry().find("gfx1250"); + const IsaTargetDescriptor *target = default_isa_target_registry().find("cdna5"); ASSERT_NE(target, nullptr); EXPECT_TRUE(target->supports_execution); EXPECT_TRUE(cdna5::Operand::full_execution_backend_complete()); @@ -39,7 +39,7 @@ TEST(Gfx1250ExecutionTest, ScalarMovesTreatS102AndS103AsOrdinarySgprs) { write_wave_sgpr(*cu, *wf, 93, 0xeeff0011u); write_wave_sgpr(*cu, *wf, 102, 0); write_wave_sgpr(*cu, *wf, 103, 0); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); constexpr std::array kMove64 = { @@ -128,7 +128,7 @@ TEST(Gfx1250ExecutionTest, Wave32VectorComparePreservesVccHiScratch) { cu->write_vgpr(vgpr_base + 18, 0, 6u); cu->write_vgpr(vgpr_base + 18, 1, 8u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); constexpr auto kCompare = cdna5::build_vopc(cdna5::kVCmpGtI32Vopc, {.src0 = 28, .vsrc1 = 18}); std::unique_ptr decoded(decode_valid(*decoder, kCompare.data())); @@ -274,7 +274,7 @@ TEST(Gfx1250ExecutionTest, IreeF16ReductionTailKeepsLane31Sum) { ASSERT_EQ(wf->wf_size(), 32u); wf->set_exec(0xffffffffu); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const uint32_t vgpr_base = wf->vgpr_alloc().base; @@ -396,7 +396,7 @@ TEST(Gfx1250LiteralOperandTest, SplitBackendPreservesSignedAndEncodingSemantics) ASSERT_NE(wf, nullptr); wf->set_exec(1u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); ASSERT_TRUE(cdna5::Operand::full_execution_backend_complete()); amdgpu::RegisterAccess regs(*wf); @@ -503,7 +503,7 @@ TEST(Gfx1250LiteralOperandTest, NegativeI64CompareCoversScalarAndAvailableSimdPa cu->write_vgpr(vgpr_base + 1, lane, 0u); } - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto compare_base = cdna5::build_vop3(cdna5::kVCmpLtI64Vop3, {.vdst = 0, .src0 = 255, .src1 = 256}); @@ -537,7 +537,7 @@ TEST(Gfx1250LiteralOperandTest, ScalarMaskOperandsRejectLiteralMarkers) { const char *name; std::array encoding; }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (const uint16_t marker : {uint16_t{254}, uint16_t{255}}) { const std::array test_cases{ @@ -577,7 +577,7 @@ TEST(Gfx1250LiteralOperandTest, PkF32LiteralReplicatesAndUsesAvailableSimdPath) {.vdst = 0, .src0 = 255, .src1 = 128, .opsel_hi = 3}); const std::array add_words{add_base[0], add_base[1], literal}; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr add(decode_valid(*decoder, add_words.data())); ASSERT_NE(add, nullptr); @@ -666,7 +666,7 @@ TEST(Gfx1250LiteralOperandTest, PkF32MixedLiteralVgprSourcesUseAvailableSimdPath if (test_case.operation == Operation::Fma) base[0] |= uint32_t{1} << 14; // pad_14 is the src2 high-half selector. const std::array words{base[0], base[1], kLiteral}; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); @@ -724,7 +724,7 @@ TEST(Gfx1250LiteralOperandTest, PkF32MixedLiteralSourceSpecificSelectorFallsBack const auto base = cdna5::build_vop3p(cdna5::kVPkAddF32Vop3p, {.vdst = 4, .src0 = 255, .src1 = 258, .opsel_hi = 2}); const std::array words{base[0], base[1], kLiteral}; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); @@ -772,7 +772,7 @@ TEST(Gfx1250ExecutionTest, PkF32AddMulSimdMatchesScalarWithPartialExec) { const auto words = cdna5::build_vop3p( test_case.opcode, {.vdst = 4, .neg_hi = 2, .src0 = 256, .src1 = 258, .opsel_hi = 3, .neg = 1}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); @@ -881,7 +881,7 @@ TEST(Gfx1250ExecutionTest, PkF32EveryNondefaultSelectorGateFallsBackToScalar) { test_case.ternary ? cdna5::kVPkFmaF32Vop3p : cdna5::kVPkAddF32Vop3p, fields); if (test_case.op_sel_hi_2 != 0u) words[0] |= uint32_t{1} << 14; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); @@ -952,7 +952,7 @@ TEST(Gfx1250ExecutionTest, PkFmaF32SimdMatchesScalarWithPartialExec) { cdna5::kVPkFmaF32Vop3p, {.vdst = 6, .neg_hi = 4, .src0 = 256, .src1 = 258, .src2 = 260, .opsel_hi = 3, .neg = 2}); words[0] |= uint32_t{1} << 14; // pad_14 is the src2 high-half selector. - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr instruction(decode_valid(*decoder, words.data())); ASSERT_NE(instruction, nullptr); @@ -1012,7 +1012,7 @@ TEST(Gfx1250ExecutionTest, PkFmaF32SimdMatchesScalarWithPartialExec) { } TEST(Gfx1250DecodeTest, Vop3pRejectsLiteral64SelectorInEverySourcePosition) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (const cdna5::Vop3pBuilderFields fields : { @@ -1026,7 +1026,7 @@ TEST(Gfx1250DecodeTest, Vop3pRejectsLiteral64SelectorInEverySourcePosition) { } TEST(Gfx1250DecodeTest, BinaryVop3pIgnoresLiteral64SelectorInUnusedSrc2) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (const uint32_t opcode : {cdna5::kVPkAddF32Vop3p, cdna5::kVPkMulF32Vop3p}) { @@ -1073,7 +1073,7 @@ TEST(Gfx1250ExecutionTest, Wave32ScalarVccHiWritePreservesUpperHalf) { wf->set_exec(0xffff0000u); wf->set_vcc(0); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const uint32_t words[] = {0x8c6b7e6bu, 0}; // s_or_b32 vcc_hi, vcc_hi, exec_lo diff --git a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp index fa435d7aeea3..d559c5d31945 100644 --- a/emulation/rocjitsu/tests/cdna5_instruction_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_instruction_test.cpp @@ -82,7 +82,7 @@ TEST(Gfx1250SimulationTest, SAddPcI64WrapsAtUnsignedBoundaries) { const auto add_one = cdna5::build_sop1(cdna5::kSAddPcI64Sop1, {.ssrc0 = 129}); const auto add_minus_one = cdna5::build_sop1(cdna5::kSAddPcI64Sop1, {.ssrc0 = 193}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr increment(decode_valid(*decoder, add_one.data())); std::unique_ptr decrement(decode_valid(*decoder, add_minus_one.data())); @@ -283,7 +283,7 @@ TEST(Gfx1250SimulationTest, NamedBarrierSignalIsfirstPreservesSccWithoutAllocati auto *wf = sim.dispatch_scratch_wf(); ASSERT_NE(wf, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const std::array signal_words = {0xBE804F7Du}; std::unique_ptr signal(decode_valid(*decoder, signal_words.data())); @@ -304,7 +304,7 @@ void expect_barrier_init_reads_implicit_m0(uint32_t init_encoding, uint32_t init ASSERT_NE(wf1, nullptr); cu->begin_workgroup(0, 0, 2, 4); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const std::array init_words = {init_encoding}; const std::array join_words = {0xBE805281u}; // s_barrier_join 1 @@ -355,7 +355,7 @@ TEST(Gfx1250SimulationTest, NamedBarrierSynchronizesJoinedWavesAcrossPhases) { ASSERT_NE(wf1, nullptr); cu->begin_workgroup(0, 0, 2, 4); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const std::array join_words = {0xBE80527Du}; const std::array signal_words = {0xBE804F7Du}; @@ -494,7 +494,7 @@ TEST(Gfx1250SimulationTest, WorkgroupSignalIsfirstAcceptsNegativeInlineBarrierId ASSERT_NE(wf1, nullptr); cu->begin_workgroup(0, 0, 2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const std::array signal_words = {0xBE804FC1u}; // s_barrier_signal_isfirst -1 std::unique_ptr signal(decode_valid(*decoder, signal_words.data())); @@ -1428,7 +1428,7 @@ TEST(Gfx1250SimulationTest, VopdFmamkUsesSrc2HighBank) { cu->write_vgpr(vb + kAddend, 0, std::bit_cast(100.0f)); cu->write_vgpr(vb + kSrc2Bank * kBankStride + kAddend, 0, std::bit_cast(4.0f)); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words.data())); ASSERT_NE(inst, nullptr); @@ -1564,7 +1564,7 @@ TEST(Gfx1250SimulationTest, DsAddtidLoadAndStoreUseM0ByteBaseAddresses) { constexpr uint32_t kM0ByteBase = 0x1000; wf->set_m0(kM0ByteBase); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const uint32_t vb = wf->vgpr_alloc().base; constexpr uint32_t kLane0Data = 0x12345678u; @@ -1730,7 +1730,7 @@ TEST(Gfx1250ExecutionTest, Vopd3CndmaskAppliesB32NegModifiers) { wf->set_exec(0x3u); wf->set_vcc(0x1u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, cndmask.data())); ASSERT_NE(inst, nullptr); diff --git a/emulation/rocjitsu/tests/cdna5_sim_test_common.h b/emulation/rocjitsu/tests/cdna5_sim_test_common.h index 47e5ae4506f0..0656093fb7de 100644 --- a/emulation/rocjitsu/tests/cdna5_sim_test_common.h +++ b/emulation/rocjitsu/tests/cdna5_sim_test_common.h @@ -75,7 +75,7 @@ RJ_DIAGNOSTIC_POP #include namespace rocjitsu::test::cdna5 { -inline const std::string kGfx1250ConfigPath = std::string(CONFIG_DIR) + "/gfx1250.json"; +inline const std::string kGfx1250ConfigPath = std::string(CONFIG_DIR) + "/gfx1250_mi455x.json"; inline constexpr uint32_t S_ENDPGM_GFX12 = 0xBFB00000u; inline constexpr uint32_t S_WAIT_KMCNT_0_GFX12 = 0xBFC70000u; @@ -323,7 +323,7 @@ inline uint32_t read_global_u32(amdgpu::GpuMemory &memory, uint64_t addr) { inline std::unique_ptr decode_gfx1250(const std::array &words, std::string_view expected_mnemonic) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); if (!decoder) { ADD_FAILURE() << "Decoder::create() returned nullptr for gfx1250"; return nullptr; diff --git a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp index 69d370ac4b9e..1a06ea418aa0 100644 --- a/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_tensor_dma_test.cpp @@ -1122,7 +1122,7 @@ TEST(Gfx1250ExecutionTest, SBarrierWaitIsNoOpForSingleWaveWorkgroup) { ASSERT_NE(wf, nullptr); ASSERT_EQ(wf->state(), amdgpu::WfState::RUNNING); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const std::array wait_words = {0xBF94FFFFu, 0u}; @@ -1149,7 +1149,7 @@ TEST(Gfx1250ExecutionTest, SBarrierWaitReleasesOnlyAfterSignalQuorum) { ASSERT_NE(wf1, nullptr); cu->begin_workgroup(0, 0, 2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const std::array wait_words = {0xBF94FFFFu, 0u}; diff --git a/emulation/rocjitsu/tests/code/kernel_descriptor_scan_test.cpp b/emulation/rocjitsu/tests/code/kernel_descriptor_scan_test.cpp index b9ebd02b1f28..41eec4d15339 100644 --- a/emulation/rocjitsu/tests/code/kernel_descriptor_scan_test.cpp +++ b/emulation/rocjitsu/tests/code/kernel_descriptor_scan_test.cpp @@ -139,7 +139,7 @@ TEST(KernelWavefrontSize, Rdna4HonorsEnableWavefrontSize32Bit) { rocr::llvm::amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, 1); EXPECT_EQ(kernel_wavefront_size(ROCJITSU_CODE_ARCH_RDNA4, desc), 32); // bit set EXPECT_EQ(kernel_wavefront_size(ROCJITSU_CODE_ARCH_CDNA4, desc), 64); - EXPECT_EQ(kernel_wavefront_size(ROCJITSU_CODE_ARCH_GFX1250, desc), 32); + EXPECT_EQ(kernel_wavefront_size(ROCJITSU_CODE_ARCH_CDNA5, desc), 32); } // The AMDHSA descriptor VGPR granule is wave-size dependent on RDNA: 8 for Wave32, @@ -150,7 +150,7 @@ TEST(KernelDescriptorVgprGranule, RdnaIsWaveSizeDependent) { EXPECT_EQ(descriptor_vgpr_granularity_for_wavefront(ROCJITSU_CODE_ARCH_RDNA4, 64), 4u); EXPECT_EQ(descriptor_vgpr_granularity_for_wavefront(ROCJITSU_CODE_ARCH_CDNA4, 64), 8u); EXPECT_EQ(descriptor_vgpr_granularity_for_wavefront(ROCJITSU_CODE_ARCH_CDNA1, 64), 4u); - EXPECT_EQ(descriptor_vgpr_granularity_for_wavefront(ROCJITSU_CODE_ARCH_GFX1250, 32), 16u); + EXPECT_EQ(descriptor_vgpr_granularity_for_wavefront(ROCJITSU_CODE_ARCH_CDNA5, 32), 16u); } // Paired Wave32/Wave64 example: an RDNA4 descriptor with GRANULATED_WORKITEM_VGPR_COUNT=0 diff --git a/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp b/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp index 8e711567c128..eee2ac73e45f 100644 --- a/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp +++ b/emulation/rocjitsu/tests/code/relocation_function_table_test.cpp @@ -536,10 +536,10 @@ TEST(RelocationFunctionTable, ResolvesDynamicDispatchThroughGotAndTableLoads) { const auto tables = discover_relocation_function_tables(object); ASSERT_EQ(tables.size(), 1u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::array leaders{40}; - const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_CDNA5, leaders); const auto dispatches = analyze_relocation_pairs(blocks, tables, 0x1000).dispatches; ASSERT_EQ(dispatches.size(), 1u); EXPECT_EQ(dispatches[0].table_index, 0u); @@ -561,10 +561,10 @@ TEST(RelocationFunctionTable, ResolvesRcclDirectIndexedTableDispatch) { ASSERT_EQ(tables.size(), 1u); EXPECT_TRUE(tables[0].got_slot_vaddrs.empty()); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::array leaders{32}; - const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_CDNA5, leaders); const auto analysis = analyze_relocation_pairs(blocks, tables, 0x1000); const auto &dispatches = analysis.dispatches; ASSERT_EQ(dispatches.size(), 1u); @@ -600,10 +600,10 @@ TEST(RelocationFunctionTable, RejectsChainedAddressAddDispatch) { const auto tables = discover_relocation_function_tables(object); ASSERT_EQ(tables.size(), 1u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::array leaders{44}; - const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_CDNA5, leaders); const auto dispatches = analyze_relocation_pairs(blocks, tables, 0x1000).dispatches; // The base is built with two literal adds; only one add offset can be relocated, // so the dispatch must fail closed rather than resolve to a value whose first @@ -629,10 +629,10 @@ TEST(RelocationFunctionTable, ResolvesBackwardTableAddress) { const auto tables = discover_relocation_function_tables(object); ASSERT_EQ(tables.size(), 1u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::array leaders{32}; - const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_GFX1250, leaders); + const auto blocks = build_valid_blocks(object, *decoder, ROCJITSU_CODE_ARCH_CDNA5, leaders); const auto dispatches = analyze_relocation_pairs(blocks, tables, kAssumedTextVaddr).dispatches; ASSERT_EQ(dispatches.size(), 1u); EXPECT_EQ(dispatches[0].table_index, 0u); diff --git a/emulation/rocjitsu/tests/config_test.cpp b/emulation/rocjitsu/tests/config_test.cpp index 0022a5a9744a..17596e350eef 100644 --- a/emulation/rocjitsu/tests/config_test.cpp +++ b/emulation/rocjitsu/tests/config_test.cpp @@ -862,7 +862,7 @@ TEST(ConfigLoaderTest, RejectsSimulatorConfigForHardwareDbtBackend) { TEST(ConfigLoaderTest, Gfx1250ComputeUnitDefaultsCoverTtmpAndHighVgprs) { const char *json = R"({"max_ticks":1000,"num_threads":1, - "vm":{"arch":"gfx1250"}, + "vm":{"arch":"cdna5"}, "topology":{"root":{"name":"soc","type":"soc","children":[ {"name":"vram","type":"gpu_memory"}, {"name":"xcd0","type":"xcd","children":[ @@ -1166,7 +1166,7 @@ TEST(CheckpointTest, SaveAndRestoreWave32ExecScratch) { TEST(CheckpointTest, SaveAndRestoreHwregState) { const char *json = R"({"max_ticks":10000,"num_threads":1, - "vm":{"arch":"gfx1250"}, + "vm":{"arch":"cdna5"}, "topology":{ "root":{ "name":"soc","type":"soc", diff --git a/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh b/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh index 3123f90a1fc0..07f410f0a51e 100755 --- a/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh +++ b/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh @@ -45,7 +45,7 @@ targets=( "gfx950 gfx950_cdna4.json gfx950_skip_tests.json" "gfx1100 gfx1100_w7900.json gfx1100_skip_tests.json" "gfx1201 gfx1201_r9700.json gfx1201_skip_tests.json" - "gfx1250 gfx1250.json gfx1250_skip_tests.json" + "gfx1250 gfx1250_mi455x.json gfx1250_skip_tests.json" ) while (( $# )); do diff --git a/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp b/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp index df2e44dbfe96..516935c2cb7a 100644 --- a/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp +++ b/emulation/rocjitsu/tests/dbt/relocation_function_table_hip_test.cpp @@ -96,10 +96,10 @@ TEST(RelocationFunctionTableHip, TranslatesEightWayDeviceDispatch) { std::ranges::sort(source_targets); EXPECT_EQ(std::ranges::adjacent_find(source_targets), source_targets.end()); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto blocks = - rocjitsu::build_valid_blocks(*source, *decoder, ROCJITSU_CODE_ARCH_GFX1250, source_targets); + rocjitsu::build_valid_blocks(*source, *decoder, ROCJITSU_CODE_ARCH_CDNA5, source_targets); const auto dispatches = rocjitsu::analyze_relocation_pairs(blocks, source_tables, source->text_sections()[0]->vaddr()) .dispatches; @@ -109,7 +109,7 @@ TEST(RelocationFunctionTableHip, TranslatesEightWayDeviceDispatch) { rocjitsu::BinaryTranslatorOptions options; options.input_revision = rocjitsu::ProcessorRevision::Gfx1250B0; options.output_revision = rocjitsu::ProcessorRevision::Gfx1250A0; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); auto result = translator.translate(*source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "translation failed without diagnostics" @@ -154,7 +154,7 @@ TEST(RelocationFunctionTableHip, TranslationIgnoresExplicitNonAllocatedRelocatio options.input_revision = rocjitsu::ProcessorRevision::Gfx1250B0; options.output_revision = rocjitsu::ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(augmented); diff --git a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp index 86074f1464ae..c1f3402c97af 100644 --- a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp @@ -2339,7 +2339,7 @@ TEST(BinaryTranslatorE2E, Gfx1250LongDirectBranchGrowthIsIdempotent) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2352,14 +2352,14 @@ TEST(BinaryTranslatorE2E, Gfx1250LongDirectBranchGrowthIsIdempotent) { const auto *target_words = reinterpret_cast(translated.text_sections()[0]->data()); const uint32_t marker = rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ((target_words[0] >> 16) & 0x7fu, cdna5::kSCbranchScc1Sopp); EXPECT_EQ(target_words[1], marker); const auto translated_word_count = translated.text_sections()[0]->size() / sizeof(uint32_t); EXPECT_EQ(std::count(target_words, target_words + translated_word_count, marker), 2); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -2403,7 +2403,7 @@ TEST(BinaryTranslatorE2E, Gfx1250LongBranchReportsSgprExhaustionAfterSemanticExp rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2439,7 +2439,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CompactConditionalLayoutIsIdempotent) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -2455,7 +2455,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CompactConditionalLayoutIsIdempotent) { static_cast(kTargetWord - 1))); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -2488,10 +2488,10 @@ TEST(BinaryTranslatorE2E, Gfx1250KeepsDirectlyCalledHelperThatIsAlsoAddressTaken const std::vector words = { kGfx1250SEndpgm, // word 0: kernel 0 entry kGfx1250SNop, // word 1: padding - rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_GFX1250), // word 2: kernel 1 - kGfx1250SEndpgm, // word 3 - kGfx1250SNop, // word 4: helper - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), // word 5: return + rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_CDNA5), // word 2: kernel 1 + kGfx1250SEndpgm, // word 3 + kGfx1250SNop, // word 4: helper + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), // word 5: return }; auto image = @@ -2501,7 +2501,7 @@ TEST(BinaryTranslatorE2E, Gfx1250KeepsDirectlyCalledHelperThatIsAlsoAddressTaken ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2511,7 +2511,7 @@ TEST(BinaryTranslatorE2E, Gfx1250KeepsDirectlyCalledHelperThatIsAlsoAddressTaken rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_TRUE(translated.is_valid()); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -2554,7 +2554,7 @@ translate_kernarg_fixture(const std::vector &words, bool enable_kernar rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); EXPECT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); return translator.translate(source); @@ -2573,8 +2573,8 @@ TEST(BinaryTranslatorE2E, Gfx1250AdmitsKernargLoadedIndirectCallTarget) { kernarg_load_word(0), kernarg_load_word(1), rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, - ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; EXPECT_TRUE(translate_kernarg_fixture(words, /*enable_kernarg=*/true).ok()); } @@ -2587,8 +2587,8 @@ TEST(BinaryTranslatorE2E, Gfx1250RefusesIndirectCallWhenNoKernargSegmentExists) kernarg_load_word(0), kernarg_load_word(1), rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, - ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; EXPECT_TRUE(refused_unrecovered_transfer(translate_kernarg_fixture(words, /*enable_kernarg=*/false))); @@ -2603,8 +2603,8 @@ TEST(BinaryTranslatorE2E, Gfx1250KernargFactSurvivesWriteToTheRegisterAboveThePa cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = static_cast(kKernargTargetSreg + 2)})[0], rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, - ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; EXPECT_TRUE(translate_kernarg_fixture(words, /*enable_kernarg=*/true).ok()); } @@ -2620,8 +2620,8 @@ TEST(BinaryTranslatorE2E, Gfx1250RefusesKernargTargetClobberedOnOnePath) { cdna5::build_sop1(cdna5::kSMovB64Sop1, {.ssrc0 = 128, .sdst = static_cast(kKernargTargetSreg)})[0], rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, - ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; EXPECT_TRUE(refused_unrecovered_transfer(translate_kernarg_fixture(words, /*enable_kernarg=*/true))); @@ -2634,10 +2634,10 @@ TEST(BinaryTranslatorE2E, Gfx1250AdmitsKernargTargetLiveOnBothPaths) { kernarg_load_word(0), kernarg_load_word(1), cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 1})[0], - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, - ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; EXPECT_TRUE(translate_kernarg_fixture(words, /*enable_kernarg=*/true).ok()); } @@ -2648,11 +2648,11 @@ TEST(BinaryTranslatorE2E, Gfx1250AdmitsKernargTargetReachedThroughALoopLatch) { const std::vector words = { kernarg_load_word(0), kernarg_load_word(1), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = static_cast(-3)})[0], - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; EXPECT_TRUE(translate_kernarg_fixture(words, /*enable_kernarg=*/true).ok()); } @@ -2670,16 +2670,16 @@ TEST(BinaryTranslatorE2E, Gfx1250StopsAdoptedRootReturnWalkAtTheNextRoot) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr uint16_t kSharedReturnSreg = 30; const std::vector words = { - rocjitsu::build_s_getpc_b64(10, ROCJITSU_CODE_ARCH_GFX1250), // word 0: kernel 0, poisons the - // code-address accounting - kGfx1250SEndpgm, // word 1: kernel 1 entry + rocjitsu::build_s_getpc_b64(10, ROCJITSU_CODE_ARCH_CDNA5), // word 0: kernel 0, poisons the + // code-address accounting + kGfx1250SEndpgm, // word 1: kernel 1 entry cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 3})[0], // word 2: root A -> word 6 - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // word 3: A falls into B - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // word 4: root B - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), // word 5 + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // word 3: A falls into B + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // word 4: root B + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), // word 5 rocjitsu::build_s_setpc_b64(kSharedReturnSreg, - ROCJITSU_CODE_ARCH_GFX1250), // word 6: reached from both - kGfx1250SEndpgm, // word 7 + ROCJITSU_CODE_ARCH_CDNA5), // word 6: reached from both + kGfx1250SEndpgm, // word 7 }; auto image = @@ -2690,7 +2690,7 @@ TEST(BinaryTranslatorE2E, Gfx1250StopsAdoptedRootReturnWalkAtTheNextRoot) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2712,7 +2712,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RefusesFunctionPointerIntoTheMiddleOfAnInstruct constexpr uint16_t kLiteralOperand = 255; const std::vector words = { kGfx1250SEndpgm, // word 0: kernel entry - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), // word 1: two-word instruction 0x00000010u, // word 2: its literal kGfx1250SEndpgm, // word 3 @@ -2725,7 +2725,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RefusesFunctionPointerIntoTheMiddleOfAnInstruct ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2745,15 +2745,15 @@ TEST(BinaryTranslatorE2E, Gfx1250SizedFunctionSymbolEndingInsideMarkedWindowKeep // skips. A plain nop makes the consumer compact instead, which never exercises the mapping. std::vector words = { rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 2 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), }; words.resize(kTargetOffset / sizeof(uint32_t), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5)); words.push_back(kGfx1250SEndpgm); // Four words: the marker, the getpc, and its two-word delta add. The extent therefore ends @@ -2764,7 +2764,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SizedFunctionSymbolEndingInsideMarkedWindowKeep ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto first = translator.translate(source); @@ -2773,7 +2773,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SizedFunctionSymbolEndingInsideMarkedWindowKeep rocjitsu::AmdGpuCodeObject translated(first.elf_bytes.data(), first.elf_bytes.size()); ASSERT_TRUE(translated.is_valid()); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -2802,15 +2802,15 @@ TEST(BinaryTranslatorE2E, Gfx1250CompilerLongJumpCompactsIdempotentlyAfterPaddin constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; std::vector words = { - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 2 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), }; words.resize(kTargetOffset / sizeof(uint32_t), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5)); words.push_back(kGfx1250SEndpgm); auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); @@ -2818,7 +2818,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CompilerLongJumpCompactsIdempotentlyAfterPaddin ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2830,11 +2830,11 @@ TEST(BinaryTranslatorE2E, Gfx1250CompilerLongJumpCompactsIdempotentlyAfterPaddin ASSERT_FALSE(translated.text_sections().empty()); const auto *target_words = reinterpret_cast(translated.text_sections()[0]->data()); - EXPECT_EQ(target_words[0], rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250)); + EXPECT_EQ(target_words[0], rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5)); EXPECT_EQ((target_words[4] >> 16) & 0x7fu, cdna5::kSBranchSopp); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -2850,14 +2850,14 @@ TEST(BinaryTranslatorE2E, Gfx1250MarkedLongJumpStaysLongWhenTargetIsDirectlyReac constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr uint32_t kTargetOffset = 5 * sizeof(uint32_t); const uint32_t marker = rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); const std::vector words = { marker, - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 2 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), kGfx1250SEndpgm, }; @@ -2866,7 +2866,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MarkedLongJumpStaysLongWhenTargetIsDirectlyReac ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2879,10 +2879,10 @@ TEST(BinaryTranslatorE2E, Gfx1250MarkedLongJumpStaysLongWhenTargetIsDirectlyReac const auto *target_words = reinterpret_cast(translated.text_sections()[0]->data()); EXPECT_EQ(target_words[0], marker); - EXPECT_EQ(target_words[4], rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250)); + EXPECT_EQ(target_words[4], rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5)); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -2899,17 +2899,17 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotTreatLiteralAsLongJumpMarker) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr uint32_t kTargetOffset = 7 * sizeof(uint32_t); const uint32_t marker = rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); const std::vector words = { - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, 0, kUnrelatedSgpr, kUnrelatedSgpr, + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, 0, kUnrelatedSgpr, kUnrelatedSgpr, kLiteralOperand), marker, - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 3 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), kGfx1250SEndpgm, }; @@ -2918,7 +2918,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotTreatLiteralAsLongJumpMarker) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2929,7 +2929,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotTreatLiteralAsLongJumpMarker) { ASSERT_TRUE(translated.is_valid()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_setpc_b64"; }), 0); @@ -2947,16 +2947,16 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAcrossBlockBoundar constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr uint32_t kTargetOffset = 7 * sizeof(uint32_t); const uint32_t marker = rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); const std::vector words = { cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 1})[0], marker, - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 3 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), kGfx1250SEndpgm, }; @@ -2965,7 +2965,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAcrossBlockBoundar ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -2976,7 +2976,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAcrossBlockBoundar ASSERT_TRUE(translated.is_valid()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_setpc_b64"; }), 0); @@ -2994,19 +2994,19 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAcrossInteriorBloc constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr uint32_t kTargetOffset = 8 * sizeof(uint32_t); const uint32_t marker = rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); const std::vector words = { marker, - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), // The branch retains the getpc result while making the add an interior // block entry in the recovered window. - rocjitsu::build_s_branch(1, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_branch(1, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 2 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), kGfx1250SEndpgm, }; @@ -3015,7 +3015,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAcrossInteriorBloc ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -3033,17 +3033,17 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAtConsumerBlockEnt constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; constexpr uint32_t kTargetOffset = 5 * sizeof(uint32_t); const uint32_t marker = rocjitsu::build_s_nop(rocjitsu::kLongDirectBranchMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); const std::vector words = { marker, - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - 2 * sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), // The recovered target branches back to the consumer, making the // consumer itself a second block entry into the marked window. - rocjitsu::build_s_branch(-2, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_branch(-2, ROCJITSU_CODE_ARCH_CDNA5), kGfx1250SEndpgm, }; @@ -3052,7 +3052,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAtConsumerBlockEnt ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -3063,7 +3063,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotPreserveLongJumpMarkerAtConsumerBlockEnt ASSERT_TRUE(translated.is_valid()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_setpc_b64"; }), 0); @@ -3091,7 +3091,7 @@ TEST(BinaryTranslatorE2E, LongDirectBranchInvertsEveryGfx1250ConditionalPair) { for (const TestCase &test_case : test_cases) { const uint32_t branch_word = rocjitsu::pack_sopp(test_case.source_opcode, 0); - const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_GFX1250); + const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(branch, nullptr); std::vector text(kTargetOffset + sizeof(uint32_t), 0); @@ -3116,7 +3116,7 @@ TEST(BinaryTranslatorE2E, LongDirectBranchInvertsEveryGfx1250ConditionalPair) { .translated_words = {branch_word}}); const auto result = - rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(result.ok) << result.message; uint32_t inverted = 0; std::memcpy(&inverted, text.data(), sizeof(inverted)); @@ -3147,8 +3147,8 @@ TEST(BinaryTranslatorE2E, RebaseTextOffsetShiftsOffsetsAtInsertionBoundaries) { } TEST(BinaryTranslatorE2E, GrowDirectBranchWindowsRebasesEveryLaterLayoutOffset) { - const uint32_t branch_word = rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250); - const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_GFX1250); + const uint32_t branch_word = rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5); + const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(branch, nullptr); constexpr uint64_t kWord = sizeof(uint32_t); @@ -3190,7 +3190,7 @@ TEST(BinaryTranslatorE2E, GrowDirectBranchWindowsRebasesEveryLaterLayoutOffset) .required_window_bytes = 5 * kWord}, }; const auto insertions = - rocjitsu::grow_control_flow_windows(text, layout, requirements, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::grow_control_flow_windows(text, layout, requirements, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(insertions.has_value()); ASSERT_EQ(insertions->size(), 2u); EXPECT_EQ(insertions->at(0).offset, kWord); @@ -3212,7 +3212,7 @@ TEST(BinaryTranslatorE2E, GrowDirectBranchWindowsRebasesEveryLaterLayoutOffset) EXPECT_EQ(layout.recovered_builder_fixups[0].target_recovery_end_offset, 10 * kWord); EXPECT_EQ(layout.branch_island_slots[0], 11 * kWord); - const uint32_t expected_nop = rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250); + const uint32_t expected_nop = rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5); uint32_t inserted_word = 0; std::memcpy(&inserted_word, text.data() + kWord, sizeof(inserted_word)); EXPECT_EQ(inserted_word, expected_nop); @@ -3227,8 +3227,8 @@ TEST(BinaryTranslatorE2E, GrowDirectBranchWindowsRebasesEveryLaterLayoutOffset) TEST(BinaryTranslatorE2E, FixedDirectBranchWindowRejectsGrowthWithoutMutation) { constexpr uint64_t kWord = sizeof(uint32_t); constexpr uint64_t kTargetOffset = 140000; - const uint32_t branch_word = rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250); - const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_GFX1250); + const uint32_t branch_word = rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5); + const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(branch, nullptr); std::vector text(kTargetOffset + kWord, 0); @@ -3250,8 +3250,7 @@ TEST(BinaryTranslatorE2E, FixedDirectBranchWindowRejectsGrowthWithoutMutation) { .translated_words = {branch_word}}); const auto original_text = text; - const auto result = - rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250); + const auto result = rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); EXPECT_FALSE(result.ok); EXPECT_EQ(result.reason, rocjitsu::TextLayoutFailureReason::BranchOutOfRange); @@ -3261,8 +3260,8 @@ TEST(BinaryTranslatorE2E, FixedDirectBranchWindowRejectsGrowthWithoutMutation) { } TEST(BinaryTranslatorE2E, DirectBranchWindowsRejectInvalidGrowthWithoutMutation) { - const uint32_t branch_word = rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250); - const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_GFX1250); + const uint32_t branch_word = rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5); + const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(branch, nullptr); auto rejects_without_mutation = @@ -3279,7 +3278,7 @@ TEST(BinaryTranslatorE2E, DirectBranchWindowsRejectInvalidGrowthWithoutMutation) const auto original_text = text; const auto result = rocjitsu::grow_control_flow_windows(text, layout, requirements, - ROCJITSU_CODE_ARCH_GFX1250); + ROCJITSU_CODE_ARCH_CDNA5); EXPECT_FALSE(result.has_value()); EXPECT_EQ(text, original_text); EXPECT_EQ(layout.body_end, sizeof(uint32_t)); @@ -3311,7 +3310,7 @@ TEST(BinaryTranslatorE2E, DirectBranchWindowsRejectInvalidGrowthWithoutMutation) const auto original_text = text; const auto result = - rocjitsu::grow_control_flow_windows(text, layout, requirements, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::grow_control_flow_windows(text, layout, requirements, ROCJITSU_CODE_ARCH_CDNA5); EXPECT_FALSE(result.has_value()); EXPECT_EQ(text, original_text); EXPECT_EQ(layout.body_end, sizeof(uint32_t)); @@ -3325,7 +3324,7 @@ TEST(BinaryTranslatorE2E, PatchesOutOfRangeConditionalThroughIslandSlotWithoutSg constexpr uint64_t kIslandOffset = 70000; const uint32_t branch_word = rocjitsu::pack_sopp(cdna5::kSCbranchScc1Sopp, static_cast(0)); - const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_GFX1250); + const auto branch = rocjitsu::test_support::decode_one(branch_word, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(branch, nullptr); std::vector text(kTargetOffset + kWord, 0); @@ -3346,30 +3345,29 @@ TEST(BinaryTranslatorE2E, PatchesOutOfRangeConditionalThroughIslandSlotWithoutSg layout.branch_island_slots.push_back(kIslandOffset); const auto before_growth = - rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_FALSE(before_growth.ok); ASSERT_EQ(before_growth.required_windows.size(), 1u); EXPECT_EQ(before_growth.required_windows.front().required_window_bytes, 2 * kWord); const auto insertions = rocjitsu::grow_control_flow_windows( - text, layout, before_growth.required_windows, ROCJITSU_CODE_ARCH_GFX1250); + text, layout, before_growth.required_windows, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(insertions.has_value()); - ASSERT_TRUE(rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250).ok); + ASSERT_TRUE(rocjitsu::patch_direct_branch_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5).ok); const auto *target_words = reinterpret_cast(text.data()); EXPECT_EQ(target_words[0], rocjitsu::pack_sopp(cdna5::kSCbranchScc0Sopp, 1)); const uint64_t rebased_island_offset = kIslandOffset + kWord; const auto source_to_island = rocjitsu::compute_sopp_branch_simm16(kWord, rebased_island_offset); ASSERT_TRUE(source_to_island.has_value()); - EXPECT_EQ(target_words[1], - rocjitsu::build_s_branch(*source_to_island, ROCJITSU_CODE_ARCH_GFX1250)); + EXPECT_EQ(target_words[1], rocjitsu::build_s_branch(*source_to_island, ROCJITSU_CODE_ARCH_CDNA5)); uint32_t island_word = 0; std::memcpy(&island_word, text.data() + rebased_island_offset, sizeof(island_word)); const auto island_to_target = rocjitsu::compute_sopp_branch_simm16(rebased_island_offset, kTargetOffset + kWord); ASSERT_TRUE(island_to_target.has_value()); - EXPECT_EQ(island_word, rocjitsu::build_s_branch(*island_to_target, ROCJITSU_CODE_ARCH_GFX1250)); + EXPECT_EQ(island_word, rocjitsu::build_s_branch(*island_to_target, ROCJITSU_CODE_ARCH_CDNA5)); } TEST(BinaryTranslatorE2E, FullSgprConditionalPreservesPoolAfterUnconditionalBranch) { @@ -3468,19 +3466,19 @@ TEST(BinaryTranslatorE2E, Gfx1250RelocatesReachableGeneratedIslandPoolSlotsIdemp // reaches the pool header and skip. cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 2})[0], rocjitsu::build_s_nop(rocjitsu::kBranchIslandPoolMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), rocjitsu::build_s_branch(static_cast(rocjitsu::kDirectBranchIslandPoolSlots), - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), }; words.insert(words.end(), rocjitsu::kDirectBranchIslandPoolSlots, - rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5)); words.push_back(kGfx1250SEndpgm); auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto first = translator.translate(source); @@ -3500,21 +3498,21 @@ TEST(BinaryTranslatorE2E, Gfx1250RejectsGeneratedIslandPoolSlotTargetingOutsideT // Reach the first private slot so it is live in this kernel scope. cdna5::build_sopp(cdna5::kSCbranchScc0Sopp, {.simm16 = 2})[0], rocjitsu::build_s_nop(rocjitsu::kBranchIslandPoolMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), rocjitsu::build_s_branch(static_cast(rocjitsu::kDirectBranchIslandPoolSlots), - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), }; words.insert(words.end(), rocjitsu::kDirectBranchIslandPoolSlots, - rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5)); words[rocjitsu::kGeneratedIslandPoolHeaderWords + 1] = - rocjitsu::build_s_branch(30000, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::build_s_branch(30000, ROCJITSU_CODE_ARCH_CDNA5); words.push_back(kGfx1250SEndpgm); auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -3529,12 +3527,12 @@ TEST(BinaryTranslatorE2E, Gfx1250InvalidPoolCandidateFallsBackToNormalDecodeDiag constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; std::vector words = { rocjitsu::build_s_nop(rocjitsu::kBranchIslandPoolMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), rocjitsu::build_s_branch(static_cast(rocjitsu::kDirectBranchIslandPoolSlots), - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), }; words.insert(words.end(), rocjitsu::kDirectBranchIslandPoolSlots, - rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5)); words[rocjitsu::kGeneratedIslandPoolHeaderWords] = cdna5::build_vop1(cdna5::kVReadfirstlaneB32Vop1, {.src0 = 255})[0]; words.push_back(kGfx1250SEndpgm); @@ -3543,7 +3541,7 @@ TEST(BinaryTranslatorE2E, Gfx1250InvalidPoolCandidateFallsBackToNormalDecodeDiag rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -3558,21 +3556,21 @@ TEST(BinaryTranslatorE2E, Gfx1250RejectsNearMissGeneratedIslandPool) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; std::vector words = { rocjitsu::build_s_nop(rocjitsu::kBranchIslandPoolMarkerNopImmediate, - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), rocjitsu::build_s_branch(static_cast(rocjitsu::kDirectBranchIslandPoolSlots), - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), }; words.insert(words.end(), rocjitsu::kDirectBranchIslandPoolSlots, - rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250)); + rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5)); words[2 + rocjitsu::kDirectBranchIslandPoolSlots / 2] = - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5); words.push_back(kGfx1250SEndpgm); auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto first = translator.translate(source); @@ -3582,7 +3580,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RejectsNearMissGeneratedIslandPool) { ASSERT_TRUE(translated.is_valid()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if(decoded, [](const auto &inst) { return inst->mnemonic() == "s_branch"; }), 1); @@ -3638,8 +3636,8 @@ TEST(BinaryTranslatorE2E, DuplicatesSharedReachableBlocksPerKernel) { TEST(BinaryTranslatorE2E, RejectsAmbiguousRuntimeEntryClonedAcrossKernelScopes) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; const std::vector words = { - rocjitsu::build_s_branch(1, ROCJITSU_CODE_ARCH_GFX1250), // kernel0 -> helper 0x08. - rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250), // kernel1 -> helper 0x08. + rocjitsu::build_s_branch(1, ROCJITSU_CODE_ARCH_CDNA5), // kernel0 -> helper 0x08. + rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5), // kernel1 -> helper 0x08. kGfx1250SEndpgm, }; for (const auto relocation : {rocjitsu::test_support::TestRuntimeTextRelocation::Abs64, @@ -3658,7 +3656,7 @@ TEST(BinaryTranslatorE2E, RejectsAmbiguousRuntimeEntryClonedAcrossKernelScopes) ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -3707,7 +3705,7 @@ TEST(BinaryTranslatorE2E, PreservesUniqueRelocationBackedTextEntries) { auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.verify_rewrite_discharge = true; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -3719,8 +3717,7 @@ TEST(BinaryTranslatorE2E, PreservesUniqueRelocationBackedTextEntries) { ASSERT_TRUE(translated.is_valid()); ASSERT_EQ(translated.text_sections().size(), 1u); const auto *text = translated.text_sections().front(); - rocjitsu::KernelDescriptorTranslator parser(ROCJITSU_CODE_ARCH_GFX1250, - ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::KernelDescriptorTranslator parser(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5); const auto infos = parser.translate_image(result.elf_bytes, text->sectionOffset(), text->size(), rocjitsu::KernelDescriptorTranslationOptions{}); ASSERT_EQ(infos.size(), 2u); @@ -7145,14 +7142,14 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesUnaffectedInstructionsForB0ToA0) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); EXPECT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" : result.diagnostics.front().message); - EXPECT_EQ(result.host_arch, ROCJITSU_CODE_ARCH_GFX1250); + EXPECT_EQ(result.host_arch, ROCJITSU_CODE_ARCH_CDNA5); } TEST(BinaryTranslatorE2E, Gfx1250ReplacesSClauseWithNopForB0ToA0) { @@ -7164,7 +7161,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ReplacesSClauseWithNopForB0ToA0) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7192,7 +7189,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesSClauseOutsideB0ToA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(revision, revision)); auto result = translator.translate(source); @@ -7210,13 +7207,13 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesSClauseOutsideB0ToA0) { TEST(BinaryTranslatorE2E, Gfx1250RelocatesDirectCallForB0ToA0) { constexpr uint16_t kReturnSreg = 30; const std::vector words = { - rocjitsu::build_s_branch(2, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_call_b64(kReturnSreg, 2, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_branch(2, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_call_b64(kReturnSreg, 2, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5), }; auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); @@ -7225,7 +7222,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RelocatesDirectCallForB0ToA0) { auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.verify_rewrite_discharge = true; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); auto result = translator.translate(source); @@ -7237,14 +7234,13 @@ TEST(BinaryTranslatorE2E, Gfx1250RelocatesDirectCallForB0ToA0) { ASSERT_FALSE(translated.text_sections().empty()); const auto *target_words = reinterpret_cast(translated.text_sections()[0]->data()); - EXPECT_EQ(target_words[0], rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_GFX1250)); - EXPECT_EQ(target_words[1], - rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_GFX1250)); - EXPECT_EQ(target_words[2], rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250)); - EXPECT_EQ(target_words[3], rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_GFX1250)); + EXPECT_EQ(target_words[0], rocjitsu::build_s_branch(0, ROCJITSU_CODE_ARCH_CDNA5)); + EXPECT_EQ(target_words[1], rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_CDNA5)); + EXPECT_EQ(target_words[2], rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5)); + EXPECT_EQ(target_words[3], rocjitsu::build_s_setpc_b64(kReturnSreg, ROCJITSU_CODE_ARCH_CDNA5)); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_GE(decoded.size(), 4u); EXPECT_EQ(decoded[1]->mnemonic(), "s_call_i64"); ASSERT_TRUE(decoded[1]->branch_offset_bytes().has_value()); @@ -7254,16 +7250,16 @@ TEST(BinaryTranslatorE2E, Gfx1250RelocatesDirectCallForB0ToA0) { TEST(BinaryTranslatorE2E, Gfx1250DirectTailTransferCompactionIsIdempotent) { constexpr uint16_t kReturnSreg = 30; const std::vector words = { - rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_call_b64(kReturnSreg, 1, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), }; auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -7275,12 +7271,11 @@ TEST(BinaryTranslatorE2E, Gfx1250DirectTailTransferCompactionIsIdempotent) { ASSERT_FALSE(translated.text_sections().empty()); const auto *target_words = reinterpret_cast(translated.text_sections()[0]->data()); - EXPECT_EQ(target_words[0], - rocjitsu::build_s_call_b64(kReturnSreg, 0, ROCJITSU_CODE_ARCH_GFX1250)); - EXPECT_EQ(target_words[1], rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_GFX1250)); + EXPECT_EQ(target_words[0], rocjitsu::build_s_call_b64(kReturnSreg, 0, ROCJITSU_CODE_ARCH_CDNA5)); + EXPECT_EQ(target_words[1], rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5)); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto second = verifier.translate(translated); @@ -7308,7 +7303,7 @@ TEST(BinaryTranslatorE2E, Gfx1250KernargPreloadUsesSingleDescriptorEntry) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7333,7 +7328,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesUnaffectedLiteralOperandsForB0ToA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7362,7 +7357,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesFp8ConversionsWhenClampIsClear) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7388,7 +7383,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesCvtPkFp8F32ClampSetForA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7397,7 +7392,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesCvtPkFp8F32ClampSetForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &item) { return item->mnemonic() == "v_cvt_pk_fp8_f32"; }), 0); @@ -7416,7 +7411,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesLiteralCvtPkFp8F32ClampSetForA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7425,7 +7420,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesLiteralCvtPkFp8F32ClampSetForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &item) { return item->mnemonic() == "v_cvt_pk_fp8_f32"; }), 0); @@ -7446,7 +7441,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MaterializedE5m3LiteralIgnoresTheGuestSourceBan rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -7455,7 +7450,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MaterializedE5m3LiteralIgnoresTheGuestSourceBan : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "v_cvt_pk_fp8_f32"; }), 0); @@ -7482,7 +7477,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesCvtSrFp8F32ClampSetForA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7491,7 +7486,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesCvtSrFp8F32ClampSetForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &item) { return item->mnemonic() == "v_cvt_sr_fp8_f32"; }), 0); @@ -7599,7 +7594,7 @@ run_gfx1250_e5m3_replacement(uint16_t opcode, uint8_t opsel, Gfx1250E5m3Operand rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(source_words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -7618,7 +7613,7 @@ run_gfx1250_e5m3_replacement(uint16_t opcode, uint8_t opsel, Gfx1250E5m3Operand rocjitsu::amdgpu::GpuMemory gpu_mem("gfx1250_e5m3_mem"); rocjitsu::amdgpu::L2Cache l2("gfx1250_e5m3_l2"); rocjitsu::amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; // Every bank must be addressable: a role's two-bit selector resolves an @@ -7649,7 +7644,7 @@ run_gfx1250_e5m3_replacement(uint16_t opcode, uint8_t opsel, Gfx1250E5m3Operand place(src1, src1_bank, kSrc1Vgpr, kSrc1Sgpr); cu->write_vgpr(vb + (dst_bank << 8) + kDstVgpr, 0, vdst_initial); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); if (!decoder) { ADD_FAILURE() << "no gfx1250 decoder"; return std::nullopt; @@ -7885,7 +7880,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3PackRejectsDpp) { {words[0], words[1], words[2], kEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -7913,7 +7908,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3PackRejectsLiteral64) { {conversion[0], conversion[1], kLiteralLow, kLiteralHigh, kEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -7932,7 +7927,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3PackUsesCarriersUnderSgprPressure) { rocjitsu::make_gfx1250_image_with_live_sgprs(conversion, rocjitsu::REGISTER_SET_MAX_SGPRS); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -7940,7 +7935,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3PackUsesCarriersUnderSgprPressure) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_cbranch_execz"; }), 1); @@ -7959,7 +7954,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesLiteralCvtF32Fp8E32WithoutClampEmulation) {conversion[0], kLiteral, kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7983,7 +7978,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesCvtF32Fp8E5m3ForA0) { {conversion[0], conversion[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -7991,7 +7986,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EmulatesCvtF32Fp8E5m3ForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "v_cvt_f32_fp8"; }), 0); @@ -8044,7 +8039,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3CompareMasksTargetDeadSgprs) { auto image = rocjitsu::make_gfx1250_image_with_live_sgprs(conversion, kLiveSgprs); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -8053,7 +8048,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3CompareMasksTargetDeadSgprs) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::optional nan_mask; std::optional exp31_mask; std::vector cndmask_predicates; @@ -8090,7 +8085,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3UnpackUsesVgprCarriersUnderSgprPressure) { auto image = rocjitsu::make_gfx1250_image_with_live_sgprs(conversion, live_sgprs); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -8099,7 +8094,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3UnpackUsesVgprCarriersUnderSgprPressure) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_cbranch_execz"; }), 1); @@ -8131,7 +8126,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3SeparatesVectorAndScalarSpillSlots) { auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -8139,7 +8134,7 @@ TEST(BinaryTranslatorE2E, Gfx1250E5m3SeparatesVectorAndScalarSpillSlots) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector store_offsets; std::vector load_offsets; for (const auto &inst : decoded) { @@ -8174,7 +8169,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesWmmaOutsideB0ToA0Profile) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8202,7 +8197,7 @@ TEST(BinaryTranslatorE2E, Gfx1250EqualRevisionsUseIdentityProfile) { for (const rocjitsu::ProcessorRevision revision : {rocjitsu::ProcessorRevision::Gfx1250A0, rocjitsu::ProcessorRevision::Gfx1250B0}) { SCOPED_TRACE(revision == rocjitsu::ProcessorRevision::Gfx1250A0 ? "A0-to-A0" : "B0-to-B0"); - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(revision, revision)); auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -8225,7 +8220,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RejectsA0ToB0Translation) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250A0, rocjitsu::ProcessorRevision::Gfx1250B0)); auto result = translator.translate(source); @@ -8279,7 +8274,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ExpandsEveryDs2VariantForA0) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8332,7 +8327,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2LoadPreservesAliasedAddressUntilBothLoadsIss rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8364,7 +8359,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2ExchangeCyclicOverlapFailsClosed) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8385,7 +8380,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2OversizedStride64OffsetFailsClosed) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8407,7 +8402,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2MovesData1VgprBankToSecondData0Role) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8416,7 +8411,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2MovesData1VgprBankToSecondData0Role) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // The generated bank transitions carry these immediates, and each generated // s_set_vgpr_msb must be preceded by an s_wait_xcnt drain. Collect the generated // transitions dynamically so the assertion does not depend on absolute offsets. @@ -8446,7 +8441,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2AdjustsDestinationBankForSecondLoad) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8455,7 +8450,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Ds2AdjustsDestinationBankForSecondLoad) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // Two generated bank transitions (0x0040, 0x4000), each guarded by s_wait_xcnt. std::vector generated_modes; for (size_t index = 0; index < decoded.size(); ++index) { @@ -8503,7 +8498,7 @@ TEST(SemanticTranslator, Gfx1250ClassifiesLivenessFreeExpandRules) { // absent because they query operand-bank liveness. EXPECT_EQ(liveness_free_rules, expected); - rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, + rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); constexpr auto tensor_mask_clear = @@ -8512,10 +8507,10 @@ TEST(SemanticTranslator, Gfx1250ClassifiesLivenessFreeExpandRules) { cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = 128, .sdst = 125}); constexpr auto v_nop = cdna5::build_vop1(cdna5::kVNopVop1); const auto tensor_clear_inst = - rocjitsu::test_support::decode_one(tensor_mask_clear[0], ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::test_support::decode_one(tensor_mask_clear[0], ROCJITSU_CODE_ARCH_CDNA5); const auto cluster_clear_inst = - rocjitsu::test_support::decode_one(cluster_m0_clear[0], ROCJITSU_CODE_ARCH_GFX1250); - const auto v_nop_inst = rocjitsu::test_support::decode_one(v_nop[0], ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::test_support::decode_one(cluster_m0_clear[0], ROCJITSU_CODE_ARCH_CDNA5); + const auto v_nop_inst = rocjitsu::test_support::decode_one(v_nop[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(tensor_clear_inst, nullptr); ASSERT_NE(cluster_clear_inst, nullptr); ASSERT_NE(v_nop_inst, nullptr); @@ -8612,7 +8607,7 @@ TEST(SemanticTranslator, Gfx1250RegistryHasCompleteDischargeContracts) { EXPECT_EQ(flat_scratch.discharge.disposition, rocjitsu::RewriteDischargeDisposition::Checked); EXPECT_EQ(flat_scratch.discharge.context, rocjitsu::RewriteDischargeContext::Instruction); - rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, + rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); EXPECT_TRUE(translator.supports_rewrite_discharge()); @@ -8622,8 +8617,8 @@ TEST(SemanticTranslator, Gfx1250RegistryHasCompleteDischargeContracts) { EXPECT_FALSE(legacy_translator.supports_rewrite_discharge()); constexpr auto selector_230 = cdna5::build_sop1(cdna5::kSMovB64Sop1, {.ssrc0 = 230, .sdst = 10}); constexpr auto selector_231 = cdna5::build_sop1(cdna5::kSMovB64Sop1, {.ssrc0 = 231, .sdst = 10}); - const auto low = rocjitsu::test_support::decode_one(selector_230[0], ROCJITSU_CODE_ARCH_GFX1250); - const auto high = rocjitsu::test_support::decode_one(selector_231[0], ROCJITSU_CODE_ARCH_GFX1250); + const auto low = rocjitsu::test_support::decode_one(selector_230[0], ROCJITSU_CODE_ARCH_CDNA5); + const auto high = rocjitsu::test_support::decode_one(selector_231[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(low, nullptr); ASSERT_NE(high, nullptr); EXPECT_TRUE(translator.has_instruction_rewrite(*low)); @@ -8742,9 +8737,9 @@ TEST(SemanticTranslator, Gfx1250ResidualChecksRecognizeEveryActionableSourceRule } ASSERT_EQ(samples.size(), residual_rules.size()); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); - rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, + rocjitsu::SemanticTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); for (size_t sample_index = 0; sample_index < samples.size(); ++sample_index) { @@ -8799,7 +8794,7 @@ TEST(BinaryTranslatorE2E, Gfx1250UsesNeutralScaledK128Fp8Bf8Wmma) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -8845,7 +8840,7 @@ TEST(BinaryTranslatorE2E, Gfx1250K128WmmaTranslatesCapturedEncodingWithoutK64Fal {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -8856,7 +8851,7 @@ TEST(BinaryTranslatorE2E, Gfx1250K128WmmaTranslatesCapturedEncodingWithoutK64Fal ASSERT_FALSE(translated.text_sections().empty()); EXPECT_EQ(translated.text_sections()[0]->size(), 6 * sizeof(uint32_t)); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if(decoded, [](const auto &candidate) { return candidate->mnemonic() == @@ -8886,7 +8881,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaRejectsNonVgprMatrixInputs) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -8912,7 +8907,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaRejectsClamp) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -8949,7 +8944,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaAcceptsOperandsThePackedF16PathRejec {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -8978,7 +8973,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F32K128WmmaRejectsScalarAccumulator) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9013,7 +9008,7 @@ TEST(BinaryTranslatorE2E, Gfx1250LowersF16K128Fp8Bf8WmmaThroughF32Scratch) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9023,7 +9018,7 @@ TEST(BinaryTranslatorE2E, Gfx1250LowersF16K128Fp8Bf8WmmaThroughF32Scratch) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); const auto matrix = std::ranges::find_if(decoded, [](const auto &candidate) { return candidate->mnemonic() == "v_wmma_scale_f32_16x16x128_f8f6f4"; }); @@ -9096,7 +9091,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaAcceptsInlineZeroAccumulator) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9105,7 +9100,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaAcceptsInlineZeroAccumulator) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ( std::ranges::count_if( decoded, [](const auto &candidate) { return candidate->mnemonic() == "v_cvt_f32_f16"; }), @@ -9130,7 +9125,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaRejectsNonVgprNonzeroAccumulator) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9153,7 +9148,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaUsesAccumulatorBankAsGeneratedSrc0) {set_vgpr_msb[0], source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9162,7 +9157,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaUsesAccumulatorBankAsGeneratedSrc0) rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector modes; for (const auto &candidate : decoded) { if (candidate->mnemonic() == "s_set_vgpr_msb") @@ -9182,7 +9177,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaAllowsSequentialTuplesToCrossVgprBan {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9191,7 +9186,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaAllowsSequentialTuplesToCrossVgprBan rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector unpack_sources; std::vector packed_destinations; std::vector modes; @@ -9225,7 +9220,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaRejectsOddVgprTuples) { {source_wmma[0], source_wmma[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9244,7 +9239,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaUsesCarrierUnderSgprPressure) { rocjitsu::make_gfx1250_image_with_live_sgprs(source_wmma, rocjitsu::REGISTER_SET_MAX_SGPRS); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9253,7 +9248,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaUsesCarrierUnderSgprPressure) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ( std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "v_readfirstlane_b32_e32"; }), @@ -9286,7 +9281,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaUsesSpillBackedScratchWhenVgprsAreFu auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -9294,7 +9289,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaUsesSpillBackedScratchWhenVgprsAreFu rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "scratch_store_b32"; }), 9); @@ -9336,7 +9331,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaLoweringMatchesUnloweredExecution) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9349,7 +9344,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaLoweringMatchesUnloweredExecution) { reinterpret_cast(translated.text_sections()[0]->data()); const size_t text_word_count = translated.text_sections()[0]->size() / sizeof(uint32_t); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::vector body_words; @@ -9370,7 +9365,7 @@ TEST(BinaryTranslatorE2E, Gfx1250F16K128WmmaLoweringMatchesUnloweredExecution) { rocjitsu::amdgpu::GpuMemory gpu_mem("gfx1250_f16_k128_diff_mem"); rocjitsu::amdgpu::L2Cache l2("gfx1250_f16_k128_diff_l2"); rocjitsu::amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -9562,7 +9557,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MasksM0AroundOffFormClusterLoadForA0) { {cluster[0], cluster[1], cluster[2], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -9570,7 +9565,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MasksM0AroundOffFormClusterLoadForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // The load stays a cluster load (no demotion to global_load). EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "cluster_load_b32"; }), @@ -9593,7 +9588,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MasksM0AroundOffFormClusterLoadForA0) { EXPECT_TRUE(cleared_m0) << "off-form cluster load must still set M0 (125) = inline 0 (128)"; rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -9611,7 +9606,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MasksM0AroundSaddrClusterLoadForA0) { {cluster[0], cluster[1], cluster[2], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -9619,7 +9614,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MasksM0AroundSaddrClusterLoadForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "cluster_load_b64"; }), 1); @@ -9652,7 +9647,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MasksM0AroundSaddrClusterLoadForA0) { EXPECT_TRUE(restored_m0) << "no s_mov_b32 restores M0 (125) from the saved scratch"; rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -9672,7 +9667,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadsUseVgprCarrierUnderSgprPressure) { rocjitsu::make_gfx1250_image_with_live_sgprs(cluster, rocjitsu::REGISTER_SET_MAX_SGPRS); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9681,7 +9676,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadsUseVgprCarrierUnderSgprPressure) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_cbranch_execz"; }), 0); @@ -9733,7 +9728,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadFailsClosedWithoutExecIndependentCar auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); @@ -9768,7 +9763,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DischargesEveryClusterLoadVariant) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9780,7 +9775,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DischargesEveryClusterLoadVariant) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ( std::ranges::count_if( decoded, [&](const auto &inst) { return inst->mnemonic() == test_case.mnemonic; }), @@ -9798,7 +9793,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadPreservesGuestM0ClearWithoutRestore) rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -9817,7 +9812,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadPreservesGuestM0ClearWithoutRestore) EXPECT_EQ(target_words[4], kGfx1250SEndpgm); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -9842,7 +9837,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadDoesNotReuseNonzeroM0Write) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -9865,7 +9860,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadDoesNotReuseNonzeroM0Write) { EXPECT_EQ(target_words[8], kGfx1250SEndpgm); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -9887,7 +9882,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadDoesNotReuseZeroWriteToOtherSgpr) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -9925,7 +9920,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadDoesNotReuseM0ClearBypassedByBranch) rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -9954,7 +9949,7 @@ TEST(BinaryTranslatorE2E, Gfx1250ClusterLoadDoesNotReuseM0ClearBypassedByBranch) EXPECT_EQ(target_words[11], kGfx1250SEndpgm); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -9972,7 +9967,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MaterializesDsAddtidAddressForA0) { {addtid[0], addtid[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -9980,7 +9975,7 @@ TEST(BinaryTranslatorE2E, Gfx1250MaterializesDsAddtidAddressForA0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "ds_load_addtid_b32"; }), 0); @@ -10096,7 +10091,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AdoptsDeviceFunctionBodyReachedByNoScope) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -10133,7 +10128,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AdoptsDeviceFunctionBodyHeldByAnUnnamedPointerS << "the slot must not qualify as a table, or this covers the same path as the test above"; rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -10173,7 +10168,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AllowsUnprovableCallWhenOnlyProducerIsAnAnonymo << "the slot must stay anonymous, or the producer comes from table discovery instead"; rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -10240,7 +10235,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RepointsPcRelativeDataRangeBoundsAfterRelocatio rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -10307,7 +10302,7 @@ TEST(BinaryTranslatorE2E, Gfx1250FailsClosedOnExcludedBarrierSignalIsfirst) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10328,7 +10323,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RejectsLiteralSpellingOfExcludedBarrierId) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -10352,7 +10347,7 @@ TEST(BinaryTranslatorE2E, Gfx1250FailsClosedOnReservedBarrierSignalSelector) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -10388,7 +10383,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesRemainingBarrierSignalIsfirstFormsForA0) {barrier[0], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10426,7 +10421,7 @@ TEST(BinaryTranslatorE2E, Gfx1250WrapsBareF8f6f4WmmaInNeutralScaleForA0) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10435,7 +10430,7 @@ TEST(BinaryTranslatorE2E, Gfx1250WrapsBareF8f6f4WmmaInNeutralScaleForA0) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_GE(decoded.size(), 3u); EXPECT_EQ(decoded[0]->mnemonic(), "v_wmma_scale_f32_16x16x128_f8f6f4"); EXPECT_EQ(decoded[0]->size(), 4 * static_cast(sizeof(uint32_t))); @@ -10487,7 +10482,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesSupportedK64LowPrecisionWmmaAndAppends rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()) << c.name; rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); struct TraceClassification { @@ -10548,7 +10543,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DoesNotCreditTrailingWaitAcrossDependentWmma) { {producer[0], producer[1], consumer[0], consumer[1], completion_wait[0], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); @@ -10596,7 +10591,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CompletionWaitCreditChecksOnlyVaVdst) { {wmma[0], wmma[1], source_wait[0], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); @@ -10642,7 +10637,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CreditsWaitAcrossCanonicalBankTransitionScaffol upper_bank_wmma[1], completion_wait[0], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); @@ -10651,7 +10646,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CreditsWaitAcrossCanonicalBankTransitionScaffol : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_wait_alu"; }), 1); @@ -10675,7 +10670,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CreditsPhysicallyAdjacentWaitAcrossBasicBlockBo {branch_to_wait[0], wmma[0], wmma[1], completion_wait[0], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); @@ -10685,7 +10680,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CreditsPhysicallyAdjacentWaitAcrossBasicBlockBo rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_wait_alu"; }), 1); @@ -10709,7 +10704,7 @@ TEST(BinaryTranslatorE2E, Gfx1250CopiesA0CompatibleLowPrecisionSwmmac) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10737,7 +10732,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Allows32BitFlatScratchBaseHiSource) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10768,8 +10763,8 @@ TEST(RjCodeTranslateCApi, RejectsSameArchGfx1250) { ASSERT_TRUE(source.co->is_valid()); rj_code_dbt_options_t options{}; - options.guest_arch = ROCJITSU_CODE_ARCH_GFX1250; - options.host_arch = ROCJITSU_CODE_ARCH_GFX1250; + options.guest_arch = ROCJITSU_CODE_ARCH_CDNA5; + options.host_arch = ROCJITSU_CODE_ARCH_CDNA5; rj_code_object_t *translated = nullptr; EXPECT_NE(rj_code_translate(&source, &options, &translated), ROCJITSU_STATUS_SUCCESS); EXPECT_EQ(translated, nullptr); @@ -10786,7 +10781,7 @@ TEST(BinaryTranslatorEnforcesGfx1250Revisions, SameArchUnspecifiedRevisionFailsC rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5); auto result = translator.translate(source); EXPECT_FALSE(result.ok()); EXPECT_EQ(result.elf_bytes, image) << "fail-closed must leave the object unchanged"; @@ -10804,7 +10799,7 @@ TEST(BinaryTranslatorEnforcesGfx1250Revisions, TranslatesGfx1250B0ToA0WithRevisi ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10813,7 +10808,7 @@ TEST(BinaryTranslatorEnforcesGfx1250Revisions, TranslatesGfx1250B0ToA0WithRevisi rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "cluster_load_b64"; }), 1); @@ -10829,7 +10824,7 @@ TEST(BinaryTranslatorE2E, Gfx1250GeneratedVgprMsbTransitionsCarryPreviousState) {original_mode[0], 1u << 2, addtid[0], addtid[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -10837,7 +10832,7 @@ TEST(BinaryTranslatorE2E, Gfx1250GeneratedVgprMsbTransitionsCarryPreviousState) : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // The guest MODE write opens the block, so its separation rule puts two V_NOPs // ahead of it before anything this test is about. ASSERT_GE(decoded.size(), 7u); @@ -10891,7 +10886,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AddtidStoreUsesSpillBackedScratchWhenVgprsAreFu auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -10899,7 +10894,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AddtidStoreUsesSpillBackedScratchWhenVgprsAreFu rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "scratch_store_b32"; }), 1); @@ -10985,7 +10980,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SpillBackedRulesFailClosedForDynamicStackKernel auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); @@ -11040,7 +11035,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SpillWaitsForOutstandingVgprProducer) { auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -11048,7 +11043,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SpillWaitsForOutstandingVgprProducer) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::optional pending_load_index; std::optional wait_idle_index; std::optional scratch_store_index; @@ -11086,7 +11081,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DeadScratchWaitsForOutstandingVgprProducer) { {pending_load[0], pending_load[1], addtid[0], addtid[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11095,7 +11090,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DeadScratchWaitsForOutstandingVgprProducer) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::optional pending_load_index; std::optional wait_idle_index; std::optional scratch_write_index; @@ -11136,7 +11131,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AddtidLoadWaitsForOutstandingVgprProducer) { {pending_load[0], pending_load[1], addtid[0], addtid[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11145,7 +11140,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AddtidLoadWaitsForOutstandingVgprProducer) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::optional wait_idle_index; std::optional scratch_write_index; for (size_t index = 0; index < decoded.size(); ++index) { @@ -11183,7 +11178,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AddtidStoreModeUsesSrc1BankNotSrc0) { {original_mode[0], kModeLiteral, addtid[0], addtid[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11191,7 +11186,7 @@ TEST(BinaryTranslatorE2E, Gfx1250AddtidStoreModeUsesSrc1BankNotSrc0) { : result.diagnostics.front().message); rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // Assert the full generated s_set_vgpr_msb sequence, not just the store mode's // low byte, so this also catches a regression that drops the previous-mode @@ -11319,7 +11314,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Iu8WmmaSpacingCreditsOnlySameBlockCanonicalVNop rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11351,7 +11346,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Iu8WmmaSpacingCreditsOnlySameBlockCanonicalVNop expected_words); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -11376,7 +11371,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Iu8WmmaDoesNotCreditVNopsAcrossBlockBoundary) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11395,7 +11390,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Iu8WmmaDoesNotCreditVNopsAcrossBlockBoundary) { EXPECT_EQ(target_words[21], kGfx1250SEndpgm); rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second_result = verifier.translate(translated); @@ -11418,7 +11413,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadAlwaysClearsDynamicMulticastMask) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11461,7 +11456,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadUsesHighDeadSgprUnderCompilerPressure source_tensor, rocjitsu::REGISTER_SET_ALLOCATABLE_SGPRS); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11470,7 +11465,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadUsesHighDeadSgprUnderCompilerPressure rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if( decoded, [](const auto &inst) { return inst->mnemonic() == "s_cbranch_execz"; }), 0); @@ -11520,7 +11515,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorScratchWaitsForOutstandingSgprProducer) { kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11529,7 +11524,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorScratchWaitsForOutstandingSgprProducer) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::optional pending_load_index; std::optional wait_idle_index; std::optional scratch_write_index; @@ -11567,7 +11562,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadFailsClosedWhenEverySgprIsLive) { rocjitsu::make_gfx1250_image_with_live_sgprs(source_tensor, rocjitsu::REGISTER_SET_MAX_SGPRS); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11595,7 +11590,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadPreservesGuestMaskClearWithoutRestore auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.verify_rewrite_discharge = true; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -11633,7 +11628,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadDoesNotReuseNonzeroMaskWrite) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto first = translator.translate(source); @@ -11680,7 +11675,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadDoesNotReuseClearOfDifferentDescripto rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11722,7 +11717,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TensorLoadDoesNotReuseMaskPrefixBypassedByBranc rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11768,7 +11763,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularWmmaScaleEncodesSrc2AndWaitsForCompletio rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11821,7 +11816,7 @@ TEST(BinaryTranslatorE2E, Gfx1250FloatingScaledWmmaRejectsNonzeroCmFields) { {prefix[0], prefix[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11842,7 +11837,7 @@ TEST(BinaryTranslatorE2E, Gfx1250BareFloatingWmmaRejectsClamp) { {matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11865,7 +11860,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesVop3DppExtensionWord) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -11894,7 +11889,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SplitsRegularScaleFp4AcrossMForA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -11959,7 +11954,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4RejectsEveryDestructiveUpperInpu rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12000,7 +11995,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4RejectsScaleSourceOverlap) { {set_vgpr_msb[0], scale[0], scale[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12024,7 +12019,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4AcceptsScalarAndInlineScaleSourc rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12059,7 +12054,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4AdjustsUpperCAndDestinationBanks {set_vgpr_msb[0], scale[0], scale[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12082,7 +12077,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4AdjustsUpperCAndDestinationBanks EXPECT_EQ(upper.src2, 256u + 4u); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector modes; for (const auto &inst : decoded) { if (inst->mnemonic() == "s_set_vgpr_msb") { @@ -12104,7 +12099,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4AdjustsUpperABank) { {scale[0], scale[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12125,7 +12120,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4AdjustsUpperABank) { EXPECT_EQ(upper.src0, 256u + 4u); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector modes; for (const auto &inst : decoded) { if (inst->mnemonic() == "s_set_vgpr_msb") { @@ -12148,7 +12143,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RegularScaleFp4RejectsBank3UpperHalfOverflow) { {set_vgpr_msb[0], scale[0], scale[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12179,7 +12174,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SplitsScale16Fp4AcrossMOnlyForA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12247,7 +12242,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16Fp4AcceptsScalarAndInlineScaleSources) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12306,7 +12301,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16RejectsMisalignedOrOutOfRangeVgprPairs) {scale16[0], scale16[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12353,7 +12348,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16Fp4RejectsEveryDestructiveUpperInputOver {scale16[0], scale16[1], matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12379,7 +12374,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16Fp4AdjustsUpperCAndDestinationBanks) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12402,7 +12397,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16Fp4AdjustsUpperCAndDestinationBanks) { EXPECT_EQ(upper.src2, 256u + 4u); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector modes; for (const auto &inst : decoded) { if (inst->mnemonic() == "s_set_vgpr_msb") { @@ -12427,7 +12422,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16Fp4RejectsBank3UpperHalfOverflow) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12457,7 +12452,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesNativeM16Scale16ForA0) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -12480,7 +12475,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesNativeM16Scale16ForA0) { EXPECT_EQ(target_words[5], kGfx1250SEndpgm); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); EXPECT_EQ(std::ranges::count_if(decoded, [](const auto &candidate) { return candidate->mnemonic() == @@ -12514,7 +12509,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16M32DoesNotNeedScratchWhenVgprsAreFull) { auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -12526,7 +12521,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16M32DoesNotNeedScratchWhenVgprsAreFull) { reinterpret_cast(translated.text_sections()[0]->data()); const size_t target_word_count = translated.text_sections()[0]->size() / sizeof(uint32_t); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); struct ScratchAccess { size_t word_offset; @@ -12599,7 +12594,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Scale16M32IgnoresUnavailableScratchSpillSpace) auto options = gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0); options.debug_min_free_vgpr = 256; - rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + rocjitsu::BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); @@ -12619,7 +12614,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4RejectsNonZeroClampForA0) { {matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12652,7 +12647,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SplitsStandalone32x16Fp4IntoScaledHalvesForA0) rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -12662,7 +12657,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SplitsStandalone32x16Fp4IntoScaledHalvesForA0) rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // The B0-only M=32 opcode must be gone, replaced by two scaled M=16 forms. EXPECT_EQ( std::ranges::count_if( @@ -12733,7 +12728,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4AdjustsUpperABank) { {matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12756,7 +12751,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4AdjustsUpperABank) { EXPECT_EQ(upper.src1, 256u + 32u) << "matrix B is not sliced and keeps its bank"; const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); std::vector modes; for (size_t index = 0; index < decoded.size(); ++index) { if (decoded[index]->mnemonic() != "s_set_vgpr_msb") @@ -12796,7 +12791,7 @@ TEST(BinaryTranslatorE2E, Gfx1250FailsClosedOnStandalone32x16Fp4NonVgprMatrixFor {matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12820,7 +12815,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4PreservesInlineMatrixCForA0) {matrix[0], matrix[1], kGfx1250SEndpgm}); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12876,7 +12871,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4SplitMatchesUnsplitExecution) rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -12889,7 +12884,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4SplitMatchesUnsplitExecution) reinterpret_cast(translated.text_sections()[0]->data()); const size_t text_word_count = translated.text_sections()[0]->size() / sizeof(uint32_t); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); // Collect the translated body, stopping at the terminator. @@ -12914,7 +12909,7 @@ TEST(BinaryTranslatorE2E, Gfx1250Standalone32x16Fp4SplitMatchesUnsplitExecution) rocjitsu::amdgpu::GpuMemory gpu_mem("gfx1250_fp4_split_diff_mem"); rocjitsu::amdgpu::L2Cache l2("gfx1250_fp4_split_diff_l2"); rocjitsu::amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -13039,11 +13034,11 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoversAddNcU64PcBuilder) { constexpr uint32_t kGfx1250SEndpgm = 0xBFB00000u; const std::vector words = { - rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, kGfx1250SAddNcU64Opcode, kPcSreg, + rocjitsu::build_s_getpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, kGfx1250SAddNcU64Opcode, kPcSreg, kPcSreg, kLiteralOperand), kTargetOffset - sizeof(uint32_t), - rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_GFX1250), + rocjitsu::build_s_setpc_b64(kPcSreg, ROCJITSU_CODE_ARCH_CDNA5), kGfx1250SNop, kGfx1250SEndpgm, }; @@ -13052,7 +13047,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoversAddNcU64PcBuilder) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13086,15 +13081,15 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteKeepsTheXcntDrain) { .target_recovery_end_offset = 4 * kWord}); const auto patched = - rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(patched.ok) << patched.message; std::array replacement{}; std::memcpy(replacement.data(), text.data() + kWord, replacement.size() * sizeof(uint32_t)); - EXPECT_EQ(replacement[0], rocjitsu::build_s_wait_xcnt(ROCJITSU_CODE_ARCH_GFX1250).value()); + EXPECT_EQ(replacement[0], rocjitsu::build_s_wait_xcnt(ROCJITSU_CODE_ARCH_CDNA5).value()); EXPECT_EQ(replacement[1], - rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, cdna5::kSAddNcU64Sop2, - kPcSreg, kPcSreg, kLiteralOperand)); + rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSAddNcU64Sop2, kPcSreg, + kPcSreg, kLiteralOperand)); // s_get_pc_i64 leaves the address of the next instruction, and the target is // the block at 4 * kWord. EXPECT_EQ(replacement[2], 3 * kWord); @@ -13120,7 +13115,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteOmitsAnUnneededXcntDrain .target_recovery_end_offset = 4 * kWord}); const auto patched = - rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(patched.ok) << patched.message; // The point of this case is that no XCNT drain precedes the add -- the first word of the range @@ -13129,7 +13124,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteOmitsAnUnneededXcntDrain // which models only that encoding, can still see this builder on a later translation pass. uint32_t first = 0; std::memcpy(&first, text.data() + kWord, sizeof(first)); - EXPECT_EQ(first, rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, cdna5::kSAddNcU64Sop2, + EXPECT_EQ(first, rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSAddNcU64Sop2, kPcSreg, kPcSreg, kLiteral64Operand)); } @@ -13160,7 +13155,7 @@ TEST(BinaryTranslatorE2E, RecoveredBuilderReuseRejectsDisagreeingXcntDrain) { .target_recovery_end_offset = 4 * kWord}); const auto patched = - rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); EXPECT_FALSE(patched.ok); EXPECT_NE(patched.message.find("incompatible replacements"), std::string::npos) << patched.message; @@ -13174,7 +13169,7 @@ TEST(BinaryTranslatorE2E, Gfx1250IgnoresUndecodablePaddingAfterTerminator) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13192,7 +13187,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesFallthroughIntoZeroPadding) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13202,7 +13197,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesFallthroughIntoZeroPadding) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // Only the first two instructions are pinned: the relocated body may be followed by target-side // alignment padding, which decodes as additional instructions. ASSERT_GE(decoded.size(), 2u); @@ -13235,7 +13230,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SeparatesModeWriteWithLeadingVNops) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13245,7 +13240,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SeparatesModeWriteWithLeadingVNops) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(decoded.size(), 8u); EXPECT_EQ(decoded[0]->mnemonic(), "v_nop_e32"); @@ -13268,7 +13263,7 @@ TEST(BinaryTranslatorE2E, Gfx1250SeparatesModeWriteWithLeadingVNops) { // Separation already present must be counted, or a repeated translation would keep prepending. rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second = verifier.translate(translated); @@ -13294,7 +13289,7 @@ TEST(BinaryTranslatorE2E, Gfx1250IgnoresLeadingVNopsAcrossABlockBoundary) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13304,7 +13299,7 @@ TEST(BinaryTranslatorE2E, Gfx1250IgnoresLeadingVNopsAcrossABlockBoundary) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(decoded.size(), 7u) << "the write must receive a fresh pair, not count the skipped ones"; @@ -13337,7 +13332,7 @@ TEST(BinaryTranslatorE2E, Gfx1250IgnoresLeadingVNopsAcrossABlockBoundary) { // Retargeting moved the write, so this is the case where a second pass could disagree with the // first about which V_NOPs belong to the write's own block. rocjitsu::BinaryTranslator verifier( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto second = verifier.translate(translated); @@ -13358,7 +13353,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesSetupFallthroughIntoZeroPadding) { ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13368,7 +13363,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesSetupFallthroughIntoZeroPadding) { rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // The MODE write opens its block, so its separation rule contributes both V_NOPs here. ASSERT_EQ(decoded.size(), 4u) << "the synthesized endpgm must be the only instruction after the stub body"; @@ -13400,7 +13395,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesPrefetchSetupFallthroughIntoZeroPaddi ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13410,7 +13405,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TerminatesPrefetchSetupFallthroughIntoZeroPaddi rocjitsu::AmdGpuCodeObject translated(result.elf_bytes.data(), result.elf_bytes.size()); ASSERT_FALSE(translated.text_sections().empty()); const auto decoded = - decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*translated.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); // The prologue's own V_NOP counts toward the MODE write's separation, so it needs // only one more rather than a fresh pair. ASSERT_EQ(decoded.size(), 5u) @@ -13438,14 +13433,14 @@ TEST(BinaryTranslatorE2E, Gfx1250MaterializesSectionFinalClangUnreachableKernelS ASSERT_TRUE(source.is_valid()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto first = translator.translate(source); ASSERT_TRUE(first.ok()) << (first.diagnostics.empty() ? "" : first.diagnostics.front().message); rocjitsu::AmdGpuCodeObject first_output(first.elf_bytes.data(), first.elf_bytes.size()); const auto decoded = - decode_text_instructions(*first_output.text_sections()[0], ROCJITSU_CODE_ARCH_GFX1250); + decode_text_instructions(*first_output.text_sections()[0], ROCJITSU_CODE_ARCH_CDNA5); ASSERT_EQ(decoded.size(), 4u); EXPECT_EQ(decoded[0]->mnemonic(), "v_nop_e32"); EXPECT_EQ(decoded[1]->mnemonic(), "v_nop_e32"); @@ -13526,7 +13521,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesSourceInstPrefSize) { rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13567,7 +13562,7 @@ TEST(BinaryTranslatorE2E, Gfx1250PreservesDisabledInstPrefSizeFromGfx10PlusSourc rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); auto result = translator.translate(source); @@ -13603,8 +13598,8 @@ TEST(KernelDescriptorTranslator, Gfx1250UsesWave32SixteenVgprGranularity) { rocjitsu::test_support::write_kernel_descriptor_for_test(image.data() + rodata->sectionOffset(), descriptor); - rocjitsu::KernelDescriptorTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, - ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::KernelDescriptorTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, + ROCJITSU_CODE_ARCH_CDNA5); const auto translations = translator.translate_image( image, text->sectionOffset(), text->size(), rocjitsu::KernelDescriptorTranslationOptions{}); @@ -13636,8 +13631,8 @@ TEST(KernelDescriptorTranslator, Gfx1250AcceptsLdsAboveTcpPartitionSize) { offsetof(rocjitsu::test_support::TestKernelDescriptor, group_segment_fixed_size), kStaticLdsBytes); - rocjitsu::KernelDescriptorTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, - ROCJITSU_CODE_ARCH_GFX1250); + rocjitsu::KernelDescriptorTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, + ROCJITSU_CODE_ARCH_CDNA5); const auto translations = translator.translate_image( image, text->sectionOffset(), text->size(), rocjitsu::KernelDescriptorTranslationOptions{}); @@ -14034,7 +14029,7 @@ translate_gfx1250_indexed_flat_scratch_destination(uint32_t gpr_index_control) { auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); return translator.translate(source); @@ -14050,7 +14045,7 @@ translate_gfx1250_b0_to_a0_words(std::vector words, rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); if (trace_callback) @@ -14302,7 +14297,7 @@ TEST(BinaryTranslatorE2E, Gfx1250StagesFlatScratchBaseInDestinationWhenSgprsAreL auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -14325,7 +14320,7 @@ TEST(BinaryTranslatorE2E, Gfx1250StagesFlatScratchBaseInDestinationWhenSgprsAreL << "the selector read must wait for the preceding s102 producer"; EXPECT_NE(std::ranges::find(low_move + 1, out + out_words, high[0]), out + out_words); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); bool found_rewritten_add = false; for (size_t offset = 0; offset < out_words;) { @@ -14364,7 +14359,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DestinationStagingExecutesInMatchingNonzeroBank auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -14379,7 +14374,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DestinationStagingExecutesInMatchingNonzeroBank rocjitsu::amdgpu::GpuMemory gpu_mem("gfx1250_flat_scratch_stage_mem"); rocjitsu::amdgpu::L2Cache l2("gfx1250_flat_scratch_stage_l2"); rocjitsu::amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 1024; @@ -14395,7 +14390,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DestinationStagingExecutesInMatchingNonzeroBank cu->write_vgpr(vb + 2, 0, 0u); cu->write_vgpr(vb + 3, 0, 0u); - auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = rocjitsu::Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (size_t offset = 0; offset < translated_count;) { std::unique_ptr inst(decode_valid(*decoder, translated_words + offset)); @@ -14429,7 +14424,7 @@ TEST(BinaryTranslatorE2E, Gfx1250DestinationStagingRejectsMismatchedBanks) { auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -14486,7 +14481,7 @@ TEST(BinaryTranslatorE2E, Gfx1250FailsClosedWhenFlatScratchTemporariesAlias) { auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text(words); rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); rocjitsu::BinaryTranslator translator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); const auto result = translator.translate(source); @@ -14715,7 +14710,7 @@ translate_gfx1250_b0_to_a0_result(rocjitsu::BinaryTranslator &translator, [[nodiscard]] rocjitsu::BinaryTranslator make_gfx1250_b0_to_a0_translator() { return rocjitsu::BinaryTranslator( - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, rocjitsu::ProcessorRevision::Gfx1250A0)); } diff --git a/emulation/rocjitsu/tests/dbt/translate_test.cpp b/emulation/rocjitsu/tests/dbt/translate_test.cpp index f8266eb35ea2..cfa810970717 100644 --- a/emulation/rocjitsu/tests/dbt/translate_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_test.cpp @@ -759,7 +759,7 @@ TEST(BinaryTranslatorE2E, EmptyTextSameArchIsSuccessfulNoOp) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_TRUE(result.ok()); @@ -797,7 +797,7 @@ TEST(BinaryTranslatorE2E, EmptyTextCrossArchStillFails) { AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_RDNA4); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_RDNA4); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -829,7 +829,7 @@ TEST(BinaryTranslatorE2E, EmptyTextGfx1250StillRequiresRevisions) { AmdGpuCodeObject source(image.data(), image.size()); ASSERT_TRUE(source.is_valid()); - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -846,7 +846,7 @@ TEST(BinaryTranslatorE2E, EmptyTextGfx1250StillRejectsA0ToB0) { BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250A0; options.output_revision = ProcessorRevision::Gfx1250B0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -866,7 +866,7 @@ TEST(BinaryTranslatorE2E, Gfx1250InvalidInstructionIsDiagnosedAndLeavesObjectUnc BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -888,7 +888,7 @@ TEST(BinaryTranslatorE2E, DescriptorlessExecutableTextIsSuccessfulNoOp) { BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_TRUE(result.ok()); @@ -912,7 +912,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeCannotVerifySkippedKernelStubs) { options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; options.skip_failed_kernels = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1136,7 +1136,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeRejectsIdentityOutputWithResidualTrigg options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1167,7 +1167,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeRejectsNonDwordTextTail) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1194,7 +1194,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeRejectsTruncatedMultiwordInstruction) options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1219,7 +1219,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeRejectsResidualFlatScratchBaseSelector options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(code_object); EXPECT_FALSE(result.ok()); @@ -1272,7 +1272,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TranslationIgnoresUnreferencedVisibleTextSymbol BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1330,7 +1330,7 @@ TEST(BinaryTranslatorE2E, Gfx1250TranslationIgnoresUnreferencedSymbolInsideInstr BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1387,7 +1387,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresUnreferencedLocalTextLabel) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1441,7 +1441,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeHonorsRelocationBackedLocalTextEntry) options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1504,7 +1504,7 @@ TEST(BinaryTranslatorE2E, PreservesEtRelNotypeAbs64EntryPolicy) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(has_error_containing(result, DiagnosticKind::Legalization, @@ -1544,7 +1544,7 @@ TEST(BinaryTranslatorE2E, PreservesExplicitTargetStaticRelocationPolicy) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1597,7 +1597,7 @@ TEST(BinaryTranslatorE2E, ExplicitTargetNonAbs64FunctionReferenceCreatesTextEntr options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1662,7 +1662,7 @@ TEST(BinaryTranslatorE2E, RejectsDynamicNoneBeforeResolvingSymbolMetadata) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1698,7 +1698,7 @@ TEST(BinaryTranslatorE2E, RejectsDynamicNoneBeforeInspectingInvalidPlace) { BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1739,7 +1739,7 @@ TEST(BinaryTranslatorE2E, IgnoresTargetlessShtRelNoneLikeRocr) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1802,7 +1802,7 @@ TEST(BinaryTranslatorE2E, IgnoresExplicitTargetNoneRelocationToTextSymbol) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1823,7 +1823,7 @@ TEST(BinaryTranslatorE2E, RejectsUnsupportedSymbolRelocationsToText) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1844,7 +1844,7 @@ TEST(BinaryTranslatorE2E, RejectsUnsupportedRelocationBackedTextSymbolTypes) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -1889,7 +1889,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeDoesNotPromoteRelocationBackedNonEntry options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_TRUE(result.ok()); @@ -1928,7 +1928,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresExplicitNonAllocatedRelocation) options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -1969,7 +1969,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresMalformedUnreferencedSymbolTabl options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -2003,7 +2003,7 @@ TEST(BinaryTranslatorE2E, RejectsAllocatedExecutableNobitsSections) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2047,7 +2047,7 @@ TEST(BinaryTranslatorE2E, UsesActualTextSectionIndexForRelocationBackedEntries) BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2079,7 +2079,7 @@ TEST(BinaryTranslatorE2E, TranslationFailsClosedOnMalformedAllocatedRelocation) BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2139,7 +2139,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresUnreferencedVisibleSymbolMetada options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -2167,7 +2167,7 @@ TEST(BinaryTranslatorE2E, TranslationFailsClosedOnMultipleExecutableSections) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2204,7 +2204,7 @@ TEST(BinaryTranslatorE2E, TranslationRejectsSoleExecutableSectionNotNamedText) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2233,7 +2233,7 @@ TEST(BinaryTranslatorE2E, TranslationRejectsMalformedNameOnAdditionalExecutableS options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2260,7 +2260,7 @@ TEST(BinaryTranslatorE2E, TranslationRejectsMalformedNameOnSoleExecutableSection options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2310,7 +2310,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeIgnoresUnreferencedVisibleTextSymbolEn options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); ASSERT_TRUE(result.ok()) << (result.diagnostics.empty() ? "" @@ -2377,7 +2377,7 @@ TEST(BinaryTranslatorE2E, RewriteDischargeDoesNotCreditPredecessorAcrossRelative options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2429,7 +2429,7 @@ TEST(BinaryTranslatorE2E, RejectsRelocationBackedEntryOutsideKernelTranslationSc BinaryTranslatorOptions options; options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); @@ -2533,7 +2533,7 @@ TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { }; // Matching layout: carried verbatim, both the wide INST_PREF_SIZE and NAMED_BAR_CNT. - const auto same_layout = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); + const auto same_layout = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(same_layout.has_value()); EXPECT_EQ(*same_layout, source_rsrc3); EXPECT_EQ(AMDHSA_BITS_GET(*same_layout, COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE), 107u); @@ -2541,7 +2541,7 @@ TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { // GFX10 targets have no INST_PREF_SIZE and no IMAGE_OP; the GFX12 word must not be inherited. for (const rj_code_arch_t gfx10 : {ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2}) { - const auto rebuilt = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, gfx10); + const auto rebuilt = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA5, gfx10); ASSERT_TRUE(rebuilt.has_value()); EXPECT_NE(*rebuilt, source_rsrc3); EXPECT_EQ(AMDHSA_BITS_GET(*rebuilt, COMPUTE_PGM_RSRC3_GFX10_PLUS_INST_PREF_SIZE), 0u) @@ -2549,7 +2549,7 @@ TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { } // A GFX9/CDNA source encodes ACCUM_OFFSET here, so it is rebuilt for a GFX12 target. - const auto from_cdna = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_GFX1250); + const auto from_cdna = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(from_cdna.has_value()); EXPECT_NE(*from_cdna, source_rsrc3); EXPECT_EQ(AMDHSA_BITS_GET(*from_cdna, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 0u); @@ -2585,7 +2585,7 @@ TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_TCP_SPLIT, 5u); AMDHSA_BITS_SET(gfx125_rsrc3, COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR, 1u); source_rsrc3 = gfx125_rsrc3; - const auto to_gfx120 = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_RDNA4); + const auto to_gfx120 = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_RDNA4); ASSERT_TRUE(to_gfx120.has_value()); EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_NAMED_BAR_CNT), 0u) << "bits 21:14 are reserved on GFX120 and must not inherit GFX125 state"; @@ -2593,7 +2593,7 @@ TEST(CodeObjectPatcher, Rsrc3IsCarriedOnlyBetweenMatchingLayouts) { EXPECT_EQ(AMDHSA_BITS_GET(*to_gfx120, COMPUTE_PGM_RSRC3_GFX125_ENABLE_DYNAMIC_VGPR), 0u); // GFX125 -> GFX125 keeps all of it. - const auto gfx125_same = patched_rsrc3(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250); + const auto gfx125_same = patched_rsrc3(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(gfx125_same.has_value()); EXPECT_EQ(*gfx125_same, gfx125_rsrc3); } @@ -2758,7 +2758,7 @@ TEST(CodeObjectPatcher, AppliesArchSpecificWgpModeBit) { EXPECT_EQ(AMDHSA_BITS_GET(*rdna4_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED), 1u); EXPECT_EQ(AMDHSA_BITS_GET(*rdna4_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS), 1u); - const auto gfx1250_rsrc1 = patched_rsrc1(ROCJITSU_CODE_ARCH_GFX1250); + const auto gfx1250_rsrc1 = patched_rsrc1(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_TRUE(gfx1250_rsrc1.has_value()); EXPECT_EQ(AMDHSA_BITS_GET(*gfx1250_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE), 0u); EXPECT_EQ(AMDHSA_BITS_GET(*gfx1250_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED), 1u); @@ -3383,7 +3383,7 @@ TEST(BinaryTranslatorE2E, RejectsMalformedRelocationWithNonzeroNullTarget) { options.input_revision = ProcessorRevision::Gfx1250B0; options.output_revision = ProcessorRevision::Gfx1250A0; options.verify_rewrite_discharge = true; - BinaryTranslator translator(ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_GFX1250, 0, options); + BinaryTranslator translator(ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, options); const auto result = translator.translate(source); EXPECT_FALSE(result.ok()); diff --git a/emulation/rocjitsu/tests/decode_execute_benchmark.cpp b/emulation/rocjitsu/tests/decode_execute_benchmark.cpp index 851394034040..7e8615512b86 100644 --- a/emulation/rocjitsu/tests/decode_execute_benchmark.cpp +++ b/emulation/rocjitsu/tests/decode_execute_benchmark.cpp @@ -255,7 +255,7 @@ TEST(DecodeExecuteBenchmark, Rdna4) { } TEST(DecodeExecuteBenchmark, Gfx1250) { - run_benchmark(ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", + run_benchmark(ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", reinterpret_cast(cdna5::test_data::ENCODINGS), cdna5::test_data::NUM_ENCODINGS); } diff --git a/emulation/rocjitsu/tests/decode_smoke_test.cpp b/emulation/rocjitsu/tests/decode_smoke_test.cpp index 12d2568a01ec..65a469346e41 100644 --- a/emulation/rocjitsu/tests/decode_smoke_test.cpp +++ b/emulation/rocjitsu/tests/decode_smoke_test.cpp @@ -98,10 +98,10 @@ TEST(OperandLayoutTest, DeferredSelectorStateFitsExistingPadding) { } TEST(CodeArchApiTest, PreservesExistingPublicEnumValues) { + EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_CDNA5), 11); EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_RDNA4), 8); EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_RV32I), 9); EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_RV64I), 10); - EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_GFX1250), 11); EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_NUM_ARCHS), 12); EXPECT_EQ(static_cast(ROCJITSU_CODE_ARCH_INVALID), 12); } @@ -117,7 +117,7 @@ struct DecodeCase { class DecoderSmokeTest : public ::testing::TestWithParam {}; TEST(DecoderDiagnosticTest, ValidEncodingEmitsNothingAndKeepsLocation) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::vector messages; auto collect = [&](std::string_view message) { messages.emplace_back(message); }; @@ -131,7 +131,7 @@ TEST(DecoderDiagnosticTest, ValidEncodingEmitsNothingAndKeepsLocation) { TEST(DecoderDiagnosticTest, InvalidOpcodeEmitsExactlyOneDiagnostic) { constexpr uint32_t invalid_opcode = 0xffffffffu; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::vector messages; auto collect = [&](std::string_view message) { messages.emplace_back(message); }; @@ -145,7 +145,7 @@ TEST(DecoderDiagnosticTest, InvalidOpcodeEmitsExactlyOneDiagnostic) { TEST(DecoderDiagnosticTest, InvalidOperandEmitsExactlyOneDiagnostic) { constexpr auto words = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 209, .vdst = 0}); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::vector messages; auto collect = [&](std::string_view message) { messages.emplace_back(message); }; @@ -159,7 +159,7 @@ TEST(DecoderDiagnosticTest, InvalidOperandEmitsExactlyOneDiagnostic) { TEST(DecoderDiagnosticTest, NoOpEmitterStillRejectsInvalidOpcode) { constexpr uint32_t invalid_opcode = 0xffffffffu; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_TRUE(decoder->decode(&invalid_opcode).failed()); @@ -185,7 +185,7 @@ TEST(Gfx1250DecodeTest, DisassemblesDpp8Selectors) { 0x000040CCu, // v204, dpp8:[0,0,1,0,0,0,0,0]. }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -218,8 +218,8 @@ INSTANTIATE_TEST_SUITE_P( DecodeCase{ROCJITSU_CODE_ARCH_RDNA3_5, "rdna3_5", S_ENDPGM_GFX11, "s_endpgm", 4}, DecodeCase{ROCJITSU_CODE_ARCH_RDNA4, "rdna4", S_NOP, "s_nop", 4}, DecodeCase{ROCJITSU_CODE_ARCH_RDNA4, "rdna4", S_ENDPGM_GFX11, "s_endpgm", 4}, - DecodeCase{ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", S_NOP, "s_nop", 4}, - DecodeCase{ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", S_ENDPGM_GFX11, "s_endpgm", 4}), + DecodeCase{ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", S_NOP, "s_nop", 4}, + DecodeCase{ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", S_ENDPGM_GFX11, "s_endpgm", 4}), [](const ::testing::TestParamInfo &info) { std::string name = info.param.arch_name; name += "_"; @@ -293,7 +293,7 @@ TEST(OperandSelectorDecodeTest, Cdna1RestrictedScalarSourceRejectsLiteralSelecto TEST(OperandSelectorDecodeTest, DirectSourceAndSmemOffsetRejectReservedSelectors) { constexpr auto vop1 = cdna5::build_vop1(cdna5::kVMovB32Vop1, {.src0 = 209, .vdst = 0}); - auto gfx1250_decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto gfx1250_decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(gfx1250_decoder, nullptr); EXPECT_TRUE(decode_fails(*gfx1250_decoder, vop1.data())); @@ -305,7 +305,7 @@ TEST(OperandSelectorDecodeTest, DirectSourceAndSmemOffsetRejectReservedSelectors } TEST(OperandSelectorDecodeTest, RestrictedVectorAndLaneOperandsRejectLiteralMarkers) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto expect_rejected = [&](const auto &encoding) { @@ -325,7 +325,7 @@ TEST(OperandSelectorDecodeTest, RestrictedVectorAndLaneOperandsRejectLiteralMark } TEST(OperandSelectorDecodeTest, Gfx1250WmmaSrc2ValidatesVgprOrInlineSelector) { - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto words_for = [](uint16_t selector) { @@ -401,7 +401,7 @@ TEST(OperandSelectorDecodeTest, Gfx1250AndRdna4ValidateBarrierIdSelectors) { }; validate( - ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", + ROCJITSU_CODE_ARCH_CDNA5, "cdna5", [](uint8_t selector) { return cdna5::build_sop1(cdna5::kSBarrierSignalIsfirstSop1, {.ssrc0 = selector}); }, @@ -432,7 +432,7 @@ TEST(RawEncodingTest, PreservesScalarLiteralWordsAcrossAmdgpuIsas) { {ROCJITSU_CODE_ARCH_RDNA3, "rdna3", s_mov_b32_literal}, {ROCJITSU_CODE_ARCH_RDNA3_5, "rdna3_5", s_mov_b32_literal}, {ROCJITSU_CODE_ARCH_RDNA4, "rdna4", s_mov_b32_literal}, - {ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", s_mov_b32_literal}, + {ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", s_mov_b32_literal}, }; for (const auto &tc : cases) { @@ -953,9 +953,9 @@ INSTANTIATE_TEST_SUITE_P( make_vopdxy_pair(14, 8)}, InvalidVopdSlotCase{ROCJITSU_CODE_ARCH_RDNA4, "rdna4", "invalid_y", make_vopdxy_pair(8, 14)}, - InvalidVopdSlotCase{ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", "invalid_x", + InvalidVopdSlotCase{ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", "invalid_x", make_vopdxy_pair(12, 8)}, - InvalidVopdSlotCase{ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", + InvalidVopdSlotCase{ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", "invalid_y_defined_opcode", make_vopdxy_pair(8, 18)}), [](const ::testing::TestParamInfo &info) { std::string name = info.param.arch_name; @@ -1533,7 +1533,7 @@ TEST(Gfx1250DecodeTest, FmamkF64ConsumesThreeDwords) { 0xC1F00000u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -1551,7 +1551,7 @@ TEST(Gfx1250DecodeTest, FmaakF64ConsumesThreeDwords) { 0xC1F00000u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -1567,7 +1567,7 @@ TEST(Gfx1250DecodeTest, Vop3True16DestinationUsesFullEightBitVgprIndex) { 0x000000FFu, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -1590,7 +1590,7 @@ TEST(Gfx1250DecodeTest, FlatVaddrWidthFollowsSaddrMode) { 0x00000001u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr saddr_inst(decode_valid(*decoder, saddr_words)); @@ -1638,7 +1638,7 @@ TEST(Gfx1250DecodeTest, GlobalVaddrWidthFollowsSaddrMode) { 0x0000000Au, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr saddr_inst(decode_valid(*decoder, saddr_words)); @@ -1680,7 +1680,7 @@ TEST(Gfx1250DecodeTest, GlobalStoreUsesScalarOffsetVaddrWidth) { 0x0000000Au, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); @@ -1697,7 +1697,7 @@ TEST(Gfx1250DecodeTest, Vop3CompareWritesSingleScalarMaskRegister) { 0x02021805u, }; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, words)); ASSERT_NE(inst, nullptr); diff --git a/emulation/rocjitsu/tests/decoder_c_api_test.cpp b/emulation/rocjitsu/tests/decoder_c_api_test.cpp index 7f35941c367a..4ff1512dc748 100644 --- a/emulation/rocjitsu/tests/decoder_c_api_test.cpp +++ b/emulation/rocjitsu/tests/decoder_c_api_test.cpp @@ -28,7 +28,7 @@ static_assert(std::is_same_v(static_cast(1)); diff --git a/emulation/rocjitsu/tests/execution_plugin_test.cpp b/emulation/rocjitsu/tests/execution_plugin_test.cpp index 3fa6a3b695ca..9dbbf018df77 100644 --- a/emulation/rocjitsu/tests/execution_plugin_test.cpp +++ b/emulation/rocjitsu/tests/execution_plugin_test.cpp @@ -854,7 +854,7 @@ struct Wave32PluginFixture { std::unique_ptr cu; std::shared_ptr plugin_group; - explicit Wave32PluginFixture(rj_code_arch_t arch = ROCJITSU_CODE_ARCH_GFX1250) + explicit Wave32PluginFixture(rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA5) : gpu_mem(std::make_unique("wave32_plugin_mem")), l2(std::make_unique("wave32_plugin_l2")) { amdgpu::ComputeUnitCore::Config cfg{}; @@ -1274,7 +1274,7 @@ TEST(ExecutionPluginTest, Dpp8FetchInactiveControlsSourceObservation) { const uint32_t vb = wf->vgpr_alloc().base; const uint32_t lane_sel = (0u << 0u) | (0u << 3u) | (2u << 6u) | (3u << 9u) | (4u << 12u) | (5u << 15u) | (6u << 18u) | (7u << 21u); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto run = [&](uint32_t src_marker) { @@ -1335,7 +1335,7 @@ TEST(ExecutionPluginTest, True16InstructionsReportSelectedSourceAndDestinationHa }; const uint32_t vb = wf->vgpr_alloc().base; - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); for (const Case &test_case : cases) { SCOPED_TRACE(std::format("instruction word 0x{:08x}", test_case.word)); @@ -1386,7 +1386,7 @@ TEST(ExecutionPluginTest, Gfx1250Simd64BitWriteReportsBothDestinationRegisters) const uint32_t word = vop1_encode(/*v_mov_b64 opcode=*/29, kDst, /*generic VGPR source=*/256 + kSrc); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); std::unique_ptr inst(decode_valid(*decoder, &word)); ASSERT_NE(inst, nullptr); @@ -2080,7 +2080,7 @@ TEST(ExecutionPluginTest, MemoryPipelineCompletionDoesNotObserveInstructionWrite } TEST(ExecutionPluginTest, D16MemoryCompletionPreservesHalfWithoutObservation) { - PluginFixture f(/*num_wf_slots=*/1, /*arch=*/"gfx1250", /*wavefront_size=*/32); + PluginFixture f(/*num_wf_slots=*/1, /*arch=*/"cdna5", /*wavefront_size=*/32); auto *plugin = f.attach_ordering_plugin(); auto *cu = f.cu(); auto *wf = cu->dispatch_wf(0, 0, /*sgprs=*/104, /*vgprs=*/256); @@ -2854,7 +2854,7 @@ TEST(RaceDetectorPluginOutputTest, DispatchLineUsesReadableNameAndExactSymbol) { } TEST(RaceDetectorPluginTest, DroppedAsyncLdsLaneDoesNotCreateLowAddressRace) { - PluginFixture f(/*num_wf_slots=*/2, /*arch=*/"gfx1250", /*wavefront_size=*/32); + PluginFixture f(/*num_wf_slots=*/2, /*arch=*/"cdna5", /*wavefront_size=*/32); PluginSinkConfig sink_config; StringSink &sink = sink_config.emplace(); f.plugin_group_ = std::make_shared(std::move(sink_config)); diff --git a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp index 21e62c9ce852..0ba0b81fc34e 100644 --- a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp +++ b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp @@ -157,7 +157,7 @@ constexpr HwregArchCase kHwregArchCases[] = { rdna3_5::kSSetregImm32B32Sopk}, {ROCJITSU_CODE_ARCH_RDNA4, "rdna4", rdna4::kSGetregB32Sopk, rdna4::kSSetregB32Sopk, rdna4::kSSetregImm32B32Sopk}, - {ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", cdna5::kSGetregB32Sopk, cdna5::kSSetregB32Sopk, + {ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", cdna5::kSGetregB32Sopk, cdna5::kSSetregB32Sopk, cdna5::kSSetregImm32B32Sopk}, }; @@ -466,7 +466,7 @@ TEST(Rdna4ExecMaskTest, Wave32ExecHiRemainsAvailableAsScalarScratch) { EXPECT_EQ(wf->exec(), static_cast(kRawExec)); } TEST(InstructionExecutionHarness, Gfx1250) { - RUN_HARNESS(cdna5, ROCJITSU_CODE_ARCH_GFX1250, "gfx1250"); + RUN_HARNESS(cdna5, ROCJITSU_CODE_ARCH_CDNA5, "gfx1250"); } #undef RUN_HARNESS @@ -476,7 +476,7 @@ TEST(Gfx1250MemoryExecutionHarness, ExecutesRepresentativeValidAddressStores) { amdgpu::L2Cache l2("gfx1250_memory_harness_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -484,7 +484,7 @@ TEST(Gfx1250MemoryExecutionHarness, ExecutesRepresentativeValidAddressStores) { Gfx1250MemoryTestCu cu("gfx1250", cfg, &gpu_mem, &l2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu.dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -671,7 +671,7 @@ TEST(ScalarSccTest, ScalarCvtPreservesScc) { run_scalar_cvt_preserves_scc(ROCJITSU_CODE_ARCH_RDNA3_5, "rdna3_5", cases.data(), cases.size()); run_scalar_cvt_preserves_scc(ROCJITSU_CODE_ARCH_RDNA4, "rdna4", cases.data(), cases.size()); - run_scalar_cvt_preserves_scc(ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", cases.data(), cases.size()); + run_scalar_cvt_preserves_scc(ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", cases.data(), cases.size()); } TEST(Cdna4Vop3Test, CmpClassF16WritesWave64UpperMaskDword) { @@ -1130,7 +1130,7 @@ TEST(Gfx1250WmmaTest, F16Fp8K64MatchesReferenceLayout) { amdgpu::L2Cache l2("gfx1250_wmma_f16_fp8_k64_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1144,7 +1144,7 @@ TEST(Gfx1250WmmaTest, F16Fp8K64MatchesReferenceLayout) { ASSERT_EQ(wf->wf_size(), 32u); wf->set_exec((1ULL << wf->wf_size()) - 1ULL); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const uint32_t vb = wf->vgpr_alloc().base; @@ -1247,7 +1247,7 @@ TEST(Gfx1250WmmaTest, Bf16F32K32Bf16PreservesAccumulatorLayout) { amdgpu::L2Cache l2("gfx1250_wmma_bf16f32_k32_bf16_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1322,7 +1322,7 @@ TEST(Gfx1250Dpp8Test, Vop2AddF16UsesPermutedSourceLanes) { amdgpu::L2Cache l2("gfx1250_dpp8_add_f16_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1331,7 +1331,7 @@ TEST(Gfx1250Dpp8Test, Vop2AddF16UsesPermutedSourceLanes) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1378,7 +1378,7 @@ TEST(Gfx1250ExecMaskTest, CmpxNeqAndScalarOrRestoreExec) { amdgpu::L2Cache l2("gfx1250_exec_mask_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1387,7 +1387,7 @@ TEST(Gfx1250ExecMaskTest, CmpxNeqAndScalarOrRestoreExec) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1435,7 +1435,7 @@ TEST(Gfx1250ExecMaskTest, Vop3CmpxGtI32KeepsInRangeLanesActive) { amdgpu::L2Cache l2("gfx1250_cmpx_gt_i32_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1444,7 +1444,7 @@ TEST(Gfx1250ExecMaskTest, Vop3CmpxGtI32KeepsInRangeLanesActive) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1475,7 +1475,7 @@ TEST(Gfx1250ExecMaskTest, Vop3CmpF32PreservesHighMaskSgprOnWave32) { amdgpu::L2Cache l2("gfx1250_cmp_f32_mask_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1484,7 +1484,7 @@ TEST(Gfx1250ExecMaskTest, Vop3CmpF32PreservesHighMaskSgprOnWave32) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1521,7 +1521,7 @@ TEST(Gfx1250True16Vop3Test, SelectedHalfArithmeticPreservesDestinationHalf) { amdgpu::L2Cache l2("gfx1250_true16_arith_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1530,7 +1530,7 @@ TEST(Gfx1250True16Vop3Test, SelectedHalfArithmeticPreservesDestinationHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1595,7 +1595,7 @@ TEST(Gfx1250True16Vop2Test, AddF16UsesSelectedHighVsrc1AndPreservesLowDestinatio amdgpu::L2Cache l2("gfx1250_true16_vop2_add_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1604,7 +1604,7 @@ TEST(Gfx1250True16Vop2Test, AddF16UsesSelectedHighVsrc1AndPreservesLowDestinatio auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1637,7 +1637,7 @@ TEST(Gfx1250True16Vop2Test, FmacF16HighDestinationUsesSelectedAccumulatorHalf) { amdgpu::L2Cache l2("gfx1250_true16_vop2_fmac_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1646,7 +1646,7 @@ TEST(Gfx1250True16Vop2Test, FmacF16HighDestinationUsesSelectedAccumulatorHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1679,7 +1679,7 @@ TEST(Gfx1250True16Vop3Test, MulLoU16UsesSelectedHighSourceHalf) { amdgpu::L2Cache l2("gfx1250_true16_mul_src_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1688,7 +1688,7 @@ TEST(Gfx1250True16Vop3Test, MulLoU16UsesSelectedHighSourceHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1717,7 +1717,7 @@ TEST(Gfx1250True16Vop3Test, CmpLtI16UsesSelectedHighSourceHalf) { amdgpu::L2Cache l2("gfx1250_true16_cmp_src_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1726,7 +1726,7 @@ TEST(Gfx1250True16Vop3Test, CmpLtI16UsesSelectedHighSourceHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1763,7 +1763,7 @@ TEST(Gfx1250True16Vop3Test, CmpClassF16UsesSelectedMaskHalf) { : "gfx1250_true16_class_simd_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1772,7 +1772,7 @@ TEST(Gfx1250True16Vop3Test, CmpClassF16UsesSelectedMaskHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1811,7 +1811,7 @@ TEST(Gfx1250True16Vop3Test, CmpxClassF16UsesSelectedMaskHalf) { : "gfx1250_true16_cmpx_class_simd_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1820,7 +1820,7 @@ TEST(Gfx1250True16Vop3Test, CmpxClassF16UsesSelectedMaskHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1857,7 +1857,7 @@ TEST(Gfx1250True16Vop3Test, SpecialVop3OpsUseSelectedHalves) { : "gfx1250_true16_special_simd_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1866,7 +1866,7 @@ TEST(Gfx1250True16Vop3Test, SpecialVop3OpsUseSelectedHalves) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -1936,7 +1936,7 @@ TEST(Gfx1250True16VopcTest, CmpLtI16ReadsPackedHighVsrc1) { amdgpu::L2Cache l2("gfx1250_true16_vopc_cmp_src_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -1945,7 +1945,7 @@ TEST(Gfx1250True16VopcTest, CmpLtI16ReadsPackedHighVsrc1) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3336,7 +3336,7 @@ TEST(Gfx1250True16Vop3Test, CndmaskB16UsesSelectedSourceHalfAndPreservesDestinat amdgpu::L2Cache l2("gfx1250_true16_cndmask_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3345,7 +3345,7 @@ TEST(Gfx1250True16Vop3Test, CndmaskB16UsesSelectedSourceHalfAndPreservesDestinat auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3383,7 +3383,7 @@ TEST(Gfx1250True16Vop3Test, LshrrevB16UsesSelectedSourceHalfAndPreservesDestinat amdgpu::L2Cache l2("gfx1250_true16_lshrrev_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3392,7 +3392,7 @@ TEST(Gfx1250True16Vop3Test, LshrrevB16UsesSelectedSourceHalfAndPreservesDestinat auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3421,7 +3421,7 @@ TEST(Gfx1250True16Vop3Test, Bitop3B16UsesSelectedSourceHalfAndPreservesDestinati amdgpu::L2Cache l2("gfx1250_true16_bitop_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3430,7 +3430,7 @@ TEST(Gfx1250True16Vop3Test, Bitop3B16UsesSelectedSourceHalfAndPreservesDestinati auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3485,7 +3485,7 @@ TEST(Gfx1250True16Vop1Test, MovB16HighDestinationPreservesLowHalf) { amdgpu::L2Cache l2("gfx1250_true16_vop1_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3494,7 +3494,7 @@ TEST(Gfx1250True16Vop1Test, MovB16HighDestinationPreservesLowHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3678,7 +3678,7 @@ TEST(Gfx1250True16Vop1Test, CvtF16F32HighDestinationPreservesLowHalf) { amdgpu::L2Cache l2("gfx1250_true16_cvt_vop1_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3687,7 +3687,7 @@ TEST(Gfx1250True16Vop1Test, CvtF16F32HighDestinationPreservesLowHalf) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3717,7 +3717,7 @@ TEST(Gfx1250CvtFp8Test, F16DecodeVop3UsesSelectedByte) { amdgpu::L2Cache l2("gfx1250_cvt_fp8_bytesel_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3726,7 +3726,7 @@ TEST(Gfx1250CvtFp8Test, F16DecodeVop3UsesSelectedByte) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3765,7 +3765,7 @@ TEST(Gfx1250CvtFp8Test, F16E5M3OverflowHonorsFp16OvflMode) { amdgpu::L2Cache l2("gfx1250_cvt_fp8_f16_e5m3_overflow_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3774,7 +3774,7 @@ TEST(Gfx1250CvtFp8Test, F16E5M3OverflowHonorsFp16OvflMode) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3819,7 +3819,7 @@ TEST(Gfx1250CvtFp8Test, F32DecodeVop3UsesSelectedByte) { amdgpu::L2Cache l2("gfx1250_cvt_fp8_f32_bytesel_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3828,7 +3828,7 @@ TEST(Gfx1250CvtFp8Test, F32DecodeVop3UsesSelectedByte) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3865,7 +3865,7 @@ TEST(Gfx1250CvtFp8Test, E4M3OverflowHonorsFp16OvflMode) { amdgpu::L2Cache l2("gfx1250_cvt_fp8_overflow_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3874,7 +3874,7 @@ TEST(Gfx1250CvtFp8Test, E4M3OverflowHonorsFp16OvflMode) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3908,7 +3908,7 @@ TEST(Gfx1250CvtFp8Test, Bf8OverflowHonorsFp16OvflMode) { amdgpu::L2Cache l2("gfx1250_cvt_bf8_overflow_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3917,7 +3917,7 @@ TEST(Gfx1250CvtFp8Test, Bf8OverflowHonorsFp16OvflMode) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -3951,7 +3951,7 @@ TEST(Gfx1250CvtF16Test, SrPackedF16ConsumesAdvancedSeedAndFp16OvflMode) { amdgpu::L2Cache l2("gfx1250_cvt_sr_pk_f16_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -3960,7 +3960,7 @@ TEST(Gfx1250CvtF16Test, SrPackedF16ConsumesAdvancedSeedAndFp16OvflMode) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); const auto words = @@ -4640,7 +4640,7 @@ TEST(Gfx1250CvtFp8Test, F16SourceFp8Bf8ConversionsIgnoreFp16OvflMode) { amdgpu::L2Cache l2("gfx1250_cvt_fp8_f16_source_mode_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -4649,7 +4649,7 @@ TEST(Gfx1250CvtFp8Test, F16SourceFp8Bf8ConversionsIgnoreFp16OvflMode) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -4993,7 +4993,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { amdgpu::L2Cache l2("gfx1250_cvt_fp8_e5m3_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5002,7 +5002,7 @@ TEST(Gfx1250CvtFp8Test, E5M3ClampSelectsUnsignedFp8Format) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5077,7 +5077,7 @@ TEST(Gfx1250CvtScaleTest, UnpackUsesSelectedE8M0ScaleByte) { amdgpu::L2Cache l2("gfx1250_cvt_scale_e8m0_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5086,7 +5086,7 @@ TEST(Gfx1250CvtScaleTest, UnpackUsesSelectedE8M0ScaleByte) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5132,7 +5132,7 @@ TEST(Gfx1250DsSwizzleTest, VdsBroadcastReadsAddrSource) { amdgpu::L2Cache l2("gfx1250_ds_swizzle_vds_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5141,7 +5141,7 @@ TEST(Gfx1250DsSwizzleTest, VdsBroadcastReadsAddrSource) { auto cu = amdgpu::ComputeUnitCore::create("gfx1250", cfg, &gpu_mem, &l2); ASSERT_NE(cu, nullptr); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5192,7 +5192,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddF32ReturnsOldValue) { amdgpu::L2Cache l2("gfx1250_atomic_add_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5200,7 +5200,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddF32ReturnsOldValue) { Gfx1250MemoryTestCu cu("gfx1250", cfg, &gpu_mem, &l2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu.dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5235,7 +5235,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddF32AllowsDstSrcAlias) { amdgpu::L2Cache l2("gfx1250_atomic_add_alias_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5243,7 +5243,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddF32AllowsDstSrcAlias) { Gfx1250MemoryTestCu cu("gfx1250", cfg, &gpu_mem, &l2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu.dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5278,7 +5278,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddU64CopiesHighSourceDword) { amdgpu::L2Cache l2("gfx1250_atomic_add_u64_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5286,7 +5286,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicAddU64CopiesHighSourceDword) { Gfx1250MemoryTestCu cu("gfx1250", cfg, &gpu_mem, &l2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu.dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5321,7 +5321,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicCmpswapB32ReturnsOldValue) { amdgpu::L2Cache l2("gfx1250_atomic_cmpswap_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5329,7 +5329,7 @@ TEST(Gfx1250AtomicReturnTest, GlobalAtomicCmpswapB32ReturnsOldValue) { Gfx1250MemoryTestCu cu("gfx1250", cfg, &gpu_mem, &l2); - auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_GFX1250); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); auto *wf = cu.dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); @@ -5462,7 +5462,7 @@ TEST(HwregHelperTest, Gfx1250PreservesWaveSchedModeHwreg) { amdgpu::L2Cache l2("hwreg_helper_gfx1250_wave_sched_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5499,7 +5499,7 @@ TEST(HwregHelperTest, Gfx1250UsesManualHwregIdsInsteadOfLegacyAliases) { amdgpu::L2Cache l2("hwreg_helper_gfx1250_hwreg_ids_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5534,7 +5534,7 @@ TEST(HwregHelperTest, Gfx1250ReadsModeledIbStsCounters) { amdgpu::L2Cache l2("hwreg_helper_gfx1250_ib_sts_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5574,7 +5574,7 @@ TEST(HwregHelperTest, Gfx1250ReadsModeledIbSts2Counters) { amdgpu::L2Cache l2("hwreg_helper_gfx1250_ib_sts2_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 106; cfg.vgprs_per_wf = 256; @@ -5631,7 +5631,7 @@ TEST(HwregHelperTest, ModeBit27OnlyEnablesGprIndexingWhereArchitected) { {ROCJITSU_CODE_ARCH_CDNA3, "cdna3", true}, {ROCJITSU_CODE_ARCH_CDNA4, "cdna4", true}, {ROCJITSU_CODE_ARCH_RDNA1, "rdna1", false}, {ROCJITSU_CODE_ARCH_RDNA2, "rdna2", false}, {ROCJITSU_CODE_ARCH_RDNA3, "rdna3", false}, {ROCJITSU_CODE_ARCH_RDNA3_5, "rdna3_5", false}, - {ROCJITSU_CODE_ARCH_RDNA4, "rdna4", false}, {ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", true}, + {ROCJITSU_CODE_ARCH_RDNA4, "rdna4", false}, {ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", true}, }; for (const GprIdxModeCase &arch_case : cases) { diff --git a/emulation/rocjitsu/tests/isa_target_registry_test.cpp b/emulation/rocjitsu/tests/isa_target_registry_test.cpp index e32f6cc3f989..f08af8b600fd 100644 --- a/emulation/rocjitsu/tests/isa_target_registry_test.cpp +++ b/emulation/rocjitsu/tests/isa_target_registry_test.cpp @@ -331,8 +331,8 @@ TEST(IsaTargetRegistryTest, BuiltinRegistryUsesDescriptorOwnedPublicEnumBindings const IsaTargetRegistry ®istry = default_isa_target_registry(); ASSERT_TRUE(registry.ok()) << registry.error(); const std::vector expected = { - "cdna1", "cdna2", "cdna3", "cdna4", "rdna1", "rdna2", - "rdna3", "rdna3_5", "rdna4", "gfx1250", "risc-v", + "cdna1", "cdna2", "cdna3", "cdna4", "rdna1", "rdna2", + "rdna3", "rdna3_5", "rdna4", "cdna5", "risc-v", }; std::vector actual; for (const IsaTargetDescriptor &target : registry.targets()) @@ -351,6 +351,9 @@ TEST(IsaTargetRegistryTest, BuiltinRegistryUsesDescriptorOwnedPublicEnumBindings const IsaTargetDescriptor *gfx1201_enum = registry.find(ROCJITSU_CODE_TARGET_GFX1201); ASSERT_NE(gfx1201_enum, nullptr); EXPECT_EQ(gfx1201_enum->id, "rdna4"); + const IsaTargetDescriptor *gfx1250 = registry.find("gfx1250"); + ASSERT_NE(gfx1250, nullptr); + EXPECT_EQ(gfx1250->id, "cdna5"); EXPECT_NE(Decoder::create(registry, "gfx942"), nullptr); EXPECT_NE(Decoder::create(registry, ROCJITSU_CODE_ARCH_CDNA3), nullptr); EXPECT_EQ(registry.find("rv32i"), nullptr); diff --git a/emulation/rocjitsu/tests/model_only_isa_test.cpp b/emulation/rocjitsu/tests/model_only_isa_test.cpp index cfff2d9de4e8..0b3f15d8fffc 100644 --- a/emulation/rocjitsu/tests/model_only_isa_test.cpp +++ b/emulation/rocjitsu/tests/model_only_isa_test.cpp @@ -24,10 +24,10 @@ TEST(ModelOnlyIsaTest, DecodesWithoutExecutionCallback) { const IsaTargetRegistry ®istry = default_isa_target_registry(); ASSERT_EQ(registry.targets().size(), 1u); - EXPECT_EQ(registry.targets()[0].id, "gfx1250"); + EXPECT_EQ(registry.targets()[0].id, "cdna5"); EXPECT_FALSE(registry.targets()[0].supports_execution); - std::unique_ptr decoder = Decoder::create(registry, ROCJITSU_CODE_ARCH_GFX1250); + std::unique_ptr decoder = Decoder::create(registry, ROCJITSU_CODE_ARCH_CDNA5); ASSERT_NE(decoder, nullptr); EXPECT_EQ(Decoder::create(registry, ROCJITSU_CODE_ARCH_RDNA4), nullptr); diff --git a/emulation/rocjitsu/tests/patch/instruction_builder_test.cpp b/emulation/rocjitsu/tests/patch/instruction_builder_test.cpp index 178fe817a713..90ceb134004b 100644 --- a/emulation/rocjitsu/tests/patch/instruction_builder_test.cpp +++ b/emulation/rocjitsu/tests/patch/instruction_builder_test.cpp @@ -169,16 +169,16 @@ TEST(GeneratedInstructionBuilder, Gfx1250ScalarPathsUseGeneratedLayouts) { constexpr uint16_t kSsrc1 = 9; constexpr auto sopp = cdna5::build_sopp(cdna5::kSBranchSopp, {.simm16 = kSimm16}); - EXPECT_EQ(build_sopp_encoding(ROCJITSU_CODE_ARCH_GFX1250, cdna5::kSBranchSopp, kSimm16), sopp[0]); + EXPECT_EQ(build_sopp_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSBranchSopp, kSimm16), sopp[0]); constexpr auto sop1 = cdna5::build_sop1(cdna5::kSMovB32Sop1, {.ssrc0 = kSsrc0, .sdst = kSdst}); - EXPECT_EQ(build_sop1_encoding(ROCJITSU_CODE_ARCH_GFX1250, cdna5::kSMovB32Sop1, kSdst, kSsrc0), + EXPECT_EQ(build_sop1_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSMovB32Sop1, kSdst, kSsrc0), sop1[0]); constexpr auto sop2 = cdna5::build_sop2(cdna5::kSLshlB32Sop2, {.ssrc0 = kSsrc0, .ssrc1 = kSsrc1, .sdst = kSdst}); EXPECT_EQ( - build_sop2_encoding(ROCJITSU_CODE_ARCH_GFX1250, cdna5::kSLshlB32Sop2, kSdst, kSsrc0, kSsrc1), + build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSLshlB32Sop2, kSdst, kSsrc0, kSsrc1), sop2[0]); } @@ -189,7 +189,7 @@ TEST(InstructionBuilder, BuildSGetpcB64) { EXPECT_EQ(build_s_getpc_b64(0, ROCJITSU_CODE_ARCH_RDNA3), 0xBE804700u); EXPECT_EQ(build_s_getpc_b64(0, ROCJITSU_CODE_ARCH_RDNA4), 0xBE804700u); // gfx1250 renames the family (s_get_pc_i64) but keeps opcode 0x47. - EXPECT_EQ(build_s_getpc_b64(0, ROCJITSU_CODE_ARCH_GFX1250), 0xBE804700u); + EXPECT_EQ(build_s_getpc_b64(0, ROCJITSU_CODE_ARCH_CDNA5), 0xBE804700u); } TEST(InstructionBuilder, BuildSAddU32) { @@ -216,7 +216,7 @@ TEST(InstructionBuilder, BuildSSwappcB64) { EXPECT_EQ(build_s_swappc_b64(30, 0, ROCJITSU_CODE_ARCH_RDNA3), 0xBE9E4900u); EXPECT_EQ(build_s_swappc_b64(30, 0, ROCJITSU_CODE_ARCH_RDNA4), 0xBE9E4900u); // gfx1250: s_swap_pc_i64, opcode 0x49 - EXPECT_EQ(build_s_swappc_b64(30, 0, ROCJITSU_CODE_ARCH_GFX1250), 0xBE9E4900u); + EXPECT_EQ(build_s_swappc_b64(30, 0, ROCJITSU_CODE_ARCH_CDNA5), 0xBE9E4900u); } TEST(InstructionBuilder, BuildSCallB64UsesGfx1250SCallI64Opcode) { @@ -226,7 +226,7 @@ TEST(InstructionBuilder, BuildSCallB64UsesGfx1250SCallI64Opcode) { cdna5::build_sopk(cdna5::kSCallI64Sopk, {.simm16 = static_cast(kOffsetDwords), .sdst = static_cast(kReturnSreg)}); - EXPECT_EQ(build_s_call_b64(kReturnSreg, kOffsetDwords, ROCJITSU_CODE_ARCH_GFX1250), expected[0]); + EXPECT_EQ(build_s_call_b64(kReturnSreg, kOffsetDwords, ROCJITSU_CODE_ARCH_CDNA5), expected[0]); EXPECT_EQ(expected[0], 0xBA1EFFFEu); } @@ -243,7 +243,7 @@ TEST(InstructionBuilder, BuildSCselectB32) { 0x98028081u); // gfx1250 uses the GFX11+ opcode 0x30. EXPECT_EQ(build_s_cselect_b32(2, scalar_positive_inline_u32(1), scalar_positive_inline_u32(0), - ROCJITSU_CODE_ARCH_GFX1250), + ROCJITSU_CODE_ARCH_CDNA5), 0x98028081u); } @@ -255,7 +255,7 @@ TEST(InstructionBuilder, BuildSCmpLgU32) { // Opcode 7 is invariant across gens, including gfx1250. EXPECT_EQ(build_s_cmp_lg_u32(2, scalar_positive_inline_u32(0), ROCJITSU_CODE_ARCH_RDNA4), 0xBF078002u); - EXPECT_EQ(build_s_cmp_lg_u32(2, scalar_positive_inline_u32(0), ROCJITSU_CODE_ARCH_GFX1250), + EXPECT_EQ(build_s_cmp_lg_u32(2, scalar_positive_inline_u32(0), ROCJITSU_CODE_ARCH_CDNA5), 0xBF078002u); } @@ -409,13 +409,13 @@ TEST(InstructionBuilder, ScalarOperandCodesMatchGeneratedTables) { EXPECT_EQ(scalar_operand_vcc_lo(ROCJITSU_CODE_ARCH_CDNA4), cdna4::OPR_SDST_VCC_LO); EXPECT_EQ(scalar_operand_vcc_lo(ROCJITSU_CODE_ARCH_RDNA2), rdna2::OPR_SDST_VCC_LO); EXPECT_EQ(scalar_operand_vcc_lo(ROCJITSU_CODE_ARCH_RDNA4), rdna4::OPR_SDST_VCC_LO); - EXPECT_EQ(scalar_operand_vcc_lo(ROCJITSU_CODE_ARCH_GFX1250), cdna5::OPR_SDST_VCC_LO); + EXPECT_EQ(scalar_operand_vcc_lo(ROCJITSU_CODE_ARCH_CDNA5), cdna5::OPR_SDST_VCC_LO); EXPECT_EQ(scalar_operand_exec_lo(ROCJITSU_CODE_ARCH_CDNA1), cdna1::OPR_SDST_EXEC_LO); EXPECT_EQ(scalar_operand_exec_lo(ROCJITSU_CODE_ARCH_CDNA4), cdna4::OPR_SDST_EXEC_LO); EXPECT_EQ(scalar_operand_exec_lo(ROCJITSU_CODE_ARCH_RDNA2), rdna2::OPR_SDST_EXEC_LO); EXPECT_EQ(scalar_operand_exec_lo(ROCJITSU_CODE_ARCH_RDNA4), rdna4::OPR_SDST_EXEC_LO); - EXPECT_EQ(scalar_operand_exec_lo(ROCJITSU_CODE_ARCH_GFX1250), cdna5::OPR_SDST_EXEC_LO); + EXPECT_EQ(scalar_operand_exec_lo(ROCJITSU_CODE_ARCH_CDNA5), cdna5::OPR_SDST_EXEC_LO); // Inline-constant source for -1 (193), also generation-stable. EXPECT_EQ(scalar_inline_neg_one(ROCJITSU_CODE_ARCH_CDNA4), 193); @@ -423,7 +423,7 @@ TEST(InstructionBuilder, ScalarOperandCodesMatchGeneratedTables) { EXPECT_EQ(scalar_inline_neg_one(ROCJITSU_CODE_ARCH_CDNA4), cdna4::OPR_SRC_NEG_INT_MIN); EXPECT_EQ(scalar_inline_neg_one(ROCJITSU_CODE_ARCH_RDNA2), rdna2::OPR_SRC_NEG_INT_MIN); EXPECT_EQ(scalar_inline_neg_one(ROCJITSU_CODE_ARCH_RDNA4), rdna4::OPR_SRC_NEG_INT_MIN); - EXPECT_EQ(scalar_inline_neg_one(ROCJITSU_CODE_ARCH_GFX1250), cdna5::OPR_SRC_NEG_INT_MIN); + EXPECT_EQ(scalar_inline_neg_one(ROCJITSU_CODE_ARCH_CDNA5), cdna5::OPR_SRC_NEG_INT_MIN); // Base for non-negative inline integers (128 = 0), also generation-stable. EXPECT_EQ(kScalarPositiveInlineBase, 128); @@ -446,13 +446,13 @@ TEST(InstructionBuilder, ScalarOperandM0IsPerArch) { EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_RDNA3), rdna3::OPR_SDST_M0); EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_RDNA3_5), rdna3_5::OPR_SDST_M0); EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_RDNA4), rdna4::OPR_SDST_M0); - EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_GFX1250), cdna5::OPR_SDST_M0); + EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_CDNA5), cdna5::OPR_SDST_M0); // gfx9 / gfx10.x = 124; gfx11+ = 125. EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_CDNA4), 124); EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_RDNA2), 124); EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_RDNA4), 125); - EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_GFX1250), 125); + EXPECT_EQ(scalar_operand_m0(ROCJITSU_CODE_ARCH_CDNA5), 125); } } // namespace diff --git a/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp b/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp index a2661fb28686..2da8d3b172ea 100644 --- a/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp +++ b/emulation/rocjitsu/tests/pseudo_scalar_exec_test.cpp @@ -70,7 +70,7 @@ struct PseudoScalarProfile { constexpr std::array kProfiles{{ {ROCJITSU_CODE_ARCH_RDNA4, "rdna4", rdna4_encoding, rdna4::kSSetregB32Sopk, rdna4::kSSetregImm32B32Sopk}, - {ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", gfx1250_encoding, cdna5::kSSetregB32Sopk, + {ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", gfx1250_encoding, cdna5::kSSetregB32Sopk, cdna5::kSSetregImm32B32Sopk}, }}; diff --git a/emulation/rocjitsu/tests/register_access_test.cpp b/emulation/rocjitsu/tests/register_access_test.cpp index c1bd3339c5f3..ccd6d98651ca 100644 --- a/emulation/rocjitsu/tests/register_access_test.cpp +++ b/emulation/rocjitsu/tests/register_access_test.cpp @@ -268,7 +268,7 @@ TEST(RegisterAccessTest, ReadRegionObservesAllRegistersAndReturnsLaneSpans) { } TEST(RegisterAccessTest, ReadRegionTraversesAndCopiesLogicalRegisterRange) { - for (const auto arch : {ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_GFX1250}) { + for (const auto arch : {ROCJITSU_CODE_ARCH_CDNA4, ROCJITSU_CODE_ARCH_CDNA5}) { Fixture fx(arch); ASSERT_NE(fx.wf, nullptr); SCOPED_TRACE(arch); diff --git a/emulation/rocjitsu/tests/scalar_scc_test.cpp b/emulation/rocjitsu/tests/scalar_scc_test.cpp index 49f7e4b992b5..fb7c481c6cba 100644 --- a/emulation/rocjitsu/tests/scalar_scc_test.cpp +++ b/emulation/rocjitsu/tests/scalar_scc_test.cpp @@ -119,7 +119,7 @@ const std::array kScalarSccProfiles{{ {ROCJITSU_CODE_ARCH_RDNA3, "rdna3", rdna3_encoding, WrexecDialect::AndNot, true}, {ROCJITSU_CODE_ARCH_RDNA3_5, "rdna3_5", rdna3_5_encoding, WrexecDialect::AndNot, true}, {ROCJITSU_CODE_ARCH_RDNA4, "rdna4", rdna4_encoding, WrexecDialect::AndNot, true}, - {ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", gfx1250_encoding, WrexecDialect::AndNot, true}, + {ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", gfx1250_encoding, WrexecDialect::AndNot, true}, }}; EncodingWords require_encoding(const ScalarSccProfile &profile, std::string_view mnemonic) { diff --git a/emulation/rocjitsu/tests/shared_infra_test.cpp b/emulation/rocjitsu/tests/shared_infra_test.cpp index fb8af3de139d..283f2ef74f02 100644 --- a/emulation/rocjitsu/tests/shared_infra_test.cpp +++ b/emulation/rocjitsu/tests/shared_infra_test.cpp @@ -133,21 +133,20 @@ static_assert(!HasMonolithicWaitcnt); static_assert(!HasMonolithicWaitcnt); static_assert(!isa_properties(ROCJITSU_CODE_ARCH_CDNA3).supports_wgp_mode); static_assert(isa_properties(ROCJITSU_CODE_ARCH_RDNA4).supports_wgp_mode); -static_assert(!isa_properties(ROCJITSU_CODE_ARCH_GFX1250).supports_wgp_mode); +static_assert(!isa_properties(ROCJITSU_CODE_ARCH_CDNA5).supports_wgp_mode); static_assert(!isa_properties(ROCJITSU_CODE_ARCH_CDNA3).uses_ttmp_workgroup_ids); static_assert(isa_properties(ROCJITSU_CODE_ARCH_RDNA4).uses_ttmp_workgroup_ids); static_assert(!isa_properties(ROCJITSU_CODE_ARCH_RDNA4).uses_cluster_ttmp_workgroup_ids); -static_assert(isa_properties(ROCJITSU_CODE_ARCH_GFX1250).uses_ttmp_workgroup_ids); -static_assert(isa_properties(ROCJITSU_CODE_ARCH_GFX1250).uses_cluster_ttmp_workgroup_ids); +static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA5).uses_ttmp_workgroup_ids); +static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA5).uses_cluster_ttmp_workgroup_ids); static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA2).descriptor_vgpr_count_granule_wave32 == 0); static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA2).descriptor_vgpr_count_granule_wave64 == 8); static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA3).descriptor_vgpr_count_granule_wave32 == 0); static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA3).descriptor_vgpr_count_granule_wave64 == 8); static_assert(isa_properties(ROCJITSU_CODE_ARCH_RDNA4).descriptor_vgpr_count_granule_wave32 == 8); static_assert(isa_properties(ROCJITSU_CODE_ARCH_RDNA4).descriptor_vgpr_count_granule_wave64 == 4); -static_assert(isa_properties(ROCJITSU_CODE_ARCH_GFX1250).descriptor_vgpr_count_granule_wave32 == - 16); -static_assert(isa_properties(ROCJITSU_CODE_ARCH_GFX1250).descriptor_vgpr_count_granule_wave64 == 0); +static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA5).descriptor_vgpr_count_granule_wave32 == 16); +static_assert(isa_properties(ROCJITSU_CODE_ARCH_CDNA5).descriptor_vgpr_count_granule_wave64 == 0); // RDNA3/3.5 retain monolithic S_WAITCNT (GFX11 layout). static_assert(HasMonolithicWaitcnt); @@ -185,7 +184,7 @@ TEST(IsaPropertiesTest, DescriptorVgprGranuleSupportsEveryAmdgpuWavefrontMode) { ExpectedGranule{ROCJITSU_CODE_ARCH_RDNA3_5, 64, 4}, ExpectedGranule{ROCJITSU_CODE_ARCH_RDNA4, 32, 8}, ExpectedGranule{ROCJITSU_CODE_ARCH_RDNA4, 64, 4}, - ExpectedGranule{ROCJITSU_CODE_ARCH_GFX1250, 32, 16}, + ExpectedGranule{ROCJITSU_CODE_ARCH_CDNA5, 32, 16}, }; for (const auto &[arch, wavefront_size, granule] : cases) { @@ -203,7 +202,7 @@ TEST(IsaPropertiesTest, DescriptorVgprGranuleRejectsUnsupportedInputs) { EXPECT_FALSE( descriptor_vgpr_count_granule_for_wavefront(ROCJITSU_CODE_ARCH_CDNA2, 32).has_value()); EXPECT_FALSE( - descriptor_vgpr_count_granule_for_wavefront(ROCJITSU_CODE_ARCH_GFX1250, 64).has_value()); + descriptor_vgpr_count_granule_for_wavefront(ROCJITSU_CODE_ARCH_CDNA5, 64).has_value()); } TEST(CommandProcessorTest, ConfigureForCdna2UsesEightVgprDescriptorGranule) { @@ -2043,7 +2042,7 @@ TEST(CuFactoryTest, CdnaAccVgprsAreClearedOnRedispatch) { INSTANTIATE_TEST_SUITE_P(AllIsas, CuFactoryTest, ::testing::Values(ROCJITSU_CODE_ARCH_CDNA1, ROCJITSU_CODE_ARCH_CDNA2, ROCJITSU_CODE_ARCH_CDNA3, ROCJITSU_CODE_ARCH_CDNA4, - ROCJITSU_CODE_ARCH_GFX1250, ROCJITSU_CODE_ARCH_RDNA1, + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2, ROCJITSU_CODE_ARCH_RDNA3, ROCJITSU_CODE_ARCH_RDNA3_5, ROCJITSU_CODE_ARCH_RDNA4)); @@ -2443,7 +2442,7 @@ struct Rdna3_5DppTraits { struct Gfx1250DppTraits { static constexpr const char *name = "gfx1250"; - static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_GFX1250; + static constexpr rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA5; static const IsaExecutionBackend &backend() { return cdna5::execution_backend(); } using MachineInst = cdna5::MachineInst; using VopcMachineInst = cdna5::VopcMachineInst; @@ -4039,7 +4038,7 @@ TEST(Gfx1250AddrCalcTest, FlatPrivateScratchDecodesLaneBits) { amdgpu::GpuMemory mem("gfx1250_flat_private_mem"); amdgpu::L2Cache l2("gfx1250_flat_private_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 128; cfg.vgprs_per_wf = 32; @@ -4230,7 +4229,7 @@ TEST(RdnaAddrCalcTest, Gfx1250VbufferWrapsOffsetPartBeforeBoundsCheck) { amdgpu::GpuMemory mem("gfx1250_vbuffer_wrap_mem"); amdgpu::L2Cache l2("gfx1250_vbuffer_wrap_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 128; cfg.vgprs_per_wf = 16; @@ -4269,7 +4268,7 @@ TEST(Gfx1250AddrCalcTest, VbufferZeroNumRecordsMasksAllLanes) { amdgpu::GpuMemory mem("gfx1250_vbuffer_zero_records_mem"); amdgpu::L2Cache l2("gfx1250_vbuffer_zero_records_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 128; cfg.vgprs_per_wf = 16; @@ -4307,7 +4306,7 @@ TEST(Gfx1250AddrCalcTest, VbufferStructuredStrideChecksIndexBounds) { amdgpu::GpuMemory mem("gfx1250_vbuffer_structured_stride_mem"); amdgpu::L2Cache l2("gfx1250_vbuffer_structured_stride_l2"); amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = 128; cfg.vgprs_per_wf = 16; diff --git a/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp b/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp index f9b1dd60fa0d..be9694560f88 100644 --- a/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/vop3_carry_simd_correctness_test.cpp @@ -306,8 +306,7 @@ void run_rdna4_wave64(uint64_t exec) { void run_gfx1250_wave32(uint64_t exec) { for (const auto &c : kRdnaCases) check_case<32>("vop3_carry_simd_gfx1250_mem", "vop3_carry_simd_gfx1250_l2", - "cu_vop3_carry_simd_gfx1250", ROCJITSU_CODE_ARCH_GFX1250, c, kRdna3Encoding, - exec); + "cu_vop3_carry_simd_gfx1250", ROCJITSU_CODE_ARCH_CDNA5, c, kRdna3Encoding, exec); } void check_rdna4_wave64_carry_in_oracle() { diff --git a/emulation/rocjitsu/tests/simd_correctness/wmma_simd_exact_test.cpp b/emulation/rocjitsu/tests/simd_correctness/wmma_simd_exact_test.cpp index cb1a6c15b373..ad466479b6d0 100644 --- a/emulation/rocjitsu/tests/simd_correctness/wmma_simd_exact_test.cpp +++ b/emulation/rocjitsu/tests/simd_correctness/wmma_simd_exact_test.cpp @@ -35,7 +35,7 @@ using WmmaF16SpecFn = void (*)(amdgpu::ComputeUnitCore &, uint32_t, uint32_t, ui uint32_t, bool); struct WmmaFixture : ExactFixture { - WmmaFixture() : ExactFixture(ROCJITSU_CODE_ARCH_GFX1250, WF) {} + WmmaFixture() : ExactFixture(ROCJITSU_CODE_ARCH_CDNA5, WF) {} }; // Drive one (kernel, fmt) case across all trial modes and both accumulator diff --git a/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp b/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp index 6447f9074268..1b1242aa2447 100644 --- a/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp +++ b/emulation/rocjitsu/tests/smem_sbase_operand_test.cpp @@ -133,7 +133,7 @@ INSTANTIATE_TEST_SUITE_P( SmemCase{ROCJITSU_CODE_ARCH_RDNA3, "rdna3", kRdnaGfx1011SLoad64, "s_load_b64", 2}, SmemCase{ROCJITSU_CODE_ARCH_RDNA3_5, "rdna3_5", kRdnaGfx1011SLoad64, "s_load_b64", 2}, SmemCase{ROCJITSU_CODE_ARCH_RDNA4, "rdna4", kGfx12SLoadB64, "s_load_b64", 2}, - SmemCase{ROCJITSU_CODE_ARCH_GFX1250, "gfx1250", kGfx12SLoadB64, "s_load_b64", 2}, + SmemCase{ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", kGfx12SLoadB64, "s_load_b64", 2}, // 128-bit buffer-descriptor SBASE (width 4) -> s[4:7], both naming forms. SmemCase{ROCJITSU_CODE_ARCH_CDNA4, "cdna4_buffer_load_x4", kCdnaSBufferLoadDwordx4, "s_buffer_load_dwordx4", 4}, diff --git a/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp b/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp index f26b61f4db85..24f31df8b5f7 100644 --- a/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp +++ b/emulation/rocjitsu/tests/tools/rj_dbt_translate_smoke_test.cpp @@ -736,8 +736,8 @@ TEST(RjDbtTranslate, RejectsInvalidRewriteDischargeOptionCombinations) { ASSERT_TRUE(error.has_value()); EXPECT_EQ(*error, "--verify-rewrite-discharge requires gfx1250 b0-to-a0 translation"); - options.guest_arch = ROCJITSU_CODE_ARCH_GFX1250; - options.host_arch = ROCJITSU_CODE_ARCH_GFX1250; + options.guest_arch = ROCJITSU_CODE_ARCH_CDNA5; + options.host_arch = ROCJITSU_CODE_ARCH_CDNA5; options.input_revision = rocjitsu::ProcessorRevision::Gfx1250B0; options.output_revision = rocjitsu::ProcessorRevision::Gfx1250A0; options.skip_failed_kernels = true; diff --git a/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp b/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp index 479d43e5b1ec..0906275ba3dd 100644 --- a/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp +++ b/emulation/rocjitsu/tests/vgpr_redispatch_test.cpp @@ -81,7 +81,7 @@ INSTANTIATE_TEST_SUITE_P( WaveSizes, VgprRedispatchTest, ::testing::Values(RedispatchCase{ROCJITSU_CODE_ARCH_RDNA4, 32, 256, "Wave32"}, RedispatchCase{ROCJITSU_CODE_ARCH_CDNA4, 64, 256, "Wave64"}, - RedispatchCase{ROCJITSU_CODE_ARCH_GFX1250, 32, 1024, "Gfx1250"}), + RedispatchCase{ROCJITSU_CODE_ARCH_CDNA5, 32, 1024, "Gfx1250"}), [](const ::testing::TestParamInfo &info) { return info.param.name; }); } // namespace diff --git a/emulation/rocjitsu/tests/wmma_simd_benchmark.cpp b/emulation/rocjitsu/tests/wmma_simd_benchmark.cpp index 74eca76964e1..7dfa2b5e3185 100644 --- a/emulation/rocjitsu/tests/wmma_simd_benchmark.cpp +++ b/emulation/rocjitsu/tests/wmma_simd_benchmark.cpp @@ -72,7 +72,7 @@ struct BenchFixture { BenchFixture() : gpu_mem("wmma_simd_bench_mem"), l2("wmma_simd_bench_l2") { amdgpu::ComputeUnitCore::Config cfg{}; - cfg.arch = ROCJITSU_CODE_ARCH_GFX1250; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; cfg.num_wf_slots = 1; cfg.sgprs_per_wf = SGPRS_PER_WF; cfg.vgprs_per_wf = VGPRS_PER_WF; diff --git a/emulation/rocjitsu/tools/dbt_translate.cpp b/emulation/rocjitsu/tools/dbt_translate.cpp index a1de9e73be7a..6add9daa3ea0 100644 --- a/emulation/rocjitsu/tools/dbt_translate.cpp +++ b/emulation/rocjitsu/tools/dbt_translate.cpp @@ -90,7 +90,7 @@ void record_decode_failure(CodeSectionReport §ion_report, size_t byte_offset // Linked gfx1250 objects use zero-filled holes between independently // aligned function bodies. BasicBlock::build() treats these words as // padding rather than instructions, so host validation must do the same. - if (arch == ROCJITSU_CODE_ARCH_GFX1250 && words[pc] == 0) { + if (arch == ROCJITSU_CODE_ARCH_CDNA5 && words[pc] == 0) { ++pc; continue; } @@ -420,24 +420,24 @@ struct SelectedInput { } // namespace std::optional translation_request_error(const TranslateOptions &options) { - if (options.guest_arch == ROCJITSU_CODE_ARCH_GFX1250 && + if (options.guest_arch == ROCJITSU_CODE_ARCH_CDNA5 && options.input_revision == ProcessorRevision::Unspecified) { return "--input-revision is required when --input-target is gfx1250"; } - if (options.guest_arch != ROCJITSU_CODE_ARCH_GFX1250 && + if (options.guest_arch != ROCJITSU_CODE_ARCH_CDNA5 && options.input_revision != ProcessorRevision::Unspecified) { return "--input-revision is only valid when --input-target is gfx1250"; } - if (options.host_arch == ROCJITSU_CODE_ARCH_GFX1250 && + if (options.host_arch == ROCJITSU_CODE_ARCH_CDNA5 && options.output_revision == ProcessorRevision::Unspecified) { return "--output-revision is required when --output-target is gfx1250"; } - if (options.host_arch != ROCJITSU_CODE_ARCH_GFX1250 && + if (options.host_arch != ROCJITSU_CODE_ARCH_CDNA5 && options.output_revision != ProcessorRevision::Unspecified) { return "--output-revision is only valid when --output-target is gfx1250"; } - if (options.guest_arch == ROCJITSU_CODE_ARCH_GFX1250 && - options.host_arch == ROCJITSU_CODE_ARCH_GFX1250 && + if (options.guest_arch == ROCJITSU_CODE_ARCH_CDNA5 && + options.host_arch == ROCJITSU_CODE_ARCH_CDNA5 && options.input_revision == ProcessorRevision::Gfx1250A0 && options.output_revision == ProcessorRevision::Gfx1250B0) { return "gfx1250 A0-to-B0 translation is not supported"; @@ -447,8 +447,8 @@ std::optional translation_request_error(const TranslateOptions if (options.verify_idempotence && options.skip_failed_kernels) return "--verify-idempotence cannot be combined with --skip-failed-kernels"; if (options.verify_rewrite_discharge && - !(options.guest_arch == ROCJITSU_CODE_ARCH_GFX1250 && - options.host_arch == ROCJITSU_CODE_ARCH_GFX1250 && + !(options.guest_arch == ROCJITSU_CODE_ARCH_CDNA5 && + options.host_arch == ROCJITSU_CODE_ARCH_CDNA5 && options.input_revision == ProcessorRevision::Gfx1250B0 && options.output_revision == ProcessorRevision::Gfx1250A0)) { return "--verify-rewrite-discharge requires gfx1250 b0-to-a0 translation"; diff --git a/emulation/rocjitsu/tools/dbt_translate_cli.cpp b/emulation/rocjitsu/tools/dbt_translate_cli.cpp index fa20cbcd29a2..f7add7fe2737 100644 --- a/emulation/rocjitsu/tools/dbt_translate_cli.cpp +++ b/emulation/rocjitsu/tools/dbt_translate_cli.cpp @@ -52,7 +52,7 @@ constexpr std::array kTargetInfos = {{ ROCJITSU_CODE_TARGET_GFX1201}, // gfx1250 A0 and B0 share the same ELF machine and structural ISA. Separate // revision options select the translation direction. - {"gfx1250", ROCJITSU_CODE_ARCH_GFX1250, EF_AMDGPU_MACH_AMDGCN_GFX1250, + {"gfx1250", ROCJITSU_CODE_ARCH_CDNA5, EF_AMDGPU_MACH_AMDGCN_GFX1250, ROCJITSU_CODE_TARGET_GFX1250}, }}; diff --git a/emulation/rocjitsu/tools/rj_decode_benchmark.cpp b/emulation/rocjitsu/tools/rj_decode_benchmark.cpp index d642eef7b21a..c73b549dd7be 100644 --- a/emulation/rocjitsu/tools/rj_decode_benchmark.cpp +++ b/emulation/rocjitsu/tools/rj_decode_benchmark.cpp @@ -73,7 +73,7 @@ void print_usage(std::ostream &os) { if (value == "gfx1200" || value == "gfx1201") return ROCJITSU_CODE_ARCH_RDNA4; if (value == "gfx1250") - return ROCJITSU_CODE_ARCH_GFX1250; + return ROCJITSU_CODE_ARCH_CDNA5; return std::nullopt; } @@ -87,7 +87,7 @@ void print_usage(std::ostream &os) { case ROCJITSU_CODE_TARGET_GFX1201: return ROCJITSU_CODE_ARCH_RDNA4; case ROCJITSU_CODE_TARGET_GFX1250: - return ROCJITSU_CODE_ARCH_GFX1250; + return ROCJITSU_CODE_ARCH_CDNA5; default: return std::nullopt; } From bfb5f9fab0408d7649b0af865e78688bb192c5f1 Mon Sep 17 00:00:00 2001 From: Han-Chung Wang Date: Wed, 19 Aug 2026 11:21:33 -0700 Subject: [PATCH 21/27] [rocjitsu] Align CDNA4 MI350X configs with captured topology (#10274) Take the updated topology and device properties from the checked-in MI350X KFD captures: ``` projects/rocprofiler-sdk/source/lib/rocprofiler-sdk/tests/data/topology/nodes/5/properties: simd_count 1024 array_count 32 simd_arrays_per_engine 1 cu_per_simd_array 9 simd_per_cu 4 device_id 30112 num_sdma_engines 2 num_sdma_xgmi_engines 14 num_cp_queues 24 max_engine_clk_fcompute 2200 capability 2889327232 capability2 1 debug_prop 1494 ``` ``` projects/rocprofiler-sdk/source/lib/rocprofiler-sdk/tests/data/topology/nodes/5/mem_banks/0/properties: size_in_bytes 309220868096 width 8192 mem_clk_max 1900 ``` The topology values describe 288 physical CU slots but only 256 active CUs: ``` physical CUs = 32 arrays * 9 CUs/array = 288 active CUs = 1024 SIMDs / 4 SIMDs/CU = 256 ``` With eight XCDs, the physical geometry becomes four shader engines and 36 CU slots per XCD: ``` shader engines/XCD = (32 arrays / 1 array/engine) / 8 XCDs = 4 physical CUs/XCD = 4 engines * 1 array/engine * 9 CUs/array = 36 ``` The config's local_mem_size field represents advertised VRAM capacity in bytes, so set it from the memory-bank size_in_bytes value. rocminfo displays the same capacity in KB: ``` 309220868096 bytes / 1024 = 301973504 KB ``` Adjust topology stress workloads to cover the 288 instantiated CU slots and bound matrix workgroups beyond their 256 useful output tiles. Add sysfs and rocminfo regressions to prevent the physical topology and externally reported active-CU count from drifting apart. rocJITsu does not currently model a harvested-CU mask, so all 288 physical slots remain schedulable even though rocminfo reports 256 active CUs. ## Issue Tracking N/A ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. --------- Signed-off-by: hanhanW (cherry picked from commit b05a587f893a28ac51ab6ccbd39468c7cfa99eb8) --- emulation/mirage/builtin/src/agents.rs | 4 +- emulation/rocjitsu/README.md | 6 +- .../{gfx950_cdna4.json => gfx950_mi355x.json} | 33 ++++---- ..._cdna4_kmd.json => gfx950_mi355x_kmd.json} | 30 ++++--- ..._2gpu.json => gfx950_mi355x_kmd_2gpu.json} | 32 ++++---- emulation/rocjitsu/docs/building.md | 2 +- emulation/rocjitsu/docs/configuration.md | 12 +-- emulation/rocjitsu/docs/race-detector.md | 2 +- emulation/rocjitsu/docs/rocjitsu-cli.md | 8 +- emulation/rocjitsu/docs/vm-design.md | 2 +- .../src/rocjitsu/config/config_common.h | 1 + .../src/rocjitsu/config/kfd_device_config.h | 4 + .../rocjitsu/kmd/linux/amdgpu_properties.h | 5 +- .../src/rocjitsu/kmd/linux/interposer.cpp | 73 +++++++++-------- .../rocjitsu/src/rocjitsu/kmd/linux/sysfs.cpp | 3 +- .../rocjitsu/src/rocjitsu/kmd/linux/sysfs.h | 7 +- .../rocjitsu/schemas/simulation_config.fbs | 6 ++ .../rocjitsu/scripts/rocjitsu-docker-run.sh | 8 +- emulation/rocjitsu/tests/CMakeLists.txt | 13 ++- emulation/rocjitsu/tests/config_test.cpp | 23 ++---- .../rocjitsu/tests/corpus/run-corpus-tests.sh | 2 +- emulation/rocjitsu/tests/daemon_api_test.cpp | 2 +- .../rocjitsu/tests/interposer_dup_test.cpp | 25 ++++++ .../rocjitsu/tests/kernels/matmul_mfma.hip | 10 ++- .../rocjitsu/tests/kernels/matmul_tiled.hip | 8 +- .../rocjitsu/tests/kernels/vector_add.hip | 7 +- emulation/rocjitsu/tests/kfd_ioctl_test.cpp | 2 +- emulation/rocjitsu/tests/matmul_test.cpp | 21 ++--- .../rocjitsu/tests/partitioning_test.cpp | 4 +- .../tests/race-detector/CMakeLists.txt | 2 +- emulation/rocjitsu/tests/rocminfo_test.cpp | 82 +++++++++++++++++++ emulation/rocjitsu/tests/scaling_test.cpp | 4 +- .../rocjitsu/tests/simulated_kfd_test.cpp | 2 +- emulation/rocjitsu/tests/sysfs_test.cpp | 53 +++++++++++- emulation/rocjitsu/tests/vector_add_test.cpp | 10 +-- 35 files changed, 346 insertions(+), 162 deletions(-) rename emulation/rocjitsu/configs/{gfx950_cdna4.json => gfx950_mi355x.json} (83%) rename emulation/rocjitsu/configs/{gfx950_cdna4_kmd.json => gfx950_mi355x_kmd.json} (74%) rename emulation/rocjitsu/configs/{gfx950_cdna4_kmd_2gpu.json => gfx950_mi355x_kmd_2gpu.json} (74%) diff --git a/emulation/mirage/builtin/src/agents.rs b/emulation/mirage/builtin/src/agents.rs index 4656e342b536..09eeccfcee71 100644 --- a/emulation/mirage/builtin/src/agents.rs +++ b/emulation/mirage/builtin/src/agents.rs @@ -2,7 +2,7 @@ //! //! Each agent mirrors one of the rocjitsu `configs/*.json` files: //! `MI300X` follows `gfx942_cdna3.json`, `MI350X` follows -//! `gfx950_cdna4.json`, and `MI450X` follows `gfx1250_mi455x.json`. +//! `gfx950_mi355x.json`, and `MI450X` follows `gfx1250_mi455x.json`. //! All three share the same `soc -> {vram, iod, xcd -> {l2, cp, //! se -> cu}}` component tree and six link patterns; they differ //! only in their device identity, the IOD fan-out, and the per-CU @@ -77,7 +77,7 @@ pub fn mi300x() -> AgentDef { } /// `MI350X` builtin agent (registry key `MI350X`), mirroring the -/// rocjitsu `gfx950_cdna4.json` config: `arch = cdna4`, marketing +/// rocjitsu `gfx950_mi355x.json` config: `arch = cdna4`, marketing /// name "AMD Instinct MI350X", and an 8-XCD / 4-SE / 8-CU shader /// fabric over a 2-IOD memory tier. pub fn mi350x() -> AgentDef { diff --git a/emulation/rocjitsu/README.md b/emulation/rocjitsu/README.md index 15971d4d50f2..ff7e3fea4909 100644 --- a/emulation/rocjitsu/README.md +++ b/emulation/rocjitsu/README.md @@ -81,10 +81,10 @@ not found. ```bash # Local mode (in-process simulation) -rocjitsu --config configs/gfx950_cdna4_kmd.json -- ./my_hip_app +rocjitsu --config configs/gfx950_mi355x_kmd.json -- ./my_hip_app # Daemon mode (separate daemon process) -rocjitsu --daemon --config configs/gfx950_cdna4_kmd.json -- ./my_hip_app +rocjitsu --daemon --config configs/gfx950_mi355x_kmd.json -- ./my_hip_app ``` See [docs/rocjitsu-cli.md](docs/rocjitsu-cli.md) for all CLI modes. @@ -106,7 +106,7 @@ See ## Running PyTorch ```bash -rocjitsu --daemon --config configs/gfx950_cdna4_kmd.json -- \ +rocjitsu --daemon --config configs/gfx950_mi355x_kmd.json -- \ python3 -c "import torch; x = torch.randn(4, 4, device='cuda'); print(x @ x)" ``` diff --git a/emulation/rocjitsu/configs/gfx950_cdna4.json b/emulation/rocjitsu/configs/gfx950_mi355x.json similarity index 83% rename from emulation/rocjitsu/configs/gfx950_cdna4.json rename to emulation/rocjitsu/configs/gfx950_mi355x.json index 84c280b14ce6..0493059ad6f6 100644 --- a/emulation/rocjitsu/configs/gfx950_cdna4.json +++ b/emulation/rocjitsu/configs/gfx950_mi355x.json @@ -9,26 +9,27 @@ "gpu_id": 38144, "gfx_target_version": 90500, "vendor_id": 4098, - "device_id": 5892, + "device_id": 30112, "family_id": 160, "unique_id": 5929628898254127105, "marketing_name": "AMD Instinct MI350X", "simd_count": 1024, "max_waves_per_simd": 8, "num_shader_engines": 4, - "num_shader_arrays_per_engine": 2, - "num_cu_per_sh": 4, + "num_shader_arrays_per_engine": 1, + "num_cu_per_sh": 9, "simd_per_cu": 4, "wave_front_size": 64, - "local_mem_size": 309237645312, + "local_mem_size": 309220868096, "lds_size_kb": 160, "mem_width": 8192, - "mem_clk_max": 1600, + "mem_clk_max": 1900, "l2_size_kb": 4096, - "num_sdma_engines": 5, - "num_sdma_xgmi_engines": 12, - "num_cp_queues": 128, - "max_engine_clk_fcompute": 2700, + "num_sdma_engines": 2, + "num_sdma_xgmi_engines": 14, + "num_sdma_queues_per_engine": 8, + "num_cp_queues": 24, + "max_engine_clk_fcompute": 2200, "capability": 2889327232, "capability2": 1, "debug_prop": 1494 @@ -52,7 +53,7 @@ { "name": "se[0:4]", "type": "shader_engine", "children": [{ - "name": "cu[0:8]", "type": "compute_unit", + "name": "cu[0:9]", "type": "compute_unit", "config": [ { "key": "num_wf_slots", "value": "32" }, { "key": "sgprs_per_wf", "value": "104" }, @@ -67,20 +68,20 @@ }, "links": [ { - "pattern": "xcd[i].cp.req_[j*8+k] -> xcd[i].se[j].cu[k].cpl", + "pattern": "xcd[i].cp.req_[j*9+k] -> xcd[i].se[j].cu[k].cpl", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 2 }, { - "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*8+k]", + "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*9+k]", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 10 }, @@ -103,7 +104,7 @@ "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 7 } + { "var_name": "k", "start": 0, "end": 8 } ], "latency": 1, "weight": 2 }, @@ -112,7 +113,7 @@ "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 7 } + { "var_name": "k", "start": 0, "end": 8 } ], "latency": 1, "weight": 2 } diff --git a/emulation/rocjitsu/configs/gfx950_cdna4_kmd.json b/emulation/rocjitsu/configs/gfx950_mi355x_kmd.json similarity index 74% rename from emulation/rocjitsu/configs/gfx950_cdna4_kmd.json rename to emulation/rocjitsu/configs/gfx950_mi355x_kmd.json index 48f42a47b6f4..d9f6970d749b 100644 --- a/emulation/rocjitsu/configs/gfx950_cdna4_kmd.json +++ b/emulation/rocjitsu/configs/gfx950_mi355x_kmd.json @@ -17,25 +17,29 @@ "simd_count": 1024, "max_waves_per_simd": 8, "num_shader_engines": 4, - "num_shader_arrays_per_engine": 2, - "num_cu_per_sh": 4, + "num_shader_arrays_per_engine": 1, + "num_cu_per_sh": 9, "simd_per_cu": 4, "wave_front_size": 64, "max_slots_scratch_cu": 32, - "local_mem_size": 309237645312, + "local_mem_size": 309220868096, "lds_size_kb": 160, "mem_width": 8192, - "mem_clk_max": 1600, + "mem_clk_max": 1900, "l1_size_kb": 32, "l1_line_size": 128, "l1_assoc": 4, "l2_size_kb": 4096, "l2_line_size": 128, "l2_assoc": 16, - "num_sdma_engines": 5, - "num_sdma_xgmi_engines": 12, - "num_cp_queues": 128, - "max_engine_clk_fcompute": 2400 + "num_sdma_engines": 2, + "num_sdma_xgmi_engines": 14, + "num_sdma_queues_per_engine": 8, + "num_cp_queues": 24, + "max_engine_clk_fcompute": 2200, + "capability": 2889327232, + "capability2": 1, + "debug_prop": 1494 } } }, @@ -52,7 +56,7 @@ { "name": "se[0:4]", "type": "shader_engine", "children": [{ - "name": "cu[0:8]", "type": "compute_unit", + "name": "cu[0:9]", "type": "compute_unit", "config": [ { "key": "num_wf_slots", "value": "32" }, { "key": "sgprs_per_wf", "value": "104" }, @@ -67,20 +71,20 @@ }, "links": [ { - "pattern": "xcd[i].cp.req_[j*8+k] -> xcd[i].se[j].cu[k].cpl", + "pattern": "xcd[i].cp.req_[j*9+k] -> xcd[i].se[j].cu[k].cpl", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 2 }, { - "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*8+k]", + "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*9+k]", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 10 } diff --git a/emulation/rocjitsu/configs/gfx950_cdna4_kmd_2gpu.json b/emulation/rocjitsu/configs/gfx950_mi355x_kmd_2gpu.json similarity index 74% rename from emulation/rocjitsu/configs/gfx950_cdna4_kmd_2gpu.json rename to emulation/rocjitsu/configs/gfx950_mi355x_kmd_2gpu.json index 29207477736c..a88fcd905848 100644 --- a/emulation/rocjitsu/configs/gfx950_cdna4_kmd_2gpu.json +++ b/emulation/rocjitsu/configs/gfx950_mi355x_kmd_2gpu.json @@ -18,27 +18,31 @@ "simd_count": 1024, "max_waves_per_simd": 8, "num_shader_engines": 4, - "num_shader_arrays_per_engine": 2, - "num_cu_per_sh": 4, + "num_shader_arrays_per_engine": 1, + "num_cu_per_sh": 9, "simd_per_cu": 4, "wave_front_size": 64, "max_slots_scratch_cu": 32, - "local_mem_size": 309237645312, + "local_mem_size": 309220868096, "lds_size_kb": 160, "mem_width": 8192, - "mem_clk_max": 1600, + "mem_clk_max": 1900, "l1_size_kb": 32, "l1_line_size": 128, "l1_assoc": 4, "l2_size_kb": 4096, "l2_line_size": 128, "l2_assoc": 16, - "num_sdma_engines": 5, - "num_sdma_xgmi_engines": 12, - "num_cp_queues": 128, - "max_engine_clk_fcompute": 2400, + "num_sdma_engines": 2, + "num_sdma_xgmi_engines": 14, + "num_sdma_queues_per_engine": 8, + "num_cp_queues": 24, + "max_engine_clk_fcompute": 2200, "location_id": 768, - "hive_id": 1 + "hive_id": 1, + "capability": 2889327232, + "capability2": 1, + "debug_prop": 1494 } } }, @@ -55,7 +59,7 @@ { "name": "se[0:4]", "type": "shader_engine", "children": [{ - "name": "cu[0:8]", "type": "compute_unit", + "name": "cu[0:9]", "type": "compute_unit", "config": [ { "key": "num_wf_slots", "value": "32" }, { "key": "sgprs_per_wf", "value": "104" }, @@ -70,20 +74,20 @@ }, "links": [ { - "pattern": "xcd[i].cp.req_[j*8+k] -> xcd[i].se[j].cu[k].cpl", + "pattern": "xcd[i].cp.req_[j*9+k] -> xcd[i].se[j].cu[k].cpl", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 2 }, { - "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*8+k]", + "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*9+k]", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 10 } diff --git a/emulation/rocjitsu/docs/building.md b/emulation/rocjitsu/docs/building.md index 9f26b9eb083e..ee1116aab824 100644 --- a/emulation/rocjitsu/docs/building.md +++ b/emulation/rocjitsu/docs/building.md @@ -84,6 +84,6 @@ docker run -it --name rocjitsu-dev \ cd /workspace cmake -B build -G Ninja -DCMAKE_BUILD_TYPE=Release cmake --build build -rocjitsu --daemon --config configs/gfx950_cdna4_kmd.json -- \ +rocjitsu --daemon --config configs/gfx950_mi355x_kmd.json -- \ python3 -c "import torch; print(torch.randn(4,4,device='cuda'))" ``` diff --git a/emulation/rocjitsu/docs/configuration.md b/emulation/rocjitsu/docs/configuration.md index aab177c5d7c1..e18b35c1cfaf 100644 --- a/emulation/rocjitsu/docs/configuration.md +++ b/emulation/rocjitsu/docs/configuration.md @@ -12,9 +12,9 @@ Pre-built simulator configs are in `configs/`: |---|---| | `gfx942_cdna3.json` | Single CDNA3 GPU (standalone simulation) | | `gfx942_cdna3_kmd.json` | Single CDNA3 GPU (daemon/KFD mode) | -| `gfx950_cdna4.json` | Single CDNA4 GPU (standalone simulation) | -| `gfx950_cdna4_kmd.json` | Single CDNA4 GPU (daemon/KFD mode) | -| `gfx950_cdna4_kmd_2gpu.json` | Two CDNA4 GPUs (multi-GPU daemon mode) | +| `gfx950_mi355x.json` | Single CDNA4 GPU (standalone simulation) | +| `gfx950_mi355x_kmd.json` | Single CDNA4 GPU (daemon/KFD mode) | +| `gfx950_mi355x_kmd_2gpu.json` | Two CDNA4 GPUs (multi-GPU daemon mode) | | `gfx1250_mi455x.json` | Single CDNA5 GPU (standalone simulation, no KMD) | | `gfx1100_w7900.json` | Single RDNA3 GPU (standalone simulation) | | `gfx1151.json` | Single RDNA3.5 GPU (standalone simulation) | @@ -51,11 +51,11 @@ The remaining sections describe simulator topology configs. }, "links": [ { - "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*8+k]", + "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*9+k]", "for_ranges": [ { "var_name": "i", "start": 0, "end": 8 }, { "var_name": "j", "start": 0, "end": 4 }, - { "var_name": "k", "start": 0, "end": 8 } + { "var_name": "k", "start": 0, "end": 9 } ], "latency": 1, "weight": 10 } @@ -121,5 +121,5 @@ location IDs. Each GPU gets its own command processor, memory, and cache hierarchy. The daemon manages all GPUs and routes KFD ioctls to the correct device based on `gpu_id`. -See `configs/gfx950_cdna4_kmd_2gpu.json` for a working two-GPU +See `configs/gfx950_mi355x_kmd_2gpu.json` for a working two-GPU configuration used by the RCCL collective tests. diff --git a/emulation/rocjitsu/docs/race-detector.md b/emulation/rocjitsu/docs/race-detector.md index 152f845a69dc..6390cc29d334 100644 --- a/emulation/rocjitsu/docs/race-detector.md +++ b/emulation/rocjitsu/docs/race-detector.md @@ -58,7 +58,7 @@ int main() { Compile it with `hipcc` or `amdclang++`. The `--offload-arch` must match the emulated GPU, which depends on the config file you pass to rocjitsu (e.g. -`gfx950_cdna4.json` emulates gfx950). If using `amdclang++`, pass `-O1` or +`gfx950_mi355x.json` emulates gfx950). If using `amdclang++`, pass `-O1` or higher — the emulator does not currently support unoptimized (`-O0`) GPU code objects. `hipcc` defaults to `-O3` so this isn't an issue there. diff --git a/emulation/rocjitsu/docs/rocjitsu-cli.md b/emulation/rocjitsu/docs/rocjitsu-cli.md index f010776771fd..e0d7c6f60023 100644 --- a/emulation/rocjitsu/docs/rocjitsu-cli.md +++ b/emulation/rocjitsu/docs/rocjitsu-cli.md @@ -34,16 +34,16 @@ Usage: rocjitsu --config [--daemon|--attach] -- [args...] ```bash # Local mode: in-process simulation -rocjitsu --config configs/gfx950_cdna4_kmd.json -- ./app +rocjitsu --config configs/gfx950_mi355x_kmd.json -- ./app # Daemon mode: fork daemon + launch app -rocjitsu --daemon --config configs/gfx950_cdna4_kmd.json -- ./app args... +rocjitsu --daemon --config configs/gfx950_mi355x_kmd.json -- ./app args... # Daemon-only: run server (no app launched) -rocjitsu --daemon --config configs/gfx950_cdna4_kmd.json +rocjitsu --daemon --config configs/gfx950_mi355x_kmd.json # Attach to running daemon -rocjitsu --attach --config configs/gfx950_cdna4_kmd.json -- ./app +rocjitsu --attach --config configs/gfx950_mi355x_kmd.json -- ./app ``` ## Architecture diff --git a/emulation/rocjitsu/docs/vm-design.md b/emulation/rocjitsu/docs/vm-design.md index 194980d78725..d9c958f2efe9 100644 --- a/emulation/rocjitsu/docs/vm-design.md +++ b/emulation/rocjitsu/docs/vm-design.md @@ -317,7 +317,7 @@ convenience wrapper that releases the last reference and tears down the VM. #include rj_vm_t *vm = NULL; -rj_vm_create("configs/gfx950_cdna4.json", &vm); +rj_vm_create("configs/gfx950_mi355x.json", &vm); uint64_t ticks = 0; rj_vm_run(vm, &ticks); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_common.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_common.h index 6f24cefbb12c..159633cf726b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_common.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_common.h @@ -97,6 +97,7 @@ inline KfdDeviceConfig kfd_device_from_fb(const fb::KfdDeviceInfo *device) { config.l2_assoc = device->l2_assoc(); config.num_sdma_engines = device->num_sdma_engines(); config.num_sdma_xgmi_engines = device->num_sdma_xgmi_engines(); + config.num_sdma_queues_per_engine = device->num_sdma_queues_per_engine(); config.num_cp_queues = device->num_cp_queues(); config.max_engine_clk_fcompute = device->max_engine_clk_fcompute(); config.location_id = device->location_id(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/kfd_device_config.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/kfd_device_config.h index 81e8d1089dec..1b3cb24cc5c8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/kfd_device_config.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/kfd_device_config.h @@ -62,6 +62,10 @@ struct KfdDeviceConfig { uint32_t capability2 = 0; ///< KFD debug capability2 bits, or 0 to derive. uint64_t debug_prop = 0; ///< KFD debug_prop bits, or 0 to derive. bool present = false; ///< True if device section existed in config. + + // TODO(hanchung): Set this in every GPU config, reject zero when regular SDMA engines are + // present, and remove the legacy fallback. + uint32_t num_sdma_queues_per_engine = 2; ///< Regular SDMA queues; 2 preserves legacy configs. }; } // namespace rocjitsu::config diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/amdgpu_properties.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/amdgpu_properties.h index f3b0172ac481..ff2c5ca1eede 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/amdgpu_properties.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/amdgpu_properties.h @@ -189,8 +189,9 @@ constexpr uint32_t drm_shader_engine_count(uint32_t kfd_array_count, uint32_t ar constexpr uint32_t drm_quad_shader_pipe_count(uint32_t kfd_array_count) { return kfd_array_count; } -constexpr uint32_t drm_cu_active_number(uint32_t kfd_array_count, uint32_t cu_per_shader_array) { - return kfd_array_count * cu_per_shader_array; +/// Total active CUs exposed through DRM, derived from the KFD SIMD topology. +constexpr uint32_t drm_cu_active_number(uint32_t simd_count, uint32_t simd_per_cu) { + return simd_per_cu == 0 ? 0 : simd_count / simd_per_cu; } } // namespace rocjitsu::kmd diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp index e767c185bd5c..2b99aceaf7fb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp @@ -2351,42 +2351,43 @@ RJ_INTERPOSER_EXPORT int ioctl(int fd, unsigned long request, ...) { return 0; } case AMDGPU_INFO_DEV_INFO: { - if (info->return_size >= sizeof(drm_amdgpu_info_device)) { - auto *dev = static_cast(out); - dev->device_id = gpu->device_id; - dev->chip_rev = gpu->revision_id; - dev->external_rev = rocjitsu::kmd::external_rev_id_for_gfx_target_version( - gpu->gfx_target_version, gpu->revision_id); - dev->pci_rev = gpu->pci_revision_id; - dev->family = gpu->family_id; - // libdrm reports shader engines, which GpuInfo already stores - // directly; the KFD array_count these helpers invert is the derived - // value. Round-tripping through drm_shader_engine_count keeps the two - // views pinned to one definition. - dev->num_shader_engines = rocjitsu::kmd::drm_shader_engine_count( - gpu->array_count_per_xcc(), gpu->num_shader_arrays_per_engine); - dev->num_shader_arrays_per_engine = gpu->num_shader_arrays_per_engine; - dev->gpu_counter_freq = 100000; - dev->max_engine_clock = gpu->max_engine_clk_fcompute; - dev->max_memory_clock = gpu->mem_clk_max; - dev->wave_front_size = gpu->wave_front_size; - dev->num_cu_per_sh = gpu->num_cu_per_sh; - dev->num_hw_gfx_contexts = - rocjitsu::kmd::num_hw_gfx_contexts_for_gfx_target_version(gpu->gfx_target_version); - dev->vram_type = gpu->vram_type; - dev->vram_bit_width = gpu->mem_width; - dev->cu_active_number = - rocjitsu::kmd::drm_cu_active_number(gpu->array_count_per_xcc(), gpu->num_cu_per_sh); - // VA aperture — libdrm's VA manager (amdgpu_vamgr_init) needs a sane - // range. Mirror the KFD GPUVM aperture used elsewhere. - dev->virtual_address_offset = 0x200000; // 2 MiB - dev->virtual_address_max = 0x800000000000ULL; // 47-bit canonical - dev->virtual_address_alignment = 0x1000; // 4 KiB - dev->pte_fragment_size = 0x200000; // 2 MiB - dev->gart_page_size = 0x1000; // 4 KiB - dev->high_va_offset = 0xffff800000000000ULL; - dev->high_va_max = 0xffffffffffffffffULL; - } + drm_amdgpu_info_device dev{}; + dev.device_id = gpu->device_id; + dev.chip_rev = gpu->revision_id; + dev.external_rev = rocjitsu::kmd::external_rev_id_for_gfx_target_version( + gpu->gfx_target_version, gpu->revision_id); + dev.pci_rev = gpu->pci_revision_id; + dev.family = gpu->family_id; + // libdrm reports shader engines, which GpuInfo already stores directly; + // round-trip the derived KFD array_count to keep the two views pinned to + // one definition. + dev.num_shader_engines = rocjitsu::kmd::drm_shader_engine_count( + gpu->array_count_per_xcc(), gpu->num_shader_arrays_per_engine); + dev.num_shader_arrays_per_engine = gpu->num_shader_arrays_per_engine; + dev.gpu_counter_freq = 100000; + dev.max_engine_clock = gpu->max_engine_clk_fcompute; + dev.max_memory_clock = gpu->mem_clk_max; + dev.wave_front_size = gpu->wave_front_size; + dev.num_cu_per_sh = gpu->num_cu_per_sh; + dev.num_hw_gfx_contexts = + rocjitsu::kmd::num_hw_gfx_contexts_for_gfx_target_version(gpu->gfx_target_version); + dev.vram_type = gpu->vram_type; + dev.vram_bit_width = gpu->mem_width; + dev.cu_active_number = + rocjitsu::kmd::drm_cu_active_number(gpu->simd_count, gpu->simd_per_cu); + // VA aperture — libdrm's VA manager (amdgpu_vamgr_init) needs a sane + // range. Mirror the KFD GPUVM aperture used elsewhere. + dev.virtual_address_offset = 0x200000; // 2 MiB + dev.virtual_address_max = 0x800000000000ULL; // 47-bit canonical + dev.virtual_address_alignment = 0x1000; // 4 KiB + dev.pte_fragment_size = 0x200000; // 2 MiB + dev.gart_page_size = 0x1000; // 4 KiB + dev.high_va_offset = 0xffff800000000000ULL; + dev.high_va_max = 0xffffffffffffffffULL; + + // Older libdrm headers use a shorter trailing struct. The kernel ABI + // returns the prefix that fits instead of withholding every field. + std::memcpy(out, &dev, std::min(info->return_size, sizeof(dev))); return 0; } default: diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.cpp index ff0763999116..9c53eeab9709 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.cpp @@ -327,7 +327,7 @@ void Sysfs::write_gpu_node(const std::string &nodes_dir, uint32_t node_idx, cons << "hive_id " << gpu.hive_id << "\n" << "num_sdma_engines " << gpu.num_sdma_engines << "\n" << "num_sdma_xgmi_engines " << gpu.num_sdma_xgmi_engines << "\n" - << "num_sdma_queues_per_engine 2\n" + << "num_sdma_queues_per_engine " << gpu.num_sdma_queues_per_engine << "\n" << "num_cp_queues " << gpu.num_cp_queues << "\n" << "max_engine_clk_fcompute " << gpu.max_engine_clk_fcompute << "\n" << "max_engine_clk_ccompute 0\n" @@ -572,6 +572,7 @@ Sysfs::GpuInfo gpu_info_from_config(const config::KfdDeviceConfig &dev, uint32_t gpu.l2_assoc = dev.l2_assoc; gpu.num_sdma_engines = dev.num_sdma_engines; gpu.num_sdma_xgmi_engines = dev.num_sdma_xgmi_engines; + gpu.num_sdma_queues_per_engine = dev.num_sdma_queues_per_engine; gpu.num_cp_queues = dev.num_cp_queues; gpu.max_engine_clk_fcompute = dev.max_engine_clk_fcompute; gpu.num_xcc = num_xcc; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.h index 6ea0a621ee8d..8853fd350720 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/sysfs.h @@ -73,6 +73,8 @@ class Sysfs { // Engines and queues uint32_t num_sdma_engines = 2; uint32_t num_sdma_xgmi_engines = 0; + // TODO(hanchung): Remove this legacy fallback with the KfdDeviceConfig fallback. + uint32_t num_sdma_queues_per_engine = 2; uint32_t num_cp_queues = 128; uint32_t max_engine_clk_fcompute = 2100; // MHz @@ -109,9 +111,8 @@ class Sysfs { /// recovers NumShaderBanks as array_count / simd_arrays_per_engine and /// rocdbgapi recovers the engine count as /// array_count * num_xcc / simd_arrays_per_engine, so both invert this - /// product to get num_shader_engines back. Deriving it here keeps the - /// configs stating the geometry they model -- an MI350X XCD has four - /// shader engines of two arrays, so num_shader_engines is 4, not 8. + /// product to get num_shader_engines back. Deriving the array count from + /// the configured geometry keeps these representations consistent. uint32_t array_count_per_xcc() const { return num_shader_engines * effective_arrays_per_engine(); } diff --git a/emulation/rocjitsu/schemas/simulation_config.fbs b/emulation/rocjitsu/schemas/simulation_config.fbs index cfb327efa7dd..2e1a3db91024 100644 --- a/emulation/rocjitsu/schemas/simulation_config.fbs +++ b/emulation/rocjitsu/schemas/simulation_config.fbs @@ -108,6 +108,12 @@ table KfdDeviceInfo { capability: uint32 = 0; capability2: uint32 = 0; debug_prop: uint64 = 0; + + // Appended to preserve existing field IDs. The default retains rocJitsu's + // legacy synthetic-sysfs value; hardware-backed configs should override it. + // TODO(hanchung): Set this in every GPU config, reject zero when regular + // SDMA engines are present, and remove the legacy fallback. + num_sdma_queues_per_engine: uint32 = 2; } /// Top-level AMDGPU configuration. diff --git a/emulation/rocjitsu/scripts/rocjitsu-docker-run.sh b/emulation/rocjitsu/scripts/rocjitsu-docker-run.sh index 97d5378b8e31..04f38012a1fa 100755 --- a/emulation/rocjitsu/scripts/rocjitsu-docker-run.sh +++ b/emulation/rocjitsu/scripts/rocjitsu-docker-run.sh @@ -28,7 +28,7 @@ # # Environment variables: # RJ_BUILD_DIR - Host build directory (default: ./build) -# RJ_CONFIG - Config file (default: configs/gfx950_cdna4_kmd.json) +# RJ_CONFIG - Config file (default: configs/gfx950_mi355x_kmd.json) # RJ_INSTALL_DIR - Install prefix inside container (default: /opt/rocm) # RJ_INSTALLED - Set to 1 if rocjitsu is pre-installed in the image @@ -66,7 +66,7 @@ shift # Common environment for both modes. ENV_ARGS=( -e "LD_PRELOAD=${INSTALL_DIR}/lib/librocjitsu.so" - -e "RJ_CONFIG=${INSTALL_DIR}/share/rocjitsu/configs/gfx950_cdna4_kmd.json" + -e "RJ_CONFIG=${INSTALL_DIR}/share/rocjitsu/configs/gfx950_mi355x_kmd.json" -e "HSA_ENABLE_SDMA=1" -e "ROCPROFILER_REGISTER_ENABLED=0" ) @@ -76,7 +76,7 @@ VOLUME_ARGS=() if [[ "${RJ_INSTALLED:-0}" != "1" ]]; then # Bind-mount mode: mount host files into the container at the install paths. BUILD_DIR="${RJ_BUILD_DIR:-${PROJECT_DIR}/build}" - CONFIG="${RJ_CONFIG:-${PROJECT_DIR}/configs/gfx950_cdna4_kmd.json}" + CONFIG="${RJ_CONFIG:-${PROJECT_DIR}/configs/gfx950_mi355x_kmd.json}" SCHEMA="${PROJECT_DIR}/schemas/simulation_config.fbs" LIB_PATH="${BUILD_DIR}/librocjitsu.so" @@ -92,7 +92,7 @@ if [[ "${RJ_INSTALLED:-0}" != "1" ]]; then VOLUME_ARGS=( -v "${LIB_PATH}:${INSTALL_DIR}/lib/librocjitsu.so:ro" - -v "${CONFIG}:${INSTALL_DIR}/share/rocjitsu/configs/gfx950_cdna4_kmd.json:ro" + -v "${CONFIG}:${INSTALL_DIR}/share/rocjitsu/configs/gfx950_mi355x_kmd.json:ro" -v "${SCHEMA}:${INSTALL_DIR}/share/rocjitsu/schemas/simulation_config.fbs:ro" ) diff --git a/emulation/rocjitsu/tests/CMakeLists.txt b/emulation/rocjitsu/tests/CMakeLists.txt index 92fc48e70613..08d88035b566 100644 --- a/emulation/rocjitsu/tests/CMakeLists.txt +++ b/emulation/rocjitsu/tests/CMakeLists.txt @@ -883,9 +883,9 @@ rj_configure_target(scaling_test TEST) # The CLI handles LD_PRELOAD and config discovery. rj_add_test gives launcher # tests isolated runtime directories, so no RESOURCE_LOCK is needed. -set(RJ_CDNA4_KMD_CONFIG "${CMAKE_SOURCE_DIR}/configs/gfx950_cdna4_kmd.json") +set(RJ_CDNA4_KMD_CONFIG "${CMAKE_SOURCE_DIR}/configs/gfx950_mi355x_kmd.json") set(RJ_CDNA4_KMD_2GPU_CONFIG - "${CMAKE_SOURCE_DIR}/configs/gfx950_cdna4_kmd_2gpu.json" + "${CMAKE_SOURCE_DIR}/configs/gfx950_mi355x_kmd_2gpu.json" ) set(RJ_CDNA3_KMD_CONFIG "${CMAKE_SOURCE_DIR}/configs/gfx942_cdna3_kmd.json") set(RJ_CDNA4_TO_CDNA3_SIM_DBT_CONFIG @@ -982,7 +982,7 @@ endif() set(RJ_KMD_PRELOAD_ENV "LD_PRELOAD=${RJ_SANITIZER_PRELOAD_PREFIX}$" - "RJ_CONFIG=${CMAKE_SOURCE_DIR}/configs/gfx950_cdna4.json" + "RJ_CONFIG=${CMAKE_SOURCE_DIR}/configs/gfx950_mi355x.json" ) add_executable(guest_kfd_test guest_kfd_test.cpp) @@ -1432,6 +1432,11 @@ if(NOT RJ_ENABLE_TSAN) endif() rj_add_interposer_test_suite(InterposerDupTest ${_rj_interposer_dup_tests}) +rj_add_interposer_test_suite( + InterposerDrmTest + DeviceInfoReportsActiveCuCount +) + rj_add_interposer_test_suite( InterposerGemTest GemNamespaceIsPrivateButSharedByDuplicates @@ -1534,6 +1539,8 @@ if(ROCMINFO_EXECUTABLE AND RJ_HAS_KFD_DEVICE) DetectsGpuAgent ReportsGfx950 ReportsWavefrontSize + ReportsMi350xActiveComputeUnits + ReportsMi350xMaxClockFrequency ) rj_add_test( NAME "RocminfoTest.${_rocminfo_test}" diff --git a/emulation/rocjitsu/tests/config_test.cpp b/emulation/rocjitsu/tests/config_test.cpp index 17596e350eef..21d29d2ba9ef 100644 --- a/emulation/rocjitsu/tests/config_test.cpp +++ b/emulation/rocjitsu/tests/config_test.cpp @@ -52,16 +52,18 @@ test::ScopedTempFile write_temp_config(std::string_view json) { } TEST(ConfigLoaderTest, LoadCdna4Config) { - std::string json = CONFIG_DIR_PATH + "/gfx950_cdna4.json"; + std::string json = CONFIG_DIR_PATH + "/gfx950_mi355x.json"; auto loaded = config::load_config(json, rocjitsu::kEmbeddedSchema); auto *soc = loaded.soc(); - // CDNA4 config: 8 XCDs, 4 SEs per XCD, 8 CUs per SE, 2 IODs. + // MI350X physical geometry: 8 XCDs, 4 SEs per XCD, 9 CUs per SE, 2 IODs. + // The part exposes 256 active CUs through simd_count but has capacity for 288. EXPECT_EQ(soc->num_xcds(), 8u); EXPECT_EQ(soc->num_iods(), 2u); auto *xcd = soc->xcd(0); EXPECT_EQ(xcd->num_shader_engines(), 4u); - EXPECT_EQ(xcd->shader_engine(0)->num_compute_units(), 8u); + EXPECT_EQ(xcd->shader_engine(0)->num_compute_units(), 9u); + EXPECT_EQ(kmd::drm_cu_active_number(loaded.device.simd_count, loaded.device.simd_per_cu), 256u); } TEST(ConfigLoaderTest, LoadRdnaKmdConfigs) { @@ -87,10 +89,7 @@ TEST(ConfigLoaderTest, LoadRdnaKmdConfigs) { rdna4.device.num_shader_arrays_per_engine, rdna4.device.num_shader_arrays_per_engine), 4u); - EXPECT_EQ(kmd::drm_cu_active_number(rdna4.device.num_shader_engines * - rdna4.device.num_shader_arrays_per_engine, - rdna4.device.num_cu_per_sh), - 64u); + EXPECT_EQ(kmd::drm_cu_active_number(rdna4.device.simd_count, rdna4.device.simd_per_cu), 64u); EXPECT_EQ(kmd::external_rev_id_for_gfx_target_version(rdna4.device.gfx_target_version, rdna4.device.revision_id), 0x51u); @@ -136,10 +135,7 @@ TEST(ConfigLoaderTest, LoadRdnaKmdConfigs) { rdna3.device.num_shader_arrays_per_engine, rdna3.device.num_shader_arrays_per_engine), 6u); - EXPECT_EQ(kmd::drm_cu_active_number(rdna3.device.num_shader_engines * - rdna3.device.num_shader_arrays_per_engine, - rdna3.device.num_cu_per_sh), - 96u); + EXPECT_EQ(kmd::drm_cu_active_number(rdna3.device.simd_count, rdna3.device.simd_per_cu), 96u); EXPECT_EQ(kmd::external_rev_id_for_gfx_target_version(rdna3.device.gfx_target_version, rdna3.device.revision_id), 0x1u); @@ -173,10 +169,7 @@ TEST(ConfigLoaderTest, LoadRdnaKmdConfigs) { rdna35.device.num_shader_arrays_per_engine, rdna35.device.num_shader_arrays_per_engine), 2u); - EXPECT_EQ(kmd::drm_cu_active_number(rdna35.device.num_shader_engines * - rdna35.device.num_shader_arrays_per_engine, - rdna35.device.num_cu_per_sh), - 32u); + EXPECT_EQ(kmd::drm_cu_active_number(rdna35.device.simd_count, rdna35.device.simd_per_cu), 32u); EXPECT_EQ(kmd::external_rev_id_for_gfx_target_version(rdna35.device.gfx_target_version, rdna35.device.revision_id), 0xc1u); diff --git a/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh b/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh index 07f410f0a51e..5e8b8c04efee 100755 --- a/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh +++ b/emulation/rocjitsu/tests/corpus/run-corpus-tests.sh @@ -42,7 +42,7 @@ usage() { targets=( "gfx942 gfx942_cdna3.json gfx942_skip_tests.json" - "gfx950 gfx950_cdna4.json gfx950_skip_tests.json" + "gfx950 gfx950_mi355x.json gfx950_skip_tests.json" "gfx1100 gfx1100_w7900.json gfx1100_skip_tests.json" "gfx1201 gfx1201_r9700.json gfx1201_skip_tests.json" "gfx1250 gfx1250_mi455x.json gfx1250_skip_tests.json" diff --git a/emulation/rocjitsu/tests/daemon_api_test.cpp b/emulation/rocjitsu/tests/daemon_api_test.cpp index 571d002bb631..eeeb889b53d9 100644 --- a/emulation/rocjitsu/tests/daemon_api_test.cpp +++ b/emulation/rocjitsu/tests/daemon_api_test.cpp @@ -47,7 +47,7 @@ class TempDirectory { const std::string &daemon_json() { static const std::string config = [] { - std::ifstream input(std::filesystem::path(CONFIG_DIR) / "gfx950_cdna4_kmd.json"); + std::ifstream input(std::filesystem::path(CONFIG_DIR) / "gfx950_mi355x_kmd.json"); return std::string(std::istreambuf_iterator(input), std::istreambuf_iterator()); }(); return config; diff --git a/emulation/rocjitsu/tests/interposer_dup_test.cpp b/emulation/rocjitsu/tests/interposer_dup_test.cpp index 5a5a21f6fc50..a65984dcef3d 100644 --- a/emulation/rocjitsu/tests/interposer_dup_test.cpp +++ b/emulation/rocjitsu/tests/interposer_dup_test.cpp @@ -452,6 +452,14 @@ namespace { // callers open /dev/kfd first. int open_drm_render() { return open("/dev/dri/renderD128", O_RDWR | O_CLOEXEC); } +bool query_drm_device_info(int drm_fd, drm_amdgpu_info_device *device) { + drm_amdgpu_info query{}; + query.return_pointer = reinterpret_cast(device); + query.return_size = sizeof(*device); + query.query = AMDGPU_INFO_DEV_INFO; + return ioctl(drm_fd, DRM_IOCTL_AMDGPU_INFO, &query) == 0; +} + // Create an mmap-able, sized stand-in for a dmabuf export fd. PRIME_FD_TO_HANDLE // fstats the fd for the BO size and later MAP mmaps it, so the fd must be a real // sized, mappable object; a memfd satisfies both without a KFD allocation. @@ -497,6 +505,23 @@ int64_t monotonic_deadline_after(std::chrono::nanoseconds delay) { } // namespace +TEST(InterposerDrmTest, DeviceInfoReportsActiveCuCount) { + int kfd = open_kfd(); + ASSERT_GE(kfd, 0); + ASSERT_TRUE(kfd_version_ok(kfd)); + + int drm = open_drm_render(); + ASSERT_GE(drm, 0); + + drm_amdgpu_info_device device{}; + ASSERT_TRUE(query_drm_device_info(drm, &device)); + EXPECT_EQ(device.device_id, 30112u); + EXPECT_EQ(device.cu_active_number, 256u); + + EXPECT_EQ(close(drm), 0); + EXPECT_EQ(close(kfd), 0); +} + TEST(InterposerSyncobjTest, VmTimelineWaitObservesSynchronousMapAndUnmap) { int kfd = open_kfd(); ASSERT_GE(kfd, 0); diff --git a/emulation/rocjitsu/tests/kernels/matmul_mfma.hip b/emulation/rocjitsu/tests/kernels/matmul_mfma.hip index 0f4a4e811cb8..a6ea9ac7537b 100644 --- a/emulation/rocjitsu/tests/kernels/matmul_mfma.hip +++ b/emulation/rocjitsu/tests/kernels/matmul_mfma.hip @@ -15,8 +15,9 @@ /// row of the 4x4 accumulator. The K-loop iterates over the shared dimension, /// feeding one column of A and one row of B per iteration via rank-1 updates. /// -/// With N=64 and 256 workgroups of 64 threads each, all 256 CUs across 8 XCDs -/// are utilized (16x16 tiles of 4x4 = 64x64 output elements). +/// With N=64, the first 256 workgroups cover the 16x16 grid of 4x4 tiles. A +/// 288-workgroup MI350X topology stress dispatch gives each physical CU a group; +/// the final 32 groups exit before accessing the matrices. /// /// Kernel arguments (passed via the argument buffer): /// A - pointer to input matrix A (N*N floats, row-major) @@ -26,11 +27,12 @@ using v4f32 = __attribute__((ext_vector_type(4))) float; -extern "C" __global__ void matmul_mfma(const float *__restrict__ A, - const float *__restrict__ B, +extern "C" __global__ void matmul_mfma(const float *__restrict__ A, const float *__restrict__ B, float *__restrict__ C, unsigned N) { constexpr unsigned TILE = 4; unsigned tiles_per_row = N / TILE; + if (blockIdx.x >= tiles_per_row * tiles_per_row) + return; unsigned tile_row = blockIdx.x / tiles_per_row; unsigned tile_col = blockIdx.x % tiles_per_row; unsigned lane = threadIdx.x % TILE; diff --git a/emulation/rocjitsu/tests/kernels/matmul_tiled.hip b/emulation/rocjitsu/tests/kernels/matmul_tiled.hip index b8934f69be6b..6766fd56d53e 100644 --- a/emulation/rocjitsu/tests/kernels/matmul_tiled.hip +++ b/emulation/rocjitsu/tests/kernels/matmul_tiled.hip @@ -10,8 +10,9 @@ /// global_id = workgroup_id * 64 + thread_id /// row = global_id / N, col = global_id % N /// -/// With N=128 and 256 workgroups of 64 threads each, all 16384 output elements -/// are covered, distributing one workgroup per compute unit across 256 CUs. +/// With N=128, the first 256 workgroups cover all 16384 output elements. A +/// 288-workgroup MI350X topology stress dispatch gives each physical CU a group; +/// the final 32 groups exit through the gid bounds check. /// /// Kernel arguments (passed via the argument buffer): /// A - pointer to input matrix A (N*N floats, row-major) @@ -19,8 +20,7 @@ /// C - pointer to output matrix C (N*N floats, row-major) /// N - matrix dimension -extern "C" __global__ void matmul_tiled(const float *__restrict__ A, - const float *__restrict__ B, +extern "C" __global__ void matmul_tiled(const float *__restrict__ A, const float *__restrict__ B, float *__restrict__ C, unsigned N) { // blockDim.x is always 64 (one wavefront per workgroup). constexpr unsigned BLOCK_SIZE = 64; diff --git a/emulation/rocjitsu/tests/kernels/vector_add.hip b/emulation/rocjitsu/tests/kernels/vector_add.hip index 79048d355b2f..0c3cf43f0e9c 100644 --- a/emulation/rocjitsu/tests/kernels/vector_add.hip +++ b/emulation/rocjitsu/tests/kernels/vector_add.hip @@ -9,8 +9,8 @@ /// The global thread ID determines which element each lane computes: /// global_id = workgroup_id * 64 + thread_id /// -/// With 256 workgroups of 64 threads each, all 16384 elements are covered, -/// distributing one workgroup per compute unit across 256 CUs (8 XCDs). +/// With 288 workgroups of 64 threads each, all 18432 elements are covered, +/// distributing one workgroup per physical compute unit across 288 CUs (8 XCDs). /// /// Kernel arguments (passed via the argument buffer): /// A - pointer to input vector A (N floats) @@ -18,8 +18,7 @@ /// C - pointer to output vector C (N floats) /// N - number of elements -extern "C" __global__ void vector_add(const float *__restrict__ A, - const float *__restrict__ B, +extern "C" __global__ void vector_add(const float *__restrict__ A, const float *__restrict__ B, float *__restrict__ C, unsigned N) { constexpr unsigned BLOCK_SIZE = 64; unsigned gid = blockIdx.x * BLOCK_SIZE + threadIdx.x; diff --git a/emulation/rocjitsu/tests/kfd_ioctl_test.cpp b/emulation/rocjitsu/tests/kfd_ioctl_test.cpp index 021bfdff4aff..317f07ccac09 100644 --- a/emulation/rocjitsu/tests/kfd_ioctl_test.cpp +++ b/emulation/rocjitsu/tests/kfd_ioctl_test.cpp @@ -37,7 +37,7 @@ namespace { -const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_cdna4.json"; +const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_mi355x.json"; constexpr uint32_t kGpuId = 38144; uint32_t query_gb_addr_config(const std::string &config_path, uint32_t gpu_id) { diff --git a/emulation/rocjitsu/tests/matmul_test.cpp b/emulation/rocjitsu/tests/matmul_test.cpp index 6b858abb2eb5..0701403899b7 100644 --- a/emulation/rocjitsu/tests/matmul_test.cpp +++ b/emulation/rocjitsu/tests/matmul_test.cpp @@ -42,10 +42,10 @@ namespace { using namespace rocjitsu; using test::kernel_path; -const std::string CONFIG_PATH = test::config_path("gfx950_cdna4.json"); +const std::string CONFIG_PATH = test::config_path("gfx950_mi355x.json"); constexpr uint32_t TOTAL_XCDS = 8; -constexpr uint32_t CUS_PER_XCD = 32; // 4 SEs × 8 CUs +constexpr uint32_t CUS_PER_XCD = 36; // 4 SEs × 9 physical CUs constexpr uint32_t TOTAL_CUS = TOTAL_XCDS * CUS_PER_XCD; // AMDGPU kernel descriptor (HSA code object v3, 64 bytes). @@ -285,7 +285,9 @@ TEST(MatmulCodeObjectTest, TiledKernelDescriptor) { EXPECT_GE((kd.compute_pgm_rsrc2 >> 1) & 0x1F, 2u) << "Need at least 2 user SGPRs for kernarg ptr"; } -// Each test dispatches one workgroup per CU across all 8 XCDs (256 CUs total). +// Each stress test dispatches one workgroup per physical CU across all 8 XCDs +// (288 CUs total). Some extra workgroups exit through kernel bounds checks +// because the square matrix shapes contain 256 useful output tiles. constexpr unsigned STRESS_N = 128; @@ -295,9 +297,9 @@ void run_matmul_stress(const char *kernel_name, unsigned N, uint32_t num_threads // For MFMA with 4x4 tiles: total_wgs = (N/4)^2. // For tiled with 64-element blocks: total_wgs = ceil(N*N / 64). - // With N=128: tiled = 256 WGs, MFMA (4x4 tiles) = 1024 WGs. - // With N=64: tiled = 64 WGs, MFMA (4x4 tiles) = 256 WGs. - // We pick N so that the number of WGs equals TOTAL_CUS for exact 1:1 mapping. + // N controls the useful output range; dispatch_all_xcds deliberately launches + // TOTAL_CUS workgroups so every physical CU participates. Out-of-range groups + // return without touching memory. // Generate input matrices. std::vector A(mat_elems); @@ -338,12 +340,11 @@ void run_matmul_stress(const char *kernel_name, unsigned N, uint32_t num_threads EXPECT_EQ(mismatches, 0u) << mismatches << " elements differ (showing first 10)"; } -// Tiled (VALU) stress test: N=128, 256 WGs of 64 threads each. +// Tiled (VALU) stress test: N=128, 288 WGs of 64 threads each. // global_id = blockIdx.x * 64 + threadIdx.x → covers all 128*128 = 16384 elements. TEST(MatmulStressTest, TiledAllCUs) { run_matmul_stress("matmul_tiled", STRESS_N); } -// MFMA stress test: N=64, 256 WGs of 4x4 MFMA tiles. -// (64/4)^2 = 16*16 = 256 tiles, one per CU. +// MFMA stress test: N=64, 288 WGs; 256 useful 4x4 tiles and 32 bounded exits. constexpr unsigned MFMA_N = 64; TEST(MatmulStressTest, MfmaAllCUs) { run_matmul_stress("matmul_mfma", MFMA_N); } @@ -359,7 +360,7 @@ TEST(MatmulStressTest, MfmaAllCUs_MultiThreaded) { } // Topology-only stress test: verify that the CDNA4 topology builds correctly -// and all 256 CUs can dispatch and halt wavefronts (engine-driven, no kernel execution). +// and all 288 physical CUs can dispatch and halt wavefronts (engine-driven, no kernel execution). TEST(MatmulStressTest, Cdna4TopologyDispatchAndHalt) { constexpr uint32_t total_wgs = TOTAL_CUS; diff --git a/emulation/rocjitsu/tests/partitioning_test.cpp b/emulation/rocjitsu/tests/partitioning_test.cpp index c37b5339a845..039bca8bb515 100644 --- a/emulation/rocjitsu/tests/partitioning_test.cpp +++ b/emulation/rocjitsu/tests/partitioning_test.cpp @@ -26,8 +26,8 @@ namespace { using namespace rocjitsu; -const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_cdna4.json"; -const std::string CONFIG_2GPU_PATH = std::string(CONFIG_DIR) + "/gfx950_cdna4_kmd_2gpu.json"; +const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_mi355x.json"; +const std::string CONFIG_2GPU_PATH = std::string(CONFIG_DIR) + "/gfx950_mi355x_kmd_2gpu.json"; const std::string CONFIG_1XCD_PATH = std::string(CONFIG_DIR) + "/gfx1100_w7900.json"; std::string config_json_with_num_threads(const std::string &path, uint32_t num_threads) { diff --git a/emulation/rocjitsu/tests/race-detector/CMakeLists.txt b/emulation/rocjitsu/tests/race-detector/CMakeLists.txt index ce2db2484a7f..dd85c7533f37 100644 --- a/emulation/rocjitsu/tests/race-detector/CMakeLists.txt +++ b/emulation/rocjitsu/tests/race-detector/CMakeLists.txt @@ -3,7 +3,7 @@ # --- Race detection HIP tests --- # Uses a lightweight config (race_test_config.json) with 1 XCD and 4 CUs -# instead of the full MI350X topology (8 XCDs, 256 CUs). Each race test +# instead of the full MI350X topology (8 XCDs, 288 physical / 256 active CUs). Each race test # spawns a complete simulation engine, and with ctest -j the full config # causes OOM kills at moderate parallelism (~15+ concurrent tests). The # race detector only needs a few CUs to exercise cross-wave and diff --git a/emulation/rocjitsu/tests/rocminfo_test.cpp b/emulation/rocjitsu/tests/rocminfo_test.cpp index 3505bd7a15cb..30d9bf3a3fc4 100644 --- a/emulation/rocjitsu/tests/rocminfo_test.cpp +++ b/emulation/rocjitsu/tests/rocminfo_test.cpp @@ -8,10 +8,13 @@ #include #include +#include #include #include #include +#include #include +#include #include namespace { @@ -94,6 +97,62 @@ const ProcessResult &rocminfo_output() { return result; } +// Removes surrounding horizontal whitespace from a rocminfo field or line. +std::string_view trim(std::string_view value) { + const size_t first = value.find_first_not_of(" \t\r"); + if (first == std::string_view::npos) + return {}; + const size_t last = value.find_last_not_of(" \t\r"); + return value.substr(first, last - first + 1); +} + +// Returns the value of an exactly labeled field within one rocminfo agent block. +std::optional agent_field(std::string_view agent, std::string_view label) { + size_t line_start = 0; + while (line_start < agent.size()) { + const size_t line_end = agent.find('\n', line_start); + std::string_view line = trim(agent.substr(line_start, line_end - line_start)); + if (line.size() > label.size() && line.compare(0, label.size(), label) == 0 && + line[label.size()] == ':') { + return trim(line.substr(label.size() + 1)); + } + if (line_end == std::string_view::npos) + break; + line_start = line_end + 1; + } + return std::nullopt; +} + +// Finds the rocminfo agent block identified as a gfx950 GPU. +std::optional gfx950_gpu_agent(std::string_view output) { + constexpr std::string_view kAgentHeading = "\nAgent "; + size_t agent_start = output.find(kAgentHeading); + while (agent_start != std::string_view::npos) { + const size_t next_agent = output.find(kAgentHeading, agent_start + kAgentHeading.size()); + std::string_view agent = output.substr(agent_start, next_agent - agent_start); + const auto name = agent_field(agent, "Name"); + const auto device_type = agent_field(agent, "Device Type"); + if (name && device_type && *name == "gfx950" && *device_type == "GPU") { + return agent; + } + agent_start = next_agent; + } + return std::nullopt; +} + +// Parses an entire rocminfo agent field as an unsigned decimal integer. +std::optional decimal_agent_field(std::string_view agent, std::string_view label) { + const auto text = agent_field(agent, label); + if (!text) + return std::nullopt; + + uint64_t value = 0; + const auto [end, error] = std::from_chars(text->data(), text->data() + text->size(), value); + if (error != std::errc{} || end != text->data() + text->size()) + return std::nullopt; + return value; +} + TEST(RocminfoTest, ExitsSuccessfully) { EXPECT_EQ(rocminfo_output().exit_code, 0) << "rocminfo failed with exit code " << rocminfo_output().exit_code << "\nOutput:\n" @@ -134,4 +193,27 @@ TEST(RocminfoTest, ReportsWavefrontSize) { << rocminfo_output().output; } +TEST(RocminfoTest, ReportsMi350xActiveComputeUnits) { + ASSERT_EQ(rocminfo_output().exit_code, 0) << rocminfo_output().output; + const auto agent = gfx950_gpu_agent(rocminfo_output().output); + ASSERT_TRUE(agent) << "rocminfo did not report a gfx950 GPU agent.\nOutput:\n" + << rocminfo_output().output; + const auto compute_units = decimal_agent_field(*agent, "Compute Unit"); + ASSERT_TRUE(compute_units) + << "rocminfo did not report a numeric GPU Compute Unit field.\nOutput:\n" + << rocminfo_output().output; + EXPECT_EQ(*compute_units, 256u); +} + +TEST(RocminfoTest, ReportsMi350xMaxClockFrequency) { + ASSERT_EQ(rocminfo_output().exit_code, 0) << rocminfo_output().output; + const auto agent = gfx950_gpu_agent(rocminfo_output().output); + ASSERT_TRUE(agent) << "rocminfo did not report a gfx950 GPU agent.\nOutput:\n" + << rocminfo_output().output; + const auto max_clock = decimal_agent_field(*agent, "Max Clock Freq. (MHz)"); + ASSERT_TRUE(max_clock) << "rocminfo did not report a numeric GPU maximum clock field.\nOutput:\n" + << rocminfo_output().output; + EXPECT_EQ(*max_clock, 2200u); +} + } // namespace diff --git a/emulation/rocjitsu/tests/scaling_test.cpp b/emulation/rocjitsu/tests/scaling_test.cpp index 4dfd078fa2ed..be2235c997c8 100644 --- a/emulation/rocjitsu/tests/scaling_test.cpp +++ b/emulation/rocjitsu/tests/scaling_test.cpp @@ -36,11 +36,11 @@ RJ_DIAGNOSTIC_POP using namespace rocjitsu; -static const std::string CONFIG_PATH = test::config_path("gfx950_cdna4.json"); +static const std::string CONFIG_PATH = test::config_path("gfx950_mi355x.json"); using test::kernel_path; static constexpr uint32_t TOTAL_XCDS = 8; -static constexpr uint32_t CUS_PER_XCD = 32; +static constexpr uint32_t CUS_PER_XCD = 36; // 4 SEs x 9 physical CUs static constexpr uint32_t TOTAL_CUS = TOTAL_XCDS * CUS_PER_XCD; static constexpr uint32_t WF_SIZE = 64; diff --git a/emulation/rocjitsu/tests/simulated_kfd_test.cpp b/emulation/rocjitsu/tests/simulated_kfd_test.cpp index d4ad4e309fc2..23eecd2b58a0 100644 --- a/emulation/rocjitsu/tests/simulated_kfd_test.cpp +++ b/emulation/rocjitsu/tests/simulated_kfd_test.cpp @@ -38,7 +38,7 @@ RJ_DIAGNOSTIC_POP namespace { -const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_cdna4.json"; +const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_mi355x.json"; struct TestVM { rocjitsu::config::LoadedConfig loaded; diff --git a/emulation/rocjitsu/tests/sysfs_test.cpp b/emulation/rocjitsu/tests/sysfs_test.cpp index ea07c80625b2..767e66ccd12a 100644 --- a/emulation/rocjitsu/tests/sysfs_test.cpp +++ b/emulation/rocjitsu/tests/sysfs_test.cpp @@ -292,6 +292,57 @@ TEST(SysfsTopologyGeometryTest, ArrayCountIsScaledByNumXcc) { } } +// MI350X is harvested too: its captured KFD topology has 32 shader arrays of +// 9 CUs (288 physical CUs), while simd_count exposes 1024 SIMDs, or 256 active +// CUs at four SIMDs per CU. Keep every full-device gfx950 config pinned to that +// same capture so local, KMD, and multi-GPU launch paths cannot drift apart. +TEST(SysfsTopologyGeometryTest, Mi350xMatchesCapturedPhysicalAndActiveCuCounts) { + const std::string config_dir = CONFIG_DIR; + constexpr const char *kMi350xConfigs[] = {"gfx950_mi355x.json", "gfx950_mi355x_kmd.json", + "gfx950_mi355x_kmd_2gpu.json"}; + + for (const char *cfg : kMi350xConfigs) { + SCOPED_TRACE(cfg); + auto loaded = config::load_config(config_dir + "/" + cfg, rocjitsu::kEmbeddedSchema); + ASSERT_TRUE(loaded.device.present); + ASSERT_NE(loaded.soc(), nullptr); + const uint32_t num_xcc = loaded.soc()->num_xcds(); + ASSERT_EQ(num_xcc, 8u); + + Sysfs sysfs; + std::string topology_dir = sysfs.generate(gpu_info_from_config(loaded.device, num_xcc)); + ASSERT_FALSE(topology_dir.empty()); + auto props = read_properties(topology_dir + "/nodes/1/properties"); + + ASSERT_TRUE(props.count("array_count")); + ASSERT_TRUE(props.count("simd_arrays_per_engine")); + ASSERT_TRUE(props.count("cu_per_simd_array")); + ASSERT_TRUE(props.count("simd_count")); + ASSERT_TRUE(props.count("simd_per_cu")); + EXPECT_EQ(props["array_count"], 32u); + EXPECT_EQ(props["simd_arrays_per_engine"], 1u); + EXPECT_EQ(props["cu_per_simd_array"], 9u); + EXPECT_EQ(props["simd_count"], 1024u); + EXPECT_EQ(props["simd_per_cu"], 4u); + + const uint64_t physical_cus = props["array_count"] * props["cu_per_simd_array"]; + const uint64_t active_cus = props["simd_count"] / props["simd_per_cu"]; + EXPECT_EQ(physical_cus, 288u); + EXPECT_EQ(active_cus, 256u); + + EXPECT_EQ(loaded.device.device_id, 30112u); + EXPECT_EQ(loaded.device.local_mem_size, 309220868096ULL); + EXPECT_EQ(loaded.device.mem_clk_max, 1900u); + EXPECT_EQ(loaded.device.num_sdma_engines, 2u); + EXPECT_EQ(loaded.device.num_sdma_xgmi_engines, 14u); + EXPECT_EQ(loaded.device.num_sdma_queues_per_engine, 8u); + ASSERT_TRUE(props.count("num_sdma_queues_per_engine")); + EXPECT_EQ(props["num_sdma_queues_per_engine"], 8u); + EXPECT_EQ(loaded.device.num_cp_queues, 24u); + EXPECT_EQ(loaded.device.max_engine_clk_fcompute, 2200u); + } +} + // Every shipped config must describe the machine it actually simulates. // // num_shader_engines is the per-XCC shader-engine count, so it has to equal the @@ -419,7 +470,7 @@ TEST(SysfsTopologyDebugCapabilityTest, ConfigTopologyMatchesRealHardware) { // Configs whose device matches a captured real-hardware topology dump. constexpr const char *kConfigs[] = { "gfx942_cdna3.json", // MI300X - "gfx950_cdna4.json", // MI350X + "gfx950_mi355x.json", // MI350X "gfx1201_r9700.json", // R9700 }; diff --git a/emulation/rocjitsu/tests/vector_add_test.cpp b/emulation/rocjitsu/tests/vector_add_test.cpp index 6cfbab03f192..ae9b34880f6b 100644 --- a/emulation/rocjitsu/tests/vector_add_test.cpp +++ b/emulation/rocjitsu/tests/vector_add_test.cpp @@ -3,8 +3,8 @@ /// @file Multi-XCD vector addition stress test with golden reference validation. /// -/// Loads a compiled vector_add.hip kernel and dispatches 256 workgroups across -/// all 8 XCDs (CDNA4 topology), one workgroup per CU. Each wavefront of 64 +/// Loads a compiled vector_add.hip kernel and dispatches 288 workgroups across +/// all 8 XCDs (CDNA4 physical topology), one workgroup per CU. Each wavefront of 64 /// threads computes C[gid] = A[gid] + B[gid]. Results are compared against a /// CPU golden reference. @@ -46,14 +46,14 @@ namespace { using namespace rocjitsu; -const std::string CONFIG_PATH = test::config_path("gfx950_cdna4.json"); +const std::string CONFIG_PATH = test::config_path("gfx950_mi355x.json"); using test::kernel_path; constexpr uint32_t TOTAL_XCDS = 8; -constexpr uint32_t CUS_PER_XCD = 32; // 4 SEs x 8 CUs +constexpr uint32_t CUS_PER_XCD = 36; // 4 SEs x 9 physical CUs constexpr uint32_t TOTAL_CUS = TOTAL_XCDS * CUS_PER_XCD; constexpr uint32_t WF_SIZE = 64; -constexpr uint32_t N = TOTAL_CUS * WF_SIZE; // 16384 elements, one WG per CU +constexpr uint32_t N = TOTAL_CUS * WF_SIZE; // 18432 elements, one WG per physical CU constexpr uint64_t KD_ADDR = 0x10000; constexpr uint64_t A_ADDR = 0x100000; From 8177b5725ca9fdbbfd7a072b3f405951118b5282 Mon Sep 17 00:00:00 2001 From: Austin Lu Date: Wed, 19 Aug 2026 15:01:51 -0400 Subject: [PATCH 22/27] feat(rocjitsu): cdna5 OOB behavior implementation (#10362) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Motivation Implement OOB memory access behavior for gfx1250/cdna5. Lay groundwork for other architectures. ## Technical Details - Implemented missing gfx1250’s per-component VBUFFER OOB behavior. - Model CDNA5 descriptor bounds, scaled stride, OOB_SELECT, and 45-bit offset rules. - Implement ordinary aligned, unswizzled TYPE=0 semantics: each dword is checked independently, OOB load components return zero, OOB store components are dropped, atomics remain all-or-nothing, and valid lanes retain coalesced cache traffic. Swizzle, alignment modes/MEMVIOL, and resource-TYPE validation remain follow-ups. ## Issue Tracking N/A ## Test Plan Added new tests. Ran tests. ## Test Result Tests pass. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit f81f9d40db67e85bed3b9d156194292980e26d09) --- .../isa/arch/amdgpu/cdna5/addr_calc.cpp | 99 ++-- .../isa/arch/amdgpu/cdna5/addr_calc.h | 14 + .../rocjitsu/vm/amdgpu/l1_vector_cache.cpp | 61 ++- .../src/rocjitsu/vm/amdgpu/l1_vector_cache.h | 12 +- .../src/rocjitsu/vm/amdgpu/mem_state.h | 4 + .../rocjitsu/vm/amdgpu/memory_pipeline.cpp | 7 +- .../rocjitsu/tests/cdna5_execution_test.cpp | 203 +++++++ .../rocjitsu/tests/shared_infra_test.cpp | 513 +++++++++++++++++- 8 files changed, 856 insertions(+), 57 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp index 1d82aa44c2bf..401bb84ae024 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp @@ -4,7 +4,6 @@ #include "rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand_types.h" -#include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/lds.h" #include "rocjitsu/vm/amdgpu/mem_state.h" @@ -21,6 +20,8 @@ namespace rocjitsu::cdna5 { namespace { +constexpr uint64_t kBufferOffsetMask = (uint64_t{1} << 45) - 1; + uint32_t scaled_vaddr_factor(const amdgpu::VectorMemState &d) { // LLVM folds gfx1250 scale_offset when the scale matches the full memory // access size. The encoded immediate offset remains a byte offset. @@ -64,18 +65,6 @@ uint32_t resolved_vgpr_base(const amdgpu::Wavefront &wf, uint32_t operand, *Isa::resolved_vgpr_offset(wf, OperandType::OPR_VGPR, operand, role); } -uint64_t buffer_base_addr(uint32_t srd0, uint32_t srd1) { - return (static_cast(srd1 & 0x01FF'FFFFu) << 32) | srd0; -} - -uint64_t buffer_num_records(uint32_t srd1, uint32_t srd2, uint32_t srd3) { - return ((static_cast(srd3 & 0x3Fu) << 32) | srd2) << 7 | ((srd1 >> 25) & 0x7Fu); -} - -uint32_t buffer_stride(uint32_t srd3) { return (srd3 >> 12) & 0xFFFFu; } - -bool buffer_oob_raw(uint32_t srd3) { return (srd3 & 0x8000'0000u) != 0; } - void init_vector_mem_state(amdgpu::Wavefront &wf, amdgpu::VectorMemState &d) { uint64_t exec = wf.exec(); d.lane_mask = exec; @@ -86,6 +75,17 @@ void init_vector_mem_state(amdgpu::Wavefront &wf, amdgpu::VectorMemState &d) { d.cu_path = wf.cu().full_path(); } +int64_t logical_buffer_offset(uint32_t index, uint32_t stride, uint32_t voffset, int32_t ioffset) { + return static_cast(index) * stride + voffset + ioffset; +} + +bool byte_range_exceeds(int64_t offset, uint32_t size, uint64_t bound) { + if (offset < 0) + return true; + uint64_t unsigned_offset = static_cast(offset); + return unsigned_offset > bound || size > bound - unsigned_offset; +} + bool decode_flat_private_address(amdgpu::Wavefront &wf, uint64_t addr, uint64_t *translated) { uint32_t lane_stride = wf.scratch_lane_size(); if (lane_stride == 0) @@ -150,6 +150,21 @@ void flat_global_calculate_addresses(const Inst &inst, amdgpu::Wavefront &wf, } // namespace +BufferResource decode_buffer_resource(uint32_t srd0, uint32_t srd1, uint32_t srd2, uint32_t srd3) { + static constexpr uint32_t stride_multipliers[] = {1, 4, 8, 32}; + BufferResource resource{}; + resource.base_address = (static_cast(srd1 & 0x01FF'FFFFu) << 32) | srd0; + resource.num_records = + ((static_cast(srd3 & 0x3Fu) << 32) | srd2) << 7 | ((srd1 >> 25) & 0x7Fu); + resource.raw_stride = (srd3 >> 12) & 0x3FFFu; + resource.stride_scale = static_cast((srd3 >> 26) & 0x3u); + resource.stride = resource.raw_stride * stride_multipliers[resource.stride_scale]; + resource.swizzle_enabled = ((srd3 >> 28) & 0x1u) != 0; + resource.oob_select = ((srd3 >> 29) & 0x1u) != 0; + resource.type = static_cast((srd3 >> 30) & 0x3u); + return resource; +} + uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf, uint32_t access_size_bytes) { auto &cu = wf.cu(); @@ -233,12 +248,9 @@ void mubuf_calculate_addresses(const VbufferMachineInst &inst, amdgpu::Wavefront uint32_t srd1 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 1); uint32_t srd2 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 2); uint32_t srd3 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 3); - uint64_t base_addr = buffer_base_addr(srd0, srd1); - uint64_t num_records = buffer_num_records(srd1, srd2, srd3); - uint32_t stride = buffer_stride(srd3); - bool oob_raw = buffer_oob_raw(srd3); + BufferResource resource = decode_buffer_resource(srd0, srd1, srd2, srd3); uint32_t soffset_val = has_smem_offset(inst.soffset) ? read_sreg_m0_operand(wf, inst.soffset) : 0; - int64_t ioff = static_cast(signed_ioffset(inst.ioffset)); + int32_t ioff = signed_ioffset(inst.ioffset); uint32_t vbase = 0; if (inst.idxen || inst.offen) vbase = resolved_vgpr_base(wf, inst.vaddr, amdgpu::VgprMsbRole::Src0); @@ -248,6 +260,18 @@ void mubuf_calculate_addresses(const VbufferMachineInst &inst, amdgpu::Wavefront uint32_t reg_count = (inst.idxen && inst.offen) ? 2 : 1; vaddr_region.emplace(regs.read_vgpr_region(vbase, reg_count, exec)); } + assert(d.elem_size != 0 && d.num_elems != 0); + d.element_lane_masks.clear(); + if (ioff < 0) { + // CDNA5 requires VBUFFER IOFFSET to be non-negative. Suppress illegal + // encodings defensively so their wrapped 45-bit address cannot reach L1. + d.element_lane_masks.assign(d.num_elems, 0); + d.lane_mask = 0; + return; + } + if (!resource.swizzle_enabled) + d.element_lane_masks.assign(d.num_elems, exec); + d.lane_mask = 0; for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; @@ -261,21 +285,34 @@ void mubuf_calculate_addresses(const VbufferMachineInst &inst, amdgpu::Wavefront } else if (inst.offen) { voffset = vaddr_region->lane(0, lane); } - uint32_t offset_part = amdgpu::addr_calc::buffer_offset_part(voffset, ioff); - uint64_t total_offset = - amdgpu::addr_calc::buffer_total_offset(index, stride, offset_part, soffset_val); - bool oob; - if (!oob_raw && stride > 0) { - oob = index >= num_records; - } else { - oob = offset_part >= num_records; + int64_t logical_offset = logical_buffer_offset(index, resource.stride, voffset, ioff); + uint64_t buffer_offset = static_cast(logical_offset) & kBufferOffsetMask; + d.per_lane_addr[lane] = resource.base_address + soffset_val + buffer_offset; + + if (resource.swizzle_enabled) { + // Swizzled address generation is not modeled yet. Preserve the existing + // linear address behavior, but do not apply unswizzled bounds rules. + d.lane_mask |= uint64_t{1} << lane; + continue; } - if (oob) { - d.lane_mask &= ~(1ULL << lane); - d.per_lane_addr[lane] = 0; - } else { - d.per_lane_addr[lane] = (base_addr + total_offset) & 0xFFFFFFFFFFFFULL; + + int64_t record_offset = static_cast(soffset_val) + voffset + ioff; + int64_t total_offset = static_cast(soffset_val) + logical_offset; + for (uint32_t elem = 0; elem < d.num_elems; ++elem) { + int64_t component_offset = static_cast(elem) * d.elem_size; + bool oob = + byte_range_exceeds(total_offset + component_offset, d.elem_size, resource.num_records); + if (resource.oob_select) { + oob = oob || + byte_range_exceeds(record_offset + component_offset, d.elem_size, resource.stride); + } + if (oob) + d.element_lane_masks[elem] &= ~(uint64_t{1} << lane); + else + d.lane_mask |= uint64_t{1} << lane; } + if (!(d.lane_mask & (uint64_t{1} << lane))) + d.per_lane_addr[lane] = 0; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h index 2b954116be6c..ad306b7c4c4e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h @@ -18,6 +18,20 @@ struct VectorMemState; namespace rocjitsu::cdna5 { +/// @brief Decoded CDNA5 buffer resource descriptor fields. +struct BufferResource { + uint64_t base_address = 0; + uint64_t num_records = 0; + uint32_t raw_stride = 0; + uint32_t stride = 0; + uint8_t stride_scale = 0; + bool swizzle_enabled = false; + bool oob_select = false; + uint8_t type = 0; +}; + +BufferResource decode_buffer_resource(uint32_t srd0, uint32_t srd1, uint32_t srd2, uint32_t srd3); + /// @brief Sign-extend a CDNA5 24-bit IOFFSET field. inline int32_t signed_ioffset(uint32_t ioffset) { return static_cast(ioffset << 8) >> 8; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp index c3ef800433e7..c792104b9c21 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp @@ -43,6 +43,23 @@ uint32_t for_each_coalesced_lane_run(const uint64_t *addrs, uint64_t lane_mask, return run_count; } +bool all_elements_use_lane_mask(std::span element_lane_masks, uint64_t lane_mask, + uint32_t num_elems) { + if (element_lane_masks.empty()) + return true; + assert(element_lane_masks.size() == num_elems); + (void)num_elems; + return std::ranges::all_of(element_lane_masks, + [lane_mask](uint64_t mask) { return mask == lane_mask; }); +} + +uint64_t fully_valid_lane_mask(std::span element_lane_masks, uint64_t lane_mask) { + uint64_t full_lane_mask = lane_mask; + for (uint64_t element_mask : element_lane_masks) + full_lane_mask &= element_mask; + return full_lane_mask; +} + } // namespace L1VectorCache::L1VectorCache(L2Cache *l2) @@ -193,10 +210,30 @@ void L1VectorCache::write_bytes(uint64_t addr, const uint8_t *src, uint32_t size void L1VectorCache::load(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, uint8_t *dst, Mtype mtype, bool non_temporal, - bool request_l1_bypass, uint32_t wf_size, uint32_t vmid) { + bool request_l1_bypass, uint32_t wf_size, uint32_t vmid, + std::span element_lane_masks) { auto coherence_guard = DeviceCacheCoherence::instance().acquire_l1_access(); synchronize_epoch_locked(); uint32_t stride = num_elems * elem_size; + if (!all_elements_use_lane_mask(element_lane_masks, lane_mask, num_elems)) { + uint64_t full_lane_mask = fully_valid_lane_mask(element_lane_masks, lane_mask); + for_each_coalesced_lane_run( + addrs, full_lane_mask, wf_size, stride, [&](uint32_t first_lane, uint32_t run_lanes) { + read_bytes(addrs[first_lane], dst + first_lane * stride, run_lanes * stride, mtype, + non_temporal, request_l1_bypass, vmid); + }); + for (uint32_t elem = 0; elem < num_elems; ++elem) { + uint64_t mask = element_lane_masks[elem] & lane_mask & ~full_lane_mask; + while (mask) { + const uint32_t lane = std::countr_zero(mask); + mask &= ~(uint64_t{1} << lane); + read_bytes(addrs[lane] + static_cast(elem) * elem_size, + dst + lane * stride + elem * elem_size, elem_size, mtype, non_temporal, + request_l1_bypass, vmid); + } + } + return; + } for_each_coalesced_lane_run( addrs, lane_mask, wf_size, stride, [&](uint32_t first_lane, uint32_t run_lanes) { read_bytes(addrs[first_lane], dst + first_lane * stride, run_lanes * stride, mtype, @@ -206,7 +243,8 @@ void L1VectorCache::load(const uint64_t *addrs, uint64_t lane_mask, uint32_t ele void L1VectorCache::store(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, const uint8_t *src, Mtype mtype, bool non_temporal, - uint32_t wf_size, uint32_t vmid) { + uint32_t wf_size, uint32_t vmid, + std::span element_lane_masks) { auto coherence_guard = DeviceCacheCoherence::instance().acquire_l1_access(); synchronize_epoch_locked(); uint32_t stride = num_elems * elem_size; @@ -214,6 +252,25 @@ void L1VectorCache::store(const uint64_t *addrs, uint64_t lane_mask, uint32_t el ++store_count_; if (active_lanes > 0) ++store_active_count_; + if (!all_elements_use_lane_mask(element_lane_masks, lane_mask, num_elems)) { + uint64_t full_lane_mask = fully_valid_lane_mask(element_lane_masks, lane_mask); + store_l2_writes_ += for_each_coalesced_lane_run( + addrs, full_lane_mask, wf_size, stride, [&](uint32_t first_lane, uint32_t run_lanes) { + write_bytes(addrs[first_lane], src + first_lane * stride, run_lanes * stride, mtype, + non_temporal, vmid); + }); + for (uint32_t elem = 0; elem < num_elems; ++elem) { + uint64_t mask = element_lane_masks[elem] & lane_mask & ~full_lane_mask; + store_l2_writes_ += std::popcount(mask); + while (mask) { + const uint32_t lane = std::countr_zero(mask); + mask &= ~(uint64_t{1} << lane); + write_bytes(addrs[lane] + static_cast(elem) * elem_size, + src + lane * stride + elem * elem_size, elem_size, mtype, non_temporal, vmid); + } + } + return; + } store_l2_writes_ += for_each_coalesced_lane_run( addrs, lane_mask, wf_size, stride, [&](uint32_t first_lane, uint32_t run_lanes) { write_bytes(addrs[first_lane], src + first_lane * stride, run_lanes * stride, mtype, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h index a13f800f560a..27e73ad56752 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h @@ -8,6 +8,7 @@ #include "simdojo/components/cache.h" #include +#include namespace rocjitsu { namespace amdgpu { @@ -41,13 +42,20 @@ class L1VectorCache { void set_l2(L2Cache *l2); void set_memory(GpuMemory *mem); + + /// @param element_lane_masks Empty when every element uses @p lane_mask; + /// otherwise contains exactly @p num_elems masks. In the latter form, + /// @p lane_mask is the union of lanes valid for at least one element. void load(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, uint8_t *dst, Mtype mtype, bool non_temporal, bool request_l1_bypass, uint32_t wf_size, - uint32_t vmid = 0); + uint32_t vmid = 0, std::span element_lane_masks = {}); + /// @param element_lane_masks Empty when every element uses @p lane_mask; + /// otherwise contains exactly @p num_elems masks. In the latter form, + /// @p lane_mask is the union of lanes valid for at least one element. void store(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, const uint8_t *src, Mtype mtype, bool non_temporal, uint32_t wf_size, - uint32_t vmid = 0); + uint32_t vmid = 0, std::span element_lane_masks = {}); void invalidate(uint64_t addr, uint32_t vmid = 0); void invalidate_all(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h index 56d73e0755db..39d129765e51 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h @@ -91,6 +91,10 @@ struct VectorMemState : DynamicInstState { } std::array per_lane_addr = {}; uint64_t lane_mask = 0; + /// Optional per-element lane validity. Empty means every element uses + /// lane_mask; otherwise the vector contains exactly num_elems masks and + /// lane_mask is their union. + std::vector element_lane_masks; uint64_t exec_mask = 0; ///< EXEC mask at issue time. Set by addr calc functions. ///< Writeback zeroes OOB lanes (exec_mask & ~lane_mask). uint32_t wf_size = 64; ///< Wavefront width (set from wavefront's wf_size()). diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp index 566606290a64..39eeeb8b6505 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp @@ -493,12 +493,13 @@ void GlobalMemPipeline::initiate_access(Instruction &inst, Wavefront &wf) { } if (d.is_load) { - d.response_data.resize(d.wf_size * d.num_elems * d.elem_size); + d.response_data.assign(d.wf_size * d.num_elems * d.elem_size, 0); l1_->load(d.per_lane_addr.data(), d.lane_mask, d.elem_size, d.num_elems, d.response_data.data(), - d.mtype, d.non_temporal, d.request_force_l1_bypass, d.wf_size, wf.process_id()); + d.mtype, d.non_temporal, d.request_force_l1_bypass, d.wf_size, wf.process_id(), + d.element_lane_masks); } else { l1_->store(d.per_lane_addr.data(), d.lane_mask, d.elem_size, d.num_elems, d.store_data.data(), - d.mtype, d.non_temporal, d.wf_size, wf.process_id()); + d.mtype, d.non_temporal, d.wf_size, wf.process_id(), d.element_lane_masks); } } diff --git a/emulation/rocjitsu/tests/cdna5_execution_test.cpp b/emulation/rocjitsu/tests/cdna5_execution_test.cpp index a01e2ac36194..245626232b7c 100644 --- a/emulation/rocjitsu/tests/cdna5_execution_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_execution_test.cpp @@ -3,6 +3,7 @@ #include "cdna5_sim_test_common.h" #include "decode_test_util.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna5/vbuffer.h" namespace { @@ -139,6 +140,208 @@ TEST(Gfx1250ExecutionTest, Wave32VectorComparePreservesVccHiScratch) { } } +TEST(Gfx1250ExecutionTest, VbufferB128LoadsZeroAndStoresDropPartialOobDwords) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_exec(1u); + + constexpr uint64_t kAddr = 0xC000; + constexpr uint32_t kResourceSgpr = 4; + constexpr uint32_t kLoadVgpr = 8; + constexpr uint32_t kStoreVgpr = 12; + constexpr std::array kInitial = {0x101u, 0x102u, 0x103u, 0x104u}; + constexpr std::array kStored = {0x201u, 0x202u, 0x203u, 0x204u}; + for (uint32_t i = 0; i < kInitial.size(); ++i) + sim.memory->write32(kAddr + i * sizeof(uint32_t), kInitial[i]); + + // gfx1250 NUM_RECORDS is a 45-bit byte count split across SRD words 1-3. + constexpr uint64_t kNumRecords = 10; + const std::array resource = { + static_cast(kAddr), + static_cast((kAddr >> 32) & 0x01FF'FFFFu) | + static_cast((kNumRecords & 0x7Fu) << 25), + static_cast(kNumRecords >> 7), + static_cast((kNumRecords >> 39) & 0x3Fu), + }; + for (uint32_t i = 0; i < resource.size(); ++i) + cu->write_sgpr(wf->sgpr_alloc().base + kResourceSgpr + i, resource[i]); + + cdna5::VbufferMachineInst machine{}; + machine.vdata = kLoadVgpr; + machine.rsrc = kResourceSgpr; + machine.soffset = cdna5::OPR_SREG_NULL; + machine.scope = 3; // System scope selects uncached accesses for direct memory checks. + + amdgpu::GlobalMemPipeline pipeline(&cu->l1_vector(), cu->l2()); + auto *load = + new cdna5::BufferLoadB128Vbuffer(reinterpret_cast(&machine)); + load->execute_impl(*wf); + pipeline.issue(load, *wf); + + EXPECT_EQ(cu->read_vgpr(wf->vgpr_alloc().base + kLoadVgpr + 0, 0), kInitial[0]); + EXPECT_EQ(cu->read_vgpr(wf->vgpr_alloc().base + kLoadVgpr + 1, 0), kInitial[1]); + EXPECT_EQ(cu->read_vgpr(wf->vgpr_alloc().base + kLoadVgpr + 2, 0), 0u); + EXPECT_EQ(cu->read_vgpr(wf->vgpr_alloc().base + kLoadVgpr + 3, 0), 0u); + + for (uint32_t i = 0; i < kStored.size(); ++i) + cu->write_vgpr(wf->vgpr_alloc().base + kStoreVgpr + i, 0, kStored[i]); + machine.vdata = kStoreVgpr; + auto *store = + new cdna5::BufferStoreB128Vbuffer(reinterpret_cast(&machine)); + store->execute_impl(*wf); + pipeline.issue(store, *wf); + + EXPECT_EQ(sim.memory->read32(kAddr), kStored[0]); + EXPECT_EQ(sim.memory->read32(kAddr + 4), kStored[1]); + EXPECT_EQ(sim.memory->read32(kAddr + 8), kInitial[2]); + EXPECT_EQ(sim.memory->read32(kAddr + 12), kInitial[3]); +} + +TEST(Gfx1250ExecutionTest, VbufferB64B96MixedLanesHonorStructuredPartialOob) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_exec(0x3u); + + constexpr uint64_t kAddr = 0xC080; + constexpr uint32_t kResourceSgpr = 4; + constexpr uint32_t kSoffsetSgpr = 12; + constexpr uint32_t kAddressVgpr = 4; + constexpr uint32_t kB96LoadVgpr = 8; + constexpr uint32_t kB64LoadVgpr = 12; + constexpr uint32_t kStoreVgpr = 16; + constexpr uint64_t kNumRecords = 32; + constexpr uint32_t kRawStride = 4; + constexpr uint32_t kStrideScale = 1; + constexpr uint32_t kStride = kRawStride * 4; + const std::array resource = { + static_cast(kAddr), + static_cast((kAddr >> 32) & 0x01FF'FFFFu) | + static_cast((kNumRecords & 0x7Fu) << 25), + static_cast(kNumRecords >> 7), + static_cast((kNumRecords >> 39) & 0x3Fu) | (kRawStride << 12) | + (kStrideScale << 26) | (1u << 29), + }; + for (uint32_t i = 0; i < resource.size(); ++i) + cu->write_sgpr(wf->sgpr_alloc().base + kResourceSgpr + i, resource[i]); + cu->write_sgpr(wf->sgpr_alloc().base + kSoffsetSgpr, 4); + + const uint32_t vbase = wf->vgpr_alloc().base; + cu->write_vgpr(vbase + kAddressVgpr, 0, 0); + cu->write_vgpr(vbase + kAddressVgpr + 1, 0, 0); + cu->write_vgpr(vbase + kAddressVgpr, 1, 1); + cu->write_vgpr(vbase + kAddressVgpr + 1, 1, 8); + + constexpr std::array kLane0Initial = {0x101u, 0x102u, 0x103u}; + constexpr std::array kLane1Initial = {0x201u, 0x202u, 0x203u}; + for (uint32_t i = 0; i < kLane0Initial.size(); ++i) + sim.memory->write32(kAddr + 4 + i * sizeof(uint32_t), kLane0Initial[i]); + for (uint32_t i = 0; i < kLane1Initial.size(); ++i) + sim.memory->write32(kAddr + 28 + i * sizeof(uint32_t), kLane1Initial[i]); + + cdna5::VbufferMachineInst machine{}; + machine.rsrc = kResourceSgpr; + machine.soffset = kSoffsetSgpr; + machine.vaddr = kAddressVgpr; + machine.idxen = 1; + machine.offen = 1; + machine.scope = 3; + amdgpu::GlobalMemPipeline pipeline(&cu->l1_vector(), cu->l2()); + + machine.vdata = kB64LoadVgpr; + auto *b64_load = + new cdna5::BufferLoadB64Vbuffer(reinterpret_cast(&machine)); + b64_load->execute_impl(*wf); + pipeline.issue(b64_load, *wf); + EXPECT_EQ(cu->read_vgpr(vbase + kB64LoadVgpr, 0), kLane0Initial[0]); + EXPECT_EQ(cu->read_vgpr(vbase + kB64LoadVgpr + 1, 0), kLane0Initial[1]); + EXPECT_EQ(cu->read_vgpr(vbase + kB64LoadVgpr, 1), kLane1Initial[0]); + EXPECT_EQ(cu->read_vgpr(vbase + kB64LoadVgpr + 1, 1), 0u); + + machine.vdata = kB96LoadVgpr; + auto *b96_load = + new cdna5::BufferLoadB96Vbuffer(reinterpret_cast(&machine)); + b96_load->execute_impl(*wf); + pipeline.issue(b96_load, *wf); + for (uint32_t i = 0; i < kLane0Initial.size(); ++i) + EXPECT_EQ(cu->read_vgpr(vbase + kB96LoadVgpr + i, 0), kLane0Initial[i]); + EXPECT_EQ(cu->read_vgpr(vbase + kB96LoadVgpr, 1), kLane1Initial[0]); + EXPECT_EQ(cu->read_vgpr(vbase + kB96LoadVgpr + 1, 1), 0u); + EXPECT_EQ(cu->read_vgpr(vbase + kB96LoadVgpr + 2, 1), 0u); + + constexpr std::array kLane0Stored = {0x301u, 0x302u, 0x303u}; + constexpr std::array kLane1Stored = {0x401u, 0x402u, 0x403u}; + for (uint32_t i = 0; i < kLane0Stored.size(); ++i) { + cu->write_vgpr(vbase + kStoreVgpr + i, 0, kLane0Stored[i]); + cu->write_vgpr(vbase + kStoreVgpr + i, 1, kLane1Stored[i]); + } + machine.vdata = kStoreVgpr; + auto *b96_store = + new cdna5::BufferStoreB96Vbuffer(reinterpret_cast(&machine)); + b96_store->execute_impl(*wf); + pipeline.issue(b96_store, *wf); + + for (uint32_t i = 0; i < kLane0Stored.size(); ++i) + EXPECT_EQ(sim.memory->read32(kAddr + 4 + i * sizeof(uint32_t)), kLane0Stored[i]); + EXPECT_EQ(sim.memory->read32(kAddr + kStride + 12), kLane1Stored[0]); + EXPECT_EQ(sim.memory->read32(kAddr + kStride + 16), kLane1Initial[1]); + EXPECT_EQ(sim.memory->read32(kAddr + kStride + 20), kLane1Initial[2]); +} + +TEST(Gfx1250ExecutionTest, NonReturningVbufferB64AtomicHonorsWholePayloadBounds) { + Gfx1250Sim sim; + auto *cu = sim.cu(); + auto *wf = cu->dispatch_wf(0, 0, kGfx1250ScalarSlots, 32); + ASSERT_NE(wf, nullptr); + wf->set_exec(1u); + + constexpr uint64_t kAddr = 0xC100; + constexpr uint32_t kResourceSgpr = 4; + constexpr uint32_t kDataVgpr = 8; + constexpr uint64_t kInitial = 0x0102'0304'0506'0708ULL; + constexpr uint64_t kAddend = 0x1011'1213'1415'1617ULL; + auto write_resource = [&](uint64_t num_records) { + const std::array resource = { + static_cast(kAddr), + static_cast((kAddr >> 32) & 0x01FF'FFFFu) | + static_cast((num_records & 0x7Fu) << 25), + static_cast(num_records >> 7), + static_cast((num_records >> 39) & 0x3Fu), + }; + for (uint32_t i = 0; i < resource.size(); ++i) + cu->write_sgpr(wf->sgpr_alloc().base + kResourceSgpr + i, resource[i]); + }; + + cu->write_vgpr(wf->vgpr_alloc().base + kDataVgpr, 0, static_cast(kAddend)); + cu->write_vgpr(wf->vgpr_alloc().base + kDataVgpr + 1, 0, static_cast(kAddend >> 32)); + cdna5::VbufferMachineInst machine{}; + machine.vdata = kDataVgpr; + machine.rsrc = kResourceSgpr; + machine.soffset = cdna5::OPR_SREG_NULL; + machine.scope = 3; + machine.th = 0; + amdgpu::GlobalMemPipeline pipeline(&cu->l1_vector(), cu->l2()); + + sim.memory->write64(kAddr, kInitial); + write_resource(/*num_records=*/8); + auto *exact_end = + new cdna5::BufferAtomicAddU64Vbuffer(reinterpret_cast(&machine)); + exact_end->execute_impl(*wf); + pipeline.issue(exact_end, *wf); + EXPECT_EQ(sim.memory->read64(kAddr), kInitial + kAddend); + + sim.memory->write64(kAddr, kInitial); + write_resource(/*num_records=*/6); + auto *partial_oob = + new cdna5::BufferAtomicAddU64Vbuffer(reinterpret_cast(&machine)); + partial_oob->execute_impl(*wf); + pipeline.issue(partial_oob, *wf); + EXPECT_EQ(sim.memory->read64(kAddr), kInitial); +} + TEST(Gfx1250ExecutionTest, DivScaleWritesExplicitSdstMask) { Gfx1250Sim sim; auto *cu = sim.cu(); diff --git a/emulation/rocjitsu/tests/shared_infra_test.cpp b/emulation/rocjitsu/tests/shared_infra_test.cpp index 283f2ef74f02..7e692d37c5c5 100644 --- a/emulation/rocjitsu/tests/shared_infra_test.cpp +++ b/emulation/rocjitsu/tests/shared_infra_test.cpp @@ -1763,6 +1763,114 @@ TEST(L1VectorCacheTest, UcDwordx4RoundTripPreservesVectorTransaction) { EXPECT_EQ(std::memcmp(load_bytes.data() + sizeof(kLane0), kLane1.data(), sizeof(kLane1)), 0); } +TEST(L1VectorCacheTest, PartialElementMasksSkipMaskedLoads) { + amdgpu::GpuMemory mem("test_mem"); + amdgpu::L2Cache l2("test_l2"); + amdgpu::L1VectorCache l1(&l2); + l2.set_backing_memory(&mem); + + constexpr uint64_t kAddr = 0x7880; + constexpr std::array kLane0 = {0x101u, 0x102u, 0x103u, 0x104u}; + constexpr std::array kLane1 = {0x201u, 0x202u, 0x203u, 0x204u}; + for (uint32_t elem = 0; elem < 4; ++elem) { + mem.write32(kAddr + elem * sizeof(uint32_t), kLane0[elem]); + mem.write32(kAddr + 0x40 + elem * sizeof(uint32_t), kLane1[elem]); + } + + uint64_t addrs[64] = {}; + addrs[0] = kAddr; + addrs[1] = kAddr + 0x40; + constexpr std::array kElementMasks = {0x3, 0x1, 0x1, 0x0}; + std::array bytes{}; + l1.load(addrs, /*lane_mask=*/0x3, /*elem_size=*/4, /*num_elems=*/4, bytes.data(), + amdgpu::Mtype::UC, /*non_temporal=*/false, /*request_l1_bypass=*/false, + cdna3::Isa::WF_SIZE, /*vmid=*/0, kElementMasks); + + std::array lane0{}; + std::array lane1{}; + std::memcpy(lane0.data(), bytes.data(), sizeof(lane0)); + std::memcpy(lane1.data(), bytes.data() + sizeof(lane0), sizeof(lane1)); + EXPECT_EQ(lane0, (std::array{0x101u, 0x102u, 0x103u, 0u})); + EXPECT_EQ(lane1, (std::array{0x201u, 0u, 0u, 0u})); +} + +TEST(L1VectorCacheTest, PartialElementMasksDropSkippedStores) { + amdgpu::GpuMemory mem("test_mem"); + amdgpu::L2Cache l2("test_l2"); + amdgpu::L1VectorCache l1(&l2); + l2.set_backing_memory(&mem); + + constexpr uint64_t kAddr = 0x78c0; + constexpr std::array kInitial = {0xA0u, 0xA1u, 0xA2u, 0xA3u}; + constexpr std::array kStored = {0xB0u, 0xB1u, 0xB2u, 0xB3u}; + for (uint32_t elem = 0; elem < 4; ++elem) + mem.write32(kAddr + elem * sizeof(uint32_t), kInitial[elem]); + + uint64_t addrs[64] = {}; + addrs[0] = kAddr; + std::array bytes{}; + std::memcpy(bytes.data(), kStored.data(), sizeof(kStored)); + constexpr std::array kElementMasks = {0x1, 0x1, 0x0, 0x0}; + l1.store(addrs, /*lane_mask=*/0x1, /*elem_size=*/4, /*num_elems=*/4, bytes.data(), + amdgpu::Mtype::UC, /*non_temporal=*/false, cdna3::Isa::WF_SIZE, /*vmid=*/0, + kElementMasks); + + EXPECT_EQ(mem.read32(kAddr), kStored[0]); + EXPECT_EQ(mem.read32(kAddr + 4), kStored[1]); + EXPECT_EQ(mem.read32(kAddr + 8), kInitial[2]); + EXPECT_EQ(mem.read32(kAddr + 12), kInitial[3]); +} + +TEST(L1VectorCacheTest, PartialElementMasksCoalesceFullyValidLanes) { + amdgpu::GpuMemory mem("test_mem"); + amdgpu::L2Cache l2("test_l2"); + amdgpu::L1VectorCache l1(&l2); + l2.set_backing_memory(&mem); + + constexpr uint64_t kAddr = 0x78e0; + constexpr std::array kLane0 = {0x101u, 0x102u, 0x103u, 0x104u}; + constexpr std::array kLane1 = {0x201u, 0x202u, 0x203u, 0x204u}; + constexpr std::array kLane2 = {0x301u, 0x302u, 0x303u, 0x304u}; + uint64_t addrs[64] = {}; + addrs[0] = kAddr; + addrs[1] = kAddr + sizeof(kLane0); + addrs[2] = kAddr + 2 * sizeof(kLane0); + std::array store_bytes{}; + std::memcpy(store_bytes.data(), kLane0.data(), sizeof(kLane0)); + std::memcpy(store_bytes.data() + sizeof(kLane0), kLane1.data(), sizeof(kLane1)); + std::memcpy(store_bytes.data() + 2 * sizeof(kLane0), kLane2.data(), sizeof(kLane2)); + constexpr std::array kElementMasks = {0x7, 0x7, 0x3, 0x3}; + + l1.store(addrs, /*lane_mask=*/0x7, /*elem_size=*/4, /*num_elems=*/4, store_bytes.data(), + amdgpu::Mtype::UC, /*non_temporal=*/false, cdna3::Isa::WF_SIZE, /*vmid=*/0, + kElementMasks); + EXPECT_EQ(l1.store_l2_writes(), 3u); + EXPECT_EQ(l2.backing_write_transactions(), 3u); + EXPECT_EQ(mem.read32(kAddr + 0), kLane0[0]); + EXPECT_EQ(mem.read32(kAddr + 4), kLane0[1]); + EXPECT_EQ(mem.read32(kAddr + 8), kLane0[2]); + EXPECT_EQ(mem.read32(kAddr + 12), kLane0[3]); + EXPECT_EQ(mem.read32(kAddr + 16), kLane1[0]); + EXPECT_EQ(mem.read32(kAddr + 20), kLane1[1]); + EXPECT_EQ(mem.read32(kAddr + 24), kLane1[2]); + EXPECT_EQ(mem.read32(kAddr + 28), kLane1[3]); + EXPECT_EQ(mem.read32(kAddr + 32), kLane2[0]); + EXPECT_EQ(mem.read32(kAddr + 36), kLane2[1]); + EXPECT_EQ(mem.read32(kAddr + 40), 0u); + EXPECT_EQ(mem.read32(kAddr + 44), 0u); + + std::array load_bytes{}; + l1.load(addrs, /*lane_mask=*/0x7, /*elem_size=*/4, /*num_elems=*/4, load_bytes.data(), + amdgpu::Mtype::UC, /*non_temporal=*/false, /*request_l1_bypass=*/false, + cdna3::Isa::WF_SIZE, /*vmid=*/0, kElementMasks); + EXPECT_EQ(l2.backing_read_transactions(), 3u); + EXPECT_EQ(std::memcmp(load_bytes.data(), kLane0.data(), sizeof(kLane0)), 0); + EXPECT_EQ(std::memcmp(load_bytes.data() + sizeof(kLane0), kLane1.data(), sizeof(kLane1)), 0); + std::array loaded_lane2{}; + std::memcpy(loaded_lane2.data(), load_bytes.data() + 2 * sizeof(kLane0), sizeof(loaded_lane2)); + EXPECT_EQ(loaded_lane2, (std::array{kLane2[0], kLane2[1], 0u, 0u})); +} + TEST(L1VectorCacheTest, UcDwordx4CoalescesAdjacentLanes) { amdgpu::GpuMemory mem("test_mem"); amdgpu::L2Cache l2("test_l2"); @@ -4225,7 +4333,49 @@ TEST(RdnaAddrCalcTest, Rdna4VbufferWrapsOffsetPartBeforeBaseAddition) { EXPECT_EQ(d.per_lane_addr[0], kBase); } -TEST(RdnaAddrCalcTest, Gfx1250VbufferWrapsOffsetPartBeforeBoundsCheck) { +std::array encode_gfx1250_buffer_resource(uint64_t base, uint64_t num_records, + uint32_t stride = 0, + uint32_t stride_scale = 0, + bool swizzle = false, + bool oob_select = false, uint32_t type = 0) { + return { + static_cast(base), + static_cast((base >> 32) & 0x01FF'FFFFu) | + static_cast((num_records & 0x7Fu) << 25), + static_cast(num_records >> 7), + static_cast((num_records >> 39) & 0x3Fu) | ((stride & 0x3FFFu) << 12) | + ((stride_scale & 0x3u) << 26) | (static_cast(swizzle) << 28) | + (static_cast(oob_select) << 29) | ((type & 0x3u) << 30), + }; +} + +void write_gfx1250_buffer_resource(amdgpu::ComputeUnitCore &cu, amdgpu::Wavefront &wf, + uint32_t first_sgpr, const std::array &resource) { + for (uint32_t i = 0; i < resource.size(); ++i) + cu.write_sgpr(wf.sgpr_alloc().base + first_sgpr + i, resource[i]); +} + +TEST(Gfx1250AddrCalcTest, DecodesBufferResourceFields) { + constexpr uint64_t kBase = 0x0101'2345'6789'ABCDULL; + constexpr uint64_t kNumRecords = 0x0123'4567'89ABULL; + constexpr uint32_t kRawStride = 0x1234; + auto words = encode_gfx1250_buffer_resource(kBase, kNumRecords, kRawStride, + /*stride_scale=*/3, /*swizzle=*/true, + /*oob_select=*/true, /*type=*/2); + + cdna5::BufferResource resource = + cdna5::decode_buffer_resource(words[0], words[1], words[2], words[3]); + EXPECT_EQ(resource.base_address, kBase); + EXPECT_EQ(resource.num_records, kNumRecords); + EXPECT_EQ(resource.raw_stride, kRawStride); + EXPECT_EQ(resource.stride_scale, 3); + EXPECT_EQ(resource.stride, kRawStride * 32); + EXPECT_TRUE(resource.swizzle_enabled); + EXPECT_TRUE(resource.oob_select); + EXPECT_EQ(resource.type, 2); +} + +TEST(Gfx1250AddrCalcTest, VbufferUses45BitBufferOffsetAnd57BitBase) { amdgpu::GpuMemory mem("gfx1250_vbuffer_wrap_mem"); amdgpu::L2Cache l2("gfx1250_vbuffer_wrap_l2"); amdgpu::ComputeUnitCore::Config cfg{}; @@ -4241,13 +4391,10 @@ TEST(RdnaAddrCalcTest, Gfx1250VbufferWrapsOffsetPartBeforeBoundsCheck) { ASSERT_NE(wf, nullptr); wf->set_exec(1ULL); - constexpr uint64_t kBase = 0x2'0000'1000ULL; - uint32_t sbase = wf->sgpr_alloc().base; + constexpr uint64_t kBase = 0x0010'0002'0000'1000ULL; + constexpr uint64_t kOffset = uint64_t{1} << 32; uint32_t vbase = wf->vgpr_alloc().base; - cu->write_sgpr(sbase + 4, static_cast(kBase)); - cu->write_sgpr(sbase + 5, static_cast(kBase >> 32)); - cu->write_sgpr(sbase + 6, 0x100); - cu->write_sgpr(sbase + 7, 0); + write_gfx1250_buffer_resource(*cu, *wf, 4, encode_gfx1250_buffer_resource(kBase, kOffset + 4)); cu->write_vgpr(vbase + 4, 0, 0xFFFF'8200u); cdna5::VbufferMachineInst inst{}; @@ -4259,9 +4406,105 @@ TEST(RdnaAddrCalcTest, Gfx1250VbufferWrapsOffsetPartBeforeBoundsCheck) { inst.ioffset = 0x7E00; amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 1; cdna5::mubuf_calculate_addresses(inst, *wf, d); EXPECT_EQ(d.lane_mask, 1ULL); + EXPECT_EQ(d.per_lane_addr[0], kBase + kOffset); + EXPECT_EQ(d.element_lane_masks, (std::vector{1ULL})); +} + +TEST(Gfx1250AddrCalcTest, VbufferRangeCheckDoesNotWrapAt45Bits) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_range_wrap_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_range_wrap_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_range_wrap_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(0x1FULL); + + constexpr uint64_t kBase = 0x2'0000'1000ULL; + constexpr uint64_t kMaxNumRecords = (uint64_t{1} << 45) - 1; + constexpr uint32_t kRawStride = 8192; + write_gfx1250_buffer_resource( + *cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, kMaxNumRecords, kRawStride, /*stride_scale=*/1)); + uint32_t vbase = wf->vgpr_alloc().base; + cu->write_vgpr(vbase + 4, 0, 0); + cu->write_vgpr(vbase + 5, 0, 0); + cu->write_vgpr(vbase + 4, 1, uint32_t{1} << 30); + cu->write_vgpr(vbase + 5, 1, 0); + cu->write_vgpr(vbase + 4, 2, (uint32_t{1} << 30) - 1); + cu->write_vgpr(vbase + 5, 2, 32763); + cu->write_vgpr(vbase + 4, 3, (uint32_t{1} << 30) - 1); + cu->write_vgpr(vbase + 5, 3, 32764); + cu->write_vgpr(vbase + 4, 4, uint32_t{1} << 30); + cu->write_vgpr(vbase + 5, 4, 1); + + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + inst.idxen = 1; + inst.offen = 1; + inst.vaddr = 4; + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 1; + cdna5::mubuf_calculate_addresses(inst, *wf, d); + EXPECT_EQ(d.lane_mask, 0x5ULL); + EXPECT_EQ(d.element_lane_masks, (std::vector{0x5ULL})); EXPECT_EQ(d.per_lane_addr[0], kBase); + EXPECT_EQ(d.per_lane_addr[1], 0ULL); + EXPECT_EQ(d.per_lane_addr[2], kBase + kMaxNumRecords - 4); + EXPECT_EQ(d.per_lane_addr[3], 0ULL); + EXPECT_EQ(d.per_lane_addr[4], 0ULL); +} + +TEST(Gfx1250AddrCalcTest, VbufferRangeCheckAcceptsExactEndOnly) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_exact_end_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_exact_end_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_exact_end_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(0x3ULL); + + constexpr uint64_t kBase = 0x2'0000'1800ULL; + write_gfx1250_buffer_resource(*cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, /*num_records=*/8)); + uint32_t vbase = wf->vgpr_alloc().base; + cu->write_vgpr(vbase + 4, 0, 4); + cu->write_vgpr(vbase + 4, 1, 5); + + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + inst.offen = 1; + inst.vaddr = 4; + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 1; + cdna5::mubuf_calculate_addresses(inst, *wf, d); + EXPECT_EQ(d.lane_mask, 0x1ULL); + EXPECT_EQ(d.element_lane_masks, (std::vector{0x1ULL})); + EXPECT_EQ(d.per_lane_addr[0], kBase + 4); + EXPECT_EQ(d.per_lane_addr[1], 0ULL); } TEST(Gfx1250AddrCalcTest, VbufferZeroNumRecordsMasksAllLanes) { @@ -4280,9 +4523,9 @@ TEST(Gfx1250AddrCalcTest, VbufferZeroNumRecordsMasksAllLanes) { ASSERT_NE(wf, nullptr); wf->set_exec(0x3ULL); - // A null optional pointer is represented by an all-zero descriptor. Its - // zero-sized range makes every access out of bounds, so loads return zero - // and stores are dropped without touching address zero. + // The rocjitsu runtime represents a null optional pointer with an all-zero + // descriptor. This is a runtime convention, not a distinguished ISA + // descriptor encoding. Its zero-sized range makes every access out of bounds. uint32_t vbase = wf->vgpr_alloc().base; cu->write_vgpr(vbase + 4, 0, 0); cu->write_vgpr(vbase + 4, 1, 0x1000); @@ -4295,6 +4538,8 @@ TEST(Gfx1250AddrCalcTest, VbufferZeroNumRecordsMasksAllLanes) { inst.vaddr = 4; amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 1; cdna5::mubuf_calculate_addresses(inst, *wf, d); EXPECT_EQ(d.exec_mask, 0x3ULL); EXPECT_EQ(d.lane_mask, 0ULL); @@ -4319,16 +4564,13 @@ TEST(Gfx1250AddrCalcTest, VbufferStructuredStrideChecksIndexBounds) { wf->set_exec(0x3ULL); constexpr uint64_t kBase = 0x2'0000'1000ULL; - constexpr uint32_t kNumRecords = 2; + constexpr uint32_t kNumBytes = 32; constexpr uint32_t kStride = 16; - uint32_t sbase = wf->sgpr_alloc().base; uint32_t vbase = wf->vgpr_alloc().base; - cu->write_sgpr(sbase + 40, static_cast(kBase)); - cu->write_sgpr(sbase + 41, static_cast(kBase >> 32) | (kNumRecords << 25)); - cu->write_sgpr(sbase + 42, 0); - cu->write_sgpr(sbase + 43, kStride << 12); - cu->write_vgpr(vbase + 4, 0, kNumRecords - 1); - cu->write_vgpr(vbase + 4, 1, kNumRecords); + write_gfx1250_buffer_resource(*cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, kNumBytes, kStride)); + cu->write_vgpr(vbase + 4, 0, 1); + cu->write_vgpr(vbase + 4, 1, 2); cdna5::VbufferMachineInst inst{}; inst.rsrc = 40; @@ -4338,13 +4580,246 @@ TEST(Gfx1250AddrCalcTest, VbufferStructuredStrideChecksIndexBounds) { inst.vaddr = 4; amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 1; cdna5::mubuf_calculate_addresses(inst, *wf, d); EXPECT_EQ(d.exec_mask, 0x3ULL); EXPECT_EQ(d.lane_mask, 0x1ULL); - EXPECT_EQ(d.per_lane_addr[0], kBase + (kNumRecords - 1) * kStride); + EXPECT_EQ(d.per_lane_addr[0], kBase + kStride); EXPECT_EQ(d.per_lane_addr[1], 0ULL); } +TEST(Gfx1250AddrCalcTest, VbufferChecksB64B96AndB128DwordsIndependently) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_partial_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_partial_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_partial_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(1ULL); + + constexpr uint64_t kBase = 0x2'0000'2000ULL; + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + + write_gfx1250_buffer_resource(*cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, /*num_records=*/6)); + amdgpu::VectorMemState b64(amdgpu::GLOBAL_MEM); + b64.elem_size = 4; + b64.num_elems = 2; + cdna5::mubuf_calculate_addresses(inst, *wf, b64); + EXPECT_EQ(b64.lane_mask, 1ULL); + EXPECT_EQ(b64.element_lane_masks, (std::vector{1ULL, 0ULL})); + + write_gfx1250_buffer_resource(*cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, /*num_records=*/10)); + amdgpu::VectorMemState b96(amdgpu::GLOBAL_MEM); + b96.elem_size = 4; + b96.num_elems = 3; + cdna5::mubuf_calculate_addresses(inst, *wf, b96); + EXPECT_EQ(b96.lane_mask, 1ULL); + EXPECT_EQ(b96.element_lane_masks, (std::vector{1ULL, 1ULL, 0ULL})); + + amdgpu::VectorMemState b128(amdgpu::GLOBAL_MEM); + b128.elem_size = 4; + b128.num_elems = 4; + cdna5::mubuf_calculate_addresses(inst, *wf, b128); + EXPECT_EQ(b128.lane_mask, 1ULL); + EXPECT_EQ(b128.element_lane_masks, (std::vector{1ULL, 1ULL, 0ULL, 0ULL})); +} + +TEST(Gfx1250AddrCalcTest, VbufferNegativeIoffsetCannotReachL1) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_negative_ioffset_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_negative_ioffset_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_negative_ioffset_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(1ULL); + + constexpr uint64_t kBase = 0x2'0000'2400ULL; + write_gfx1250_buffer_resource(*cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, /*num_records=*/4)); + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + inst.ioffset = 0x00FF'FFFCu; // -4 as a signed 24-bit VBUFFER IOFFSET. + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 2; + cdna5::mubuf_calculate_addresses(inst, *wf, d); + + EXPECT_EQ(d.exec_mask, 1ULL); + EXPECT_EQ(d.lane_mask, 0ULL); + EXPECT_EQ(d.element_lane_masks, (std::vector{0ULL, 0ULL})); + EXPECT_EQ(d.per_lane_addr[0], 0ULL); +} + +TEST(Gfx1250AddrCalcTest, VbufferSoffsetParticipatesInNumRecordsAndStrideBounds) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_soffset_bounds_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_soffset_bounds_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_soffset_bounds_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(1ULL); + + constexpr uint64_t kBase = 0x2'0000'2800ULL; + write_gfx1250_buffer_resource( + *cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, /*num_records=*/16, /*stride=*/16, + /*stride_scale=*/0, /*swizzle=*/false, + /*oob_select=*/true)); + + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = 8; + + uint32_t sbase = wf->sgpr_alloc().base; + cu->write_sgpr(sbase + 8, 8); + amdgpu::VectorMemState exact_end(amdgpu::GLOBAL_MEM); + exact_end.elem_size = 4; + exact_end.num_elems = 2; + cdna5::mubuf_calculate_addresses(inst, *wf, exact_end); + EXPECT_EQ(exact_end.lane_mask, 1ULL); + EXPECT_EQ(exact_end.element_lane_masks, (std::vector{1ULL, 1ULL})); + EXPECT_EQ(exact_end.per_lane_addr[0], kBase + 8); + + cu->write_sgpr(sbase + 8, 9); + amdgpu::VectorMemState one_byte_over(amdgpu::GLOBAL_MEM); + one_byte_over.elem_size = 4; + one_byte_over.num_elems = 2; + cdna5::mubuf_calculate_addresses(inst, *wf, one_byte_over); + EXPECT_EQ(one_byte_over.lane_mask, 1ULL); + EXPECT_EQ(one_byte_over.element_lane_masks, (std::vector{1ULL, 0ULL})); + EXPECT_EQ(one_byte_over.per_lane_addr[0], kBase + 9); +} + +TEST(Gfx1250AddrCalcTest, VbufferOobSelectAlsoChecksRecordStride) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_oob_select_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_oob_select_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_oob_select_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(1ULL); + + constexpr uint64_t kBase = 0x2'0000'3000ULL; + write_gfx1250_buffer_resource( + *cu, *wf, 40, + encode_gfx1250_buffer_resource(kBase, /*num_records=*/64, /*stride=*/8, + /*stride_scale=*/0, /*swizzle=*/false, + /*oob_select=*/true)); + cu->write_vgpr(wf->vgpr_alloc().base + 4, 0, 4); + + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + inst.offen = 1; + inst.vaddr = 4; + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 2; + cdna5::mubuf_calculate_addresses(inst, *wf, d); + EXPECT_EQ(d.lane_mask, 1ULL); + EXPECT_EQ(d.element_lane_masks, (std::vector{1ULL, 0ULL})); +} + +TEST(Gfx1250AddrCalcTest, VbufferSwizzleDefersBoundsWithNoElementMasks) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_swizzle_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_swizzle_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_swizzle_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(1ULL); + write_gfx1250_buffer_resource( + *cu, *wf, 40, + encode_gfx1250_buffer_resource(/*base=*/0x4000, /*num_records=*/0, /*stride=*/16, + /*stride_scale=*/0, /*swizzle=*/true)); + + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 4; + d.num_elems = 4; + cdna5::mubuf_calculate_addresses(inst, *wf, d); + EXPECT_EQ(d.lane_mask, 1ULL); + EXPECT_TRUE(d.element_lane_masks.empty()); +} + +TEST(Gfx1250AddrCalcTest, VbufferAtomicChecksWholePayload) { + amdgpu::GpuMemory mem("gfx1250_vbuffer_atomic_oob_mem"); + amdgpu::L2Cache l2("gfx1250_vbuffer_atomic_oob_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA5; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 128; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("gfx1250_vbuffer_atomic_oob_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 128, 16); + ASSERT_NE(wf, nullptr); + wf->set_exec(1ULL); + write_gfx1250_buffer_resource(*cu, *wf, 40, + encode_gfx1250_buffer_resource(/*base=*/0x5000, /*num_records=*/6)); + + cdna5::VbufferMachineInst inst{}; + inst.rsrc = 40; + inst.soffset = cdna5::OPR_SREG_NULL; + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + d.elem_size = 8; + d.num_elems = 1; + d.atomic_op = amdgpu::AtomicOp::ADD; + cdna5::mubuf_calculate_addresses(inst, *wf, d); + EXPECT_EQ(d.lane_mask, 0ULL); + EXPECT_EQ(d.element_lane_masks, (std::vector{0ULL})); + EXPECT_EQ(d.per_lane_addr[0], 0ULL); +} + void expect_vector_lane_reads_use_own_wave_vgprs(rj_code_arch_t arch) { amdgpu::GpuMemory mem("rdna_lane_read_mem"); amdgpu::L2Cache l2("rdna_lane_read_l2"); From 141b1094326c36ed383c530ac78ded1388b2c06a Mon Sep 17 00:00:00 2001 From: Tony G Date: Wed, 19 Aug 2026 12:09:15 -0700 Subject: [PATCH 23/27] [rocjitsu] add per-XCD workgroup dispatch observability (#10283) A HW queue is bound to a single XCD by SoC::assign_queue_cp(), so every workgroup of every dispatch on that queue is placed by that one XCD's command processor on that one XCD's compute units. On the 8-XCD CDNA4 configs a single-queue application reaches 32 of the 256 CUs the topology advertises, but nothing in the tree measured this. Count workgroups placed per command processor and expose the per-XCD histogram from the SoC, then pin current behavior in xcd_distribution_test: one queue confines the whole grid to one XCD, and only opening multiple queues reaches multiple XCDs. The follow-on fan-out work flips the first expectation. (cherry picked from commit 53a939bd00021300861462846d3727433085c82f) --- .../rocjitsu/vm/amdgpu/command_processor.cpp | 1 + .../rocjitsu/vm/amdgpu/command_processor.h | 14 ++ .../lib/rocjitsu/src/rocjitsu/vm/soc.h | 17 ++ emulation/rocjitsu/tests/CMakeLists.txt | 1 + .../rocjitsu/tests/xcd_distribution_test.cpp | 175 ++++++++++++++++++ 5 files changed, 208 insertions(+) create mode 100644 emulation/rocjitsu/tests/xcd_distribution_test.cpp diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp index 28723c0d9d4e..28afd4705dff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp @@ -1232,6 +1232,7 @@ uint32_t CommandProcessor::dispatch_workgroups(DispatchEntry &entry) { ++entry.dispatched_wgs; ++dispatched; + dispatched_workgroups_.fetch_add(1, std::memory_order_relaxed); return true; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h index 68b216910ffe..06c069314c7b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h @@ -176,6 +176,19 @@ class CommandProcessor : public simdojo::Component { size_t dispatched_count() const { return total_dispatched_; } + /// @brief Total workgroups this CP has placed on its own XCD's compute units. + /// @details Distinct from dispatched_count(), which counts AQL packets. This is + /// a lifetime running total, not a per-dispatch figure: to see how one grid was + /// spread, snapshot every XCD's counter before the dispatch and diff afterwards. + /// + /// Atomic because the increment happens on the dispatch path under + /// hw_queue_mutex_ while SoC::dispatched_workgroups_per_xcd() reads every XCD's + /// counter without that lock. Relaxed ordering is enough: this is a cumulative + /// statistic, not a synchronization point. + [[nodiscard]] uint64_t dispatched_workgroups() const { + return dispatched_workgroups_.load(std::memory_order_relaxed); + } + size_t next_cu_index() const { return next_cu_; } const std::vector &dispatch_ports() const { return dispatch_ports_; } @@ -337,6 +350,7 @@ class CommandProcessor : public simdojo::Component { SdmaPacketDialect sdma_packet_dialect_ = SdmaPacketDialect::Legacy; uint32_t next_dispatch_id_ = 1; size_t total_dispatched_ = 0; + std::atomic dispatched_workgroups_{0}; struct ClusterWorkgroupPlacement { ComputeUnitCore *cu = nullptr; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h index e243ac23a05d..090bb7d112a3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h @@ -113,6 +113,23 @@ class SoC : public simdojo::CompositeComponent { return xcds_[idx]->command_processor(); } + /// @brief Per-XCD histogram of workgroups placed by each XCD's command processor. + /// + /// @details Index i is the count for xcd(i). Each entry is that CP's lifetime + /// running total, so this describes one grid only when it is the sole dispatch, + /// as in the tests; otherwise diff a snapshot taken before the dispatch against + /// one taken after. A single non-zero bucket means the work ran on one XCD. + /// @returns One entry per XCD, in XCD index order. + std::vector dispatched_workgroups_per_xcd() const { + std::vector counts; + counts.reserve(xcds_.size()); + for (const auto *xcd_ptr : xcds_) { + const auto *cp = xcd_ptr->command_processor(); + counts.push_back(cp ? cp->dispatched_workgroups() : 0); + } + return counts; + } + /// @brief Apply a function to all XCD command processors. /// /// @details Used for broadcast operations (setting callbacks, flushing, etc.) diff --git a/emulation/rocjitsu/tests/CMakeLists.txt b/emulation/rocjitsu/tests/CMakeLists.txt index 08d88035b566..9c45b1092cd6 100644 --- a/emulation/rocjitsu/tests/CMakeLists.txt +++ b/emulation/rocjitsu/tests/CMakeLists.txt @@ -402,6 +402,7 @@ add_executable( daemon_api_test.cpp matmul_test.cpp vector_add_test.cpp + xcd_distribution_test.cpp cdna5_architecture_test.cpp cdna5_cluster_test.cpp cdna5_dispatch_memory_test.cpp diff --git a/emulation/rocjitsu/tests/xcd_distribution_test.cpp b/emulation/rocjitsu/tests/xcd_distribution_test.cpp new file mode 100644 index 000000000000..ff8aa303e514 --- /dev/null +++ b/emulation/rocjitsu/tests/xcd_distribution_test.cpp @@ -0,0 +1,175 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file xcd_distribution_test.cpp +/// @brief How a single AQL dispatch is spread across the XCDs of a multi-XCD SoC. + +#include "aql_queue.h" +#include "test_paths.h" + +#include "embedded_schema.h" +#include "rocjitsu/code/builders/instruction_builder.h" +#include "rocjitsu/config/config_loader.h" +#include "rocjitsu/vm/amdgpu/gpu_memory.h" +#include "rocjitsu/vm/soc.h" + +#include "simdojo/sim/simulation.h" +#include "simdojo/sim/topology.h" + +#include "rocjitsu/base/rj_compiler.h" +RJ_DIAGNOSTIC_PUSH +RJ_DIAGNOSTIC_IGNORE_PEDANTIC +#include "hsa/AMDHSAKernelDescriptor.h" +RJ_DIAGNOSTIC_POP + +#include + +#include +#include +#include +#include +#include + +namespace { + +using namespace rocjitsu; + +const std::string CONFIG_PATH = test::config_path("gfx950_cdna4.json"); + +constexpr uint32_t kTotalXcds = 8; +constexpr uint32_t kCusPerXcd = 32; // 4 SEs x 8 CUs +constexpr uint32_t kTotalCus = kTotalXcds * kCusPerXcd; +constexpr uint64_t kKdAddr = 0x10000; +constexpr uint32_t kWavefrontSize = 64; + +/// A loaded gfx950 SoC plus a trivial s_endpgm kernel resident in GPU memory. +struct XcdDistributionFixture { + config::LoadedConfig loaded; + std::unique_ptr engine; + SoC *soc = nullptr; + amdgpu::GpuMemory *memory = nullptr; + + XcdDistributionFixture() : loaded(config::load_config(CONFIG_PATH, rocjitsu::kEmbeddedSchema)) { + soc = loaded.soc(); + memory = loaded.memory(); + engine = std::make_unique(loaded.engine_config); + engine->topology().set_root(loaded.take_root()); + loaded.wire_links(engine->topology()); + engine->create(); + + using namespace rocr::llvm::amdhsa; + kernel_descriptor_t kd{}; + kd.kernel_code_entry_byte_offset = sizeof(kernel_descriptor_t); + AMDHSA_BITS_SET(kd.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, + ((256 / 8) - 1)); // CDNA4 VGPR granularity is 8 + AMDHSA_BITS_SET(kd.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT, + ((104 / 8) - 1)); + AMDHSA_BITS_SET(kd.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT, 2); + memory->load_image(reinterpret_cast(&kd), sizeof(kd), kKdAddr); + memory->write32(kKdAddr + sizeof(kernel_descriptor_t), + build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA4)); + } +}; + +/// Index of the XCD whose command processor is @p cp. +uint32_t assigned_xcd_index(const SoC &soc, const amdgpu::CommandProcessor *cp) { + for (uint32_t xi = 0; xi < soc.num_xcds(); ++xi) + if (soc.xcd(xi)->command_processor() == cp) + return xi; + ADD_FAILURE() << "command processor does not belong to this SoC"; + return 0; +} + +} // namespace + +// One HW queue is placed on one XCD by SoC::assign_queue_cp(), which is the +// selector the KFD CREATE_QUEUE path uses. Every workgroup of a dispatch on that +// queue is therefore placed by that one XCD's command processor, on that one +// XCD's compute units. +// +// This pins CURRENT behavior, which is a fidelity gap: a multi-XCD part running +// as one partition spreads a dispatch over every XCD. The topology here +// advertises 256 CUs, so a single-queue application reaches an eighth of them. +// Follow-on work in this stack flips this expectation to an even spread. +TEST(XcdDistributionTest, SingleQueueGridLandsOnOneXcd) { + XcdDistributionFixture fx; + ASSERT_EQ(fx.soc->num_xcds(), kTotalXcds); + ASSERT_EQ(fx.soc->all_cus().size(), kTotalCus); + + auto *cp = fx.soc->assign_queue_cp(); + ASSERT_NE(cp, nullptr); + test::AqlQueue queue(fx.memory, cp); + queue.dispatch(kKdAddr, kTotalCus * kWavefrontSize, kWavefrontSize); + + fx.engine->run(); + + auto counts = fx.soc->dispatched_workgroups_per_xcd(); + ASSERT_EQ(counts.size(), kTotalXcds); + EXPECT_EQ(std::accumulate(counts.begin(), counts.end(), uint64_t{0}), kTotalCus); + + size_t xcds_used = 0; + for (auto count : counts) + xcds_used += count > 0 ? 1 : 0; + EXPECT_EQ(xcds_used, 1u) << "expected the whole grid confined to one XCD"; + + // ...and it must be the XCD the queue was actually assigned to. Cardinality + // alone would still pass if the grid ran on the wrong one. + EXPECT_EQ(counts[assigned_xcd_index(*fx.soc, cp)], kTotalCus); +} + +// assign_queue_cp() rotates queues across XCDs, so N queues do reach N XCDs. +// This is the only XCD spreading that exists today, and it only helps an +// application that opens more than one HW queue. +TEST(XcdDistributionTest, QueuesRotateAcrossXcds) { + XcdDistributionFixture fx; + ASSERT_EQ(fx.soc->num_xcds(), kTotalXcds); + ASSERT_EQ(fx.soc->all_cus().size(), kTotalCus); + + constexpr uint32_t kWgsPerQueue = kCusPerXcd; + std::vector> queues; + for (uint32_t qi = 0; qi < kTotalXcds; ++qi) { + auto *cp = fx.soc->assign_queue_cp(); + ASSERT_NE(cp, nullptr); + uint64_t ring = 0xF0000000ULL + qi * 0x100000ULL; + queues.push_back(std::make_unique(fx.memory, cp, ring, 4096, ring + 0x10000, + ring + 0x10008, ring + 0x10010)); + queues.back()->dispatch(kKdAddr, kWgsPerQueue * kWavefrontSize, kWavefrontSize); + } + + fx.engine->run(); + + auto counts = fx.soc->dispatched_workgroups_per_xcd(); + ASSERT_EQ(counts.size(), kTotalXcds); + for (uint32_t xi = 0; xi < kTotalXcds; ++xi) + EXPECT_EQ(counts[xi], kWgsPerQueue) << "xcd" << xi; +} + +// The counter is documented as a lifetime running total, so a second dispatch on +// the same queue must add to it rather than replace it. Both other tests submit +// one packet per command processor, so they would still pass if the counter were +// reset or overwritten per packet; this samples the histogram around the second +// dispatch and checks the delta as well as the accumulated total. +TEST(XcdDistributionTest, CounterAccumulatesAcrossDispatchesOnOneQueue) { + XcdDistributionFixture fx; + ASSERT_EQ(fx.soc->num_xcds(), kTotalXcds); + ASSERT_EQ(fx.soc->all_cus().size(), kTotalCus); + + auto *cp = fx.soc->assign_queue_cp(); + ASSERT_NE(cp, nullptr); + const uint32_t xi = assigned_xcd_index(*fx.soc, cp); + + constexpr uint32_t kFirstWgs = kCusPerXcd; + constexpr uint32_t kSecondWgs = kCusPerXcd / 2; + + test::AqlQueue queue(fx.memory, cp); + queue.dispatch(kKdAddr, kFirstWgs * kWavefrontSize, kWavefrontSize); + queue.dispatch(kKdAddr, kSecondWgs * kWavefrontSize, kWavefrontSize); + fx.engine->run(); + + auto counts = fx.soc->dispatched_workgroups_per_xcd(); + ASSERT_EQ(counts.size(), kTotalXcds); + EXPECT_EQ(counts[xi], kFirstWgs + kSecondWgs) + << "counter must accumulate across packets, not restart per packet"; + EXPECT_EQ(std::accumulate(counts.begin(), counts.end(), uint64_t{0}), + uint64_t{kFirstWgs} + kSecondWgs); +} From 6bb4c5a9597018746a91f19963f5365708d16184 Mon Sep 17 00:00:00 2001 From: Erick Ochoa Lopez Date: Wed, 19 Aug 2026 15:26:37 -0400 Subject: [PATCH 24/27] [rocjitsu] Refactor test encoding handling in execution tests (NFC) (#10414) ## Motivation Better code quality in tests. ## Technical Details Share mnemonic prefix helpers and use typed templates for generated ISA encoding tables, eliminating duplicate structs and unsafe casts. ## Issue Tracking N/A ## Test Plan Test on CI ## Test Result Test pass ## Submission Checklist - [X] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. (cherry picked from commit a0fb11bc1795d579bef31d802cb4db65d721cd97) --- .../tests/decode_execute_benchmark.cpp | 39 ++++++------------- .../instruction_execution_harness_test.cpp | 20 +++------- .../rocjitsu/tests/test_encodings_util.h | 20 ++++++++++ 3 files changed, 37 insertions(+), 42 deletions(-) create mode 100644 emulation/rocjitsu/tests/test_encodings_util.h diff --git a/emulation/rocjitsu/tests/decode_execute_benchmark.cpp b/emulation/rocjitsu/tests/decode_execute_benchmark.cpp index 7e8615512b86..138dcc0c0d59 100644 --- a/emulation/rocjitsu/tests/decode_execute_benchmark.cpp +++ b/emulation/rocjitsu/tests/decode_execute_benchmark.cpp @@ -19,6 +19,7 @@ #include "rocjitsu/vm/amdgpu/gpu_memory.h" #include "rocjitsu/vm/amdgpu/l2_cache.h" #include "rocjitsu/vm/amdgpu/wavefront.h" +#include "test_encodings_util.h" #include "util/except.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/test_encodings.h" @@ -39,12 +40,6 @@ namespace { using namespace rocjitsu; using Clock = std::chrono::steady_clock; -/// @brief Common test encoding entry (matches all ISA test_encodings.h). -struct TestEncEntry { - std::string_view mnemonic; - std::array words; -}; - enum class InstCategory : uint8_t { SCALAR_ALU, VECTOR_ALU, MEMORY }; struct CorpusEntry { @@ -75,15 +70,13 @@ inline bool should_skip(std::string_view mn) { "s_icache_inv", "s_sendmsghalt", "v_readlane", "v_writelane", "v_readfirstlane", "v_mfma_", "v_permlane", "v_smfma_", "v_wmma_", "v_swmmac_", }; - for (auto p : SKIP) - if (mn.substr(0, p.size()) == p) - return true; - return false; + return mnemonic_has_any_prefix(mn, SKIP); } /// @brief Build a corpus of decodable instructions from test data. /// Only filters by skip list and decodability — does not try execute. -std::vector build_corpus(const TestEncEntry *encodings, size_t num_encodings, +template +std::vector build_corpus(const Encoding *encodings, size_t num_encodings, Decoder &decoder) { std::vector corpus; @@ -116,7 +109,8 @@ struct TimingResult { }; /// @brief Run the benchmark for a given ISA. -void run_benchmark(rj_code_arch_t arch, std::string_view arch_name, const TestEncEntry *encodings, +template +void run_benchmark(rj_code_arch_t arch, std::string_view arch_name, const Encoding *encodings, size_t num_encodings) { // Set up CU + wavefront. amdgpu::GpuMemory gpu_mem(std::string(arch_name) + "_bench_mem"); @@ -242,22 +236,13 @@ void run_benchmark(rj_code_arch_t arch, std::string_view arch_name, const TestEn // --- Benchmark tests --- -TEST(DecodeExecuteBenchmark, Cdna4) { - run_benchmark(ROCJITSU_CODE_ARCH_CDNA4, "cdna4", - reinterpret_cast(cdna4::test_data::ENCODINGS), - cdna4::test_data::NUM_ENCODINGS); -} +#define RUN_BENCHMARK(ISA_NS, ARCH_ENUM, ARCH_STR) \ + run_benchmark(ARCH_ENUM, ARCH_STR, ISA_NS::test_data::ENCODINGS, ISA_NS::test_data::NUM_ENCODINGS) -TEST(DecodeExecuteBenchmark, Rdna4) { - run_benchmark(ROCJITSU_CODE_ARCH_RDNA4, "rdna4", - reinterpret_cast(rdna4::test_data::ENCODINGS), - rdna4::test_data::NUM_ENCODINGS); -} +TEST(DecodeExecuteBenchmark, Cdna4) { RUN_BENCHMARK(cdna4, ROCJITSU_CODE_ARCH_CDNA4, "cdna4"); } -TEST(DecodeExecuteBenchmark, Gfx1250) { - run_benchmark(ROCJITSU_CODE_ARCH_CDNA5, "gfx1250", - reinterpret_cast(cdna5::test_data::ENCODINGS), - cdna5::test_data::NUM_ENCODINGS); -} +TEST(DecodeExecuteBenchmark, Rdna4) { RUN_BENCHMARK(rdna4, ROCJITSU_CODE_ARCH_RDNA4, "rdna4"); } + +TEST(DecodeExecuteBenchmark, Gfx1250) { RUN_BENCHMARK(cdna5, ROCJITSU_CODE_ARCH_CDNA5, "gfx1250"); } } // namespace diff --git a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp index 0ba0b81fc34e..d03c676ca05a 100644 --- a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp +++ b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp @@ -34,6 +34,7 @@ #include "rocjitsu/vm/amdgpu/hwreg.h" #include "rocjitsu/vm/amdgpu/l2_cache.h" #include "rocjitsu/vm/amdgpu/wavefront.h" +#include "test_encodings_util.h" #include "util/data_types.h" #include "util/except.h" #include "util/simd.h" @@ -74,12 +75,6 @@ namespace { using namespace rocjitsu; -/// @brief Common test encoding entry (matches all ISA test_encodings.h). -struct TestEncEntry { - std::string_view mnemonic; - std::array words; -}; - constexpr uint32_t pack16(uint16_t lo, uint16_t hi) { return static_cast(lo) | (static_cast(hi) << 16); } @@ -237,10 +232,7 @@ inline bool should_skip_inst(std::string_view mn) { "s_setreg", "s_rfe", }; - for (auto p : SKIP_PREFIXES) - if (mn.substr(0, p.size()) == p) - return true; - return false; + return mnemonic_has_any_prefix(mn, SKIP_PREFIXES); } constexpr std::array EXPECTED_CDNA_UNIMPLEMENTED = {"s_setvskip"}; @@ -271,8 +263,9 @@ const HarnessExpectation *harness_expectation(std::string_view arch_name) { } /// @brief Helper to run all test encodings for a given ISA. +template void run_execution_harness(rj_code_arch_t arch, std::string_view arch_name, - const TestEncEntry *encodings, size_t num_encodings) { + const Encoding *encodings, size_t num_encodings) { // Set up minimal CU with zeroed memory. amdgpu::GpuMemory gpu_mem(std::string(arch_name) + "_mem"); amdgpu::L2Cache l2(std::string(arch_name) + "_l2"); @@ -387,11 +380,8 @@ void run_execution_harness(rj_code_arch_t arch, std::string_view arch_name, // --- Parameterized tests per ISA --- -// Helper macro: cast the ISA-specific TestEncoding array to the common layout. -// The struct layout (string_view + array) is identical across all ISAs. #define RUN_HARNESS(ISA_NS, ARCH_ENUM, ARCH_STR) \ - run_execution_harness(ARCH_ENUM, ARCH_STR, \ - reinterpret_cast(ISA_NS::test_data::ENCODINGS), \ + run_execution_harness(ARCH_ENUM, ARCH_STR, ISA_NS::test_data::ENCODINGS, \ ISA_NS::test_data::NUM_ENCODINGS) TEST(InstructionExecutionHarness, Cdna1) { RUN_HARNESS(cdna1, ROCJITSU_CODE_ARCH_CDNA1, "cdna1"); } diff --git a/emulation/rocjitsu/tests/test_encodings_util.h b/emulation/rocjitsu/tests/test_encodings_util.h new file mode 100644 index 000000000000..b87352e304a9 --- /dev/null +++ b/emulation/rocjitsu/tests/test_encodings_util.h @@ -0,0 +1,20 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#pragma once + +#include +#include + +namespace rocjitsu { + +template +inline bool mnemonic_has_any_prefix(std::string_view mnemonic, + const std::string_view (&prefixes)[EncodingCount]) { + for (std::string_view prefix : prefixes) + if (mnemonic.starts_with(prefix)) + return true; + return false; +} + +} // namespace rocjitsu From 322ac26b44e2e1898c50e5ffb11cc6c45abca8b0 Mon Sep 17 00:00:00 2001 From: "Rosa, Ada" Date: Wed, 19 Aug 2026 15:12:28 -0700 Subject: [PATCH 25/27] feat(emulation): debug emulated GPU kernels with real ROCgdb (#9844) ## Motivation Debugging a GPU kernel has required a physical AMD GPU. rocjitsu already emulates the AMD KFD closely enough to run real ROCr/HIP workloads, but it had no debug surface: `AMDKFD_IOC_DBG_TRAP` was unimplemented, waves could not be stopped, and there was no CWSR state for a debugger to read or write. This PR closes that gap. **Real ROCgdb and real `librocm-dbgapi`, unmodified, now attach to a workload running on the emulated GPU and debug its kernels end to end**, with no AMD hardware present: breakpoints, single-step, watchpoints, multi-wave `info threads`, source-level locals out of private/scratch, SIGILL and SIGSEGV on GPU faults, and clean detach. One command drives it: ```bash mirage run --profile mi350x --gdb -- ./my_hip_app ``` The bar this is measured against is the official ROCgdb `gdb.rocm` test suite, which is written for hardware and knows nothing about the emulator. All 89 of its files pass. ## Technical Details All KFD debug behaviour is mirrored from the real driver source (`amd/amdkfd/{kfd_chardev.c,kfd_debug.c,kfd_topology.c}`, amdgpu-6.16.13), cross-checked against a physical MI300X and against the in-tree `projects/rocdbgapi` client. Changes are confined to `emulation/`. **KFD debug protocol** (`kmd/linux/{simulated_kfd,remote_driver,rj_daemon,interposer}`) - `DBG_TRAP` sub-operation dispatcher with the driver's validation ladder, authorized by a *real* ptrace relationship and marshalled over the daemon. The debugger and the inferior are separate processes, so in-process mode cannot host this and daemon mode is mandatory. - Debug sessions keyed by inferior pid, so ROCgdb can attach before the inferior ever opens `/dev/kfd`; full attach/detach lifecycle, `GET_DEVICE_SNAPSHOT`, `GET_QUEUE_SNAPSHOT`, `SET_EXCEPTIONS_ENABLED` / `SET_FLAGS`, and `SET_WAVE_LAUNCH_OVERRIDE` validated against the gfx9.4 trap mask. - Debuggee memory access authorized through the daemon (debugger-opened proc memory and pinned process descriptors travel with the enable request), preserving remote `DONTFORK` semantics and naming the synthetic KFD marker as `/dev/kfd` in proc-map snapshots so fork and `gcore` behave as they do on hardware. - Runtime enable/disable handshake reported only to an attached debugger, `-ESRCH` (not `-EPERM`) once the target's KFD state is gone, and suspend/resume of already-destroyed queues answered so rocdbgapi can retire them during teardown. **Engine wave-stop and CWSR** (`vm/amdgpu/{compute_unit,wavefront,command_processor}`, `kmd/linux/cwsr.{h,cpp}`) - Waves stop on `s_trap` for the KFD debugger; stopped-wave state is serialized into the real CWSR area layout and written back on resume. - The runtime's own gfx9.4 trap handler is executed rather than shimmed. A wave frozen inside it needs the *interrupted* architectural state published, not the handler's, so EXEC and STATUS are shadowed in both directions: a debugger's edit lands on the state `s_rfe` restores instead of the register the handler is still running under. - Deterministic single-step via `TRAPSTS.trap_after_inst`; reserved debugger memory for displaced stepping; GPU address watchpoints; illegal instruction reported as SIGILL; memory violation reported as SIGSEGV; private/scratch reads so `print` and `info args` resolve. - Multi-wave: atomic queue resume, wave reclaim on queue destroy, scheduler-locked residency, 3D workgroup coordinates in CWSR records, and gfx950 LDS preservation. - Bounded functional-mode scheduling quantum while debugging so active CUs make fair progress without starving peer waves. **ISA and memory fixes surfaced by the suite** (`isa/arch/amdgpu/`, `vm/amdgpu/`) Running real debugger workloads exercised paths nothing else had: linked helper calls resolved against the `GETPC` base, ALU exception classification in generated execute paths, scalar memory access faults, signed scratch offsets, unaligned swizzled scratch, cross-XCD atomic coherence, the `v_bcnt` accumulator, pageable host copies through SDMA, and `s_sleep`'s architected delay. Generator changes live in `lib/python/amdisa/` with the generated output regenerated, not hand-edited. **Debugger UX, docs, demos.** `mirage run --gdb` / `--gdb-ex`; `docs/rocgdb-debugging.md`; four recorded walkthroughs under `demos/` (quickstart, watchpoint, fault, multi-wave), each with a `.md` explainer, a runnable `.sh`, and an asciinema `.cast`. **Test tooling.** `tools/run_rocgdb_official.py` runs each `gdb.rocm` file in a fresh, bounded, verified Mirage daemon session and records a per-test summary plus backend hashes; `tools/repeat_rocgdb_test.sh` repeats a subset serially under an `flock` (two concurrent Mirage sessions collide and manufacture failures) for chasing intermittents. Both archive the daemon's `host.log` alongside `gdb.log`. The emulated KFD's diagnostics land there and nowhere else, and three debugger defects fixed in this PR were invisible until it was collected. ## Issue Tracking Epic: https://github.com/ROCm/rocm-systems/issues/8276 Closes #8364, closes #8365, closes #8366, closes #8367, closes #8368, closes #8369, closes #8370, closes #8371, closes #8372, closes #8373, closes #8374, closes #8375, closes #8376, closes #8377, closes #8378, closes #8379, closes #8380, closes #8381. | Item | Work | |---|---| | #8364 | Authorize `DBG_TRAP` by real ptrace + daemon transport | | #8365 | Key debug sessions by inferior pid so rocgdb can attach | | #8366 | Complete the `DBG_TRAP` attach/detach lifecycle | | #8367 | Enumerate compute queues in `GET_QUEUE_SNAPSHOT` | | #8368 | Stop a GPU wave on `s_trap` for the KFD debugger | | #8369 | Serialize stopped-wave state into the CWSR area layout | | #8370 | Raise a debug event and serialize the CWSR when a wave traps | | #8371 | Drive GPU wave debugging end to end with ROCgdb | | #8372 | `mirage run --gdb` one-command debugging | | #8373 | Deterministic single-step via `TRAPSTS.trap_after_inst` | | #8374 | Reserve debugger memory for step-over | | #8375 | Validate `SET_WAVE_LAUNCH_OVERRIDE` against the gfx9.4 trap mask | | #8376 | GPU address watchpoints | | #8377 | Illegal instruction reported as SIGILL | | #8378 | Memory-access violation reported as SIGSEGV | | #8379 | Private/scratch reads for `print` / `info args` | | #8380 | Multi-wave GPU kernel debugging | | #8381 | ROCgdb debugging guide and demos index | Built on the already-merged foundations #8280, #8281, #8353 and #8363. ## Test Plan 1. **Official ROCgdb suite.** All 89 `gdb.rocm` test files, each in its own fresh, bounded Mirage daemon session, run serially via `tools/run_rocgdb_official.py --profile mi350x`. The suite is upstream ROCgdb's own, written for hardware and unmodified. 2. **rocjitsu unit/integration suite.** Full non-benchmark `ctest` run, including the 66 test cases added here (19 in the new `wave_debug_test.cpp`, 34 in `kfd_ioctl_test.cpp`, the rest across shared-infra, VM, interposer and decode tests). 3. **End-to-end smoke test in CI.** New `RocgdbDebug.KernelBreakpoint` ctest target drives real ROCgdb through `mirage run` to set a kernel breakpoint, stop, read wave registers, and continue to a correct result. Gated on `rocgdb` and `hipcc` being present; skips cleanly otherwise. ## Test Result Both suites green at `c998c5cd` (branch tip): | Suite | Result | |---|---| | Official ROCgdb `gdb.rocm` | **89/89 files pass, 0 FAIL**. 2376 PASS over 2407 executed assertions (9 UNSUPPORTED, 7 KFAIL, 3 XFAIL, 6 WARNING, 6 UNTESTED) | | rocjitsu `ctest` (non-benchmark) | **2492 tests, 0 failures** (4 skipped by design) | ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. --------- Co-authored-by: Claude Opus 5 (1M context) (cherry picked from commit e5109e315e1334ced00388d4731d02701b11831e) --- emulation/mirage/ctl/src/lib.rs | 86 +- emulation/mirage/rocjitsu_sys/src/lib.rs | 6 +- emulation/mirage/scripts/record_demo.sh | 116 + emulation/rocjitsu/README.md | 1 + emulation/rocjitsu/demos/rocgdb-fault.cast | 17 + emulation/rocjitsu/demos/rocgdb-fault.md | 31 + emulation/rocjitsu/demos/rocgdb-fault.sh | 36 + .../rocjitsu/demos/rocgdb-multiwave.cast | 24 + emulation/rocjitsu/demos/rocgdb-multiwave.md | 34 + emulation/rocjitsu/demos/rocgdb-multiwave.sh | 41 + .../rocjitsu/demos/rocgdb-quickstart.cast | 20 + emulation/rocjitsu/demos/rocgdb-quickstart.md | 27 + emulation/rocjitsu/demos/rocgdb-quickstart.sh | 39 + .../rocjitsu/demos/rocgdb-watchpoint.cast | 24 + emulation/rocjitsu/demos/rocgdb-watchpoint.md | 36 + emulation/rocjitsu/demos/rocgdb-watchpoint.sh | 46 + emulation/rocjitsu/docs/rocgdb-debugging.md | 127 + .../lib/python/amdisa/codegen/_generator.py | 197 +- .../python/amdisa/codegen/execute/__init__.py | 2 + .../amdisa/codegen/execute/simd_codegen.py | 15 +- .../amdisa/codegen/execute/vector_special.py | 20 + .../rocjitsu/lib/python/amdisa/semantics.py | 8 + .../python/amdisa/tests/test_sleep_body.py | 56 + .../amdisa/tests/test_trap_control_bodies.py | 112 + .../lib/rocjitsu/include/rocjitsu/vm/rj_vm.h | 14 +- .../src/rocjitsu/config/checkpoint.cpp | 81 +- .../isa/arch/amdgpu/cdna4/addr_calc.cpp | 9 +- .../isa/arch/amdgpu/cdna5/addr_calc.cpp | 20 +- .../arch/amdgpu/generated/cdna1/smem_exec.cpp | 59 +- .../arch/amdgpu/generated/cdna1/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/cdna2/smem_exec.cpp | 59 +- .../arch/amdgpu/generated/cdna2/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/cdna3/smem_exec.cpp | 59 +- .../arch/amdgpu/generated/cdna3/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/cdna4/smem_exec.cpp | 59 +- .../arch/amdgpu/generated/cdna4/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/cdna5/smem_exec.cpp | 20 + .../arch/amdgpu/generated/cdna5/sop1_exec.cpp | 51 +- .../arch/amdgpu/generated/cdna5/vop3_alu.cpp | 59 - .../amdgpu/generated/cdna5/vop3_exec_alu.cpp | 11 - .../amdgpu/generated/cdna5/vop3_exec_misc.cpp | 11 + .../arch/amdgpu/generated/cdna5/vop3_misc.cpp | 59 + .../arch/amdgpu/generated/rdna1/smem_exec.cpp | 13 + .../arch/amdgpu/generated/rdna1/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/rdna2/smem_exec.cpp | 10 + .../arch/amdgpu/generated/rdna2/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/rdna3/smem_exec.cpp | 10 + .../arch/amdgpu/generated/rdna3/sop1_exec.cpp | 20 +- .../amdgpu/generated/rdna3_5/smem_exec.cpp | 10 + .../amdgpu/generated/rdna3_5/sop1_exec.cpp | 20 +- .../arch/amdgpu/generated/rdna4/smem_exec.cpp | 20 + .../arch/amdgpu/generated/rdna4/sop1_exec.cpp | 20 +- .../amdgpu/generated/shared/execute_shared.h | 135 +- .../isa/arch/amdgpu/rdna1/addr_calc.cpp | 14 +- .../isa/arch/amdgpu/rdna2/addr_calc.cpp | 14 +- .../isa/arch/amdgpu/rdna3/addr_calc.cpp | 18 +- .../isa/arch/amdgpu/rdna3_5/addr_calc.cpp | 18 +- .../isa/arch/amdgpu/rdna4/addr_calc.cpp | 31 +- .../isa/arch/amdgpu/shared/addr_calc_buffer.h | 29 +- .../isa/arch/amdgpu/shared/addr_calc_flat.h | 53 +- .../isa/arch/amdgpu/shared/addr_calc_scalar.h | 9 +- .../isa/arch/amdgpu/shared/alu_exceptions.h | 161 + .../arch/amdgpu/shared/scalar_operand_read.h | 62 + .../amdgpu/shared/scalar_operand_resolve.h | 26 +- .../src/rocjitsu/kmd/linux/CMakeLists.txt | 1 + .../rocjitsu/src/rocjitsu/kmd/linux/cwsr.cpp | 490 +++ .../rocjitsu/src/rocjitsu/kmd/linux/cwsr.h | 258 ++ .../src/rocjitsu/kmd/linux/interposer.cpp | 87 +- .../src/rocjitsu/kmd/linux/kfd_process.h | 132 +- .../src/rocjitsu/kmd/linux/kfd_topology.h | 29 +- .../src/rocjitsu/kmd/linux/remote_driver.cpp | 334 +- .../src/rocjitsu/kmd/linux/remote_driver.h | 4 +- .../src/rocjitsu/kmd/linux/rj_daemon.cpp | 112 +- .../src/rocjitsu/kmd/linux/simulated_kfd.cpp | 2281 ++++++++++++- .../src/rocjitsu/kmd/linux/simulated_kfd.h | 191 +- .../rocjitsu/vm/amdgpu/command_processor.cpp | 387 ++- .../rocjitsu/vm/amdgpu/command_processor.h | 70 +- .../src/rocjitsu/vm/amdgpu/compute_unit.cpp | 300 +- .../src/rocjitsu/vm/amdgpu/compute_unit.h | 164 +- .../src/rocjitsu/vm/amdgpu/dispatch_entry.h | 5 + .../src/rocjitsu/vm/amdgpu/gpu_memory.h | 183 +- .../rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp | 39 +- .../vm/amdgpu/instruction_compute_unit_view.h | 4 + .../rocjitsu/vm/amdgpu/l1_vector_cache.cpp | 64 +- .../src/rocjitsu/vm/amdgpu/l1_vector_cache.h | 6 +- .../src/rocjitsu/vm/amdgpu/mem_state.h | 24 + .../rocjitsu/vm/amdgpu/memory_pipeline.cpp | 35 +- .../lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h | 27 +- .../src/rocjitsu/vm/amdgpu/wavefront.cpp | 4 +- .../src/rocjitsu/vm/amdgpu/wavefront.h | 329 +- .../lib/rocjitsu/src/rocjitsu/vm/rj_vm.cpp | 78 +- .../lib/rocjitsu/src/rocjitsu/vm/soc.h | 13 +- .../simdojo/components/sparse_memory.h | 9 + .../include/simdojo/components/vector_reg.h | 14 +- .../simdojo/include/simdojo/sim/simulation.h | 22 + .../rocjitsu/lib/simdojo/src/simulation.cpp | 71 +- emulation/rocjitsu/schemas/checkpoint.fbs | 18 + emulation/rocjitsu/tests/CMakeLists.txt | 181 + emulation/rocjitsu/tests/amdgpu_vm_test.cpp | 138 +- .../rocjitsu/tests/cdna5_cluster_test.cpp | 2 +- .../tests/cdna5_dispatch_memory_test.cpp | 12 +- emulation/rocjitsu/tests/config_test.cpp | 131 + emulation/rocjitsu/tests/daemon_test.cpp | 5 + .../rocjitsu/tests/decode_smoke_test.cpp | 30 + .../rocjitsu/tests/halt_snapshot_plugin.h | 30 +- .../instruction_execution_harness_test.cpp | 155 +- .../rocjitsu/tests/interposer_dup_test.cpp | 47 + emulation/rocjitsu/tests/kfd_ioctl_test.cpp | 2971 ++++++++++++++++- emulation/rocjitsu/tests/rocgdb/add_one.hip | 39 + .../rocjitsu/tests/rocgdb/bad_access.hip | 35 + .../rocjitsu/tests/rocgdb/debug_kernel.sh | 506 +++ .../rocjitsu/tests/rocgdb/multi_wave.hip | 34 + .../rocjitsu/tests/shared_infra_test.cpp | 221 +- emulation/rocjitsu/tests/simdojo_sim_test.cpp | 27 + .../rocjitsu/tests/sparse_memory_test.cpp | 28 + emulation/rocjitsu/tests/sysfs_test.cpp | 33 +- emulation/rocjitsu/tests/wave_debug_test.cpp | 1435 ++++++++ .../rocjitsu/tests/xcd_distribution_test.cpp | 10 +- .../rocjitsu/tools/repeat_rocgdb_test.sh | 76 + .../rocjitsu/tools/run_rocgdb_official.py | 471 +++ 120 files changed, 14001 insertions(+), 906 deletions(-) create mode 100755 emulation/mirage/scripts/record_demo.sh create mode 100644 emulation/rocjitsu/demos/rocgdb-fault.cast create mode 100644 emulation/rocjitsu/demos/rocgdb-fault.md create mode 100755 emulation/rocjitsu/demos/rocgdb-fault.sh create mode 100644 emulation/rocjitsu/demos/rocgdb-multiwave.cast create mode 100644 emulation/rocjitsu/demos/rocgdb-multiwave.md create mode 100755 emulation/rocjitsu/demos/rocgdb-multiwave.sh create mode 100644 emulation/rocjitsu/demos/rocgdb-quickstart.cast create mode 100644 emulation/rocjitsu/demos/rocgdb-quickstart.md create mode 100755 emulation/rocjitsu/demos/rocgdb-quickstart.sh create mode 100644 emulation/rocjitsu/demos/rocgdb-watchpoint.cast create mode 100644 emulation/rocjitsu/demos/rocgdb-watchpoint.md create mode 100755 emulation/rocjitsu/demos/rocgdb-watchpoint.sh create mode 100644 emulation/rocjitsu/docs/rocgdb-debugging.md create mode 100644 emulation/rocjitsu/lib/python/amdisa/tests/test_sleep_body.py create mode 100644 emulation/rocjitsu/lib/python/amdisa/tests/test_trap_control_bodies.py create mode 100644 emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h create mode 100644 emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h create mode 100644 emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.cpp create mode 100644 emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.h create mode 100644 emulation/rocjitsu/tests/rocgdb/add_one.hip create mode 100644 emulation/rocjitsu/tests/rocgdb/bad_access.hip create mode 100755 emulation/rocjitsu/tests/rocgdb/debug_kernel.sh create mode 100644 emulation/rocjitsu/tests/rocgdb/multi_wave.hip create mode 100644 emulation/rocjitsu/tests/wave_debug_test.cpp create mode 100755 emulation/rocjitsu/tools/repeat_rocgdb_test.sh create mode 100644 emulation/rocjitsu/tools/run_rocgdb_official.py diff --git a/emulation/mirage/ctl/src/lib.rs b/emulation/mirage/ctl/src/lib.rs index 32d97c37a607..10809354c4d2 100644 --- a/emulation/mirage/ctl/src/lib.rs +++ b/emulation/mirage/ctl/src/lib.rs @@ -603,6 +603,18 @@ pub struct RunArgs { /// daemon (the default). #[arg(long = "in-process")] in_process: bool, + /// Debug the workload interactively under ROCgdb: the command is + /// wrapped as `rocgdb --args `, with kernel breakpoints + /// made pending so `break ` works before the GPU code object + /// loads at launch. Requires a profile whose container ships ROCgdb. + #[arg(long)] + gdb: bool, + /// Extra ROCgdb command to run before the program, injected as + /// `-ex ` (repeatable, applied in order). Implies `--gdb`. + /// Useful for scripted/batch debugging, e.g. + /// `--gdb-ex 'break add_one' --gdb-ex run --gdb-ex continue`. + #[arg(long = "gdb-ex", value_name = "CMD")] + gdb_ex: Vec, /// The command and its arguments. #[arg(trailing_var_arg = true, required = true, allow_hyphen_values = true)] argv: Vec, @@ -1765,6 +1777,32 @@ fn split_argv(argv: &[String]) -> (String, Vec) { (cmd, it.collect()) } +/// Wrap a workload argv so it runs under ROCgdb for GPU kernel debugging +/// (`mirage run --gdb`). `["./add_one", "5"]` becomes +/// `rocgdb -ex "set breakpoint pending on" [-ex EX]... --args ./add_one 5`. +/// +/// Kernel breakpoints are made pending because GPU code objects load lazily at +/// dispatch: a `break ` set before launch would otherwise be rejected. +/// Extra `-ex` commands (`--gdb-ex`) are injected in order, before `--args`, so +/// a run can be fully scripted. When any `-ex` command is present the session is +/// non-interactive, so `--batch` is added: ROCgdb runs the commands and exits +/// (a bare `--gdb`, with no `-ex`, stays interactive and reads the terminal). +fn gdb_wrap_argv(argv: &[String], gdb_ex: &[String]) -> Vec { + let mut wrapped = vec!["rocgdb".to_string()]; + if !gdb_ex.is_empty() { + wrapped.push("--batch".to_string()); + } + wrapped.push("-ex".to_string()); + wrapped.push("set breakpoint pending on".to_string()); + for ex in gdb_ex { + wrapped.push("-ex".to_string()); + wrapped.push(ex.clone()); + } + wrapped.push("--args".to_string()); + wrapped.extend_from_slice(argv); + wrapped +} + /// Parse repeated `KEY=VALUE` pairs from the CLI into the env map /// used by [`ExecArgs`]. Rejects entries without an `=` so a typo /// surfaces immediately instead of silently being dropped. @@ -2013,7 +2051,14 @@ async fn run_cmd(ctl: Arc, a: RunArgs) -> anyhow::Res (def.id, true) } }; - let (cmd, args) = split_argv(&a.argv); + // `--gdb` / `--gdb-ex` wrap the workload under ROCgdb for interactive GPU + // kernel debugging. `--gdb-ex` implies `--gdb`. + let effective_argv = if a.gdb || !a.gdb_ex.is_empty() { + gdb_wrap_argv(&a.argv, &a.gdb_ex) + } else { + a.argv.clone() + }; + let (cmd, args) = split_argv(&effective_argv); let env = parse_envs(&a.envs)?; let def = ExecDef { timestamp: chrono::Utc::now(), @@ -2234,6 +2279,45 @@ mod tests { assert!(parse_option("=value").is_err()); } + #[test] + fn gdb_wrap_prepends_rocgdb_with_pending_breakpoints() { + let got = gdb_wrap_argv(&["./add_one".to_string(), "5".to_string()], &[]); + assert_eq!( + got, + vec![ + "rocgdb", + "-ex", + "set breakpoint pending on", + "--args", + "./add_one", + "5", + ] + ); + } + + #[test] + fn gdb_wrap_injects_extra_ex_commands_in_order() { + let got = gdb_wrap_argv( + &["./add_one".to_string()], + &["break add_one".to_string(), "run".to_string()], + ); + assert_eq!( + got, + vec![ + "rocgdb", + "--batch", + "-ex", + "set breakpoint pending on", + "-ex", + "break add_one", + "-ex", + "run", + "--args", + "./add_one", + ] + ); + } + #[test] fn no_overrides_keeps_by_name_ref() { let mut p = sample_profile(); diff --git a/emulation/mirage/rocjitsu_sys/src/lib.rs b/emulation/mirage/rocjitsu_sys/src/lib.rs index 97d6021035b3..c2878f267e47 100644 --- a/emulation/mirage/rocjitsu_sys/src/lib.rs +++ b/emulation/mirage/rocjitsu_sys/src/lib.rs @@ -115,6 +115,10 @@ pub struct RjVmCmd { /// In daemon mode the VM substitutes it into DBG_TRAP ENABLE and, on /// adoption, clears it to -1 so the caller does not close it. pub in_handle: RjHandle, + /// `[in/out]` Debugger-authorized target `/proc/pid/mem` fd, or -1. + pub in_mem_handle: RjHandle, + /// `[in]` Pinned target `/proc/pid` directory fd, or -1. + pub in_proc_handle: RjHandle, } /// Device memory mapping descriptor (`rj_vm_map_t`). @@ -610,7 +614,7 @@ mod tests { assert_eq!(std::mem::size_of::(), 16); // rj_vm_cmd_t: u32 + (pad) + ptr + usize + i32 + i32 + i32 + (pad) // on 64-bit. - assert_eq!(std::mem::size_of::(), 40); + assert_eq!(std::mem::size_of::(), 48); assert_eq!(RjVmMode::Daemon as i32, 2); // rj_vm_gpu_info_t — must match the 312-byte RpcGpuInfo the // daemon handshake embeds (static_assert in rpc.h). diff --git a/emulation/mirage/scripts/record_demo.sh b/emulation/mirage/scripts/record_demo.sh new file mode 100755 index 000000000000..aefdc5326de9 --- /dev/null +++ b/emulation/mirage/scripts/record_demo.sh @@ -0,0 +1,116 @@ +#!/usr/bin/env bash +# +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# Record an asciinema demo of a mirage/rocjitsu workflow. +# +# WHY: the emulation demos under `emulation/rocjitsu/demos/` each ship three +# files — `.md` (what it shows), `.sh` (the exact commands), and +# `.cast` (the recording). This helper is the single, reproducible way to +# (re)generate the `.cast`: it builds a portable mirage + rocjitsu with +# `mirage-docker-build.sh`, puts that `mirage` on `PATH`, and records the demo +# script with asciinema, overwriting the `.cast` next to the `.sh` by default. +# +# Usage: +# scripts/record_demo.sh [options] [output.cast] +# +# Examples: +# # Build mirage+rocjitsu, record emulation/rocjitsu/demos/rocgdb-quickstart.cast +# scripts/record_demo.sh ../rocjitsu/demos/rocgdb-quickstart.sh +# +# # Reuse an already-built prefix (skip the ~minutes-long docker build) +# scripts/record_demo.sh --no-build --prefix ./build/manylinux \ +# ../rocjitsu/demos/rocgdb-quickstart.sh +# +# Options: +# --no-build Skip the docker build; reuse --prefix / $MIRAGE_BIN. +# --prefix DIR Build into / read the mirage prefix here +# (default: mirage/build/manylinux; also $MIRAGE_PREFIX). +# --title STR asciinema recording title (default: the demo name). +# -h, --help Show this help. +# +# Environment: +# MIRAGE_BIN Explicit `mirage` binary to use (implies --no-build). +# MIRAGE_PREFIX Same as --prefix. +# CARGO_PROFILE Passed to mirage-docker-build.sh (default: release). +# ASCIINEMA_COLS/ROWS Terminal size for the recording (default 100x30). + +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +MIRAGE_DIR="$(cd "$SCRIPT_DIR/.." && pwd)" + +no_build=0 +prefix="${MIRAGE_PREFIX:-$MIRAGE_DIR/build/manylinux}" +title="" +demo="" +out="" + +usage() { sed -n '2,40p' "${BASH_SOURCE[0]}" | sed 's/^# \{0,1\}//'; } + +while [[ $# -gt 0 ]]; do + case "$1" in + --no-build) no_build=1; shift ;; + --prefix) prefix="$2"; shift 2 ;; + --title) title="$2"; shift 2 ;; + -h|--help) usage; exit 0 ;; + --) shift; break ;; + -*) echo "record_demo: unknown option: $1" >&2; usage >&2; exit 2 ;; + *) if [[ -z "$demo" ]]; then demo="$1"; elif [[ -z "$out" ]]; then out="$1"; else + echo "record_demo: unexpected argument: $1" >&2; exit 2; fi; shift ;; + esac +done + +[[ -n "$demo" ]] || { echo "record_demo: missing " >&2; usage >&2; exit 2; } +[[ -f "$demo" ]] || { echo "record_demo: no such demo script: $demo" >&2; exit 1; } +demo="$(cd "$(dirname "$demo")" && pwd)/$(basename "$demo")" +# Default output: .cast next to the .sh, overwritten. +[[ -n "$out" ]] || out="${demo%.sh}.cast" +[[ -n "$title" ]] || title="$(basename "${demo%.sh}")" + +# --- Require asciinema ------------------------------------------------------ +# Recording a demo is a developer convenience, which is not a good enough reason +# to mutate the machine it runs on. Provision the tool in the build or container +# environment instead; this script only reports what is missing. +command -v asciinema >/dev/null 2>&1 || { + echo "record_demo: asciinema not found. Install it and re-run, e.g." >&2 + echo " apt-get install asciinema | dnf install asciinema" >&2 + echo " pipx install asciinema | pip install --user asciinema" >&2 + exit 1 +} + +# --- Build mirage + rocjitsu (portable) ------------------------------------- +mirage_bin="${MIRAGE_BIN:-}" +if [[ -z "$mirage_bin" && "$no_build" -eq 0 ]]; then + echo "record_demo: building mirage + rocjitsu into $prefix" >&2 + "$SCRIPT_DIR/mirage-docker-build.sh" "$prefix" >&2 +fi +if [[ -z "$mirage_bin" ]]; then + mirage_bin="$prefix/bin/mirage" +fi +[[ -x "$mirage_bin" ]] || { + echo "record_demo: mirage binary not found at $mirage_bin" >&2 + echo " build it first (drop --no-build) or set \$MIRAGE_BIN." >&2 + exit 1 +} +mirage_bin="$(cd "$(dirname "$mirage_bin")" && pwd)/$(basename "$mirage_bin")" +echo "record_demo: using mirage: $mirage_bin" >&2 + +# --- Record ----------------------------------------------------------------- +# The demo script finds `mirage` on PATH (built above) and may read $MIRAGE_BIN. +# asciinema replays the exact stdout of `bash `; --overwrite keeps the +# `.cast` regenerable in place. +echo "record_demo: recording $demo -> $out" >&2 +env \ + PATH="$(dirname "$mirage_bin"):$PATH" \ + MIRAGE_BIN="$mirage_bin" \ + asciinema rec \ + --overwrite \ + --title "$title" \ + --cols "${ASCIINEMA_COLS:-100}" \ + --rows "${ASCIINEMA_ROWS:-30}" \ + --command "bash '$demo'" \ + "$out" + +echo "record_demo: wrote $out" >&2 diff --git a/emulation/rocjitsu/README.md b/emulation/rocjitsu/README.md index ff7e3fea4909..af723c89418e 100644 --- a/emulation/rocjitsu/README.md +++ b/emulation/rocjitsu/README.md @@ -122,6 +122,7 @@ See [docs/building.md](docs/building.md) for container setup with PyTorch. | [Configuration](docs/configuration.md) | JSON config format and topology | | [CLI & Transport](docs/rocjitsu-cli.md) | CLI modes, daemon RPC protocol | | [Race Detector](docs/race-detector.md) | Race detection tutorial and internals | +| [Debugging with ROCgdb](docs/rocgdb-debugging.md) | Debug emulated GPU kernels with ROCgdb: breakpoints, watchpoints, faults, multi-wave | ### Design diff --git a/emulation/rocjitsu/demos/rocgdb-fault.cast b/emulation/rocjitsu/demos/rocgdb-fault.cast new file mode 100644 index 000000000000..526d01ec0978 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-fault.cast @@ -0,0 +1,17 @@ +{"version": 2, "width": 100, "height": 30, "timestamp": 1783636162, "env": {"SHELL": "/bin/bash", "TERM": "xterm-256color"}, "title": "rocgdb-fault"} +[0.009987, "o", "\r\n\u001b[1;36m# A HIP kernel that stores through a wild, never-mapped device pointer:\u001b[0m\r\n"] +[0.011269, "o", "__global__ void bad_access(int *data, int n) {\r\n int i = blockIdx.x * blockDim.x + threadIdx.x;\r\n // A wild, never-mapped device address. The store below faults.\r\n int *wild = reinterpret_cast(0x0000dead0000ULL);\r\n if (i < n)\r\n wild[i] = data[i] + 1;\r\n}\r\n"] +[0.011443, "o", "\r\n\u001b[1;36m# Build it for gfx950 (MI350X) with device debug info:\u001b[0m\r\n"] +[0.014641, "o", "+ hipcc --offload-arch=gfx950 -g -O0 -o /tmp/tmp.wtWfqkbt4t/bad_access /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/bad_access.hip\r\n"] +[0.531921, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/bad_access.hip:29:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 29 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[0.635648, "o", "1 warning generated when compiling for gfx950.\r\n"] +[1.136021, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/bad_access.hip:29:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 29 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[1.189941, "o", "1 warning generated when compiling for host.\r\n"] +[1.221753, "o", "\r\n\u001b[1;36m# Run it under ROCgdb — the emulator faults the wave on the wild store:\u001b[0m\r\n"] +[1.222347, "o", "+ /home/arosa/rocm-systems/emulation/mirage/target/debug/mirage run --profile mi350x --gdb --gdb-ex run --gdb-ex backtrace --gdb-ex 'info registers pc' -- /tmp/tmp.wtWfqkbt4t/bad_access\r\n"] +[2.484295, "o", "[Thread debugging using libthread_db enabled]\r\nUsing host libthread_db library \"/lib/x86_64-linux-gnu/libthread_db.so.1\".\r\n"] +[2.633349, "o", "[New Thread 0x7ffff27ff6c0 (LWP 1839316)]\r\n[New Thread 0x7fffebfff6c0 (LWP 1839317)]\r\n[New Thread 0x7ffff1ffe6c0 (LWP 1839319)]\r\n[Thread 0x7ffff1ffe6c0 (LWP 1839319) exited]\r\n"] +[2.883424, "o", "[New Thread 0x7ffff17fd6c0 (LWP 1839399)]\r\n[Thread 0x7ffff17fd6c0 (LWP 1839399) exited]\r\n[New Thread 0x7ffff2d7e6c0 (LWP 1839400)]\r\n"] +[2.983503, "o", "\r\nThread 7 received signal SIGSEGV, Segmentation fault.\r\nWarning: precise memory violation signal reporting is not enabled, reported\r\nlocation may not be accurate. See \"show amdgpu precise-memory\".\r\n[Switching to thread 7, lane 0 (AMDGPU Lane 1:2:?:1/0 (?,?,?)[?,?,?])]\r\n"] +[3.034011, "o", "0x000000540002d11c in bad_access (data=, n=) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/bad_access.hip:17\r\n17\t wild[i] = data[i] + 1;\r\n#0 0x000000540002d11c in bad_access (data=, n=) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/bad_access.hip:17\r\npc 0x540002d11c 0x540002d11c \r\n"] +[4.097695, "o", "\r\n\u001b[1;36m# ROCgdb caught the GPU memory violation as SIGSEGV, stopped at the faulting store — no AMD GPU required.\u001b[0m\r\n"] diff --git a/emulation/rocjitsu/demos/rocgdb-fault.md b/emulation/rocjitsu/demos/rocgdb-fault.md new file mode 100644 index 000000000000..31aa8c1ef6a7 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-fault.md @@ -0,0 +1,31 @@ +# rocgdb-fault + +Catch a GPU **memory-access fault (SIGSEGV)** with ROCgdb — in software, with no +AMD GPU required. + +A wave that dereferences an unmapped device address is the GPU equivalent of a +segfault. On real hardware it raises a memory-access fault that stops the wave; +on the emulated MI350X the memory pipeline detects the unmapped access, raises +`TRAPSTS.xnack_error`, and reports it to rocm-dbgapi as +`WAVE_STOP_REASON_MEMORY_VIOLATION`, which ROCgdb surfaces as **SIGSEGV** at the +faulting instruction. + +This demo builds a tiny HIP kernel that stores through a wild pointer +(`0x0000dead0000`) and runs it under `mirage run --gdb`: ROCgdb stops the GPU +wave with a segmentation fault at the offending store, so you can see the PC and +backtrace of the wave that went out of bounds. + +## Run it + +Record (builds a portable mirage + rocjitsu, then captures the `.cast`): + + emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-fault.sh + +Or run against an already-built `mirage`: + + MIRAGE_BIN=/path/to/mirage bash emulation/rocjitsu/demos/rocgdb-fault.sh + +Requires `hipcc` and `rocgdb` on `PATH` (from a ROCm install). + +See [rocgdb-debugging.md](../docs/rocgdb-debugging.md) for how the emulator maps +GPU exceptions to debugger stop reasons. diff --git a/emulation/rocjitsu/demos/rocgdb-fault.sh b/emulation/rocjitsu/demos/rocgdb-fault.sh new file mode 100755 index 000000000000..bfa7fc96d765 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-fault.sh @@ -0,0 +1,36 @@ +#!/usr/bin/env bash +# +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# Demo: catch a GPU memory-access fault (SIGSEGV) with ROCgdb, entirely in +# software with no AMD GPU. See rocgdb-fault.md. Regenerate the .cast with: +# emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-fault.sh + +set -euo pipefail + +here="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +kernel="$here/../tests/rocgdb/bad_access.hip" +mirage="${MIRAGE_BIN:-mirage}" + +say() { printf '\n\033[1;36m# %s\033[0m\n' "$*"; } + +say "A HIP kernel that stores through a wild, never-mapped device pointer:" +sed -n '/__global__/,/^}/p' "$kernel" + +say "Build it for gfx950 (MI350X) with device debug info:" +tmp="$(mktemp -d)" +trap 'rm -rf "$tmp"' EXIT +app="$tmp/bad_access" +( set -x; hipcc --offload-arch=gfx950 -g -O0 -o "$app" "$kernel" ) + +say "Run it under ROCgdb — the emulator faults the wave on the wild store:" +( set -x + "$mirage" run --profile mi350x --gdb \ + --gdb-ex 'run' \ + --gdb-ex 'backtrace' \ + --gdb-ex 'info registers pc' \ + -- "$app" +) + +say "ROCgdb caught the GPU memory violation as SIGSEGV, stopped at the faulting store — no AMD GPU required." diff --git a/emulation/rocjitsu/demos/rocgdb-multiwave.cast b/emulation/rocjitsu/demos/rocgdb-multiwave.cast new file mode 100644 index 000000000000..406d86cd5d5e --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-multiwave.cast @@ -0,0 +1,24 @@ +{"version": 2, "width": 100, "height": 30, "timestamp": 1783636824, "env": {"SHELL": "/bin/bash", "TERM": "xterm-256color"}, "title": "rocgdb-multiwave"} +[0.010458, "o", "\r\n\u001b[1;36m# A HIP kernel launched as one workgroup of 128 threads = two 64-lane waves:\u001b[0m\r\n"] +[0.013315, "o", "__global__ void multi_wave(int *data, int n) {\r\n int i = blockIdx.x * blockDim.x + threadIdx.x;\r\n int local = i * 7 + 3;\r\n if (i < n)\r\n data[i] = local;\r\n}\r\n"] +[0.013508, "o", "\r\n\u001b[1;36m# Build it for gfx950 (MI350X) with device debug info:\u001b[0m\r\n"] +[0.015736, "o", "+ hipcc --offload-arch=gfx950 -g -O0 -o /tmp/tmp.RHDDLnRxDh/multi_wave /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip\r\n"] +[0.533249, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:28:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 28 | hipDeviceSynchronize();\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~~~~~~~~~~~~~\r\n\u001b[0m\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:30:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 30 | hipMemcp"] +[0.533364, "o", "y(h, d, n * \u001b[0;34msizeof\u001b[0m(\u001b[0;34mint\u001b[0m), hipMemcpyDeviceToHost);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r\n\u001b[0m"] +[0.533673, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:32:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 32 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[0.641285, "o", "3 warnings generated when compiling for gfx950.\r\n"] +[1.147942, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:28:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 28 | hipDeviceSynchronize();\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~~~~~~~~~~~~~\r\n\u001b[0m"] +[1.147993, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:30:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 30 | hipMemcpy(h, d, n * \u001b[0;34msizeof\u001b[0m(\u001b[0;34mint\u001b[0m"] +[1.148212, "o", "), hipMemcpyD"] +[1.148329, "o", "eviceToHost);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r\n\u001b[0m\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:32:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 32 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[1.202216, "o", "3 warnings generated when compiling for host.\r\n"] +[1.23639, "o", "\r\n\u001b[1;36m# Break inside the kernel: both waves of the workgroup stop together:\u001b[0m\r\n"] +[1.236942, "o", "+ /home/arosa/rocm-systems/emulation/mirage/target/debug/mirage run --profile mi350x --gdb --gdb-ex 'break multi_wave.hip:19' --gdb-ex run --gdb-ex 'info threads' --gdb-ex 'thread apply all -q print local' --gdb-ex continue -- /tmp/tmp.RHDDLnRxDh/multi_wave\r\n"] +[2.299, "o", "No compiled code for line 19 in file \"multi_wave.hip\".\r\nBreakpoint 1 (multi_wave.hip:19) pending.\r\n"] +[2.548754, "o", "[Thread debugging using libthread_db enabled]\r\nUsing host libthread_db library \"/lib/x86_64-linux-gnu/libthread_db.so.1\".\r\n"] +[2.648631, "o", "[New Thread 0x7ffff27ff6c0 (LWP 1860196)]\r\n[New Thread 0x7ffff1ffe6c0 (LWP 1860197)]\r\n[New Thread 0x7ffff17fd6c0 (LWP 1860198)]\r\n[Thread 0x7ffff17fd6c0 (LWP 1860198) exited]\r\n"] +[2.898856, "o", "[New Thread 0x7ffff0ffc6c0 (LWP 1860201)]\r\n"] +[2.948406, "o", "[Thread 0x7ffff0ffc6c0 (LWP 1860201) exited]\r\n[New Thread 0x7ffff2d7e6c0 (LWP 1860202)]\r\n"] +[2.999011, "o", "[Switching to thread 7, lane 0 (AMDGPU Lane 1:2:1:1/0 (0,0,0)[0,0,0])]\r\n"] +[3.048576, "o", "\r\nThread 7 \"multi_wave\" hit Breakpoint 1, with lanes [0-63], multi_wave (data=0x5400c00000, n=128) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:19\r\n19\t data[i] = local;\r\n Id Target Id Frame \r\n 1 Thread 0x7ffff30b5080 (LWP 1860190) \"multi_wave\" 0x00007ffff28669a3 in ?? () from /opt/rocm-7.2.4/lib/libhsa-runtime64.so.1\r\n 2 Thread 0x7ffff27ff6c0 (LWP 1860196) \"multi_wave\" 0x00007ffff2f2728d in syscall () from /lib/x86_64-linux-gnu/libc.so.6\r\n 3 Thread 0x7ffff1ffe6c0 (LWP 1860197) \"multi_wave\" 0x00007ffff2f2728d in syscall () from /lib/x86_64-linux-gnu/libc.so.6\r\n 6 Thread 0x7ffff2d7e6c0 (LWP 1860202) \"multi_wave\" 0x00007ffff287768e in ?? () from /opt/rocm-7.2.4/lib/libhsa-runtime64.so.1\r\n* 7 AMDGPU Wave 1:2:1:1 (0,0,0)/0 \"multi_wave\" multi_wave (data=0x5400c00000, n=128) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:19\r\n 8 AMDGPU Wave 1:2:1:2 (0,0,0)/1 \"multi_wave\" multi_wave (data=0x5400c00000, n=128) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:19\r\n$1 = 451\r\n$2 = 3\r\nNo symbol \"local\" in current context.\r\n[Switching to thread 8, lane 0 (AMDGPU Lane 1:2:1:2/0 (0,0,0)[64,0,0])]\r\n\r\nThread 8 \"multi_wave\" hit Breakpoint 1, with lanes [0-63], multi_wave (data=0x5400c00000, n=128) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/multi_wave.hip:19\r\n19\t data[i] = local;\r\n"] +[4.113342, "o", "\r\n\u001b[1;36m# Both waves correlated to workgroup (0,0,0) at positions /0 and /1, each reading its own private 'local' (3 and 451) — a real multi-wave kernel, no AMD GPU required.\u001b[0m\r\n"] diff --git a/emulation/rocjitsu/demos/rocgdb-multiwave.md b/emulation/rocjitsu/demos/rocgdb-multiwave.md new file mode 100644 index 000000000000..c0a895174377 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-multiwave.md @@ -0,0 +1,34 @@ +# rocgdb-multiwave + +Debug a real **multi-wave** GPU kernel with ROCgdb — in software, with no AMD +GPU required. + +Real GPU kernels are almost always multi-wave: a workgroup spans many 64-lane +wavefronts, and there are usually many workgroups. This demo launches one +workgroup of 128 threads — exactly two 64-lane waves — and sets a breakpoint +inside the kernel so **both waves trap together**. + +ROCgdb (through rocm-dbgapi) correlates each trapped wave to its dispatch and +workgroup: `info threads` shows both waves of workgroup `(0,0,0)` at positions +`/0` and `/1`, and reading the scratch-resident `local` in each wave returns +that wave's own value (`3` for global thread 0, `451` for global thread 64) — +proving per-wave private memory and workgroup correlation, not one wave's state +smeared across both. + +This is the capability that makes the emulated debugger practical for real +kernels rather than single-wave toys. + +## Run it + +Record (builds a portable mirage + rocjitsu, then captures the `.cast`): + + emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-multiwave.sh + +Or run against an already-built `mirage`: + + MIRAGE_BIN=/path/to/mirage bash emulation/rocjitsu/demos/rocgdb-multiwave.sh + +Requires `hipcc` and `rocgdb` on `PATH` (from a ROCm install). + +See [rocgdb-debugging.md](../docs/rocgdb-debugging.md) for how the emulator +serializes a stable multi-wave control stack and maps per-wave scratch. diff --git a/emulation/rocjitsu/demos/rocgdb-multiwave.sh b/emulation/rocjitsu/demos/rocgdb-multiwave.sh new file mode 100755 index 000000000000..1c1c57ee3e2a --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-multiwave.sh @@ -0,0 +1,41 @@ +#!/usr/bin/env bash +# +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# Demo: debug a real multi-wave GPU kernel with ROCgdb, entirely in software +# with no AMD GPU. See rocgdb-multiwave.md. Regenerate the .cast with: +# emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-multiwave.sh + +set -euo pipefail + +here="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +kernel="$here/../tests/rocgdb/multi_wave.hip" +mirage="${MIRAGE_BIN:-mirage}" + +say() { printf '\n\033[1;36m# %s\033[0m\n' "$*"; } + +say "A HIP kernel launched as one workgroup of 128 threads = two 64-lane waves:" +sed -n '/__global__/,/^}/p' "$kernel" + +say "Build it for gfx950 (MI350X) with device debug info:" +tmp="$(mktemp -d)" +trap 'rm -rf "$tmp"' EXIT +app="$tmp/multi_wave" +( set -x; hipcc --offload-arch=gfx950 -g -O0 -o "$app" "$kernel" ) + +# Break on the store line so both waves have computed their per-thread `local`. +line="$(grep -nE 'data\[i\] = local' "$kernel" | head -1 | cut -d: -f1)" + +say "Break inside the kernel: both waves of the workgroup stop together:" +( set -x + "$mirage" run --profile mi350x --gdb \ + --gdb-ex "break multi_wave.hip:${line}" \ + --gdb-ex 'run' \ + --gdb-ex 'info threads' \ + --gdb-ex 'thread apply all -q print local' \ + --gdb-ex 'continue' \ + -- "$app" +) + +say "Both waves correlated to workgroup (0,0,0) at positions /0 and /1, each reading its own private 'local' (3 and 451) — a real multi-wave kernel, no AMD GPU required." diff --git a/emulation/rocjitsu/demos/rocgdb-quickstart.cast b/emulation/rocjitsu/demos/rocgdb-quickstart.cast new file mode 100644 index 000000000000..15da605058cc --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-quickstart.cast @@ -0,0 +1,20 @@ +{"version": 2, "width": 100, "height": 30, "timestamp": 1783636466, "env": {"SHELL": "/bin/bash", "TERM": "xterm-256color"}, "title": "rocgdb-quickstart"} +[0.009363, "o", "\r\n\u001b[1;36m# A tiny HIP kernel that adds 1 to every element:\u001b[0m\r\n"] +[0.010584, "o", "__global__ void add_one(int *data, int n) {\r\n int i = blockIdx.x * blockDim.x + threadIdx.x;\r\n if (i < n)\r\n data[i] += 1;\r\n}\r\n"] +[0.010783, "o", "\r\n\u001b[1;36m# Build it for gfx950 (MI350X) with device debug info:\u001b[0m\r\n"] +[0.013605, "o", "+ hipcc --offload-arch=gfx950 -g -O0 -o /tmp/tmp.s5wicjgC1O/add_one /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip\r\n"] +[0.529119, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:33:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 33 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[0.633696, "o", "1 warning generated when compiling for gfx950.\r\n"] +[1.132734, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:33:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 33 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[1.186899, "o", "1 warning generated when compiling for host.\r\n"] +[1.218745, "o", "\r\n\u001b[1;36m# Debug the GPU kernel with one command — no GPU required:\u001b[0m\r\n"] +[1.219503, "o", "+ /home/arosa/rocm-systems/emulation/mirage/target/debug/mirage run --profile mi350x --gdb --gdb-ex 'break add_one' --gdb-ex run --gdb-ex 'info args' --gdb-ex 'print n' --gdb-ex 'print data[0]' --gdb-ex continue -- /tmp/tmp.s5wicjgC1O/add_one\r\n"] +[2.282027, "o", "Function \"add_one\" not defined.\r\nBreakpoint 1 (add_one) pending.\r\n"] +[2.482227, "o", "[Thread debugging using libthread_db enabled]\r\nUsing host libthread_db library \"/lib/x86_64-linux-gnu/libthread_db.so.1\".\r\n"] +[2.631847, "o", "[New Thread 0x7ffff27ff6c0 (LWP 1849099)]\r\n[New Thread 0x7ffff1ffe6c0 (LWP 1849100)]\r\n[New Thread 0x7ffff17fd6c0 (LWP 1849101)]\r\n[Thread 0x7ffff17fd6c0 (LWP 1849101) exited]\r\n"] +[2.881755, "o", "[New Thread 0x7ffff0ffc6c0 (LWP 1849104)]\r\n[Thread 0x7ffff0ffc6c0 (LWP 1849104) exited]\r\n[New Thread 0x7ffff2d7e6c0 (LWP 1849105)]\r\n"] +[2.932321, "o", "[Switching to thread 7, lane 0 (AMDGPU Lane 1:2:?:1/0 (?,?,?)[?,?,?])]\r\n"] +[2.981919, "o", "\r\nThread 7 hit Breakpoint 1, with lanes [0-63], add_one (data=0x5400c00000, n=64) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:13\r\n13\t int i = blockIdx.x * blockDim.x + threadIdx.x;\r\ndata = 0x5400c00000\r\nn = 64\r\n$1 = 64\r\n$2 = 0\r\n"] +[3.031534, "o", "add_one done: host[0]=1 host[63]=1\r\nwarning: Temporarily disabling breakpoints for unloaded shared library \"file:///tmp/tmp.s5wicjgC1O/add_one#offset=8192&size=66944\"\r\n[Thread 0x7ffff2d7e6c0 (LWP 1849105) exited]\r\n[Thread 0x7ffff27ff6c0 (LWP 1849099) exited]\r\n[Thread 0x7ffff1ffe6c0 (LWP 1849100) exited]\r\n"] +[3.082133, "o", "[Inferior 1 (process 1849093) exited normally]\r\n"] +[4.096039, "o", "\r\n\u001b[1;36m# ROCgdb stopped a real emulated wave, read its source-level arguments, and resumed it.\u001b[0m\r\n"] diff --git a/emulation/rocjitsu/demos/rocgdb-quickstart.md b/emulation/rocjitsu/demos/rocgdb-quickstart.md new file mode 100644 index 000000000000..e9fda36c9ffe --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-quickstart.md @@ -0,0 +1,27 @@ +# rocgdb-quickstart + +Debug a real GPU kernel with a single command — entirely in software, with no +AMD GPU required. + +`mirage run --gdb` boots the emulated MI350X, launches the workload under +ROCgdb, and makes kernel breakpoints pending so `break ` resolves when +the GPU code object loads at dispatch. This demo builds a tiny HIP kernel and +drives ROCgdb through it: setting a breakpoint on the GPU kernel, running to the +stopped wave, reading its source-level arguments and locals (`info args`, +`print n`, `print data[0]`), and continuing to completion. + +It is the fastest way to see the emulated GPU debugger working end to end, and +the same flow (`mirage run --gdb -- ./your_app`) drops you into an interactive +ROCgdb session on your own kernels. + +## Run it + +Record (builds a portable mirage + rocjitsu, then captures the `.cast`): + + emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-quickstart.sh + +Or run against an already-built `mirage`: + + MIRAGE_BIN=/path/to/mirage bash emulation/rocjitsu/demos/rocgdb-quickstart.sh + +Requires `hipcc` and `rocgdb` on `PATH` (from a ROCm install). diff --git a/emulation/rocjitsu/demos/rocgdb-quickstart.sh b/emulation/rocjitsu/demos/rocgdb-quickstart.sh new file mode 100755 index 000000000000..31bf6ff6e2dd --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-quickstart.sh @@ -0,0 +1,39 @@ +#!/usr/bin/env bash +# +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# Demo: debug a real GPU kernel with one command — `mirage run --gdb`. +# See rocgdb-quickstart.md. Regenerate the .cast with: +# emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-quickstart.sh + +set -euo pipefail + +here="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +kernel="$here/../tests/rocgdb/add_one.hip" +mirage="${MIRAGE_BIN:-mirage}" + +say() { printf '\n\033[1;36m# %s\033[0m\n' "$*"; } + +say "A tiny HIP kernel that adds 1 to every element:" +sed -n '/__global__/,/^}/p' "$kernel" + +say "Build it for gfx950 (MI350X) with device debug info:" +tmp="$(mktemp -d)" +trap 'rm -rf "$tmp"' EXIT +app="$tmp/add_one" +( set -x; hipcc --offload-arch=gfx950 -g -O0 -o "$app" "$kernel" ) + +say "Debug the GPU kernel with one command — no GPU required:" +( set -x + "$mirage" run --profile mi350x --gdb \ + --gdb-ex 'break add_one' \ + --gdb-ex 'run' \ + --gdb-ex 'info args' \ + --gdb-ex 'print n' \ + --gdb-ex 'print data[0]' \ + --gdb-ex 'continue' \ + -- "$app" +) + +say "ROCgdb stopped a real emulated wave, read its source-level arguments, and resumed it." diff --git a/emulation/rocjitsu/demos/rocgdb-watchpoint.cast b/emulation/rocjitsu/demos/rocgdb-watchpoint.cast new file mode 100644 index 000000000000..1ecf40787b90 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-watchpoint.cast @@ -0,0 +1,24 @@ +{"version": 2, "width": 100, "height": 30, "timestamp": 1783635550, "env": {"SHELL": "/bin/bash", "TERM": "xterm-256color"}, "title": "rocgdb-watchpoint"} +[0.008605, "o", "\r\n\u001b[1;36m# A tiny HIP kernel that adds 1 to every element of a device buffer:\u001b[0m\r\n"] +[0.009877, "o", "__global__ void add_one(int *data, int n) {\r\n int i = blockIdx.x * blockDim.x + threadIdx.x;\r\n if (i < n)\r\n data[i] += 1;\r\n}\r\n"] +[0.010079, "o", "\r\n\u001b[1;36m# Build it for gfx950 (MI350X) with device debug info:\u001b[0m\r\n"] +[0.011887, "o", "+ hipcc --offload-arch=gfx950 -g -O0 -o /tmp/tmp.aZNGXRzm1I/add_one /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip\r\n"] +[0.528479, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:33:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 33 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[0.633036, "o", "1 warning generated when compiling for gfx950.\r\n"] +[1.136597, "o", "\u001b[1m/home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:33:3: \u001b[0m\u001b[0;1;35mwarning: \u001b[0m\u001b[1mignoring return value of type 'hipError_t' declared with 'nodiscard' attribute [-Wunused-value]\u001b[0m\r\n 33 | hipFree(d);\u001b[0m\r\n | \u001b[0;1;32m ^~~~~~~~~~\r\n\u001b[0m"] +[1.190908, "o", "1 warning generated when compiling for host.\r\n"] +[1.225168, "o", "\r\n\u001b[1;36m# Set a hardware watchpoint on the device buffer and catch the GPU store:\u001b[0m\r\n"] +[1.225987, "o", "+ /home/arosa/rocm-systems/emulation/mirage/target/debug/mirage run --profile mi350x --gdb --gdb-ex 'break add_one.hip:27' --gdb-ex 'break add_one' --gdb-ex run --gdb-ex 'set $waddr = (unsigned long)d' --gdb-ex continue --gdb-ex 'watch *(int*)$waddr' --gdb-ex continue --gdb-ex continue -- /tmp/tmp.aZNGXRzm1I/add_one\r\n"] +[2.338152, "o", "Breakpoint 1 at 0x21394a: file /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip, line 27.\r\nFunction \"add_one\" not defined.\r\nBreakpoint 2 (add_one) pending.\r\n"] +[2.537729, "o", "[Thread debugging using libthread_db enabled]\r\nUsing host libthread_db library \"/lib/x86_64-linux-gnu/libthread_db.so.1\".\r\n"] +[2.637869, "o", "[New Thread 0x7ffff27ff6c0 (LWP 1824780)]\r\n[New Thread 0x7ffff1ffe6c0 (LWP 1824781)]\r\n"] +[2.688382, "o", "[New Thread 0x7ffff17fd6c0 (LWP 1824782)]\r\n[Thread 0x7ffff17fd6c0 (LWP 1824782) exited]\r\n"] +[2.887668, "o", "\r\nThread 1 \"add_one\" hit Breakpoint 1, main () at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:27\r\n27\t add_one<<>>(d, n);\r\n"] +[2.938255, "o", "[New Thread 0x7ffff0ffc6c0 (LWP 1824785)]\r\n[Thread 0x7ffff0ffc6c0 (LWP 1824785) exited]\r\n[New Thread 0x7ffff2d7e6c0 (LWP 1824786)]\r\n"] +[2.987928, "o", "[Switching to thread 7, lane 0 (AMDGPU Lane 1:2:?:1/0 (?,?,?)[?,?,?])]\r\n"] +[3.037585, "o", "\r\nThread 7 hit Breakpoint 2, with lanes [0-63], add_one (data=, n=) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:13\r\n13\t int i = blockIdx.x * blockDim.x + threadIdx.x;\r\nHardware watchpoint 3: *(int*)$waddr\r\n"] +[3.838409, "o", "\r\nThread 7 hit Hardware watchpoint 3: *(int*)$waddr\r\n\r\nOld value = 0\r\nNew value = 1\r\n0x000000540002d088 in add_one (data=, n=) at /home/arosa/rocm-systems/emulation/rocjitsu/demos/../tests/rocgdb/add_one.hip:15\r\n15\t data[i] += 1;\r\nWarning: precise memory signal reporting is not enabled, watchpoint stop\r\nlocation may not be accurate. See \"show amdgpu precise-memory\".\r\nadd_one done: host[0]=1 host[63]=1\r\n"] +[3.888045, "o", "warning: Temporarily disabling breakpoints for unloaded shared library \"file:///tmp/tmp.aZNGXRzm1I/add_one#offset=8192&size=66944\"\r\n[Thread 0x7ffff2d7e6c0 (LWP 1824786) exited]\r\n"] +[4.037819, "o", "[Thread 0x7ffff27ff6c0 (LWP 1824780) exited]\r\n"] +[4.088431, "o", "[Thread 0x7ffff1ffe6c0 (LWP 1824781) exited]\r\n[Inferior 1 (process 1824775) exited normally]\r\n"] +[5.15237, "o", "\r\n\u001b[1;36m# ROCgdb trapped the exact wave whose 'data[i] += 1' wrote the watched address (Old value = 0, New value = 1).\u001b[0m\r\n"] diff --git a/emulation/rocjitsu/demos/rocgdb-watchpoint.md b/emulation/rocjitsu/demos/rocgdb-watchpoint.md new file mode 100644 index 000000000000..1da36fc7cb05 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-watchpoint.md @@ -0,0 +1,36 @@ +# rocgdb-watchpoint + +Catch which GPU wave writes a buffer with a **hardware data watchpoint** — in +software, with no AMD GPU required. + +Hardware watchpoints (`watch`/`rwatch`/`awatch`) are how you find the code that +touches a piece of memory without single-stepping the whole program. On the +emulated MI350X, ROCgdb programs one of the GPU's four address-watch registers +and the emulator traps the wave whose global-memory access hits the watched +address — reporting the old and new value and stopping at the exact store. + +This demo builds a tiny HIP kernel that adds 1 to every element of a device +buffer, sets a watchpoint on the buffer from GPU context, and continues: the +kernel's `data[i] += 1` store trips the watchpoint (`Old value = 0`, +`New value = 1`), stopped at the source line that wrote it. + +## Run it + +Record (builds a portable mirage + rocjitsu, then captures the `.cast`): + + emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-watchpoint.sh + +Or run against an already-built `mirage`: + + MIRAGE_BIN=/path/to/mirage bash emulation/rocjitsu/demos/rocgdb-watchpoint.sh + +Requires `hipcc` and `rocgdb` on `PATH` (from a ROCm install). + +## How it works + +`break add_one.hip:` stops on the host at the kernel launch so ROCgdb can +read the device pointer `d` (no hard-coded VA); `watch *(int*)$waddr` programs a +hardware watchpoint on that address. When the GPU wave executes `data[i] += 1`, +the emulator's memory pipeline matches the access against the debugger's watch +registers, raises `TRAPSTS.addr_watch`, and stops the wave — exactly as gfx9 +hardware does. See [rocgdb-debugging.md](../docs/rocgdb-debugging.md). diff --git a/emulation/rocjitsu/demos/rocgdb-watchpoint.sh b/emulation/rocjitsu/demos/rocgdb-watchpoint.sh new file mode 100755 index 000000000000..14196988a780 --- /dev/null +++ b/emulation/rocjitsu/demos/rocgdb-watchpoint.sh @@ -0,0 +1,46 @@ +#!/usr/bin/env bash +# +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# Demo: catch which GPU wave writes a buffer with a hardware data watchpoint, +# entirely in software with no AMD GPU. See rocgdb-watchpoint.md. Regenerate the +# .cast with: +# emulation/mirage/scripts/record_demo.sh emulation/rocjitsu/demos/rocgdb-watchpoint.sh + +set -euo pipefail + +here="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +kernel="$here/../tests/rocgdb/add_one.hip" +mirage="${MIRAGE_BIN:-mirage}" + +say() { printf '\n\033[1;36m# %s\033[0m\n' "$*"; } + +say "A tiny HIP kernel that adds 1 to every element of a device buffer:" +sed -n '/__global__/,/^}/p' "$kernel" + +say "Build it for gfx950 (MI350X) with device debug info:" +tmp="$(mktemp -d)" +trap 'rm -rf "$tmp"' EXIT +app="$tmp/add_one" +( set -x; hipcc --offload-arch=gfx950 -g -O0 -o "$app" "$kernel" ) + +# The launch line lets ROCgdb read the device pointer `d` before the kernel runs +# (no hard-coded GPU virtual address). +launch_line="$(grep -nE 'add_one<<<' "$kernel" | head -1 | cut -d: -f1)" + +say "Set a hardware watchpoint on the device buffer and catch the GPU store:" +( set -x + "$mirage" run --profile mi350x --gdb \ + --gdb-ex "break add_one.hip:${launch_line}" \ + --gdb-ex 'break add_one' \ + --gdb-ex 'run' \ + --gdb-ex 'set $waddr = (unsigned long)d' \ + --gdb-ex 'continue' \ + --gdb-ex 'watch *(int*)$waddr' \ + --gdb-ex 'continue' \ + --gdb-ex 'continue' \ + -- "$app" +) + +say "ROCgdb trapped the exact wave whose 'data[i] += 1' wrote the watched address (Old value = 0, New value = 1)." diff --git a/emulation/rocjitsu/docs/rocgdb-debugging.md b/emulation/rocjitsu/docs/rocgdb-debugging.md new file mode 100644 index 000000000000..fce112f8beed --- /dev/null +++ b/emulation/rocjitsu/docs/rocgdb-debugging.md @@ -0,0 +1,127 @@ +# Debugging emulated GPU kernels with ROCgdb + +rocjitsu emulates the AMD KFD closely enough that **real ROCgdb / rocm-dbgapi** +can attach to a workload running on the emulated GPU and debug its kernels — no +physical AMD GPU required. This document explains how the pieces fit together, +how to debug your own kernel, and tracks what is implemented. + +All KFD debug behaviour is mirrored from the real driver source +(`amd/amdkfd/{kfd_chardev.c,kfd_debug.c,kfd_topology.c}`, amdgpu-6.16.13), +cross-checked against a physical MI300X and the in-tree `projects/rocdbgapi`. + +## 1. How the pieces fit together + +ROCgdb does not talk to the GPU directly. It loads `librocm-dbgapi`, which opens +`/dev/kfd` and issues `AMDKFD_IOC_DBG_TRAP` sub-operations against the **pid of +the inferior**; the kernel correlates debugger and inferior by the ptrace +relationship. The emulator has no real `/dev/kfd`, so both processes run under +the rocjitsu LD_PRELOAD interposer and share one rocjitsu **daemon** that hosts +the GPU/wave state. + +```mermaid +flowchart LR + subgraph rocgdb process + G[ROCgdb] --> D[librocm-dbgapi] + D --> I1[interposer] + end + subgraph inferior process + A[HIP app] --> R[ROCr/HIP] + R --> I2[interposer] + end + I1 -- "RPC: DBG_TRAP pid=inferior" --> S[(rocjitsu daemon)] + I2 -- "RPC: queues, memory, waves" --> S + G -. ptrace .-> A +``` + +Local (in-process) mode cannot host ROCgdb: the debugger and inferior would each +get a private `SimulatedDriver`, so the debugger's dbgapi would never see the +inferior's process table. **Daemon mode is mandatory**, and `mirage run` drives +it in one command — it starts the session daemon, runs ROCgdb under the +interposer connected to that session, and ROCgdb launches the inferior into the +same session. The `--gdb` flag wraps the workload for you: + +```bash +mirage run --profile mi350x --gdb -- ./my_hip_app +``` + +is shorthand for `-- rocgdb -ex 'set breakpoint pending on' --args ./my_hip_app`; +drop `--gdb` to pass your own `rocgdb` invocation for full control. + +## 2. Debugging your own kernel + +1. Compile with device debug info, matching the mirage profile's arch + (`mi350x` = `gfx950`): + ```bash + hipcc --offload-arch=gfx950 -g -O0 -o app app.hip + ``` +2. Run under `mirage run --gdb` — one command drops you into ROCgdb with + kernel breakpoints already pending: + ```bash + mirage run --profile mi350x --gdb -- ./app + ``` + Script the session with repeatable `--gdb-ex` commands (implies `--gdb`): + ```bash + mirage run --profile mi350x --gdb-ex 'break add_one' --gdb-ex run -- ./app + ``` +3. In ROCgdb: `break `, `run`. (`--gdb` already applied + `set breakpoint pending on`, so the kernel symbol resolves at dispatch.) + +## 3. Demos + +Recorded, runnable walkthroughs live in `emulation/rocjitsu/demos/` (each has a +`.md` explainer, a runnable `.sh`, and an asciinema `.cast`): + +| Demo | Shows | +|---|---| +| [rocgdb-quickstart](../demos/rocgdb-quickstart.md) | Debug a GPU kernel with one command; inspect arguments and locals | +| [rocgdb-watchpoint](../demos/rocgdb-watchpoint.md) | Catch which wave writes a buffer with a hardware watchpoint | +| [rocgdb-fault](../demos/rocgdb-fault.md) | Catch a GPU memory-access fault (SIGSEGV) | +| [rocgdb-multiwave](../demos/rocgdb-multiwave.md) | Debug a real multi-wave kernel: both waves, each with its own private data | + +Regenerate a `.cast` with `emulation/mirage/scripts/record_demo.sh .sh`. +That script requires `asciinema` on `PATH` and will not install it for you -- +provision it in your container or dev environment (`apt-get install asciinema`, +`pipx install asciinema`). + +## 4. Status + +Real ROCgdb, driven by `mirage run`, **debugs an emulated GPU kernel end to +end**: it attaches, enumerates the GPU agent, stops at a kernel breakpoint, reads +wave registers / PC / disassembly, single-steps instructions, resolves +source-level arguments and locals from private/scratch memory (`print`, +`info args`), and continues the kernel to correct completion. `info agents` lists +the synthetic `gfx950 / MI350X` agent, a breakpoint on a GPU kernel stops the +trapping wave, and a hardware `watch` on GPU memory traps the wave that accesses +it. Multi-wave kernels are fully supported: `info threads` correlates every +trapped wave to its workgroup and position, and each wave reads its own private +memory. + +| Area | Status | +|---|---| +| Topology debug capabilities (`capability`/`debug_prop`) | done | +| `AMDKFD_IOC_DBG_TRAP` dispatcher + validation ladder | done | +| ENABLE / DISABLE + `kfd_runtime_info` | done | +| GET_DEVICE_SNAPSHOT agent enumeration | done | +| Real ptrace authorization + daemon transport | done | +| Debug sessions keyed by inferior pid (attach before connect) | done | +| SET_EXCEPTIONS_ENABLED / SET_FLAGS / launch-mode/override (accept) | done | +| Attach/detach lifecycle (clean detach after inferior exit) | done | +| GET_QUEUE_SNAPSHOT (real queues) | done | +| Wave stop on `s_trap` + CWSR serialization | done | +| Debug events + register write-back (breakpoint stop end to end) | done | +| One-command debugging (`mirage run --gdb` / `--gdb-ex`) | done | +| Deterministic single-step (`stepi`) | done | +| Displaced stepping / step-over (debugger memory reserved) | done | +| GPU address watchpoints (`watch`/`rwatch`/`awatch`) | done | +| Illegal-instruction exception (SIGILL) | done | +| Memory-access violation (SIGSEGV) | done | +| Private/scratch reads (`print`, `info args`) | done | +| Multi-wave workgroup debugging (`info threads`, per-wave scratch) | done | + +## 5. Sources + +- KFD UAPI: `linux/uapi/kfd_ioctl.h`, `linux/uapi/kfd_sysfs.h` (vendored). +- KFD driver: `amd/amdkfd/{kfd_chardev.c,kfd_debug.c,kfd_topology.c}` + (amdgpu-6.16.13). +- Client: `projects/rocdbgapi/src/os_driver_kfd.cpp`. +- Hardware cross-check: MI300X sysfs `capability` / `debug_prop`. diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py index 457eaa36e047..d780c932cd6e 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py @@ -4545,6 +4545,131 @@ def _true16_vop3_info( enabled=enabled, ) + # The trap-handler control ops are spelled differently per ISA. Every + # spelling has to be listed: an omitted one derives as `true_nop` and its + # generated execute_impl() comes out an empty body, which leaves that ISA's + # trap handlers unable to return at all. GFX1250 spells the return + # S_RFE_I64 (SOP1 opcode 74). + _TRAP_RETURN_NAMES = ('S_RFE', 'S_RFE_B64', 'S_RFE_I64') + _TRAP_SENDMSG_NAMES = ('S_SENDMSG', 'S_SENDMSGHALT') + + def _sleep_body(self, sem: InstructionSemantics) -> str: + """execute() body for S_SLEEP / S_SLEEP_VAR. + + The MR ISA gives these no pseudocode, so they derive as `true_nop` and + the generator used to emit the yield alone. The delay *is* the whole + instruction -- there is no result register -- so retiring it in one step + leaves it with no effect and lets a sleep loop spin at the speed of its + own scalar code. That is not only a performance detail: an asynchronous + debugger suspend then lands uniformly across the loop body instead of + overwhelmingly on the sleep, and -O0 loop bodies are full of short + windows where the compiler has forced EXEC to all lanes to spill an + AGPR. Stopping inside one reports every lane active, which + gdb.rocm/lane-info.exp catches by comparing the stopped lane states + against the ones it recorded at a breakpoint. That expect test is the + only guard -- the C++ ISA harness lists s_sleep in SKIP_PREFIXES -- so + the policy belongs here, where a regeneration cannot drop it. + """ + # S_SLEEP idles the wave for 64 * SIMM16[6:0] clocks; S_SLEEP_VAR takes + # the same 7-bit count from a scalar operand instead of the literal. + count = ( + 'static_cast(simm16.encoding_value_)' + if sem.name == 'S_SLEEP' + else 'amdgpu::RegisterAccess(wf).read_scalar(ssrc0)' + ) + return ( + ' constexpr uint32_t kSleepClocksPerUnit = 64;\n' + f' wf.set_sleep_cycles(kSleepClocksPerUnit * ({count} & 0x7Fu));\n' + ' wf.cu().request_functional_yield();' + ) + + def _trap_control_body(self, sem: InstructionSemantics) -> str | None: + """execute() body for a trap-handler control op, or None if not one. + + The MR ISA carries no pseudocode for these, so they derive as + `true_nop`. They are not nops: the configured GPU trap handler returns + through S_RFE and reports through S_SENDMSG, and leaving them empty + silently disables ROCgdb's whole stop/resume path (see + docs/rocgdb-debugging.md). The bodies belong here rather than in a + hand-edit of the generated header, which a regeneration would drop. + """ + if sem.name in self._TRAP_RETURN_NAMES: + # Return from exception: restore the PC the trap handler saved in + # ssrc0. The 48-bit mask drops the status bits the hardware packs + # into the high half, and the instruction size is subtracted + # because the interpreter advances the PC after execute() returns. + return ( + # Bare operand and size_ spellings: that is the arch-local form + # every generated execute_impl() uses, and + # _write_shared_execute_templates() lifts them to inst.ssrc0 / + # inst.size() for the shared template. Writing the lifted form + # here instead compiles only on the ISAs that happen to share + # the body -- S_RFE_I64 is gfx1250-only, so it does not. + ' uint64_t saved_pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0);\n' + ' constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL;\n' + ' wf.pc = (saved_pc & kPcAddressMask) - size_;\n' + '\n' + ' // Returning from the handler puts the interrupted EXEC back. The handler runs\n' + ' // under its own mask -- it parks a doorbell id in EXEC_LO on the way to\n' + ' // MSG_INTERRUPT -- and restoring that is part of returning, not part of\n' + ' // stopping for a debugger: a handler that returns without stopping the wave\n' + ' // used to leave its mask installed, so the application ran on with every lane\n' + ' // active. That silently un-diverges a branch (gdb.rocm/lane-info.exp sees\n' + ' // lanes that converged out of a branch reported active again) and is\n' + ' // permanent, because nothing later puts the application\'s mask back.\n' + ' if (wf.in_trap_handler())\n' + ' wf.set_exec(wf.trap_saved_exec());\n' + ' wf.set_in_trap_handler(false);\n' + '\n' + ' // The handler sets STATUS.HALT when it wants the wave to stay\n' + ' // stopped for the debugger; honour that on the way out.\n' + ' constexpr uint32_t kStatusHalt = 1u << 13;\n' + ' if ((wf.status_raw() & kStatusHalt) != 0) {\n' + ' wf.set_debug_single_step(false);\n' + ' wf.set_debug_halted(true);\n' + ' } else {\n' + ' // Nothing is halting the wave any more, so an s_sendmsghalt marker\n' + ' // left over from an earlier stop is stale. Leaving it set would make\n' + ' // the next resume clear a HALT the handler raises later.\n' + ' wf.set_self_halted(false);\n' + ' }' + ) + + if sem.name in self._TRAP_SENDMSG_NAMES: + # MSG_INTERRUPT (id 1) from inside the trap handler is how the wave + # tells KFD it has stopped; the CU turns it into a debug event. + body = ( + ' const uint32_t message = static_cast(simm16.encoding_value_);\n' + ' if (wf.in_trap_handler() && (message & 0xFu) == 1u)\n' + ' wf.set_trap_interrupt_sent(true);\n' + ' wf.cu().handle_sendmsg(wf, message);' + ) + if sem.name == 'S_SENDMSGHALT': + # "...and then HALT the wavefront". The halt is architectural, + # so publish it in STATUS.HALT and not only in the debugger's + # private flag: the s_rfe path above reads STATUS.HALT to decide + # whether the wave stays stopped, and saw 0 for a wave this + # instruction had already halted. Both halves now agree, and a + # debugger reading STATUS sees the same thing the wave does. + body += ( + '\n' + '\n' + ' // S_SENDMSGHALT halts the wave. Keep the architectural bit and the\n' + ' // scheduler flag in step -- s_rfe consults STATUS.HALT on the way out.\n' + ' constexpr uint32_t kStatusHalt = 1u << 13;\n' + ' wf.set_status_raw(wf.status_raw() | kStatusHalt);\n' + ' wf.set_debug_halted(true);\n' + ' // Remember who raised the bit. The trap handler also raises HALT, via\n' + ' // s_setreg just before it returns, and there it means "keep the wave\n' + ' // stopped" -- the opposite of what it means here, where the wave has\n' + ' // already reported and is waiting to be resumed. The CWSR record cannot\n' + ' // distinguish the two, so the resume path reads this instead.\n' + ' wf.set_self_halted(true);' + ) + return body + + return None + def _gen_execute_body( self, inst: Instruction, sem: InstructionSemantics, enc_name: str = '' ) -> str: @@ -4873,13 +4998,13 @@ def _semantic_reg_class(opnd: Operand) -> RegClass: # Fallback: inline dispatch for classes not yet extracted. L = [] # output lines - # Sleep has no architectural register effect, but FUNCTIONAL execution - # must return to the event loop so peer CUs can make progress. - if cls == 'true_nop' and sem.name in ('S_SLEEP', 'S_SLEEP_VAR'): - return ' wf.cu().request_functional_yield();' - if cls == 'true_nop': - return ' (void)wf;' + # Sleep has no architectural register effect, but FUNCTIONAL + # execution must return to the event loop so peer CUs can make + # progress. + if sem.name in ('S_SLEEP', 'S_SLEEP_VAR'): + return self._sleep_body(sem) + return self._trap_control_body(sem) or ' (void)wf;' if cls == 'gpr_idx': if op == 'on': @@ -5060,17 +5185,39 @@ def _semantic_reg_class(opnd: Operand) -> RegClass: return '\n'.join(L) if cls == 'scalar_setpc': + L.append(' constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL;') + L.append(' constexpr uint64_t kPcSignBit = 1ULL << 47;') L.append( - f' wf.pc = amdgpu::RegisterAccess(wf).read_scalar64({src_ops[0]}) - size_;' + f' const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64({src_ops[0]});' ) + L.append(' uint64_t target = encoded & kPcAddressMask;') + L.append( + ' if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0)' + ) + L.append( + ' target = wf.code_load_bias() + static_cast(encoded);' + ) + L.append(' else if (target & kPcSignBit)') + L.append(' target |= ~kPcAddressMask;') + L.append(' wf.pc = target - size_;') return '\n'.join(L) if cls == 'scalar_swappc': # S_SWAPPC_B64: dst = PC of next inst, then jump to src. + L.append(' constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL;') + L.append(' constexpr uint64_t kPcSignBit = 1ULL << 47;') L.append(f' uint64_t next_pc = wf.pc + size_;') L.append( - f' wf.pc = amdgpu::RegisterAccess(wf).read_scalar64({src_ops[0]}) - size_;' + f' const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64({src_ops[0]});' + ) + L.append(' uint64_t target = encoded & kPcAddressMask;') + L.append( + ' if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0)' ) + L.append(' target = next_pc - 20 + static_cast(encoded);') + L.append(' else if (target & kPcSignBit)') + L.append(' target |= ~kPcAddressMask;') + L.append(' wf.pc = target - size_;') L.append( f' amdgpu::RegisterAccess(wf).write_scalar64({dst_ops[0]}, next_pc);' ) @@ -5604,9 +5751,9 @@ def _semantic_reg_class(opnd: Operand) -> RegClass: return ( ' static thread_local uint64_t counter = 0;\n' ' counter += 100;\n' - ' uint32_t dst = wf.sgpr_alloc().base + inst_.sdata;\n' - ' amdgpu::RegisterAccess(wf).write_sgpr(dst, static_cast(counter));\n' - ' amdgpu::RegisterAccess(wf).write_sgpr(dst + 1, static_cast(counter >> 32));' + ' const uint32_t dst_sel = inst_.sdata;\n' + ' amdgpu::write_scalar_selector(wf, dst_sel, static_cast(counter));\n' + ' amdgpu::write_scalar_selector(wf, dst_sel + 1, static_cast(counter >> 32));' ) if cls == 'gl1_wbinv': @@ -5794,6 +5941,7 @@ def _gen_smem_load( nd = sem.num_elems if elem_size == 4 else 1 L.append(' auto d = std::make_unique();') L.append(f' d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata;') + L.append(f' d->dst_selector = inst_.sdata;') L.append(f' d->num_dwords = {nd};') L.append(f' d->elem_size = {elem_size};') L.append(f' d->sign_extend = {str(sem.sign_extend).lower()};') @@ -5821,11 +5969,10 @@ def _gen_smem_store( L.append(' d->is_load = false;') self._append_wait_counter_type(L, 'smem_store') L.append(f' d->mtype = {self._mtype_expr(is_smem=True)};') - L.append(' auto &cu = wf.cu();') - L.append(' uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata;') + L.append(' const uint32_t sdata_sel = inst_.sdata;') L.append(f' for (uint32_t i = 0; i < {nd}; ++i)') L.append( - ' d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i);' + ' d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i);' ) if self.isa_spec.profile.smem_address_uses_access_size: addr_args = 'inst_, wf, d->elem_size * d->num_dwords' @@ -10555,6 +10702,7 @@ def _write_shared_execute_templates(self) -> None: '#include "rocjitsu/vm/amdgpu/mem_state.h"', '#include "rocjitsu/vm/amdgpu/register_access.h"', '#include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h"', + '#include "rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h"', '#include "rocjitsu/isa/arch/amdgpu/shared/transcendental.h"', '#include "rocjitsu/isa/arch/amdgpu/shared/pseudo_scalar.h"', *simd_extra_includes(), @@ -10579,9 +10727,28 @@ def _write_shared_execute_templates(self) -> None: f'[[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) {{' ) probe = simd_probe_line(mnemonic, true16_vop3=is_true16_vop3) + alu_classifiers = { + 'v_mul_f32_vop2': 'classify_mul_f32_vop2', + 'v_mul_f32_vop3': 'classify_mul_f32_vop3', + 'v_sqrt_f32_vop1': 'classify_sqrt_f32_vop1', + 'v_sqrt_f32_vop3': 'classify_sqrt_f32_vop3', + 'v_div_fixup_f32_vop3': 'classify_div_fixup_f32_exceptions', + 'v_rcp_iflag_f32_vop1': 'classify_rcp_iflag_f32_exceptions', + 'v_rcp_iflag_f32_vop3': 'classify_rcp_iflag_f32_exceptions', + } + classifier = alu_classifiers.get(mnemonic) + if classifier is not None: + lines.append(f' uint32_t alu_causes = {classifier}(inst, wf);') if probe is not None: - lines.append(probe) + if classifier is None: + lines.append(probe) + else: + lines.append(' if (!(wf.mode_raw() & kAluExceptionModeMask)) {') + lines.append(probe.replace(' ', ' ', 1)) + lines.append(' }') lines.append(prefixed_body) + if classifier is not None: + lines.append(' wf.set_trapsts(wf.trapsts() | alu_causes);') lines.append('}') lines.append('') diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py index 9ab84a3c002c..3e515b21ef1a 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/__init__.py @@ -81,6 +81,7 @@ def _register_handlers() -> None: gen_vector_cmpx, ) from amdisa.codegen.execute.vector_special import ( + gen_vector_bcnt, gen_vector_mbcnt, gen_vector_movrel, gen_vector_mad_64_32, @@ -148,6 +149,7 @@ def _register_handlers() -> None: ) # Vector special + DISPATCH['vector_bcnt'] = lambda c: gen_vector_bcnt(c.dst_ops, c.src_ops) DISPATCH['vector_mbcnt'] = lambda c: gen_vector_mbcnt(c.dst_ops, c.src_ops, c.op) DISPATCH['vector_movrel'] = lambda c: gen_vector_movrel( c.dst_ops, c.src_ops, c.op, c.profile.uses_vgpr_msb_indexing diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/simd_codegen.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/simd_codegen.py index c84a198f4dab..bad9340d659e 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/simd_codegen.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/simd_codegen.py @@ -1747,6 +1747,13 @@ def _build_simd_vopc_vop3_f64() -> dict[str, str]: # 16-bit wrap. 32-bit forms use the wrap-around add/sub on uint32 lanes; # signed-vs-unsigned wraps the same way. SIMD_VOP3_BINARY_INT_EXTRA: dict[str, tuple[str, str]] = { + # v_bcnt_u32_b32: VOP3-only (no VOP1 twin). D = CountOneBits(S0) + S1 -- the + # second source is an accumulator, so this is binary, not unary. Keep the + # functor in step with the scalar body in vector_alu.py. + 'v_bcnt_u32_b32_vop3': ( + 'uint32_t', + '[](auto a, auto b) { return util::popcount_u32_simd(a) + b; }', + ), # Pack two clamped 32-bit ints into the hi/lo 16-bit halves of the dst. # v_cvt_pk_i16_i32: signed-clamp each source to [-32768, 32767]; u16_u32: # unsigned-saturate each to 0xFFFF. Pure element-wise, no modifiers. @@ -1939,14 +1946,6 @@ def _build_simd_vopc_vop3_f64() -> dict[str, str]: 'uint32_t', '[](auto a) { return (~a) & 0xFFFFu; }', ), - # v_bcnt_u32_b32: VOP3-only (no VOP1 twin). The scalar body is a plain - # std::popcount(src0) -> vdst (src1 is read but unused by this codebase's - # body), so the unary src0->vdst glue is bit-exact. - 'v_bcnt_u32_b32_vop3': ( - 'uint32_t', - 'uint32_t', - '[](auto a) { return util::popcount_u32_simd(a); }', - ), } diff --git a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py index e1479c7bc876..c6ca75356ba5 100644 --- a/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py +++ b/emulation/rocjitsu/lib/python/amdisa/codegen/execute/vector_special.py @@ -86,6 +86,26 @@ def _read_vop3_true16_src(opnd: str, opsel: str, src_idx: int) -> str: ) +def gen_vector_bcnt(dst: list[str], src: list[str]) -> str: + """Generate V_BCNT_U32_B32 body: D.u32 = CountOneBits(S0.u32) + S1.u32.""" + L = [] + L.append(' uint64_t exec = wf.exec();') + L.append(' for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) {') + L.append(' if (!(exec & (1ULL << lane))) continue;') + L.append( + f' uint32_t bits = amdgpu::RegisterAccess(wf).read_lane({src[0]}, lane);' + ) + L.append( + f' uint32_t accum = amdgpu::RegisterAccess(wf).read_lane({src[1]}, lane);' + ) + L.append( + f' amdgpu::RegisterAccess(wf).write_lane({dst[0]}, lane,' + ' static_cast(std::popcount(bits)) + accum);' + ) + L.append(' }') + return '\n'.join(L) + + def gen_vector_mbcnt(dst: list[str], src: list[str], op: str | None) -> str: """Generate V_MBCNT_LO/HI_U32_B32 body.""" L = [] diff --git a/emulation/rocjitsu/lib/python/amdisa/semantics.py b/emulation/rocjitsu/lib/python/amdisa/semantics.py index f20fb388b247..a95eba224212 100644 --- a/emulation/rocjitsu/lib/python/amdisa/semantics.py +++ b/emulation/rocjitsu/lib/python/amdisa/semantics.py @@ -1134,6 +1134,14 @@ def _derive_vop3(name: str) -> InstructionSemantics | None: if name in ('V_MQSAD_PK_U16_U8', 'V_MQSAD_U32_U8', 'V_QSAD_PK_U16_U8'): return InstructionSemantics(name, 'nop') + # Bit count with accumulate: D.u32 = CountOneBits(S0.u32) + S1.u32. The MR + # ISA gives no pseudocode, so the generic stem table below would derive this + # as a plain unary popcount and silently drop S1 -- the same shape as the + # V_MBCNT_* pair right underneath, which is why it is classified the same + # way rather than as a 'vector_unary'. + if name == 'V_BCNT_U32_B32': + return InstructionSemantics(name, 'vector_bcnt', data_type='u32') + # Masked bit count if name == 'V_MBCNT_LO_U32_B32': return InstructionSemantics( diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_sleep_body.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_sleep_body.py new file mode 100644 index 000000000000..88966112118a --- /dev/null +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_sleep_body.py @@ -0,0 +1,56 @@ +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT + +"""S_SLEEP derives as `true_nop` and gets a real delay from the generator. + +The MR ISA gives S_SLEEP no pseudocode, and the delay *is* the instruction -- +there is no result register -- so a body that only yields leaves it with no +architectural effect and lets a sleep loop spin at the speed of its own scalar +code. The delay lived in a hand-edit of the checked-in generated header once, +which meant the next regeneration reverted it. Nothing in the C++ ISA harness +catches that (it lists s_sleep in SKIP_PREFIXES); the only guard is +gdb.rocm/lane-info.exp, hours away in the expect suite. These tests are the +near guard. +""" + +from types import SimpleNamespace + +from amdisa.codegen import CodeGenerator + + +def _body(name: str) -> str: + """Emitted execute() body for a sleep op, straight from the generator.""" + generator = CodeGenerator.__new__(CodeGenerator) + sem = SimpleNamespace( + name=name, + semantic_class='true_nop', + operation=None, + data_type=None, + sets_scc=None, + branch_condition=None, + ) + return CodeGenerator._sleep_body(generator, sem) + + +class TestSleepBody: + def test_sleep_charges_the_wave_for_the_delay(self): + body = _body('S_SLEEP') + assert 'wf.set_sleep_cycles(' in body + assert 'kSleepClocksPerUnit = 64' in body + + def test_sleep_takes_its_count_from_the_literal(self): + body = _body('S_SLEEP') + assert 'simm16.encoding_value_' in body + assert '0x7Fu' in body + + def test_sleep_var_takes_its_count_from_a_scalar(self): + """S_SLEEP_VAR is the same delay with the 7-bit count in an operand.""" + body = _body('S_SLEEP_VAR') + assert 'read_scalar(ssrc0)' in body + assert '0x7Fu' in body + assert 'wf.set_sleep_cycles(' in body + + def test_both_still_yield_to_the_event_loop(self): + """FUNCTIONAL execution has to return so peer CUs can make progress.""" + for name in ('S_SLEEP', 'S_SLEEP_VAR'): + assert 'wf.cu().request_functional_yield();' in _body(name), name diff --git a/emulation/rocjitsu/lib/python/amdisa/tests/test_trap_control_bodies.py b/emulation/rocjitsu/lib/python/amdisa/tests/test_trap_control_bodies.py new file mode 100644 index 000000000000..33321b253a29 --- /dev/null +++ b/emulation/rocjitsu/lib/python/amdisa/tests/test_trap_control_bodies.py @@ -0,0 +1,112 @@ +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT + +"""The trap-handler control ops derive as `true_nop` and get real bodies. + +The MR ISA carries no pseudocode for S_RFE / S_SENDMSG / S_SENDMSGHALT, so +they derive as `true_nop`. They are not nops: the configured GPU trap handler +returns through S_RFE and reports through S_SENDMSG, and leaving these empty +disables ROCgdb's whole stop/resume path. The bodies therefore live in the +generator, and these tests pin the parts of them that a regeneration has +previously been able to silently drop. +""" + +from types import SimpleNamespace + +from amdisa.codegen import CodeGenerator + + +def _body(name: str) -> str: + """Emitted execute() body for a trap-control op, straight from the generator.""" + generator = CodeGenerator.__new__(CodeGenerator) + sem = SimpleNamespace( + name=name, + semantic_class='true_nop', + operation=None, + data_type=None, + sets_scc=None, + branch_condition=None, + ) + return CodeGenerator._trap_control_body(generator, sem) + + +class TestSRfeBody: + def test_restores_the_saved_pc(self): + body = _body('S_RFE_B64') + assert 'read_scalar64(ssrc0)' in body + assert 'kPcAddressMask' in body + + def test_restores_the_interrupted_exec(self): + """Regression: a handler that returns without stopping the wave used to + leave its own EXEC mask installed, silently un-diverging a branch for + the rest of the kernel. gdb.rocm/lane-info.exp catches it, as does + WaveDebugTest.TrapHandlerRestoresInterruptedExecWhenReturningWithoutStopping. + This block once existed only in the checked-in generated header, so the + next regeneration would have removed it.""" + body = _body('S_RFE_B64') + assert 'wf.set_exec(wf.trap_saved_exec());' in body + assert 'if (wf.in_trap_handler())' in body + # The restore has to happen while the flag still says we are in the + # handler, so it must precede the clear. + assert body.index('wf.set_exec(wf.trap_saved_exec());') < body.index( + 'wf.set_in_trap_handler(false);' + ) + + def test_honours_status_halt_on_the_way_out(self): + body = _body('S_RFE_B64') + assert 'kStatusHalt' in body + assert 'wf.set_debug_halted(true);' in body + + def test_every_spelling_of_the_return_gets_a_body(self): + """GFX1250 spells it S_RFE_I64 (SOP1 opcode 74). Omitting a spelling + leaves that ISA's generated execute_impl() an empty no-op, so its trap + handlers can never return.""" + for name in ('S_RFE', 'S_RFE_B64', 'S_RFE_I64'): + body = _body(name) + assert 'kPcAddressMask' in body, f'{name} has no trap-return body' + assert 'wf.set_exec(wf.trap_saved_exec());' in body, name + + +class TestSendmsgBody: + def test_reports_msg_interrupt_from_inside_the_handler(self): + body = _body('S_SENDMSG') + assert 'wf.set_trap_interrupt_sent(true);' in body + assert 'wf.cu().handle_sendmsg(wf, message);' in body + + def test_sendmsghalt_halts_through_architectural_status(self): + """S_SENDMSGHALT halts the wave -- that is the instruction, not a + debugger artefact. Setting only the debugger's private flag left the + two halves disagreeing: the s_rfe body reads STATUS.HALT to decide + whether the wave stays stopped, and saw 0 for a wave this instruction + had already halted.""" + body = _body('S_SENDMSGHALT') + assert 'kStatusHalt' in body + assert 'wf.set_status_raw(' in body + assert 'wf.set_debug_halted(true);' in body + + def test_sendmsghalt_records_that_it_raised_the_halt(self): + """The trap handler raises STATUS.HALT too, with s_setreg just before it + returns, and there the bit means "keep the wave stopped" -- the opposite + of what it means here. The CWSR record cannot tell the two apart, so the + resume path in SimulatedKfd::apply_cwsr_to_wave reads this marker to + decide whether clearing HALT loses a breakpoint or unsticks a wave.""" + body = _body('S_SENDMSGHALT') + assert 'wf.set_self_halted(true);' in body + + def test_plain_sendmsg_does_not_halt(self): + body = _body('S_SENDMSG') + assert 'set_debug_halted' not in body + assert 'set_self_halted' not in body + + +class TestSelfHaltedProvenance: + def test_rfe_clears_a_stale_marker_when_nothing_is_halting_the_wave(self): + """Leaving the marker set past a resume would make the *next* stop clear + a STATUS.HALT the trap handler raised, silently losing that breakpoint.""" + body = _body('S_RFE_B64') + assert 'wf.set_self_halted(false);' in body + # Only on the not-halted path: a wave staying stopped keeps its + # provenance, which is what the resume needs to read. + assert body.index('wf.set_debug_halted(true);') < body.index( + 'wf.set_self_halted(false);' + ) diff --git a/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/vm/rj_vm.h b/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/vm/rj_vm.h index 5044d3d9405b..e6c36f25ec66 100644 --- a/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/vm/rj_vm.h +++ b/emulation/rocjitsu/lib/rocjitsu/include/rocjitsu/vm/rj_vm.h @@ -54,12 +54,14 @@ typedef enum rj_vm_mode_t { /// @brief Device command descriptor for rj_vm_execute. typedef struct rj_vm_cmd_t { - uint32_t cmd; ///< Platform-specific command number. - void *buf; ///< Command arguments buffer (with inlined arrays). - size_t buf_size; ///< Total size of the arguments buffer. - int32_t result; ///< [out] Return code (0 on success, negative errno on failure). - rj_handle_t shared_handle; ///< [out] Borrowed backing handle, or -1; owned by the VM. - rj_handle_t in_handle; ///< [in,out] Client-provided fd (e.g. debugger notifier), or -1. + uint32_t cmd; ///< Platform-specific command number. + void *buf; ///< Command arguments buffer (with inlined arrays). + size_t buf_size; ///< Total size of the arguments buffer. + int32_t result; ///< [out] Return code (0 on success, negative errno on failure). + rj_handle_t shared_handle; ///< [out] Borrowed backing handle, or -1; owned by the VM. + rj_handle_t in_handle; ///< [in,out] Client-provided fd (e.g. debugger notifier), or -1. + rj_handle_t in_mem_handle; ///< [in,out] Debugger-authorized target /proc/pid/mem fd, or -1. + rj_handle_t in_proc_handle; ///< [in] Pinned target /proc/pid directory fd, or -1. } rj_vm_cmd_t; /// @brief Device memory mapping descriptor. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp index 407331b07610..6d0fb40968d1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp @@ -3,12 +3,14 @@ #include "rocjitsu/config/checkpoint.h" #include "rocjitsu/config/config_loader.h" +#include "rocjitsu/isa/arch/amdgpu/generated/shared/isa_properties.h" #include "rocjitsu/vm/virtual_machine.h" #include "checkpoint_generated.h" #include "flatbuffers/flatbuffers.h" #include +#include #include #include #include @@ -19,6 +21,14 @@ namespace config { namespace { +/// @brief First scalar selector that named a TTMP before TTMPs became their own +/// register file. +/// @details The decoder used to alias selectors 108..123 into the wavefront SGPR +/// block on every architecture, so in a checkpoint written then those slots hold +/// exactly the TTMP file. Selectors that high are unreachable as ordinary SGPR +/// operands, so reading them back as TTMPs needs no per-architecture test. +constexpr uint32_t kLegacyTtmpSgprBase = 108; + flatbuffers::Offset> serialize_vgpr_block(flatbuffers::FlatBufferBuilder &builder, const amdgpu::ComputeUnitCore &cu, uint32_t base) { @@ -146,14 +156,49 @@ void save_checkpoint(const std::string &path, const SoC &soc, uint64_t tick, if (w->is_halted()) continue; + // The record holds the architectural registers and the TTMPs, but + // none of the trap/debug state around them: in_trap_handler, the + // saved EXEC and STATUS the handler will restore, TRAPSTS, and the + // halted/suspended reasons. Restoring a wave captured mid-handler + // from such a record would skip the EXEC restore and the privileged + // STATUS write on the way out and resume the application with the + // handler's state installed -- silently wrong, and hard to trace + // back here. Refuse instead of writing a checkpoint that cannot be + // restored faithfully. + // + // debug_stopped(), not debug_paused(): a wave whose only pause reason + // is the runtime's (queue_percentage 0) carries no trap or debugger + // state, and the CP re-derives queue suspension on restore. Refusing + // it would make an ordinary throttled queue unable to checkpoint, and + // blame a debugger that is not attached. + if (w->in_trap_handler() || w->debug_stopped()) + throw std::runtime_error( + "Cannot checkpoint " + cu->name() + " wf" + std::to_string(w->wf_id()) + + ": the wave is in a trap handler or stopped for a debugger, and that state " + "is not part of the checkpoint format"); + auto sgprs_vec = builder.CreateVector(cu->sgpr_data(w->sgpr_alloc().base), w->num_sgprs()); auto vgprs_vec = serialize_vgpr_block(builder, *cu, w->vgpr_alloc().base); + // TTMPs are their own file, so they are not covered by sgprs_vec. + std::array ttmps{}; + for (uint32_t t = 0; t < ttmps.size(); ++t) + ttmps[t] = w->ttmp(t); + auto ttmps_vec = builder.CreateVector(ttmps.data(), ttmps.size()); + + // Dispatch identity. The flat wg_id above cannot stand in for it -- + // unflattening needs the grid dimensions, which belong to the + // dispatch packet and are not checkpointed -- and trap entry publishes + // exactly these three values in TTMP8/9/10 for the CWSR record to + // match. + const auto &wg_coord = w->wg_coord(); + auto wg_coord_vec = builder.CreateVector(wg_coord.data(), wg_coord.size()); + auto wfs = fb::CreateWavefrontState(builder, w->wf_id(), w->wg_id(), w->pc, w->exec_raw(), w->vcc(), w->m0(), w->is_halted(), w->status_raw(), sgprs_vec, vgprs_vec, w->mode_raw(), - w->wave_sched_mode_raw()); + w->wave_sched_mode_raw(), ttmps_vec, wg_coord_vec); wf_offsets.push_back(wfs); } @@ -278,13 +323,45 @@ LoadedConfig restore_checkpoint(const std::string &path) { wf->set_mode_raw(wf_state->mode()); wf->set_wave_sched_mode_raw(wf_state->wave_sched_mode()); - if (auto *sgprs = wf_state->sgprs()) { + const auto *sgprs = wf_state->sgprs(); + if (sgprs != nullptr) { for (size_t r = 0; r < sgprs->size() && r < wf->num_sgprs(); ++r) { cu->write_sgpr(wf->sgpr_alloc().base + static_cast(r), sgprs->Get(static_cast(r))); } } + if (auto *ttmps = wf_state->ttmps()) { + for (uint32_t t = 0; t < ttmps->size() && t < 16; ++t) + wf->set_ttmp(t, ttmps->Get(t)); + } else if (sgprs != nullptr && sgprs->size() > kLegacyTtmpSgprBase) { + // Written before TTMPs were split out of the SGPR file. Back then + // the decoder aliased scalar selectors 108..123 into the SGPR block + // on every architecture, so those slots are exactly the TTMP file + // and the migration needs no per-arch test. Leaving them behind + // loses real launch state: RDNA4 and GFX1250 seed TTMP6/7/9 with + // workgroup ids at dispatch, and TTMP operands no longer read the + // SGPR slots the old checkpoint restores them into. + const uint32_t available = std::min(16, sgprs->size() - kLegacyTtmpSgprBase); + for (uint32_t t = 0; t < available; ++t) + wf->set_ttmp(t, sgprs->Get(kLegacyTtmpSgprBase + t)); + } + + // Dispatch identity. A record written before this field existed has + // to fall back to something defined, and the only other place the + // coordinate appears is the TTMP file: on the architectures that do + // not carry workgroup ids in TTMP6/7/9, trap entry writes x/y/z into + // TTMP8/9/10 and the CWSR codec reads them from there, so those slots + // are authoritative for any wave that reached a trap handler. Waves + // that never trapped leave them zero, which is what the coordinate + // restored to before this field was added; nothing else in an old + // record can improve on that. + if (auto *wg_coord = wf_state->wg_coord(); wg_coord != nullptr && wg_coord->size() >= 3) { + wf->set_wg_coord(wg_coord->Get(0), wg_coord->Get(1), wg_coord->Get(2)); + } else if (!isa_properties(cu->arch()).uses_ttmp_workgroup_ids) { + wf->set_wg_coord(wf->ttmp(8), wf->ttmp(9), wf->ttmp(10)); + } + // dispatch_wf_at() has just allocated this block, so RegisterFile::allocate()'s // zero-state postcondition satisfies the sparse restore helper's precondition. if (auto *vgprs = wf_state->vgprs()) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/addr_calc.cpp index 47bed7ae9542..cbe600f0a4e5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna4/addr_calc.cpp @@ -5,6 +5,7 @@ #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_flat.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" @@ -27,16 +28,14 @@ uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront & // S_SCRATCH_LOAD / S_SCRATCH_STORE per CDNA4 ISA spec (section 8.2.1.1): // ADDR = SGPR[base] + inst_offset + { M0 or SGPR[soffset] or zero } * 64 - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t inst_offset = 0; if (inst.imm) inst_offset = static_cast(static_cast(inst.offset << 11) >> 11); uint64_t sgpr_off = 0; if (inst.soffset_en) - sgpr_off = amdgpu::RegisterAccess(cu).read_sgpr(wf.sgpr_alloc().base + inst.soffset); + sgpr_off = amdgpu::read_scalar_selector(wf, inst.soffset); uint64_t addr = base + inst_offset + sgpr_off * 64; util::Logger::cp([&](auto &os) { static thread_local uint64_t scratch_smem_count = 0; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp index 401bb84ae024..f92b52ebaa00 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.cpp @@ -4,6 +4,7 @@ #include "rocjitsu/isa/arch/amdgpu/cdna5/addr_calc.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/operand_types.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/lds.h" #include "rocjitsu/vm/amdgpu/mem_state.h" @@ -167,11 +168,9 @@ BufferResource decode_buffer_resource(uint32_t srd0, uint32_t srd1, uint32_t srd uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf, uint32_t access_size_bytes) { - auto &cu = wf.cu(); assert(access_size_bytes != 0); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t off = static_cast(signed_ioffset(inst.ioffset)); uint32_t scale = inst.scale_offset ? access_size_bytes : 1; if (has_smem_offset(inst.soffset)) @@ -243,11 +242,14 @@ void mubuf_calculate_addresses(const VbufferMachineInst &inst, amdgpu::Wavefront auto &cu = wf.cu(); init_vector_mem_state(wf, d); uint64_t exec = d.exec_mask; - uint32_t sb = wf.sgpr_alloc().base + inst.rsrc; - uint32_t srd0 = amdgpu::RegisterAccess(cu).read_sgpr(sb); - uint32_t srd1 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 1); - uint32_t srd2 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 2); - uint32_t srd3 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 3); + // Read through the scalar selector rather than the SGPR allocation: a + // descriptor sourced from TTMPs lives in the trap-temporary file, and + // read_sgpr() would fetch whatever the allocation holds at that index. + const uint32_t sb_sel = inst.rsrc; + uint32_t srd0 = amdgpu::read_scalar_selector(wf, sb_sel); + uint32_t srd1 = amdgpu::read_scalar_selector(wf, sb_sel + 1); + uint32_t srd2 = amdgpu::read_scalar_selector(wf, sb_sel + 2); + uint32_t srd3 = amdgpu::read_scalar_selector(wf, sb_sel + 3); BufferResource resource = decode_buffer_resource(srd0, srd1, srd2, srd3); uint32_t soffset_val = has_smem_offset(inst.soffset) ? read_sreg_m0_operand(wf, inst.soffset) : 0; int32_t ioff = signed_ioffset(inst.ioffset); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem_exec.cpp index b7ce1ae654a9..17b5f0e24ce5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/smem_exec.cpp @@ -11,7 +11,6 @@ #include "rocjitsu/isa/arch/amdgpu/shared/simd_glue.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" -#include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" #include "util/data_types.h" #include "util/except.h" @@ -28,6 +27,7 @@ namespace cdna1 { void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -41,6 +41,7 @@ void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -54,6 +55,7 @@ void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -67,6 +69,7 @@ void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -80,6 +83,7 @@ void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -93,6 +97,7 @@ void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -106,6 +111,7 @@ void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -119,6 +125,7 @@ void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -132,6 +139,7 @@ void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -145,6 +153,7 @@ void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -158,6 +167,7 @@ void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -171,6 +181,7 @@ void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -184,6 +195,7 @@ void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -200,10 +212,9 @@ void SStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -214,10 +225,9 @@ void SStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -228,10 +238,9 @@ void SStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -242,10 +251,9 @@ void SScratchStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -256,10 +264,9 @@ void SScratchStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -270,10 +277,9 @@ void SScratchStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -284,10 +290,9 @@ void SBufferStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -298,10 +303,9 @@ void SBufferStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -312,10 +316,9 @@ void SBufferStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1_exec.cpp index e823905772c6..a20eda2e29fc 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna1/sop1_exec.cpp @@ -126,12 +126,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem_exec.cpp index 70c1673a1cd4..8359671b68f5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/smem_exec.cpp @@ -11,7 +11,6 @@ #include "rocjitsu/isa/arch/amdgpu/shared/simd_glue.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" -#include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" #include "util/data_types.h" #include "util/except.h" @@ -28,6 +27,7 @@ namespace cdna2 { void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -41,6 +41,7 @@ void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -54,6 +55,7 @@ void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -67,6 +69,7 @@ void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -80,6 +83,7 @@ void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -93,6 +97,7 @@ void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -106,6 +111,7 @@ void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -119,6 +125,7 @@ void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -132,6 +139,7 @@ void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -145,6 +153,7 @@ void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -158,6 +167,7 @@ void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -171,6 +181,7 @@ void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -184,6 +195,7 @@ void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -200,10 +212,9 @@ void SStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -214,10 +225,9 @@ void SStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -228,10 +238,9 @@ void SStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -242,10 +251,9 @@ void SScratchStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -256,10 +264,9 @@ void SScratchStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -270,10 +277,9 @@ void SScratchStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -284,10 +290,9 @@ void SBufferStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -298,10 +303,9 @@ void SBufferStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -312,10 +316,9 @@ void SBufferStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1_exec.cpp index 00e750644807..325bd6d8d34a 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna2/sop1_exec.cpp @@ -126,12 +126,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem_exec.cpp index 38c72d4ef6d1..ffdaf12e6a67 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/smem_exec.cpp @@ -12,7 +12,6 @@ #include "rocjitsu/isa/arch/amdgpu/shared/simd_glue.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" -#include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" #include "util/data_types.h" #include "util/except.h" @@ -29,6 +28,7 @@ namespace cdna3 { void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -42,6 +42,7 @@ void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -55,6 +56,7 @@ void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -68,6 +70,7 @@ void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -81,6 +84,7 @@ void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -94,6 +98,7 @@ void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -107,6 +112,7 @@ void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -120,6 +126,7 @@ void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -133,6 +140,7 @@ void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -146,6 +154,7 @@ void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -159,6 +168,7 @@ void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -172,6 +182,7 @@ void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -185,6 +196,7 @@ void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -201,10 +213,9 @@ void SStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -215,10 +226,9 @@ void SStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -229,10 +239,9 @@ void SStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -243,10 +252,9 @@ void SScratchStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -257,10 +265,9 @@ void SScratchStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -271,10 +278,9 @@ void SScratchStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -285,10 +291,9 @@ void SBufferStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -299,10 +304,9 @@ void SBufferStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -313,10 +317,9 @@ void SBufferStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1_exec.cpp index ea5e7b827a8d..83db9393fb96 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna3/sop1_exec.cpp @@ -126,12 +126,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem_exec.cpp index 17ef4ecf3772..a7aaaddc39cf 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/smem_exec.cpp @@ -12,7 +12,6 @@ #include "rocjitsu/isa/arch/amdgpu/shared/simd_glue.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" -#include "rocjitsu/vm/amdgpu/register_access.h" #include "rocjitsu/vm/amdgpu/wavefront.h" #include "util/data_types.h" #include "util/except.h" @@ -29,6 +28,7 @@ namespace cdna4 { void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -42,6 +42,7 @@ void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -55,6 +56,7 @@ void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -68,6 +70,7 @@ void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -81,6 +84,7 @@ void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -94,6 +98,7 @@ void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -107,6 +112,7 @@ void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -120,6 +126,7 @@ void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -133,6 +140,7 @@ void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -146,6 +154,7 @@ void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -159,6 +168,7 @@ void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -172,6 +182,7 @@ void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -185,6 +196,7 @@ void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -201,10 +213,9 @@ void SStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -215,10 +226,9 @@ void SStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -229,10 +239,9 @@ void SStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -243,10 +252,9 @@ void SScratchStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -257,10 +265,9 @@ void SScratchStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -271,10 +278,9 @@ void SScratchStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -285,10 +291,9 @@ void SBufferStoreDwordSmem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 1; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -299,10 +304,9 @@ void SBufferStoreDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 2; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } @@ -313,10 +317,9 @@ void SBufferStoreDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { d->is_load = false; d->wait_counter_type = amdgpu::WaitCounterType::LGKMCNT; d->mtype = amdgpu::mtype_from_flags_gfx9(inst_.glc); - auto &cu = wf.cu(); - uint32_t sdata_base = wf.sgpr_alloc().base + inst_.sdata; + const uint32_t sdata_sel = inst_.sdata; for (uint32_t i = 0; i < 4; ++i) - d->store_data[i] = amdgpu::RegisterAccess(cu).read_sgpr(sdata_base + i); + d->store_data[i] = amdgpu::read_scalar_selector(wf, sdata_sel + i); d->addr = smem_calculate_address(inst_, wf); set_data(std::move(d)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1_exec.cpp index 4720fd01bd31..844ec2f6a4b4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna4/sop1_exec.cpp @@ -126,12 +126,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem_exec.cpp index e988b9b1e80e..3720188bc0ac 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/smem_exec.cpp @@ -26,6 +26,7 @@ namespace cdna5 { void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -39,6 +40,7 @@ void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -52,6 +54,7 @@ void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -65,6 +68,7 @@ void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -78,6 +82,7 @@ void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -91,6 +96,7 @@ void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 3; d->elem_size = 4; d->sign_extend = false; @@ -104,6 +110,7 @@ void SLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = true; @@ -117,6 +124,7 @@ void SLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = false; @@ -130,6 +138,7 @@ void SLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = true; @@ -143,6 +152,7 @@ void SLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadU16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = false; @@ -156,6 +166,7 @@ void SLoadU16Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -169,6 +180,7 @@ void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -182,6 +194,7 @@ void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -195,6 +208,7 @@ void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -208,6 +222,7 @@ void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -221,6 +236,7 @@ void SBufferLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 3; d->elem_size = 4; d->sign_extend = false; @@ -234,6 +250,7 @@ void SBufferLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = true; @@ -247,6 +264,7 @@ void SBufferLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = false; @@ -260,6 +278,7 @@ void SBufferLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = true; @@ -273,6 +292,7 @@ void SBufferLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadU16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = false; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp index 67d7c4f7c52b..611ab4bb453e 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/sop1_exec.cpp @@ -300,16 +300,61 @@ void SGetPcI64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetPcI64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwapPcI64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } -void SRfeI64Sop1::execute_impl(amdgpu::Wavefront &wf) { (void)wf; } +void SRfeI64Sop1::execute_impl(amdgpu::Wavefront &wf) { + uint64_t saved_pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + wf.pc = (saved_pc & kPcAddressMask) - size_; + + // Returning from the handler puts the interrupted EXEC back. The handler runs + // under its own mask -- it parks a doorbell id in EXEC_LO on the way to + // MSG_INTERRUPT -- and restoring that is part of returning, not part of + // stopping for a debugger: a handler that returns without stopping the wave + // used to leave its mask installed, so the application ran on with every lane + // active. That silently un-diverges a branch (gdb.rocm/lane-info.exp sees + // lanes that converged out of a branch reported active again) and is + // permanent, because nothing later puts the application's mask back. + if (wf.in_trap_handler()) + wf.set_exec(wf.trap_saved_exec()); + wf.set_in_trap_handler(false); + + // The handler sets STATUS.HALT when it wants the wave to stay + // stopped for the debugger; honour that on the way out. + constexpr uint32_t kStatusHalt = 1u << 13; + if ((wf.status_raw() & kStatusHalt) != 0) { + wf.set_debug_single_step(false); + wf.set_debug_halted(true); + } else { + // Nothing is halting the wave any more, so an s_sendmsghalt marker + // left over from an earlier stop is stale. Leaving it set would make + // the next resume clear a HALT the handler raises later. + wf.set_self_halted(false); + } +} void SAddPcI64Sop1::execute_impl(amdgpu::Wavefront &wf) { wf.pc += amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp index fdc545fa2f7f..485519148ab2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_alu.cpp @@ -7336,65 +7336,6 @@ DecodeResult decodeVBfmB32Vop3(const MachineInst *opcode, const DecodeErrorEmitt } } // namespace detail -VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) - : Vop3(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) - ? "v_bcnt_u32_b32_e64_dpp" - : "v_bcnt_u32_b32", - reinterpret_cast(inst), - selected_exec_fn(InstructionExecutionId::VBcntU32B32Vop3)), - vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), - src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), - src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { - dst_operands_[0] = &vdst; - src_operands_[0] = &src0; - src_operands_[1] = &src1; - num_src_ = 2; - num_dst_ = 1; - if (reinterpret_cast(inst)->src0 == 255) - src0 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); - if (reinterpret_cast(inst)->src1 == 255) - src1 = Operand( - 32, OperandType::OPR_SIMM32, - static_cast(reinterpret_cast(inst)->simm32)); - if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) { - auto *dp8 = reinterpret_cast(inst); - src0 = Operand(32, OperandType::OPR_VGPR, dp8->vsrc0); - dpp8_lane_sel_ = (dp8->lane_sel_0 << 0) | (dp8->lane_sel_1 << 3) | (dp8->lane_sel_2 << 6) | - (dp8->lane_sel_3 << 9) | (dp8->lane_sel_4 << 12) | (dp8->lane_sel_5 << 15) | - (dp8->lane_sel_6 << 18) | (dp8->lane_sel_7 << 21); - dpp_fi_ = amdgpu::dpp::src_dpp8_fi(reinterpret_cast(inst)->src0); - } - if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) { - auto *dp = reinterpret_cast(inst); - src0 = Operand(32, OperandType::OPR_VGPR, dp->vsrc0); - dpp_ctrl_ = dp->dpp_ctrl; - dpp_row_mask_ = dp->row_mask; - dpp_bank_mask_ = dp->bank_mask; - dpp_bound_ctrl_ = dp->bound_ctrl; - dpp_fi_ = dp->fi; - } - vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); - src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); - src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); -} - -namespace detail { -DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, - const DecodeErrorEmitter &emit_error) { - const auto *inst = opcode; - Result validation = Vop3::validate_encoding( - amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) - ? "v_bcnt_u32_b32_e64_dpp" - : "v_bcnt_u32_b32", - reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); - if (validation.failed()) [[unlikely]] - return Result::failure(); - return std::make_unique(opcode); -} -} // namespace detail - VMbcntLoU32B32Vop3::VMbcntLoU32B32Vop3(const MachineInst *inst) : Vop3(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_mbcnt_lo_u32_b32_e64_dpp" diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_alu.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_alu.cpp index ffe15d7368a7..4595fc6d2448 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_alu.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_alu.cpp @@ -2726,17 +2726,6 @@ void VBfmB32Vop3::execute_impl(amdgpu::Wavefront &wf) { amdgpu::execute_v_bfm_b32_vop3(*this, wf); } -void VBcntU32B32Vop3::execute_impl(amdgpu::Wavefront &wf) { - if (inst_.src0 == amdgpu::SRC_DPP) - amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, - dpp_bound_ctrl_, dpp_fi_, dpp_src0_, wf); - if (amdgpu::dpp::is_src_dpp8(inst_.src0)) - amdgpu::dpp::apply_dpp8(src_operands_[0], dpp8_lane_sel_, dpp_fi_, dpp_src0_, wf); - ScopedOperandDelegate dpp_src0_binding_(src0, dpp_src0_.get()); - ScopedOperandDelegate dpp_src1_binding_(src1, dpp_src1_.get()); - amdgpu::execute_v_bcnt_u32_b32_vop3(*this, wf); -} - void VMbcntLoU32B32Vop3::execute_impl(amdgpu::Wavefront &wf) { if (inst_.src0 == amdgpu::SRC_DPP) amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_misc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_misc.cpp index 077c4affa676..b327de70bb55 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_misc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_exec_misc.cpp @@ -83,6 +83,17 @@ void VMqsadU32U8Vop3::execute_impl(amdgpu::Wavefront &wf) { throw util::UnimplementedInst(mnemonic()); } +void VBcntU32B32Vop3::execute_impl(amdgpu::Wavefront &wf) { + if (inst_.src0 == amdgpu::SRC_DPP) + amdgpu::dpp::apply_dpp(src_operands_[0], dpp_ctrl_, dpp_row_mask_, dpp_bank_mask_, + dpp_bound_ctrl_, dpp_fi_, dpp_src0_, wf); + if (amdgpu::dpp::is_src_dpp8(inst_.src0)) + amdgpu::dpp::apply_dpp8(src_operands_[0], dpp8_lane_sel_, dpp_fi_, dpp_src0_, wf); + ScopedOperandDelegate dpp_src0_binding_(src0, dpp_src0_.get()); + ScopedOperandDelegate dpp_src1_binding_(src1, dpp_src1_.get()); + amdgpu::execute_v_bcnt_u32_b32_vop3(*this, wf); +} + void VTrigPreopF64Vop3::execute_impl(amdgpu::Wavefront &wf) { (void)wf; throw util::UnimplementedInst(mnemonic()); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp index b3537a235be2..c2b6b9bf3ed2 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/cdna5/vop3_misc.cpp @@ -630,6 +630,65 @@ DecodeResult decodeVMqsadU32U8Vop3(const MachineInst *opcode, } } // namespace detail +VBcntU32B32Vop3::VBcntU32B32Vop3(const MachineInst *inst) + : Vop3(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bcnt_u32_b32_e64_dpp" + : "v_bcnt_u32_b32", + reinterpret_cast(inst), + selected_exec_fn(InstructionExecutionId::VBcntU32B32Vop3)), + vdst(32, OperandType::OPR_VGPR, reinterpret_cast(inst)->vdst), + src0(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src0), + src1(32, OperandType::OPR_SRC, reinterpret_cast(inst)->src1) { + dst_operands_[0] = &vdst; + src_operands_[0] = &src0; + src_operands_[1] = &src1; + num_src_ = 2; + num_dst_ = 1; + if (reinterpret_cast(inst)->src0 == 255) + src0 = Operand( + 32, OperandType::OPR_SIMM32, + static_cast(reinterpret_cast(inst)->simm32)); + if (reinterpret_cast(inst)->src1 == 255) + src1 = Operand( + 32, OperandType::OPR_SIMM32, + static_cast(reinterpret_cast(inst)->simm32)); + if (amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0)) { + auto *dp8 = reinterpret_cast(inst); + src0 = Operand(32, OperandType::OPR_VGPR, dp8->vsrc0); + dpp8_lane_sel_ = (dp8->lane_sel_0 << 0) | (dp8->lane_sel_1 << 3) | (dp8->lane_sel_2 << 6) | + (dp8->lane_sel_3 << 9) | (dp8->lane_sel_4 << 12) | (dp8->lane_sel_5 << 15) | + (dp8->lane_sel_6 << 18) | (dp8->lane_sel_7 << 21); + dpp_fi_ = amdgpu::dpp::src_dpp8_fi(reinterpret_cast(inst)->src0); + } + if (reinterpret_cast(inst)->src0 == amdgpu::SRC_DPP) { + auto *dp = reinterpret_cast(inst); + src0 = Operand(32, OperandType::OPR_VGPR, dp->vsrc0); + dpp_ctrl_ = dp->dpp_ctrl; + dpp_row_mask_ = dp->row_mask; + dpp_bank_mask_ = dp->bank_mask; + dpp_bound_ctrl_ = dp->bound_ctrl; + dpp_fi_ = dp->fi; + } + vdst.set_vgpr_msb_role(amdgpu::VgprMsbRole::Dst); + src0.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src0); + src1.set_vgpr_msb_role(amdgpu::VgprMsbRole::Src1); +} + +namespace detail { +DecodeResult decodeVBcntU32B32Vop3(const MachineInst *opcode, + const DecodeErrorEmitter &emit_error) { + const auto *inst = opcode; + Result validation = Vop3::validate_encoding( + amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) + ? "v_bcnt_u32_b32_e64_dpp" + : "v_bcnt_u32_b32", + reinterpret_cast(opcode), emit_error, LiteralSupport::Literal32, 2); + if (validation.failed()) [[unlikely]] + return Result::failure(); + return std::make_unique(opcode); +} +} // namespace detail + VTrigPreopF64Vop3::VTrigPreopF64Vop3(const MachineInst *inst) : Vop3(amdgpu::dpp::is_src_dpp8(reinterpret_cast(inst)->src0) ? "v_trig_preop_f64_e64_dpp" diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem_exec.cpp index cc01629ac8d2..fce8d822944d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/smem_exec.cpp @@ -27,6 +27,7 @@ namespace rdna1 { void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -40,6 +41,7 @@ void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -53,6 +55,7 @@ void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -66,6 +69,7 @@ void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -79,6 +83,7 @@ void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -92,6 +97,7 @@ void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -105,6 +111,7 @@ void SScratchLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -118,6 +125,7 @@ void SScratchLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -131,6 +139,7 @@ void SScratchLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -144,6 +153,7 @@ void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -157,6 +167,7 @@ void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -170,6 +181,7 @@ void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -183,6 +195,7 @@ void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1_exec.cpp index 3ab2c48bf52d..4c4646161568 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna1/sop1_exec.cpp @@ -126,12 +126,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem_exec.cpp index 393193b1eddb..eacda86d4fd6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/smem_exec.cpp @@ -27,6 +27,7 @@ namespace rdna2 { void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -40,6 +41,7 @@ void SLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -53,6 +55,7 @@ void SLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -66,6 +69,7 @@ void SLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -79,6 +83,7 @@ void SLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -92,6 +97,7 @@ void SLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -105,6 +111,7 @@ void SBufferLoadDwordSmem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -118,6 +125,7 @@ void SBufferLoadDwordx2Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -131,6 +139,7 @@ void SBufferLoadDwordx4Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -144,6 +153,7 @@ void SBufferLoadDwordx8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadDwordx16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1_exec.cpp index 3e90c6f80829..991000b1bc06 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna2/sop1_exec.cpp @@ -126,12 +126,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem_exec.cpp index 58229261ffe7..e24bbbdc664b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/smem_exec.cpp @@ -27,6 +27,7 @@ namespace rdna3 { void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -40,6 +41,7 @@ void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -53,6 +55,7 @@ void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -66,6 +69,7 @@ void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -79,6 +83,7 @@ void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -92,6 +97,7 @@ void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -105,6 +111,7 @@ void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -118,6 +125,7 @@ void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -131,6 +139,7 @@ void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -144,6 +153,7 @@ void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1_exec.cpp index 85cdd56779c1..f3540d6beac1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3/sop1_exec.cpp @@ -294,12 +294,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem_exec.cpp index 7c40e01cced4..cc7abb4a34ae 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/smem_exec.cpp @@ -27,6 +27,7 @@ namespace rdna3_5 { void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -40,6 +41,7 @@ void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -53,6 +55,7 @@ void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -66,6 +69,7 @@ void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -79,6 +83,7 @@ void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -92,6 +97,7 @@ void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -105,6 +111,7 @@ void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -118,6 +125,7 @@ void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -131,6 +139,7 @@ void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -144,6 +153,7 @@ void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1_exec.cpp index a9e4debaf58b..2e781448e232 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna3_5/sop1_exec.cpp @@ -294,12 +294,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem_exec.cpp index 2661acb85032..25f3e666c04d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/smem_exec.cpp @@ -26,6 +26,7 @@ namespace rdna4 { void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -39,6 +40,7 @@ void SLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -52,6 +54,7 @@ void SLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -65,6 +68,7 @@ void SLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -78,6 +82,7 @@ void SLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -91,6 +96,7 @@ void SLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 3; d->elem_size = 4; d->sign_extend = false; @@ -104,6 +110,7 @@ void SLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = true; @@ -117,6 +124,7 @@ void SLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = false; @@ -130,6 +138,7 @@ void SLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = true; @@ -143,6 +152,7 @@ void SLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { void SLoadU16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = false; @@ -156,6 +166,7 @@ void SLoadU16Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 4; d->sign_extend = false; @@ -169,6 +180,7 @@ void SBufferLoadB32Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 2; d->elem_size = 4; d->sign_extend = false; @@ -182,6 +194,7 @@ void SBufferLoadB64Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 4; d->elem_size = 4; d->sign_extend = false; @@ -195,6 +208,7 @@ void SBufferLoadB128Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 8; d->elem_size = 4; d->sign_extend = false; @@ -208,6 +222,7 @@ void SBufferLoadB256Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 16; d->elem_size = 4; d->sign_extend = false; @@ -221,6 +236,7 @@ void SBufferLoadB512Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 3; d->elem_size = 4; d->sign_extend = false; @@ -234,6 +250,7 @@ void SBufferLoadB96Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = true; @@ -247,6 +264,7 @@ void SBufferLoadI8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 1; d->sign_extend = false; @@ -260,6 +278,7 @@ void SBufferLoadU8Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = true; @@ -273,6 +292,7 @@ void SBufferLoadI16Smem::execute_impl(amdgpu::Wavefront &wf) { void SBufferLoadU16Smem::execute_impl(amdgpu::Wavefront &wf) { auto d = std::make_unique(); d->dst_reg_base = wf.sgpr_alloc().base + inst_.sdata; + d->dst_selector = inst_.sdata; d->num_dwords = 1; d->elem_size = 2; d->sign_extend = false; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp index 680c76f2bb6b..af4ec1293b80 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/rdna4/sop1_exec.cpp @@ -294,12 +294,28 @@ void SGetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { } void SSetpcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = wf.code_load_bias() + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; } void SSwappcB64Sop1::execute_impl(amdgpu::Wavefront &wf) { + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + constexpr uint64_t kPcSignBit = 1ULL << 47; uint64_t next_pc = wf.pc + size_; - wf.pc = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0) - size_; + const uint64_t encoded = amdgpu::RegisterAccess(wf).read_scalar64(ssrc0); + uint64_t target = encoded & kPcAddressMask; + if ((encoded >> 32 == 0x1FFFFu || encoded >> 32 == 0xFFFFFFFFu) && wf.code_load_bias() != 0) + target = next_pc - 20 + static_cast(encoded); + else if (target & kPcSignBit) + target |= ~kPcAddressMask; + wf.pc = target - size_; amdgpu::RegisterAccess(wf).write_scalar64(sdst, next_pc); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h index 0514779bc56a..ae1882c3611c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/generated/shared/execute_shared.h @@ -8,6 +8,7 @@ #define ROCJITSU_ISA_AMDGPU_SHARED_EXECUTE_SHARED_H_ #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h" #include "rocjitsu/isa/arch/amdgpu/shared/pseudo_scalar.h" #include "rocjitsu/isa/arch/amdgpu/shared/simd_glue.h" #include "rocjitsu/isa/arch/amdgpu/shared/transcendental.h" @@ -1905,18 +1906,18 @@ inline void execute_s_memrealtime_smem([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { static thread_local uint64_t counter = 0; counter += 100; - uint32_t dst = wf.sgpr_alloc().base + inst.inst_.sdata; - amdgpu::RegisterAccess(wf).write_sgpr(dst, static_cast(counter)); - amdgpu::RegisterAccess(wf).write_sgpr(dst + 1, static_cast(counter >> 32)); + const uint32_t dst_sel = inst.inst_.sdata; + amdgpu::write_scalar_selector(wf, dst_sel, static_cast(counter)); + amdgpu::write_scalar_selector(wf, dst_sel + 1, static_cast(counter >> 32)); } template inline void execute_s_memtime_smem([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { static thread_local uint64_t counter = 0; counter += 100; - uint32_t dst = wf.sgpr_alloc().base + inst.inst_.sdata; - amdgpu::RegisterAccess(wf).write_sgpr(dst, static_cast(counter)); - amdgpu::RegisterAccess(wf).write_sgpr(dst + 1, static_cast(counter >> 32)); + const uint32_t dst_sel = inst.inst_.sdata; + amdgpu::write_scalar_selector(wf, dst_sel, static_cast(counter)); + amdgpu::write_scalar_selector(wf, dst_sel + 1, static_cast(counter >> 32)); } template @@ -2373,7 +2374,36 @@ inline void execute_s_quadmask_b64_sop1([[maybe_unused]] Inst &inst, } template -inline void execute_s_rfe_b64_sop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) {} +inline void execute_s_rfe_b64_sop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { + uint64_t saved_pc = amdgpu::RegisterAccess(wf).read_scalar64(inst.ssrc0); + constexpr uint64_t kPcAddressMask = 0x0000FFFFFFFFFFFFULL; + wf.pc = (saved_pc & kPcAddressMask) - inst.size(); + + // Returning from the handler puts the interrupted EXEC back. The handler runs + // under its own mask -- it parks a doorbell id in EXEC_LO on the way to + // MSG_INTERRUPT -- and restoring that is part of returning, not part of + // stopping for a debugger: a handler that returns without stopping the wave + // used to leave its mask installed, so the application ran on with every lane + // active. That silently un-diverges a branch (gdb.rocm/lane-info.exp sees + // lanes that converged out of a branch reported active again) and is + // permanent, because nothing later puts the application's mask back. + if (wf.in_trap_handler()) + wf.set_exec(wf.trap_saved_exec()); + wf.set_in_trap_handler(false); + + // The handler sets STATUS.HALT when it wants the wave to stay + // stopped for the debugger; honour that on the way out. + constexpr uint32_t kStatusHalt = 1u << 13; + if ((wf.status_raw() & kStatusHalt) != 0) { + wf.set_debug_single_step(false); + wf.set_debug_halted(true); + } else { + // Nothing is halting the wave any more, so an s_sendmsghalt marker + // left over from an earlier stop is stale. Leaving it set would make + // the next resume clear a HALT the handler raises later. + wf.set_self_halted(false); + } +} template inline void execute_s_rndne_f16_sop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { @@ -2395,7 +2425,12 @@ inline void execute_s_round_mode_sopp([[maybe_unused]] Inst &inst, [[maybe_unuse } template -inline void execute_s_sendmsg_sopp([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) {} +inline void execute_s_sendmsg_sopp([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { + const uint32_t message = static_cast(inst.simm16.encoding_value_); + if (wf.in_trap_handler() && (message & 0xFu) == 1u) + wf.set_trap_interrupt_sent(true); + wf.cu().handle_sendmsg(wf, message); +} template inline void execute_s_sendmsg_rtn_b32_sop1([[maybe_unused]] Inst &inst, @@ -2459,7 +2494,24 @@ inline void execute_s_sendmsg_rtn_b64_sop1([[maybe_unused]] Inst &inst, template inline void execute_s_sendmsghalt_sopp([[maybe_unused]] Inst &inst, - [[maybe_unused]] Wavefront &wf) {} + [[maybe_unused]] Wavefront &wf) { + const uint32_t message = static_cast(inst.simm16.encoding_value_); + if (wf.in_trap_handler() && (message & 0xFu) == 1u) + wf.set_trap_interrupt_sent(true); + wf.cu().handle_sendmsg(wf, message); + + // S_SENDMSGHALT halts the wave. Keep the architectural bit and the + // scheduler flag in step -- s_rfe consults STATUS.HALT on the way out. + constexpr uint32_t kStatusHalt = 1u << 13; + wf.set_status_raw(wf.status_raw() | kStatusHalt); + wf.set_debug_halted(true); + // Remember who raised the bit. The trap handler also raises HALT, via + // s_setreg just before it returns, and there it means "keep the wave + // stopped" -- the opposite of what it means here, where the wave has + // already reported and is waiting to be resumed. The CWSR record cannot + // distinguish the two, so the resume path reads this instead. + wf.set_self_halted(true); +} template inline void execute_s_set_gpr_idx_idx_sop1([[maybe_unused]] Inst &inst, @@ -2524,11 +2576,17 @@ inline void execute_s_sext_i32_i8_sop1([[maybe_unused]] Inst &inst, template inline void execute_s_sleep_sopp([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { + constexpr uint32_t kSleepClocksPerUnit = 64; + wf.set_sleep_cycles(kSleepClocksPerUnit * + (static_cast(inst.simm16.encoding_value_) & 0x7Fu)); wf.cu().request_functional_yield(); } template inline void execute_s_sleep_var_sop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { + constexpr uint32_t kSleepClocksPerUnit = 64; + wf.set_sleep_cycles(kSleepClocksPerUnit * + (amdgpu::RegisterAccess(wf).read_scalar(inst.ssrc0) & 0x7Fu)); wf.cu().request_functional_yield(); } @@ -3487,15 +3545,16 @@ inline void execute_v_ashrrev_i64_vop3([[maybe_unused]] Inst &inst, template inline void execute_v_bcnt_u32_b32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP1_UNARY(uint32_t, uint32_t, - [](auto a) { return util::popcount_u32_simd(a); }); + ROCJITSU_TRY_SIMD_VOP3_BINARY_INT(uint32_t, + [](auto a, auto b) { return util::popcount_u32_simd(a) + b; }); uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; + uint32_t bits = amdgpu::RegisterAccess(wf).read_lane(inst.src0, lane); + uint32_t accum = amdgpu::RegisterAccess(wf).read_lane(inst.src1, lane); sdwa::write_lane(inst, wf, inst.vdst, lane, - static_cast(std::popcount( - amdgpu::RegisterAccess(wf).read_lane(inst.src0, lane)))); + static_cast(std::popcount(bits)) + accum); } } @@ -9838,8 +9897,11 @@ inline void execute_v_div_fixup_f16_vop3([[maybe_unused]] Inst &inst, template inline void execute_v_div_fixup_f32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP3_TERNARY_FP32( - [](auto p, auto b, auto c) { return ::rocjitsu::amdgpu::div_fixup_f32_simd(p, b, c); }); + uint32_t alu_causes = classify_div_fixup_f32_exceptions(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP3_TERNARY_FP32( + [](auto p, auto b, auto c) { return ::rocjitsu::amdgpu::div_fixup_f32_simd(p, b, c); }); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -9894,6 +9956,7 @@ inline void execute_v_div_fixup_f32_vop3([[maybe_unused]] Inst &inst, result = std::clamp(result, 0.0f, 1.0f); sdwa::write_lane(inst, wf, inst.vdst, lane, std::bit_cast(result)); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template @@ -16005,7 +16068,10 @@ inline void execute_v_mul_f16_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] template inline void execute_v_mul_f32_vop2([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP2_BINARY(float32_t, std::multiplies<>{}); + uint32_t alu_causes = classify_mul_f32_vop2(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP2_BINARY(float32_t, std::multiplies<>{}); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -16016,11 +16082,15 @@ inline void execute_v_mul_f32_vop2([[maybe_unused]] Inst &inst, [[maybe_unused]] (std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.src0, lane)) * std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.vsrc1, lane))))); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template inline void execute_v_mul_f32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP3_BINARY_FP(float32_t, std::multiplies<>{}); + uint32_t alu_causes = classify_mul_f32_vop3(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP3_BINARY_FP(float32_t, std::multiplies<>{}); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -16059,6 +16129,7 @@ inline void execute_v_mul_f32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] return v; }())); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template @@ -17542,7 +17613,11 @@ inline void execute_v_rcp_f64_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] template inline void execute_v_rcp_iflag_f32_vop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP1_UNARY(float32_t, float32_t, [](auto a) { return util::rcp_f32_simd(a); }); + uint32_t alu_causes = classify_rcp_iflag_f32_exceptions(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP1_UNARY(float32_t, float32_t, + [](auto a) { return util::rcp_f32_simd(a); }); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -17552,13 +17627,17 @@ inline void execute_v_rcp_iflag_f32_vop1([[maybe_unused]] Inst &inst, std::bit_cast(amdgpu::transcendental::rcp_f32( std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.src0, lane))))); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template inline void execute_v_rcp_iflag_f32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP3_UNARY_FP(float32_t, float32_t, - [](auto a) { return util::rcp_f32_simd(a); }); + uint32_t alu_causes = classify_rcp_iflag_f32_exceptions(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP3_UNARY_FP(float32_t, float32_t, + [](auto a) { return util::rcp_f32_simd(a); }); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -17587,6 +17666,7 @@ inline void execute_v_rcp_iflag_f32_vop3([[maybe_unused]] Inst &inst, return v; }())); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template @@ -18204,7 +18284,11 @@ inline void execute_v_sqrt_f16_vop3([[maybe_unused]] Inst &inst, [[maybe_unused] template inline void execute_v_sqrt_f32_vop1([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP1_UNARY(float32_t, float32_t, [](auto a) { return util::sqrt_f32_simd(a); }); + uint32_t alu_causes = classify_sqrt_f32_vop1(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP1_UNARY(float32_t, float32_t, + [](auto a) { return util::sqrt_f32_simd(a); }); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -18214,12 +18298,16 @@ inline void execute_v_sqrt_f32_vop1([[maybe_unused]] Inst &inst, [[maybe_unused] std::bit_cast(amdgpu::transcendental::sqrt_f32( std::bit_cast(amdgpu::RegisterAccess(wf).read_lane(inst.src0, lane))))); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template inline void execute_v_sqrt_f32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused]] Wavefront &wf) { - ROCJITSU_TRY_SIMD_VOP3_UNARY_FP(float32_t, float32_t, - [](auto a) { return util::sqrt_f32_simd(a); }); + uint32_t alu_causes = classify_sqrt_f32_vop3(inst, wf); + if (!(wf.mode_raw() & kAluExceptionModeMask)) { + ROCJITSU_TRY_SIMD_VOP3_UNARY_FP(float32_t, float32_t, + [](auto a) { return util::sqrt_f32_simd(a); }); + } uint64_t exec = dpp::execution_lane_mask(inst, wf); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) @@ -18248,6 +18336,7 @@ inline void execute_v_sqrt_f32_vop3([[maybe_unused]] Inst &inst, [[maybe_unused] return v; }())); } + wf.set_trapsts(wf.trapsts() | alu_causes); } template diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/addr_calc.cpp index 33441dc9f2e6..da0810ff2962 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna1/addr_calc.cpp @@ -5,6 +5,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/operand_types.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -23,16 +24,14 @@ uint32_t read_smem_offset(uint32_t soffset, amdgpu::Wavefront &wf) { return 0; if (soffset == OPR_SMEM_OFFSET_M0) return wf.m0(); - return amdgpu::RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + soffset); + return amdgpu::read_scalar_selector(wf, soffset); } } // namespace uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf) { - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t off = static_cast(static_cast(inst.offset << 11) >> 11); off += read_smem_offset(inst.soffset, wf); return (base + off) & ~0x3ULL; @@ -47,9 +46,8 @@ void flat_calculate_addresses(const FlatMachineInst &inst, amdgpu::Wavefront &wf int64_t offset = static_cast(static_cast(inst.offset << 20) >> 20); uint64_t saddr_val = 0; if (inst.saddr != 0x7F) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t vbase = wf.vgpr_alloc().base + inst.addr; amdgpu::RegisterAccess regs(cu); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/addr_calc.cpp index 53e4fa06a2d4..d45df9d385f0 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna2/addr_calc.cpp @@ -5,6 +5,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna2/operand_types.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -23,16 +24,14 @@ uint32_t read_smem_offset(uint32_t soffset, amdgpu::Wavefront &wf) { return 0; if (soffset == OPR_SMEM_OFFSET_M0) return wf.m0(); - return amdgpu::RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + soffset); + return amdgpu::read_scalar_selector(wf, soffset); } } // namespace uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf) { - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t off = static_cast(static_cast(inst.offset << 11) >> 11); off += read_smem_offset(inst.soffset, wf); return (base + off) & ~0x3ULL; @@ -47,9 +46,8 @@ void flat_calculate_addresses(const FlatMachineInst &inst, amdgpu::Wavefront &wf int64_t offset = static_cast(static_cast(inst.offset << 20) >> 20); uint64_t saddr_val = 0; if (inst.saddr != 0x7F) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t vbase = wf.vgpr_alloc().base + inst.addr; amdgpu::RegisterAccess regs(cu); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/addr_calc.cpp index ba36699b9ee9..c68a44151cb1 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3/addr_calc.cpp @@ -5,6 +5,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3/operand_types.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -35,16 +36,14 @@ uint32_t read_smem_offset(uint32_t soffset, amdgpu::Wavefront &wf) { return 0; if (soffset == OPR_SMEM_OFFSET_M0) return wf.m0(); - return amdgpu::RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + soffset); + return amdgpu::read_scalar_selector(wf, soffset); } } // namespace uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf) { - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t off = static_cast(static_cast(inst.offset << 11) >> 11); off += read_smem_offset(inst.soffset, wf); return (base + off) & ~0x3ULL; @@ -62,8 +61,8 @@ void flat_calculate_addresses(const FlatMachineInst &inst, amdgpu::Wavefront &wf if (inst.seg == 1) { uint32_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector(wf, sb_sel); } uint64_t scratch_base = wf.scratch_base(); uint32_t lane_stride = wf.scratch_lane_size(); @@ -88,9 +87,8 @@ void flat_calculate_addresses(const FlatMachineInst &inst, amdgpu::Wavefront &wf uint64_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t priv_hi = static_cast(wf.private_aperture_base() >> 32); uint64_t scratch_base = wf.scratch_base(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/addr_calc.cpp index 780f896d3d54..df93c5e4dfad 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna3_5/addr_calc.cpp @@ -5,6 +5,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna3_5/operand_types.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -35,16 +36,14 @@ uint32_t read_smem_offset(uint32_t soffset, amdgpu::Wavefront &wf) { return 0; if (soffset == OPR_SMEM_OFFSET_M0) return wf.m0(); - return amdgpu::RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + soffset); + return amdgpu::read_scalar_selector(wf, soffset); } } // namespace uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf) { - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t off = static_cast(static_cast(inst.offset << 11) >> 11); off += read_smem_offset(inst.soffset, wf); return (base + off) & ~0x3ULL; @@ -62,8 +61,8 @@ void flat_calculate_addresses(const FlatMachineInst &inst, amdgpu::Wavefront &wf if (inst.seg == 1) { uint32_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector(wf, sb_sel); } uint64_t scratch_base = wf.scratch_base(); uint32_t lane_stride = wf.scratch_lane_size(); @@ -88,9 +87,8 @@ void flat_calculate_addresses(const FlatMachineInst &inst, amdgpu::Wavefront &wf uint64_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t priv_hi = static_cast(wf.private_aperture_base() >> 32); uint64_t scratch_base = wf.scratch_base(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/addr_calc.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/addr_calc.cpp index c62f152aeb61..db9e4d35455c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/addr_calc.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/rdna4/addr_calc.cpp @@ -5,6 +5,7 @@ #include "rocjitsu/isa/arch/amdgpu/generated/rdna4/operand_types.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -30,7 +31,7 @@ uint32_t read_optional_sreg_m0(uint32_t reg, amdgpu::Wavefront &wf) { return 0; if (reg == OPR_SREG_M0_M0) return wf.m0(); - return amdgpu::RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + reg); + return amdgpu::read_scalar_selector(wf, reg); } uint32_t read_smem_offset(uint32_t soffset, amdgpu::Wavefront &wf) { @@ -38,7 +39,7 @@ uint32_t read_smem_offset(uint32_t soffset, amdgpu::Wavefront &wf) { return 0; if (soffset == OPR_SMEM_OFFSET_M0) return wf.m0(); - return amdgpu::RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + soffset); + return amdgpu::read_scalar_selector(wf, soffset); } void init_vector_mem_state(amdgpu::Wavefront &wf, amdgpu::VectorMemState &d) { @@ -56,10 +57,8 @@ void init_vector_mem_state(amdgpu::Wavefront &wf, amdgpu::VectorMemState &d) { uint64_t smem_calculate_address(const SmemMachineInst &inst, amdgpu::Wavefront &wf) { // GFX12 SMEM: sbase is an aligned SGPR pair, ioffset is a 24-bit signed immediate, // soffset is an SGPR/M0/null selector from rdna4/operand_types.h. - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); int64_t off = static_cast(static_cast(inst.ioffset << 8) >> 8); off += read_smem_offset(inst.soffset, wf); return (base + off) & ~0x3ULL; @@ -74,9 +73,8 @@ void flat_calculate_addresses(const VflatMachineInst &inst, amdgpu::Wavefront &w int64_t offset = static_cast(static_cast(inst.ioffset << 8) >> 8); uint64_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t priv_hi = static_cast(wf.private_aperture_base() >> 32); uint64_t scratch_base = wf.scratch_base(); @@ -109,9 +107,8 @@ void flat_calculate_addresses(const VglobalMachineInst &inst, amdgpu::Wavefront int64_t offset = static_cast(static_cast(inst.ioffset << 8) >> 8); uint64_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t vbase = wf.vgpr_alloc().base + inst.vaddr; amdgpu::RegisterAccess regs(cu); @@ -141,8 +138,8 @@ void flat_calculate_addresses(const VscratchMachineInst &inst, amdgpu::Wavefront uint32_t lane_stride = wf.scratch_lane_size(); uint32_t saddr_val = 0; if (has_saddr(inst.saddr)) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector(wf, sb_sel); } uint32_t vbase = wf.vgpr_alloc().base + inst.vaddr; amdgpu::RegisterAccess regs(cu); @@ -166,10 +163,10 @@ void mubuf_calculate_addresses(const VbufferMachineInst &inst, amdgpu::Wavefront uint64_t exec = wf.exec(); d.lane_mask = exec; d.exec_mask = exec; - uint32_t sb = wf.sgpr_alloc().base + inst.rsrc; + const uint32_t sb_sel = inst.rsrc; uint64_t base_addr = - (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1) & 0xFFFF) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + (static_cast(amdgpu::read_scalar_selector(wf, sb_sel + 1) & 0xFFFF) << 32) | + amdgpu::read_scalar_selector(wf, sb_sel); uint32_t soffset_val = read_optional_sreg_m0(inst.soffset, wf); int64_t ioff = static_cast(static_cast(inst.ioffset << 8) >> 8); assert(!inst.idxen && "Vbuffer idxen not yet supported"); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h index a2b8d89d0a16..77a0b0d95a14 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_buffer.h @@ -11,6 +11,7 @@ /// type so they work with any ISA family whose encoding struct exposes the /// required field names. +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -54,17 +55,15 @@ void mubuf_calculate_addresses(const MubufInst &inst, amdgpu::Wavefront &wf, Vec d.wg_id = wf.wg_id(); d.wf_id = wf.wf_id(); d.cu_path = wf.cu().full_path(); - uint32_t sb = wf.sgpr_alloc().base + inst.srsrc * 4; - uint32_t srd0 = amdgpu::RegisterAccess(cu).read_sgpr(sb); - uint32_t srd1 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 1); - uint32_t srd2 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 2); - uint32_t srd3 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 3); + const uint32_t sb_sel = inst.srsrc * 4; + uint32_t srd0 = amdgpu::read_scalar_selector(wf, sb_sel); + uint32_t srd1 = amdgpu::read_scalar_selector(wf, sb_sel + 1); + uint32_t srd2 = amdgpu::read_scalar_selector(wf, sb_sel + 2); + uint32_t srd3 = amdgpu::read_scalar_selector(wf, sb_sel + 3); uint64_t base_addr = (static_cast(srd1 & 0xFFFF) << 32) | srd0; // soffset field: 0-105 = SGPR index, 128 (0x80) = inline constant 0. uint32_t soffset_val = - (inst.soffset == 0x80) - ? 0u - : amdgpu::RegisterAccess(cu).read_sgpr(wf.sgpr_alloc().base + inst.soffset); + (inst.soffset == 0x80) ? 0u : amdgpu::read_scalar_selector(wf, inst.soffset); // GFX9 buffer bounds checking: OOB loads return 0, OOB stores are dropped. // Per ISA spec (structured mode, stride=0): num_records is the buffer size // in bytes. The OOB check uses voffset + inst_offset only — soffset is NOT @@ -166,16 +165,14 @@ void mtbuf_calculate_addresses(const MtbufInst &inst, amdgpu::Wavefront &wf, Vec d.wg_id = wf.wg_id(); d.wf_id = wf.wf_id(); d.cu_path = wf.cu().full_path(); - uint32_t sb = wf.sgpr_alloc().base + inst.srsrc * 4; - uint32_t srd0 = amdgpu::RegisterAccess(cu).read_sgpr(sb); - uint32_t srd1 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 1); - uint32_t srd2 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 2); - uint32_t srd3 = amdgpu::RegisterAccess(cu).read_sgpr(sb + 3); + const uint32_t sb_sel = inst.srsrc * 4; + uint32_t srd0 = amdgpu::read_scalar_selector(wf, sb_sel); + uint32_t srd1 = amdgpu::read_scalar_selector(wf, sb_sel + 1); + uint32_t srd2 = amdgpu::read_scalar_selector(wf, sb_sel + 2); + uint32_t srd3 = amdgpu::read_scalar_selector(wf, sb_sel + 3); uint64_t base_addr = (static_cast(srd1 & 0xFFFF) << 32) | srd0; uint32_t soffset_val = - (inst.soffset == 0x80) - ? 0u - : amdgpu::RegisterAccess(cu).read_sgpr(wf.sgpr_alloc().base + inst.soffset); + (inst.soffset == 0x80) ? 0u : amdgpu::read_scalar_selector(wf, inst.soffset); uint32_t num_records = srd2; uint32_t stride = (srd1 >> 16) & 0x3FFF; bool oob_raw = (srd3 >> 31) & 1; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_flat.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_flat.h index 5c1e3f4f18f8..09cf8625ea51 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_flat.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_flat.h @@ -12,6 +12,7 @@ /// /// Segment encoding: seg==0 → FLAT, seg==1 → SCRATCH, seg==2 → GLOBAL. +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -58,17 +59,24 @@ void flat_calculate_addresses(const FlatInst &inst, amdgpu::Wavefront &wf, Vecto if (inst.seg == 1) { // SCRATCH: architected flat scratch (GFX940/CDNA4). - // addr = FLAT_SCRATCH + lane * scratch_lane_size + VGPR[lane] + saddr + offset. - // On real hardware FLAT_SCRATCH is a dedicated register, not part of the - // SGPR file. We store it in the wavefront's scratch_base_ member and also - // mirror it to the flat_scratch_init user SGPRs for legacy compatibility. + // The hardware stores scratch in a dword-interleaved ("swizzled") layout: + // a lane's private byte offset `off` maps to + // scratch_base + (off/4)*lane_count*4 + lane*4 + off%4 + // so consecutive dwords of one lane are lane_count*4 bytes apart. We + // reproduce that exact layout (rather than lane-major) so it matches how + // rocm-dbgapi reads private_swizzled memory (rocdbgapi memory.cpp), letting + // ROCgdb resolve scratch-resident variables. The interleave granule is a + // dword (rocdbgapi architecture.cpp: private_lane interleave_size = + // sizeof(uint32_t)). FLAT_SCRATCH is a dedicated register held in the + // wavefront's scratch_base_ member. + constexpr uint32_t kScratchInterleave = sizeof(uint32_t); + const uint32_t lane_count = wf.wf_size(); uint64_t scratch_base = wf.scratch_base(); - uint32_t saddr_val = 0; + int64_t saddr_val = 0; if (inst.saddr != 0x7F) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = static_cast(amdgpu::read_scalar_selector(wf, sb_sel)); } - uint32_t lane_stride = wf.scratch_lane_size(); bool has_vaddr = true; if constexpr (requires { inst.sve; }) has_vaddr = (inst.sve == 1); @@ -78,23 +86,27 @@ void flat_calculate_addresses(const FlatInst &inst, amdgpu::Wavefront &wf, Vecto std::optional vaddr_region; if (has_vaddr) vaddr_region.emplace(regs.read_vgpr_region(vbase, 1, exec)); + d.scratch_swizzle = true; + d.scratch_addr_stride = lane_count * kScratchInterleave; + d.scratch_lane_mask = exec; for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { if (!(exec & (1ULL << lane))) continue; uint32_t vaddr = 0; if (has_vaddr) vaddr = vaddr_region->lane(0, lane); + uint64_t priv_off = static_cast(static_cast(vaddr) + saddr_val + offset); d.per_lane_addr[lane] = - scratch_base + static_cast(lane) * lane_stride + vaddr + saddr_val + offset; + scratch_base + (priv_off / kScratchInterleave) * lane_count * kScratchInterleave + + static_cast(lane) * kScratchInterleave + (priv_off % kScratchInterleave); } } else if (inst.seg == 2) { // GLOBAL: saddr (64-bit SGPR pair) + VGPR (32-bit) + offset, // or VGPR pair (64-bit) + offset when saddr==0x7F. uint64_t saddr_val = 0; if (inst.saddr != 0x7F) { - uint32_t sb = wf.sgpr_alloc().base + inst.saddr; - saddr_val = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sb + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sb); + const uint32_t sb_sel = inst.saddr; + saddr_val = amdgpu::read_scalar_selector64(wf, sb_sel); } uint32_t vbase = wf.vgpr_alloc().base + inst.addr; auto vaddr_region = regs.read_vgpr_region(vbase, inst.saddr != 0x7F ? 1 : 2, exec); @@ -115,10 +127,13 @@ void flat_calculate_addresses(const FlatInst &inst, amdgpu::Wavefront &wf, Vecto // Real hardware checks the address against private/shared apertures and // routes accordingly. We perform the same conversion here so that private // (scratch) accesses reach the mapped scratch buffer instead of the - // unmapped aperture VA range. + // unmapped aperture VA range, using the same dword-interleaved swizzle as + // dedicated SCRATCH ops so the private layout is uniform (and readable by + // rocm-dbgapi). + constexpr uint32_t kScratchInterleave = sizeof(uint32_t); + const uint32_t lane_count = wf.wf_size(); uint32_t priv_hi = static_cast(wf.private_aperture_base() >> 32); uint64_t scratch_base = wf.scratch_base(); - uint32_t lane_stride = wf.scratch_lane_size(); uint32_t vbase = wf.vgpr_alloc().base + inst.addr; auto vaddr_region = regs.read_vgpr_region(vbase, 2, exec); for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { @@ -126,8 +141,14 @@ void flat_calculate_addresses(const FlatInst &inst, amdgpu::Wavefront &wf, Vecto continue; uint64_t vaddr = vaddr_region.lane64(0, lane); uint64_t addr = vaddr + offset; - if (priv_hi != 0 && static_cast(addr >> 32) == priv_hi) - addr = scratch_base + static_cast(lane) * lane_stride + (addr & 0xFFFFFFFFULL); + if (priv_hi != 0 && static_cast(addr >> 32) == priv_hi) { + uint64_t priv_off = addr & 0xFFFFFFFFULL; + addr = scratch_base + (priv_off / kScratchInterleave) * lane_count * kScratchInterleave + + static_cast(lane) * kScratchInterleave + (priv_off % kScratchInterleave); + d.scratch_swizzle = true; + d.scratch_addr_stride = lane_count * kScratchInterleave; + d.scratch_lane_mask |= 1ULL << lane; + } d.per_lane_addr[lane] = addr; } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h index 68b4821e4c38..2c86eb3bd908 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h @@ -12,6 +12,7 @@ /// These functions are templated on the machine instruction type so they work /// with any ISA family whose encoding struct exposes the required field names. +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "rocjitsu/vm/amdgpu/register_access.h" @@ -30,13 +31,11 @@ namespace addr_calc { /// Requires: inst.sbase, inst.soffset_en, inst.soffset, inst.imm, inst.offset. template uint64_t smem_calculate_address(const SmemInst &inst, amdgpu::Wavefront &wf) { - auto &cu = wf.cu(); - uint32_t sbase = wf.sgpr_alloc().base + inst.sbase * 2; - uint64_t base = (static_cast(amdgpu::RegisterAccess(cu).read_sgpr(sbase + 1)) << 32) | - amdgpu::RegisterAccess(cu).read_sgpr(sbase); + const uint32_t sbase_sel = inst.sbase * 2; + uint64_t base = amdgpu::read_scalar_selector64(wf, sbase_sel); uint64_t off = 0; if (inst.soffset_en) - off += amdgpu::RegisterAccess(cu).read_sgpr(wf.sgpr_alloc().base + inst.soffset); + off += amdgpu::read_scalar_selector(wf, inst.soffset); if (inst.imm) off += static_cast(static_cast(inst.offset << 11) >> 11); uint64_t addr = base + off; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h new file mode 100644 index 000000000000..8b58b086a5d4 --- /dev/null +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h @@ -0,0 +1,161 @@ +// Copyright (c) 2025-2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +#ifndef ROCJITSU_ISA_AMDGPU_SHARED_ALU_EXCEPTIONS_H_ +#define ROCJITSU_ISA_AMDGPU_SHARED_ALU_EXCEPTIONS_H_ + +#include "rocjitsu/vm/amdgpu/register_access.h" +#include "rocjitsu/vm/amdgpu/wavefront.h" +#include +#include +#include + +namespace rocjitsu::amdgpu { + +inline constexpr uint32_t kAluExceptionModeShift = 12; +inline constexpr uint32_t kAluExceptionModeMask = 0x7fu << kAluExceptionModeShift; +inline constexpr uint32_t kAluExceptionTrapstsMask = 0x7fu; + +// Every classifier below reports what it found through wf.raise_alu_causes() +// as well as returning it. The generated call sites OR the return value into +// TRAPSTS, which is architecturally sticky and so cannot tell the CU whether +// the current instruction raised a cause or merely inherited a bit some +// earlier instruction latched. Trap delivery needs the former, so a classifier +// that grows a new early return has to report on that path too. + +/// @brief EXCP causes raised by `lhs * rhs`, optionally scaled by an output +/// modifier. +/// @details @p omod_scale must be applied to the exact and the rounded value +/// alike. Deriving INEXACT by comparing the scaled result against the unscaled +/// product instead reports every nonzero product as inexact the moment an +/// output modifier is present, because scaling by 2 changes the value it is +/// being compared against. +inline uint32_t classify_mul_f32(float lhs, float rhs, float omod_scale = 1.0f) { + uint32_t causes = 0; + if (std::fpclassify(lhs) == FP_SUBNORMAL || std::fpclassify(rhs) == FP_SUBNORMAL) + causes |= 1u << 1; + const long double exact = + static_cast(lhs) * static_cast(rhs) * omod_scale; + const float result = (lhs * rhs) * omod_scale; + if (std::isfinite(lhs) && std::isfinite(rhs) && std::isinf(result)) + causes |= 1u << 3; + if (exact != 0.0L && (result == 0.0f || std::fpclassify(result) == FP_SUBNORMAL)) + causes |= 1u << 4; + if (std::isfinite(exact) && static_cast(result) != exact) + causes |= 1u << 5; + return causes; +} + +template uint32_t classify_mul_f32_vop2(const Inst &inst, Wavefront &wf) { + uint32_t causes = 0; + const uint64_t exec = wf.exec(); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { + if (!(exec & (1ULL << lane))) + continue; + const float lhs = std::bit_cast(RegisterAccess(wf).read_lane(inst.src0, lane)); + const float rhs = std::bit_cast(RegisterAccess(wf).read_lane(inst.vsrc1, lane)); + causes |= classify_mul_f32(lhs, rhs); + } + wf.raise_alu_causes(causes); + return causes; +} + +template uint32_t classify_mul_f32_vop3(const Inst &inst, Wavefront &wf) { + uint32_t causes = 0; + const uint64_t exec = wf.exec(); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { + if (!(exec & (1ULL << lane))) + continue; + float lhs = std::bit_cast(RegisterAccess(wf).read_lane(inst.src0, lane)); + float rhs = std::bit_cast(RegisterAccess(wf).read_lane(inst.src1, lane)); + if (inst.inst_.abs & 1u) + lhs = std::fabs(lhs); + if (inst.inst_.neg & 1u) + lhs = -lhs; + if (inst.inst_.abs & 2u) + rhs = std::fabs(rhs); + if (inst.inst_.neg & 2u) + rhs = -rhs; + // OMOD scales the result, so it has to take part in deriving the causes + // rather than being compared against the unscaled product afterwards. + float omod_scale = 1.0f; + if (inst.inst_.omod == 1) + omod_scale = 2.0f; + else if (inst.inst_.omod == 2) + omod_scale = 4.0f; + else if (inst.inst_.omod == 3) + omod_scale = 0.5f; + causes |= classify_mul_f32(lhs, rhs, omod_scale); + } + wf.raise_alu_causes(causes); + return causes; +} + +template uint32_t classify_sqrt_f32_vop1(const Inst &inst, Wavefront &wf) { + const uint64_t exec = wf.exec(); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) + if ((exec & (1ULL << lane)) && + std::bit_cast(RegisterAccess(wf).read_lane(inst.src0, lane)) < 0.0f) { + wf.raise_alu_causes(1u); + return 1u; + } + return 0; +} + +template uint32_t classify_sqrt_f32_vop3(const Inst &inst, Wavefront &wf) { + const uint64_t exec = wf.exec(); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { + if (!(exec & (1ULL << lane))) + continue; + float source = std::bit_cast(RegisterAccess(wf).read_lane(inst.src0, lane)); + if (inst.inst_.abs & 1u) + source = std::fabs(source); + if (inst.inst_.neg & 1u) + source = -source; + if (source < 0.0f) { + wf.raise_alu_causes(1u); + return 1u; + } + } + return 0; +} + +template +uint32_t classify_div_fixup_f32_exceptions(const Inst &inst, Wavefront &wf) { + const uint64_t exec = wf.exec(); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) { + if (!(exec & (1ULL << lane))) + continue; + float denominator = std::bit_cast(RegisterAccess(wf).read_lane(inst.src1, lane)); + float numerator = std::bit_cast(RegisterAccess(wf).read_lane(inst.src2, lane)); + if (inst.inst_.abs & 2u) + denominator = std::fabs(denominator); + if (inst.inst_.neg & 2u) + denominator = -denominator; + if (inst.inst_.abs & 4u) + numerator = std::fabs(numerator); + if (inst.inst_.neg & 4u) + numerator = -numerator; + if (denominator == 0.0f && numerator != 0.0f) { + wf.raise_alu_causes(1u << 2); + return 1u << 2; + } + } + return 0; +} + +template +uint32_t classify_rcp_iflag_f32_exceptions(const Inst &inst, Wavefront &wf) { + const uint64_t exec = wf.exec(); + for (uint32_t lane = 0; lane < wf.wf_size(); ++lane) + if ((exec & (1ULL << lane)) && + std::bit_cast(RegisterAccess(wf).read_lane(inst.src0, lane)) == 0.0f) { + wf.raise_alu_causes(1u << 6); + return 1u << 6; + } + return 0; +} + +} // namespace rocjitsu::amdgpu + +#endif // ROCJITSU_ISA_AMDGPU_SHARED_ALU_EXCEPTIONS_H_ diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h new file mode 100644 index 000000000000..94f3d9986272 --- /dev/null +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h @@ -0,0 +1,62 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file scalar_operand_read.h +/// @brief Read a scalar register by its encoded operand selector. + +#ifndef ROCJITSU_ISA_ARCH_AMDGPU_SHARED_SCALAR_OPERAND_READ_H_ +#define ROCJITSU_ISA_ARCH_AMDGPU_SHARED_SCALAR_OPERAND_READ_H_ + +#include "rocjitsu/vm/amdgpu/register_access.h" +#include "rocjitsu/vm/amdgpu/wavefront.h" + +#include + +namespace rocjitsu { +namespace amdgpu { + +/// @brief First scalar selector that addresses a trap-temporary register. +inline constexpr uint32_t kTtmpSelectorFirst = 108; +/// @brief Last scalar selector that addresses a trap-temporary register. +inline constexpr uint32_t kTtmpSelectorLast = 123; + +/// @brief Read the scalar register named by an encoded operand selector. +/// +/// @details Address-computation helpers take the raw selector out of an +/// instruction field (SBASE, SOFFSET, SADDR, SRSRC) and would otherwise index +/// it straight into the wave's SGPR allocation. Selectors 108..123 do not live +/// there: they name the trap-temporary file, which the decoder routes to +/// Wavefront::ttmp(). A trap handler that loads through a TTMP-held pointer -- +/// which the ROCr handler does -- must read the TTMP, not whatever SGPR happens +/// to sit at that offset in the allocation. +[[nodiscard]] inline uint32_t read_scalar_selector(Wavefront &wf, uint32_t selector) { + if (selector >= kTtmpSelectorFirst && selector <= kTtmpSelectorLast) + return wf.ttmp(selector - kTtmpSelectorFirst); + return RegisterAccess(wf.cu()).read_sgpr(wf.sgpr_alloc().base + selector); +} + +/// @brief Read a 64-bit scalar pair named by an encoded operand selector. +/// @details The two halves are resolved independently so a pair that straddles +/// the TTMP boundary still reads each half from the file that owns it. +[[nodiscard]] inline uint64_t read_scalar_selector64(Wavefront &wf, uint32_t selector) { + return (static_cast(read_scalar_selector(wf, selector + 1)) << 32) | + read_scalar_selector(wf, selector); +} + +/// @brief Write the scalar register named by an encoded operand selector. +/// @details Counterpart to read_scalar_selector(): a destination in 108..123 +/// must land in the trap-temporary file. Writing it through the SGPR +/// allocation would both lose the value (every read comes from the TTMP file) +/// and scribble past the end of this wave's allocation into a neighbour's. +inline void write_scalar_selector(Wavefront &wf, uint32_t selector, uint32_t value) { + if (selector >= kTtmpSelectorFirst && selector <= kTtmpSelectorLast) { + wf.set_ttmp(selector - kTtmpSelectorFirst, value); + return; + } + RegisterAccess(wf.cu()).write_sgpr(wf.sgpr_alloc().base + selector, value); +} + +} // namespace amdgpu +} // namespace rocjitsu + +#endif // ROCJITSU_ISA_ARCH_AMDGPU_SHARED_SCALAR_OPERAND_READ_H_ diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h index 426ec1e6e048..68ac7ca47f5b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/scalar_operand_resolve.h @@ -36,8 +36,13 @@ inline uint32_t resolve_src_scalar(const Wavefront &wf, int ev, int m0_ev) { return static_cast(wf.vcc()); if (ev == 107) return static_cast(wf.vcc() >> 32); + // TTMP0-15 are the trap handler's private scratch registers. They are NOT + // part of the wave's SGPR allocation: hardware banks them separately, the CP + // seeds them with the dispatch/queue identity that rocm-dbgapi reads back out + // of the CWSR area, and a shader that never enters a trap must not be able to + // clobber them through an SGPR write. if (ev >= 108 && ev <= 123) - return RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + static_cast(ev)); + return wf.ttmp(static_cast(ev - 108)); if (m0_ev == 125 && ev == 124) return 0u; // NULL if (ev == m0_ev) @@ -145,10 +150,9 @@ inline uint64_t resolve_src_scalar64(const Wavefront &wf, int ev, int m0_ev) { } if (ev == 106) return wf.vcc(); - if (ev >= 108 && ev <= 122) { - uint32_t lo = RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + static_cast(ev)); - uint32_t hi = - RegisterAccess(wf).read_sgpr(wf.sgpr_alloc().base + static_cast(ev + 1)); + if (ev >= 108 && ev <= 122) { // TTMP pair; see resolve_src_scalar() + uint32_t lo = wf.ttmp(static_cast(ev - 108)); + uint32_t hi = wf.ttmp(static_cast(ev - 107)); return static_cast(hi) << 32 | lo; } if (m0_ev == 125 && ev == 124) @@ -215,8 +219,8 @@ inline void resolve_dst_write(Wavefront &wf, int ev, uint32_t val, int m0_ev) { wf.set_vcc((wf.vcc() & 0x00000000FFFFFFFFULL) | (static_cast(val) << 32)); return; } - if (ev >= 108 && ev <= 123) { - RegisterAccess(wf).write_sgpr(wf.sgpr_alloc().base + static_cast(ev), val); + if (ev >= 108 && ev <= 123) { // see resolve_src_scalar() + wf.set_ttmp(static_cast(ev - 108), val); return; } if (m0_ev == 125 && ev == 124) @@ -252,11 +256,9 @@ inline void resolve_dst_write64(Wavefront &wf, int ev, uint64_t val) { wf.set_vcc(val); return; } - if (ev >= 108 && ev <= 122) { - RegisterAccess(wf).write_sgpr(wf.sgpr_alloc().base + static_cast(ev), - static_cast(val)); - RegisterAccess(wf).write_sgpr(wf.sgpr_alloc().base + static_cast(ev + 1), - static_cast(val >> 32)); + if (ev >= 108 && ev <= 122) { // TTMP pair; see resolve_src_scalar() + wf.set_ttmp(static_cast(ev - 108), static_cast(val)); + wf.set_ttmp(static_cast(ev - 107), static_cast(val >> 32)); return; } if (ev == 124) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/CMakeLists.txt b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/CMakeLists.txt index a906802a9ab5..434d9e48cd3d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/CMakeLists.txt +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/CMakeLists.txt @@ -2,6 +2,7 @@ # SPDX-License-Identifier: MIT rj_add_object_library(rocjitsu_kmd + cwsr.cpp events.cpp guest_kfd.cpp libc_passthrough.cpp diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.cpp new file mode 100644 index 000000000000..6101a644345f --- /dev/null +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.cpp @@ -0,0 +1,490 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file cwsr.cpp +/// @brief CWSR (context-save-restore) area serialization for rocm-dbgapi. + +#include "rocjitsu/kmd/linux/cwsr.h" + +#include +#include +#include + +namespace rocjitsu { +namespace kmd { + +namespace { + +// Layout constants matching gfx9_4/mi cwsr_record_t in rocdbgapi. +constexpr uint32_t kHwregCount = 32; // hwreg_count() +constexpr uint32_t kTtmpCount = 16; // ttmps saved at the top of the hwreg block +constexpr uint32_t kVgprLaneBytes = 64 * sizeof(uint32_t); // one VGPR = 64 lanes * 4 bytes +// The saved block holds kCwsrSavedSgprSlots scalars, so that is the ceiling a +// wave can carry. It is deliberately not the architected count (102): s104 and +// s105 are ordinary registers above the FLAT_SCRATCH alias, and CDNA3/CDNA4 +// default to 112 SGPRs per wave (config_loader default_sgprs_per_wf), so a +// lower bound here would reject an ordinary dispatch and fail the queue's whole +// CWSR publish. Slots that alias travel in their own fields either way. +constexpr uint32_t kMaxSgprs = kCwsrSavedSgprSlots; +constexpr uint32_t kMaxVgprs = 256; +constexpr uint32_t kCwsrHeaderBytes = 10 * sizeof(uint32_t); +constexpr uint32_t kControlStackOffset = 0x100u; + +// COMPUTE_RELAUNCH classification bits (control_stack_iterate): a word with bit +// 30 set is an event (skipped) and a word with bit 31 set is a state word; a +// wave word has both clear. +constexpr uint32_t kRelaunchStateBit = 1u << 31; + +constexpr uint32_t round_up(uint32_t v, uint32_t m) { return (v / m + (v % m != 0)) * m; } + +// Encode the COMPUTE_RELAUNCH "state" word so rocm-dbgapi decodes exactly +// @vgpr_count / @sgpr_count with zero accumulation (ACC) VGPRs: +// vgpr_count = (accum_offset[24:29] + 1) * 4 +// acc_vgpr_count = (vgprs[0:5] + 1) * 8 - vgpr_count (== 0 here) +// sgpr_count = (sgprs[6:8] + 1) * 16 - 16 +// lds_size = lds[9:16] * 1280 bytes on gfx950 +uint32_t encode_state_word(uint32_t vgpr_count, uint32_t sgpr_count, uint32_t lds_size) { + uint32_t vgprs_field = (vgpr_count / 8) - 1; // acc == 0 => vgpr_count = (vgprs+1)*8 + uint32_t accum_offset = (vgpr_count / 4) - 1; // vgpr_count = (accum_offset+1)*4 + uint32_t sgprs_field = sgpr_count / 16; // sgpr_count = sgprs_field*16 + uint32_t w = 0; + w |= (vgprs_field & 0x3Fu); + w |= (sgprs_field & 0x7u) << 6; + w |= ((lds_size / 1280) & 0xFFu) << 9; + w |= (accum_offset & 0x3Fu) << 24; + w |= kRelaunchStateBit; + return w; +} + +// Encode the COMPUTE_RELAUNCH "wave" word (bits 30/31 clear so it is neither an +// event nor a state word). +uint32_t encode_wave_word(bool first_wave, bool last_wave, uint32_t scratch_scoreboard_id) { + uint32_t w = 0; + // scratch_scoreboard_id[0:8] locates the wave's private memory; se_id[9:11]=0, + // scratch_en[15]=0. + w |= (scratch_scoreboard_id & 0x1FFu); + if (last_wave) + w |= 1u << 16; + if (first_wave) + w |= 1u << 17; + return w; +} + +uint32_t encode_ttmp6(const CwsrWaveState &w) { + uint32_t v = 0; + if (w.wave_stopped) + v |= 1u << 30; + if (w.saved_status_halt) + v |= 1u << 29; + v |= (w.trap_id & 0xFu) << 25; + // bit 31 (spi_ttmps_setup_disabled) reflects whether the SPI initialized the + // dispatch bookkeeping TTMPs (group ids in ttmp8-10, packet id in ttmp11). + // When the process runtime-enabled without ttmp-save (kfd_runtime_info + // ttmp_setup == 0), those registers are not meaningful, so mark the wave + // accordingly. rocm-dbgapi (>= r_debug v10) then skips packet/workgroup + // correlation and uses its dummy dispatch instead of validating a packet id + // against the queue's read/write dispatch ids (rocdbgapi architecture.cpp + // spi_ttmps_setup_enabled, queue.cpp get_os_queue_packet_id). + if (!w.spi_ttmps_setup) + v |= 1u << 31; + return v; +} + +uint32_t encode_ttmp11(const CwsrWaveState &w) { + uint32_t v = 0; + v |= (w.wave_in_group & 0x3Fu); + v |= (w.queue_packet_id & 0x1FFFFFFu) << 6; // [6:30] + v |= 1u << 31; // trap_handler_ttmps_setup + return v; +} + +struct CwsrGeometry { + CwsrLayout layout{}; + uint32_t vgpr_count = 0; + uint32_t sgpr_count = kCwsrSavedSgprSlots; + uint32_t vcc_lo_slot = kCwsrVccLoSlot; + uint32_t flat_scratch_lo_slot = kCwsrFlatScratchLoSlot; + uint32_t hwreg_bytes = 0; + uint32_t sgpr_bytes = 0; + uint32_t vgpr_bytes = 0; + uint32_t lds_bytes = 0; + uint64_t per_wave = 0; +}; + +CwsrGeometry compute_geometry(uint32_t area_size, const std::vector &waves) { + CwsrGeometry geometry{}; + if (waves.empty() || waves.size() > std::numeric_limits::max()) + return geometry; + + uint32_t max_vgprs = 0; + uint32_t max_lds = 0; + for (const auto &wave : waves) { + if (wave.num_vgprs > kMaxVgprs || wave.num_sgprs > kMaxSgprs || wave.trap_id > 0xFu || + wave.wave_in_group > 0x3Fu || wave.queue_packet_id > 0x1FFFFFFu) + return geometry; + max_vgprs = std::max(max_vgprs, wave.num_vgprs); + if (wave.lds.size() > std::numeric_limits::max()) + return geometry; + max_lds = std::max(max_lds, static_cast(wave.lds.size())); + } + + geometry.lds_bytes = round_up(max_lds, 1280); + if (geometry.lds_bytes / 1280 > 0xFFu) + return geometry; + + geometry.vgpr_count = std::max(round_up(max_vgprs, 8), 8); + // Alias slots come from cwsr.h so the codec, the wave writeback and the tests + // share one definition. FLAT_SCRATCH being written but read back from a + // separately open-coded offset is exactly how it came to be dropped. + geometry.hwreg_bytes = kHwregCount * sizeof(uint32_t); + geometry.sgpr_bytes = geometry.sgpr_count * sizeof(uint32_t); + geometry.vgpr_bytes = geometry.vgpr_count * kVgprLaneBytes; + geometry.per_wave = 64u + geometry.hwreg_bytes + geometry.sgpr_bytes + geometry.vgpr_bytes; + + const uint64_t num_waves = waves.size(); + const uint64_t num_groups = std::count_if( + waves.begin(), waves.end(), [](const auto &wave) { return wave.is_first_in_group; }); + const uint64_t wave_state_size = geometry.per_wave * num_waves + geometry.lds_bytes * num_groups; + const uint64_t control_stack_size = (3u + num_waves) * sizeof(uint32_t); + const uint64_t wave_area_begin = kControlStackOffset + control_stack_size; + const uint64_t wave_state_offset = wave_area_begin + wave_state_size; + if (control_stack_size > std::numeric_limits::max() || + wave_state_size > std::numeric_limits::max() || + wave_state_offset > std::numeric_limits::max() || wave_state_offset > area_size) + return geometry; + + constexpr uint32_t kDebuggerBytesPerWave = 32; + constexpr uint32_t kDebuggerBytesAlign = 64; + constexpr uint32_t kDebuggerReserveChunks = 8; + const uint64_t debug_size_64 = + ((num_waves + kDebuggerReserveChunks) * kDebuggerBytesPerWave + kDebuggerBytesAlign - 1) / + kDebuggerBytesAlign * kDebuggerBytesAlign; + const uint64_t debug_offset_64 = + (wave_state_offset + kDebuggerBytesAlign - 1) / kDebuggerBytesAlign * kDebuggerBytesAlign; + const bool debug_fits = debug_offset_64 <= std::numeric_limits::max() && + debug_size_64 <= std::numeric_limits::max() && + debug_offset_64 + debug_size_64 <= area_size; + + geometry.layout.control_stack_offset = kControlStackOffset; + geometry.layout.control_stack_size = static_cast(control_stack_size); + geometry.layout.wave_state_offset = static_cast(wave_state_offset); + geometry.layout.wave_state_size = static_cast(wave_state_size); + geometry.layout.debug_offset = debug_fits ? static_cast(debug_offset_64) : 0; + geometry.layout.debug_size = debug_fits ? static_cast(debug_size_64) : 0; + geometry.layout.ok = true; + return geometry; +} + +uint32_t image_word(std::span image, uint32_t offset) { + uint32_t value = 0; + std::memcpy(&value, image.data() + offset, sizeof(value)); + return value; +} + +} // namespace + +CwsrLayout serialize_queue_cwsr(uint64_t ctx_base, uint32_t area_size, + const std::vector &waves, + const std::function &write32) { + CwsrLayout layout{}; + if (waves.empty() || !write32 || (ctx_base & (alignof(uint32_t) - 1)) != 0) + return layout; + + // Uniform per-dispatch register geometry. ACC-VGPRs are not modeled. gfx950 + // saves one uniformly-sized LDS block before each workgroup leader. + const CwsrGeometry geometry = compute_geometry(area_size, waves); + if (!geometry.layout.ok) + return layout; + layout = geometry.layout; + const uint32_t vgpr_count = geometry.vgpr_count; + const uint32_t sgpr_count = geometry.sgpr_count; + const uint32_t vcc_lo_slot = geometry.vcc_lo_slot; + const uint32_t hwreg_bytes = geometry.hwreg_bytes; + const uint32_t sgpr_bytes = geometry.sgpr_bytes; + const uint32_t vgpr_bytes = geometry.vgpr_bytes; + const uint32_t lds_bytes = geometry.lds_bytes; + const uint64_t num_waves = waves.size(); + const uint64_t wave_state_offset = layout.wave_state_offset; + if (ctx_base > std::numeric_limits::max() - wave_state_offset) + return CwsrLayout{}; + + // Write the payload first so a newly allocated area is not advertised before + // all bytes referenced by its header are initialized. + const uint64_t cs_base = ctx_base + layout.control_stack_offset; + write32(cs_base + 0, 0); // PM4 (skipped) + write32(cs_base + 4, 0); // PM4 (skipped) + write32(cs_base + 8, encode_state_word(vgpr_count, sgpr_count, lds_bytes)); + for (size_t i = 0; i < num_waves; ++i) { + // first/last mark workgroup boundaries in the control stack, not the whole + // queue: a wave is "first" if it opens a new workgroup (group leader) and + // "last" if it closes one. Callers order waves so each workgroup's waves are + // contiguous and set these flags per workgroup. + write32(cs_base + 12 + i * 4, + encode_wave_word(waves[i].is_first_in_group, waves[i].is_last_in_group, + waves[i].scratch_scoreboard_id)); + } + + // --- Per-wave register blocks, laid out high-to-low from wave_state_offset, + // reproducing gfx9_architecture_t::cwsr_record_t::register_address. --- + uint64_t last_wave_area = ctx_base + wave_state_offset; + for (size_t i = 0; i < num_waves; ++i) { + const CwsrWaveState &w = waves[i]; + const uint64_t save_area_addr = last_wave_area - 64; + uint64_t register_area_end = save_area_addr; + for (uint32_t byte = 0; byte < 64; byte += sizeof(uint32_t)) + write32(save_area_addr + byte, 0); + + if (w.is_first_in_group) { + register_area_end -= lds_bytes; + for (uint32_t byte = 0; byte < lds_bytes; byte += sizeof(uint32_t)) { + uint32_t value = 0; + if (byte < w.lds.size()) + std::memcpy(&value, w.lds.data() + byte, + std::min(sizeof(value), w.lds.size() - byte)); + write32(register_area_end + byte, value); + } + } + const uint64_t hwregs_addr = register_area_end - hwreg_bytes; + const uint64_t ttmps_addr = register_area_end - kTtmpCount * sizeof(uint32_t); + const uint64_t sgprs_addr = hwregs_addr - sgpr_bytes; + const uint64_t vgprs_addr = sgprs_addr - vgpr_bytes; + + // HWREG block (32 dwords). The top 16 dwords are the TTMPs. + write32(hwregs_addr + 0 * 4, w.m0); + write32(hwregs_addr + 1 * 4, static_cast(w.pc & 0xFFFFFFFF)); + write32(hwregs_addr + 2 * 4, static_cast(w.pc >> 32)); + write32(hwregs_addr + 3 * 4, static_cast(w.exec & 0xFFFFFFFF)); + write32(hwregs_addr + 4 * 4, static_cast(w.exec >> 32)); + write32(hwregs_addr + 5 * 4, w.status); + write32(hwregs_addr + 6 * 4, w.trapsts); + write32(hwregs_addr + 7 * 4, 0); // xnack_mask_lo + write32(hwregs_addr + 8 * 4, 0); // xnack_mask_hi + write32(hwregs_addr + 9 * 4, w.mode); + for (uint32_t h = 10; h < 16; ++h) + write32(hwregs_addr + h * 4, 0); + + // TTMP0-15 occupy hwreg[16..31] (== ttmps_addr). + uint32_t ttmp[kTtmpCount] = {}; + ttmp[4] = static_cast(w.wave_id & 0xFFFFFFFF); + ttmp[5] = static_cast(w.wave_id >> 32); + ttmp[6] = encode_ttmp6(w); + ttmp[8] = w.group_ids[0]; + ttmp[9] = w.group_ids[1]; + ttmp[10] = w.group_ids[2]; + ttmp[11] = encode_ttmp11(w); + for (uint32_t t = 0; t < kTtmpCount; ++t) + write32(ttmps_addr + t * 4, ttmp[t]); + + // SGPR block. Fill meaningful scalars, then place VCC at its aliased slot. + // num_sgprs may reach the full block, so without this bound the aliases + // would be filled from sgprs[] first and then overwritten, and deserialize + // would read the alias bytes straight back as SGPRs. Skip only the slots + // the aliases below actually occupy, not everything above the gfx9.4 + // architected count: s104/s105 sit between FLAT_SCRATCH and VCC and are + // real registers. Filling an aliased slot from sgprs[] first would be + // harmless (it is overwritten), but deserialize and the wave writeback have + // to skip exactly the same set, and deriving all three from one predicate + // is what keeps them in step. + for (uint32_t s = 0; s < sgpr_count; ++s) { + const bool aliased = cwsr_sgpr_slot_is_aliased(s); + uint32_t val = (!aliased && s < w.num_sgprs && s < w.sgprs.size()) ? w.sgprs[s] : 0u; + write32(sgprs_addr + s * 4, val); + } + write32(sgprs_addr + vcc_lo_slot * 4, static_cast(w.vcc & 0xFFFFFFFF)); + write32(sgprs_addr + (vcc_lo_slot + 1) * 4, static_cast(w.vcc >> 32)); + // FLAT_SCRATCH aliases the two scalar slots below VCC (gfx9_4: + // aliased_sgpr_end - 6/-5; rocdbgapi architecture.cpp register_address). + // rocm-dbgapi checks its computed per-wave scratch base against this + // register, so it must hold the wave's scratch base. + const uint32_t flat_scratch_lo_slot = geometry.flat_scratch_lo_slot; + write32(sgprs_addr + flat_scratch_lo_slot * 4, + static_cast(w.flat_scratch & 0xFFFFFFFF)); + write32(sgprs_addr + (flat_scratch_lo_slot + 1) * 4, + static_cast(w.flat_scratch >> 32)); + + // VGPR block: each VGPR is 64 lanes * 4 bytes; lane l of vgpr r at +r*256+l*4. + for (uint32_t r = 0; r < vgpr_count; ++r) { + for (uint32_t lane = 0; lane < 64; ++lane) { + uint32_t idx = r * 64 + lane; + uint32_t val = (r < w.num_vgprs && idx < w.vgprs.size()) ? w.vgprs[idx] : 0u; + write32(vgprs_addr + r * kVgprLaneBytes + lane * 4, val); + } + } + + last_wave_area = vgprs_addr; // == register_address(v0_64) + } + + // Publish the ABI header after the complete payload. A caller that permits a + // debugger to read concurrently must still provide the required exclusion. + write32(ctx_base + 0, layout.control_stack_offset); + write32(ctx_base + 4, layout.control_stack_size); + write32(ctx_base + 8, layout.wave_state_offset); + write32(ctx_base + 12, layout.wave_state_size); + write32(ctx_base + 16, layout.debug_offset); + write32(ctx_base + 20, layout.debug_size); + write32(ctx_base + 24, 0); // err_payload_addr lo + write32(ctx_base + 28, 0); // err_payload_addr hi + write32(ctx_base + 32, 0); // err_event_id + write32(ctx_base + 36, 0); // reserved1 + + return layout; +} + +CwsrLayout serialize_queue_cwsr_bulk( + uint64_t ctx_base, uint32_t area_size, const std::vector &waves, + const std::function)> &write_block) { + if (!write_block) + return {}; + + std::vector image; + CwsrLayout layout = + serialize_queue_cwsr(ctx_base, area_size, waves, [&](uint64_t address, uint32_t value) { + const uint64_t offset = address - ctx_base; + if (offset + sizeof(value) > image.size()) + image.resize(static_cast(offset + sizeof(value))); + std::memcpy(image.data() + offset, &value, sizeof(value)); + }); + if (!layout.ok) + return layout; + + image.resize(layout.wave_state_offset); + const std::span bytes{image}; + write_block(ctx_base + layout.control_stack_offset, + bytes.subspan(layout.control_stack_offset, + layout.wave_state_offset - layout.control_stack_offset)); + write_block(ctx_base, bytes.first(kCwsrHeaderBytes)); + return layout; +} + +bool deserialize_queue_cwsr(uint64_t ctx_base, uint32_t area_size, + std::vector &waves, + const std::function &read32) { + if (waves.empty() || !read32 || (ctx_base & (alignof(uint32_t) - 1)) != 0) + return false; + + // Reproduce the exact geometry serialize_queue_cwsr chose (see that function). + // The wave count and per-wave sgpr/vgpr counts must match, so the register + // block addresses computed below land on the same dwords that were written. + const CwsrGeometry geometry = compute_geometry(area_size, waves); + if (!geometry.layout.ok || + ctx_base > std::numeric_limits::max() - geometry.layout.wave_state_offset) + return false; + const uint32_t vcc_lo_slot = geometry.vcc_lo_slot; + const uint32_t hwreg_bytes = geometry.hwreg_bytes; + const uint32_t sgpr_bytes = geometry.sgpr_bytes; + const uint32_t vgpr_bytes = geometry.vgpr_bytes; + const uint32_t lds_bytes = geometry.lds_bytes; + const uint32_t num_waves = static_cast(waves.size()); + + uint64_t last_wave_area = ctx_base + geometry.layout.wave_state_offset; + for (uint32_t i = 0; i < num_waves; ++i) { + CwsrWaveState &w = waves[i]; + const uint64_t save_area_addr = last_wave_area - 64; + uint64_t register_area_end = save_area_addr; + if (w.is_first_in_group) { + register_area_end -= lds_bytes; + w.lds.resize(lds_bytes); + for (uint32_t byte = 0; byte < lds_bytes; byte += sizeof(uint32_t)) { + const uint32_t value = read32(register_area_end + byte); + std::memcpy(w.lds.data() + byte, &value, sizeof(value)); + } + } else { + w.lds.clear(); + } + const uint64_t hwregs_addr = register_area_end - hwreg_bytes; + const uint64_t ttmps_addr = register_area_end - kTtmpCount * sizeof(uint32_t); + const uint64_t sgprs_addr = hwregs_addr - sgpr_bytes; + const uint64_t vgprs_addr = sgprs_addr - vgpr_bytes; + + w.m0 = read32(hwregs_addr + 0 * 4); + w.pc = static_cast(read32(hwregs_addr + 1 * 4)) | + (static_cast(read32(hwregs_addr + 2 * 4)) << 32); + w.exec = static_cast(read32(hwregs_addr + 3 * 4)) | + (static_cast(read32(hwregs_addr + 4 * 4)) << 32); + w.status = read32(hwregs_addr + 5 * 4); + w.trapsts = read32(hwregs_addr + 6 * 4); + w.mode = read32(hwregs_addr + 9 * 4); + + const uint32_t ttmp4 = read32(ttmps_addr + 4 * 4); + const uint32_t ttmp5 = read32(ttmps_addr + 5 * 4); + w.wave_id = static_cast(ttmp4) | (static_cast(ttmp5) << 32); + const uint32_t ttmp6 = read32(ttmps_addr + 6 * 4); + w.wave_stopped = (ttmp6 & (1u << 30)) != 0; + w.saved_status_halt = (ttmp6 & (1u << 29)) != 0; + w.spi_ttmps_setup = (ttmp6 & (1u << 31)) == 0; + w.group_ids[0] = read32(ttmps_addr + 8 * 4); + w.group_ids[1] = read32(ttmps_addr + 9 * 4); + w.group_ids[2] = read32(ttmps_addr + 10 * 4); + const uint32_t ttmp11 = read32(ttmps_addr + 11 * 4); + w.wave_in_group = ttmp11 & 0x3Fu; + w.queue_packet_id = (ttmp11 >> 6) & 0x1FFFFFFu; + + // Read back only the slots that hold real registers. The aliased ones are + // decoded as the registers they alias, below; treating them as SGPRs put + // FLAT_SCRATCH's bytes into s102/s103 on a round trip. + w.sgprs.assign(w.num_sgprs, 0u); + for (uint32_t s = 0; s < w.num_sgprs; ++s) + if (!cwsr_sgpr_slot_is_aliased(s)) + w.sgprs[s] = read32(sgprs_addr + s * 4); + const uint32_t vcc_lo = read32(sgprs_addr + vcc_lo_slot * 4); + const uint32_t vcc_hi = read32(sgprs_addr + (vcc_lo_slot + 1) * 4); + w.vcc = static_cast(vcc_lo) | (static_cast(vcc_hi) << 32); + // FLAT_SCRATCH is serialized into its alias slots but was never read back, + // so a serialize/deserialize round trip silently dropped it. + const uint32_t flat_scratch_lo_slot = geometry.flat_scratch_lo_slot; + const uint32_t fs_lo = read32(sgprs_addr + flat_scratch_lo_slot * 4); + const uint32_t fs_hi = read32(sgprs_addr + (flat_scratch_lo_slot + 1) * 4); + w.flat_scratch = static_cast(fs_lo) | (static_cast(fs_hi) << 32); + + w.vgprs.resize(static_cast(w.num_vgprs) * 64); + for (uint32_t r = 0; r < w.num_vgprs; ++r) + for (uint32_t lane = 0; lane < 64; ++lane) + w.vgprs[r * 64 + lane] = read32(vgprs_addr + r * kVgprLaneBytes + lane * 4); + + last_wave_area = vgprs_addr; + } + return true; +} + +bool deserialize_queue_cwsr_bulk( + uint64_t ctx_base, uint32_t area_size, std::vector &waves, + const std::function)> &read_block) { + if (!read_block || (ctx_base & (alignof(uint32_t) - 1)) != 0) + return false; + const CwsrGeometry geometry = compute_geometry(area_size, waves); + if (!geometry.layout.ok || + ctx_base > std::numeric_limits::max() - geometry.layout.wave_state_offset) + return false; + + std::array header{}; + read_block(ctx_base, header); + const std::span header_bytes{header}; + if (image_word(header_bytes, 0) != geometry.layout.control_stack_offset || + image_word(header_bytes, 4) != geometry.layout.control_stack_size || + image_word(header_bytes, 8) != geometry.layout.wave_state_offset || + image_word(header_bytes, 12) != geometry.layout.wave_state_size || + image_word(header_bytes, 16) != geometry.layout.debug_offset || + image_word(header_bytes, 20) != geometry.layout.debug_size) + return false; + + std::vector image(geometry.layout.wave_state_offset); + std::memcpy(image.data(), header.data(), header.size()); + std::span payload{image.data() + geometry.layout.control_stack_offset, + geometry.layout.wave_state_offset - + geometry.layout.control_stack_offset}; + read_block(ctx_base + geometry.layout.control_stack_offset, payload); + + bool in_bounds = true; + const bool decoded = deserialize_queue_cwsr(ctx_base, area_size, waves, [&](uint64_t address) { + const uint64_t offset = address - ctx_base; + if (offset + sizeof(uint32_t) > image.size()) { + in_bounds = false; + return uint32_t{0}; + } + return image_word(image, static_cast(offset)); + }); + return decoded && in_bounds; +} + +} // namespace kmd +} // namespace rocjitsu diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.h new file mode 100644 index 000000000000..ee1390a55ea3 --- /dev/null +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/cwsr.h @@ -0,0 +1,258 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file cwsr.h +/// @brief Serialization of stopped-wave state into the KFD context-save-restore +/// (CWSR) area in the exact layout rocm-dbgapi parses. +/// +/// @details rocm-dbgapi never reads wave registers through an ioctl. It reads +/// them by `pread`-ing the inferior's /proc//mem at the queue's +/// context-save-restore GPU virtual address, interpreting a control stack and a +/// per-wave save area whose byte layout is defined by the CWSR ABI. The +/// emulator hosts wave state in the daemon, so on a wave stop it must write that +/// state into the (memfd-shared) CWSR area at exactly the offsets dbgapi +/// computes. This module reproduces the gfx9.4 layout used by CDNA3/CDNA4 +/// (gfx942/gfx950), cross-checked against projects/rocdbgapi/src/architecture.cpp +/// (gfx90a/gfx9_4/mi cwsr_record_t). Earlier gfx9 generations differ: gfx908 +/// saves an ACC-VGPR block, and gfx908/gfx90a keep the packet id in TTMP6. + +#ifndef ROCJITSU_KMD_LINUX_CWSR_H_ +#define ROCJITSU_KMD_LINUX_CWSR_H_ + +#include "rocjitsu/code/rj_code.h" +#include "rocjitsu/kmd/linux/amdgpu_properties.h" + +#include +#include +#include +#include +#include + +namespace rocjitsu { +namespace kmd { + +/// @brief Whether this module models the CWSR record layout for @p arch. +/// @details The codec reproduces the gfx9.4 layout only, and the differences on +/// other generations are not confined to one field: the control stack carries a +/// different number of state words, COMPUTE_RELAUNCH packs different bits, the +/// VGPR stride assumes wave64, the SGPR alias slots sit elsewhere, and the +/// dispatch identity lives in different TTMPs. Serializing a wave from an +/// unmodelled architecture would hand rocm-dbgapi an image it decodes against +/// its own layout, which is worse than refusing: the debugger reads plausible +/// nonsense instead of reporting that the target is unsupported. +/// @param arch Architecture of the GPU whose queue would be serialized. +/// @returns True if serialize/deserialize produce an image dbgapi can decode. +constexpr bool cwsr_layout_modelled(rj_code_arch_t arch) { + // gfx942 / gfx950. gfx908 adds an ACC-VGPR block and gfx908/gfx90a keep the + // packet id in TTMP6, so CDNA1/CDNA2 are deliberately excluded even though + // they are also gfx9. + return arch == ROCJITSU_CODE_ARCH_CDNA3 || arch == ROCJITSU_CODE_ARCH_CDNA4; +} + +/// @brief The same question as cwsr_layout_modelled(), asked of a GPU named the +/// way KFD names one. +/// @details The two predicates exist because their callers hold different +/// identities. The DBG_TRAP paths have a SoC and so an arch enum; the KFD +/// topology paths only ever see a @c gfx_target_version, which they translate to +/// the GC hardware IP version the amdkfd driver keys on. Kept adjacent so the +/// two spellings of "gfx942 and gfx950 only" cannot be updated apart -- +/// KfdTopologyTest.ArchAndGcSpellingsOfTheCwsrGateAgree pins them together. +/// \NPI update this alongside cwsr_layout_modelled() when the codec learns a +/// new record layout. +/// @param gc_ip_version Packed GC hardware IP version, as +/// gc_ip_version_for_gfx_target_version() produces. +/// @returns True if serialize/deserialize produce an image dbgapi can decode. +constexpr bool cwsr_layout_modelled_for_gc_ip_version(uint32_t gc_ip_version) { + return gc_ip_version == make_gc_ip_version(9, 4, 3) || // gfx942 (CDNA3) + gc_ip_version == make_gc_ip_version(9, 5, 0); // gfx950 (CDNA4) +} + +/// @brief Number of scalar slots in a saved SGPR block (gfx9.4 sgpr_count). +/// @details The block is a fixed 112 slots regardless of how many scalars the +/// dispatch actually allocated. It is also an input to the COMPUTE_RELAUNCH +/// state word (sgprs_field = kCwsrSavedSgprSlots / 16, which must stay inside +/// three bits), not just to the alias arithmetic below. +inline constexpr uint32_t kCwsrSavedSgprSlots = 112; +/// @brief gfx9.4 scalar_register_count(): the architected scalars s0..s101. +/// @details Selectors at or above this alias VCC, FLAT_SCRATCH and XNACK_MASK +/// rather than naming an SGPR. +inline constexpr uint32_t kCwsrArchScalarRegisters = 102; +/// @brief One past the last aliased slot (+ gfx9.4 scalar_alias_count() of 6). +inline constexpr uint32_t kCwsrAliasedSgprEnd = kCwsrArchScalarRegisters + 6; // 108 +/// @brief Slot holding VCC_LO; VCC_HI is the next one up. +inline constexpr uint32_t kCwsrVccLoSlot = kCwsrAliasedSgprEnd - 2; // 106 +/// @brief Slot holding FLAT_SCRATCH_LO; FLAT_SCRATCH_HI is the next one up. +inline constexpr uint32_t kCwsrFlatScratchLoSlot = kCwsrAliasedSgprEnd - 6; // 102 +static_assert(kCwsrAliasedSgprEnd <= kCwsrSavedSgprSlots, + "aliased slots must land inside the saved SGPR block"); + +/// @brief Whether a saved SGPR slot is occupied by an aliased register. +/// +/// @details VCC and FLAT_SCRATCH are written into slots near the top of the +/// block rather than being stored separately, so those slots do not hold the +/// SGPR their index names. Every path that walks the block by slot index must +/// consult this: the codec (both directions) so a round trip does not read an +/// alias back as a register, and the wave writeback so a debugger edit to a +/// real register above @ref kCwsrArchScalarRegisters is not dropped. Note that +/// the aliases are *not* a contiguous top range -- s104 and s105 sit between +/// FLAT_SCRATCH and VCC and are ordinary registers -- which is why a `slot < +/// 102` bound is not equivalent. +/// @param slot Index into the saved SGPR block. +/// @returns True if the slot holds an alias rather than SGPR @p slot. +constexpr bool cwsr_sgpr_slot_is_aliased(uint32_t slot) { + return slot == kCwsrVccLoSlot || slot == kCwsrVccLoSlot + 1 || slot == kCwsrFlatScratchLoSlot || + slot == kCwsrFlatScratchLoSlot + 1; +} + +/// @brief The saved architectural state of one stopped wave. +/// +/// @details Register values are the live wave state; the serializer places them +/// at the CWSR offsets rocm-dbgapi expects and synthesizes the trap-temporary +/// registers (TTMP4-11) that carry the wave's debugger metadata. +struct CwsrWaveState { + uint64_t pc = 0; ///< Program counter (past the s_trap on a breakpoint). + uint64_t exec = 0; ///< EXEC mask. + uint64_t vcc = 0; ///< VCC (placed into its aliased SGPR slot). + /// FLAT_SCRATCH base register (gfx9_4 architected flat scratch), placed into + /// its aliased SGPR slot. rocm-dbgapi validates the scratch base it computes + /// from COMPUTE_TMPRING_SIZE against this register (wave.cpp + /// scratch_memory_region); a mismatch disables private-memory access. + uint64_t flat_scratch = 0; + uint32_t status = 0; ///< STATUS register. + uint32_t trapsts = 0; ///< TRAPSTS register. + uint32_t mode = 0; ///< MODE register. + uint32_t m0 = 0; ///< M0 register. + + uint64_t wave_id = 0; ///< Stable, unique wave id (TTMP4:5) dbgapi reads as its own. + std::array group_ids{}; ///< Workgroup coordinates (TTMP8/9/10). + uint32_t wave_in_group = 0; ///< Wave index within the workgroup (TTMP11[0:5]). + uint32_t queue_packet_id = 0; ///< Dispatch packet id (TTMP11[6:30]). + /// Whether this wave is the first / last of its workgroup in the control stack. + /// rocm-dbgapi groups consecutive control-stack waves into a workgroup: the + /// first wave becomes the group leader and following waves must share its + /// group ids until the last wave closes the group (rocdbgapi queue.cpp + /// update_waves). These must therefore be set per workgroup, not per queue. + bool is_first_in_group = true; + bool is_last_in_group = true; + /// This wave's slot in the queue's scratch allocation (COMPUTE_RELAUNCH wave + /// word bits [0:8]). rocm-dbgapi multiplies it by the per-wave scratch size to + /// locate the wave's private memory, so it must match the wave's scratch base. + uint32_t scratch_scoreboard_id = 0; + uint32_t trap_id = 0; ///< Trap id from the s_trap (TTMP6[25:28]). + bool wave_stopped = true; ///< Whether the wave is stopped (TTMP6[30]). + bool saved_status_halt = false; ///< Saved STATUS.HALT (TTMP6[29]). + /// Whether the SPI initialized the dispatch-bookkeeping TTMPs (group ids in + /// TTMP8-10, packet id in TTMP11). Mirrors kfd_runtime_info.ttmp_setup; when + /// false, TTMP6[31] (spi_ttmps_setup_disabled) is set and rocm-dbgapi skips + /// packet/workgroup correlation for the wave. + bool spi_ttmps_setup = false; + + /// Meaningful scalar registers, at most @ref kCwsrSavedSgprSlots. Slots for + /// which @ref cwsr_sgpr_slot_is_aliased holds do not round trip: they carry + /// VCC and FLAT_SCRATCH, which travel in their own fields. + uint32_t num_sgprs = 0; + uint32_t num_vgprs = 0; ///< Meaningful wave64 vector registers (at most 256). + /// Scalar register values, index = sgpr number. + std::vector sgprs; + /// Vector register values, index = vgpr_number * 64 + lane. + std::vector vgprs; + /// Workgroup LDS bytes. Present only on the first wave in each workgroup. + std::vector lds; +}; + +/// @brief The CWSR geometry chosen for a serialized wave save area. +/// +/// @details Returned so callers (and tests) can locate the per-register offsets +/// dbgapi will compute. All offsets are relative to the ctx-save base. +struct CwsrLayout { + uint32_t control_stack_offset = 0; ///< Offset to the first control-stack word. + uint32_t control_stack_size = 0; ///< Control-stack size in bytes. + /// Offset to the high end (one past the last byte) of the wave-state area. + uint32_t wave_state_offset = 0; + uint32_t wave_state_size = 0; ///< Size extending down from @ref wave_state_offset. + uint32_t debug_offset = 0; ///< Offset of the debugger displaced-step region. + uint32_t debug_size = 0; ///< Size of the debugger displaced-step region. + bool ok = false; ///< False if the waves do not fit in the ctx-save area. +}; + +/// @brief Serialize a queue's stopped waves into its CWSR area. +/// +/// @param ctx_base Context-save-restore GPU virtual address (from the queue). +/// @param area_size Context-save-restore area size in bytes (from the queue). +/// @param waves The stopped waves, in the order they should appear (the first +/// owns the workgroup's LDS region at the top of the save area). +/// @param write32 Callback that writes one dword to a GPU virtual address. +/// @returns The chosen layout; @ref CwsrLayout::ok is false if the waves do not +/// fit, in which case nothing is written. +/// +/// The written layout satisfies rocm-dbgapi's invariants: a header at the base, +/// a control stack (two skipped PM4 words, one state word, one wave word per +/// wave) contiguous with the wave save area, and per-wave register blocks laid +/// out high-to-low as [TTMP|HWREG] / [SGPR] / [VGPR] at the offsets +/// gfx9_architecture_t::cwsr_record_t::register_address computes. +/// +/// This gfx9.4 serializer requires a dword-aligned base, no more than +/// @ref kCwsrSavedSgprSlots meaningful SGPRs or 256 VGPRs per wave, and a +/// non-null writer. The caller +/// must keep the queue suspended and wave/register storage alive for the whole +/// call, serialize against a stable snapshot, and provide a writer that +/// publishes directly to the inferior-visible coherent CWSR mapping. The +/// serializer writes payload before the header, but cross-thread/process +/// exclusion and any required cache maintenance remain the caller's +/// responsibility. +CwsrLayout serialize_queue_cwsr(uint64_t ctx_base, uint32_t area_size, + const std::vector &waves, + const std::function &write32); + +/// @brief Serialize a queue using two block writes: payload first, then header. +/// +/// @details This is the production-oriented equivalent of +/// @ref serialize_queue_cwsr. It constructs the same byte-exact image but +/// publishes the contiguous control-stack/wave payload with one callback and +/// the 40-byte ABI header with a second callback. Keeping the header write last +/// preserves the CWSR publication contract while avoiding a GPU page-table +/// lookup and lock acquisition for every dword of every wave register. +/// +/// @param write_block Callback receiving a target address and contiguous bytes. +/// @returns The chosen layout; @ref CwsrLayout::ok is false and no callback is +/// made when the image is invalid or does not fit. +CwsrLayout serialize_queue_cwsr_bulk( + uint64_t ctx_base, uint32_t area_size, const std::vector &waves, + const std::function)> &write_block); + +/// @brief Read wave register state back from a serialized CWSR area. +/// +/// @details The inverse of @ref serialize_queue_cwsr. rocm-dbgapi writes a +/// stopped wave's registers (PC, EXEC, VCC, STATUS, MODE, SGPRs, VGPRs, and the +/// TTMP6 run/stop and MODE.debug_en bits) straight into the CWSR area via +/// /proc//mem; on resume the driver reads them back to apply the debugger's +/// edits to the live wave and to learn the requested run vs. single-step state. +/// +/// @param ctx_base Context-save-restore GPU virtual address (from the queue). +/// @param area_size Context-save-restore area size in bytes (from the queue). +/// @param waves In: each element supplies the wave geometry (@ref +/// CwsrWaveState::num_sgprs / @ref CwsrWaveState::num_vgprs) and ordering +/// used to reproduce the exact layout; Out: filled with the values +/// currently stored in the area. The count and geometry must match the +/// @ref serialize_queue_cwsr call that produced the area. +/// @param read32 Callback that reads one dword from a GPU virtual address. +/// @returns True on success; false if the waves do not fit the area (in which +/// case @p waves is left unchanged). +bool deserialize_queue_cwsr(uint64_t ctx_base, uint32_t area_size, + std::vector &waves, + const std::function &read32); + +/// @brief Read and deserialize a queue CWSR image using block transfers. +/// +/// @details Validates the ABI header against the geometry implied by @p waves, +/// reads the contiguous control-stack/wave payload once, then applies the same +/// decoder as @ref deserialize_queue_cwsr. The queue must remain suspended for +/// the complete operation. +bool deserialize_queue_cwsr_bulk( + uint64_t ctx_base, uint32_t area_size, std::vector &waves, + const std::function)> &read_block); + +} // namespace kmd +} // namespace rocjitsu + +#endif // ROCJITSU_KMD_LINUX_CWSR_H_ diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp index 2b99aceaf7fb..e8c27597fefb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/interposer.cpp @@ -44,6 +44,7 @@ RJ_DIAGNOSTIC_POP #include "util/log.h" #include +#include #include #include #include @@ -135,6 +136,57 @@ int try_connect(const std::string &path) { return sock; } +bool is_proc_maps_path(const char *path) { + if (!path || !std::string_view(path).starts_with("/proc/")) + return false; + const std::string_view name(path); + return name.ends_with("/maps") || name.ends_with("/smaps"); +} + +int open_proc_maps_snapshot(const char *path, int flags) { + if (!is_proc_maps_path(path) || (flags & O_ACCMODE) != O_RDONLY) + return -1; + + auto &libc = rocjitsu::libc_passthrough(); + int source = libc.openat(AT_FDCWD, path, flags, 0); + if (source < 0) + return -1; + std::string contents; + std::array buffer{}; + while (true) { + ssize_t count = libc.read(source, buffer.data(), buffer.size()); + if (count <= 0) + break; + contents.append(buffer.data(), static_cast(count)); + } + int read_errno = errno; + libc.close(source); + if (contents.find("/memfd:rocjitsu_remote_kfd (deleted)") == std::string::npos) { + errno = read_errno; + return -1; + } + + constexpr std::string_view marker = "/memfd:rocjitsu_remote_kfd (deleted)"; + size_t position = 0; + while ((position = contents.find(marker, position)) != std::string::npos) { + contents.replace(position, marker.size(), "/dev/kfd"); + position += sizeof("/dev/kfd") - 1; + } + + int snapshot = libc.memfd_create("rocjitsu_proc_maps", MFD_CLOEXEC); + if (snapshot < 0) + return -1; + if (libc.write(snapshot, contents.data(), contents.size()) != + static_cast(contents.size()) || + lseek(snapshot, 0, SEEK_SET) < 0) { + int saved_errno = errno; + libc.close(snapshot); + errno = saved_errno; + return -1; + } + return snapshot; +} + /// @brief Connect to the daemon for this invocation's per-PID runtime directory. /// @details Connects to /daemon.sock. Only when that per-PID /// directory does not exist (attach / daemon-only clients that share the @@ -264,6 +316,7 @@ class InterposerContext { static void init() { new (storage_) InterposerContext(); + ctx.owner_pid_ = getpid(); // Resolve the per-invocation runtime directory once here, in the library // constructor: this runs single-threaded before any app code (and thus before // any app fork). Writing it once here keeps invocation_runtime_dir() an @@ -297,9 +350,9 @@ class InterposerContext { // remote_ aliasing the parent's daemon connection — the next interposed // open()/ioctl()/close() in that child would then deadlock or corrupt the // parent's connection. pthread_atfork's child handler runs inside libc fork, - // covering every fork that goes through glibc. (vfork/posix_spawn children run - // no atfork handlers by design, but they may only exec/_exit, so there is no - // interposer state for them to corrupt.) reset_after_fork() is idempotent. It is + // covering every fork that goes through glibc. vfork/posix_spawn children run + // no atfork handlers; interposed close() detects that window by owner PID and + // avoids mutating the parent-shared context. reset_after_fork() is idempotent. It is // NOT strictly async-signal-safe — container clear()/destructors call free() and it // closes the child's dmabuf-dup fds — so it relies on the standard fork-then-exec / // single-threaded-fork assumption (the same one the remote_ handling documents @@ -317,6 +370,7 @@ class InterposerContext { /// be locked by threads that no longer exist. We reinitialize everything so /// the next open("/dev/kfd") creates a fresh connection. void reset_after_fork() { + owner_pid_ = getpid(); active_driver_.store(nullptr, std::memory_order_release); rj_vm_ = nullptr; if (guest_driver_) @@ -410,6 +464,8 @@ class InterposerContext { /// the same daemon rather than recomputing a dir under its own PID. const std::string &invocation_runtime_dir() const { return invocation_runtime_dir_; } + bool owned_by_current_process() const { return owner_pid_ == getpid(); } + // No lock needed: the snapshot keeps the RemoteDriver alive, and its handshake // metadata (topology/drm paths, gpu_info) is immutable after open() — close() // does not clear it — so this read never races a concurrent teardown. Callers @@ -1749,6 +1805,7 @@ class InterposerContext { } private: + pid_t owner_pid_ = 0; rj_vm_t *rj_vm_ = nullptr; std::unique_ptr guest_driver_; std::atomic active_driver_{nullptr}; @@ -2037,6 +2094,9 @@ RJ_INTERPOSER_EXPORT int open(const char *path, int flags, ...) { if (!p || InterposerContext::in_construction) return InterposerContext::real().openat(AT_FDCWD, path, flags, mode); + if (int snapshot = open_proc_maps_snapshot(path, flags); snapshot >= 0) + return snapshot; + if (auto drm_fd = open_synthetic_drm_fd(path); drm_fd.handled) return drm_fd.fd; @@ -2114,6 +2174,9 @@ RJ_INTERPOSER_EXPORT int openat(int dirfd, const char *path, int flags, ...) { return InterposerContext::real().openat(dirfd, path, flags, mode); if (path[0] == '/') { + if (int snapshot = open_proc_maps_snapshot(path, flags); snapshot >= 0) + return snapshot; + if (auto drm_fd = open_synthetic_drm_fd(path); drm_fd.handled) return drm_fd.fd; @@ -2153,6 +2216,11 @@ RJ_INTERPOSER_EXPORT int openat64(int dirfd, const char *path, int flags, ...) { RJ_INTERPOSER_EXPORT int close(int fd) { assert(InterposerContext::real().ready()); + // A vfork child shares the parent's address space until exec/_exit but has a + // separate descriptor table. Descriptor cleanup in that window must close the + // child's fd without clearing the parent's KFD/DRM bookkeeping. + if (!InterposerContext::ctx.owned_by_current_process()) + return static_cast(InterposerContext::real().close(fd)); if (InterposerContext::ctx.remote_lookup(fd)) { // Closing the primary remote KFD fd drops one open reference; the synthetic // fd and RPC connection are torn down only when the last reference is @@ -2913,8 +2981,10 @@ RJ_INTERPOSER_EXPORT int mprotect(void *addr, size_t length, int prot) { RJ_INTERPOSER_EXPORT int madvise(void *addr, size_t length, int advice) { assert(InterposerContext::real().ready()); - if ((advice == MADV_HUGEPAGE || advice == MADV_DONTFORK) && - reinterpret_cast(addr) >= 0x1000000000ULL) + const bool high_gpu_address = reinterpret_cast(addr) >= 0x1000000000ULL; + if (advice == MADV_HUGEPAGE && high_gpu_address) + return 0; + if (advice == MADV_DONTFORK && high_gpu_address && InterposerContext::ctx.driver_is_simulated()) return 0; return InterposerContext::real().madvise(addr, length, advice); } @@ -2955,6 +3025,10 @@ RJ_INTERPOSER_EXPORT FILE *fopen(const char *path, const char *mode) { if (!path || !mode) return nullptr; + int open_flags = InterposerContext::fopen_flags_from_mode(mode); + if (int snapshot = open_proc_maps_snapshot(path, open_flags); snapshot >= 0) + return fdopen(snapshot, mode); + const char *actual = path; std::string redirected; if (!InterposerContext::in_construction) { @@ -2965,8 +3039,7 @@ RJ_INTERPOSER_EXPORT FILE *fopen(const char *path, const char *mode) { actual = redirected.c_str(); } - int fd = InterposerContext::real().openat(AT_FDCWD, actual, - InterposerContext::fopen_flags_from_mode(mode), 0644); + int fd = InterposerContext::real().openat(AT_FDCWD, actual, open_flags, 0644); if (fd < 0) return nullptr; return fdopen(fd, mode); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_process.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_process.h index 75ba2f74e2a5..f75ef165c064 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_process.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_process.h @@ -13,10 +13,12 @@ #define ROCJITSU_KMD_LINUX_KFD_PROCESS_H_ #include "rocjitsu/kmd/linux/events.h" +#include "rocjitsu/kmd/linux/kfd_topology.h" #include "rocjitsu/vm/amdgpu/mtype.h" #include "util/unique_handle.h" #include +#include #include #include #include @@ -129,13 +131,15 @@ class KfdProcess { uint64_t r_debug = 0; }; - /// @brief Per-process debugger session state. + /// @brief Debugger session state for one target process. /// /// @details Mirrors the debug-related fields the kernel maintains on /// @c struct @c kfd_process in /// @c drivers/gpu/drm/amd/amdkfd/kfd_priv.h. - /// Managed by the @c AMDKFD_IOC_DBG_TRAP ioctl handler - /// (@c kfd_ioctl_set_debug_trap in the real driver). + /// SimulatedKfd stores these sessions in a table keyed by the target's Linux + /// pid, independently of KfdProcess, so a debugger can attach before the + /// inferior opens /dev/kfd. This mirrors the real driver's DBG_TRAP_ENABLE + /// path creating the target kfd_process. /// /// Field mapping to @c kfd_priv.h: /// | DebugSession field | kfd_process field | @@ -158,6 +162,15 @@ class KfdProcess { /// Bitmask of exception classes that are forwarded to the debugger. uint64_t exception_enable_mask = 0; + /// @brief Previously configured process debug flags. + uint32_t flags = 0; + + /// @brief Current wave launch mode. + uint32_t launch_mode = 0; + + /// @brief Current wave-launch trap override mask. + uint32_t launch_override_enable = 0; + /// @brief Mirrors @c kfd_process::dbg_ev_file (flattened from @c struct @c file* to fd). /// File descriptor used as the debugger notification / poll target. /// -1 when no debugger is attached. @@ -171,9 +184,98 @@ class KfdProcess { /// descriptor and is not owned here. RAII replaces an explicit close. util::UniqueHandle owned_dbg_fd; + /// @brief Debugger-authorized access to the target's address space. + /// @details The ptrace parent opens /proc//mem and transfers it to + /// the daemon, which cannot use process_vm_readv/process_vm_writev itself. + util::UniqueHandle target_mem_fd; + + /// @brief Pins the target process identity and reports target exit. + /// @details Prevents a stale session from being mistaken for a later process + /// that reuses the same numeric pid. + util::UniqueHandle target_pidfd; + + /// @brief Pins the target's procfs directory used for ptrace authorization. + /// @details Status is opened relative to this descriptor so authorization + /// cannot silently switch to a process that reuses the numeric pid. + util::UniqueHandle target_procfd; + /// @brief Mirrors @c kfd_process::debugger_process (stored as pid instead of pointer). /// Linux PID of the attached debugger (ptrace parent). 0 when not attached. pid_t debugger_pid = 0; + + /// @brief Target exit was observed and owned resources were released. + /// @details Keeps the pinned pidfd identity until a racing DISABLE consumes + /// the session, so numeric PID reuse cannot turn process exit into EINVAL. + bool target_exited = false; + + /// @brief The target's KfdProcess has been observed at least once. + /// @details Distinguishes the two ways a target can have no KfdProcess. + /// The real driver has only one: DBG_TRAP_ENABLE calls kfd_create_process, + /// so from then on the kfd_process exists and a failed lookup means the + /// process is gone (-ESRCH). Here the KfdProcess appears only when the + /// inferior opens /dev/kfd, which can be after the debugger attaches, so + /// "not up yet" and "torn down" are otherwise indistinguishable. + bool saw_kfd_process = false; + + /// @brief Pins the debugger process identity and reports debugger exit. + /// @details Mirrors the kernel's debugger-process notifier: the session is + /// disabled when the debugger task exits, even if the target remains alive. + util::UniqueHandle debugger_pidfd; + + /// @brief One programmed hardware address-watch register (TCP_WATCH0..3). + struct AddressWatch { + bool active = false; + uint64_t address = 0; + uint64_t mask = 0; + uint32_t mode = 0; + + /// @brief Construct the full hardware compare state from the KFD UAPI. + /// @details KFD transports only the programmable low 32 mask bits. The + /// upper address bits are fixed compares in TCP_WATCH and must remain + /// set, or unrelated addresses with the same low 32 bits alias. + static constexpr AddressWatch from_kfd(uint64_t address, uint32_t mask, uint32_t mode) { + return AddressWatch{true, address, 0xFFFFFFFF00000000ULL | mask, mode}; + } + + /// @brief Return whether an access overlaps the watched address block. + [[nodiscard]] constexpr bool overlaps(uint64_t access_address, uint32_t bytes) const { + if (!active || bytes == 0) + return false; + const uint64_t block_base = address & mask; + const uint64_t block_size = ~mask + 1; + const uint64_t access_end = + access_address > UINT64_MAX - bytes ? UINT64_MAX : access_address + bytes; + const uint64_t block_end = block_size == 0 || block_base > UINT64_MAX - block_size + ? UINT64_MAX + : block_base + block_size; + return block_size == 0 || (access_address < block_end && block_base < access_end); + } + }; + /// The register file the topology advertises, so a debugger can never hold + /// more watchpoints than the device snapshot told it exist. + static constexpr uint32_t kMaxAddressWatches = kmd::kNumWatchPoints; + std::array address_watches; + + /// @brief Return a bit for every hardware watch slot matching an access. + /// @details A single access may overlap multiple programmed watch ranges. + /// Hardware reports all of them concurrently in TRAPSTS, allowing the + /// debugger to associate every logical watchpoint with the same stop. + /// @param matching_modes Bit set of watch modes the access satisfies, + /// indexed by mode value. The modes overlap (a write is both NONREAD and + /// ALL), so the caller -- which owns the KFD ABI -- resolves them into this + /// set rather than passing a single mode to compare for equality. + [[nodiscard]] constexpr uint32_t matching_address_watch_slots(uint64_t access_address, + uint32_t bytes, + uint32_t matching_modes) const { + uint32_t slots = 0; + for (uint32_t slot = 0; slot < kMaxAddressWatches; ++slot) { + const auto &watch = address_watches[slot]; + if (watch.mode < 32 && ((matching_modes >> watch.mode) & 1u) != 0 && + watch.overlaps(access_address, bytes)) + slots |= uint32_t{1} << slot; + } + return slots; + } }; // GPUVM uses the simulator's fixed 4 KiB translation granule. This models @@ -497,6 +599,27 @@ class KfdProcess { }; std::unordered_map queue_doorbell_map_; + /// @brief Debug-relevant per-queue info reported by GET_QUEUE_SNAPSHOT. + /// + /// @details Captured when CREATE_QUEUE completes. rocm-dbgapi consumes the + /// context-save-restore address/size to locate each queue's CWSR area (from + /// which it walks the wave save state), plus the ring pointers to correlate + /// dispatches. Mirrors the fields the kernel fills in + /// @c kfd_queue_snapshot_entry (kfd_process_queue_manager.c: + /// @c pqm_get_queue_snapshot). + struct QueueSnapshotInfo { + uint64_t ring_base_address = 0; + uint64_t write_pointer_address = 0; + uint64_t read_pointer_address = 0; + uint64_t ctx_save_restore_address = 0; + uint32_t ctx_save_restore_area_size = 0; + uint32_t ring_size = 0; + uint32_t queue_type = 0; + uint32_t gpu_id = 0; + uint64_t exception_status = 0; ///< Raised exceptions on this queue (KFD_EC_MASK bits). + }; + std::unordered_map queue_snapshot_map_; + EventState event_state_; std::unordered_map memory_policies_; @@ -506,9 +629,6 @@ class KfdProcess { std::mutex runtime_mutex_; RuntimeState runtime_state_; - mutable std::mutex debug_mutex_; - DebugSession debug_session_; - private: static void normalize_host_extents(PageTableEntry &page) { auto &extents = page.host_extents; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_topology.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_topology.h index 8a084a2c2407..36a4fc09d620 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_topology.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_topology.h @@ -32,6 +32,7 @@ RJ_DIAGNOSTIC_IGNORE_PEDANTIC RJ_DIAGNOSTIC_POP #include "rocjitsu/kmd/linux/amdgpu_properties.h" +#include "rocjitsu/kmd/linux/cwsr.h" #include @@ -117,7 +118,10 @@ inline DebugTopology debug_topology_for(uint32_t gfx_target_version) { DebugTopology topo; - // Trap-based debugging is advertised for every debug-capable GPU. + // Trap-based debugging is advertised for every debug-capable GPU. The + // simulator withholds the support bit again at the end of this function for + // parts whose CWSR layout it cannot produce; derive it here so the driver + // mirroring stays readable as one piece. topo.capability = HSA_CAP_TRAP_DEBUG_SUPPORT | HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED | HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED; @@ -125,7 +129,9 @@ inline DebugTopology debug_topology_for(uint32_t gfx_target_version) { // Every debug-capable ASIC the simulator models carries the four hardware // address-watch registers, so advertise them here rather than alongside the // generic non-debug bits: rocdbgapi reads this out of the device snapshot to - // decide how many data watchpoints it may insert. + // decide how many data watchpoints it may insert. Without the bits it reports + // zero watch registers and refuses to insert one ("too many hardware + // watchpoints"). topo.capability |= HSA_CAP_WATCH_POINTS_SUPPORTED | ((kWatchPointsTotalBits << HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT) & HSA_CAP_WATCH_POINTS_TOTALBITS_MASK); @@ -171,6 +177,19 @@ inline DebugTopology debug_topology_for(uint32_t gfx_target_version) { // The simulator always provides compatible "firmware", so advertise it. topo.capability |= HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED; + // Everything above mirrors the driver. This does not, and is the one place the + // simulator is deliberately less capable than the hardware it models: a + // debugger can only be serviced on a part whose CWSR record layout the codec + // reproduces, because rocm-dbgapi reads wave state straight out of the save + // area rather than through an ioctl. Withhold the single bit it keys + // agent_t::supports_debugging() on, so an unmodelled agent is declined at the + // capability boundary -- at attach, with every other agent still usable -- + // instead of attaching and then having each individual wave stop declined. + // The descriptive sub-capabilities stay as the driver derives them; they + // qualify a support that is no longer claimed. + if (!cwsr_layout_modelled_for_gc_ip_version(gc)) + topo.capability &= ~static_cast(HSA_CAP_TRAP_DEBUG_SUPPORT); + return topo; } @@ -188,6 +207,12 @@ inline DebugTopology effective_topology_for(uint32_t gfx_target_version, uint32_ effective.capability = (effective.capability & ~HSA_CAP_ASIC_REVISION_MASK) | ((revision_id << HSA_CAP_ASIC_REVISION_SHIFT) & HSA_CAP_ASIC_REVISION_MASK); + // Again after the override merge, not only in debug_topology_for(): a config + // that captured a real device's capability word carries that device's + // trap-debug bit, and the simulator must not inherit a claim it cannot honour. + if (!cwsr_layout_modelled_for_gc_ip_version( + gc_ip_version_for_gfx_target_version(gfx_target_version))) + effective.capability &= ~static_cast(HSA_CAP_TRAP_DEBUG_SUPPORT); return effective; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.cpp index 47e0007610ef..df528df9d02d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.cpp @@ -7,6 +7,7 @@ #include "rocjitsu/kmd/linux/remote_driver.h" #include "rocjitsu/kmd/linux/kfd_ioctl_utils.h" #include "rocjitsu/kmd/linux/rpc.h" +#include "util/unique_handle.h" #include #include @@ -127,21 +128,54 @@ Sysfs::GpuInfo gpu_info_from_rpc(const RpcGpuInfo &src) { return gpu; } -/// @brief Ceiling on the device count a snapshot request may reserve room for. +/// @brief Ceiling on the entry count a snapshot request may reserve room for. /// /// @details Two orders of magnitude above anything a KFD enumerates (the /// driver's own MAX_GPU_INSTANCE and libhsakmt's NUM_OF_SUPPORTED_GPUS are both /// 64), so it can never truncate a real answer, while keeping the reserved tail -/// at half a megabyte instead of the whole payload budget. -inline constexpr uint32_t kMaxSnapshotDevices = 4096; +/// at half a megabyte instead of the whole payload budget. The same ceiling +/// bounds the queue snapshot: a process with more than 4096 live queues has +/// exhausted the driver's own doorbell budget long before it gets here. +inline constexpr uint32_t kMaxSnapshotEntries = 4096; + +/// @brief The request fields shared by the two DBG_TRAP snapshot ops. +struct SnapshotFields { + // __u64/__u32 rather than uint64_t/uint32_t: these alias the uapi struct's + // own fields, and __u64 is unsigned long long where uint64_t is unsigned long. + __u64 *buf_ptr; + __u32 *count; + __u32 *entry_size; + uint32_t struct_size; +}; + +/// @brief Bind the snapshot request fields of @p dbg for its op. +/// +/// @details GET_DEVICE_SNAPSHOT and GET_QUEUE_SNAPSHOT differ only in which +/// sub-struct of kfd_ioctl_dbg_trap_args carries the caller's buffer, entry +/// count and stride, and in the entry struct the driver fills. Binding them in +/// one place lets the request clamp and the strided copy-back below serve both +/// ops instead of drifting into two divergent copies of the same reasoning. +/// +/// @p op is passed separately rather than read from @p dbg because the reply +/// path runs against an arg struct the daemon echoed back; the op that selects +/// the union member has to be the one *we* sent, not one a peer could vary. +/// +/// @pre @p op is GET_DEVICE_SNAPSHOT or GET_QUEUE_SNAPSHOT. +SnapshotFields snapshot_fields(kfd_ioctl_dbg_trap_args *dbg, uint32_t op) { + if (op == KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT) + return {&dbg->device_snapshot.snapshot_buf_ptr, &dbg->device_snapshot.num_devices, + &dbg->device_snapshot.entry_size, sizeof(kfd_dbg_device_info_entry)}; + return {&dbg->queue_snapshot.snapshot_buf_ptr, &dbg->queue_snapshot.num_queues, + &dbg->queue_snapshot.entry_size, sizeof(kfd_queue_snapshot_entry)}; +} /// @brief Clamp a DBG_TRAP device-snapshot request to a transmittable size. /// /// @details The snapshot buffer is pure ioctl output, so the request carries an -/// inline tail of @p num_devices * @p entry_size zero bytes purely to reserve -/// room for the daemon's reply. num_devices is caller-controlled, and callers -/// are entitled to oversize it: the uapi contract is that KFD fills only the -/// devices that exist and reports the true total back, so libhsakmt's +/// inline tail of @p count * @p entry_size zero bytes purely to reserve room +/// for the daemon's reply. The count is caller-controlled, and callers are +/// entitled to oversize it: the uapi contract is that KFD fills only the +/// entries that exist and reports the true total back, so libhsakmt's /// hsaKmtDbgGetDeviceDataCtx() just passes UINT32_MAX. Taken literally that /// reserves UINT32_MAX * sizeof(kfd_dbg_device_info_entry) bytes (120 B/entry, /// so ~480 GiB); the resize throws std::bad_alloc out of an interposed ioctl() @@ -149,40 +183,40 @@ inline constexpr uint32_t kMaxSnapshotDevices = 4096; /// /// Clamping the transmitted count keeps the ioctl's semantics rather than /// failing a request the kernel would have served: the daemon still reports the -/// true device total in num_devices(OUT), and the ceiling is far above any -/// device count a KFD can enumerate, so it cannot drop an entry the daemon +/// true total in the count(OUT) field, and the ceiling is far above any device +/// or queue count a KFD can enumerate, so it cannot drop an entry the daemon /// could have returned. /// -/// The ceiling is @ref kMaxSnapshotDevices rather than the transport's raw +/// The ceiling is @ref kMaxSnapshotEntries rather than the transport's raw /// capacity. Filling the whole payload budget would be correct but ruinous: at /// 120 B/entry it reserves ~16 MiB of zeros in the request and makes the daemon /// echo ~16 MiB back (rj_daemon replies with the buffer it received), i.e. ~32 /// MiB moved under rpc_mutex_ on every debugger attach to describe one GPU. /// -/// A zero return for a non-zero @p num_devices means not even one entry fits; -/// the caller must fail the ioctl rather than transmit the count, because -/// num_devices(IN) == 0 is the count-only probe the daemon answers with success. +/// A zero return for a non-zero @p count means not even one entry fits; the +/// caller must fail the ioctl rather than transmit the count, because +/// count(IN) == 0 is the count-only probe the daemon answers with success. /// -/// @returns the device count to transmit, whose tail is guaranteed to fit +/// @returns the entry count to transmit, whose tail is guaranteed to fit /// within @ref kMaxPayloadBytes alongside @p arg_size bytes of ioctl args. -uint32_t clamp_snapshot_devices(uint32_t num_devices, uint32_t entry_size, size_t arg_size) { +uint32_t clamp_snapshot_entries(uint32_t count, uint32_t entry_size, size_t arg_size) { // A zero stride reserves nothing whatever the count is, so pass the caller's // count through untouched. The driver does not reject a zero stride: its // per-entry copy_to_user() moves entry_size(OUT) == 0 bytes and succeeds, so // the call reports the device total and writes nothing // (DbgTrapDeviceSnapshotZeroStrideReportsCountAndWritesNothing pins that - // locally). num_devices(IN) is still what the driver clamps its fill count - // against, and it is echoed back as part of the request, so rewriting it to - // zero here would hand the daemon a different request than the caller made. + // locally). count(IN) is still what the driver clamps its fill count against, + // and it is echoed back as part of the request, so rewriting it to zero here + // would hand the daemon a different request than the caller made. if (entry_size == 0) - return num_devices; + return count; const size_t overhead = sizeof(RpcIoctlRequest) + arg_size; if (overhead >= kMaxPayloadBytes) return 0; const size_t max_entries = - std::min(kMaxSnapshotDevices, (kMaxPayloadBytes - overhead) / entry_size); - return static_cast(std::min(num_devices, max_entries)); + std::min(kMaxSnapshotEntries, (kMaxPayloadBytes - overhead) / entry_size); + return static_cast(std::min(count, max_entries)); } } // namespace @@ -233,6 +267,8 @@ RemoteDriver::~RemoteDriver() { if (fd >= 0) syscall(SYS_close, fd); } + if (kfd_marker_ != nullptr) + syscall(SYS_munmap, kfd_marker_, kfd_marker_size_); if (sock_ >= 0) syscall(SYS_close, sock_); if (shutdown_efd_ >= 0) @@ -341,9 +377,29 @@ int RemoteDriver::reissue_synthetic_kfd_fd() { int fd_min = static_cast(rl.rlim_cur) - 64; if (fd_min < 256) fd_min = 256; + // NOTE: the name here is deliberately NOT "/dev/kfd". Naming it that makes + // /proc//maps carry a second "/memfd:/dev/kfd (deleted)" line, which + // breaks gdb.rocm/core-no-read-special-files.exp -- that test parses + // `info proc mappings` for the one real /dev/kfd mapping and finds none once + // this decoy is present. InterposerDupTest.ProcMapsNamesRemoteKfdMarker + // asserts the opposite (that maps names /dev/kfd and never this marker); the + // two expectations are in direct conflict and the upstream ROCgdb test wins, + // so that unit test currently only passes on a daemon-backed run and needs a + // design decision about what the marker is actually for. auto raw_fd = static_cast(syscall(SYS_memfd_create, "rocjitsu_remote_kfd", MFD_CLOEXEC)); if (raw_fd < 0) return -1; + if (kfd_marker_ == nullptr) { + constexpr size_t kMarkerSize = 4096; + if (syscall(SYS_ftruncate, raw_fd, kMarkerSize) == 0) { + void *marker = reinterpret_cast( + syscall(SYS_mmap, nullptr, kMarkerSize, PROT_NONE, MAP_SHARED, raw_fd, 0)); + if (marker != MAP_FAILED) { + kfd_marker_ = marker; + kfd_marker_size_ = kMarkerSize; + } + } + } // Use the raw syscall, not fcntl(): this shared object exports an interposed // fcntl with default visibility, so an unqualified call would re-enter the // shim (reserve_dup_backend/untrack_dup, fd_mutex_) for a plain memfd dup. @@ -490,17 +546,22 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { uint64_t saved_device_ids_ptr = 0; uint64_t saved_dbg_rinfo_ptr = 0; uint32_t saved_dbg_rinfo_size = 0; + uint32_t saved_dbg_op = 0; uint64_t saved_dbg_snapshot_ptr = 0; - // The response overwrites num_devices/entry_size with the daemon's outputs, - // so the request's own count and stride have to be kept to reproduce the - // driver's strided write on copy-back. Together they are also the caller's - // declared buffer capacity. - uint32_t saved_dbg_snapshot_devices = 0; + // The response overwrites the count/entry_size pair with the daemon's + // outputs, so the request's own count and stride have to be kept to reproduce + // the driver's strided write on copy-back. Together they are also the + // caller's declared buffer capacity. + uint32_t saved_dbg_snapshot_count = 0; uint32_t saved_dbg_snapshot_stride = 0; // The stride actually put on the wire, which is the caller's clamped to the // struct the daemon fills. Entries arrive packed at this pitch and are // scattered out at the caller's, so the two cannot be conflated. uint32_t saved_dbg_snapshot_wire_stride = 0; + // SUSPEND/RESUME_QUEUES carry an inbound array of queue ids the daemon + // rewrites to its own tail, and report per-queue status back through it. + uint64_t saved_dbg_queue_array_ptr = 0; + uint32_t saved_dbg_queue_count = 0; if (has_embedded_pointers(request)) { switch (request) { case AMDKFD_IOC_WAIT_EVENTS: @@ -517,6 +578,7 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { break; case AMDKFD_IOC_DBG_TRAP: { auto *dbg = static_cast(arg); + saved_dbg_op = dbg->op; switch (dbg->op) { case KFD_IOC_DBG_TRAP_ENABLE: saved_dbg_rinfo_ptr = dbg->enable.rinfo_ptr; @@ -535,9 +597,33 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { if (dbg->device_snapshot.snapshot_buf_ptr == 0) return -EINVAL; saved_dbg_snapshot_ptr = dbg->device_snapshot.snapshot_buf_ptr; - saved_dbg_snapshot_devices = dbg->device_snapshot.num_devices; + saved_dbg_snapshot_count = dbg->device_snapshot.num_devices; saved_dbg_snapshot_stride = dbg->device_snapshot.entry_size; break; + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: + // Deliberately no null-buffer rejection here, unlike the device op + // above. The local path answers a null buffer with success when the + // process has no queues to report and only -EFAULT when it has some + // (SimulatedKfd::debug_queue_snapshot), and the client cannot know that + // count before it asks. The verdict is reconstructed on copy-back + // instead, from the queue total the daemon reports. + saved_dbg_snapshot_ptr = dbg->queue_snapshot.snapshot_buf_ptr; + saved_dbg_snapshot_count = dbg->queue_snapshot.num_queues; + saved_dbg_snapshot_stride = dbg->queue_snapshot.entry_size; + break; + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + saved_dbg_snapshot_ptr = dbg->query_exception_info.info_ptr; + saved_dbg_snapshot_count = 1; + saved_dbg_snapshot_stride = dbg->query_exception_info.info_size; + break; + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: + saved_dbg_queue_array_ptr = dbg->suspend_queues.queue_array_ptr; + saved_dbg_queue_count = dbg->suspend_queues.num_queues; + break; + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: + saved_dbg_queue_array_ptr = dbg->resume_queues.queue_array_ptr; + saved_dbg_queue_count = dbg->resume_queues.num_queues; + break; default: break; } @@ -588,12 +674,13 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { inline_size = std::min(static_cast(dbg->enable.rinfo_size), sizeof(kfd_runtime_info)); break; - case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: { + case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: { // Rewrite the transmitted count, not just the tail length: the daemon - // recomputes num_devices * entry_size and disconnects any client whose + // recomputes count * entry_size and disconnects any client whose // payload does not match it exactly (validate_ioctl_payload). Only the // serialized copy is edited — the caller's args keep the original - // request until the reply overwrites them with the true device total. + // request until the reply overwrites them with the true total. // // Transmit a compact stride rather than the caller's. entry_size(IN) is // documented as the caller's buffer stride and is allowed to exceed the @@ -604,25 +691,53 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { // produced would come back as success over an untouched buffer. The // daemon fills at this stride; the copy-back scatters each entry into // the caller's own wider slot. - const uint32_t wire_stride = - std::min(dbg->device_snapshot.entry_size, sizeof(kfd_dbg_device_info_entry)); - const uint32_t requested = dbg->device_snapshot.num_devices; - const uint32_t devices = clamp_snapshot_devices(requested, wire_stride, arg_size); + const SnapshotFields snap = snapshot_fields(dbg, dbg->op); + const uint32_t wire_stride = std::min(*snap.entry_size, snap.struct_size); + const uint32_t requested = *snap.count; + const uint32_t entries = clamp_snapshot_entries(requested, wire_stride, arg_size); // A single compact entry not fitting would mean kMaxPayloadBytes is // smaller than one struct; fail rather than degrade to the count probe. - if (devices == 0 && requested != 0 && wire_stride != 0) + if (entries == 0 && requested != 0 && wire_stride != 0) return -ENOMEM; - dbg->device_snapshot.num_devices = devices; - dbg->device_snapshot.entry_size = wire_stride; + *snap.count = entries; + *snap.entry_size = wire_stride; saved_dbg_snapshot_wire_stride = wire_stride; - inline_size = static_cast(devices) * wire_stride; + inline_size = static_cast(entries) * wire_stride; break; } + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + inline_size = dbg->query_exception_info.info_size; + break; + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: + inline_size = static_cast(dbg->suspend_queues.num_queues) * sizeof(uint32_t); + break; + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: + inline_size = static_cast(dbg->resume_queues.num_queues) * sizeof(uint32_t); + break; default: break; } - if (inline_size > 0) + // QUERY_EXCEPTION_INFO takes info_size straight from the caller, and + // SUSPEND/RESUME derive theirs from num_queues; none of the three is + // clamped the way snapshot requests are. Bound them by the same protocol + // ceiling the daemon enforces, before resize() and the memcpy above run: + // UINT32_MAX alone still admits a multi-gigabyte allocation, a + // std::bad_alloc, or a huge read from the caller's buffer, all of which + // happen before the daemon ever sees the frame and rejects it. + // + // Fail rather than clamp. The daemon recomputes the expected tail from + // the echoed args, so a clamped tail with an unclamped count is a + // mismatch and drops the connection. + const size_t payload_so_far = buf.size() - sizeof(RpcHeader); + if (payload_so_far >= kMaxPayloadBytes || inline_size > kMaxPayloadBytes - payload_so_far) + return -E2BIG; + if (inline_size > 0) { + const size_t inline_offset = buf.size(); buf.resize(buf.size() + inline_size); + if (saved_dbg_queue_array_ptr != 0) + std::memcpy(buf.data() + inline_offset, + reinterpret_cast(saved_dbg_queue_array_ptr), inline_size); + } break; } default: @@ -645,11 +760,35 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { // dbg_fd so the driver can wake the debugger when a wave stops — the same fd // the real kernel would receive through the ioctl. KFD_INVALID_FD (0xffffffff) // casts to -1 and is not sent. - int send_fd = -1; + int send_fds[3] = {-1, -1, -1}; + size_t num_send_fds = 0; + // Owned only for the duration of the send: SCM_RIGHTS installs the daemon's + // own copies, so ours are released on every path out of here, including the + // early returns below. + util::UniqueHandle target_mem_fd; + util::UniqueHandle target_proc_fd; if (request == AMDKFD_IOC_DBG_TRAP) { auto *dbg = static_cast(arg); - if (dbg->op == KFD_IOC_DBG_TRAP_ENABLE && static_cast(dbg->enable.dbg_fd) >= 0) - send_fd = static_cast(dbg->enable.dbg_fd); + if (dbg->op == KFD_IOC_DBG_TRAP_ENABLE && static_cast(dbg->enable.dbg_fd) >= 0) { + if (::fcntl(static_cast(dbg->enable.dbg_fd), F_GETFD) < 0) + return transport_errno(); + // The daemon cannot reach the debuggee's address space on its own: it is + // not the ptrace parent, so process_vm_readv/writev are refused. We are, + // so open the target's memory here and transfer the authorization along + // with the notifier. The directory fd pins the identity, so the daemon + // can tell a target that exited from one whose pid was reused. + const std::string proc_path = std::format("/proc/{}", dbg->pid); + target_proc_fd = + util::UniqueHandle(::open(proc_path.c_str(), O_RDONLY | O_DIRECTORY | O_CLOEXEC)); + if (!target_proc_fd) + return transport_errno(); + target_mem_fd = util::UniqueHandle(::openat(target_proc_fd.get(), "mem", O_RDWR | O_CLOEXEC)); + if (!target_mem_fd) + return transport_errno(); + send_fds[num_send_fds++] = static_cast(dbg->enable.dbg_fd); + send_fds[num_send_fds++] = target_mem_fd.get(); + send_fds[num_send_fds++] = target_proc_fd.get(); + } } // A send that fails without putting a byte on the wire is recoverable: the // daemon never saw a frame, so the stream is still aligned and the caller just @@ -657,11 +796,11 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { // daemon is left waiting on the rest of a frame that will never arrive, and // will parse our next request as its tail. Those two have to be told apart, // hence the byte counts. - if (send_fd >= 0) { + if (num_send_fds > 0) { // sendmsg() on a stream socket may accept only part of the buffer; the - // ancillary fd rides on the first byte, so a short send is a truncated frame - // with the descriptor already handed over. - const auto sent = rpc_send_msg(sock_, buf.data(), buf.size(), &send_fd, 1); + // ancillary fds ride on the first byte, so a short send is a truncated frame + // with the descriptors already handed over. + const auto sent = rpc_send_msg(sock_, buf.data(), buf.size(), send_fds, num_send_fds); if (sent > 0 && static_cast(sent) != buf.size()) return poison_stream(); if (sent <= 0) { @@ -747,15 +886,17 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { break; case AMDKFD_IOC_DBG_TRAP: { auto *dbg = static_cast(arg); - switch (dbg->op) { + switch (saved_dbg_op) { case KFD_IOC_DBG_TRAP_ENABLE: dbg->enable.rinfo_ptr = saved_dbg_rinfo_ptr; break; case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: - dbg->device_snapshot.snapshot_buf_ptr = saved_dbg_snapshot_ptr; - // num_devices and entry_size are inputs the request rewrote to the + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: { + const SnapshotFields snap = snapshot_fields(dbg, saved_dbg_op); + *snap.buf_ptr = saved_dbg_snapshot_ptr; + // The count and entry_size are inputs the request rewrote to the // compact wire values, and the daemon echoes back whatever it was - // sent. On success that echo is the answer (the device total and the + // sent. On success that echo is the answer (the true total and the // bytes filled), but on failure it would hand the caller our internal // values instead of leaving the inputs alone: libhsakmt's UINT32_MAX // probe comes back as the 4096 clamp and its stride as the struct @@ -763,9 +904,28 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { // (SimulatedKfd::debug_device_snapshot), so a failed op leaves both // fields exactly as the caller set them; match that. if (resp->result != 0) { - dbg->device_snapshot.num_devices = saved_dbg_snapshot_devices; - dbg->device_snapshot.entry_size = saved_dbg_snapshot_stride; + *snap.count = saved_dbg_snapshot_count; + *snap.entry_size = saved_dbg_snapshot_stride; + break; } + // The queue op does not reject a null output buffer on the request + // path, because whether one is required depends on the queue total + // only the driver knows. Now that the total is back, apply the local + // path's verdict: entries to report and nowhere to put them is + // -EFAULT, no entries is success (SimulatedKfd::debug_queue_snapshot). + if (saved_dbg_op == KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT && saved_dbg_snapshot_ptr == 0 && + saved_dbg_snapshot_count > 0 && *snap.count > 0) + resp->result = -EFAULT; + break; + } + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + dbg->query_exception_info.info_ptr = saved_dbg_snapshot_ptr; + break; + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: + dbg->suspend_queues.queue_array_ptr = saved_dbg_queue_array_ptr; + break; + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: + dbg->resume_queues.queue_array_ptr = saved_dbg_queue_array_ptr; break; default: break; @@ -798,7 +958,7 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { auto *dbg = static_cast(arg); void *dst = nullptr; size_t copy_len = 0; - switch (dbg->op) { + switch (saved_dbg_op) { case KFD_IOC_DBG_TRAP_ENABLE: // Only propagate runtime-info bytes on success; a failed op (e.g. // -EBADF from a rejected notifier fd) must not mutate caller memory @@ -809,37 +969,41 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { std::min(static_cast(dbg->enable.rinfo_size), extra)); } break; - case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: { + case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: { // Only propagate snapshot bytes on success; a failed op (e.g. -ENOSYS) // must not mutate caller memory or dereference the saved output // pointer. if (resp->result != 0) break; - // Belt and braces: the request path already rejects a null output - // buffer with -EINVAL, so this is unreachable. Keep it so the memcpy - // below can never run through a null pointer if that check moves. + // The device op's request path rejects a null output buffer with + // -EINVAL, and the queue op's reply path above turns a null with + // entries to report into -EFAULT. A null that reaches here is + // therefore a queue snapshot with nothing to report, which writes + // nothing anyway — but keep the guard so the memcpy below can never + // run through a null pointer if either check moves. if (saved_dbg_snapshot_ptr == 0) break; // Replay the driver's write pattern instead of bulk-copying the tail. - // amdkfd fills min(num_devices(IN), device total) entries, writing + // amdkfd fills min(count(IN), true total) entries, writing // entry_size(OUT) bytes at entry_size(IN) stride, and leaves the rest - // of the caller's buffer alone — both the entries past the device - // count and, when the caller's stride is wider than the current - // struct, the padding inside each entry. A bulk copy of the declared - // capacity would instead zero all of that (the request tail is sent - // empty, so the daemon fills only what it enumerates), diverging from - // what SimulatedKfd writes on the local path. It would also trust - // num_devices(IN) as a real allocation size, which callers are - // entitled to oversize. + // of the caller's buffer alone — both the entries past the total and, + // when the caller's stride is wider than the current struct, the + // padding inside each entry. A bulk copy of the declared capacity + // would instead zero all of that (the request tail is sent empty, so + // the daemon fills only what it enumerates), diverging from what + // SimulatedKfd writes on the local path. It would also trust + // count(IN) as a real allocation size, which callers are entitled to + // oversize. // - // num_devices(IN) is the caller's declared capacity in entries, so - // capping the loop at it is the same bound the driver applies; the - // per-entry `extra` test additionally refuses to read past the tail - // the daemon actually sent. + // count(IN) is the caller's declared capacity in entries, so capping + // the loop at it is the same bound the driver applies; the per-entry + // `extra` test additionally refuses to read past the tail the daemon + // actually sent. if (saved_dbg_snapshot_stride == 0 || saved_dbg_snapshot_wire_stride == 0) break; - const uint32_t entries = - std::min(saved_dbg_snapshot_devices, dbg->device_snapshot.num_devices); + const SnapshotFields snap = snapshot_fields(dbg, saved_dbg_op); + const uint32_t entries = std::min(saved_dbg_snapshot_count, *snap.count); // Two pitches: the tail is packed at the stride we transmitted, the // caller's buffer is laid out at the stride it declared. const size_t src_stride = saved_dbg_snapshot_wire_stride; @@ -848,9 +1012,8 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { // clamps it to the struct it actually fills, so apply the same bound // here: an inflated value would pull the neighbouring entries' bytes // into the padding the caller's wider stride leaves between entries. - const size_t written = std::min( - std::min(dbg->device_snapshot.entry_size, sizeof(kfd_dbg_device_info_entry)), - std::min(src_stride, dst_stride)); + const size_t written = std::min(std::min(*snap.entry_size, snap.struct_size), + std::min(src_stride, dst_stride)); // A zero-width entry writes nothing, so the loop has nothing to do — // and the `src + written > extra` bound below degenerates into a bare // offset test that lets a daemon-reported entry_size(OUT) of 0 spin @@ -861,13 +1024,30 @@ int RemoteDriver::send_ioctl(unsigned long request, void *arg) { auto *snapshot_out = reinterpret_cast(saved_dbg_snapshot_ptr); for (uint32_t i = 0; i < entries; ++i) { const size_t src = static_cast(i) * src_stride; - const size_t dst = static_cast(i) * dst_stride; + const size_t dst_offset = static_cast(i) * dst_stride; if (src + written > extra) break; - std::memcpy(snapshot_out + dst, payload.data() + arg_size + src, written); + std::memcpy(snapshot_out + dst_offset, payload.data() + arg_size + src, written); } break; } + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + if (resp->result == 0) { + dst = reinterpret_cast(saved_dbg_snapshot_ptr); + copy_len = std::min(static_cast(saved_dbg_snapshot_stride), extra); + } + break; + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: + // KFD returns a non-negative queue count on success and annotates + // every requested ID with ERROR/INVALID status bits in the same + // caller-owned array. + if (resp->result >= 0) { + dst = reinterpret_cast(saved_dbg_queue_array_ptr); + copy_len = + std::min(static_cast(saved_dbg_queue_count) * sizeof(uint32_t), extra); + } + break; default: break; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.h index 6567294a8cb9..dac2a95c88f5 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/remote_driver.h @@ -155,7 +155,9 @@ class RemoteDriver : public Driver { /// is set the connection is terminal and further ioctl/mmap/munmap calls fail /// with -EPROTO rather than returning bogus results from a poisoned stream. std::atomic protocol_failed_{false}; - int shutdown_efd_ = -1; ///< eventfd written by close() to wake WAIT_EVENTS pollers. + int shutdown_efd_ = -1; ///< eventfd written by close() to wake WAIT_EVENTS pollers. + void *kfd_marker_ = nullptr; ///< Non-readable mapping identifying /dev/kfd in proc maps. + size_t kfd_marker_size_ = 0; /// @brief Serializes all RPC send+recv pairs on sock_. /// @details ROCR is multithreaded — concurrent ioctl/mmap calls interleave diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/rj_daemon.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/rj_daemon.cpp index 90d86274b486..abb768175a61 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/rj_daemon.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/rj_daemon.cpp @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -85,14 +86,41 @@ bool validate_ioctl_payload(uint32_t command, const void *buffer, size_t buffer_ break; } case AMDKFD_IOC_DBG_TRAP: { + // Every op the client reserves an inline tail for has to appear here, or + // the exact-length test below rejects a well-formed request and the + // connection is dropped. Keep this in step with the tail sizes + // RemoteDriver::send_ioctl() computes and the pointers + // reconstruct_embedded_pointers() repoints (rj_vm.cpp) -- all three must + // agree on the same set of ops. const auto *args = static_cast(buffer); - if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { + switch (args->op) { + case KFD_IOC_DBG_TRAP_ENABLE: inline_size = std::min(static_cast(args->enable.rinfo_size), sizeof(kfd_runtime_info)); - } else if (args->op == KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT && - !checked_product(args->device_snapshot.num_devices, args->device_snapshot.entry_size, - &inline_size)) { - return false; + break; + case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: + if (!checked_product(args->device_snapshot.num_devices, args->device_snapshot.entry_size, + &inline_size)) + return false; + break; + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: + if (!checked_product(args->queue_snapshot.num_queues, args->queue_snapshot.entry_size, + &inline_size)) + return false; + break; + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + inline_size = args->query_exception_info.info_size; + break; + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: + if (!checked_product(args->suspend_queues.num_queues, sizeof(uint32_t), &inline_size)) + return false; + break; + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: + if (!checked_product(args->resume_queues.num_queues, sizeof(uint32_t), &inline_size)) + return false; + break; + default: + break; } break; } @@ -115,15 +143,33 @@ bool send_with_fd_exact(int socket, const void *data, size_t size, int fd) { rpc_send_exact(socket, static_cast(data) + bytes_sent, size - bytes_sent); } -bool receive_header_with_fd(int socket, RpcHeader *header, util::UniqueHandle *fd) { - int received_fds[1] = {-1}; - size_t received_fd_count = 1; +/// @brief The SCM_RIGHTS descriptors a client may attach to one request. +/// +/// @details DBG_TRAP ENABLE sends three: the debugger's notifier, and the +/// authorization the daemon needs to reach the debuggee's address space -- +/// /proc//mem, plus the /proc/ directory that pins the identity that +/// fd belongs to. Every other request sends at most the notifier. Ownership is +/// RAII, so descriptors the VM declines to adopt are released with the request +/// rather than leaked for the life of the connection. +struct ReceivedFds { + util::UniqueHandle notifier; + util::UniqueHandle target_mem; + util::UniqueHandle target_proc; +}; + +bool receive_header_with_fds(int socket, RpcHeader *header, ReceivedFds *fds) { + int received_fds[3] = {-1, -1, -1}; + size_t received_fd_count = std::size(received_fds); ssize_t header_bytes = 0; do { header_bytes = rpc_recv_msg(socket, header, sizeof(*header), received_fds, &received_fd_count); } while (header_bytes < 0 && errno == EINTR); if (received_fd_count > 0) - fd->reset(received_fds[0]); + fds->notifier.reset(received_fds[0]); + if (received_fd_count > 1) + fds->target_mem.reset(received_fds[1]); + if (received_fd_count > 2) + fds->target_proc.reset(received_fds[2]); if (header_bytes <= 0) return false; const size_t bytes_received = static_cast(header_bytes); @@ -194,12 +240,12 @@ class ClientSession { try { while (!stop.stop_requested() && !daemon_->stop_requested.load(std::memory_order_acquire)) { RpcHeader header{}; - util::UniqueHandle input_fd; - if (!receive_header_with_fd(client_fd_, &header, &input_fd)) + ReceivedFds input_fds; + if (!receive_header_with_fds(client_fd_, &header, &input_fds)) break; if (header.reserved != 0 || - handle_request(header, input_fd) == RequestDisposition::Disconnect) { + handle_request(header, input_fds) == RequestDisposition::Disconnect) { break; } } @@ -209,25 +255,25 @@ class ClientSession { } private: - RequestDisposition handle_request(const RpcHeader &header, util::UniqueHandle &input_fd) { + RequestDisposition handle_request(const RpcHeader &header, ReceivedFds &input_fds) { switch (header.opcode) { case RPC_HANDSHAKE: - return handle_handshake(header, input_fd); + return handle_handshake(header, input_fds); case RPC_CLOSE: - return handle_close(header, input_fd); + return handle_close(header, input_fds); case RPC_MMAP: - return handle_mmap(header, input_fd); + return handle_mmap(header, input_fds); case RPC_MUNMAP: - return handle_munmap(header, input_fd); + return handle_munmap(header, input_fds); case RPC_IOCTL: - return handle_ioctl(header, input_fd); + return handle_ioctl(header, input_fds); default: return RequestDisposition::Disconnect; } } - RequestDisposition handle_handshake(const RpcHeader &header, const util::UniqueHandle &input_fd) { - if (process_id_ != 0 || header.payload_bytes != 0 || input_fd.get() >= 0) + RequestDisposition handle_handshake(const RpcHeader &header, const ReceivedFds &input_fds) { + if (process_id_ != 0 || header.payload_bytes != 0 || input_fds.notifier) return RequestDisposition::Disconnect; if (rj_vm_device_open(daemon_->vm, client_pid_, &process_id_) != ROCJITSU_STATUS_SUCCESS) { @@ -275,8 +321,8 @@ class ClientSession { return sent ? RequestDisposition::Continue : RequestDisposition::Disconnect; } - RequestDisposition handle_close(const RpcHeader &header, const util::UniqueHandle &input_fd) { - if (process_id_ == 0 || header.payload_bytes != 0 || input_fd.get() >= 0) + RequestDisposition handle_close(const RpcHeader &header, const ReceivedFds &input_fds) { + if (process_id_ == 0 || header.payload_bytes != 0 || input_fds.notifier) return RequestDisposition::Disconnect; close_device(); @@ -287,8 +333,8 @@ class ClientSession { return RequestDisposition::Disconnect; } - RequestDisposition handle_mmap(const RpcHeader &header, const util::UniqueHandle &input_fd) { - if (process_id_ == 0 || header.payload_bytes != sizeof(RpcMmapRequest) || input_fd.get() >= 0) { + RequestDisposition handle_mmap(const RpcHeader &header, const ReceivedFds &input_fds) { + if (process_id_ == 0 || header.payload_bytes != sizeof(RpcMmapRequest) || input_fds.notifier) { return RequestDisposition::Disconnect; } RpcMmapRequest request{}; @@ -326,9 +372,9 @@ class ClientSession { return sent ? RequestDisposition::Continue : RequestDisposition::Disconnect; } - RequestDisposition handle_munmap(const RpcHeader &header, const util::UniqueHandle &input_fd) { + RequestDisposition handle_munmap(const RpcHeader &header, const ReceivedFds &input_fds) { if (process_id_ == 0 || header.payload_bytes != sizeof(RpcMunmapRequest) || - input_fd.get() >= 0) { + input_fds.notifier) { return RequestDisposition::Disconnect; } RpcMunmapRequest request{}; @@ -344,7 +390,7 @@ class ClientSession { : RequestDisposition::Disconnect; } - RequestDisposition handle_ioctl(const RpcHeader &header, util::UniqueHandle &input_fd) { + RequestDisposition handle_ioctl(const RpcHeader &header, ReceivedFds &input_fds) { if (process_id_ == 0 || header.payload_bytes > kMaxPayloadBytes || header.payload_bytes < sizeof(RpcIoctlRequest)) { return RequestDisposition::Disconnect; @@ -365,11 +411,19 @@ class ClientSession { command.buf = arguments; command.buf_size = request->args_bytes; command.shared_handle = -1; - command.in_handle = input_fd.get(); + command.in_handle = input_fds.notifier.get(); + command.in_mem_handle = input_fds.target_mem.get(); + // Borrowed, not adopted: the driver dups it if the session needs to keep it + // (rj_vm.cpp passes it by value), so this side always closes its own copy. + command.in_proc_handle = input_fds.target_proc.get(); if (rj_vm_execute_as(daemon_->vm, process_id_, &command) != ROCJITSU_STATUS_SUCCESS) return RequestDisposition::Disconnect; + // The VM clears each handle it took ownership of; drop ours to match, so + // RAII does not close a descriptor the debug session now owns. if (command.in_handle < 0) - static_cast(input_fd.release()); + static_cast(input_fds.notifier.release()); + if (command.in_mem_handle < 0) + static_cast(input_fds.target_mem.release()); if (command.buf_size > available_arguments) return RequestDisposition::Disconnect; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.cpp index 0efd73947f38..5820cce09eef 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.cpp @@ -3,10 +3,14 @@ #include "rocjitsu/kmd/linux/simulated_kfd.h" #include "rocjitsu/kmd/linux/amdgpu_properties.h" +#include "rocjitsu/kmd/linux/cwsr.h" #include "rocjitsu/kmd/linux/kfd_ioctl_utils.h" #include "rocjitsu/kmd/linux/kfd_topology.h" #include "rocjitsu/kmd/linux/libc_passthrough.h" #include "rocjitsu/vm/amdgpu/command_processor.h" +#include "rocjitsu/vm/amdgpu/compute_unit.h" +#include "rocjitsu/vm/amdgpu/gpu_memory.h" +#include "rocjitsu/vm/amdgpu/wavefront.h" #include "rocjitsu/base/rj_compiler.h" RJ_DIAGNOSTIC_PUSH @@ -21,20 +25,38 @@ RJ_DIAGNOSTIC_POP #include #include #include +#include +#include #include #include #include #include #include #include +#include #include +#include #include #include #include #include +#include #ifndef MADV_POPULATE_WRITE #define MADV_POPULATE_WRITE 23 #endif +// pidfd_open(2) landed in Linux 5.3. The build hosts are older than their +// kernels here -- gcc-toolset-13 on the CI base image ships sanitized headers +// that predate it -- so the wrapper and even __NR_pidfd_open can be missing +// while the running kernel implements it fine. 434 is the number on every +// architecture ROCm targets; the syscall was added after new numbers began +// being allocated identically across arches. +#ifndef SYS_pidfd_open +#ifdef __NR_pidfd_open +#define SYS_pidfd_open __NR_pidfd_open +#else +#define SYS_pidfd_open 434 +#endif +#endif #include #include #include @@ -108,6 +130,114 @@ template int safe_fcntl(int fd, int cmd, Args... args) { return libc_passthrough().fcntl(fd, cmd, args...); } +int pidfd_is_exited(int pidfd) { + pollfd pfd{pidfd, POLLIN, 0}; + const int rc = ::poll(&pfd, 1, 0); + if (rc < 0) + return -errno; + return rc == 1 && (pfd.revents & (POLLIN | POLLHUP)) ? 1 : 0; +} + +/// @brief Report whether the process behind @p procfd has exited but not been +/// reaped. +/// +/// @details A pidfd stays readable for a zombie, so pidfd_is_exited() cannot +/// tell a live debuggee from one that has already run to completion. The state +/// character in /proc//stat can. It sits after the last ')' because the +/// comm field is parenthesised and may itself contain spaces and parentheses. +/// +/// @retval 1 The target is a zombie (Z) or dead (X). +/// @retval 0 The target is still running. +/// @retval <0 Negative errno; the state could not be determined. +int procfd_is_zombie(int procfd) { + const int stat_fd = ::openat(procfd, "stat", O_RDONLY | O_CLOEXEC); + if (stat_fd < 0) + return errno == ENOENT ? 1 : -errno; + char buffer[4096]; + const ssize_t bytes = ::read(stat_fd, buffer, sizeof(buffer) - 1); + const int read_error = errno; + ::close(stat_fd); + if (bytes < 0) + return -read_error; + buffer[bytes] = '\0'; + const char *name_end = std::strrchr(buffer, ')'); + if (name_end == nullptr || name_end[1] != ' ' || name_end[2] == '\0') + return -EIO; + return name_end[2] == 'Z' || name_end[2] == 'X'; +} + +int pin_process_identity(pid_t pid, util::UniqueHandle &pidfd, util::UniqueHandle &procfd) { + const int raw_pidfd = static_cast(::syscall(SYS_pidfd_open, pid, 0)); + if (raw_pidfd < 0) + return errno == ESRCH ? -ESRCH : -errno; + pidfd = util::UniqueHandle(raw_pidfd); + + const std::string proc_path = "/proc/" + std::to_string(pid); + const int raw_procfd = ::open(proc_path.c_str(), O_RDONLY | O_DIRECTORY | O_CLOEXEC); + if (raw_procfd < 0) { + const int open_error = errno; + const int exited = pidfd_is_exited(pidfd.get()); + return exited == 1 ? -ESRCH : (exited < 0 ? exited : -open_error); + } + procfd = util::UniqueHandle(raw_procfd); + + const int exited = pidfd_is_exited(pidfd.get()); + return exited == 0 ? 0 : (exited == 1 ? -ESRCH : exited); +} + +/// @brief Read TracerPid through a procfs directory pinned to the pidfd identity. +int tracer_pid_of(const util::UniqueHandle &pidfd, const util::UniqueHandle &procfd, + const SimulatedKfd::DebugIdentityValidationHook &validation_hook, + pid_t &tracer_pid) { + int exited = pidfd_is_exited(pidfd.get()); + if (exited != 0) + return exited == 1 ? -ESRCH : exited; + + util::UniqueHandle status_fd(::openat(procfd.get(), "status", O_RDONLY | O_CLOEXEC)); + if (status_fd.get() < 0) { + const int open_error = errno; + const int exited = pidfd_is_exited(pidfd.get()); + return exited == 1 ? -ESRCH : (exited < 0 ? exited : -open_error); + } + + std::string status; + char buffer[4096]; + for (;;) { + const ssize_t count = ::read(status_fd.get(), buffer, sizeof(buffer)); + if (count > 0) { + status.append(buffer, static_cast(count)); + continue; + } + if (count == 0) + break; + if (errno == EINTR) + continue; + return -errno; + } + + constexpr std::string_view kKey = "TracerPid:"; + tracer_pid = 0; + size_t offset = 0; + while (offset < status.size()) { + const size_t end = status.find('\n', offset); + const std::string_view line(status.data() + offset, + (end == std::string::npos ? status.size() : end) - offset); + if (line.substr(0, kKey.size()) == kKey) { + tracer_pid = static_cast(std::strtol(line.data() + kKey.size(), nullptr, 10)); + break; + } + if (end == std::string::npos) + break; + offset = end + 1; + } + + if (validation_hook) + validation_hook(); + + exited = pidfd_is_exited(pidfd.get()); + return exited == 0 ? 0 : (exited == 1 ? -ESRCH : exited); +} + } // namespace std::shared_ptr SimulatedKfd::find_process(uint32_t process_id) const { @@ -182,7 +312,11 @@ void SimulatedKfd::setup_topology(const config::KfdDeviceConfig &dev, uint32_t n setup_topology(gpu_info_from_config(dev, num_xcc)); } -SimulatedKfd::SimulatedKfd(SoC &soc, bool daemon_mode) : daemon_mode_(daemon_mode) { +SimulatedKfd::SimulatedKfd(SoC &soc, bool daemon_mode, + DebugIdentityValidationHook debug_identity_validation_hook) + : daemon_mode_(daemon_mode), + debug_identity_validation_hook_(std::move(debug_identity_validation_hook)), + debug_session_reaper_([this](std::stop_token stop) { reap_exited_debug_sessions(stop); }) { // Resolve the real libc entry points once, up front and single-threaded, so no // passthrough call site ever triggers a first-time dlsym under a per-process // lock. Idempotent: a no-op if the interposer already resolved the table. @@ -190,8 +324,11 @@ SimulatedKfd::SimulatedKfd(SoC &soc, bool daemon_mode) : daemon_mode_(daemon_mod gpus_.push_back({&soc, 0, false, {}}); } -SimulatedKfd::SimulatedKfd(std::vector socs, std::vector gpu_ids, bool daemon_mode) - : daemon_mode_(daemon_mode) { +SimulatedKfd::SimulatedKfd(std::vector socs, std::vector gpu_ids, bool daemon_mode, + DebugIdentityValidationHook debug_identity_validation_hook) + : daemon_mode_(daemon_mode), + debug_identity_validation_hook_(std::move(debug_identity_validation_hook)), + debug_session_reaper_([this](std::stop_token stop) { reap_exited_debug_sessions(stop); }) { libc_passthrough().resolve(); for (size_t i = 0; i < socs.size(); ++i) gpus_.push_back({socs[i], i < gpu_ids.size() ? gpu_ids[i] : socs[i]->gpu_id(), false, {}}); @@ -212,6 +349,9 @@ const SimulatedKfd::GpuDevice *SimulatedKfd::find_gpu(uint32_t gpu_id) const { } SimulatedKfd::~SimulatedKfd() { + debug_session_reaper_.request_stop(); + debug_session_reaper_.join(); + std::vector pids; { std::lock_guard lk(process_mutex_); @@ -219,6 +359,7 @@ SimulatedKfd::~SimulatedKfd() { for (auto &[id, proc] : processes_) pids.push_back(id); } + // close() only tears a process down on the LAST open reference (release_open() // returns true at zero); a process opened more than once (dup/daemon reuse) // would otherwise survive with its allocations, queues, and CP callbacks still @@ -230,6 +371,59 @@ SimulatedKfd::~SimulatedKfd() { } } +void SimulatedKfd::reap_exited_debug_sessions(std::stop_token stop) { + std::unique_lock lock(debug_sessions_mutex_); + while (!stop.stop_requested()) { + if (debug_sessions_.empty()) { + debug_sessions_cv_.wait(lock, stop, [&] { return !debug_sessions_.empty(); }); + } else { + debug_sessions_cv_.wait_for(lock, stop, std::chrono::milliseconds(10), [] { return false; }); + } + if (stop.stop_requested()) + break; + std::vector>> released; + for (auto it = debug_sessions_.begin(); it != debug_sessions_.end();) { + if (pidfd_is_exited(it->second.debugger_pidfd.get()) == 1) { + // The debugger is gone and will never ack; release any inferior + // blocked in the RUNTIME_ENABLE handshake for it. + cancel_runtime_handshake(it->first); + // Resolve the debuggee now, while the session's pinned identity still + // vouches for the pid. After the erase the number alone could name a + // process that merely reused it. + released.emplace_back(it->first, find_process_by_client_pid(it->first)); + it = debug_sessions_.erase(it); + } else if (pidfd_is_exited(it->second.target_pidfd.get()) == 1) { + if (!it->second.target_exited) { + if (auto target = find_process_by_client_pid(it->first)) + revoke_target_mem_routing(target->process_id()); + it->second.owned_dbg_fd.reset(); + it->second.target_mem_fd.reset(); + it->second.dbg_fd = -1; + it->second.enabled = false; + it->second.target_exited = true; + } + ++it; + } else { + ++it; + } + } + // A crashed debugger must not strand the inferior. Erasing the session only + // stops new debug traffic; the waves it left stopped, the closed queue + // gates and the target-memory routing all have to be undone too, exactly as + // an explicit detach does. Done outside debug_sessions_mutex_ because the + // release takes CU wave-state locks in the opposite order to the engine + // thread. + if (!released.empty()) { + lock.unlock(); + // The shared_ptr in `released` is what keeps proc alive across the + // unlocked release; release_debuggee_state only borrows it. + for (auto &[pid, proc] : released) + release_debuggee_state(pid, proc.get()); + lock.lock(); + } + } +} + void SimulatedKfd::setup_topology(const Sysfs::GpuInfo &gpu) { if (!gpus_.empty()) gpus_[0].gpu_id = gpu.gpu_id; @@ -302,12 +496,27 @@ void SimulatedKfd::init_command_processors_locked() { continue; if (!g.soc) continue; + // The WAVES field the CP writes into compute_tmpring_size must be a + // multiple of the per-XCC shader-engine count, or rocdbgapi disables + // private memory access outright (architecture.cpp, + // gfx9_architecture_t::scratch_memory_region). It recovers that count from + // the topology we publish: os_driver_kfd.cpp derives + // shader_engine_count = array_count * num_xcc / simd_arrays_per_engine and + // then divides by xcc_count, which inverts Sysfs::GpuInfo's + // array_count_per_xcc() exactly back to num_shader_engines. Read that same + // field here rather than recomputing a quotient, so the value the CP rounds + // to and the divisor rocdbgapi applies cannot drift apart. + const uint32_t scratch_wave_divisor = + i < gpu_infos_.size() ? std::max(1u, gpu_infos_[i].num_shader_engines) : 1u; + g.soc->for_each_cp([scratch_wave_divisor](amdgpu::CommandProcessor *cp) { + cp->set_scratch_wave_divisor(scratch_wave_divisor); + }); // Same source as the apertures GET_PROCESS_APERTURES_NEW and the DBG_TRAP // device snapshot advertise: what the shaders translate LDS/scratch against // must be what the runtime and the debugger were told. const kfd_process_device_apertures ap = gpu_apertures(static_cast(i)); g.soc->set_apertures(ap.lds_base, ap.lds_limit, ap.scratch_base, ap.scratch_limit); - g.soc->for_each_cp([this](amdgpu::CommandProcessor *cp) { + g.soc->for_each_cp([this, i](amdgpu::CommandProcessor *cp) { cp->set_interrupt_callback([this](uint32_t process_id, uint32_t event_id) { std::lock_guard ilk(interrupt_mutex_); auto it = event_dispatch_.find(process_id); @@ -336,6 +545,31 @@ void SimulatedKfd::init_command_processors_locked() { [this](uint32_t process_id, uint64_t gpu_va, size_t size) -> bool { return allocate_scratch_backing(process_id, gpu_va, size); }); + for (auto *cu : cp->compute_units()) { + const uint32_t gpu_ordinal = static_cast(i); + cu->set_trap_handler_resolver([this, gpu_ordinal](const amdgpu::Wavefront &wf) { + return resolve_trap_handler(wf, gpu_ordinal); + }); + cu->set_sendmsg_handler([this](amdgpu::Wavefront &wf, uint32_t message) { + return on_wave_sendmsg(wf, message); + }); + cu->set_trap_completion_handler( + [this](amdgpu::Wavefront &wf) { on_wave_trap_complete(wf); }); + cu->set_single_step_handler( + [this](amdgpu::Wavefront &wf) { return on_wave_single_step_complete(wf); }); + cu->set_watchpoint_handler([this](amdgpu::Wavefront &wf, uint64_t address, uint32_t bytes, + bool is_write, bool is_atomic) { + return on_wave_watchpoint(wf, address, bytes, is_write, is_atomic); + }); + cu->set_illegal_inst_handler( + [this](amdgpu::Wavefront &wf) { return on_wave_illegal_instruction(wf); }); + cu->set_alu_exception_handler( + [this](amdgpu::Wavefront &wf) { return on_wave_alu_exception(wf); }); + cu->set_memory_violation_handler( + [this](amdgpu::Wavefront &wf, uint64_t address, bool is_write) { + return on_wave_memory_violation(wf, address, is_write); + }); + } }); g.cps_initialized = true; } @@ -452,6 +686,16 @@ uint32_t SimulatedKfd::open_process(pid_t client_pid) { init_command_processors_locked(); } + if (client_pid > 0) { + std::lock_guard debug_lock(debug_sessions_mutex_); + auto session = debug_sessions_.find(client_pid); + if (session != debug_sessions_.end() && session->second.target_mem_fd.get() >= 0) { + for (auto &g : gpus_) + if (auto *mem = g.soc ? g.soc->memory() : nullptr) + mem->set_process_mem_fd(pid, session->second.target_mem_fd.get()); + } + } + return pid; } @@ -562,6 +806,45 @@ int SimulatedKfd::close(uint32_t process_id) { // paths; op_mutex_ alone does not cover them. std::lock_guard op_lock(proc.op_mutex_); + // Linux kfd_release() only drops the file's kfd_process reference; + // kfd_process_notifier_release_internal() disables debug when the process mm + // actually exits. Preserve live sessions across a /dev/kfd close, but reap + // targets whose pinned identity has exited. + std::vector>> released; + { + std::lock_guard debug_lock(debug_sessions_mutex_); + for (auto it = debug_sessions_.begin(); it != debug_sessions_.end();) { + if (pidfd_is_exited(it->second.debugger_pidfd.get()) == 1) { + // The debugger is gone and will never ack; release any inferior + // blocked in the RUNTIME_ENABLE handshake for it. + cancel_runtime_handshake(it->first); + // Resolve the debuggee now, while the session's pinned identity still + // vouches for the pid. After the erase the number alone could name a + // process that merely reused it. + released.emplace_back(it->first, find_process_by_client_pid(it->first)); + it = debug_sessions_.erase(it); + } else if (pidfd_is_exited(it->second.target_pidfd.get()) == 1) { + if (auto target = find_process_by_client_pid(it->first)) + revoke_target_mem_routing(target->process_id()); + it->second.owned_dbg_fd.reset(); + it->second.target_mem_fd.reset(); + it->second.dbg_fd = -1; + it->second.enabled = false; + it->second.target_exited = true; + ++it; + } else { + ++it; + } + } + } + // Same obligation as the background reaper: erasing the session only stops + // new debug traffic, so a debugger that died before this close still has to + // have its inferior's waves resumed, queue gates reopened and target-memory + // routing revoked. Done after the debug_sessions_mutex_ scope above, because + // this takes CU wave-state locks and the engine thread takes those first. + for (auto &[pid, proc_ref] : released) + release_debuggee_state(pid, proc_ref.get()); + // Set the closing flag first, under op_mutex_, so the dispatch_ioctl guard sees // it before any state is dismantled. proc.event_state_.notify_closing(); @@ -587,6 +870,7 @@ int SimulatedKfd::close(uint32_t process_id) { std::lock_guard alk(proc.alloc_mutex_); queue_ids.assign(proc.active_queue_ids_.begin(), proc.active_queue_ids_.end()); proc.active_queue_ids_.clear(); + proc.queue_snapshot_map_.clear(); if (trace_enabled) leaked_handles.reserve(proc.allocations_.size()); @@ -692,14 +976,16 @@ int SimulatedKfd::ioctl(unsigned long request, void *arg) { return ioctl(local_process_id_, request, arg); } -int SimulatedKfd::ioctl(uint32_t process_id, unsigned long request, void *arg) { +int SimulatedKfd::ioctl(uint32_t process_id, unsigned long request, void *arg, int *target_mem_fd, + int target_proc_fd) { auto proc = find_process(process_id); if (!proc) return -ESRCH; - return dispatch_ioctl(*proc, request, arg); + return dispatch_ioctl(*proc, request, arg, target_mem_fd, target_proc_fd); } -int SimulatedKfd::dispatch_ioctl(KfdProcess &proc, unsigned long request, void *arg) { +int SimulatedKfd::dispatch_ioctl(KfdProcess &proc, unsigned long request, void *arg, + int *target_mem_fd, int target_proc_fd) { util::Logger::driver("IOCTL pid=", proc.process_id(), " ", LinuxKfd::ioctl_name(request)); unsigned long dispatch_request = canonical_ioctl_request(request); @@ -707,6 +993,14 @@ int SimulatedKfd::dispatch_ioctl(KfdProcess &proc, unsigned long request, void * if (dispatch_request == AMDKFD_IOC_WAIT_EVENTS) return wait_events_ioctl(proc, arg); + // RUNTIME_ENABLE blocks too: when a debugger is attached it waits for that + // debugger to acknowledge EC_PROCESS_RUNTIME. Holding op_mutex_ across that + // wait would serialize the ack behind it whenever the debugger and the target + // share a KfdProcess (self-debug, and daemon clients that reuse one pid), so + // it takes the lock itself around the state mutation only. + if (dispatch_request == AMDKFD_IOC_RUNTIME_ENABLE) + return runtime_enable_ioctl(proc, arg); + std::lock_guard op_lock(proc.op_mutex_); // A concurrent close() may have snapshotted-then-erased this process and be // tearing it down under op_mutex_. ioctl() holds only a shared_ptr (no open @@ -760,10 +1054,10 @@ int SimulatedKfd::dispatch_ioctl(KfdProcess &proc, unsigned long request, void * return set_memory_policy_ioctl(proc, arg); case AMDKFD_IOC_AVAILABLE_MEMORY: return get_available_memory_ioctl(proc, arg); - case AMDKFD_IOC_RUNTIME_ENABLE: - return runtime_enable_ioctl(proc, arg); + // RUNTIME_ENABLE is handled before op_mutex_ above (it blocks on the + // debugger handshake), so it never reaches this switch. case AMDKFD_IOC_DBG_TRAP: - return debug_trap_ioctl(proc, arg); + return debug_trap_ioctl(proc, arg, target_mem_fd, target_proc_fd); case AMDKFD_IOC_SET_SCRATCH_BACKING_VA: { auto *a = static_cast(arg); uint32_t ord = gpu_ordinal(a->gpu_id); @@ -781,11 +1075,8 @@ int SimulatedKfd::dispatch_ioctl(KfdProcess &proc, unsigned long request, void * auto *a = static_cast(arg); uint32_t ord = gpu_ordinal(a->gpu_id); { - // Held under process_mutex_ for symmetry with SET_SCRATCH_BACKING_VA and - // to be race-free once the trap handler is wired into the SoC. NOTE: as of - // now trap_tba_addr/trap_tma_addr have no reader anywhere (the CP does not - // yet consume them), so this lock currently guards against a non-existent - // concurrent access — kept for forward-compatibility. + // Trap entry resolves these fields on the engine thread while ioctls may + // update them, so publish and consume them under process_mutex_. std::lock_guard plk(process_mutex_); proc.gpu(ord).trap_tba_addr = a->tba_addr; proc.gpu(ord).trap_tma_addr = a->tma_addr; @@ -1527,9 +1818,10 @@ int SimulatedKfd::create_queue_ioctl(KfdProcess &proc, void *arg) { if (!gpu || !gpu->soc) return -EINVAL; - // Select the target CP before reserving any per-process state, so a null CP - // cannot leave a doorbell offset / queue-id bookkeeping entry orphaned. - auto *target_cp = gpu->soc->assign_queue_cp(); + // Queue IDs are process-local and start at one. Equivalent runtime queues in + // different processes therefore share XCD resources while each process still + // distributes additional queues across the device. + auto *target_cp = gpu->soc->assign_queue_cp(proc.next_queue_id_ - 1); if (!target_cp) return -EINVAL; @@ -1542,6 +1834,7 @@ int SimulatedKfd::create_queue_ioctl(KfdProcess &proc, void *arg) { // ioctl can observe the partially-registered queue in the window between the // unlock and register_queue(). amdgpu::HwQueue hw{}; + uint32_t queue_id = 0; { std::lock_guard lk(proc.alloc_mutex_); @@ -1557,7 +1850,7 @@ int SimulatedKfd::create_queue_ioctl(KfdProcess &proc, void *arg) { amdgpu::Mtype::UC); } - uint32_t queue_id = proc.next_queue_id_++; + queue_id = proc.next_queue_id_++; uint32_t ord = gpu_ordinal(args->gpu_id); auto &gs = proc.gpu(ord); uint32_t db_offset; @@ -1612,6 +1905,14 @@ int SimulatedKfd::create_queue_ioctl(KfdProcess &proc, void *arg) { // amd_queue_t base: write_pointer_address points to write_dispatch_id. if (!hw.is_sdma) hw.queue_desc_va = args->write_pointer_address - offsetof(amd_queue_t, write_dispatch_id); + if (!hw.is_sdma && args->ctx_save_restore_address != 0) { + constexpr uint32_t kErrorReasonOffset = 6 * sizeof(uint32_t); + constexpr uint32_t kErrorEventIdOffset = kErrorReasonOffset + sizeof(uint64_t); + hw.exception_status_va = target_cp->read_process_memory64( + args->ctx_save_restore_address + kErrorReasonOffset, proc.process_id()); + hw.exception_event_id = static_cast(target_cp->read_process_memory64( + args->ctx_save_restore_address + kErrorEventIdOffset, proc.process_id())); + } if (hw.is_sdma && !daemon_mode_) { auto *wptr = reinterpret_cast(args->write_pointer_address); auto *rptr = reinterpret_cast(args->read_pointer_address); @@ -1635,6 +1936,24 @@ int SimulatedKfd::create_queue_ioctl(KfdProcess &proc, void *arg) { // Register with the CP OUTSIDE alloc_mutex_ (see note above). target_cp->register_queue(std::move(hw)); + + // Publish debug metadata only after CP registration. A cross-process debugger + // does not hold the target's op_mutex_, so publishing it earlier could expose + // a queue that the command processor cannot service yet. + { + std::lock_guard lk(proc.alloc_mutex_); + proc.queue_snapshot_map_[queue_id] = { + .ring_base_address = args->ring_base_address, + .write_pointer_address = args->write_pointer_address, + .read_pointer_address = args->read_pointer_address, + .ctx_save_restore_address = args->ctx_save_restore_address, + .ctx_save_restore_area_size = args->ctx_save_restore_size, + .ring_size = args->ring_size, + .queue_type = args->queue_type, + .gpu_id = args->gpu_id, + .exception_status = KFD_EC_MASK(EC_QUEUE_NEW), + }; + } return 0; } @@ -1644,8 +1963,16 @@ int SimulatedKfd::update_queue_ioctl(KfdProcess &proc, void *arg) { if (g.soc) g.soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { cp->update_queue(args->queue_id, proc.process_id(), args->ring_base_address, - args->ring_size); + args->ring_size, args->queue_percentage); }); + { + std::lock_guard lk(proc.alloc_mutex_); + if (auto it = proc.queue_snapshot_map_.find(args->queue_id); + it != proc.queue_snapshot_map_.end()) { + it->second.ring_base_address = args->ring_base_address; + it->second.ring_size = args->ring_size; + } + } return 0; } @@ -1659,6 +1986,7 @@ int SimulatedKfd::destroy_queue_ioctl(KfdProcess &proc, void *arg) { { std::lock_guard lk(proc.alloc_mutex_); std::erase(proc.active_queue_ids_, args->queue_id); + proc.queue_snapshot_map_.erase(args->queue_id); auto it = proc.queue_doorbell_map_.find(args->queue_id); if (it != proc.queue_doorbell_map_.end()) { auto &gs = proc.gpu(it->second.gpu_ordinal); @@ -2022,28 +2350,75 @@ int SimulatedKfd::svm_ioctl(KfdProcess &proc, void *arg) { int SimulatedKfd::runtime_enable_ioctl(KfdProcess &proc, void *arg) { auto *args = static_cast(arg); - std::lock_guard lock(proc.runtime_mutex_); - - if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK) { - if (proc.runtime_state_.pending) - return -EBUSY; - bool has_queues = [&] { - std::lock_guard alock(proc.alloc_mutex_); - return !proc.active_queue_ids_.empty(); - }(); - if (!proc.runtime_state_.enabled && has_queues) - return -EEXIST; - proc.runtime_state_.enabled = true; - proc.runtime_state_.pending = false; - proc.runtime_state_.mode_mask = args->mode_mask; - proc.runtime_state_.capabilities_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; - proc.runtime_state_.r_debug = args->r_debug; - args->capabilities_mask = proc.runtime_state_.capabilities_mask; - return 0; + const bool enabling = (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK) != 0; + // Whether a debugger was already attached when the runtime came up, decided + // under the same lock that DBG_TRAP_ENABLE uses to publish a session. + bool notify_debugger = false; + // Same decision for the disable direction, which reports the same way. + bool notify_disable = false; + { + // Scoped so neither lock is held across the handshake wait below. + std::lock_guard op_lock(proc.op_mutex_); + // debug_sessions_mutex_ orders this against DBG_TRAP_ENABLE, which holds it + // while it reads runtime_state_ to fill in the runtime_info it returns. + // Exactly one of the two has to take responsibility for telling the + // debugger the runtime is up: either ENABLE observes enabled==true and + // reports it (rocdbgapi then calls runtime_enable() straight from its + // attach path, process.cpp), or this side observes the session and raises + // EC_PROCESS_RUNTIME. Without a common lock both can read the other's + // pre-state -- ENABLE reports DISABLED while this side sees no session -- + // and NEITHER fires -- the debugger then waits for an event that is never + // coming and never learns the runtime came up. + // + // Closing this did NOT measurably change gdb.rocm/multi-inferior-stress.exp, + // which fails for a different reason (see below); it is fixed here because + // the window is real on its own terms, not because it cured that test. + // Taking it here also cannot double-report: whichever side takes the lock + // second observes the first, and rocdbgapi treats a runtime_state that does + // not toggle as a fatal "spurious runtime exception". + std::lock_guard session_lock(debug_sessions_mutex_); + std::lock_guard lock(proc.runtime_mutex_); + if (enabling) { + if (proc.runtime_state_.pending) + return -EBUSY; + bool has_queues = [&] { + std::lock_guard alock(proc.alloc_mutex_); + return !proc.active_queue_ids_.empty(); + }(); + if (!proc.runtime_state_.enabled && has_queues) + return -EEXIST; + proc.runtime_state_.enabled = true; + proc.runtime_state_.pending = false; + proc.runtime_state_.mode_mask = args->mode_mask; + proc.runtime_state_.capabilities_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + proc.runtime_state_.r_debug = args->r_debug; + args->capabilities_mask = proc.runtime_state_.capabilities_mask; + auto session = debug_sessions_.find(proc.client_pid()); + notify_debugger = session != debug_sessions_.end() && session->second.enabled; + } else { + // Report the !disabled -> disabled transition. rocdbgapi needs it to stop + // driving the queues of a process whose runtime has gone away: those ops + // are gated on the runtime being enabled and answer -EPERM, which it + // turns into a fatal os_driver::resume_queues failure and GDB into an + // internal error (gdb.rocm/multi-inferior-stress.exp). Only report a real + // transition -- a second disable is not one, and rocdbgapi rejects an + // event whose runtime_state has not moved as spurious. Decided against + // the session table under the same lock the enable branch uses, so an + // undebugged process exit does not re-take debug_sessions_mutex_ in the + // callee just to discover there is nobody to tell. + auto session = debug_sessions_.find(proc.client_pid()); + notify_disable = proc.runtime_state_.enabled && session != debug_sessions_.end() && + session->second.enabled; + proc.runtime_state_ = KfdProcess::RuntimeState{}; + args->capabilities_mask = 0; + } } - proc.runtime_state_ = KfdProcess::RuntimeState{}; - args->capabilities_mask = 0; + // Ordered after the state reset above so that the debugger's follow-up + // QUERY_EXCEPTION_INFO reads the new state, and outside the lock scope + // because the handshake blocks. + if (notify_debugger || notify_disable) + runtime_debugger_handshake(proc.client_pid(), /*enabling=*/notify_debugger); return 0; } @@ -2057,50 +2432,1465 @@ std::shared_ptr SimulatedKfd::find_process_by_client_pid(pid_t pid) return nullptr; } -// in real kernel, amd/amdkfd/kfd_chardev.c kfd_ioctl_set_debug_trap -int SimulatedKfd::debug_trap_ioctl(KfdProcess &caller, void *arg) { - auto *args = static_cast(arg); - util::Logger::driver("DBG_TRAP pid=", args->pid, " op=", args->op); +namespace { + +kmd::CwsrWaveState build_cwsr_wave_state(amdgpu::Wavefront &wf) { + kmd::CwsrWaveState state; + const uint32_t raw_status = wf.status_raw(); + state.pc = wf.pc; + // A wave frozen inside the trap handler has the HANDLER's EXEC live, not the + // application's: the handler runs with its own mask and parks 0x80000000 (and + // then a doorbell id) in EXEC_LO around MSG_GET_DOORBELL. Publishing that + // makes the debugger report every lane active, which inverts `lane apply + // -active/-inactive` (gdb.rocm/lane-info.exp). trap_saved_exec_ holds the + // interrupted value for the whole handler, so un-shadow it here, as the + // STATUS field below does with trap_saved_status(). + // + // in_trap_handler() is the predicate for both, and it opens at handler entry + // rather than at MSG_INTERRUPT because the doorbell park happens on the way + // there. It closes at s_rfe, which puts the interrupted values back, so from + // then on the live registers are the application's again. + // + // The record is not write-only -- apply_cwsr_to_wave() feeds it back on + // resume -- so un-shadowing here is only safe because that path shadows in + // the other direction under the same predicate: a debugger edit to EXEC is + // written to trap_saved_exec_, which the handler's s_rfe installs, instead of + // overwriting the mask a mid-flight handler is still running under. + state.exec = wf.in_trap_handler() ? wf.trap_saved_exec() : wf.exec(); + state.vcc = wf.vcc(); + state.flat_scratch = wf.scratch_base(); + state.m0 = wf.m0(); + state.mode = wf.mode_raw(); + state.trapsts = wf.trapsts(); + // Whether the application was already halted when it trapped outlives the + // handler: trap_saved_status_ still describes the interrupted wave after + // s_rfe, and trap_interrupt_sent() is the flag that says a handler produced + // this stop. in_trap_handler() has to be part of the predicate too, or the + // two halves of the published STATUS come from different registers between + // trap entry and MSG_INTERRUPT -- the body from trap_saved_status_ and the + // HALT bit from the handler's live one. apply_cwsr_to_wave() recombines them + // into a word that never existed on the wave, so an identity round-trip in + // that window rewrites the application's saved HALT with the handler's. + const bool handler_context = wf.in_trap_handler() || wf.trap_interrupt_sent(); + state.saved_status_halt = ((handler_context ? wf.trap_saved_status() : raw_status) >> 13) & 1u; + state.wave_stopped = wf.debug_halted(); + // The published STATUS shadows on the narrower predicate, the same one EXEC + // uses: only while the handler is actually running is the live register the + // handler's rather than the application's. Once s_rfe has run, the live value + // is the application's again and is what the debugger should see. + const uint32_t application_status = wf.in_trap_handler() ? wf.trap_saved_status() : raw_status; + state.status = + state.wave_stopped ? application_status | (1u << 13) : application_status & ~(1u << 13); + state.trap_id = wf.trap_id(); + state.wave_id = wf.debug_wave_id(); + state.group_ids = wf.wg_coord(); + state.wave_in_group = wf.wave_in_group(); + state.queue_packet_id = wf.aql_packet_id() & 0x1FFFFFFu; + state.scratch_scoreboard_id = wf.scratch_scoreboard_id(); + state.spi_ttmps_setup = true; + state.num_sgprs = wf.num_sgprs(); + state.num_vgprs = wf.num_vgprs(); + + state.sgprs.resize(state.num_sgprs); + for (uint32_t s = 0; s < state.num_sgprs; ++s) + state.sgprs[s] = wf.debug_read_sgpr(s); + // The CWSR record's VGPR stride is wave64-shaped (cwsr.cpp kVgprLaneBytes) + // whatever the wave size is, but the physical register only has wf_size() + // lanes -- a wave32 VectorReg<32> is exactly 32 wide, so reading lanes 32-63 + // runs off it into the neighbouring register. Read the live lanes and leave + // the rest of the wave64-shaped slot at the zero resize() already wrote; the + // restore path is bounded by wf_size() too and never looks at them. + state.vgprs.resize(static_cast(state.num_vgprs) * 64); + const uint32_t live_lanes = wf.wf_size(); + for (uint32_t r = 0; r < state.num_vgprs; ++r) + for (uint32_t lane = 0; lane < live_lanes; ++lane) + state.vgprs[static_cast(r) * 64 + lane] = wf.debug_read_vgpr(r, lane); + state.lds.resize(wf.lds_size()); + if (!state.lds.empty()) + static_cast(wf.lds()).read(wf.lds_base(), state.lds.data(), + static_cast(state.lds.size())); + return state; +} + +} // namespace + +void SimulatedKfd::raise_debug_event(const std::shared_ptr &proc, uint32_t queue_id, + uint32_t gpu_id, uint64_t exception_mask) { + if (!proc) + return; + uint64_t report_mask = exception_mask; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(queue_id); + if (queue != proc->queue_snapshot_map_.end()) { + queue->second.exception_status |= exception_mask; + report_mask |= queue->second.exception_status & KFD_EC_MASK(EC_QUEUE_NEW); + } + } + std::lock_guard lk(debug_events_mutex_); + auto &queue = debug_events_[proc->client_pid()][queue_id]; + queue.gpu_id = gpu_id; + queue.mask |= report_mask; +} + +bool SimulatedKfd::serialize_queue_debug_waves(uint32_t process_id, uint32_t queue_id, + uint32_t gpu_id, uint64_t ctx_base, + uint32_t ctx_size) { + auto *gpu = find_gpu(gpu_id); + if (!gpu || !gpu->soc || ctx_base == 0) + return false; + + // Never publish a record shaped for the wrong architecture. Handlers ask + // debug_stop_publishable() before claiming a stop, so reaching here on an + // unmodelled part means a caller skipped the gate; refuse rather than hand + // rocm-dbgapi an image it would decode against its own layout. + if (!kmd::cwsr_layout_modelled(gpu->soc->arch())) + return false; + + std::vector waves; + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + for (auto *cu : cp->compute_units()) { + cu->with_wave_state_locked([&] { + for (uint32_t i = 0; i < cu->num_wf_slots(); ++i) { + auto *wave = cu->wf(i); + if (wave->debug_stopped() && wave->process_id() == process_id && + wave->queue_id() == queue_id) + waves.push_back(build_cwsr_wave_state(*wave)); + } + }); + } + }); + if (waves.empty()) + return false; + + std::sort(waves.begin(), waves.end(), [](const auto &lhs, const auto &rhs) { + if (lhs.queue_packet_id != rhs.queue_packet_id) + return lhs.queue_packet_id < rhs.queue_packet_id; + if (lhs.group_ids != rhs.group_ids) + return lhs.group_ids < rhs.group_ids; + return lhs.wave_in_group < rhs.wave_in_group; + }); + auto same_group = [](const auto &lhs, const auto &rhs) { + return lhs.queue_packet_id == rhs.queue_packet_id && lhs.group_ids == rhs.group_ids; + }; + for (size_t index = 0; index < waves.size(); ++index) { + waves[index].is_first_in_group = index == 0 || !same_group(waves[index], waves[index - 1]); + waves[index].is_last_in_group = + index + 1 == waves.size() || !same_group(waves[index], waves[index + 1]); + if (!waves[index].is_first_in_group) + waves[index].lds.clear(); + } + auto *memory = gpu->soc->memory(); + auto proc = find_process(process_id); + if (!proc) + return false; + util::UniqueHandle target_mem = duplicate_debug_target_mem(proc->client_pid()); + bool publish_ok = true; + const auto layout = kmd::serialize_queue_cwsr_bulk( + ctx_base, ctx_size, waves, [&](uint64_t address, std::span bytes) { + if (target_mem.get() < 0) { + memory->write_block(address, bytes, process_id); + return; + } + const ssize_t written = + pwrite(target_mem.get(), bytes.data(), bytes.size(), static_cast(address)); + if (written != static_cast(bytes.size())) { + publish_ok = false; + util::Logger::warn("CWSR target write failed: addr=0x", std::hex, address, + " pid=", std::dec, proc->client_pid(), " rc=", written, + " errno=", errno); + } + }); + if (!layout.ok || !publish_ok) + return false; + + uint64_t oldest_packet = UINT64_MAX; + for (const auto &wave : waves) + oldest_packet = std::min(oldest_packet, wave.queue_packet_id); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(queue_id); + if (queue == proc->queue_snapshot_map_.end()) + return false; + read_pointer = queue->second.read_pointer_address; + write_pointer = queue->second.write_pointer_address; + } + if (read_pointer != 0 && write_pointer != 0 && + oldest_packet < memory->read64(write_pointer, process_id)) + memory->write64(read_pointer, oldest_packet, process_id); + return true; +} + +void SimulatedKfd::on_wave_trap_complete(amdgpu::Wavefront &wave) { + const uint32_t process_id = wave.process_id(); + const uint32_t queue_id = wave.queue_id(); + auto proc = find_process(process_id); + if (!proc) + return; + const pid_t target_pid = proc->client_pid(); + + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(target_pid); + if (session == debug_sessions_.end() || !session->second.enabled) + return; + } + + uint64_t ctx_base = 0; + uint32_t gpu_id = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(queue_id); + if (queue == proc->queue_snapshot_map_.end()) + return; + ctx_base = queue->second.ctx_save_restore_address; + gpu_id = queue->second.gpu_id; + } + if (ctx_base == 0) + return; + // The wave is already halted here by the handler's own STATUS.HALT, so there + // is no stop to decline -- but waking a debugger that can never be given a + // record only strands it. resolve_trap_handler() also withholds the debug + // flag on such a part, so a cooperating handler never gets this far; one that + // raises STATUS.HALT regardless still would. + if (!debug_stop_publishable(gpu_id)) + return; + + // A trap interrupt is wave-local: hardware reports it without waiting for + // every peer in the queue to stop. The debugger's ensuing SUSPEND_QUEUES + // request publishes the authoritative full-queue CWSR snapshot. + notify_debug_event(proc, queue_id, gpu_id); +} + +std::optional +SimulatedKfd::resolve_trap_handler(const amdgpu::Wavefront &wave, uint32_t gpu_ordinal) { + std::shared_ptr proc; + uint64_t tba = 0; + uint64_t tma = 0; + { + std::lock_guard lk(process_mutex_); + auto proc_it = processes_.find(wave.process_id()); + if (proc_it == processes_.end() || gpu_ordinal >= proc_it->second->gpu_state_.size()) + return std::nullopt; + proc = proc_it->second; + tba = proc->gpu(gpu_ordinal).trap_tba_addr; + tma = proc->gpu(gpu_ordinal).trap_tma_addr; + } + if (tba == 0) + return std::nullopt; + + bool debug_enabled = false; + { + std::lock_guard debug_lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(proc->client_pid()); + debug_enabled = session != debug_sessions_.end() && session->second.enabled; + } + // Do not tell the trap handler a debugger is attached on a part whose stops + // could never be published; the handler would raise STATUS.HALT and wait for + // a debugger that can never read it. + if (debug_enabled && gpu_ordinal < gpus_.size() && + !debug_stop_publishable(gpus_[gpu_ordinal].gpu_id)) + debug_enabled = false; + return amdgpu::ComputeUnitCore::TrapHandlerConfig{tba, tma, debug_enabled}; +} + +bool SimulatedKfd::on_wave_sendmsg(amdgpu::Wavefront &wave, uint32_t message) { + constexpr uint32_t kMessageIdMask = 0xFu; + constexpr uint32_t kMessageInterrupt = 1; + constexpr uint32_t kMessageGetDoorbell = 10; + const uint32_t message_id = message & kMessageIdMask; + + auto proc = find_process(wave.process_id()); + if (!proc) + return false; + + if (message_id == kMessageGetDoorbell) { + std::lock_guard lk(proc->alloc_mutex_); + auto doorbell = proc->queue_doorbell_map_.find(wave.queue_id()); + if (doorbell == proc->queue_doorbell_map_.end()) + return false; + const uint32_t doorbell_id = (doorbell->second.doorbell_offset / sizeof(uint64_t)) & 0x3FFu; + // The handler sets EXEC_LO[31] before issuing MSG_GET_DOORBELL and polls + // until hardware clears it. Return the 10-bit ID with the pending bit clear. + wave.set_exec((wave.exec() & 0xFFFFFFFF00000000ULL) | doorbell_id); + return true; + } + + if (message_id != kMessageInterrupt || !wave.in_trap_handler()) + return false; + + // CWSR publication is deferred until s_rfe applies the handler's STATUS.HALT. + return true; +} + +bool SimulatedKfd::debug_stop_publishable(uint32_t gpu_id) { + auto *gpu = find_gpu(gpu_id); + if (gpu == nullptr || gpu->soc == nullptr) + return false; + // The codec reproduces the gfx9.4 CWSR layout only (kmd/linux/cwsr.h), and + // the differences elsewhere are not confined to one field -- the control + // stack, the COMPUTE_RELAUNCH bits, the wave64 VGPR stride, the SGPR alias + // slots and the dispatch-identity TTMPs all move. rocm-dbgapi would decode + // the image against its own layout and act on whatever it read. + // + // Asked here, before the stop, rather than refused at DBG_TRAP_ENABLE: every + // errno that path can return except ESRCH and EALREADY becomes + // AMD_DBGAPI_STATUS_ERROR, which rocm-dbgapi turns into a [[noreturn]] + // fatal_error, so refusing there aborts the debugger instead of declining. + // Declining cleanly is the topology's job (HSA_CAP_TRAP_DEBUG_SUPPORT), and + // that surface is deliberately kept identical to the real KFD driver. + if (kmd::cwsr_layout_modelled(gpu->soc->arch())) + return true; + if (!gpu->cwsr_layout_warned) { + gpu->cwsr_layout_warned = true; + util::Logger::warn( + "wave stops not published on gpu_id=", gpu_id, + ": no CWSR record layout is modelled for arch=", static_cast(gpu->soc->arch()), + "; GPU debugging is supported on gfx942/gfx950 only"); + } + return false; +} + +bool SimulatedKfd::report_wave_stopped(const std::shared_ptr &proc, uint32_t queue_id, + uint32_t gpu_id, uint64_t ctx_base, uint32_t ctx_size, + uint64_t exception_mask) { + // Serialization must succeed before the debugger is woken. raise_debug_event + // latches per-queue exception status and queues an event the debugger will + // answer with SUSPEND_QUEUES; without a record that request can only come + // back as a queue error, and the wave stays halted with nothing able to + // resume it. The stop itself cannot be deferred until after serialization -- + // the serializer selects waves by debug_stopped() -- so the caller undoes it. + if (!serialize_queue_debug_waves(proc->process_id(), queue_id, gpu_id, ctx_base, ctx_size)) + return false; + notify_debug_event(proc, queue_id, gpu_id, exception_mask); + return true; +} + +void SimulatedKfd::notify_debug_event(const std::shared_ptr &proc, uint32_t queue_id, + uint32_t gpu_id, uint64_t exception_mask) { + const pid_t target_pid = proc->client_pid(); + raise_debug_event(proc, queue_id, gpu_id, exception_mask); + + // Duplicate under the session lock so DISABLE/reaping cannot close and reuse + // the descriptor, then perform notifier I/O without holding a driver lock. + util::UniqueHandle notifier; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(target_pid); + if (session != debug_sessions_.end() && session->second.dbg_fd >= 0 && + (session->second.exception_enable_mask & exception_mask) != 0) + notifier = util::UniqueHandle(safe_fcntl(session->second.dbg_fd, F_DUPFD_CLOEXEC, 0)); + } + if (notifier.get() >= 0) { + const uint64_t one = 1; + [[maybe_unused]] const ssize_t written = ::write(notifier.get(), &one, sizeof(one)); + } +} + +bool SimulatedKfd::on_wave_single_step_complete(amdgpu::Wavefront &wave) { + auto proc = find_process(wave.process_id()); + if (!proc) + return false; + uint64_t ctx_base = 0; + uint32_t gpu_id = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(wave.queue_id()); + if (queue == proc->queue_snapshot_map_.end()) + return false; + ctx_base = queue->second.ctx_save_restore_address; + gpu_id = queue->second.gpu_id; + } + if (ctx_base == 0) + return false; + if (!debug_stop_publishable(gpu_id)) { + // Clear single-step even while declining. The compute unit discards this + // callback's result and re-enters it for as long as the flag is set, so + // returning false without clearing it spins on every instruction. + wave.set_debug_single_step(false); + return false; + } + wave.set_debug_single_step(false); + wave.debug_trap(0); + // gfx9.4 reports completed single-step through TRAPSTS.TRAP_AFTER_INST. This + // is the public stop-reason bit rocm-dbgapi consumes before the next resume. + constexpr uint32_t kTrapAfterInstMask = 1u << 25; + wave.set_trapsts(wave.trapsts() | kTrapAfterInstMask); + // Single-step completion is wave-specific. Report it even if another wave + // in the queue is running; rocm-dbgapi will suspend the queue before reading + // its CWSR state. Deferring until every peer stops can lose the event forever + // when a peer runs to normal completion without entering a debug callback. + // Like hardware's trap interrupt, notification does not itself save the + // queue. The debugger's ensuing SUSPEND_QUEUES request publishes one stable, + // authoritative CWSR snapshot instead of redundantly serializing every + // resident wave here first. + notify_debug_event(proc, wave.queue_id(), gpu_id); + return true; +} + +bool SimulatedKfd::on_wave_watchpoint(amdgpu::Wavefront &wave, uint64_t address, uint32_t bytes, + bool is_write, bool is_atomic) { + auto proc = find_process(wave.process_id()); + if (!proc) + return false; + uint32_t matched_slots = 0; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(proc->client_pid()); + if (session == debug_sessions_.end() || !session->second.enabled) + return false; + // The watch modes are not disjoint, so an access can satisfy more than one + // of them: NONREAD is documented as "write or atomic operations only" + // (kfd_ioctl.h, and rocdbgapi's os_driver.h maps the STORE_AND_RMW + // watchpoint kind a plain `(gdb) watch` requests onto it), and ALL matches + // everything. Hand the set of modes this access triggers to the session + // rather than a single mode, so a write watch still fires on an atomic + // read-modify-write. KfdProcess deliberately does not include kfd_ioctl.h, + // so the mode semantics stay here, on the side of the boundary that owns + // the KFD ABI. + const uint32_t matching_modes = + (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL) | + (is_atomic ? (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC) | + (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD) + : is_write ? (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD) + : (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ)); + matched_slots = session->second.matching_address_watch_slots(address, bytes, matching_modes); + } + if (matched_slots == 0) + return false; + + uint64_t ctx_base = 0; + uint32_t ctx_size = 0; + uint32_t gpu_id = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(wave.queue_id()); + if (queue == proc->queue_snapshot_map_.end()) + return false; + ctx_base = queue->second.ctx_save_restore_address; + ctx_size = queue->second.ctx_save_restore_area_size; + gpu_id = queue->second.gpu_id; + } + if (ctx_base == 0) + return false; + if (!debug_stop_publishable(gpu_id)) + return false; + + static constexpr uint32_t kTrapstsBits[] = {1u << 7, 1u << 12, 1u << 13, 1u << 14}; + constexpr uint32_t kModeExcpEnAddrWatch = 1u << 19; + const auto saved = wave.debug_stop_state(); + uint32_t trapsts = wave.trapsts(); + for (uint32_t slot = 0; slot < KfdProcess::DebugSession::kMaxAddressWatches; ++slot) + if ((matched_slots & (uint32_t{1} << slot)) != 0) + trapsts |= kTrapstsBits[slot]; + wave.set_trapsts(trapsts); + wave.set_mode_raw(wave.mode_raw() | kModeExcpEnAddrWatch); + wave.debug_trap(0); + if (!report_wave_stopped(proc, wave.queue_id(), gpu_id, ctx_base, ctx_size)) { + wave.restore_debug_stop_state(saved); + return false; + } + return true; +} + +bool SimulatedKfd::on_wave_illegal_instruction(amdgpu::Wavefront &wave) { + auto proc = find_process(wave.process_id()); + if (!proc) + return false; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(proc->client_pid()); + if (session == debug_sessions_.end() || !session->second.enabled) + return false; + } + uint64_t ctx_base = 0; + uint32_t ctx_size = 0; + uint32_t gpu_id = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(wave.queue_id()); + if (queue == proc->queue_snapshot_map_.end()) + return false; + ctx_base = queue->second.ctx_save_restore_address; + ctx_size = queue->second.ctx_save_restore_area_size; + gpu_id = queue->second.gpu_id; + } + if (ctx_base == 0) + return false; + if (!debug_stop_publishable(gpu_id)) + return false; + constexpr uint32_t kTrapstsIllegalInst = 1u << 11; + const auto saved = wave.debug_stop_state(); + wave.set_trapsts(wave.trapsts() | kTrapstsIllegalInst); + wave.set_fatal_exception_pending(true); + wave.debug_trap(0); + if (!report_wave_stopped(proc, wave.queue_id(), gpu_id, ctx_base, ctx_size, + KFD_EC_MASK(EC_QUEUE_WAVE_ILLEGAL_INSTRUCTION))) { + wave.restore_debug_stop_state(saved); + return false; + } + return true; +} + +bool SimulatedKfd::on_wave_memory_violation(amdgpu::Wavefront &wave, uint64_t, bool) { + auto proc = find_process(wave.process_id()); + if (!proc) + return false; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(proc->client_pid()); + if (session == debug_sessions_.end() || !session->second.enabled) + return false; + } + uint64_t ctx_base = 0; + uint32_t ctx_size = 0; + uint32_t gpu_id = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(wave.queue_id()); + if (queue == proc->queue_snapshot_map_.end()) + return false; + ctx_base = queue->second.ctx_save_restore_address; + ctx_size = queue->second.ctx_save_restore_area_size; + gpu_id = queue->second.gpu_id; + } + if (ctx_base == 0) + return false; + if (!debug_stop_publishable(gpu_id)) + return false; + constexpr uint32_t kTrapstsXnackError = 1u << 28; + const auto saved = wave.debug_stop_state(); + wave.set_trapsts(wave.trapsts() | kTrapstsXnackError); + wave.debug_trap(0); + if (!report_wave_stopped(proc, wave.queue_id(), gpu_id, ctx_base, ctx_size, + KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION))) { + wave.restore_debug_stop_state(saved); + return false; + } + return true; +} + +bool SimulatedKfd::on_wave_alu_exception(amdgpu::Wavefront &wave) { + auto proc = find_process(wave.process_id()); + if (!proc) + return false; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(proc->client_pid()); + if (session == debug_sessions_.end() || !session->second.enabled) + return false; + } + uint64_t ctx_base = 0; + uint32_t ctx_size = 0; + uint32_t gpu_id = 0; + { + std::lock_guard lk(proc->alloc_mutex_); + auto queue = proc->queue_snapshot_map_.find(wave.queue_id()); + if (queue == proc->queue_snapshot_map_.end()) + return false; + ctx_base = queue->second.ctx_save_restore_address; + ctx_size = queue->second.ctx_save_restore_area_size; + gpu_id = queue->second.gpu_id; + } + if (ctx_base == 0) + return false; + if (!debug_stop_publishable(gpu_id)) + return false; + const auto saved = wave.debug_stop_state(); + wave.set_fatal_exception_pending(true); + wave.debug_trap(0); + if (!report_wave_stopped(proc, wave.queue_id(), gpu_id, ctx_base, ctx_size, + KFD_EC_MASK(EC_QUEUE_WAVE_MATH_ERROR))) { + wave.restore_debug_stop_state(saved); + return false; + } + return true; +} + +void SimulatedKfd::release_debuggee_state(pid_t target_pid, KfdProcess *target_proc) { + // Everything a session imposed on its inferior, undone in one place so that + // explicit detach and debugger death cannot drift apart. Callers have already + // erased the session and must not hold debug_sessions_mutex_ here: this takes + // CU wave-state locks, and the engine thread takes those first and then + // debug_sessions_mutex_ from its trap/watchpoint callbacks, so holding both + // in this order closes an AB-BA cycle against a wave that is trapping. + { + std::lock_guard event_lock(debug_events_mutex_); + debug_events_.erase(target_pid); + } + + // Nothing below has a debuggee to release; the event purge above was the + // whole job. Returning here keeps the rest free of repeated null tests. + if (target_proc == nullptr) { + release_debug_checks_if_last_session(); + return; + } + + std::vector> queues; + { + std::lock_guard alloc_lock(target_proc->alloc_mutex_); + for (auto &[queue_id, queue] : target_proc->queue_snapshot_map_) { + queue.exception_status = 0; + queues.emplace_back(queue_id, queue.gpu_id); + } + } + + for (const auto &[queue_id, gpu_id] : queues) { + auto *gpu = find_gpu(gpu_id); + if (!gpu || !gpu->soc) + continue; + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + cp->set_queue_debug_suspended(queue_id, target_proc->process_id(), false); + for (auto *cu : cp->compute_units()) { + bool wake = false; + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + auto *wave = cu->wf(slot); + if (wave->is_halted() || wave->process_id() != target_proc->process_id() || + wave->queue_id() != queue_id || wave->fatal_exception_pending()) + continue; + wave->set_debug_single_step(false); + wave->set_debug_halted(false); + wave->set_debug_suspended(false); + // The architectural half of the same stop. s_sendmsghalt raises + // STATUS.HALT and s_rfe consults it on the way out of the handler, + // so leaving it set outlives the session: the wave would re-halt at + // the handler return with no debugger left to resume it, and the + // queue would never drain. + wave->set_status_halt(false); + wave->set_self_halted(false); + wake = true; + } + }); + if (wake) + cu->schedule_work_async(); + } + }); + } + + revoke_target_mem_routing(target_proc->process_id()); + release_debug_checks_if_last_session(); +} + +void SimulatedKfd::revoke_target_mem_routing(uint32_t process_id) { + for (auto &g : gpus_) + if (auto *mem = g.soc ? g.soc->memory() : nullptr) + mem->set_process_mem_fd(process_id, -1); +} + +void SimulatedKfd::release_debug_checks_if_last_session() { + // Debug checks stay on only while some session still wants them. Read the + // answer under the lock, then reach into the CUs after releasing it -- the + // whole point of this function running unlocked is that debug_sessions_mutex_ + // is never held while touching a CU. + bool no_sessions_left = false; + { + std::lock_guard lk(debug_sessions_mutex_); + no_sessions_left = debug_sessions_.empty(); + } + if (no_sessions_left) + set_debug_active_on_all_cus(false); +} + +void SimulatedKfd::set_debug_active_on_all_cus(bool active) { + for (auto &gpu : gpus_) { + if (!gpu.soc) + continue; + gpu.soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + for (auto *cu : cp->compute_units()) + cu->set_debug_active(active); + }); + } +} + +util::UniqueHandle SimulatedKfd::duplicate_debug_target_mem(pid_t target_pid) const { + std::lock_guard lock(debug_sessions_mutex_); + auto session = debug_sessions_.find(target_pid); + if (session == debug_sessions_.end() || session->second.target_mem_fd.get() < 0) + return {}; + return util::UniqueHandle(safe_fcntl(session->second.target_mem_fd.get(), F_DUPFD_CLOEXEC, 0)); +} + +void SimulatedKfd::apply_cwsr_to_wave(amdgpu::Wavefront &wave, const kmd::CwsrWaveState &state) { + constexpr uint32_t kModeDebugEnMask = 1u << 11; + constexpr uint32_t kStatusHaltMask = amdgpu::Wavefront::kStatusHaltMask; + wave.pc = state.pc; + // Mirror of the un-shadowing in build_cwsr_wave_state(): while a handler is + // mid-flight the published EXEC is the interrupted application mask, so the + // value coming back belongs to the shadow, not to the live register the + // handler is executing under. s_rfe installs it when the handler returns. + if (wave.in_trap_handler()) + wave.set_trap_saved_exec(state.exec); + else + wave.set_exec(state.exec); + wave.set_vcc(state.vcc); + wave.set_m0(state.m0); + // STATUS shadows the same way EXEC does, and the cost of getting it wrong is + // higher: the ROCr handler raises STATUS.HALT and only then returns, so a + // record applied in that window used to clear the HALT the handler had just + // set. s_rfe then saw a running wave, resumed it, and the breakpoint was + // silently lost -- one inferior in gdb.rocm/multi-inferior-stress.exp running + // its kernel to completion and exiting without ever stopping. Route the + // record's HALT to the interrupted state the handler restores and leave the + // live register to the handler. + const uint32_t restored_status = + (state.status & ~kStatusHaltMask) | (state.saved_status_halt ? kStatusHaltMask : 0u); + if (wave.in_trap_handler()) + wave.set_trap_saved_status(restored_status); + else + wave.set_status_raw(restored_status); + // The live STATUS.HALT stays as it is for a handler that raised it with + // s_setreg: there the bit is the handler's own request to keep the wave + // stopped, and clearing it on a resume loses the breakpoint -- + // DbgTrapCwsrShadowsTrapHandlerRegistersAndRoutesDebuggerEdits pins that. + // A wave halted at s_sendmsghalt sits in the same window and wants the + // opposite: it has already reported and is waiting to be let go, so leaving + // the bit set strands it at the handler return. The record cannot tell the + // two apart, which is why the wave records who raised the bit. + if (!state.wave_stopped && wave.self_halted()) { + wave.set_status_halt(false); + wave.set_self_halted(false); + } + wave.set_mode_raw(state.mode); + wave.set_trapsts(state.trapsts); + wave.set_debug_wave_id(state.wave_id); + wave.set_aql_packet_id(state.queue_packet_id); + const uint32_t stack_pointer = wave.debug_read_sgpr(32); + const uint32_t stack_frame = wave.debug_read_sgpr(33); + // rocm-dbgapi may submit a lightweight control-state update with no register + // payload after displaced stepping. Preserve the SGPR/VGPR values produced + // by the displaced instruction in that case rather than restoring zeros. + // + // Skip exactly the slots the codec treats as aliases, not everything above + // the architected count: s104/s105 sit between the FLAT_SCRATCH and VCC + // aliases and are ordinary registers the debugger may edit. Sharing + // cwsr_sgpr_slot_is_aliased() with the codec is what keeps the two ends of + // the round trip from disagreeing about which slots carry register state. + if (!state.sgprs.empty()) + for (uint32_t s = 0; s < state.num_sgprs && s < state.sgprs.size(); ++s) + if (s != 32 && s != 33 && !kmd::cwsr_sgpr_slot_is_aliased(s)) + wave.debug_write_sgpr(s, state.sgprs[s]); + if (!state.vgprs.empty()) + for (uint32_t r = 0; r < state.num_vgprs; ++r) + for (uint32_t lane = 0; lane < wave.wf_size(); ++lane) { + const size_t index = static_cast(r) * 64 + lane; + if (index < state.vgprs.size()) + wave.debug_write_vgpr(r, lane, state.vgprs[index]); + } + // FLAT_SCRATCH travels in its own field because it aliases two SGPR slots the + // loop above skips. This used to save and re-install wave.scratch_base() + // around the loop, which the loop cannot reach anyway (scratch_base_ is a + // standalone member), so the only effect was discarding the debugger's edit. + wave.set_scratch_base(state.flat_scratch); + wave.debug_write_sgpr(32, stack_pointer); + wave.debug_write_sgpr(33, stack_frame); + const bool single_step = !state.wave_stopped && (state.mode & kModeDebugEnMask) != 0; + wave.set_debug_single_step(single_step); + wave.set_debug_halted(state.wave_stopped); + // debug_suspended is deliberately left set here. Clearing it per wave made + // each wave runnable the moment its own record was applied, so the engine + // could execute it while its queue-mates -- and their LDS images -- were + // still being restored. resume_debug_queues() commits the bit for every wave + // in the queue in one pass once the whole restore has succeeded. +} + +int SimulatedKfd::resume_debug_queues(KfdProcess *proc, uint32_t *queue_ids, uint32_t num_queues) { + constexpr uint32_t kQueueError = uint32_t{1} << KFD_DBG_QUEUE_ERROR_BIT; + constexpr uint32_t kQueueInvalid = uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT; + constexpr uint32_t kQueueStatus = kQueueError | kQueueInvalid; + struct QueueContext { + uint32_t request_index = 0; + uint32_t queue_id = 0; + uint64_t base = 0; + uint32_t size = 0; + uint32_t gpu_id = 0; + }; + std::vector queues; + if (proc) { + std::lock_guard lk(proc->alloc_mutex_); + for (uint32_t index = 0; index < num_queues; ++index) { + const uint32_t queue_id = queue_ids[index] & ~kQueueStatus; + queue_ids[index] = queue_id; + auto queue = proc->queue_snapshot_map_.find(queue_id); + if (queue == proc->queue_snapshot_map_.end()) { + queue_ids[index] |= kQueueInvalid; + continue; + } + const auto &info = queue->second; + queues.push_back({index, queue_id, info.ctx_save_restore_address, + info.ctx_save_restore_area_size, info.gpu_id}); + } + } else { + for (uint32_t index = 0; index < num_queues; ++index) + queue_ids[index] = (queue_ids[index] & ~kQueueStatus) | kQueueInvalid; + } + uint32_t resumed = 0; + for (const auto &context : queues) { + auto *gpu = find_gpu(context.gpu_id); + if (!gpu || !gpu->soc) { + queue_ids[context.request_index] |= kQueueError; + continue; + } + std::vector stopped; + std::vector states; + std::vector owners; + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + for (auto *cu : cp->compute_units()) { + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + auto *wave = cu->wf(slot); + if (wave->debug_stopped() && wave->process_id() == proc->process_id() && + wave->queue_id() == context.queue_id) { + stopped.push_back(wave); + states.push_back(build_cwsr_wave_state(*wave)); + owners.push_back(cu); + } + } + }); + } + }); + bool restored = stopped.empty(); + if (!stopped.empty() && context.base != 0) { + std::sort(states.begin(), states.end(), [](const auto &lhs, const auto &rhs) { + if (lhs.queue_packet_id != rhs.queue_packet_id) + return lhs.queue_packet_id < rhs.queue_packet_id; + if (lhs.group_ids != rhs.group_ids) + return lhs.group_ids < rhs.group_ids; + return lhs.wave_in_group < rhs.wave_in_group; + }); + auto same_group = [](const auto &lhs, const auto &rhs) { + return lhs.queue_packet_id == rhs.queue_packet_id && lhs.group_ids == rhs.group_ids; + }; + for (size_t index = 0; index < states.size(); ++index) { + states[index].is_first_in_group = + index == 0 || !same_group(states[index], states[index - 1]); + states[index].is_last_in_group = + index + 1 == states.size() || !same_group(states[index], states[index + 1]); + if (!states[index].is_first_in_group) + states[index].lds.clear(); + } + auto *memory = gpu->soc->memory(); + util::UniqueHandle target_mem = duplicate_debug_target_mem(proc->client_pid()); + bool read_ok = true; + restored = kmd::deserialize_queue_cwsr_bulk( + context.base, context.size, states, [&](uint64_t address, std::span bytes) { + if (target_mem.get() < 0) { + memory->read_block(address, bytes, proc->process_id()); + return; + } + const ssize_t bytes_read = + pread(target_mem.get(), bytes.data(), bytes.size(), static_cast(address)); + if (bytes_read != static_cast(bytes.size())) { + read_ok = false; + std::fill(bytes.begin(), bytes.end(), 0); + util::Logger::warn("CWSR target read failed: addr=0x", std::hex, address, + " pid=", std::dec, proc->client_pid(), " rc=", bytes_read, + " errno=", errno); + } + }); + restored = restored && read_ok; + } + std::unordered_set wake; + if (restored) { + std::vector matches; + matches.reserve(states.size()); + std::vector matched(stopped.size()); + for (const auto &state : states) { + auto find_match = [&](bool by_wave_id) { + for (size_t index = 0; index < stopped.size(); ++index) { + if (matched[index]) + continue; + const auto *candidate = stopped[index]; + if (by_wave_id ? state.wave_id != 0 && candidate->debug_wave_id() == state.wave_id + : candidate->debug_wave_id() == 0 && + candidate->aql_packet_id() == state.queue_packet_id && + candidate->wg_coord() == state.group_ids && + candidate->wave_in_group() == state.wave_in_group) + return index; + } + return stopped.size(); + }; + size_t index = find_match(true); + if (index == stopped.size()) + index = find_match(false); + if (index == stopped.size()) { + restored = false; + break; + } + matched[index] = true; + matches.push_back(index); + } + restored = restored && matches.size() == stopped.size(); + if (restored) { + for (size_t state_index = 0; state_index < states.size(); ++state_index) { + const size_t wave_index = matches[state_index]; + if (!states[state_index].lds.empty()) + stopped[wave_index]->lds().write(stopped[wave_index]->lds_base(), + states[state_index].lds.data(), + static_cast(states[state_index].lds.size())); + owners[wave_index]->with_wave_state_locked( + [&] { apply_cwsr_to_wave(*stopped[wave_index], states[state_index]); }); + } + } + } + // This is the single commit point for debug_suspended: apply_cwsr_to_wave() + // leaves every wave suspended, so none of them runs until the whole queue's + // CWSR state and LDS have been restored above. + // + // Accumulated inside the locked loop below rather than read afterwards. + // The loop clears debug_suspended, which makes these waves runnable, so + // from that point the engine thread can be writing debug_halted_ -- a plain + // bool -- concurrently. This value decides whether the queue gate reopens, + // so reading it unlocked would race the answer as well as the byte. + bool keep_dispatch_suspended = false; + for (size_t index = 0; index < stopped.size(); ++index) { + owners[index]->with_wave_state_locked([&] { + const bool fatal_exception_pending = stopped[index]->fatal_exception_pending(); + // A malformed or stale CWSR image must not strand a temporarily + // suspended wave after the queue gate is released. Architecturally + // halted waves remain halted until their CWSR record says otherwise. + stopped[index]->set_debug_suspended(fatal_exception_pending); + const bool halted = stopped[index]->debug_halted(); + keep_dispatch_suspended |= halted; + if (!halted && !stopped[index]->is_halted()) + if (!fatal_exception_pending) + wake.insert(owners[index]); + }); + } + // Keep the queue-level launch gate closed until every resident wave has + // consumed its CWSR state and become runnable. Reopen it before scheduling + // those waves so CP completion processing cannot observe a queue as still + // suspended if a resumed wave completes immediately. + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + cp->set_queue_debug_suspended(context.queue_id, proc->process_id(), keep_dispatch_suspended); + }); + for (auto *cu : wake) + cu->schedule_work_async(); + if (restored) + ++resumed; + else + queue_ids[context.request_index] |= kQueueError; + } + return static_cast(resumed); +} + +int SimulatedKfd::suspend_debug_queues(KfdProcess *proc, uint32_t *queue_ids, uint32_t num_queues, + uint64_t exception_mask) { + constexpr uint32_t kQueueError = uint32_t{1} << KFD_DBG_QUEUE_ERROR_BIT; + constexpr uint32_t kQueueInvalid = uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT; + constexpr uint32_t kQueueStatus = kQueueError | kQueueInvalid; + struct RequestedQueue { + uint32_t request_index = 0; + uint32_t queue_id = 0; + KfdProcess::QueueSnapshotInfo info{}; + }; + std::vector queues; + if (!proc) { + for (uint32_t index = 0; index < num_queues; ++index) + queue_ids[index] = (queue_ids[index] & ~kQueueStatus) | kQueueInvalid; + return 0; + } + const uint32_t process_id = proc->process_id(); + { + std::lock_guard lk(proc->alloc_mutex_); + for (uint32_t index = 0; index < num_queues; ++index) { + const uint32_t queue_id = queue_ids[index] & ~kQueueStatus; + queue_ids[index] = queue_id; + auto queue = proc->queue_snapshot_map_.find(queue_id); + if (queue == proc->queue_snapshot_map_.end() || + (queue->second.exception_status & KFD_EC_MASK(EC_QUEUE_NEW)) != 0) { + queue_ids[index] |= kQueueInvalid; + continue; + } + queue->second.exception_status &= ~exception_mask; + queues.push_back({index, queue_id, queue->second}); + } + } + uint32_t suspended = 0; + for (const auto &queue : queues) { + auto *gpu = find_gpu(queue.info.gpu_id); + if (!gpu || !gpu->soc) { + queue_ids[queue.request_index] |= kQueueError; + continue; + } + // Ask before suspending anything. This path stops waves first and only then + // tries to serialize them, so on an unmodelled architecture it would strand + // every resident wave behind a kQueueError -- the same hole the wave-stop + // callbacks have, reached through the debugger's own request instead. + if (!debug_stop_publishable(queue.info.gpu_id)) { + queue_ids[queue.request_index] |= kQueueError; + continue; + } + std::vector> newly_suspended; + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + cp->set_queue_debug_suspended(queue.queue_id, process_id, true); + for (auto *cu : cp->compute_units()) { + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + auto *wave = cu->wf(slot); + if (!wave->is_halted() && !wave->debug_suspended() && + wave->process_id() == process_id && wave->queue_id() == queue.queue_id) { + wave->set_debug_suspended(true); + newly_suspended.emplace_back(cu, wave); + } + } + }); + } + }); + bool serialized = newly_suspended.empty(); + if (!newly_suspended.empty() && queue.info.ctx_save_restore_address != 0) + serialized = serialize_queue_debug_waves(process_id, queue.queue_id, queue.info.gpu_id, + queue.info.ctx_save_restore_address, + queue.info.ctx_save_restore_area_size); + if (serialized) { + ++suspended; + continue; + } + // No record was published, so the debugger has nothing to resume from. + // Undo the suspension rather than leave the queue wedged: reporting the + // error and stranding the waves is strictly worse than reporting it alone. + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + cp->set_queue_debug_suspended(queue.queue_id, process_id, false); + }); + amdgpu::ComputeUnitCore *woken = nullptr; + for (auto &[cu, wave] : newly_suspended) { + cu->with_wave_state_locked([w = wave] { w->set_debug_suspended(false); }); + // Entries are appended compute unit by compute unit, so comparing against + // the last one woken collapses a CU's waves into a single wake. + if (cu != woken) { + cu->schedule_work_async(); + woken = cu; + } + } + queue_ids[queue.request_index] |= kQueueError; + } + return static_cast(suspended); +} + +void SimulatedKfd::clear_completed_debug_queues(KfdProcess *proc, const uint32_t *queue_ids, + uint32_t num_queues) { + if (!proc) + return; + constexpr uint32_t kQueueStatus = + (uint32_t{1} << KFD_DBG_QUEUE_ERROR_BIT) | (uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT); + const uint32_t process_id = proc->process_id(); + std::vector> queues; + { + std::lock_guard lk(proc->alloc_mutex_); + for (uint32_t index = 0; index < num_queues; ++index) { + if ((queue_ids[index] & kQueueStatus) != 0) + continue; + const uint32_t queue_id = queue_ids[index]; + auto queue = proc->queue_snapshot_map_.find(queue_id); + if (queue != proc->queue_snapshot_map_.end()) + queues.emplace_back(queue_id, queue->second); + } + } + for (const auto &[queue_id, queue] : queues) { + auto *gpu = find_gpu(queue.gpu_id); + if (!gpu || !gpu->soc || queue.ctx_save_restore_address == 0) + continue; + bool has_stopped_wave = false; + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + for (auto *cu : cp->compute_units()) { + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + const auto *wave = cu->wf(slot); + if (wave->debug_stopped() && wave->process_id() == process_id && + wave->queue_id() == queue_id) + has_stopped_wave = true; + } + }); + } + }); + if (!has_stopped_wave) { + auto *memory = gpu->soc->memory(); + for (uint64_t offset = 0; offset < 40; offset += sizeof(uint32_t)) + memory->write32(queue.ctx_save_restore_address + offset, 0, process_id); + } + } +} + +int SimulatedKfd::debug_query_event(pid_t target_pid, KfdProcess *target_proc, + uint64_t enabled_mask, + kfd_ioctl_dbg_trap_query_debug_event_args &args) { + const uint64_t clear_mask = args.exception_mask; + std::lock_guard lk(debug_events_mutex_); + auto process = debug_events_.find(target_pid); + if (process == debug_events_.end()) + return -EAGAIN; + auto &queues = process->second; + for (auto queue = queues.begin(); queue != queues.end(); ++queue) { + if ((queue->second.mask & enabled_mask) == 0) + continue; + args.exception_mask = queue->second.mask; + args.queue_id = queue->first; + args.gpu_id = queue->second.gpu_id; + queue->second.mask &= ~clear_mask; + const uint32_t queue_id = queue->first; + if (queue->second.mask == 0) + queues.erase(queue); + if (target_proc != nullptr && queue_id != 0) { + std::lock_guard alloc_lock(target_proc->alloc_mutex_); + auto snapshot = target_proc->queue_snapshot_map_.find(queue_id); + if (snapshot != target_proc->queue_snapshot_map_.end()) + snapshot->second.exception_status &= ~clear_mask; + } + return 0; + } + return -EAGAIN; +} + +void SimulatedKfd::raise_process_debug_event(pid_t target_pid, uint64_t exception_mask) { + util::UniqueHandle notifier; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(target_pid); + if (session == debug_sessions_.end() || !session->second.enabled) + return; + if ((session->second.exception_enable_mask & exception_mask) != 0) + notifier = util::UniqueHandle(safe_fcntl(session->second.dbg_fd, F_DUPFD_CLOEXEC, 0)); + } + { + std::lock_guard lk(debug_events_mutex_); + auto &event = debug_events_[target_pid][0]; + event.gpu_id = 0; + event.mask |= exception_mask; + } + if (notifier.get() >= 0) { + const uint64_t one = 1; + [[maybe_unused]] const ssize_t written = ::write(notifier.get(), &one, sizeof(one)); + } +} + +void SimulatedKfd::cancel_runtime_handshake(pid_t target_pid) { + { + std::lock_guard lk(runtime_handshake_mutex_); + runtime_handshake_cancelled_.insert(target_pid); + } + runtime_handshake_cv_.notify_all(); +} + +/// @details The inferior must not run a kernel until the debugger attached to +/// it has seen EC_PROCESS_RUNTIME and installed its breakpoints -- that is the +/// whole point of the handshake, and amdkfd's runtime_enable blocks the caller +/// for it. Returning early is not a graceful degradation: the code objects load +/// unobserved, the debugger's breakpoints are never inserted, and the kernel +/// runs to completion. Under a debugger driving many inferiors at once (see +/// gdb.rocm/multi-inferior-stress.exp, 32 of them) a short deadline expires +/// routinely while the debugger is simply busy servicing its queue, which +/// showed up as rare, load-dependent "inferior exited before hitting the +/// kernel" failures. +/// +/// So wait for the ack itself, and treat the deadline purely as a liveness +/// backstop against a debugger that has wedged without detaching -- long enough +/// that a merely slow one is never cut off, and noisy when it does fire so the +/// timeout is never again mistaken for correct behaviour. A debugger that +/// detaches or dies cancels the wait explicitly and does not pay it at all. +/// +/// The disable direction reports the transition and returns. kfd_chardev.c's +/// runtime_disable does wait there -- it raises EC_PROCESS_RUNTIME and blocks on +/// runtime_enable_sema, the same way runtime_enable does -- and this deliberately +/// does not follow it, because the two are not in the same position. The kernel +/// blocks a task; here the ioctl is served on the daemon's connection thread for +/// that client, and holding it parks the daemon's side of a process that is +/// already exiting. Doing it anyway destabilises the daemon-backed tests +/// (RemoteDriverDbg*) with no measured benefit: the -EPERM storm this was first +/// written for is answered where it is raised, by the queue gate letting a +/// suspend or resume of already-destroyed queues through. +void SimulatedKfd::runtime_debugger_handshake(pid_t target_pid, bool enabling) { + // The caller already decided, under debug_sessions_mutex_, that a debugger is + // attached; re-testing here would just re-open the window it closed. Only the + // self-debug shape still needs distinguishing. + bool self_debugged = false; + { + std::lock_guard lk(debug_sessions_mutex_); + auto session = debug_sessions_.find(target_pid); + if (session == debug_sessions_.end() || !session->second.enabled) + return; + self_debugged = session->second.debugger_pid == target_pid; + + // Drop any ack or cancellation left over from an earlier transition for this + // pid before the event goes out. The disable direction reports without + // waiting, so nothing consumes the ack it draws; a later enable would + // otherwise find that stale entry already in runtime_acked_, satisfy its wait + // immediately, and let the inferior dispatch before the debugger has + // installed its breakpoints -- the exact failure the deadline below exists to + // prevent. + // + // A cancellation does the same thing and is easier to leave behind, because + // cancel_runtime_handshake() inserts unconditionally: a detach with no waiter + // parked -- which every explicit DBG_TRAP_DISABLE performs -- leaves an entry + // nobody consumes, and the wait predicate below accepts it just as readily as + // a real ack. Clearing both under the same lock a real cancel would take + // means a cancel racing this clear necessarily lands on the new wait. + // + // That last part only holds while debug_sessions_mutex_ is still held, which + // is why the clear lives here rather than after the lookup returns. An + // explicit DBG_TRAP_DISABLE erases the session, drops the mutex, and only + // then calls cancel_runtime_handshake(). Clearing after releasing the mutex + // left a window in which the detach's cancellation was recorded after this + // function had already decided the session was live, and was then erased by + // this very clear -- so nothing remained to satisfy the wait below, no acker + // was left to provide one, and the inferior paid the full 60s deadline. + // Holding the mutex across both means a detach either erases the session + // before the lookup (which returns early) or blocks until after the clear, + // in which case its cancellation lands on the wait. + if (enabling) { + std::lock_guard hlk(runtime_handshake_mutex_); + runtime_acked_.erase(target_pid); + runtime_handshake_cancelled_.erase(target_pid); + } + } + raise_process_debug_event(target_pid, KFD_EC_MASK(EC_PROCESS_RUNTIME)); + // A process debugging itself cannot answer its own handshake: the ack would + // have to come from the thread that is, by construction, blocked here. The + // event is raised so the state is observable; waiting for a reply that can + // never arrive would just burn the liveness deadline. + if (self_debugged || !enabling) + return; + + constexpr auto kHandshakeDeadline = std::chrono::seconds(60); + std::unique_lock lk(runtime_handshake_mutex_); + const bool released = runtime_handshake_cv_.wait_for(lk, kHandshakeDeadline, [&] { + return runtime_acked_.contains(target_pid) || runtime_handshake_cancelled_.contains(target_pid); + }); + const bool cancelled = runtime_handshake_cancelled_.erase(target_pid) != 0; + runtime_acked_.erase(target_pid); + if (!released) { + util::Logger::warn("runtime-enable handshake timed out after ", kHandshakeDeadline.count(), + "s for pid=", target_pid, + "; the debugger never acknowledged EC_PROCESS_RUNTIME, so its " + "breakpoints may not be installed before the first dispatch"); + } else if (cancelled) { + util::Logger::vm("runtime-enable handshake cancelled for pid=", target_pid, + " (debugger detached)"); + } +} - KfdProcess *target = nullptr; - std::shared_ptr target_ref; - if (caller.client_pid() != 0 && static_cast(args->pid) == caller.client_pid()) { - target = &caller; // self-debug (local mode) +int SimulatedKfd::debug_query_exception_info(pid_t target_pid, + kfd_ioctl_dbg_trap_query_exception_info_args &args) { + if (args.exception_code != EC_PROCESS_RUNTIME) + return -EINVAL; + kfd_runtime_info info{}; + if (auto proc = find_process_by_client_pid(target_pid)) { + std::lock_guard lk(proc->runtime_mutex_); + info.r_debug = proc->runtime_state_.r_debug; + info.runtime_state = + proc->runtime_state_.enabled ? DEBUG_RUNTIME_STATE_ENABLED : DEBUG_RUNTIME_STATE_DISABLED; + info.ttmp_setup = + (proc->runtime_state_.mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK) ? 1u : 0u; + } + const uint32_t capacity = args.info_size; + args.info_size = sizeof(info); + if (capacity > 0 && args.info_ptr == 0) + return -EFAULT; + if (args.info_ptr != 0 && capacity > 0) + std::memcpy(reinterpret_cast(static_cast(args.info_ptr)), &info, + std::min(static_cast(capacity), sizeof(info))); + if (args.clear_exception) { + std::lock_guard lk(debug_events_mutex_); + auto process = debug_events_.find(target_pid); + if (process != debug_events_.end()) { + auto event = process->second.find(0); + if (event != process->second.end()) { + event->second.mask &= ~KFD_EC_MASK(EC_PROCESS_RUNTIME); + if (event->second.mask == 0) + process->second.erase(event); + } + } + } + return 0; +} + +namespace { + +/// @brief Whether a suspend/resume names only queues the process has destroyed. +/// @details Used to tell a request that cannot touch hardware from one that +/// can, so the runtime-down gate only refuses the latter. Any other op, an +/// absent process, or an empty request answers false, leaving the kernel's +/// behaviour in place. +bool queues_all_dead(KfdProcess *proc, const kfd_ioctl_dbg_trap_args &args) { + constexpr uint32_t kQueueStatus = KFD_DBG_QUEUE_ERROR_MASK | KFD_DBG_QUEUE_INVALID_MASK; + if (proc == nullptr) + return false; + uint32_t count = 0; + uint64_t array_ptr = 0; + if (args.op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES) { + count = args.suspend_queues.num_queues; + array_ptr = args.suspend_queues.queue_array_ptr; + } else if (args.op == KFD_IOC_DBG_TRAP_RESUME_QUEUES) { + count = args.resume_queues.num_queues; + array_ptr = args.resume_queues.queue_array_ptr; } else { - target_ref = find_process_by_client_pid(static_cast(args->pid)); - target = target_ref.get(); + return false; } - if (target == nullptr) + // An empty batch names nothing live, so it belongs on the answered side: with + // the runtime up the handlers return 0 for it, and refusing it here would flip + // that to the -EPERM rocdbgapi escalates to a fatal purely on runtime state. + if (count == 0) + return true; + // A null array with a non-zero count is malformed; leave it to the handler's + // -EFAULT rather than inventing an answer for it. + if (array_ptr == 0) + return false; + const auto *queue_ids = reinterpret_cast(static_cast(array_ptr)); + std::lock_guard lk(proc->alloc_mutex_); + for (uint32_t index = 0; index < count; ++index) + if (proc->queue_snapshot_map_.contains(queue_ids[index] & ~kQueueStatus)) + return false; + return true; +} + +} // namespace + +// in real kernel, amd/amdkfd/kfd_chardev.c kfd_ioctl_set_debug_trap +int SimulatedKfd::debug_trap_ioctl(KfdProcess &caller, void *arg, int *target_mem_fd, + int target_proc_fd) { + auto *args = static_cast(arg); + util::Logger::driver("DBG_TRAP pid=", args->pid, " op=", args->op); + // rocjitsu always models hardware scheduling, so the driver's + // KFD_SCHED_POLICY_NO_HWS -> EINVAL guard is not applicable. + + // Resolve the target process by Linux pid (kernel: find_get_pid() + + // kfd_lookup_process_by_pid()). The target's KfdProcess may not exist yet: + // rocgdb enables debug on the inferior right after exec, before its ROCr has + // opened /dev/kfd. The debug session is keyed by the target pid + // (debug_sessions_) independently of the KfdProcess, mirroring the kernel + // creating the target kfd_process in the ENABLE path. Operations that need + // live GPU state look the process up lazily. + const auto target_pid = static_cast(args->pid); + if (target_pid <= 0) return -ESRCH; - const bool self_debug = (target == &caller); - - std::lock_guard lk(target->debug_mutex_); - auto &sess = target->debug_session_; - - // Cross-process authorization is by-pid only: a non-self caller is admitted - // solely when it is the debugger already attached to this session - // (sess.debugger_pid, set by a prior successful ENABLE). This gate therefore - // only re-admits re-entrant ops from an already-attached debugger. Because a - // fresh session has debugger_pid == 0, it structurally rejects the *first* - // cross-process ENABLE with EPERM: cross-process attach is intentionally - // closed until it is implemented (#8364). Self-debug (local mode, the only - // supported path today) and DISABLE are exempt. The real kernel instead gates - // the first attach on a live ptrace relationship, which is deferred with the - // rest of cross-process support. - if (!self_debug && args->op != KFD_IOC_DBG_TRAP_DISABLE && - sess.debugger_pid != caller.client_pid()) - return -EPERM; + const bool self_debug = caller.client_pid() != 0 && target_pid == caller.client_pid(); + + std::unique_lock lk(debug_sessions_mutex_); + auto session_it = debug_sessions_.find(target_pid); + if (session_it != debug_sessions_.end()) { + if (session_it->second.target_exited) { + if (args->op != KFD_IOC_DBG_TRAP_ENABLE) + return -ESRCH; + debug_sessions_.erase(session_it); + session_it = debug_sessions_.end(); + } + } + if (session_it != debug_sessions_.end()) { + const int target_exited = pidfd_is_exited(session_it->second.target_pidfd.get()); + if (target_exited < 0) + return target_exited; + const int debugger_exited = pidfd_is_exited(session_it->second.debugger_pidfd.get()); + if (debugger_exited < 0) + return debugger_exited; + if (target_exited == 1) { + session_it->second.owned_dbg_fd.reset(); + session_it->second.target_mem_fd.reset(); + session_it->second.dbg_fd = -1; + session_it->second.enabled = false; + session_it->second.target_exited = true; + if (args->op != KFD_IOC_DBG_TRAP_ENABLE) + return -ESRCH; + debug_sessions_.erase(session_it); + session_it = debug_sessions_.end(); + } else if (debugger_exited == 1) { + debug_sessions_.erase(session_it); + session_it = debug_sessions_.end(); + } + } + const bool enabled = session_it != debug_sessions_.end(); // Non-ENABLE ops require an active debug session (kernel: EINVAL). - if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !sess.enabled) + if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !enabled) { + util::UniqueHandle probe_pidfd; + util::UniqueHandle probe_procfd; + const int probe_result = pin_process_identity(target_pid, probe_pidfd, probe_procfd); + if (probe_result == -ESRCH) + return -ESRCH; + if (probe_result != 0) + return probe_result; + const int zombie = procfd_is_zombie(probe_procfd.get()); + if (zombie != 0) + return zombie == 1 ? -ESRCH : zombie; return -EINVAL; + } + + // Pin the exact Linux task before consulting ptrace state. For an existing + // session, use the identity captured by ENABLE; otherwise capture both a + // pidfd and the matching procfs directory now. The pidfd liveness checks on + // both sides of the procfs read ensure a numeric-pid reuse can never authorize + // a different task. + util::UniqueHandle new_target_pidfd; + util::UniqueHandle new_target_procfd; + util::UniqueHandle *target_pidfd; + util::UniqueHandle *target_procfd; + if (enabled) { + target_pidfd = &session_it->second.target_pidfd; + target_procfd = &session_it->second.target_procfd; + } else { + const int pin_result = pin_process_identity(target_pid, new_target_pidfd, new_target_procfd); + if (pin_result != 0) + return pin_result; + target_pidfd = &new_target_pidfd; + target_procfd = &new_target_procfd; + } + + util::UniqueHandle new_debugger_pidfd; + util::UniqueHandle new_debugger_procfd; + if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { + const int debugger_pin_result = + pin_process_identity(caller.client_pid(), new_debugger_pidfd, new_debugger_procfd); + if (debugger_pin_result != 0) + return debugger_pin_result; + } + + // PTRACE gate: for any op other than DISABLE, a debugger acting on another + // process must be that exact process's ptrace parent. This mirrors + // ptrace_parent(target->lead_thread) == current in kfd_ioctl_set_debug_trap(). + if (!self_debug && args->op != KFD_IOC_DBG_TRAP_DISABLE) { + pid_t tracer_pid = 0; + const int tracer_result = + tracer_pid_of(*target_pidfd, *target_procfd, debug_identity_validation_hook_, tracer_pid); + if (tracer_result != 0) { + if (tracer_result == -ESRCH && enabled) + debug_sessions_.erase(target_pid); + return tracer_result; + } + if (tracer_pid != caller.client_pid()) + return -EPERM; + } - // Live runtime-enable state, set by ROCr's AMDKFD_IOC_RUNTIME_ENABLE. - const bool runtime_enabled = [&] { - std::lock_guard rlk(target->runtime_mutex_); - return target->runtime_state_.enabled; - }(); + // Resolve live GPU state only after pinning and authorizing the OS identity, + // so a KfdProcess associated with a reused numeric pid is never selected. + std::shared_ptr target_ref = + self_debug ? nullptr : find_process_by_client_pid(target_pid); + KfdProcess *target_proc = self_debug ? &caller : target_ref.get(); + if (target_proc != nullptr && session_it != debug_sessions_.end()) + session_it->second.saw_kfd_process = true; + + // Live runtime-enable state, set by ROCr's AMDKFD_IOC_RUNTIME_ENABLE on the + // inferior; false until the inferior connects and enables its runtime. + bool runtime_enabled = false; + if (target_proc != nullptr) { + std::lock_guard rlk(target_proc->runtime_mutex_); + runtime_enabled = target_proc->runtime_state_.enabled; + } + + // The target may exit after authorization. Revalidate before performing or + // committing an operation so a reused numeric pid cannot contribute live + // KfdProcess state to the pinned session. + const int still_live = pidfd_is_exited(target_pidfd->get()); + if (still_live != 0) { + if (still_live == 1 && enabled) + debug_sessions_.erase(target_pid); + return still_live == 1 ? -ESRCH : still_live; + } + if (args->op == KFD_IOC_DBG_TRAP_ENABLE) { + const int debugger_still_live = pidfd_is_exited(new_debugger_pidfd.get()); + if (debugger_still_live != 0) + return debugger_still_live == 1 ? -ESRCH : debugger_still_live; + } // https://github.com/torvalds/linux/blob/a635d6748234582ea287c5ffeae28b9b23f91c7e/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c#L3132-L3142 switch (args->op) { @@ -2111,8 +3901,37 @@ int SimulatedKfd::debug_trap_ioctl(KfdProcess &caller, void *arg) { case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: case KFD_IOC_DBG_TRAP_SET_FLAGS: - if (!runtime_enabled) - return -EPERM; + if (!runtime_enabled) { + // A target that had a KfdProcess and no longer has one is a process on + // its way out, not a live one refusing the op. The real driver cannot + // reach this gate in that state at all: its pid lookup fails first and + // returns -ESRCH, which rocdbgapi handles (PROCESS_EXITED -> invalidate + // the queues and move on). -EPERM is what it escalates to a fatal + // os_driver::resume_queues failure, so getting this distinction wrong + // crashes GDB during teardown (gdb.rocm/multi-inferior-stress.exp). + if (target_proc == nullptr && session_it != debug_sessions_.end() && + session_it->second.saw_kfd_process) + return -ESRCH; + // A suspend or resume naming only queues the process has already + // destroyed asks nothing of the hardware, and answering it is the only + // way rocdbgapi learns to drop them: the per-queue INVALID bit the normal + // path writes back. It cannot learn it any other way once the runtime is + // down, because its queue-list sweep is gated on the runtime being up + // (process.cpp update_queues), and it escalates the -EPERM to a fatal + // rather than retiring the queue. + // + // Upstream refuses this unconditionally, and never has to answer it: its + // teardown does not leave a debugger holding a suspended queue across + // runtime shutdown, so the request does not arise. Ours does, and the + // narrow shape -- no runtime, and not one live queue among those named -- + // is exactly the one where refusing costs information and buys nothing. + // Anything still live keeps the kernel's answer. + if (!queues_all_dead(target_proc, *args)) + return -EPERM; + util::Logger::vm("DBG_TRAP op=", args->op, " for pid=", target_pid, + " names only destroyed queues and the runtime is down; reporting them " + "invalid instead of -EPERM"); + } break; default: break; @@ -2132,7 +3951,7 @@ int SimulatedKfd::debug_trap_ioctl(KfdProcess &caller, void *arg) { switch (args->op) { // https://github.com/torvalds/linux/blob/a635d6748234582ea287c5ffeae28b9b23f91c7e/drivers/gpu/drm/amd/amdkfd/kfd_debug.c#L788-L847 case KFD_IOC_DBG_TRAP_ENABLE: { - if (sess.enabled) + if (enabled) return -EALREADY; // target process is already debug enabled const int dbg_fd = static_cast(args->enable.dbg_fd); @@ -2147,27 +3966,62 @@ int SimulatedKfd::debug_trap_ioctl(KfdProcess &caller, void *arg) { const int fl = safe_fcntl(dbg_fd, F_GETFL); if (fl == -1 || (fl & O_ACCMODE) == O_RDONLY) return -EBADF; + if (daemon_mode_) { + if (target_mem_fd == nullptr || *target_mem_fd < 0 || target_proc_fd < 0) + return -EBADF; + const int mem_fl = safe_fcntl(*target_mem_fd, F_GETFL); + if (mem_fl == -1 || (mem_fl & O_ACCMODE) != O_RDWR) + return -EBADF; + struct stat daemon_proc_stat {}; + struct stat client_proc_stat {}; + if (fstat(target_procfd->get(), &daemon_proc_stat) != 0 || + fstat(target_proc_fd, &client_proc_stat) != 0) + return -errno; + if (daemon_proc_stat.st_dev != client_proc_stat.st_dev || + daemon_proc_stat.st_ino != client_proc_stat.st_ino) + return -ESRCH; + // The proc directory is pinned to the right process by the check above, + // but nothing yet ties the transferred mem fd to it -- O_RDWR only says + // the fd is writable, not whose memory it addresses. This fd becomes + // authoritative for guest reads and CWSR writes, so a mismatched one + // silently redirects both at another process. procfs gives each + // /proc//mem its own inode, so comparing it against the pinned + // directory's own "mem" entry settles the question. + struct stat expected_mem_stat {}; + struct stat client_mem_stat {}; + if (fstatat(target_procfd->get(), "mem", &expected_mem_stat, 0) != 0 || + fstat(*target_mem_fd, &client_mem_stat) != 0) + return -errno; + if (expected_mem_stat.st_dev != client_mem_stat.st_dev || + expected_mem_stat.st_ino != client_mem_stat.st_ino) + return -ESRCH; + } + KfdProcess::DebugSession sess{}; + sess.target_pidfd = std::move(new_target_pidfd); + sess.target_procfd = std::move(new_target_procfd); sess.enabled = true; sess.debugger_pid = caller.client_pid(); + sess.debugger_pidfd = std::move(new_debugger_pidfd); sess.dbg_fd = dbg_fd; - // In daemon mode the session owns the transferred fd and releases it via - // RAII (on DISABLE or process teardown). In local mode dbg_fd is the - // debugger's own descriptor, left for the debugger to close. - if (daemon_mode_) - sess.owned_dbg_fd = util::UniqueHandle(dbg_fd); sess.exception_enable_mask = args->enable.exception_mask; // Snapshot the runtime-enable state under a single lock so the marshaled // runtime_state, r_debug and ttmp_setup stay mutually consistent: a // concurrent RUNTIME_ENABLE/DISABLE must not change them between reads. - // Lock order debug_mutex_ -> runtime_mutex_ is already held that way. + // Lock order debug_sessions_mutex_ -> runtime_mutex_ is already held that + // way. // Kernel: kfd_dbg_trap_enable copies the saved runtime info and returns its // size. kfd_runtime_info info{}; - { - std::lock_guard rlk(target->runtime_mutex_); - const auto &rt = target->runtime_state_; + if (target_proc != nullptr) { + // The session does not exist yet when the common path above records this, + // so ENABLE has to do it itself; otherwise an inferior that opens + // /dev/kfd, runs and exits before the debugger's first suspend/resume + // never sets the flag and the gate below answers -EPERM after all. + sess.saw_kfd_process = true; + std::lock_guard rlk(target_proc->runtime_mutex_); + const auto &rt = target_proc->runtime_state_; sess.runtime_state = rt.enabled ? DEBUG_RUNTIME_STATE_ENABLED : DEBUG_RUNTIME_STATE_DISABLED; info.r_debug = rt.r_debug; info.ttmp_setup = (rt.mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK) ? 1u : 0u; @@ -2178,35 +4032,194 @@ int SimulatedKfd::debug_trap_ioctl(KfdProcess &caller, void *arg) { std::memcpy(reinterpret_cast(static_cast(args->enable.rinfo_ptr)), &info, copy_size); args->enable.rinfo_size = sizeof(info); + + const int target_commit_live = pidfd_is_exited(sess.target_pidfd.get()); + if (target_commit_live != 0) + return target_commit_live == 1 ? -ESRCH : target_commit_live; + const int debugger_commit_live = pidfd_is_exited(sess.debugger_pidfd.get()); + if (debugger_commit_live != 0) + return debugger_commit_live == 1 ? -ESRCH : debugger_commit_live; + + // Both transferred fds are adopted here, past every failure check, because + // each only has to survive a successful ENABLE: on any earlier return the + // caller still owns it and reclaims it. Adopting the notifier sooner would + // double-close it, because the transport clears cmd->in_handle only when + // the ioctl succeeds -- a late liveness failure would destroy sess (closing + // the fd) and then let the transport close the same number again. With + // daemon requests running concurrently another thread can be handed that + // number in between, so the second close would land on an unrelated + // descriptor. In local mode dbg_fd is the debugger's own descriptor and + // nothing is owned here. + if (daemon_mode_) { + sess.owned_dbg_fd = util::UniqueHandle(dbg_fd); + sess.target_mem_fd = util::UniqueHandle(*target_mem_fd); + *target_mem_fd = -1; + } + auto [inserted, _] = debug_sessions_.emplace(target_pid, std::move(sess)); + if (target_proc != nullptr && inserted->second.target_mem_fd) { + for (auto &g : gpus_) + if (auto *mem = g.soc ? g.soc->memory() : nullptr) + mem->set_process_mem_fd(target_proc->process_id(), inserted->second.target_mem_fd.get()); + } + set_debug_active_on_all_cus(true); + debug_sessions_cv_.notify_one(); return 0; } - case KFD_IOC_DBG_TRAP_DISABLE: - // Resetting the session releases the debugger notifier: in daemon mode the - // session's UniqueHandle closes the SCM_RIGHTS-transferred fd it owns; in local - // mode nothing is owned, so the debugger's own fd is left untouched. - sess = KfdProcess::DebugSession{}; + case KFD_IOC_DBG_TRAP_DISABLE: { + // Erasing the session releases the debugger notifier: in daemon mode the + // session's UniqueHandle closes the SCM_RIGHTS-transferred fd it owns; in + // local mode nothing is owned, so the debugger's own fd is left untouched. + // + // The queued debug events and the per-queue exception status go with it. + // Both are debugger-visible state that only has meaning inside a session: + // leaving them behind would hand a stale EC_QUEUE_NEW, or an exception the + // previous debugger already consumed, to whoever attaches next. Any wave + // the departing debugger left stopped is resumed below, so detaching never + // strands the inferior's GPU work. + // + // Erase the session first, then release the inferior outside the lock. + // Dropping debug_sessions_mutex_ before touching any CU is mandatory: the + // engine thread takes these two the other way round -- ComputeUnitCore::step() + // runs the issue loop under the CU's wave-state lock and calls back into + // on_wave_trap_complete()/on_wave_watchpoint()/on_wave_illegal_inst(), each + // of which acquires debug_sessions_mutex_ -- so holding it across + // with_wave_state_locked() closes an AB-BA cycle and hangs a detach against + // a wave that is trapping at that moment. Erasing before the release also + // closes the window in which the session was still enabled while its events + // had already been cleared, letting a live callback publish into a session + // on its way out. This is the same invariant SUSPEND_QUEUES observes. + debug_sessions_.erase(target_pid); + lk.unlock(); + // target_proc, not a fresh find_process_by_client_pid(): it was resolved + // above while the pidfd/procfd pin still vouched for the identity, so a + // numeric pid reused since then cannot be selected here. It is also the + // only resolution that is correct for a self-debugging process, where the + // debuggee is `caller` and need not be reachable by client pid at all -- + // looking it up again would return nullptr and silently skip the whole + // release, stranding the very waves this path exists to free. + release_debuggee_state(target_pid, target_proc); + // An explicit detach also has to release a waiter, or the inferior pays the + // full liveness deadline for a debugger that is deliberately going away. + cancel_runtime_handshake(target_pid); + // Deliberately left unlocked: nothing below touches debug_sessions_, and + // release_debuggee_state() already re-took and released the mutex for the + // one guarded question it has to ask. return 0; + } case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: return debug_device_snapshot(args->device_snapshot); - - // Recognized ops whose handlers are not wired up yet. The kernel dispatches - // each to a real implementation; the skeleton reports ENOSYS ("not - // implemented") so a debugger can tell a stubbed-but-valid op apart from a - // genuinely unknown one (EINVAL below). Each case graduates out of this group - // as its handler lands — move it above this comment, not below it. - case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT: + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: + return debug_queue_snapshot(target_proc, args->queue_snapshot); + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + return debug_query_exception_info(target_pid, args->query_exception_info); + case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT: { + const auto &event = args->send_runtime_event; + if (event.exception_mask != 0 && + (event.exception_mask & KFD_EC_MASK(EC_PROCESS_RUNTIME)) == 0) { + // Forwarding a queue exception needs the target's live GPU state, which + // only exists once it has opened /dev/kfd. A debugger may be attached + // before that, or still attached after the target closed the device, so + // this op has to guard the lookup the way its siblings above do. + if (target_proc == nullptr) + return -ESRCH; + auto *gpu = find_gpu(event.gpu_id); + if (!gpu || !gpu->soc) + return -ENODEV; + // Drop debug_sessions_mutex_ first: signal_queue_exception() takes the CU + // wave-state lock and waits up to a second for the target to observe the + // exception word, while the engine thread runs its issue loop under that + // same wave-state lock and calls back into the trap/watchpoint handlers, + // which take debug_sessions_mutex_. Holding it across the call inverts + // that order -- the inversion DISABLE and SUSPEND_QUEUES both avoid -- and + // would additionally stall every trap callback for the duration of the + // wait. Nothing below this point reads debug_sessions_ or session_it. + lk.unlock(); + bool delivered = false; + gpu->soc->for_each_cp([&](amdgpu::CommandProcessor *cp) { + delivered |= cp->signal_queue_exception(event.queue_id, target_proc->process_id(), + event.exception_mask); + }); + return delivered ? 0 : -ENOENT; + } + std::lock_guard runtime_lock(runtime_handshake_mutex_); + runtime_acked_.insert(target_pid); + runtime_handshake_cv_.notify_all(); + return 0; + } case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED: - case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: + // kfd_dbg_set_enabled_debug_exception_mask(): record the exceptions the + // debugger wants forwarded. Delivery is wired up with the event channel. + session_it->second.exception_enable_mask = args->set_exceptions_enabled.exception_mask; + return 0; + case KFD_IOC_DBG_TRAP_SET_FLAGS: { + const uint32_t previous = session_it->second.flags; + session_it->second.flags = args->set_flags.flags; + args->set_flags.flags = previous; + return 0; + } case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE: - case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: - case KFD_IOC_DBG_TRAP_RESUME_QUEUES: - case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: - case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: - case KFD_IOC_DBG_TRAP_SET_FLAGS: + if (args->launch_mode.launch_mode != KFD_DBG_TRAP_WAVE_LAUNCH_MODE_NORMAL && + args->launch_mode.launch_mode != KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT && + args->launch_mode.launch_mode != KFD_DBG_TRAP_WAVE_LAUNCH_MODE_DEBUG) + return -EINVAL; + session_it->second.launch_mode = args->launch_mode.launch_mode; + return 0; + case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE: { + if (args->launch_override.override_mode != KFD_DBG_TRAP_OVERRIDE_OR) + return -EINVAL; + constexpr uint32_t kGfx94SupportedTrapMask = KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH; + if ((args->launch_override.support_request_mask & ~kGfx94SupportedTrapMask) != 0) + return -EACCES; + const uint32_t previous = session_it->second.launch_override_enable; + session_it->second.launch_override_enable = args->launch_override.enable_mask; + args->launch_override.enable_mask = previous; + args->launch_override.support_request_mask = kGfx94SupportedTrapMask; + return 0; + } + case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH: { + auto &watches = session_it->second.address_watches; + uint32_t slot = 0; + while (slot < KfdProcess::DebugSession::kMaxAddressWatches && watches[slot].active) + ++slot; + if (slot == KfdProcess::DebugSession::kMaxAddressWatches) + return -ENOMEM; + watches[slot] = KfdProcess::DebugSession::AddressWatch::from_kfd( + args->set_node_address_watch.address, args->set_node_address_watch.mask, + args->set_node_address_watch.mode); + args->set_node_address_watch.id = slot; + return 0; + } + case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH: { + const uint32_t slot = args->clear_node_address_watch.id; + if (slot >= KfdProcess::DebugSession::kMaxAddressWatches) + return -EINVAL; + session_it->second.address_watches[slot] = {}; + return 0; + } case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT: - case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: - case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: - return -ENOSYS; + return debug_query_event(target_pid, target_proc, session_it->second.exception_enable_mask, + args->query_debug_event); + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: { + if (args->suspend_queues.num_queues != 0 && args->suspend_queues.queue_array_ptr == 0) + return -EFAULT; + auto *queue_ids = + reinterpret_cast(static_cast(args->suspend_queues.queue_array_ptr)); + // Engine callbacks enter with a CU's wave-state lock and briefly acquire + // debug_sessions_mutex_. Do not invert that order while freezing CUs. + lk.unlock(); + const int result = suspend_debug_queues(target_proc, queue_ids, args->suspend_queues.num_queues, + args->suspend_queues.exception_mask); + clear_completed_debug_queues(target_proc, queue_ids, args->suspend_queues.num_queues); + return result; + } + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: { + if (args->resume_queues.num_queues != 0 && args->resume_queues.queue_array_ptr == 0) + return -EFAULT; + auto *queue_ids = + reinterpret_cast(static_cast(args->resume_queues.queue_array_ptr)); + lk.unlock(); + return resume_debug_queues(target_proc, queue_ids, args->resume_queues.num_queues); + } default: return -EINVAL; } @@ -2290,6 +4303,58 @@ int SimulatedKfd::debug_device_snapshot(kfd_ioctl_dbg_trap_device_snapshot_args return 0; } +int SimulatedKfd::debug_queue_snapshot(KfdProcess *target, + kfd_ioctl_dbg_trap_queue_snapshot_args &args) { + // Mirrors pqm_get_queue_snapshot(): report the total queue count, fill only + // the caller's capacity, and use the input entry size as the output stride. + const uint32_t in_num = args.num_queues; + const uint32_t in_entry_size = args.entry_size; + + args.num_queues = 0; + if (in_entry_size == 0) + return -EINVAL; + args.entry_size = std::min(in_entry_size, sizeof(kfd_queue_snapshot_entry)); + + std::vector entries; + if (target != nullptr) { + std::lock_guard lk(target->alloc_mutex_); + entries.reserve(std::min(in_num, target->active_queue_ids_.size())); + for (uint32_t qid : target->active_queue_ids_) { + auto it = target->queue_snapshot_map_.find(qid); + if (it == target->queue_snapshot_map_.end()) + continue; + if (args.num_queues < in_num) { + KfdProcess::QueueSnapshotInfo &q = it->second; + entries.push_back({ + .exception_status = q.exception_status, + .ring_base_address = q.ring_base_address, + .write_pointer_address = q.write_pointer_address, + .read_pointer_address = q.read_pointer_address, + .ctx_save_restore_address = q.ctx_save_restore_address, + .queue_id = qid, + .gpu_id = q.gpu_id, + .ring_size = q.ring_size, + .queue_type = q.queue_type, + .ctx_save_restore_area_size = q.ctx_save_restore_area_size, + .reserved = 0, + }); + q.exception_status &= ~args.exception_mask; + } + ++args.num_queues; + } + } + + if (entries.empty()) + return 0; + if (args.snapshot_buf_ptr == 0) + return -EFAULT; + + auto *out = reinterpret_cast(static_cast(args.snapshot_buf_ptr)); + for (size_t i = 0; i < entries.size(); ++i) + std::memcpy(out + static_cast(i) * in_entry_size, &entries[i], args.entry_size); + return 0; +} + int SimulatedKfd::set_xnack_mode_ioctl(void *arg) { auto *args = static_cast(arg); args->xnack_enabled = 0; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.h index 471e94cd6d59..9c97e28724c3 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_kfd.h @@ -19,14 +19,24 @@ RJ_DIAGNOSTIC_IGNORE_PEDANTIC RJ_DIAGNOSTIC_POP #include +#include #include +#include #include #include +#include #include #include namespace rocjitsu { +namespace amdgpu { +class Wavefront; +} + +namespace kmd { +struct CwsrWaveState; +} /// @brief 128-bit IPC share handle key, matching the kernel's random handle. struct IpcHandleKey { uint32_t words[4]; @@ -67,10 +77,15 @@ struct IpcObject { /// shared mutable state. class SimulatedKfd : public LinuxKfd { public: + /// @brief Test seam invoked between procfs authorization and pidfd revalidation. + using DebugIdentityValidationHook = std::function; + [[nodiscard]] bool daemon_mode() const { return daemon_mode_; } - SimulatedKfd(SoC &soc, bool daemon_mode = false); - SimulatedKfd(std::vector socs, std::vector gpu_ids, bool daemon_mode = false); + SimulatedKfd(SoC &soc, bool daemon_mode = false, + DebugIdentityValidationHook debug_identity_validation_hook = {}); + SimulatedKfd(std::vector socs, std::vector gpu_ids, bool daemon_mode = false, + DebugIdentityValidationHook debug_identity_validation_hook = {}); ~SimulatedKfd() override; /// @brief Local-mode interface (interposer). Operates on the local process. @@ -101,7 +116,8 @@ class SimulatedKfd : public LinuxKfd { uint32_t open_process(pid_t client_pid = 0); void set_process_client_pid(uint32_t process_id, pid_t client_pid); - int ioctl(uint32_t process_id, unsigned long request, void *arg); + int ioctl(uint32_t process_id, unsigned long request, void *arg, int *target_mem_fd = nullptr, + int target_proc_fd = -1); void *mmap(uint32_t process_id, void *addr, size_t length, int prot, int flags, off_t offset); int munmap(uint32_t process_id, void *addr, size_t length); int close(uint32_t process_id); @@ -193,6 +209,12 @@ class SimulatedKfd : public LinuxKfd { SoC *soc = nullptr; uint32_t gpu_id = 0; bool cps_initialized = false; + /// Whether the "no CWSR layout for this architecture" warning has been + /// logged for this GPU. The check now runs per faulting access rather than + /// once per stop, so the diagnostic is latched here -- per device, not per + /// ordinal, because gpu_ordinal() reports 0 for an unknown id and would + /// silence the real ordinal 0. + bool cwsr_layout_warned = false; kfd_process_device_apertures apertures{}; }; @@ -225,7 +247,8 @@ class SimulatedKfd : public LinuxKfd { void update_cp_doorbell_base(uint32_t gpu_ordinal, uint32_t process_id, void *base); - int dispatch_ioctl(KfdProcess &proc, unsigned long request, void *arg); + int dispatch_ioctl(KfdProcess &proc, unsigned long request, void *arg, + int *target_mem_fd = nullptr, int target_proc_fd = -1); void *dispatch_mmap(KfdProcess &proc, void *addr, size_t length, int prot, int flags, off_t offset); int dispatch_munmap(KfdProcess &proc, void *addr, size_t length); @@ -260,8 +283,123 @@ class SimulatedKfd : public LinuxKfd { int ipc_import_handle_ioctl(KfdProcess &proc, void *arg); int svm_ioctl(KfdProcess &proc, void *arg); int runtime_enable_ioctl(KfdProcess &proc, void *arg); - int debug_trap_ioctl(KfdProcess &caller, void *arg); + int debug_trap_ioctl(KfdProcess &caller, void *arg, int *target_mem_fd, int target_proc_fd); + void reap_exited_debug_sessions(std::stop_token stop); int debug_device_snapshot(kfd_ioctl_dbg_trap_device_snapshot_args &args); + int debug_queue_snapshot(KfdProcess *target, kfd_ioctl_dbg_trap_queue_snapshot_args &args); + int debug_query_event(pid_t target_pid, KfdProcess *target_proc, uint64_t enabled_mask, + kfd_ioctl_dbg_trap_query_debug_event_args &args); + int debug_query_exception_info(pid_t target_pid, + kfd_ioctl_dbg_trap_query_exception_info_args &args); + void raise_process_debug_event(pid_t target_pid, uint64_t exception_mask); + /// @brief Report an EC_PROCESS_RUNTIME transition to the attached debugger. + /// @param enabling True to block for the debugger's ack under the liveness + /// deadline. A disable transition is reported and returns immediately: + /// the ioctl is served on the daemon's connection thread for a client + /// that is already exiting, so parking it there parks the client. + void runtime_debugger_handshake(pid_t target_pid, bool enabling); + + std::optional + resolve_trap_handler(const amdgpu::Wavefront &wf, uint32_t gpu_ordinal); + bool on_wave_sendmsg(amdgpu::Wavefront &wf, uint32_t message); + void on_wave_trap_complete(amdgpu::Wavefront &wf); + + bool on_wave_single_step_complete(amdgpu::Wavefront &wf); + void notify_debug_event(const std::shared_ptr &proc, uint32_t queue_id, + uint32_t gpu_id, + uint64_t exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP)); + /// @brief Publish a wave stop: serialize the queue, then wake the debugger. + /// @returns True if the CWSR record was written and the event raised. On + /// false nothing was published and the caller must undo the stop it claimed: + /// the debugger has no record to read, so a wave left halted is invisible to + /// it and can never be resumed. + [[nodiscard]] bool report_wave_stopped(const std::shared_ptr &proc, uint32_t queue_id, + uint32_t gpu_id, uint64_t ctx_base, uint32_t ctx_size, + uint64_t exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP)); + + /// @brief Whether a wave stop on @p gpu_id could be published to a debugger. + /// @details Checked *before* a handler claims a stop. The CWSR codec models + /// the gfx9.4 record layout only (kmd/linux/cwsr.h), and serialization is the + /// last step of reporting a stop -- by the time it can refuse, the wave is + /// halted and the compute unit has been told the faulting access was handled. + /// Asking first lets the handler decline the stop instead, which is a path + /// every call site already supports. + /// @param gpu_id KFD GPU id of the queue whose wave would stop. + bool debug_stop_publishable(uint32_t gpu_id); + int resume_debug_queues(KfdProcess *proc, uint32_t *queue_ids, uint32_t num_queues); + void apply_cwsr_to_wave(amdgpu::Wavefront &wf, const kmd::CwsrWaveState &state); + + /// @brief Address-watchpoint handler installed on every compute unit. + /// @details Runs on the engine thread for each active-lane global-memory + /// access. If the address matches one of the debugger's address watchpoints + /// (compared under its mask, with a matching access mode), stops the wave with + /// the corresponding TRAPSTS.addr_watch bit set and reports it. Returns true + /// if the wave was stopped. @param addr post-translation global address; + /// @param bytes access width; @param is_write store/atomic; @param is_atomic + /// atomic read-modify-write. + bool on_wave_watchpoint(amdgpu::Wavefront &wf, uint64_t addr, uint32_t bytes, bool is_write, + bool is_atomic); + bool on_wave_illegal_instruction(amdgpu::Wavefront &wf); + bool on_wave_alu_exception(amdgpu::Wavefront &wf); + + /// @brief Memory-violation handler installed on every compute unit. + /// @details Runs on the engine thread for a global-memory access to an + /// unmapped address. If the wave's process is being debugged, sets + /// TRAPSTS.xnack_error, stops the wave, and reports an + /// EC_QUEUE_WAVE_MEMORY_VIOLATION exception (rocm-dbgapi + /// WAVE_STOP_REASON_MEMORY_VIOLATION); returns true, else false. + bool on_wave_memory_violation(amdgpu::Wavefront &wf, uint64_t addr, bool is_write); + + /// @brief Toggle per-access debugger checks on every compute unit. + void set_debug_active_on_all_cus(bool active); + + /// @brief Undo everything a debug session imposed on its inferior. + /// @details Resumes waves the departing debugger left stopped, reopens the + /// queue launch gates, clears per-queue exception status and queued debug + /// events, and revokes target-memory routing. Explicit detach and debugger + /// death must both run this, or a debugger that dies while a wave is stopped + /// strands the inferior's GPU work forever. + /// @param target_pid Client pid whose session has just been erased. + /// @note Must be called with debug_sessions_mutex_ *unlocked*: it takes CU + /// wave-state locks, and the engine thread takes those before + /// debug_sessions_mutex_. + /// @param target_proc The debuggee, resolved while the session still pinned + /// its identity. Re-resolving by pid inside the release would race pid reuse: + /// the reaper runs after the inferior may already have exited, and clearing + /// exception status, queue gates, wave stop bits and memory routing on an + /// innocent process that inherited the number is worse than leaking them. + /// Callers that resolved a std::shared_ptr must keep it alive across the + /// call; @p target_proc is borrowed, and may be nullptr when the debuggee has + /// already gone (only the queued events are then purged). + void release_debuggee_state(pid_t target_pid, KfdProcess *target_proc); + + /// @brief Revoke a process's target-memory routing on every GPU. + void revoke_target_mem_routing(uint32_t process_id); + + /// @brief Turn per-access debugger checks back off once no session wants them. + /// @note Takes debug_sessions_mutex_, so it must be called with that unlocked. + void release_debug_checks_if_last_session(); + + /// @brief Duplicate the authorized target-memory fd for lock-free I/O. + util::UniqueHandle duplicate_debug_target_mem(pid_t target_pid) const; + + /// @brief Serialize all debug-halted waves of a queue into its CWSR area. + bool serialize_queue_debug_waves(uint32_t process_id, uint32_t queue_id, uint32_t gpu_id, + uint64_t ctx_base, uint32_t ctx_size); + + /// @brief Stop the target's running waves and refresh their CWSR areas + /// (KFD_IOC_DBG_TRAP_SUSPEND_QUEUES). + int suspend_debug_queues(KfdProcess *proc, uint32_t *queue_ids, uint32_t num_queues, + uint64_t exception_mask); + + /// @brief Clear the CWSR area of any of the target's queues whose stopped waves + /// have completed, so rocm-dbgapi prunes them cleanly instead of reading a + /// stale wave against an advanced read_dispatch_id (KFD_IOC_DBG_TRAP_SUSPEND). + void clear_completed_debug_queues(KfdProcess *proc, const uint32_t *queue_ids, + uint32_t num_queues); + /// @brief Record a debug exception on a queue and reflect it on the snapshot. + void raise_debug_event(const std::shared_ptr &proc, uint32_t queue_id, + uint32_t gpu_id, uint64_t exception_mask); /// @brief Compute the LDS/scratch/GPUVM apertures for a GPU ordinal. /// @details Each further ordinal shifts the per-GPU LDS/scratch windows by @@ -299,12 +437,12 @@ class SimulatedKfd : public LinuxKfd { /// op_mutex_ < process_mutex_ /// op_mutex_ < alloc_mutex_ < {ipc_mutex_, page_table_mutex_, owned_fds_mutex_} /// op_mutex_ < runtime_mutex_ < alloc_mutex_ (runtime_enable_ioctl) - /// op_mutex_ < debug_mutex_ < runtime_mutex_ (debug_trap_ioctl) + /// op_mutex_ < debug_sessions_mutex_ < runtime_mutex_ (debug_trap_ioctl) /// process_mutex_ < interrupt_mutex_ (open()/open_process()) - /// The op_mutex_ in the debug rule is always the CALLER's, while debug_mutex_/ - /// runtime_mutex_ may belong to a DIFFERENT process (the debug target resolved - /// by client pid). debug_trap_ioctl holds only the caller's op_mutex_ and never - /// acquires the target's op_mutex_, so a cross-process attach cannot deadlock. + /// The op_mutex_ in the debug rule is always the CALLER's, while runtime_mutex_ + /// may belong to a DIFFERENT process (the debug target resolved by client pid). + /// debug_trap_ioctl holds only the caller's op_mutex_ and never acquires the + /// target's op_mutex_, so a cross-process attach cannot deadlock. /// interrupt_mutex_ is a leaf: the CP interrupt callback takes it and only /// descends into EventState::mutex_, and close() takes it only after releasing /// process_mutex_, so there is no cycle. @@ -319,6 +457,39 @@ class SimulatedKfd : public LinuxKfd { std::unordered_map> processes_; uint32_t next_process_id_ = 1; + /// @brief Debugger sessions keyed by the target inferior's Linux pid. + /// @details Decoupled from KfdProcess so a debugger (rocgdb) can enable a + /// session on an inferior before the inferior opens /dev/kfd, mirroring the + /// kernel creating the target kfd_process in the DBG_TRAP_ENABLE path. + mutable std::mutex debug_sessions_mutex_; + std::unordered_map debug_sessions_; + DebugIdentityValidationHook debug_identity_validation_hook_; + std::condition_variable_any debug_sessions_cv_; + std::jthread debug_session_reaper_; + + /// @brief Pending debug exceptions per target, grouped by queue. + /// @details Populated by wave traps (engine thread) and drained by + /// KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT (ioctl thread). Never held together + /// with debug_sessions_mutex_ by the wave-trap path (lock ordering). + struct DebugQueueException { + uint32_t gpu_id = 0; + uint64_t mask = 0; + }; + mutable std::mutex debug_events_mutex_; + std::unordered_map> debug_events_; + + mutable std::mutex runtime_handshake_mutex_; + std::condition_variable runtime_handshake_cv_; + std::unordered_set runtime_acked_; + /// @brief Targets whose debugger went away while RUNTIME_ENABLE was waiting. + /// @details A detaching or dying debugger will never send the ack, so the + /// teardown paths record the pid here and wake the waiter instead of leaving + /// the inferior blocked until the safety deadline. + std::unordered_set runtime_handshake_cancelled_; + + /// @brief Release any RUNTIME_ENABLE waiter for @p target_pid. + void cancel_runtime_handshake(pid_t target_pid); + /// @brief Interrupt dispatch: process_id → EventState*. /// @details Protected by interrupt_mutex_. Decoupled from process_mutex_ /// to avoid ABBA deadlocks with hw_queue_mutex_ in the CP doorbell thread. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp index 28afd4705dff..9a291886378d 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp @@ -67,12 +67,15 @@ static_assert(kMaxClusterWorkgroups <= kClusterMulticastMaskBits); static_assert(kMaxClusterWorkgroups <= 16, "TTMP6 cluster max and max-flat-ID fields are 4 bits wide"); -// GFX12 launch-state scalar selectors used by compiler-generated workgroup -// and cluster identity sequences. -constexpr uint32_t kGfx12Ttmp6 = 114; -constexpr uint32_t kGfx12Ttmp7 = 115; -constexpr uint32_t kGfx12Ttmp8 = 116; -constexpr uint32_t kGfx12Ttmp9 = 117; +// GFX12 launch-state TTMP indices used by compiler-generated workgroup and +// cluster identity sequences. These are indices into the wave's trap-temporary +// file (Wavefront::ttmp()), not SGPR numbers: the shader reaches them through +// the TTMP operand encodings (scalar selectors 108..123), which the ISA decoder +// routes to that file rather than to the SGPR allocation. +constexpr uint32_t kGfx12Ttmp6 = 6; +constexpr uint32_t kGfx12Ttmp7 = 7; +constexpr uint32_t kGfx12Ttmp8 = 8; +constexpr uint32_t kGfx12Ttmp9 = 9; // LLVM's gfx1250 architected-SGPR ABI maps TTMP6 as seven 4-bit fields: // cluster-local XYZ, cluster-max XYZ, and max-flat-ID from low to high bits. @@ -296,8 +299,10 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, if (AMDHSA_BITS_GET(kcp, KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER)) { if (pkt.queue_ptr != 0) { uint64_t srd_va = pkt.queue_ptr + offsetof(amd_queue_t, scratch_resource_descriptor); - cu->write_sgpr(sbase + idx + 0, read_gpu_u32(srd_va + 0, pkt.process_id)); - cu->write_sgpr(sbase + idx + 1, read_gpu_u32(srd_va + 4, pkt.process_id)); + const uint32_t srd0 = read_gpu_u32(srd_va + 0, pkt.process_id); + const uint32_t srd1 = read_gpu_u32(srd_va + 4, pkt.process_id); + cu->write_sgpr(sbase + idx + 0, srd0); + cu->write_sgpr(sbase + idx + 1, srd1); cu->write_sgpr(sbase + idx + 2, read_gpu_u32(srd_va + 8, pkt.process_id)); cu->write_sgpr(sbase + idx + 3, read_gpu_u32(srd_va + 12, pkt.process_id)); } @@ -391,13 +396,6 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, } const auto properties = isa_properties(cu->arch()); if (properties.uses_ttmp_workgroup_ids) { - // The simulator aliases TTMP scalar selectors into the wavefront SGPR - // block, so the block must include slots through TTMP9. - if (cu->config().sgprs_per_wf <= kGfx12Ttmp9) { - throw std::runtime_error("TTMP workgroup-ID launch payload requires at least 118 SGPR " - "slots per wavefront"); - } - // The ordinary TTMP ABI uses grid coordinates. Targets advertising the // clustered extension reinterpret these fields below. uint32_t ttmp6 = 0; @@ -432,10 +430,10 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, ttmp7 = (cluster_grid_z << 16) | cluster_grid_y; ttmp9 = grid_wg_id_x / cluster_size_x; } - cu->write_sgpr(sbase + kGfx12Ttmp6, ttmp6); - cu->write_sgpr(sbase + kGfx12Ttmp7, ttmp7); - cu->write_sgpr(sbase + kGfx12Ttmp8, ttmp8); - cu->write_sgpr(sbase + kGfx12Ttmp9, ttmp9); + wf->set_ttmp(kGfx12Ttmp6, ttmp6); + wf->set_ttmp(kGfx12Ttmp7, ttmp7); + wf->set_ttmp(kGfx12Ttmp8, ttmp8); + wf->set_ttmp(kGfx12Ttmp9, ttmp9); } // Workitem IDs per AMDHSA ABI. The SPI decomposes the flat thread index @@ -471,7 +469,12 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, uint64_t scratch_pool = pkt.scratch_backing_addr; if (scratch_pool == 0) scratch_pool = 0x1'0000'0000ULL; - uint64_t per_wave_size = static_cast(pkt.private_segment_fixed_size) * cu->wf_size(); + // Round the per-wave region to the 1 KB COMPUTE_TMPRING_SIZE.WAVESIZE granule + // so that each wave's base equals scratch_pool + scoreboard_id * wavesize, + // which is exactly what rocm-dbgapi computes to locate a wave's private + // memory (rocdbgapi architecture.cpp scratch_memory_region). + uint64_t raw_per_wave = static_cast(pkt.private_segment_fixed_size) * cu->wf_size(); + uint64_t per_wave_size = ((raw_per_wave + 1023) / 1024) * 1024; uint32_t wg_total_size = static_cast(pkt.workgroup_size_x) * std::max(1, pkt.workgroup_size_y) * std::max(1, pkt.workgroup_size_z); @@ -487,6 +490,18 @@ void CommandProcessor::init_wavefront_regs(ComputeUnitCore *cu, Wavefront *wf, wf->set_scratch_base(wave_scratch); wf->set_scratch_lane_size(pkt.private_segment_fixed_size); + // The scoreboard id is this wave's slot in the queue's scratch allocation; + // rocm-dbgapi multiplies it by the per-wave size to find the wave's scratch. + wf->set_scratch_scoreboard_id(static_cast(global_wave_idx)); + // CDNA compiler-generated functions use s32 as the private stack pointer + // and s33 as its current frame value for explicit scratch SADDR operands. + // The pointer is an offset within the per-wave scratch slice, not the SRD + // base address supplied in the user SGPR block. + if (cu->config().arch == ROCJITSU_CODE_ARCH_CDNA3 || + cu->config().arch == ROCJITSU_CODE_ARCH_CDNA4) { + cu->write_sgpr(sbase + 32, 32); + cu->write_sgpr(sbase + 33, 0); + } util::Logger::cp([&](auto &os) { os << std::format( "SCRATCH wf{} pool={:#x} wave_scratch={:#x} per_wave={} priv_size={} " @@ -575,8 +590,59 @@ void CommandProcessor::register_queue(HwQueue queue) { ensure_doorbell_monitor(); } +bool CommandProcessor::signal_queue_exception(uint32_t queue_id, uint32_t process_id, + uint64_t status) { + uint64_t exception_status_va = 0; + uint32_t exception_event_id = 0; + { + std::lock_guard lk(hw_queue_mutex_); + auto queue = std::find_if(hw_queues_.begin(), hw_queues_.end(), [&](const HwQueue &candidate) { + return candidate.queue_id == queue_id && candidate.process_id == process_id; + }); + if (queue == hw_queues_.end() || queue->exception_status_va == 0) + return false; + exception_status_va = queue->exception_status_va; + exception_event_id = queue->exception_event_id; + } + + memory_->write64(exception_status_va, status, process_id); + if (interrupt_cb_) + interrupt_cb_(process_id, exception_event_id); + const auto deadline = std::chrono::steady_clock::now() + std::chrono::seconds(1); + while (memory_->read64(exception_status_va, process_id) == status && + std::chrono::steady_clock::now() < deadline) + std::this_thread::yield(); + + for (auto *cu : cus_) { + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + auto *wave = cu->wf(slot); + if (!wave->is_halted() && wave->process_id() == process_id && wave->queue_id() == queue_id) + wave->set_debug_suspended(true); + } + }); + } + return true; +} + void CommandProcessor::unregister_queue(uint32_t queue_id, uint32_t process_id) { + // Holds hw_queue_mutex_ across with_wave_state_locked(), which is the order + // the dispatch path uses too (handle_doorbell -> dispatch_workgroups -> + // dispatch_wf). Nothing takes them the other way any more: a wave reaching + // s_endpgm under the wave-state lock queues its completion instead of sending + // it, and WaveStateGuard delivers it after that lock is dropped. Keep it that + // way -- a CU-side call back into the CP while the wave-state lock is held + // would deadlock a DESTROY_QUEUE against the engine worker. std::lock_guard lock(hw_queue_mutex_); + for (auto *cu : cus_) { + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + auto *wave = cu->wf(slot); + if (!wave->is_halted() && wave->process_id() == process_id && wave->queue_id() == queue_id) + wave->halt(); + } + }); + } for (size_t i = 0; i < hw_queues_.size(); ++i) { if (hw_queues_[i].queue_id == queue_id && hw_queues_[i].process_id == process_id) { hw_queues_.erase(hw_queues_.begin() + static_cast(i)); @@ -591,15 +657,86 @@ void CommandProcessor::unregister_queue(uint32_t queue_id, uint32_t process_id) } void CommandProcessor::update_queue(uint32_t queue_id, uint32_t process_id, uint64_t ring_base_va, - uint32_t ring_size) { - std::lock_guard lock(hw_queue_mutex_); - for (auto &q : hw_queues_) { - if (q.queue_id == queue_id && q.process_id == process_id) { - q.ring_base_va = ring_base_va; - q.ring_size = ring_size; - break; + uint32_t ring_size, uint32_t queue_percentage) { + const bool suspended = queue_percentage == 0; + bool changed = false; + bool wake_command_processor = false; + { + std::lock_guard lock(hw_queue_mutex_); + for (auto &q : hw_queues_) { + if (q.queue_id == queue_id && q.process_id == process_id) { + q.ring_base_va = ring_base_va; + q.ring_size = ring_size; + changed = q.runtime_suspended != suspended; + q.runtime_suspended = suspended; + // Only consume the deferral once *no* reason still gates the queue. + // debug_work_deferred is shared by both suspend reasons, so clearing it + // here while the debugger still holds the gate would leave the later + // debugger resume with nothing to release, and the already-fetched + // packets would sit until an unrelated doorbell arrived. + if (changed && !suspended && !q.debug_suspended) + wake_command_processor = std::exchange(q.debug_work_deferred, false); + break; + } + } + } + if (!changed) + return; + for (auto *cu : cus_) { + cu->with_wave_state_locked([&] { + for (uint32_t slot = 0; slot < cu->num_wf_slots(); ++slot) { + auto *wave = cu->wf(slot); + if (!wave->is_halted() && wave->process_id() == process_id && wave->queue_id() == queue_id) + // The runtime's own pause reason. Writing the debugger's bit here let + // a runtime resume clear a debugger pause, and a debugger or CWSR + // resume clear an active runtime pause. + wave->set_runtime_suspended(suspended); + } + }); + if (!suspended) + cu->schedule_work_async(); + } + // Runtime resume has to release deferred queue work the same way a debugger + // resume does, or already-fetched work sits until the next doorbell. + if (wake_command_processor && engine()) + engine()->schedule_event_now(&doorbell_event_); +} + +void CommandProcessor::set_queue_debug_suspended(uint32_t queue_id, uint32_t process_id, + bool suspended) { + bool wake_command_processor = false; + { + std::lock_guard lock(hw_queue_mutex_); + for (size_t index = 0; index < hw_queues_.size(); ++index) { + auto &q = hw_queues_[index]; + if (q.queue_id == queue_id && q.process_id == process_id) { + if (q.debug_suspended == suspended) + continue; + q.debug_suspended = suspended; + if (suspended) { + // Existing queue work needs a resume pass only when the gate, rather + // than an earlier incomplete dispatch, is what prevents it from + // running. Resident waves are reactivated directly by KFD resume. + auto &state = new_queue_states_[index]; + // Accumulate: the flag is shared with the runtime's suspend reason, + // and fetch_from_queue() may already have recorded a deferral for a + // queue the runtime had gated. Assigning would discard it, leaving + // neither resume path with anything to release. + if (state.next_dispatch_idx < state.entries.size()) { + const auto &entry = state.entries[state.next_dispatch_idx]; + const bool barrier_ready = + !entry.barrier_bit || barrier_satisfied(state, state.next_dispatch_idx); + q.debug_work_deferred |= + barrier_ready && (entry.is_non_kernel() || !entry.fully_dispatched()); + } + } else if (!q.runtime_suspended) { + wake_command_processor |= std::exchange(q.debug_work_deferred, false); + } + } } } + if (wake_command_processor && engine()) + engine()->schedule_event_now(&doorbell_event_); } void CommandProcessor::set_doorbell_base(uint32_t process_id, void *base) { @@ -839,7 +976,8 @@ HwQueueState *CommandProcessor::schedule_next_queue() { for (size_t i = 0; i < new_queue_states_.size(); ++i) { size_t idx = (start + i) % new_queue_states_.size(); auto &qs = new_queue_states_[idx]; - if (hw_queues_[idx].is_sdma) + if (hw_queues_[idx].is_sdma || hw_queues_[idx].debug_suspended || + hw_queues_[idx].runtime_suspended) continue; if (qs.next_dispatch_idx < qs.entries.size()) { next_queue_idx_ = (idx + 1) % new_queue_states_.size(); @@ -866,7 +1004,7 @@ void CommandProcessor::register_cluster_workgroup(const DispatchEntry &entry, ui uint32_t lds_base) { if (!entry.has_workgroup_clusters()) return; - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); uint32_t cluster_base_wg_id = entry.cluster_base_local_wg_id(local_wg_id) + entry.workgroup_id_offset; uint64_t cluster_key = wg_key(entry.dispatch_id, cluster_base_wg_id); @@ -926,7 +1064,7 @@ bool CommandProcessor::find_valid_cluster_barrier_locked( } bool CommandProcessor::cluster_barrier_valid(const Wavefront &wf, int32_t barrier_id) const { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); const ClusterWorkgroupPlacement *placement = nullptr; const ClusterBarrierState *barriers = nullptr; return find_valid_cluster_barrier_locked(wf, barrier_id, placement, barriers); @@ -934,7 +1072,7 @@ bool CommandProcessor::cluster_barrier_valid(const Wavefront &wf, int32_t barrie uint32_t CommandProcessor::cluster_barrier_state(const Wavefront &wf, int32_t barrier_id, uint32_t allocation_blocks) const { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); const ClusterWorkgroupPlacement *placement = nullptr; const ClusterBarrierState *barriers = nullptr; if (!find_valid_cluster_barrier_locked(wf, barrier_id, placement, barriers)) @@ -950,7 +1088,7 @@ bool CommandProcessor::cluster_barrier_signal(Wavefront &wf, int32_t barrier_id) std::vector> peers; const uint8_t completion_bit = static_cast(-barrier_id); { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); ClusterWorkgroupPlacement *placement = nullptr; ClusterBarrierState *barriers = nullptr; if (!find_valid_cluster_barrier_locked(wf, barrier_id, placement, barriers)) @@ -984,17 +1122,19 @@ bool CommandProcessor::cluster_barrier_signal(Wavefront &wf, int32_t barrier_id) } void CommandProcessor::mark_cluster_workgroup_complete(uint32_t dispatch_id, uint32_t wg_id) { + // Cluster barriers resolve here, but complete_barrier() and the LDS reclaim + // both reach into a CU. Collect them under the lock and act after it is + // dropped -- see cluster_placements_mutex_. std::array>, 2> resolved_peers; - std::vector retired_cus; - uint64_t cluster_key = 0; + std::vector> unpin; { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); auto it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); if (it == cluster_wg_placements_.end() || it->second.completed) return; it->second.completed = true; - cluster_key = it->second.cluster_key; + const uint64_t cluster_key = it->second.cluster_key; const auto peer_wg_ids = it->second.peer_wg_ids; auto barrier_it = cluster_barriers_.find(cluster_key); if (barrier_it != cluster_barriers_.end() && barrier_it->second.member_count != 0) { @@ -1018,13 +1158,11 @@ void CommandProcessor::mark_cluster_workgroup_complete(uint32_t dispatch_id, uin auto peer = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); return peer != cluster_wg_placements_.end() && peer->second.completed; }); - if (!all_completed) - cluster_key = 0; - else { + if (all_completed) { for (uint32_t peer_wg_id : peer_wg_ids) { auto peer = cluster_wg_placements_.find(wg_key(dispatch_id, peer_wg_id)); if (peer != cluster_wg_placements_.end() && peer->second.cu) - retired_cus.push_back(peer->second.cu); + unpin.emplace_back(peer->second.cu, cluster_key); cluster_wg_placements_.erase(wg_key(dispatch_id, peer_wg_id)); } cluster_barriers_.erase(cluster_key); @@ -1042,59 +1180,59 @@ void CommandProcessor::mark_cluster_workgroup_complete(uint32_t dispatch_id, uin plugin_group_->onAmdgpuBarrierResolved(std::span(members)); } - if (cluster_key != 0) { - for (auto *cu : retired_cus) { - cu->unpin_lds_for_cluster(cluster_key); - // The waves halted before the pin was released, so reclaim LDS after - // every workgroup in the cluster has retired. - cu->maybe_reset_lds_alloc(); - } + release_cluster_lds_pins(unpin); +} + +// The waves halted (and freed) before their pin was released, so reclaim each +// peer CU's LDS once the whole cluster is done. Runs with +// cluster_placements_mutex_ released: maybe_reset_lds_alloc() reaches the CU's +// wave-state lock, which is ordered ahead of it. +void CommandProcessor::release_cluster_lds_pins( + const std::vector> &unpin) { + for (const auto &[cu, cluster_key] : unpin) { + cu->unpin_lds_for_cluster(cluster_key); + cu->maybe_reset_lds_alloc(); } } void CommandProcessor::erase_cluster_workgroup(uint32_t dispatch_id, uint32_t wg_id) { - ComputeUnitCore *cu = nullptr; - uint64_t cluster_key = 0; + // maybe_reset_lds_alloc() takes the CU's wave-state lock, so it runs after the + // placements lock is dropped -- see cluster_placements_mutex_. + std::vector> unpin; { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); auto it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); if (it == cluster_wg_placements_.end()) return; - cu = it->second.cu; - cluster_key = it->second.cluster_key; - cluster_barriers_.erase(cluster_key); + if (it->second.cu) + unpin.emplace_back(it->second.cu, it->second.cluster_key); + cluster_barriers_.erase(it->second.cluster_key); cluster_wg_placements_.erase(it); } - if (cu) { - cu->unpin_lds_for_cluster(cluster_key); - cu->maybe_reset_lds_alloc(); - } + release_cluster_lds_pins(unpin); } void CommandProcessor::erase_cluster_workgroups(uint32_t dispatch_id) { - std::vector> retired; + std::vector> unpin; { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); for (auto it = cluster_wg_placements_.begin(); it != cluster_wg_placements_.end();) { if ((it->first >> 32) == dispatch_id) { cluster_barriers_.erase(it->second.cluster_key); if (it->second.cu) - retired.emplace_back(it->second.cu, it->second.cluster_key); + unpin.emplace_back(it->second.cu, it->second.cluster_key); it = cluster_wg_placements_.erase(it); } else { ++it; } } } - for (auto [cu, cluster_key] : retired) { - cu->unpin_lds_for_cluster(cluster_key); - cu->maybe_reset_lds_alloc(); - } + release_cluster_lds_pins(unpin); } std::vector CommandProcessor::cluster_lds_targets(uint32_t dispatch_id, uint32_t wg_id, uint32_t mcast_mask) { - std::lock_guard lock(cluster_barrier_mutex_); + std::lock_guard lock(cluster_placements_mutex_); std::vector targets; auto src_it = cluster_wg_placements_.find(wg_key(dispatch_id, wg_id)); if (src_it == cluster_wg_placements_.end()) @@ -1207,9 +1345,16 @@ uint32_t CommandProcessor::dispatch_workgroups(DispatchEntry &entry) { wf->set_lds_size(aligned_lds_bytes_per_workgroup(entry)); wf->set_lds(placement.lds); wf->set_dispatch_id(entry.dispatch_id); + wf->set_aql_packet_id(entry.aql_packet_id); + wf->set_code_load_bias(entry.code_load_bias); + wf->set_wave_in_group(w); wf->set_process_id(entry.process_id); wf->set_mode_raw(entry.initial_mode_raw); + wf->set_queue_id(entry.queue_id); wf->set_exec(initial_exec_mask_for_wave(entry, global_wg_id, w, cu->wf_size())); + const uint32_t relative_wg_id = global_wg_id - entry.workgroup_id_offset; + const WorkgroupCoord coord = entry.local_wg_coord(relative_wg_id); + wf->set_wg_coord(coord.x, coord.y, coord.z); wf->set_cluster_info(entry.cluster_rank_for_flat_wg_id(global_wg_id), entry.cluster_size()); try { init_wavefront_regs(cu, wf, entry, global_wg_id, w); @@ -1369,7 +1514,10 @@ void CommandProcessor::on_cu_idle() { // Retire any non-kernel entries (barriers with total_wgs==0) that are now at // the head, then drain again so a dependent kernel behind them can proceed. - for (auto &qs : new_queue_states_) { + for (size_t qi = 0; qi < new_queue_states_.size(); ++qi) { + if (hw_queues_[qi].debug_suspended || hw_queues_[qi].runtime_suspended) + continue; + auto &qs = new_queue_states_[qi]; while (qs.next_dispatch_idx < qs.entries.size()) { auto &e = qs.entries[qs.next_dispatch_idx]; if (e.barrier_bit && !barrier_satisfied(qs, qs.next_dispatch_idx)) @@ -1388,8 +1536,16 @@ void CommandProcessor::on_cu_idle() { // dispatch continuation through the doorbell path; across the many tiny kernels // of an RCCL collective the engine would idle a full tick between steps, adding // latency the host socket layer then paid for. dispatch_workgroups() schedules - // the CU's own tick event, so no explicit CU nudge is needed here. - for (auto &qs : new_queue_states_) { + // the CU's own tick event in the ordinary case. Record quiesced CUs because a + // CU containing only debug-halted waves needs an explicit activation when a + // newly dispatched wave makes it runnable again. + std::vector was_idle(cus_.size()); + for (size_t i = 0; i < cus_.size(); ++i) + was_idle[i] = cus_[i]->is_idle(); + for (size_t qi = 0; qi < new_queue_states_.size(); ++qi) { + if (hw_queues_[qi].debug_suspended || hw_queues_[qi].runtime_suspended) + continue; + auto &qs = new_queue_states_[qi]; if (qs.next_dispatch_idx < qs.entries.size()) { auto &entry = qs.entries[qs.next_dispatch_idx]; if (entry.barrier_bit && !barrier_satisfied(qs, qs.next_dispatch_idx)) @@ -1401,6 +1557,10 @@ void CommandProcessor::on_cu_idle() { } } } + for (size_t i = 0; i < cus_.size(); ++i) { + if (was_idle[i] && !cus_[i]->is_idle()) + cus_[i]->schedule_work(); + } } bool CommandProcessor::step() { @@ -1411,7 +1571,8 @@ bool CommandProcessor::step() { void CommandProcessor::process_queues() { for (size_t qi = 0; qi < new_queue_states_.size(); ++qi) { - if (hw_queues_[qi].is_sdma) + if (hw_queues_[qi].is_sdma || hw_queues_[qi].debug_suspended || + hw_queues_[qi].runtime_suspended) continue; auto &qs = new_queue_states_[qi]; while (qs.next_dispatch_idx < qs.entries.size()) { @@ -1459,6 +1620,7 @@ static const uint8_t *find_elf_base(const uint8_t *ptr, const uint8_t *limit) { void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pkt, const HwQueue &queue, uint64_t pkt_addr, uint32_t queue_packet_id, HwQueueState &qs, + uint64_t aql_packet_id, ClusterDispatchShape cluster_shape) { bool host_accessible = queue.host_accessible; using namespace rocr::llvm::amdhsa; @@ -1473,6 +1635,7 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk uint32_t sgprs = sgpr_count_is_descriptor_encoded(arch, sgpr_gran) ? (sgpr_gran + 1) * 8 : 0; uint32_t user_sgprs = AMDHSA_BITS_GET(kd.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT); uint64_t entry_pc = pkt.kernel_object + static_cast(kd.kernel_code_entry_byte_offset); + uint64_t code_load_bias = 0; uint32_t wg_size = static_cast(pkt.workgroup_size_x) * pkt.workgroup_size_y * pkt.workgroup_size_z; @@ -1494,6 +1657,7 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.queue_id = queue.queue_id; dp.queue_packet_id = queue_packet_id; dp.process_id = queue.process_id; + dp.aql_packet_id = static_cast(aql_packet_id); dp.kernel_entry_pc = entry_pc; dp.total_wgs = total_wgs; dp.dispatched_wgs = 0; @@ -1501,7 +1665,10 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.wfs_per_workgroup = wfs_per_wg; uint32_t sgpr_limit = cus_.empty() ? 112 : cus_[0]->config().sgprs_per_wf; uint32_t vgpr_limit = cus_.empty() ? 256 : cus_[0]->vgpr_allocation_block_size(); - dp.sgprs_per_wf = std::min(sgprs > 0 ? sgprs : sgpr_limit, sgpr_limit); + uint32_t required_sgprs = sgprs > 0 ? sgprs : sgpr_limit; + if (arch == ROCJITSU_CODE_ARCH_CDNA3 || arch == ROCJITSU_CODE_ARCH_CDNA4) + required_sgprs = std::max(required_sgprs, 34u); // s32 stack pointer, s33 frame pointer + dp.sgprs_per_wf = std::min(required_sgprs, sgpr_limit); dp.vgprs_per_wf = std::min(vgprs > 0 ? vgprs : vgpr_limit, vgpr_limit); dp.kernarg_addr = reinterpret_cast(pkt.kernarg_address); dp.kernarg_size = kd.kernarg_size; @@ -1552,6 +1719,32 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk dp.scratch_backing_addr = read_gpu_u64(scratch_loc_va, queue.process_id); if (dp.scratch_backing_addr == 0 && scratch_resolver_) dp.scratch_backing_addr = scratch_resolver_(queue.process_id); + + // Publish the scratch backing location and COMPUTE_TMPRING_SIZE into the + // ABI-stable part of amd_queue_t so rocm-dbgapi can compute each wave's + // private (scratch) memory region, letting ROCgdb read scratch-resident + // variables. Real CP firmware populates these when it assigns scratch to + // the queue; the emulator's ROCr instead sets the backing via + // SET_SCRATCH_BACKING_VA and leaves these fields zero, so the CP fills + // them here. Field layout per rocdbgapi architecture.cpp + // gfx9_architecture_t::scratch_memory_region: waves = tmpring[0:11], + // wavesize = tmpring[12:24] * 1024 bytes. + if (dp.scratch_backing_addr != 0 && !cus_.empty()) { + uint64_t per_wave_bytes = + static_cast(dp.private_segment_fixed_size) * cus_[0]->wf_size(); + uint32_t wavesize_kb = static_cast((per_wave_bytes + 1023) / 1024); + // The WAVES field must be a nonzero multiple of the shader-engine-per-XCC + // count, or rocm-dbgapi disables private access (scratch_memory_region + // warns and returns size 0). Round the dispatch's wave count up to it. + uint32_t se = std::max(1u, scratch_wave_divisor_); + uint64_t total_waves = static_cast(total_wgs) * wfs_per_wg; + uint32_t waves_field = + static_cast(((std::max(1, total_waves) + se - 1) / se) * se); + uint32_t tmpring = (waves_field & 0xFFFu) | ((wavesize_kb & 0x1FFFu) << 12); + memory_->write64(scratch_loc_va, dp.scratch_backing_addr, queue.process_id); + memory_->write32(dp.queue_ptr + offsetof(amd_queue_t, compute_tmpring_size), tmpring, + queue.process_id); + } } } @@ -1611,12 +1804,16 @@ void CommandProcessor::process_aql_packet(const hsa_kernel_dispatch_packet_t &pk auto *host_range_begin = reinterpret_cast(host_range_base); auto *elf_base = find_elf_base(kernel_object_host_ptr, host_range_begin); if (elf_base) { + const uint64_t kernel_offset = static_cast(kernel_object_host_ptr - elf_base); + if (pkt.kernel_object >= kernel_offset) + code_load_bias = pkt.kernel_object - kernel_offset; uint64_t elf_accessible = host_range_size - static_cast(elf_base - host_range_begin); kernel_symbol = find_kernel_symbol(kernel_object_host_ptr, elf_base, elf_accessible); } } } + dp.code_load_bias = code_load_bias; std::string kernel_name = kernel_display_name(kernel_symbol); ++total_dispatched_; @@ -1685,6 +1882,17 @@ void CommandProcessor::arm_stall_recheck(simdojo::Tick now) { void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdojo::Tick now) { if (!memory_) return; + if (queue.debug_suspended || queue.runtime_suspended) { + // A command-processor event can race a debugger suspension even when this + // queue has no new packets. Do not turn that stale event into an endless + // resume/event chain: request a resume pass only when packet fetch really + // was deferred. Compute queues count packets; SDMA queues count bytes. + const uint64_t write_idx = read_gpu_u64(queue.write_ptr_va, queue.process_id); + const uint64_t read_idx = read_gpu_u64(queue.read_ptr_va, queue.process_id); + const uint64_t fetch_idx = queue.is_sdma ? read_idx : std::max(read_idx, queue.fetch_cursor); + queue.debug_work_deferred |= fetch_idx < write_idx; + return; + } if (queue.host_accessible ? (queue.doorbell_base == nullptr) : (queue.doorbell_va == 0)) return; @@ -1722,6 +1930,12 @@ void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdoj } // AQL doorbell clamping (compute queues only). + // Use the CP-private fetch cursor as the authoritative next-packet index. It + // normally equals read_ptr_va (the CP is the sole writer of a compute queue's + // read pointer), but while the debugger holds read_ptr_va at a trapped + // dispatch, the cursor stays ahead so already-dispatched packets are not + // re-fetched. + read_idx = std::max(read_idx, queue.fetch_cursor); uint64_t process_limit = write_idx; if (queue.host_accessible) { const uint64_t doorbell = queue.last_doorbell; @@ -1791,7 +2005,7 @@ void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdoj } if (pkt_type == HSA_PACKET_TYPE_KERNEL_DISPATCH) { - process_aql_packet(pkt, queue, pkt_addr, slot, qs); + process_aql_packet(pkt, queue, pkt_addr, slot, qs, read_idx); } else if (pkt_type == HSA_PACKET_TYPE_BARRIER_AND || pkt_type == HSA_PACKET_TYPE_BARRIER_OR) { constexpr uint32_t DEP_OFF = 8; constexpr uint32_t SIG_OFF = 56; @@ -1951,7 +2165,7 @@ void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdoj cluster_shape.size_x = ext.cluster_size_x; cluster_shape.size_y = ext.cluster_size_y; cluster_shape.size_z = ext.cluster_size_z; - process_aql_packet(dispatch, queue, pkt_addr, slot, qs, cluster_shape); + process_aql_packet(dispatch, queue, pkt_addr, slot, qs, read_idx, cluster_shape); } else if (ext.amd_format == kAmdAqlFormatPm4Ib) { constexpr uint32_t SIG_OFF = 56; const uint64_t sig = read_gpu_u64(pkt_addr + SIG_OFF, queue.process_id); @@ -1979,9 +2193,14 @@ void CommandProcessor::fetch_from_queue(HwQueue &queue, HwQueueState &qs, simdoj for (uint32_t i = 0; i < sizeof(process_limit); ++i) memory_->write8(queue.read_ptr_va + i, src[i], queue.process_id); } + // Advance the CP-private cursor to match. read_ptr_va may subsequently be + // lowered by the debugger to hold a trapped dispatch; the cursor is not, so + // the next fetch resumes here rather than re-fetching held packets. + queue.fetch_cursor = process_limit; } void CommandProcessor::handle_doorbell(simdojo::Tick now) { + doorbell_handle_count_.fetch_add(1, std::memory_order_relaxed); // Release so the doorbell poll thread's acquire-load cannot observe a stale // "pending" after this handler has re-fetched; pairs with the release-stores at // the INVALID-packet and barrier/dependency stall sites. A site that is still @@ -2019,7 +2238,8 @@ void CommandProcessor::handle_doorbell(simdojo::Tick now) { progress = false; for (size_t qi = 0; qi < hw_queues_.size(); ++qi) { - if (hw_queues_[qi].is_sdma) + if (hw_queues_[qi].is_sdma || hw_queues_[qi].debug_suspended || + hw_queues_[qi].runtime_suspended) continue; auto &qs = new_queue_states_[qi]; @@ -2118,6 +2338,8 @@ void CommandProcessor::handle_doorbell(simdojo::Tick now) { fetch_from_queue(hw_queues_[i], new_queue_states_[i], now); // Process any new non-kernel entries (barriers with total_wgs==0). for (size_t qi = 0; qi < hw_queues_.size(); ++qi) { + if (hw_queues_[qi].debug_suspended || hw_queues_[qi].runtime_suspended) + continue; auto &qs = new_queue_states_[qi]; while (qs.next_dispatch_idx < qs.entries.size()) { auto &entry = qs.entries[qs.next_dispatch_idx]; @@ -2141,7 +2363,7 @@ void CommandProcessor::handle_doorbell(simdojo::Tick now) { } for (size_t i = 0; i < cus_.size(); ++i) { - if (cus_[i]->has_active_wfs()) { + if (!cus_[i]->is_idle()) { if (dispatch_ports_[i]->link()) dispatch_ports_[i]->send(std::make_unique(simdojo::MessageHeader{})); else @@ -2312,12 +2534,23 @@ void CommandProcessor::process_sdma_ring(HwQueue &queue, uint64_t read_idx, uint const bool source_known = resolve(src_va, count) != nullptr || memory_->has_range_mapping(src_va, count, queue.process_id); const bool destinations_known = std::ranges::all_of(dst_vas, [&](uint64_t dst_va) { - return range_fits(dst_va) && (resolve(dst_va, count) != nullptr || - memory_->has_range_mapping(dst_va, count, queue.process_id)); + return resolve(dst_va, count) != nullptr || + memory_->has_range_mapping(dst_va, count, queue.process_id); }); - if (!range_fits(src_va) || !source_known || !destinations_known) + if (!range_fits(src_va) || !std::ranges::all_of(dst_vas, range_fits)) return false; + // A pageable host buffer is in neither the page table nor the passthrough + // range, so in daemon mode the checks above cannot see it and the transfer + // below would read sparse zeroes. copy_block() reaches it through the + // client's memory and refuses rather than falling back to sparse, which + // leaves the packet pending for retry when the endpoint is truly gone. + if (!source_known || !destinations_known) { + return std::ranges::all_of(dst_vas, [&](uint64_t dst_va) { + return memory_->copy_block(dst_va, src_va, count, queue.process_id); + }); + } + std::array copy_buffer{}; size_t offset = 0; while (offset < count) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h index 06c069314c7b..dd46c2226b71 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h @@ -72,7 +72,19 @@ struct HwQueue { uint64_t last_doorbell = 0; bool host_accessible = false; bool is_sdma = false; + bool debug_suspended = false; + bool runtime_suspended = false; + /// A command-processor pass observed this queue while its debugger gate was closed. + /// Cleared on resume after scheduling one pass to process the deferred work. + bool debug_work_deferred = false; uint64_t queue_desc_va = 0; + uint64_t exception_status_va = 0; + uint32_t exception_event_id = 0; + /// CP-private monotonic fetch cursor: the next ring index to fetch. Normally + /// tracks read_ptr_va exactly, but stays ahead of it while the debugger holds + /// the queue's read_dispatch_id at a trapped dispatch (so packets are not + /// re-fetched). See fetch_from_queue and serialize_queue_debug_waves. + uint64_t fetch_cursor = 0; }; enum class SdmaPacketDialect { @@ -139,10 +151,24 @@ class CommandProcessor : public simdojo::Component { scratch_allocator_ = std::move(cb); } + /// @brief Number of shader engines per XCC (array_count / simd_arrays_per_engine). + /// Used as the divisor when publishing COMPUTE_TMPRING_SIZE.WAVES so that + /// rocm-dbgapi's scratch_memory_region does not disable private access. + void set_scratch_wave_divisor(uint32_t se_per_xcc) { + scratch_wave_divisor_ = se_per_xcc == 0 ? 1 : se_per_xcc; + } + void register_queue(HwQueue queue); void unregister_queue(uint32_t queue_id, uint32_t process_id); void update_queue(uint32_t queue_id, uint32_t process_id, uint64_t ring_base_va, - uint32_t ring_size); + uint32_t ring_size, uint32_t queue_percentage); + void set_queue_debug_suspended(uint32_t queue_id, uint32_t process_id, bool suspended); + bool signal_queue_exception(uint32_t queue_id, uint32_t process_id, uint64_t status); + uint64_t read_process_memory64(uint64_t address, uint32_t process_id) const { + return memory_ && memory_->is_fetchable(address, process_id) + ? memory_->read64(address, process_id) + : 0; + } void set_plugin_group(std::shared_ptr pg) { plugin_group_ = pg ? pg : ExecutionPluginGroup::empty_group(); @@ -209,6 +235,28 @@ class CommandProcessor : public simdojo::Component { return doorbell_running_; } + /// @brief Test-only view of one queue's debugger suspension gate. + [[nodiscard]] bool queue_debug_suspended_for_test(uint32_t queue_id, uint32_t process_id) { + std::lock_guard lock(hw_queue_mutex_); + auto queue = std::find_if(hw_queues_.begin(), hw_queues_.end(), [&](const auto &candidate) { + return candidate.queue_id == queue_id && candidate.process_id == process_id; + }); + return queue != hw_queues_.end() && queue->debug_suspended; + } + + [[nodiscard]] bool queue_runtime_suspended_for_test(uint32_t queue_id, uint32_t process_id) { + std::lock_guard lock(hw_queue_mutex_); + auto queue = std::find_if(hw_queues_.begin(), hw_queues_.end(), [&](const auto &candidate) { + return candidate.queue_id == queue_id && candidate.process_id == process_id; + }); + return queue != hw_queues_.end() && queue->runtime_suspended; + } + + /// @brief Test-only count of executed command-processor doorbell passes. + [[nodiscard]] uint64_t doorbell_handle_count_for_test() const { + return doorbell_handle_count_.load(std::memory_order_relaxed); + } + private: struct ClusterWorkgroupPlacement; struct ClusterBarrierState; @@ -258,9 +306,10 @@ class CommandProcessor : public simdojo::Component { void flush_gpu_caches(); /// @brief Parse an AQL dispatch packet, read its kernel descriptor, and create a DispatchEntry. + /// @param aql_packet_id AQL ring packet id (queue read index) for debugger correlation. void process_aql_packet(const hsa_kernel_dispatch_packet_t &pkt, const HwQueue &queue, uint64_t pkt_addr, uint32_t queue_packet_id, HwQueueState &qs, - ClusterDispatchShape cluster_shape = {}); + uint64_t aql_packet_id = 0, ClusterDispatchShape cluster_shape = {}); rocr::llvm::amdhsa::kernel_descriptor_t read_kernel_descriptor(uint64_t kernel_object, uint32_t vmid, bool host_accessible = false); @@ -282,6 +331,9 @@ class CommandProcessor : public simdojo::Component { void mark_cluster_workgroup_complete(uint32_t dispatch_id, uint32_t wg_id); void erase_cluster_workgroup(uint32_t dispatch_id, uint32_t wg_id); void erase_cluster_workgroups(uint32_t dispatch_id); + /// @brief Drop cluster LDS pins collected under cluster_placements_mutex_. + /// @warning Must run with that lock released; it reaches the CUs' wave-state lock. + void release_cluster_lds_pins(const std::vector> &unpin); /// @brief Asynchronous Compute Engine (ACE): dispatch workgroups from all /// active queues to SPIs and run CUs to completion. @@ -362,6 +414,16 @@ class CommandProcessor : public simdojo::Component { std::vector peer_wg_ids; }; std::unordered_map cluster_wg_placements_; + /// @brief Guards @ref cluster_wg_placements_ and @ref cluster_barriers_, not the + /// queue state. + /// @details A multicast LDS write resolves its peers from the CU's execute + /// path, which already holds that CU's wave-state lock, while a dispatch takes + /// hw_queue_mutex_ and then the wave-state lock. Sharing hw_queue_mutex_ here + /// would close that cycle, so the map gets its own lock, ordered after both. + /// Nothing may call into a CU while holding it -- see + /// erase_cluster_workgroup(), which collects its LDS cleanup and runs it after + /// the unlock. + mutable std::recursive_mutex cluster_placements_mutex_; struct ClusterBarrierState { uint32_t expected_member_count = 0; uint32_t member_count = 0; @@ -369,7 +431,6 @@ class CommandProcessor : public simdojo::Component { std::array, 2> signaled_workgroups; }; std::unordered_map cluster_barriers_; - mutable std::recursive_mutex cluster_barrier_mutex_; simdojo::Event doorbell_event_{this, simdojo::EventType::TIMER_CALLBACK}; std::recursive_mutex hw_queue_mutex_; @@ -403,10 +464,13 @@ class CommandProcessor : public simdojo::Component { InterruptCallback interrupt_cb_; ScratchBackingResolver scratch_resolver_; ScratchBackingAllocator scratch_allocator_; + uint32_t scratch_wave_divisor_ = 1; std::unique_ptr completion_; std::atomic invalid_pending_{false}; + std::atomic doorbell_handle_count_{0}; + // Set when a queue stalls on an unsatisfied barrier/dependency signal (or an // SDMA VA not yet translatable) — a wait on progress that is external to the // current engine pass (a peer rank's kernel completion arriving via the daemon, diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp index 71530a3a7094..55293326a863 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp @@ -10,11 +10,13 @@ #include "rocjitsu/isa/arch/amdgpu/cdna3/isa.h" #include "rocjitsu/isa/arch/amdgpu/cdna4/isa.h" #include "rocjitsu/isa/arch/amdgpu/cdna5/isa.h" +#include "rocjitsu/isa/arch/amdgpu/generated/shared/isa_properties.h" #include "rocjitsu/isa/arch/amdgpu/rdna1/isa.h" #include "rocjitsu/isa/arch/amdgpu/rdna2/isa.h" #include "rocjitsu/isa/arch/amdgpu/rdna3/isa.h" #include "rocjitsu/isa/arch/amdgpu/rdna3_5/isa.h" #include "rocjitsu/isa/arch/amdgpu/rdna4/isa.h" +#include "rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h" #include "rocjitsu/isa/instruction.h" #include "rocjitsu/vm/amdgpu/mem_state.h" #include "util/except.h" @@ -28,6 +30,27 @@ namespace rocjitsu { namespace amdgpu { +bool InstructionComputeUnitView::signal_queue_exception(uint32_t queue_id, uint32_t process_id, + uint64_t status) { + auto *cp = raw_cu().command_processor(); + return cp && cp->signal_queue_exception(queue_id, process_id, status); +} + +uint32_t Wavefront::debug_read_sgpr(uint32_t reg) const { + return cu_.read_sgpr(sgpr_alloc_.base + reg); +} + +uint32_t Wavefront::debug_read_vgpr(uint32_t reg, uint32_t lane) const { + return cu_.read_vgpr(vgpr_alloc_.base + reg, lane); +} + +void Wavefront::debug_write_sgpr(uint32_t reg, uint32_t value) { + cu_.write_sgpr(sgpr_alloc_.base + reg, value); +} + +void Wavefront::debug_write_vgpr(uint32_t reg, uint32_t lane, uint32_t value) { + cu_.write_vgpr(vgpr_alloc_.base + reg, lane, value); +} namespace { constexpr uint32_t kPrivilegedStatusBit = 1u << 5; @@ -129,6 +152,7 @@ std::unique_ptr ComputeUnitCore::create(std::string name, const Wavefront *ComputeUnitCore::dispatch_wf(uint32_t wg_id, uint64_t pc, uint32_t num_sgprs, uint32_t num_vgprs) { + std::lock_guard wave_state_lock(wave_state_mutex_); assert(wfs_.size() == config_.num_wf_slots && "wavefront slots not properly initialized"); // Halted wavefronts have already freed their SGPR/VGPR blocks at s_endpgm, so a // halted slot is immediately available. Find an idle slot. @@ -181,6 +205,7 @@ Wavefront *ComputeUnitCore::dispatch_wf_at(uint32_t wf_id, uint32_t wg_id, uint6 wf->exec_ = wf_size_ == 64 ? ~0ULL : (1ULL << wf_size_) - 1; wf->vcc_ = 0; wf->m0_ = 0; + wf->set_status_raw(0); wf->set_apertures(shared_aperture_base_, shared_aperture_limit_, private_aperture_base_, private_aperture_limit_); wf->state_ = WfState::RUNNING; @@ -198,6 +223,7 @@ Wavefront *ComputeUnitCore::dispatch_wf_at(uint32_t wf_id, uint32_t wg_id, uint6 } size_t ComputeUnitCore::num_wfs() const { + std::lock_guard wave_state_lock(wave_state_mutex_); size_t count = 0; for (const auto &w : wfs_) if (!w->is_halted()) @@ -206,6 +232,7 @@ size_t ComputeUnitCore::num_wfs() const { } void ComputeUnitCore::free_wavefront_resources(Wavefront &wf) { + std::lock_guard wave_state_lock(wave_state_mutex_); if (wf.sgpr_alloc().count > 0) { sgpr_file_.free(wf.sgpr_alloc().base); free_vgprs(wf.vgpr_alloc().base); @@ -214,6 +241,27 @@ void ComputeUnitCore::free_wavefront_resources(Wavefront &wf) { wf.reset(); } +void ComputeUnitCore::flush_wg_completions() { + // Loops because a notification can retire more work and queue another + // completion behind it; draining to empty keeps that from waiting for whatever + // takes the wave-state lock next. + for (;;) { + std::vector> ready; + { + std::lock_guard wave_state_lock(wave_state_mutex_); + if (pending_wg_completions_.empty()) + return; + ready.swap(pending_wg_completions_); + } + // The lock is released here, so taking hw_queue_mutex_ below cannot invert + // against the CP's dispatch path. + if (!cp_) + return; + for (const auto &[dispatch_id, wg_id] : ready) + cp_->notify_wg_complete(dispatch_id, wg_id); + } +} + void ComputeUnitCore::maybe_reset_lds_alloc() { if (!has_active_wfs() && !lds_allocation_pinned()) reset_lds_alloc(); @@ -419,7 +467,8 @@ bool ComputeUnitCore::named_barrier_leave(Wavefront &wf) { return barrier.member_count == 0; } -void ComputeUnitCore::release_wf(uint32_t dispatch_id, uint32_t wg_id) { +void ComputeUnitCore::release_wf(uint32_t dispatch_id, uint32_t wg_id, + Wavefront::CpCompletionNotice notice) { auto key = wg_key(dispatch_id, wg_id); auto group = barrier_wgs_.find(key); if (group != barrier_wgs_.end()) { @@ -444,8 +493,12 @@ void ComputeUnitCore::release_wf(uint32_t dispatch_id, uint32_t wg_id) { plugin_group_->onAmdgpuWorkgroupCompleted(dispatch_id, wg_id); active_wgs_.erase(it); barrier_wgs_.erase(key); - if (cp_) - cp_->notify_wg_complete(dispatch_id, wg_id); + // Queued rather than sent: notify_wg_complete() takes the CP's + // hw_queue_mutex_, and this runs under the wave-state lock, which the CP + // takes in the other order when it dispatches. WaveStateGuard delivers it + // once the lock is dropped. + if (cp_ && notice == Wavefront::CpCompletionNotice::Send) + pending_wg_completions_.emplace_back(dispatch_id, wg_id); } // The whole workgroup's per-WG LDS region can be reclaimed once the CU has fully // drained and no cluster peer can still multicast into it. @@ -539,7 +592,8 @@ void ComputeUnitCore::route_memory_inst(Instruction *inst, Wavefront &wf) { } } - switch (inst->data()->tag()) { + const uint8_t route_tag = inst->data()->tag(); + switch (route_tag) { case SCALAR_MEM: scalar_mem_pipeline_.issue(inst, wf); break; @@ -598,6 +652,22 @@ void ComputeUnitCore::update_wf_states() { void ComputeUnitCore::issue_instruction(Wavefront *active) { uint32_t vmid = active->process_id(); + // Deliberately not gated on debug_active_, unlike the data-side probe below. + // An unfetchable PC reads back as zeros, and zeros decode to a valid + // instruction, so an undebugged wave that branches into unmapped memory would + // otherwise execute zeros forever. Stopping it matters more than the one + // extra page-table lookup, which is a fraction of the per-issue decode cost. + if (vmid != 0 && !memory_->is_fetchable(active->pc, vmid)) { + if (memory_violation_handler_ && memory_violation_handler_(*active, active->pc, false)) + return; + // Wavefront::halt() is silent, so say why this wave stopped. Without this + // the wave simply disappears from the run with nothing in the log. + util::Logger::vm("CU ", this->name(), ": wf", active->wf_id(), " HALT(UnfetchablePc) pc=0x", + std::hex, active->pc, std::dec, " vmid=", vmid); + active->halt(); + return; + } + rj_code_binary_inst_t words[4]; for (int i = 0; i < 4; ++i) words[i] = memory_->fetch32(active->pc + i * 4, vmid); @@ -610,6 +680,11 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { util::Logger::vm("CU ", this->name(), ": wf", active->wf_id(), " HALT(decode rejection) pc=0x", std::hex, active->pc, " words=[0x", words[0], ",0x", words[1], ",0x", words[2], ",0x", words[3], "]", std::dec, " what=", decode_error.message()); + // Under a debugger, surface the undecodable instruction as an illegal- + // instruction exception (stops the wave at this PC) instead of silently + // retiring it. Without a debugger this halts as before. + if (illegal_inst_handler_ && illegal_inst_handler_(*active)) + return; active->halt(); return; } @@ -618,6 +693,8 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { int inst_size_signed = inst->size(); assert(inst_size_signed > 0 && "instruction size must be positive"); auto inst_size = static_cast(inst_size_signed); + // The cause classifiers report into this as they run; see alu_exceptions.h. + active->clear_pending_alu_causes(); if constexpr (util::Logger::group_enabled(util::Logger::GROUP_VM)) { if (active->num_vgprs_ > 0) { @@ -643,6 +720,63 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { plugin_group_->onAmdgpuBeforeExecuteInstruction(active->pc, *inst, *active); + // s_trap enters the per-process handler configured by SET_TRAP_HANDLER. The + // hardware saves the interrupted PC/status in TTMPs and begins fetching at + // TBA. The handler advances TTMP0:1 for software traps, sends the KFD + // interrupt message, restores STATUS, and returns through s_rfe_b64. + if (std::string_view(inst->mnemonic()) == "s_trap") { + uint32_t trap_id = words[0] & 0xFFu; + if (!active->in_trap_handler() && trap_handler_resolver_) { + auto config = trap_handler_resolver_(*active); + if (config && config->tba != 0) { + const uint64_t saved_pc = active->pc; + active->set_ttmp(0, static_cast(saved_pc)); + active->set_ttmp(1, static_cast(saved_pc >> 32) | (trap_id << 16)); + // Dispatch identity. Which TTMPs carry it is architecture-specific and + // this must not disagree with what CWSR publishes for the same wave, or + // rocm-dbgapi correlates the stopped wave to the wrong workgroup. + // + // On the profiles where the SPI puts workgroup ids in TTMP6/7/9, + // init_wavefront_regs() already seeded them at dispatch and trap entry + // has nothing to add -- zeroing TTMP9 here destroyed one of them. The + // rest use the gfx9 layout, TTMP8/9/10 = workgroup id x/y/z, which is + // also what CWSR serializes (cwsr.cpp writes wg_coord into ttmp[8..10]). + // Writing the flat wg_id() into TTMP8 disagreed with that too. + if (!isa_properties(this->arch()).uses_ttmp_workgroup_ids) { + const auto &wg = active->wg_coord(); + active->set_ttmp(8, wg[0]); + active->set_ttmp(9, wg[1]); + active->set_ttmp(10, wg[2]); + } + active->set_ttmp(11, ((active->aql_packet_id() & 0x1FFFFFFu) << 6) | + (active->wave_in_group() & 0x3Fu)); + active->set_ttmp(12, active->status_raw()); + const uint32_t debug_enabled = config->debug_enabled ? (1u << 23) : 0u; + active->set_ttmp(13, (active->ttmp(13) & ~(1u << 23)) | debug_enabled); + active->set_ttmp(14, static_cast(config->tma)); + active->set_ttmp(15, static_cast(config->tma >> 32)); + active->set_trap_id(trap_id); + active->set_trap_saved_status(active->status_raw()); + active->set_trap_saved_exec(active->exec()); + active->set_trap_interrupt_sent(false); + // A fresh handler entry owns the halt state from here on; a marker left + // over from a previous stop would attribute this entry's HALT to an + // s_sendmsghalt that has already been resumed past. + active->set_self_halted(false); + active->set_in_trap_handler(true); + active->pc = config->tba; + delete inst; + return; + } + } + + // With no configured TBA, or for a parked s_trap executed by TBA code, + // retire the instruction without inventing a host-side trap handler. + active->pc += inst_size; + delete inst; + return; + } + { auto mn = std::string_view(inst->mnemonic()); if (mn.find("s_setpc") != std::string_view::npos || @@ -659,6 +793,10 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { } } + // Sampled before execute so the trap-return test below can be a state + // transition rather than a per-ISA mnemonic list. See its use. + const bool was_in_trap_handler = active->in_trap_handler(); + execute_instruction(inst, *active); // A terminating instruction (s_endpgm with no pending waits) halts the wave @@ -696,6 +834,104 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { } } + // Capture debugger probe info before the pipeline consumes the instruction. + // The checks run after the PC advances (below) so that a wave stopped on a + // watchpoint or memory fault resumes past the access instead of re-executing + // it. Gated on debug_active_ so non-debugged runs pay no per-access cost. + const bool debug_probe = debug_active_.load(std::memory_order_relaxed) && inst->is_memory_op() && + inst->data() && + (inst->data()->tag() == GLOBAL_MEM || inst->data()->tag() == SCALAR_MEM); + std::vector dbg_addrs; + uint32_t dbg_bytes = 0; + bool dbg_is_write = false; + bool dbg_is_atomic = false; + if (debug_probe) { + if (inst->data()->tag() == SCALAR_MEM) { + auto &d = *inst->data_as(); + dbg_is_write = !d.is_load; + dbg_bytes = std::max(1u, d.num_dwords * d.elem_size); + dbg_addrs.push_back(d.addr); + } else { + auto &d = *inst->data_as(); + dbg_is_atomic = (d.atomic_op != AtomicOp::NONE); + dbg_is_write = !d.is_load || dbg_is_atomic; + // std::max on both arms: VectorMemState::elem_size defaults to 0 and the + // range check below reports a zero-sized range as *unmapped*, so an + // atomic whose decoder left elem_size unset would fault on every lane of + // a perfectly mapped buffer. + dbg_bytes = std::max(1u, dbg_is_atomic ? d.elem_size : d.num_elems * d.elem_size); + dbg_addrs.reserve(d.wf_size); + for (uint32_t lane = 0; lane < d.wf_size; ++lane) + if (d.lane_mask & (1ULL << lane)) + dbg_addrs.push_back(d.per_lane_addr[lane]); + } + } + // One predicate for the whole access, used both to decide that this + // instruction faulted and to pick the address reported to the debugger below. + // The two must agree: if the decision said "faulted" and the report loop then + // found no faulting address, the access would be dropped with nothing + // delivered. Checking only the first byte let a multi-byte load, store or + // atomic that starts near the end of a mapped page run off it unnoticed, so + // the whole [addr, addr + dbg_bytes) range is validated. + const uint32_t dbg_vmid = active->process_id(); + auto access_faults = [&](uint64_t addr) { + const bool shared_address = active->shared_aperture_base() != 0 && + addr >= active->shared_aperture_base() && + addr <= active->shared_aperture_limit(); + return !shared_address && !memory_->is_range_mapped(addr, dbg_bytes, dbg_vmid); + }; + // Locate the faulting address once. The report loop below resumes from this + // iterator rather than rescanning: each access_faults() call is a page-table + // walk per touched page, and dbg_addrs holds one entry per active lane. + auto first_fault = dbg_addrs.end(); + if (debug_probe && memory_violation_handler_) + first_fault = std::ranges::find_if(dbg_addrs, access_faults); + const bool debug_memory_fault = first_fault != dbg_addrs.end(); + + // The trap return is whatever instruction just left the handler. Asking the + // wave rather than matching mnemonics keeps this ISA-agnostic: the spelling + // differs per ISA (gfx1250 uses s_rfe_i64), and a hard-coded list silently + // stops calling notify_trap_complete() for any spelling it misses -- KFD is + // never told the handler returned and the debugger hangs. Only the generated + // s_rfe body clears the flag. + const bool trap_return = was_in_trap_handler && !active->in_trap_handler(); + + // A faulting access is discarded only if the debugger actually claims the + // fault. debug_active_ is CU-wide, so the probe also fires for waves of a + // process nobody is debugging; on_wave_memory_violation() declines those, and + // dropping the instruction anyway silently lost a store, or left a load's + // destination registers stale, in an undebugged process. + // + // The report has to be made against the resume PC -- a wave the handler + // serializes must come back past the access, not re-execute it -- so the PC + // is advanced for the duration of the report and put back if the fault goes + // unclaimed. Everything downstream then sees exactly the ordering it saw + // before: the instruction is routed at the issue PC and the PC advances + // afterwards. + const uint64_t issue_pc = active->pc; + bool fault_claimed = false; + if (debug_memory_fault && !active->debug_halted()) { + active->pc += inst_size; + // first_fault is already known to fault, so it is reported without a second + // range walk; only the lanes after it still have to be tested. + for (auto it = first_fault; it != dbg_addrs.end(); ++it) { + if ((it == first_fault || access_faults(*it)) && + memory_violation_handler_(*active, *it, dbg_is_write)) { + fault_claimed = true; + break; + } + } + // Only undo our own advance. A declining handler is still free to have + // moved the wave (entering a trap handler, for instance); clobbering that + // would resume the application with the handler's state half-installed. + if (!fault_claimed && active->pc == issue_pc + inst_size) + active->pc = issue_pc; + } + + if (fault_claimed) { + delete inst; + return; + } if (inst->is_memory_op()) { if (inst->data() && inst->data()->tag() == GLOBAL_MEM) { auto *d = inst->data_as(); @@ -706,14 +942,66 @@ void ComputeUnitCore::issue_instruction(Wavefront *active) { delete inst; active->pc += inst_size; + + // Deliver on the causes this instruction raised, not on TRAPSTS changing. + // TRAPSTS.EXCP is sticky and nothing in the model clears it between + // instructions, so a rising-edge test went permanently quiet for any cause + // whose bit was already latched: raise a cause with its MODE.EXCP_EN bit + // clear, enable it, repeat the operation, and the second occurrence -- the + // one hardware traps on -- was never reported. The same silence followed a + // first occurrence the handler declined, which is every occurrence before a + // debugger attaches. + // Masks come from alu_exceptions.h, which is also what the classifiers and + // the generated call sites use. A local copy here would keep checking the + // old bits if the EXCP set ever widened. + const uint32_t new_alu_causes = active->pending_alu_causes() & kAluExceptionTrapstsMask; + const uint32_t enabled_alu_causes = + (active->mode_raw() & kAluExceptionModeMask) >> kAluExceptionModeShift; + if ((new_alu_causes & enabled_alu_causes) != 0 && alu_exception_handler_ && + alu_exception_handler_(*active)) + return; + + // s_rfe follows the same target-minus-size convention as other control-flow + // instructions. Publish the handler-driven stop only after the common PC + // increment has produced the architectural return PC for CWSR serialization. + // EXEC is put back by s_rfe itself, for every return and not just this one. + if (trap_return && active->debug_halted() && active->trap_interrupt_sent()) + notify_trap_complete(*active); + + // Watchpoints, after the access completed and the PC advanced (so the + // serialized wave resumes at the next instruction). A memory fault is more + // severe than a watchpoint and wins if both would fire on the same + // instruction, which it does by returning above before reaching here. + if (debug_probe && !active->debug_halted() && watchpoint_handler_) { + for (uint64_t addr : dbg_addrs) + if (watchpoint_handler_(*active, addr, dbg_bytes, dbg_is_write, dbg_is_atomic)) + break; + } } bool ComputeUnitCore::step() { + // A wave reaching s_endpgm in this loop retires its workgroup; the guard sends + // the CP its completion after the lock is released. See WaveStateGuard. + WaveStateGuard wave_state_lock(*this); update_wf_states(); for (auto &wf : wfs_) { - if (wf->state() == WfState::RUNNING) + if (wf->state() == WfState::RUNNING && !wf->debug_paused()) { + // Burn down an in-flight S_SLEEP before issuing anything else. A + // single-step request cancels the remainder instead of spending the + // debugger's one step on it, which would look like a hung wave. + if (wf->sleep_cycles() != 0) { + if (!wf->debug_single_step()) { + wf->tick_sleep(); + continue; + } + wf->set_sleep_cycles(0); + } + const bool single_step = wf->debug_single_step(); issue_instruction(wf.get()); + if (single_step && !wf->in_trap_handler() && !wf->debug_halted() && single_step_handler_) + single_step_handler_(*wf); + } } ++step_count_; @@ -733,7 +1021,7 @@ bool ComputeUnitCore::step() { } } - return has_active_wfs(); + return has_runnable_wfs(); } // Explicit template instantiations for all AMDGPU ISAs and execution modes. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h index d8abd097fe57..a419f5596113 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h @@ -34,11 +34,14 @@ #include #include +#include #include #include #include #include #include +#include +#include #include #include #include @@ -86,6 +89,7 @@ inline constexpr uint8_t kClusterTrapBarrierBit = 4; class ComputeUnitCore : public simdojo::CompositeComponent { public: static constexpr uint32_t kFunctionalQuantum = 1024; + static constexpr uint32_t kDebugFunctionalQuantum = 64; static constexpr uint32_t kMaxNamedBarriers = 16; /// @brief Configuration for a compute unit. @@ -174,11 +178,14 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// initialization after engine creation but before simulation workers start. virtual void schedule_work() = 0; - /// @brief Check whether this CU has no active wavefronts. - /// @retval true No wavefronts are actively executing. - /// @retval false At least one wavefront is active. - /// @warning NOT thread-safe (see has_active_wfs()): engine-thread only. - virtual bool is_idle() const { return !has_active_wfs(); } + /// @brief Thread-safe scheduling for debugger resume from an ioctl thread. + virtual void schedule_work_async() = 0; + + /// @brief Check whether this CU has no runnable wavefronts. + /// @retval true No wavefront can currently execute. + /// @retval false At least one wavefront can execute. + /// @warning NOT thread-safe (see has_runnable_wfs()): engine-thread only. + virtual bool is_idle() const { return !has_runnable_wfs(); } /// @brief Register a callback invoked when this CU becomes idle. /// @@ -187,6 +194,56 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// @param cb Callback to invoke when idle. void set_on_idle(std::function cb) { on_idle_ = std::move(cb); } + struct TrapHandlerConfig { + uint64_t tba = 0; + uint64_t tma = 0; + bool debug_enabled = false; + }; + + /// @brief Resolve the KFD trap handler for a wave's process and GPU. + using TrapHandlerResolver = std::function(const Wavefront &wf)>; + void set_trap_handler_resolver(TrapHandlerResolver cb) { trap_handler_resolver_ = std::move(cb); } + + /// @brief Handle an architected scalar message issued by trap-handler code. + using SendmsgHandler = std::function; + void set_sendmsg_handler(SendmsgHandler cb) { sendmsg_handler_ = std::move(cb); } + bool handle_sendmsg(Wavefront &wf, uint32_t message) { + return sendmsg_handler_ && sendmsg_handler_(wf, message); + } + + /// @brief Notify KFD after configured TBA code returns with STATUS.HALT. + using TrapCompletionHandler = std::function; + void set_trap_completion_handler(TrapCompletionHandler cb) { + trap_completion_handler_ = std::move(cb); + } + void notify_trap_complete(Wavefront &wf) { + if (trap_completion_handler_) + trap_completion_handler_(wf); + } + + /// @brief Callback after a single-stepped wave executes one instruction. + using SingleStepHandler = std::function; + + void set_single_step_handler(SingleStepHandler cb) { single_step_handler_ = std::move(cb); } + + using WatchpointHandler = std::function; + + void set_watchpoint_handler(WatchpointHandler cb) { watchpoint_handler_ = std::move(cb); } + + using IllegalInstHandler = std::function; + void set_illegal_inst_handler(IllegalInstHandler cb) { illegal_inst_handler_ = std::move(cb); } + + using MemoryViolationHandler = + std::function; + void set_memory_violation_handler(MemoryViolationHandler cb) { + memory_violation_handler_ = std::move(cb); + } + using AluExceptionHandler = std::function; + void set_alu_exception_handler(AluExceptionHandler cb) { alu_exception_handler_ = std::move(cb); } + void set_debug_active(bool active) { debug_active_.store(active, std::memory_order_relaxed); } + bool debug_active() const { return debug_active_.load(std::memory_order_relaxed); } + /// @brief Set the command processor for WG completion notification. void set_command_processor(CommandProcessor *cp) { cp_ = cp; } @@ -234,7 +291,8 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// @brief Called by Wavefront::halt() to decrement the WG refcount. /// @details When the refcount reaches zero, all WFs in the WG have halted /// and the CP is notified via notify_wg_complete. - void release_wf(uint32_t dispatch_id, uint32_t wg_id); + void release_wf(uint32_t dispatch_id, uint32_t wg_id, + Wavefront::CpCompletionNotice notice = Wavefront::CpCompletionNotice::Send); /// @brief Roll back a committed-but-never-run workgroup on a dispatch error. /// @details Used to unwind an already-committed cluster peer when a later peer in @@ -410,13 +468,34 @@ class ComputeUnitCore : public simdojo::CompositeComponent { /// shared partition engine thread (CP and its CUs share one partition, asserted in /// CommandProcessor::startup()); callers on any other thread would race a halt(). bool has_active_wfs() const { + std::lock_guard lock(wave_state_mutex_); for (const auto &w : wfs_) if (!w->is_halted()) return true; return false; } + /// @brief Check whether any wavefront can currently make forward progress. + /// @details A debug-halted wave occupies its slot (so @ref has_active_wfs + /// stays true and the wave is not retired) but cannot run, so it must not + /// keep the CU's event loop spinning. Idle detection uses this instead of + /// @ref has_active_wfs so the engine can quiesce while a wave is stopped at + /// a breakpoint. @retval true At least one non-halted, non-debug-halted wave. + bool has_runnable_wfs() const { + std::lock_guard lock(wave_state_mutex_); + for (const auto &w : wfs_) + if (!w->is_halted() && !w->debug_paused()) + return true; + return false; + } + + template decltype(auto) with_wave_state_locked(F &&fn) { + WaveStateGuard lock(*this); + return std::forward(fn)(); + } + bool has_active_wfs_for_process(uint32_t process_id) const { + std::lock_guard lock(wave_state_mutex_); for (const auto &w : wfs_) if (!w->is_halted() && w->process_id() == process_id) return true; @@ -672,6 +751,45 @@ class ComputeUnitCore : public simdojo::CompositeComponent { std::unique_ptr decoder_; simdojo::RegisterFile sgpr_file_{"sgpr"}; std::vector> wfs_; ///< Pre-allocated wavefront slots. + /// @brief Hold the wave-state lock, then notify the CP once it is released. + /// @details The CP takes hw_queue_mutex_ and then this lock when it dispatches + /// (handle_doorbell -> dispatch_workgroups -> dispatch_wf), so anything running + /// under this lock must not reach back into the CP and take hw_queue_mutex_ -- + /// a wave hitting s_endpgm on the engine thread would otherwise close an AB-BA + /// cycle against a concurrent dispatch or DESTROY_QUEUE. release_wf() therefore + /// queues its completions instead of sending them, and the outermost guard + /// delivers them here, after the lock is dropped and in the same order. + class WaveStateGuard { + public: + explicit WaveStateGuard(ComputeUnitCore &cu) : cu_(cu), lock_(cu.wave_state_mutex_) { + ++cu_.wave_state_depth_; + } + WaveStateGuard(const WaveStateGuard &) = delete; + WaveStateGuard &operator=(const WaveStateGuard &) = delete; + ~WaveStateGuard() { + const bool outermost = --cu_.wave_state_depth_ == 0; + lock_.unlock(); + if (outermost) + cu_.flush_wg_completions(); + } + + private: + ComputeUnitCore &cu_; + std::unique_lock lock_; + }; + + /// @brief Send the workgroup completions queued under the wave-state lock. + /// @warning Must be called with that lock released; it takes hw_queue_mutex_. + void flush_wg_completions(); + + mutable std::recursive_mutex wave_state_mutex_; + /// @brief Recursion depth of WaveStateGuard on the thread holding the mutex. + /// @details Only ever touched under @ref wave_state_mutex_, so the value + /// belongs to whichever thread currently owns it. + unsigned wave_state_depth_ = 0; + /// @brief Workgroups that finished while the wave-state lock was held. + /// @details Drained by @ref flush_wg_completions once the lock is dropped. + std::vector> pending_wg_completions_; std::unique_ptr scheduler_ = std::make_unique(); uint64_t cycle_counter_ = 0; @@ -687,6 +805,15 @@ class ComputeUnitCore : public simdojo::CompositeComponent { GlobalMemPipeline global_mem_pipeline_; LocalMemPipeline local_mem_pipeline_; std::function on_idle_; ///< Callback invoked when CU becomes idle. + TrapHandlerResolver trap_handler_resolver_; + SendmsgHandler sendmsg_handler_; + TrapCompletionHandler trap_completion_handler_; + SingleStepHandler single_step_handler_; + WatchpointHandler watchpoint_handler_; + IllegalInstHandler illegal_inst_handler_; + MemoryViolationHandler memory_violation_handler_; + AluExceptionHandler alu_exception_handler_; + std::atomic debug_active_{false}; CommandProcessor *cp_ = nullptr; std::unordered_map active_wgs_; @@ -746,6 +873,12 @@ inline simdojo::SimulationEngine *InstructionComputeUnitView::engine() const { inline void InstructionComputeUnitView::request_functional_yield() { raw_cu().request_functional_yield(); } +inline bool InstructionComputeUnitView::handle_sendmsg(Wavefront &wf, uint32_t message) { + return raw_cu().handle_sendmsg(wf, message); +} +inline void InstructionComputeUnitView::notify_trap_complete(Wavefront &wf) { + raw_cu().notify_trap_complete(wf); +} inline uint32_t InstructionComputeUnitView::read_sgpr(uint32_t reg_idx) const { return raw_cu().read_sgpr(reg_idx); } @@ -773,7 +906,8 @@ template class ExecComputeUnit : public ComputeUnitCore // A request left by direct step() execution must not shorten this quantum. functional_yield_requested_ = false; last_quantum_executed_ = 0; - for (uint32_t i = 0; i < kFunctionalQuantum && step(); ++i) { + const uint32_t quantum = debug_active() ? kDebugFunctionalQuantum : kFunctionalQuantum; + for (uint32_t i = 0; i < quantum && step(); ++i) { ++last_quantum_executed_; if (std::exchange(functional_yield_requested_, false)) break; @@ -804,13 +938,23 @@ template class ExecComputeUnit : public ComputeUnitCore // any simulation worker starts, when it has exclusive access to the queues. A // cross-partition call during execution would be an executing_ data race plus // an unsynchronized event-queue push. - if (executing_ || !this->engine() || !this->has_active_wfs()) + // + // Runnable, not merely active: a wave the debugger has stopped is still + // resident on this CU, so scheduling work for it would spin the engine + // against a wave that cannot retire an instruction until the debugger + // resumes it. + if (executing_ || !this->engine() || !this->has_runnable_wfs()) return; executing_ = true; auto now = this->engine()->context(this->partition_id()).current_tick(); this->schedule_event(&tick_event_, now + 1); } + void schedule_work_async() override { + if (this->engine()) + this->engine()->schedule_event_now(&resume_event_); + } + private: // Reschedule by the number of quantum loop iterations taken, not a fixed // kFunctionalQuantum: a wavefront that requests a yield after k class ExecComputeUnit : public ComputeUnitCore if (execute_quantum()) this->schedule_event(&tick_event_, now + std::max(1, last_quantum_executed_)); }}; + // Cross-thread debugger resumes first enter this event. Its handler runs on + // the CU partition and can safely update executing_ through schedule_work(). + simdojo::Event resume_event_{this, simdojo::EventType::TIMER_CALLBACK, + [this](simdojo::Tick, simdojo::Message *) { schedule_work(); }}; uint64_t last_quantum_executed_ = 0; bool executing_ = false; }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h index 06b18d12ba7f..05dac74a2fa6 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h @@ -47,7 +47,12 @@ struct DispatchEntry { uint32_t queue_packet_id = 0; uint32_t process_id = 0; + /// AQL ring packet id (queue read index at which this dispatch's packet was + /// fetched). Used only for rocm-dbgapi wave/dispatch correlation. + uint32_t aql_packet_id = 0; + uint64_t kernel_entry_pc = 0; + uint64_t code_load_bias = 0; uint32_t wfs_per_workgroup = 1; uint32_t sgprs_per_wf = 104; uint32_t vgprs_per_wf = 256; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h index 580d61008c6d..3de694dc3b1b 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h @@ -11,12 +11,14 @@ #include "simdojo/components/sparse_memory.h" #include "simdojo/sim/component.h" #include "util/log.h" +#include "util/unique_handle.h" #include #include #include #include #include +#include #include #include #include @@ -96,6 +98,7 @@ class GpuMemory : public simdojo::SparseMemory { .page_table = pt, .mutex = mu, .client_pid = 0, + .client_mem_fd = {}, .generation = generation, }; // The VMID may now select a different page table even though neither page @@ -122,6 +125,15 @@ class GpuMemory : public simdojo::SparseMemory { it->second.client_pid = client_pid; } + void set_process_mem_fd(uint32_t pid, int mem_fd) { + std::unique_lock lk(vmid_mutex_); + auto it = vmid_table_.find(pid); + if (it == vmid_table_.end()) + return; + const int duplicate = mem_fd >= 0 ? ::fcntl(mem_fd, F_DUPFD_CLOEXEC, 0) : -1; + it->second.client_mem_fd.reset(duplicate); + } + /// @brief Enable passthrough for unmapped addresses (local/user-mode only). /// @details When true, addresses not found in the page table are treated as /// host pointers (GPU VA == host VA). This mirrors QEMU user-mode's identity @@ -154,14 +166,8 @@ class GpuMemory : public simdojo::SparseMemory { /// callers can retry a not-yet-installed range while still allowing a mapped /// page's deliberately clipped extent to produce bounded partial accesses. bool has_range_mapping(uint64_t addr, size_t size, uint32_t vmid = 0) const { - if (size == 0 || size - 1 > std::numeric_limits::max() - addr) - return false; - bool mapped = true; - for_each_page_chunk(addr, size, [&](uint64_t ea, size_t, size_t) { - if (mapped && !has_page_mapping(ea, vmid)) - mapped = false; - }); - return mapped; + return every_page(addr, size, + [&](uint64_t page_addr) { return has_page_mapping(page_addr, vmid); }); } /// @brief Resolve a GPU VA range to its first borrowed host byte. @@ -187,6 +193,29 @@ class GpuMemory : public simdojo::SparseMemory { return contiguous ? first_host_ptr : nullptr; } + /// @brief Return whether a GPU VA has a VMID page-table mapping. + bool is_mapped(uint64_t addr, uint32_t vmid = 0) const { + if (vmid == 0) + return passthrough_; + std::shared_lock lk(vmid_mutex_); + auto it = vmid_table_.find(vmid); + if (it == vmid_table_.end()) + return false; + auto &entry = it->second; + std::shared_lock pt_lk(*entry.mutex); + return entry.page_table->contains(addr >> PAGE_SHIFT); + } + + /// @brief Return whether every page touched by a range has a VMID mapping. + /// @details The range-aware form of is_mapped(), with the same deliberate + /// strictness: passthrough is ignored for vmid != 0. Use this rather than + /// is_mapped() on a base address when the access is wider than a byte -- an + /// access starting near the end of a mapped page can still run off it. + /// A zero size, or a range that wraps the address space, is not mapped. + bool is_range_mapped(uint64_t addr, size_t size, uint32_t vmid = 0) const { + return every_page(addr, size, [&](uint64_t page_addr) { return is_mapped(page_addr, vmid); }); + } + /// @brief Look up PTE MTYPE for a GPU VA in the given VMID's page table. Mtype pte_mtype(uint64_t addr, uint32_t vmid = 0) const { if (vmid == 0) @@ -199,6 +228,20 @@ class GpuMemory : public simdojo::SparseMemory { uint32_t fetch32(uint64_t addr, uint32_t vmid = 0) const { return read32(addr, vmid); } + bool is_fetchable(uint64_t addr, uint32_t vmid = 0) const { + if (is_mapped(addr, vmid) || simdojo::SparseMemory::has_page(addr)) + return true; + uint8_t byte = 0; + if (util::UniqueHandle mem_fd = duplicate_client_mem_fd(vmid); mem_fd.get() >= 0) + return pread(mem_fd.get(), &byte, sizeof(byte), static_cast(addr)) == sizeof(byte); + pid_t pid = client_pid_for_vmid(vmid); + if (pid <= 0) + return false; + iovec local{&byte, sizeof(byte)}; + iovec remote{reinterpret_cast(addr), sizeof(byte)}; + return process_vm_readv(pid, &local, 1, &remote, 1, 0) == sizeof(byte); + } + /// @brief Read a contiguous range from simulated GPU memory. /// @details Handles each page through mapped host memory, client memory, or /// sparse backing memory. A mapped access clipped by a host extent remains @@ -271,6 +314,38 @@ class GpuMemory : public simdojo::SparseMemory { atomic_rmw_unmapped(addr, size, entry.client_pid, fn); } + /// @brief Copy a contiguous range between two VMID-scoped addresses. + /// @details Unlike read_block()/write_block(), this does not fall back to + /// sparse memory: an SDMA packet must remain pending when either endpoint is + /// inaccessible. In daemon mode, pageable host pointers are accessed through + /// process_vm_readv/process_vm_writev while GPU allocations use their mapped + /// daemon backing. Transfers are split at both source and destination page + /// boundaries so each chunk resolves within one page, and each read and write + /// runs inside the page-table mapping callback: no host pointer outlives the + /// lock that keeps its allocation alive, so a concurrent process teardown + /// cannot unmap the storage mid-copy. + bool copy_block(uint64_t dst_addr, uint64_t src_addr, size_t len, uint32_t vmid = 0) { + std::array buffer{}; + size_t offset = 0; + while (offset < len) { + const uint64_t src_ea = src_addr + offset; + const uint64_t dst_ea = dst_addr + offset; + const size_t chunk = std::min( + {len - offset, PAGE_SIZE - (src_ea & PAGE_MASK), PAGE_SIZE - (dst_ea & PAGE_MASK)}); + + if (!copy_from_mapped(src_ea, buffer.data(), chunk, vmid) && + (vmid == 0 || !read_client_memory(src_ea, buffer.data(), chunk, vmid))) + return false; + + if (!copy_to_mapped(dst_ea, buffer.data(), chunk, vmid) && + (vmid == 0 || !write_client_memory(dst_ea, buffer.data(), chunk, vmid))) + return false; + + offset += chunk; + } + return true; + } + uint8_t *translate_debug(uint64_t addr, uint32_t vmid, size_t size = 1) const { return translate(addr, vmid, size); } @@ -597,6 +672,25 @@ class GpuMemory : public simdojo::SparseMemory { } } + /// @brief Whether @p pred holds for every page touched by [addr, addr+size). + /// @details Shared spine of has_range_mapping() and is_range_mapped(), which + /// differ only in their per-page predicate. Unlike for_each_page_chunk() this + /// stops at the first page that fails, so a large unmapped range costs one + /// page-table walk rather than one per 4 KiB. A zero size, or a range that + /// wraps the address space, satisfies nothing. + template static bool every_page(uint64_t addr, size_t size, Pred &&pred) { + if (size == 0 || size - 1 > std::numeric_limits::max() - addr) + return false; + size_t offset = 0; + while (offset < size) { + const uint64_t ea = addr + offset; + if (!pred(ea)) + return false; + offset += std::min(size - offset, PAGE_SIZE - (ea & PAGE_MASK)); + } + return true; + } + static constexpr uint64_t kUserSpaceLimit = 0x800000000000ULL; static size_t addressable_prefix(const uint8_t *ptr, size_t len) { @@ -698,6 +792,8 @@ class GpuMemory : public simdojo::SparseMemory { KfdProcess::PageTable *page_table = nullptr; std::shared_mutex *mutex = nullptr; pid_t client_pid = 0; + /// Debugger-authorized /proc//mem fd, or empty. + util::UniqueHandle client_mem_fd; const uint64_t *generation = nullptr; }; @@ -901,6 +997,53 @@ class GpuMemory : public simdojo::SparseMemory { }); } + /// @brief Run @p fn over a fully-backed, page-bounded host span with the + /// page-table lock held for the duration. + /// @details Applies exactly translate()'s resolution rules -- the range must + /// be contiguous, host-backed and addressable -- but hands the pointer to a + /// callback instead of returning it, so a concurrent unmap or VMID + /// unregistration cannot free the storage between resolution and use. + /// @return true if the span resolved and @p fn ran. + template + bool with_translated_span(uint64_t addr, uint32_t vmid, size_t size, F &&fn) const { + if (size == 0 || (addr & PAGE_MASK) + size > PAGE_SIZE) + return false; + bool copied = false; + with_page_mapping(addr, vmid, + [&](const KfdProcess::PageTableEntry *pte, uint8_t *passthrough_page) { + const size_t page_offset = addr & PAGE_MASK; + uint8_t *candidate = nullptr; + if (pte) { + const auto *extent = host_extent_at(*pte, page_offset); + if (!extent || size > extent->host_backed_bytes - + (page_offset - extent->gpu_page_offset)) + return; + candidate = extent->host_ptr + (page_offset - extent->gpu_page_offset); + } else { + if (addr >= kUserSpaceLimit || size > kUserSpaceLimit - addr) + return; + candidate = passthrough_page + page_offset; + } + if (addressable_prefix(candidate, size) != size) + return; + fn(candidate); + copied = true; + }); + return copied; + } + + /// @brief Read a mapped span into @p dst without ever exposing a bare pointer. + bool copy_from_mapped(uint64_t addr, void *dst, size_t size, uint32_t vmid) const { + return with_translated_span(addr, vmid, size, + [&](const uint8_t *host_ptr) { std::memcpy(dst, host_ptr, size); }); + } + + /// @brief Write @p src into a mapped span without ever exposing a bare pointer. + bool copy_to_mapped(uint64_t addr, const void *src, size_t size, uint32_t vmid) const { + return with_translated_span(addr, vmid, size, + [&](uint8_t *host_ptr) { std::memcpy(host_ptr, src, size); }); + } + uint8_t *translate(uint64_t addr, uint32_t vmid, size_t size) const { if (size == 0 || (addr & PAGE_MASK) + size > PAGE_SIZE) return nullptr; @@ -933,7 +1076,24 @@ class GpuMemory : public simdojo::SparseMemory { return (it != vmid_table_.end()) ? it->second.client_pid : 0; } + util::UniqueHandle duplicate_client_mem_fd(uint32_t vmid) const { + std::shared_lock lk(vmid_mutex_); + auto it = vmid_table_.find(vmid); + if (it == vmid_table_.end() || it->second.client_mem_fd.get() < 0) + return {}; + return util::UniqueHandle(::fcntl(it->second.client_mem_fd.get(), F_DUPFD_CLOEXEC, 0)); + } + bool read_client_memory(uint64_t addr, void *dst, size_t len, uint32_t vmid) const { + // Prefer the debugger-authorized /proc//mem fd when the debug session + // transferred one. The daemon is not the debuggee's ptrace parent, so the + // process_vm_readv() fallback below is refused (EPERM) for a target it did + // not itself attach to. + if (util::UniqueHandle mem_fd = duplicate_client_mem_fd(vmid); mem_fd.get() >= 0) { + const ssize_t rc = pread(mem_fd.get(), dst, len, static_cast(addr)); + if (rc == static_cast(len)) + return true; + } return read_client_memory_for_pid(addr, dst, len, client_pid_for_vmid(vmid)); } @@ -952,6 +1112,13 @@ class GpuMemory : public simdojo::SparseMemory { } bool write_client_memory(uint64_t addr, const void *src, size_t len, uint32_t vmid) { + // See read_client_memory(): the authorized fd is the only path that works + // for a debuggee the daemon did not ptrace-attach to itself. + if (util::UniqueHandle mem_fd = duplicate_client_mem_fd(vmid); mem_fd.get() >= 0) { + const ssize_t rc = pwrite(mem_fd.get(), src, len, static_cast(addr)); + if (rc == static_cast(len)) + return true; + } return write_client_memory_for_pid(addr, src, len, client_pid_for_vmid(vmid)); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp index 4ef756d358b3..593dc9f51570 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hwreg.cpp @@ -22,6 +22,7 @@ enum class HwregState : uint8_t { Unsupported, Mode, Status, + Trapsts, GprAllocGfx9_10, GprAllocCdna3_4, WaveSchedMode, @@ -112,8 +113,8 @@ constexpr HwregDescriptor CDNA1_2_HWREGS[] = { // unmodeled state explicit but unsupported until the corresponding VM // state, field layouts, and privilege side effects are represented. {1, "MODE", HwregState::Mode, HwregWritePolicy::UserWritable}, - {2, "STATUS", HwregState::Status, HwregWritePolicy::ReadOnly}, - {3, "TRAPSTS", HwregState::Unsupported, HwregWritePolicy::UserWritable}, + {2, "STATUS", HwregState::Status, HwregWritePolicy::Privileged}, + {3, "TRAPSTS", HwregState::Trapsts, HwregWritePolicy::UserWritable}, {4, "HW_ID", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, {5, "GPR_ALLOC", HwregState::GprAllocGfx9_10, HwregWritePolicy::ReadOnly}, {6, "LDS_ALLOC", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, @@ -138,8 +139,8 @@ constexpr HwregDescriptor CDNA3_4_HWREGS[] = { // named but unsupported until their VM state and privilege side effects are // represented. {1, "MODE", HwregState::Mode, HwregWritePolicy::UserWritable}, - {2, "STATUS", HwregState::Status, HwregWritePolicy::ReadOnly}, - {3, "TRAPSTS", HwregState::Unsupported, HwregWritePolicy::UserWritable}, + {2, "STATUS", HwregState::Status, HwregWritePolicy::Privileged}, + {3, "TRAPSTS", HwregState::Trapsts, HwregWritePolicy::UserWritable}, {4, "HW_ID", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, {5, "GPR_ALLOC", HwregState::GprAllocCdna3_4, HwregWritePolicy::ReadOnly}, {6, "LDS_ALLOC", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, @@ -168,7 +169,7 @@ constexpr HwregDescriptor RDNA1_HWREGS[] = { // are named for diagnostics but stay unsupported without modeled VM state. {1, "MODE", HwregState::Mode, HwregWritePolicy::UserWritable}, {2, "STATUS", HwregState::Status, HwregWritePolicy::ReadOnly}, - {3, "TRAPSTS", HwregState::Unsupported, HwregWritePolicy::UserWritable}, + {3, "TRAPSTS", HwregState::Trapsts, HwregWritePolicy::UserWritable}, {4, "HW_ID_LEGACY", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, {5, "GPR_ALLOC", HwregState::GprAllocGfx9_10, HwregWritePolicy::ReadOnly}, {6, "LDS_ALLOC", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, @@ -201,7 +202,7 @@ constexpr HwregDescriptor RDNA2_HWREGS[] = { // are named for diagnostics but stay unsupported without modeled VM state. {1, "MODE", HwregState::Mode, HwregWritePolicy::UserWritable}, {2, "STATUS", HwregState::Status, HwregWritePolicy::ReadOnly}, - {3, "TRAPSTS", HwregState::Unsupported, HwregWritePolicy::UserWritable}, + {3, "TRAPSTS", HwregState::Trapsts, HwregWritePolicy::UserWritable}, {5, "GPR_ALLOC", HwregState::GprAllocGfx9_10, HwregWritePolicy::ReadOnly}, {6, "LDS_ALLOC", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, {7, "IB_STS", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, @@ -232,7 +233,7 @@ constexpr HwregDescriptor RDNA3_HWREGS[] = { // but left unsupported until VM state and privilege side effects are added. {1, "MODE", HwregState::Mode, HwregWritePolicy::UserWritable}, {2, "STATUS", HwregState::Status, HwregWritePolicy::ReadOnly}, - {3, "TRAPSTS", HwregState::Unsupported, HwregWritePolicy::UserWritable}, + {3, "TRAPSTS", HwregState::Trapsts, HwregWritePolicy::UserWritable}, {5, "GPR_ALLOC", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, {6, "LDS_ALLOC", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, {7, "IB_STS", HwregState::Unsupported, HwregWritePolicy::ReadOnly}, @@ -376,6 +377,9 @@ HwregAccessResult read_raw_hwreg(Wavefront &wf, HwregState state, uint32_t &raw_ case HwregState::Status: raw_value = wf.status_raw(); return HwregAccessResult::Success; + case HwregState::Trapsts: + raw_value = wf.trapsts(); + return HwregAccessResult::Success; case HwregState::GprAllocGfx9_10: raw_value = gfx9_10_gpr_alloc_raw(wf); return HwregAccessResult::Success; @@ -405,7 +409,21 @@ HwregAccessResult write_raw_hwreg(Wavefront &wf, HwregState state, uint32_t raw_ case HwregState::WaveSchedMode: wf.set_wave_sched_mode_raw(raw_value); return HwregAccessResult::Success; + case HwregState::Trapsts: + // The trap handler clears the excp bit it just serviced before s_rfe, so + // this has to write through to wave state rather than report Unsupported. + wf.set_trapsts(raw_value); + return HwregAccessResult::Success; case HwregState::Status: + // Only reachable from a privileged (trap-handler) write; the policy check + // in write_hwreg_field() refuses user-mode writes before we get here. The + // gfx9 trap handler sets STATUS.HALT this way before returning. + // + // That makes this the other origin of STATUS.HALT, so it owns the bit now: + // drop any s_sendmsghalt provenance, whichever way the handler wrote it. + wf.set_status_raw(raw_value); + wf.set_self_halted(false); + return HwregAccessResult::Success; case HwregState::GprAllocGfx9_10: case HwregState::GprAllocCdna3_4: case HwregState::IbStsGfx1250: @@ -478,7 +496,12 @@ HwregAccessResult write_hwreg_field(Wavefront &wf, uint16_t hwreg, uint32_t src) case HwregWritePolicy::ReadOnly: return HwregAccessResult::ReadOnly; case HwregWritePolicy::Privileged: - return HwregAccessResult::Privileged; + // A wave running the trap handler is in privileged mode (hardware sets + // STATUS.PRIV on trap entry), which is exactly the context these registers + // are writable from. Everything else is user mode and is refused. + if (!wf.in_trap_handler()) + return HwregAccessResult::Privileged; + break; case HwregWritePolicy::UserWritable: break; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h index 5d15599c950e..0b843a08b7a8 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/instruction_compute_unit_view.h @@ -28,6 +28,7 @@ class L2Cache; class Lds; class OperandExecutionAccess; class RegisterAccess; +class Wavefront; /// @brief Narrow CU API exposed to AMDGPU instruction emulation code. /// @@ -51,6 +52,9 @@ class InstructionComputeUnitView { simdojo::ComponentID id() const; simdojo::SimulationEngine *engine() const; void request_functional_yield(); + bool handle_sendmsg(Wavefront &wf, uint32_t message); + void notify_trap_complete(Wavefront &wf); + bool signal_queue_exception(uint32_t queue_id, uint32_t process_id, uint64_t status); private: uint32_t read_sgpr(uint32_t reg_idx) const; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp index c792104b9c21..adb322631061 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.cpp @@ -211,10 +211,40 @@ void L1VectorCache::write_bytes(uint64_t addr, const uint8_t *src, uint32_t size void L1VectorCache::load(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, uint8_t *dst, Mtype mtype, bool non_temporal, bool request_l1_bypass, uint32_t wf_size, uint32_t vmid, - std::span element_lane_masks) { + uint32_t addr_stride, std::span element_lane_masks) { auto coherence_guard = DeviceCacheCoherence::instance().acquire_l1_access(); synchronize_epoch_locked(); uint32_t stride = num_elems * elem_size; + // Scratch swizzle: consecutive dwords of one lane's private space sit + // addr_stride bytes apart, the hardware dword-interleaved layout rocm-dbgapi + // reads. Addresses are materialized per element, so this also honours + // per-element lane validity: an element a lane is not valid for is skipped + // rather than strided over. With no element masks this walks exactly the + // lanes and bytes the uniform path would. + if (addr_stride != 0) { + const uint32_t astride = addr_stride; + for (uint32_t elem = 0; elem < num_elems; ++elem) { + uint64_t mask = + element_lane_masks.empty() ? lane_mask : (element_lane_masks[elem] & lane_mask); + while (mask) { + const uint32_t lane = std::countr_zero(mask); + mask &= mask - 1; + const uint64_t base = addrs[lane]; + uint32_t copied = elem * elem_size; + const uint32_t elem_end = copied + elem_size; + while (copied < elem_end) { + const uint32_t byte_in_dword = static_cast((base + copied) & 3); + const uint32_t chunk = std::min(elem_end - copied, 4 - byte_in_dword); + const uint64_t ea = + (base & ~uint64_t{3}) + ((base & 3) + copied) / 4 * astride + byte_in_dword; + read_bytes(ea, dst + lane * stride + copied, chunk, mtype, non_temporal, + request_l1_bypass, vmid); + copied += chunk; + } + } + } + return; + } if (!all_elements_use_lane_mask(element_lane_masks, lane_mask, num_elems)) { uint64_t full_lane_mask = fully_valid_lane_mask(element_lane_masks, lane_mask); for_each_coalesced_lane_run( @@ -243,7 +273,7 @@ void L1VectorCache::load(const uint64_t *addrs, uint64_t lane_mask, uint32_t ele void L1VectorCache::store(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, const uint8_t *src, Mtype mtype, bool non_temporal, - uint32_t wf_size, uint32_t vmid, + uint32_t wf_size, uint32_t vmid, uint32_t addr_stride, std::span element_lane_masks) { auto coherence_guard = DeviceCacheCoherence::instance().acquire_l1_access(); synchronize_epoch_locked(); @@ -252,6 +282,36 @@ void L1VectorCache::store(const uint64_t *addrs, uint64_t lane_mask, uint32_t el ++store_count_; if (active_lanes > 0) ++store_active_count_; + // Scratch swizzle: consecutive dwords of one lane's private space sit + // addr_stride bytes apart, the hardware dword-interleaved layout rocm-dbgapi + // reads. Addresses are materialized per element, so this also honours + // per-element lane validity: an element a lane is not valid for is skipped + // rather than strided over. With no element masks this walks exactly the + // lanes and bytes the uniform path would. + if (addr_stride != 0) { + const uint32_t astride = addr_stride; + for (uint32_t elem = 0; elem < num_elems; ++elem) { + uint64_t mask = + element_lane_masks.empty() ? lane_mask : (element_lane_masks[elem] & lane_mask); + store_l2_writes_ += std::popcount(mask); + while (mask) { + const uint32_t lane = std::countr_zero(mask); + mask &= mask - 1; + const uint64_t base = addrs[lane]; + uint32_t copied = elem * elem_size; + const uint32_t elem_end = copied + elem_size; + while (copied < elem_end) { + const uint32_t byte_in_dword = static_cast((base + copied) & 3); + const uint32_t chunk = std::min(elem_end - copied, 4 - byte_in_dword); + const uint64_t ea = + (base & ~uint64_t{3}) + ((base & 3) + copied) / 4 * astride + byte_in_dword; + write_bytes(ea, src + lane * stride + copied, chunk, mtype, non_temporal, vmid); + copied += chunk; + } + } + } + return; + } if (!all_elements_use_lane_mask(element_lane_masks, lane_mask, num_elems)) { uint64_t full_lane_mask = fully_valid_lane_mask(element_lane_masks, lane_mask); store_l2_writes_ += for_each_coalesced_lane_run( diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h index 27e73ad56752..87f4568506a4 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l1_vector_cache.h @@ -48,14 +48,16 @@ class L1VectorCache { /// @p lane_mask is the union of lanes valid for at least one element. void load(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, uint8_t *dst, Mtype mtype, bool non_temporal, bool request_l1_bypass, uint32_t wf_size, - uint32_t vmid = 0, std::span element_lane_masks = {}); + uint32_t vmid = 0, uint32_t addr_stride = 0, + std::span element_lane_masks = {}); /// @param element_lane_masks Empty when every element uses @p lane_mask; /// otherwise contains exactly @p num_elems masks. In the latter form, /// @p lane_mask is the union of lanes valid for at least one element. void store(const uint64_t *addrs, uint64_t lane_mask, uint32_t elem_size, uint32_t num_elems, const uint8_t *src, Mtype mtype, bool non_temporal, uint32_t wf_size, - uint32_t vmid = 0, std::span element_lane_masks = {}); + uint32_t vmid = 0, uint32_t addr_stride = 0, + std::span element_lane_masks = {}); void invalidate(uint64_t addr, uint32_t vmid = 0); void invalidate_all(); diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h index 39d129765e51..b35b249fff43 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/mem_state.h @@ -72,6 +72,15 @@ struct ScalarMemState : DynamicInstState { ScalarMemState() { tag_ = SCALAR_MEM; } uint64_t addr = 0; uint32_t dst_reg_base = 0; + /// @brief The SDATA operand selector, before it was resolved to a physical + /// register. + /// @details Selectors 108..123 name the trap-temporary file rather than a + /// slot in the wave's SGPR allocation, so the load write-back has to dispatch + /// on the selector; dst_reg_base is meaningless for those. The ROCr trap + /// handler loads straight into TTMPs (`s_load_dwordx2 ttmp[2:3], ...`), so + /// this is a live path, and writing dst_reg_base for one would land outside + /// the wave's own allocation. + uint32_t dst_selector = 0; uint32_t num_dwords = 0; uint32_t elem_size = 4; bool sign_extend = false; @@ -110,6 +119,21 @@ struct VectorMemState : DynamicInstState { // cacheability and response policy used by the downstream memory path. bool request_force_l1_bypass = false; bool sign_extend = false; + // Scratch (private) accesses store data in the hardware dword-interleaved + // ("swizzled") layout that rocm-dbgapi reads: consecutive dwords of a lane's + // private space are lane_count*4 bytes apart, not contiguous. When + // scratch_swizzle is set, per_lane_addr holds the swizzled address of element + // 0 and scratch_addr_stride (= lane_count * sizeof(uint32_t)) is the per-element + // destination-address stride; the register/LDS buffer indexing is unchanged. + // See rocm-dbgapi memory.cpp private_swizzled conversion. + // FLAT routing is per lane: one wave can mix private-aperture lanes with + // global ones. scratch_lane_mask records exactly which lanes were swizzled, + // so the stride is applied to those and not to their global neighbours. + // For dedicated SCRATCH ops every active lane is private and this equals + // lane_mask. + bool scratch_swizzle = false; + uint64_t scratch_lane_mask = 0; + uint32_t scratch_addr_stride = 0; bool d16_hi = false; ///< D16_HI load: write to upper 16 bits, preserve lower 16. bool d16_lo = false; ///< D16 load: write to lower 16 bits, preserve upper 16. AtomicOp atomic_op = AtomicOp::NONE; ///< Atomic RMW operation (NONE for regular loads/stores). diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp index 39eeeb8b6505..fc266ec800bb 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/memory_pipeline.cpp @@ -3,6 +3,7 @@ #include "rocjitsu/vm/amdgpu/memory_pipeline.h" #include "rocjitsu/isa/arch/amdgpu/shared/ds_transpose.h" +#include "rocjitsu/isa/arch/amdgpu/shared/scalar_operand_read.h" #include "rocjitsu/vm/amdgpu/cluster_lds_multicast.h" #include "rocjitsu/vm/amdgpu/command_processor.h" #include "rocjitsu/vm/amdgpu/compute_unit.h" @@ -227,9 +228,10 @@ ScalarMemPipeline::complete_access(Instruction &inst, Wavefront &wf, auto &d = *inst.data_as(); if (!d.is_load) return MemoryAccessCompletion::Complete; - auto &cu = wf.raw_cu(); for (uint32_t i = 0; i < d.num_dwords; ++i) { - cu.write_sgpr(d.dst_reg_base + i, d.response_data[i]); + // Dispatch on the selector, not the resolved base: an SDATA of 108..123 + // names the trap-temporary file, and the ROCr handler loads into TTMPs. + amdgpu::write_scalar_selector(wf, d.dst_selector + i, d.response_data[i]); } // Trace: log SMEM load values for debugging. util::Logger::vm([&](auto &os) { @@ -492,14 +494,33 @@ void GlobalMemPipeline::initiate_access(Instruction &inst, Wavefront &wf) { return; } + // A FLAT wave can route some lanes to the private aperture and others to + // global memory. The swizzle stride is a property of the lanes that landed in + // scratch, not of the instruction, so issue the two groups separately rather + // than striding a global lane's second dword by lane_count*4. Uniform waves + // (including every dedicated SCRATCH op) take the single-request path. + const uint64_t scratch_lanes = d.scratch_swizzle ? d.scratch_lane_mask & d.lane_mask : 0; + const uint64_t plain_lanes = d.lane_mask & ~scratch_lanes; + const uint32_t stride = d.scratch_addr_stride; + if (d.is_load) { d.response_data.assign(d.wf_size * d.num_elems * d.elem_size, 0); - l1_->load(d.per_lane_addr.data(), d.lane_mask, d.elem_size, d.num_elems, d.response_data.data(), - d.mtype, d.non_temporal, d.request_force_l1_bypass, d.wf_size, wf.process_id(), - d.element_lane_masks); + if (scratch_lanes) + l1_->load(d.per_lane_addr.data(), scratch_lanes, d.elem_size, d.num_elems, + d.response_data.data(), d.mtype, d.non_temporal, d.request_force_l1_bypass, + d.wf_size, wf.process_id(), stride, d.element_lane_masks); + if (plain_lanes) + l1_->load(d.per_lane_addr.data(), plain_lanes, d.elem_size, d.num_elems, + d.response_data.data(), d.mtype, d.non_temporal, d.request_force_l1_bypass, + d.wf_size, wf.process_id(), 0, d.element_lane_masks); } else { - l1_->store(d.per_lane_addr.data(), d.lane_mask, d.elem_size, d.num_elems, d.store_data.data(), - d.mtype, d.non_temporal, d.wf_size, wf.process_id(), d.element_lane_masks); + if (scratch_lanes) + l1_->store(d.per_lane_addr.data(), scratch_lanes, d.elem_size, d.num_elems, + d.store_data.data(), d.mtype, d.non_temporal, d.wf_size, wf.process_id(), stride, + d.element_lane_masks); + if (plain_lanes) + l1_->store(d.per_lane_addr.data(), plain_lanes, d.elem_size, d.num_elems, d.store_data.data(), + d.mtype, d.non_temporal, d.wf_size, wf.process_id(), 0, d.element_lane_masks); } } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h index 8a7b6ce35762..578629657702 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h @@ -116,6 +116,7 @@ class ShaderProcessorInput { wf->set_lds(placement->lds); wf->set_dispatch_id(wg.entry->dispatch_id); wf->set_process_id(wg.entry->process_id); + wf->set_queue_id(wg.entry->queue_id); wf->set_exec(initial_exec_mask_for_wave(*wg.entry, wg.global_wg_id, w, cu->wf_size())); init_wf(cu, wf, *wg.entry, wg.global_wg_id, w); wg_wfs.push_back(wf); @@ -129,17 +130,41 @@ class ShaderProcessorInput { return false; } + /// @brief Step each CU once (one round-robin pass within this SE). + bool step() { + bool any_runnable = false; + for (auto *cu : cus_) { + if (cu->has_runnable_wfs()) { + cu->step(); + any_runnable = true; + } + } + return any_runnable; + } /// @brief Check if any WGs are queued or any CU is active. bool has_pending() const { for (auto &q : pipe_queues_) if (!q.empty()) return true; for (auto *cu : cus_) - if (cu->has_active_wfs()) + if (cu->has_runnable_wfs()) return true; return false; } + /// @brief Run all CUs to idle (functional mode, for test harness use). + void run_to_idle() { + bool progress = true; + while (progress) { + progress = false; + for (auto *cu : cus_) { + if (cu->has_runnable_wfs()) { + cu->step(); + progress = true; + } + } + } + } /// @brief Legacy: select a CU with capacity for direct dispatch. /// /// @details Used by dispatch_workgroups() fallback path when SPIs are not diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp index 9af1a1b52145..229b43e21dce 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.cpp @@ -42,7 +42,7 @@ void Wavefront::barrier_wait(int32_t barrier_id) { cu_.barrier_wait(*this, barri bool Wavefront::barrier_leave() { return cu_.named_barrier_leave(*this); } -void Wavefront::halt() { +void Wavefront::halt(CpCompletionNotice notice) { // s_endpgm terminates the wave, frees its resources, and notifies the CP as one // action, mirroring hardware. Order matters: // (1) fire the halt hook while registers are still live so observers snapshot @@ -55,7 +55,7 @@ void Wavefront::halt() { const uint32_t dispatch_id = dispatch_id_; const uint32_t wg_id = wg_id_; cu_.free_wavefront_resources(*this); - cu_.release_wf(dispatch_id, wg_id); + cu_.release_wf(dispatch_id, wg_id, notice); } void Wavefront::release_wait_counter(WaitCounterType type) { diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h index 408dbd6c496e..47a36873f618 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h @@ -15,6 +15,7 @@ #include "rocjitsu/vm/plugins/wavefront_state.h" #include "rocjitsu/vm/thread_context.h" +#include #include #include #include @@ -152,6 +153,8 @@ class Wavefront : public ThreadContext { /// @brief Return the workgroup ID assigned at dispatch. /// @returns Workgroup ID. uint32_t wg_id() const { return wg_id_; } + const std::array &wg_coord() const { return wg_coord_; } + void set_wg_coord(uint32_t x, uint32_t y, uint32_t z) { wg_coord_ = {x, y, z}; } /// @brief Return the dispatch ID assigned at dispatch. uint32_t dispatch_id() const { return dispatch_id_; } @@ -159,6 +162,33 @@ class Wavefront : public ThreadContext { /// @brief Set the dispatch ID (called by DispatchController). void set_dispatch_id(uint32_t id) { dispatch_id_ = id; } + /// @brief Return the AQL ring packet id (dispatch's ring index) for this wave. + /// @details This is the queue read index at which the dispatch packet was + /// fetched. rocm-dbgapi correlates a trapped wave to its dispatch by matching + /// this against the queue's read/write dispatch ids (TTMP11[6:30]). + uint32_t aql_packet_id() const { return aql_packet_id_; } + + /// @brief Set the AQL ring packet id (called at dispatch). + void set_aql_packet_id(uint32_t id) { aql_packet_id_ = id; } + + /// @brief GPU load bias for code-object-relative function addresses. + uint64_t code_load_bias() const { return code_load_bias_; } + void set_code_load_bias(uint64_t bias) { code_load_bias_ = bias; } + + /// @brief Return this wave's position within its workgroup (0-based). + uint32_t wave_in_group() const { return wave_in_group_; } + + /// @brief Set this wave's position within its workgroup (called at dispatch). + void set_wave_in_group(uint32_t pos) { wave_in_group_ = pos; } + + /// @brief Return the KFD queue ID that launched this wave. + uint32_t queue_id() const { return queue_id_; } + + /// @brief Set the KFD queue ID (called by the command processor at dispatch). + /// @details Used by the debugger path to correlate a stopped wave with the + /// queue whose context-save-restore area holds its saved state. + void set_queue_id(uint32_t id) { queue_id_ = id; } + /// @brief Return the owning process ID (PASID analog). uint32_t process_id() const { return process_id_; } @@ -297,6 +327,10 @@ class Wavefront : public ThreadContext { static constexpr uint32_t GPR_IDX_EN_BIT = 1u << 27; static constexpr uint32_t FP16_OVFL_BIT = 1u << 23; + /// STATUS.HALT. Bit 13 on every modelled architecture -- see StatusReg::HALT + /// in each arch's isa.h, which all spell it member<13, 13>. + static constexpr uint32_t kStatusHaltMask = 1u << 13; + bool dx10_clamp() const { return (mode_raw_ & DX10_CLAMP_BIT) != 0; } bool gpr_idx_en() const { return mode_has_gpr_idx_en_ && ((mode_raw_ & GPR_IDX_EN_BIT) != 0); } bool fp16_ovfl() const { return (mode_raw_ & FP16_OVFL_BIT) != 0; } @@ -321,6 +355,14 @@ class Wavefront : public ThreadContext { /// @brief Set the per-lane private scratch allocation size in bytes. void set_scratch_lane_size(uint32_t val) { scratch_lane_size_ = val; } + /// @brief Return this wave's scratch scoreboard id (its slot in the queue's + /// scratch allocation). rocm-dbgapi multiplies it by COMPUTE_TMPRING_SIZE's + /// per-wave size to locate each wave's private memory. + uint32_t scratch_scoreboard_id() const { return scratch_scoreboard_id_; } + + /// @brief Set this wave's scratch scoreboard id (set at dispatch by the CP). + void set_scratch_scoreboard_id(uint32_t val) { scratch_scoreboard_id_ = val; } + uint64_t shared_aperture_base() const { return shared_aperture_base_; } uint64_t shared_aperture_limit() const { return shared_aperture_limit_; } uint64_t private_aperture_base() const { return private_aperture_base_; } @@ -480,6 +522,21 @@ class Wavefront : public ThreadContext { set_status_raw(val ? (s | 1u) : (s & ~1u)); } + /// @brief STATUS.HALT, the architectural "this wave is halted" bit. + /// @details Bit 13 on every architecture this emulator models (StatusReg::HALT + /// in each arch's isa.h). s_sendmsghalt sets it and s_rfe reads it to decide + /// whether the wave stays stopped on the way out of the trap handler, so it is + /// live wave state that a debugger resume has to clear -- not a private flag. + /// Named here so the bit position is written once instead of at each user. + bool status_halt() const { return (status_raw() & kStatusHaltMask) != 0; } + + /// @brief Set or clear STATUS.HALT. + /// @param val New STATUS.HALT value. + void set_status_halt(bool val) { + const uint32_t s = status_raw(); + set_status_raw(val ? (s | kStatusHaltMask) : (s & ~kStatusHaltMask)); + } + /// @brief Return the current execution state. /// @returns Current WfState. WfState state() const { return state_; } @@ -493,12 +550,200 @@ class Wavefront : public ThreadContext { /// @retval false Slot is active (running, waiting, or at a barrier). bool is_halted() const { return state_ == WfState::HALTED; } + // -- KFD debugger (trap) state -- + // + // These model the wave-level state the AMD trap handler maintains for + // rocm-dbgapi: the trap temporary registers (TTMP0-15), the trap status + // register (TRAPSTS), and the debug halt/single-step bits. + + /// @brief Read a trap temporary register (TTMP0-15). + uint32_t ttmp(uint32_t idx) const { return idx < 16 ? ttmp_[idx] : 0; } + + /// @brief Write a trap temporary register (TTMP0-15). + void set_ttmp(uint32_t idx, uint32_t val) { + if (idx < 16) + ttmp_[idx] = val; + } + + /// @brief Cycles this wave still owes an in-flight s_sleep. + /// @details S_SLEEP is a delay and nothing else: it has no register result, + /// so retiring it in a single step gives it no architectural effect at all. + /// A spin loop then runs at full speed and spends its time spread evenly + /// over its own instructions rather than parked at the sleep, which changes + /// where an asynchronous debugger suspend lands inside it. + uint32_t sleep_cycles() const { return sleep_cycles_; } + void set_sleep_cycles(uint32_t cycles) { sleep_cycles_ = cycles; } + void tick_sleep() { --sleep_cycles_; } + + /// @brief Whether the wave is currently fetching from its configured TBA. + bool in_trap_handler() const { return in_trap_handler_; } + void set_in_trap_handler(bool value) { in_trap_handler_ = value; } + + bool trap_interrupt_sent() const { return trap_interrupt_sent_; } + void set_trap_interrupt_sent(bool value) { trap_interrupt_sent_ = value; } + + /// @brief Whether the live STATUS.HALT was raised by the wave's own + /// s_sendmsghalt rather than by the trap handler's s_setreg. + /// + /// @details Both halt the wave inside the handler and both look identical in + /// the CWSR record, but a debugger resume has to treat them oppositely. The + /// ROCr handler's s_setreg raises HALT and *then* returns, so the bit is the + /// handler's request that the wave stay stopped: clearing it on a resume + /// loses the breakpoint. A wave halted at s_sendmsghalt has already reported + /// and is waiting to be let go, so leaving the bit set is what strands it. + /// The record cannot tell them apart, so record the provenance here at the + /// point where it is still known. + bool self_halted() const { return self_halted_; } + void set_self_halted(bool value) { self_halted_ = value; } + uint32_t trap_saved_status() const { return trap_saved_status_; } + void set_trap_saved_status(uint32_t value) { trap_saved_status_ = value; } + uint64_t trap_saved_exec() const { return trap_saved_exec_; } + void set_trap_saved_exec(uint64_t value) { trap_saved_exec_ = value; } + + /// @brief Record the trap id supplied by hardware trap entry. + void set_trap_id(uint32_t value) { trap_id_ = value; } + + /// @brief Read the trap status register (TRAPSTS / EXCP flags). + uint32_t trapsts() const { return trapsts_; } + + /// @brief Write the trap status register. + void set_trapsts(uint32_t val) { trapsts_ = val; } + + /// @brief EXCP causes raised by the instruction currently executing. + /// @details TRAPSTS.EXCP is a sticky accumulator: hardware records a cause + /// there and never clears it on its own, so it cannot say whether *this* + /// instruction raised the cause. Trap delivery depends on that, and on + /// hardware it depends only on the cause occurring while MODE.EXCP_EN has + /// the bit set -- not on the sticky bit changing. Cause classifiers report + /// here as well as into TRAPSTS so the CU has the transient mask. + uint32_t pending_alu_causes() const { return pending_alu_causes_; } + + /// @brief Clear the transient mask, before executing the next instruction. + void clear_pending_alu_causes() { pending_alu_causes_ = 0; } + + /// @brief Record EXCP causes raised by the instruction currently executing. + void raise_alu_causes(uint32_t causes) { pending_alu_causes_ |= causes; } + + /// @brief Whether the debugger has stopped this wave (trapped or suspended). + /// @details A debug-halted wave keeps its slot and all register state; the + /// scheduler skips it so the CU can go quiescent without retiring the wave. + bool debug_halted() const { return debug_halted_; } + void set_debug_halted(bool v) { debug_halted_ = v; } + + /// @brief Whether KFD has temporarily suspended this wave's queue. + /// @details Queue suspension freezes execution for a stable CWSR snapshot, + /// but unlike debug_halted it does not imply an architectural stop reason. + bool debug_suspended() const { return debug_suspended_; } + void set_debug_suspended(bool v) { debug_suspended_ = v; } + /// @brief Runtime-suspended: the queue's queue_percentage went to zero. + /// @details A separate reason from the debugger's, because the two overlap. + /// Sharing one bit let a runtime resume clear a debugger pause, and a + /// debugger or CWSR resume clear an active runtime pause. + bool runtime_suspended() const { return runtime_suspended_; } + void set_runtime_suspended(bool v) { runtime_suspended_ = v; } + + /// @brief Whether a *debugger* currently holds this wave stopped. + /// @details Deliberately excludes runtime_suspended_: KFD uses this to decide + /// which waves it may serialize into a CWSR record, count in the SUSPEND / + /// RESUME_QUEUES stopped set, and refuse to checkpoint. A queue the runtime + /// throttled to queue_percentage 0 is none of those things, and folding it in + /// makes RESUME_QUEUES fail its stopped-vs-restored count and publishes waves + /// to rocm-dbgapi that no debugger ever stopped. Ask debug_paused() instead + /// when the question is "may the scheduler issue this wave". + bool debug_stopped() const { return debug_halted_ || debug_suspended_; } + + /// @brief Whether any reason currently keeps this wave from being issued. + bool debug_paused() const { return debug_stopped() || runtime_suspended_; } + bool fatal_exception_pending() const { return fatal_exception_pending_; } + void set_fatal_exception_pending(bool pending) { fatal_exception_pending_ = pending; } + + /// @brief Whether a future debugger resume should request single-step mode. + bool debug_single_step() const { return single_step_; } + void set_debug_single_step(bool v) { single_step_ = v; } + + /// @brief The trap id recorded by the last s_trap (breakpoint = 1). + uint32_t trap_id() const { return trap_id_; } + + /// @brief Stable, unique debugger wave id (planted into TTMP4:5 on stop). + /// @details Zero until assigned. rocm-dbgapi reads this from the CWSR area as + /// the wave's identity, so it must be stable across re-serialization of the + /// same wave. Assigned lazily by the driver on the first stop. + uint64_t debug_wave_id() const { return debug_wave_id_; } + void set_debug_wave_id(uint64_t id) { debug_wave_id_ = id; } + + /// @brief Read one allocated SGPR for debugger state capture. + uint32_t debug_read_sgpr(uint32_t reg) const; + + /// @brief Read one allocated VGPR lane for debugger state capture. + uint32_t debug_read_vgpr(uint32_t reg, uint32_t lane) const; + + /// @brief Write one allocated SGPR from debugger state restore. + void debug_write_sgpr(uint32_t reg, uint32_t value); + + /// @brief Write one allocated VGPR lane from debugger state restore. + void debug_write_vgpr(uint32_t reg, uint32_t lane, uint32_t value); + + /// @brief Stop this wave in the debugger (models the trap handler entry). + /// @param trap_id Trap id from the s_trap immediate (breakpoint = 1). + /// @details Records the trap id and halts the wave for debugger inspection. + /// The PC is advanced past the s_trap by the caller (issue_instruction), so + /// the saved PC points just after the trap, matching the ROCr trap handler. + void debug_trap(uint32_t trap_id) { + trap_id_ = trap_id; + debug_halted_ = true; + single_step_ = false; + } + + /// @brief The wave state a debug stop mutates, captured so it can be undone. + /// + /// @details A driver stop is claimed before the CWSR record that describes it + /// can be written, because the serializer selects waves by debug_stopped(). + /// If publication then fails there is no debugger-visible record, so the stop + /// has to be rolled back rather than left in place: a halted wave with no + /// record is one the debugger cannot see, resume, or be told about, and the + /// compute unit has already been told the access was handled. + struct DebugStopState { + uint32_t trapsts = 0; + uint32_t mode_raw = 0; + uint32_t trap_id = 0; + bool debug_halted = false; + bool single_step = false; + bool fatal_exception_pending = false; + }; + + /// @brief Capture the fields @ref restore_debug_stop_state puts back. + DebugStopState debug_stop_state() const { + return DebugStopState{trapsts_, mode_raw_, trap_id_, + debug_halted_, single_step_, fatal_exception_pending_}; + } + + /// @brief Undo a debug stop captured by @ref debug_stop_state. + void restore_debug_stop_state(const DebugStopState &saved) { + trapsts_ = saved.trapsts; + set_mode_raw(saved.mode_raw); + trap_id_ = saved.trap_id; + debug_halted_ = saved.debug_halted; + single_step_ = saved.single_step; + fatal_exception_pending_ = saved.fatal_exception_pending; + } + /// @brief Halt this wavefront and notify the CU for WG completion tracking. /// @details Transitions to HALTED and decrements the CU's per-WG refcount. /// When the refcount reaches zero (all WFs in the WG halted), the CU fires /// notify_wg_complete to the CP. This is the sole completion detection path — /// driven entirely by s_endpgm → end() → halt(). - void halt(); + /// @brief Whether halting should tell the command processor the workgroup + /// finished. + /// + /// @details Suppressed only when the CP is already tearing the queue down and + /// is holding, or about to take, hw_queue_mutex_. Notifying from there would + /// make the caller acquire hw_queue_mutex_ while it holds the CU's wave-state + /// lock, which is the reverse of the order handle_doorbell() uses + /// (hw_queue_mutex_ -> dispatch_wf -> wave_state_mutex_) and deadlocks the + /// two threads against each other. + enum class CpCompletionNotice : uint8_t { Send, Suppress }; + + void halt(CpCompletionNotice notice = CpCompletionNotice::Send); /// @brief End program execution. If all memory ops are drained, halts /// immediately. Otherwise, transitions to ENDING and lets the memory @@ -521,7 +766,11 @@ class Wavefront : public ThreadContext { void reset() { pc = 0; wg_id_ = 0; + wg_coord_ = {}; dispatch_id_ = 0; + aql_packet_id_ = 0; + code_load_bias_ = 0; + wave_in_group_ = 0; process_id_ = 0; lds_base_ = 0; lds_size_ = 0; @@ -539,6 +788,7 @@ class Wavefront : public ThreadContext { set_wave_sched_mode_raw(0); scratch_base_ = 0; scratch_lane_size_ = 0; + scratch_scoreboard_id_ = 0; shared_aperture_base_ = 0; shared_aperture_limit_ = 0; private_aperture_base_ = 0; @@ -550,6 +800,24 @@ class Wavefront : public ThreadContext { wait_target_ = {}; ready_cycle_ = 0; state_ = WfState::HALTED; + for (auto &t : ttmp_) + t = 0; + trapsts_ = 0; + pending_alu_causes_ = 0; + sleep_cycles_ = 0; + in_trap_handler_ = false; + trap_interrupt_sent_ = false; + self_halted_ = false; + trap_saved_status_ = 0; + trap_saved_exec_ = 0; + debug_halted_ = false; + debug_suspended_ = false; + runtime_suspended_ = false; + fatal_exception_pending_ = false; + single_step_ = false; + trap_id_ = 0; + debug_wave_id_ = 0; + queue_id_ = 0; } protected: @@ -567,15 +835,20 @@ class Wavefront : public ThreadContext { ComputeUnitCore &cu_; ///< Parent CU (permanent, set at construction). InstructionComputeUnitView cu_view_; - uint32_t wf_id_ = 0; ///< Slot index within the CU (permanent). - uint32_t wg_id_ = 0; ///< Workgroup ID (set per dispatch). - uint32_t dispatch_id_ = 0; ///< Dispatch ID (set per dispatch, unique per dispatch). - uint32_t process_id_ = 0; ///< Owning process ID (PASID analog, set per dispatch). - uint32_t lds_base_ = 0; ///< Per-WG LDS base offset (set per dispatch). - uint32_t lds_size_ = 0; ///< Aligned per-WG LDS allocation size. - Lds *lds_ = nullptr; ///< Placement-selected LDS backing; nullptr means CU-local LDS. - uint32_t cluster_rank_ = 0; ///< Workgroup rank inside the dispatch cluster. - uint32_t cluster_size_ = 1; ///< Number of workgroups in the dispatch cluster. + uint32_t wf_id_ = 0; ///< Slot index within the CU (permanent). + uint32_t wg_id_ = 0; ///< Workgroup ID (set per dispatch). + std::array wg_coord_{}; + uint32_t dispatch_id_ = 0; ///< Dispatch ID (set per dispatch, unique per dispatch). + uint32_t aql_packet_id_ = 0; ///< AQL ring packet id of the dispatch (debugger correlation). + uint64_t code_load_bias_ = 0; ///< GPU load bias for code-object-relative call targets. + uint32_t wave_in_group_ = 0; ///< Position of this wave within its workgroup (debugger). + uint32_t process_id_ = 0; ///< Owning process ID (PASID analog, set per dispatch). + uint32_t queue_id_ = 0; ///< KFD queue ID that launched this wave (debugger correlation). + uint32_t lds_base_ = 0; ///< Per-WG LDS base offset (set per dispatch). + uint32_t lds_size_ = 0; ///< Aligned per-WG LDS allocation size. + Lds *lds_ = nullptr; ///< Placement-selected LDS backing; nullptr means CU-local LDS. + uint32_t cluster_rank_ = 0; ///< Workgroup rank inside the dispatch cluster. + uint32_t cluster_size_ = 1; ///< Number of workgroups in the dispatch cluster. uint32_t wf_size_ = 0; ///< Lanes per wavefront (ISA-fixed). uint32_t num_sgprs_ = 0; ///< Allocated scalar registers (set at dispatch). @@ -592,15 +865,16 @@ class Wavefront : public ThreadContext { uint64_t lane_mask() const { return wf_size_ >= 64 ? ~0ULL : ((1ULL << wf_size_) - 1ULL); } - uint64_t exec_ = ~0ULL; ///< EXEC mask -- one bit per lane (1 = active). - uint64_t vcc_ = 0; ///< Vector condition code (per-lane comparison result). - uint32_t m0_ = 0; ///< M0 special register (misc addressing). - uint32_t mode_raw_ = 0; ///< MODE register state. - bool mode_has_gpr_idx_en_ = false; ///< True when MODE[27] is GPR_IDX_EN. - uint8_t vgpr_msb_mode_ = 0; ///< S_SET_VGPR_MSB layout for MODE VGPR_MSB bits. - uint32_t wave_sched_mode_raw_ = 0; ///< WAVE_SCHED_MODE register state. - uint64_t scratch_base_ = 0; ///< Per-wavefront scratch (private segment) base address. - uint32_t scratch_lane_size_ = 0; ///< Per-lane private scratch allocation size in bytes. + uint64_t exec_ = ~0ULL; ///< EXEC mask -- one bit per lane (1 = active). + uint64_t vcc_ = 0; ///< Vector condition code (per-lane comparison result). + uint32_t m0_ = 0; ///< M0 special register (misc addressing). + uint32_t mode_raw_ = 0; ///< MODE register state. + bool mode_has_gpr_idx_en_ = false; ///< True when MODE[27] is GPR_IDX_EN. + uint8_t vgpr_msb_mode_ = 0; ///< S_SET_VGPR_MSB layout for MODE VGPR_MSB bits. + uint32_t wave_sched_mode_raw_ = 0; ///< WAVE_SCHED_MODE register state. + uint64_t scratch_base_ = 0; ///< Per-wavefront scratch (private segment) base address. + uint32_t scratch_lane_size_ = 0; ///< Per-lane private scratch allocation size in bytes. + uint32_t scratch_scoreboard_id_ = 0; ///< Scratch slot index (debugger private-memory mapping). uint64_t shared_aperture_base_ = 0; uint64_t shared_aperture_limit_ = 0; uint64_t private_aperture_base_ = 0; @@ -613,6 +887,23 @@ class Wavefront : public ThreadContext { WfState state_ = WfState::HALTED; ///< Current execution state. WaitCounters wait_counters_; ///< Outstanding memory operation counters. + uint32_t ttmp_[16] = {}; ///< Trap temporary registers (TTMP0-15). + uint32_t trapsts_ = 0; ///< Trap status register (EXCP flags). + uint32_t pending_alu_causes_ = 0; ///< EXCP causes from the current instruction. + uint32_t sleep_cycles_ = 0; ///< Cycles left on an in-flight S_SLEEP. + bool in_trap_handler_ = false; ///< Executing the configured trap-handler shader. + bool trap_interrupt_sent_ = false; ///< Handler issued MSG_INTERRUPT for this entry. + bool self_halted_ = false; ///< STATUS.HALT came from this wave's s_sendmsghalt. + uint32_t trap_saved_status_ = 0; ///< Interrupted STATUS restored after handler completion. + uint64_t trap_saved_exec_ = 0; ///< Interrupted EXEC restored after handler completion. + bool debug_halted_ = false; ///< Stopped by the debugger (skipped by scheduler). + bool debug_suspended_ = false; ///< Queue-suspended for a stable CWSR snapshot. + bool runtime_suspended_ = false; ///< Queue-suspended by the runtime (queue_percentage 0). + bool fatal_exception_pending_ = false; + bool single_step_ = false; ///< Execute one instruction on resume, then re-stop. + uint32_t trap_id_ = 0; ///< Trap id from the last s_trap (breakpoint = 1). + uint64_t debug_wave_id_ = 0; ///< Stable debugger wave id (TTMP4:5); 0 until assigned. + public: uint32_t trace_inst_count_ = 0; ///< Debug: instruction count for trace. diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/rj_vm.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/rj_vm.cpp index 9e949c455151..dc3465f26513 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/rj_vm.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/rj_vm.cpp @@ -154,35 +154,81 @@ rj_status_t create_from_loaded(config::LoadedConfig &loaded, rj_vm_mode_t mode, return ROCJITSU_STATUS_SUCCESS; } -void reconstruct_embedded_pointers(uint32_t cmd, void *arg, size_t arg_size, size_t total_size) { - if (total_size <= arg_size) - return; +bool reconstruct_embedded_pointers(uint32_t cmd, void *arg, size_t arg_size, size_t total_size) { + if (total_size < arg_size) + return false; auto *extra = static_cast(arg) + arg_size; + const size_t inline_size = total_size - arg_size; + auto has_entries = [inline_size](size_t count, size_t entry_size) { + return entry_size == 0 || count <= inline_size / entry_size; + }; switch (cmd) { case AMDKFD_IOC_WAIT_EVENTS: { auto *args = static_cast(arg); - args->events_ptr = reinterpret_cast(extra); + if (!has_entries(args->num_events, sizeof(kfd_event_data))) + return false; + if (args->num_events > 0) + args->events_ptr = reinterpret_cast(extra); break; } case AMDKFD_IOC_MAP_MEMORY_TO_GPU: case AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU: { auto *args = static_cast(arg); - args->device_ids_array_ptr = reinterpret_cast(extra); + if (!has_entries(args->n_devices, sizeof(uint32_t))) + return false; + if (args->n_devices > 0) + args->device_ids_array_ptr = reinterpret_cast(extra); break; } case AMDKFD_IOC_GET_PROCESS_APERTURES_NEW: { auto *args = static_cast(arg); - args->kfd_process_device_apertures_ptr = reinterpret_cast(extra); + if (!has_entries(args->num_of_nodes, sizeof(kfd_process_device_apertures))) + return false; + if (args->num_of_nodes > 0) + args->kfd_process_device_apertures_ptr = reinterpret_cast(extra); break; } case AMDKFD_IOC_DBG_TRAP: { auto *args = static_cast(arg); switch (args->op) { - case KFD_IOC_DBG_TRAP_ENABLE: - args->enable.rinfo_ptr = reinterpret_cast(extra); + case KFD_IOC_DBG_TRAP_ENABLE: { + const size_t required = + std::min(static_cast(args->enable.rinfo_size), sizeof(kfd_runtime_info)); + if (required > inline_size) + return false; + if (required > 0) + args->enable.rinfo_ptr = reinterpret_cast(extra); break; + } case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT: - args->device_snapshot.snapshot_buf_ptr = reinterpret_cast(extra); + if (!has_entries(args->device_snapshot.num_devices, args->device_snapshot.entry_size)) + return false; + if (args->device_snapshot.num_devices > 0 && args->device_snapshot.snapshot_buf_ptr != 0) + args->device_snapshot.snapshot_buf_ptr = reinterpret_cast(extra); + break; + case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT: + if (!has_entries(args->queue_snapshot.num_queues, args->queue_snapshot.entry_size)) + return false; + if (args->queue_snapshot.num_queues > 0 && args->queue_snapshot.snapshot_buf_ptr != 0) + args->queue_snapshot.snapshot_buf_ptr = reinterpret_cast(extra); + break; + case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO: + if (args->query_exception_info.info_size > inline_size) + return false; + if (args->query_exception_info.info_size > 0 && args->query_exception_info.info_ptr != 0) + args->query_exception_info.info_ptr = reinterpret_cast(extra); + break; + case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES: + if (!has_entries(args->suspend_queues.num_queues, sizeof(uint32_t))) + return false; + if (args->suspend_queues.num_queues > 0 && args->suspend_queues.queue_array_ptr != 0) + args->suspend_queues.queue_array_ptr = reinterpret_cast(extra); + break; + case KFD_IOC_DBG_TRAP_RESUME_QUEUES: + if (!has_entries(args->resume_queues.num_queues, sizeof(uint32_t))) + return false; + if (args->resume_queues.num_queues > 0 && args->resume_queues.queue_array_ptr != 0) + args->resume_queues.queue_array_ptr = reinterpret_cast(extra); break; default: break; @@ -192,6 +238,7 @@ void reconstruct_embedded_pointers(uint32_t cmd, void *arg, size_t arg_size, siz default: break; } + return true; } } // namespace @@ -325,7 +372,11 @@ namespace { rj_status_t execute_impl(SimulatedKfd *driver, uint32_t process_id, rj_vm_cmd_t *cmd) { auto arg_size = _IOC_SIZE(cmd->cmd); - reconstruct_embedded_pointers(cmd->cmd, cmd->buf, arg_size, cmd->buf_size); + if (!reconstruct_embedded_pointers(cmd->cmd, cmd->buf, arg_size, cmd->buf_size)) { + cmd->result = -EINVAL; + cmd->shared_handle = -1; + return ROCJITSU_STATUS_SUCCESS; + } // For DBG_TRAP ENABLE the debugger's notifier pipe arrives as an SCM_RIGHTS // fd in cmd->in_handle (already in the daemon's fd space). Substitute it for @@ -356,7 +407,8 @@ rj_status_t execute_impl(SimulatedKfd *driver, uint32_t process_id, rj_vm_cmd_t } } - cmd->result = driver->ioctl(process_id, cmd->cmd, cmd->buf); + cmd->result = + driver->ioctl(process_id, cmd->cmd, cmd->buf, &cmd->in_mem_handle, cmd->in_proc_handle); cmd->shared_handle = -1; if (adopting_notifier && cmd->result == 0) cmd->in_handle = -1; @@ -377,14 +429,14 @@ rj_status_t execute_impl(SimulatedKfd *driver, uint32_t process_id, rj_vm_cmd_t } // namespace rj_status_t rj_vm_execute(rj_vm_t *vm, rj_vm_cmd_t *cmd) { - if (!vm || !cmd || !vm->vm || !vm->vm->driver()) + if (!vm || !cmd || !cmd->buf || !vm->vm || !vm->vm->driver()) return ROCJITSU_STATUS_INVALID_ARGUMENT; auto *driver = vm->vm->driver(); return execute_impl(driver, driver->local_process_id(), cmd); } rj_status_t rj_vm_execute_as(rj_vm_t *vm, uint32_t process_id, rj_vm_cmd_t *cmd) { - if (!vm || !cmd || !vm->vm || !vm->vm->driver()) + if (!vm || !cmd || !cmd->buf || !vm->vm || !vm->vm->driver()) return ROCJITSU_STATUS_INVALID_ARGUMENT; return execute_impl(vm->vm->driver(), process_id, cmd); } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h index 090bb7d112a3..fbebfd3d8d5c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/soc.h @@ -99,17 +99,17 @@ class SoC : public simdojo::CompositeComponent { /// @returns Const reference to the vector of XCD pointers. const std::vector &xcds() const { return xcds_; } - /// @brief MES-like round-robin queue assignment across XCD command processors. + /// @brief MES-like queue assignment across XCD command processors. /// /// @details On real MI300X hardware, the MES firmware distributes HW queues - /// across XCDs. This method emulates that behavior with round-robin assignment. - /// Each call returns the next XCD's CP in rotation. + /// across XCDs. Use the process-local queue ordinal so equivalent queues from + /// independent processes compete for the same XCD resources. /// - /// @returns Pointer to the next CommandProcessor in rotation, or nullptr if no XCDs. - amdgpu::CommandProcessor *assign_queue_cp() { + /// @returns Pointer to the selected CommandProcessor, or nullptr if no XCDs. + amdgpu::CommandProcessor *assign_queue_cp(uint32_t queue_ordinal) { if (xcds_.empty()) return nullptr; - uint32_t idx = next_xcd_assignment_++ % static_cast(xcds_.size()); + uint32_t idx = queue_ordinal % static_cast(xcds_.size()); return xcds_[idx]->command_processor(); } @@ -186,7 +186,6 @@ class SoC : public simdojo::CompositeComponent { private: static inline std::atomic next_gpu_id_{0}; uint32_t gpu_id_ = next_gpu_id_++; - std::atomic next_xcd_assignment_{0}; rj_code_arch_t arch_ = ROCJITSU_CODE_ARCH_INVALID; simdojo::ExecMode exec_mode_ = simdojo::ExecMode::FUNCTIONAL; std::vector xcds_; diff --git a/emulation/rocjitsu/lib/simdojo/include/simdojo/components/sparse_memory.h b/emulation/rocjitsu/lib/simdojo/include/simdojo/components/sparse_memory.h index 4396797b7911..61b9cbc77a89 100644 --- a/emulation/rocjitsu/lib/simdojo/include/simdojo/components/sparse_memory.h +++ b/emulation/rocjitsu/lib/simdojo/include/simdojo/components/sparse_memory.h @@ -187,6 +187,15 @@ class SparseMemory : public Component { return count; } + /// @brief Return whether the page containing @p addr has sparse backing. + /// @details Pages are keyed by their aligned byte address, the same key + /// get_page_locked() and read_sparse_chunk() use -- not by page number. + bool has_page(uint64_t addr) const { + const auto &stripe = page_stripes_[stripe_index(addr)]; + std::shared_lock lock(stripe.mutex); + return stripe.pages.contains(addr & ~PAGE_MASK); + } + private: static constexpr size_t NUM_PAGE_STRIPES = 1024; diff --git a/emulation/rocjitsu/lib/simdojo/include/simdojo/components/vector_reg.h b/emulation/rocjitsu/lib/simdojo/include/simdojo/components/vector_reg.h index 4d0dec901f29..20b386be39bb 100644 --- a/emulation/rocjitsu/lib/simdojo/include/simdojo/components/vector_reg.h +++ b/emulation/rocjitsu/lib/simdojo/include/simdojo/components/vector_reg.h @@ -12,6 +12,7 @@ #include "util/simd.h" #include +#include #include #include #include @@ -39,8 +40,17 @@ template class VectorReg { VectorReg() = default; VectorReg(Storage data) : data_(std::move(data)) {} - VecElem operator[](size_t idx) const { return data_[idx]; } - VecElem &operator[](size_t idx) { return data_[idx]; } + // Lane indices come from wave-size-dependent loops, and a wave32 register is + // exactly 32 lanes wide: a loop that assumes 64 reads its neighbour rather + // than failing. Catch that in debug builds; release keeps the bare index. + VecElem operator[](size_t idx) const { + assert(idx < NUM_ELEMS && "VectorReg lane index out of range"); + return data_[idx]; + } + VecElem &operator[](size_t idx) { + assert(idx < NUM_ELEMS && "VectorReg lane index out of range"); + return data_[idx]; + } /// SIMD load of `native` from W contiguous lanes starting at `lane_base`. /// The storage pointer never escapes the object. T is a 32-bit lane type. diff --git a/emulation/rocjitsu/lib/simdojo/include/simdojo/sim/simulation.h b/emulation/rocjitsu/lib/simdojo/include/simdojo/sim/simulation.h index a8e20173dc26..112e3fad5f57 100644 --- a/emulation/rocjitsu/lib/simdojo/include/simdojo/sim/simulation.h +++ b/emulation/rocjitsu/lib/simdojo/include/simdojo/sim/simulation.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -357,11 +358,32 @@ class SimulationEngine { /// @brief Set up partition contexts, async queues, and engine pointers. void setup_partitions(); + /// @brief Wake an idle single-threaded worker so it re-checks its exit and event state. + /// + /// @details No-op outside single-threaded mode, or once the partition is gone. + /// The caller must already hold @ref contexts_mutex_ (shared or exclusive). + /// @param pid The partition to wake. + void wake_partition_locked(PartitionID pid); + + /// @brief Wake an idle single-threaded worker, guarding against concurrent teardown. + /// + /// @details Takes a shared lock on @ref contexts_mutex_ so the context cannot be + /// destroyed by shutdown() between the bounds check and the notify. + /// @param pid The partition to wake. + void wake_partition(PartitionID pid); + Topology topology_; ///< The simulation topology. Config config_; ///< Engine configuration. /// @brief Reusable event for the max-ticks exit sentinel. /// @details Scheduled at config_.max_ticks during init. When processed, triggers sim exit. Event max_ticks_event_{nullptr, EventType::SIM_EXIT}; + /// @brief Guards destruction of contexts_ and async_queues_ against foreign threads. + /// + /// @details The wake and async-scheduling paths run on threads the engine does not + /// own (the host thread calling request_exit(), the doorbell monitor releasing a + /// primary) and can overlap shutdown() clearing these vectors. Those readers take a + /// shared lock; shutdown() takes it exclusively around the clear. + std::shared_mutex contexts_mutex_; std::vector> contexts_; ///< Per-partition state (one per thread). std::vector workers_; ///< Worker threads (multi-threaded mode). diff --git a/emulation/rocjitsu/lib/simdojo/src/simulation.cpp b/emulation/rocjitsu/lib/simdojo/src/simulation.cpp index 0056ec21d5e8..11523149c24d 100644 --- a/emulation/rocjitsu/lib/simdojo/src/simulation.cpp +++ b/emulation/rocjitsu/lib/simdojo/src/simulation.cpp @@ -66,19 +66,22 @@ void SimulationEngine::shutdown() { // In single-threaded mode, wake idle CV. In multi-threaded mode, // threads will see done_ after their current barrier epoch completes. - if (config_.num_threads == 1 && !contexts_.empty()) { - auto &ctx = *contexts_[0]; - ctx.idle_wakeup_.store(true, std::memory_order_release); - ctx.idle_wakeup_.notify_one(); - } + wake_partition(0); workers_.clear(); barrier_.reset(); shutdown_components(); running_ = false; - contexts_.clear(); - async_queues_.clear(); + { + // Exclusive: a foreign thread may be mid-wake or mid-async-schedule on these + // vectors. Workers are already joined above, so nothing we join can be waiting + // on this lock. Taken after shutdown_components() so component teardown, which + // may still schedule, is not blocked. + std::unique_lock lock(contexts_mutex_); + contexts_.clear(); + async_queues_.clear(); + } created_ = false; } @@ -149,6 +152,9 @@ ExitStatus SimulationEngine::run() { } running_ = false; + // Copy under the lock: a foreign thread can still be inside request_exit() + // assigning exit_status_ as run() unwinds, and the copy reads its message string. + std::lock_guard lock(exit_mutex_); return exit_status_; } @@ -393,11 +399,8 @@ void SimulationEngine::primary_release() { [[maybe_unused]] uint32_t prev = active_primaries_.fetch_sub(1, std::memory_order_release); assert(prev > 0 && "primary_release called without matching register_as_primary or retain"); // Wake idle engine so it can check termination (e.g., doorbell monitor releasing primary). - if (prev == 1 && config_.num_threads == 1 && !contexts_.empty()) { - auto &ctx = *contexts_[0]; - ctx.idle_wakeup_.store(true, std::memory_order_release); - ctx.idle_wakeup_.notify_one(); - } + if (prev == 1) + wake_partition(0); } void SimulationEngine::primary_retain() { @@ -461,6 +464,19 @@ bool SimulationEngine::check_termination(Tick lbts) { return false; } +void SimulationEngine::wake_partition_locked(PartitionID pid) { + if (config_.num_threads != 1 || pid >= contexts_.size()) + return; + PartitionContext &ctx = *contexts_[pid]; + ctx.idle_wakeup_.store(true, std::memory_order_release); + ctx.idle_wakeup_.notify_one(); +} + +void SimulationEngine::wake_partition(PartitionID pid) { + std::shared_lock lock(contexts_mutex_); + wake_partition_locked(pid); +} + void SimulationEngine::request_exit(std::string reason, int code) { Tick tick = current_time_.load(std::memory_order_acquire); { @@ -475,12 +491,9 @@ void SimulationEngine::request_exit(std::string reason, int code) { done_.store(true, std::memory_order_release); } - // In single-threaded mode, wake the idle wait. - if (config_.num_threads == 1 && !contexts_.empty()) { - auto &ctx = *contexts_[0]; - ctx.idle_wakeup_.store(true, std::memory_order_release); - ctx.idle_wakeup_.notify_one(); - } + // In single-threaded mode, wake the idle wait. Guarded: the engine thread may be + // inside shutdown() destroying the contexts while the host thread requests exit. + wake_partition(0); // In multi-threaded mode, done_ is checked after each barrier epoch. // No explicit wake needed since threads will see it at the next barrier. } @@ -490,20 +503,28 @@ void SimulationEngine::schedule_event_async(Event *event, Tick timestamp, Component *target = event->target(); assert(target != nullptr && "schedule_event_async: event has no target component"); PartitionID pid = target->partition_id(); - assert(pid < async_queues_.size() && "schedule_event_async: target partition ID out of range"); + + // Shared: keeps async_queues_ and contexts_ alive for the duration. Producers do + // not exclude one another, so this stays off the critical path; only shutdown() + // blocks here. Held across the wake so the context cannot be freed under us. + std::shared_lock lock(contexts_mutex_); + if (pid >= async_queues_.size()) { + // shutdown() has cleared the queues, so the event has nowhere left to go. A + // non-empty queue vector here instead means an out-of-range partition ID, which + // is a caller bug. (Checked against async_queues_ rather than created_: that + // flag is written outside the lock, so reading it here would itself race.) + assert(async_queues_.empty() && "schedule_event_async: target partition ID out of range"); + return; + } auto &aq = *async_queues_[pid]; { - std::lock_guard lock(aq.mutex); + std::lock_guard qlock(aq.mutex); aq.events.push_back(EventQueueEntry{timestamp, 0, event, std::move(message)}); aq.pending.store(true, std::memory_order_release); } // Wake the target partition so idle workers pick up the new event. - if (config_.num_threads == 1 && pid < contexts_.size()) { - PartitionContext &pctx = *contexts_[pid]; - pctx.idle_wakeup_.store(true, std::memory_order_release); - pctx.idle_wakeup_.notify_one(); - } + wake_partition_locked(pid); // In multi-threaded mode, async events are drained at each barrier epoch. } diff --git a/emulation/rocjitsu/schemas/checkpoint.fbs b/emulation/rocjitsu/schemas/checkpoint.fbs index 5667bc824659..32f9d3a0d2e1 100644 --- a/emulation/rocjitsu/schemas/checkpoint.fbs +++ b/emulation/rocjitsu/schemas/checkpoint.fbs @@ -22,6 +22,24 @@ table WavefrontState { vgprs: [ubyte]; // Vector register file (raw bytes). mode: uint32; // MODE register. wave_sched_mode: uint32; // WAVE_SCHED_MODE register. + // Trap-temporary registers (TTMP0-15). These are a separate register file, + // not the tail of `sgprs`: the ISA decoder routes scalar selectors 108..123 + // here. Appended last so older checkpoints still load: the accessor returns + // null, and restore then migrates the values out of `sgprs[108..123]`, which + // is where the same selectors were stored before the split. Zeroing them + // instead would not be safe -- RDNA4 and GFX1250 seed TTMP6/7/9 with + // workgroup ids at dispatch, so a wave that was never in a trap handler still + // holds meaningful TTMPs there. + ttmps: [uint32]; + // Workgroup coordinate (x, y, z) this wave was dispatched with. Not derivable + // from `wg_id`: recovering the coordinate from the flat id needs the grid + // dimensions, which live in the dispatch packet and are not part of a + // checkpoint. Trap entry publishes these three values in TTMP8/9/10 and the + // CWSR codec serializes them, so a restored wave that lost them reports the + // wrong workgroup identity to the trap handler and cannot be matched back to + // its CWSR record. Appended last so older checkpoints still load; see + // restore_checkpoint() for the fallback applied when the accessor is null. + wg_coord: [uint32]; } /// Serialized state of a compute unit. diff --git a/emulation/rocjitsu/tests/CMakeLists.txt b/emulation/rocjitsu/tests/CMakeLists.txt index 9c45b1092cd6..875c2f2acdfe 100644 --- a/emulation/rocjitsu/tests/CMakeLists.txt +++ b/emulation/rocjitsu/tests/CMakeLists.txt @@ -460,6 +460,7 @@ add_executable( scalar_scc_test.cpp cdna3_predicate_mask_test.cpp scoped_temp_test.cpp + wave_debug_test.cpp decode_execute_benchmark.cpp util_result_test.cpp util_unique_handle_test.cpp @@ -1420,6 +1421,8 @@ set(_rj_interposer_dup_tests SerializedReopenUnderContentionStaysRoutable FcntlDupfdReplacesStaleDrmTracking NonDrmDuplicatesClearStaleDrmTracking + VforkChildCloseKeepsParentKfdRoutable + ProcMapsNamesRemoteKfdMarker ) # TSan models concurrent close/dup on one descriptor as an application-level fd # race even though the interposer deliberately serializes the kernel operation. @@ -2488,6 +2491,7 @@ if(RJ_ENABLE_HIP_TESTS) DaemonTest.InterposerDupSerializedReopenUnderContentionRemote DaemonTest.InterposerDupKeepsRoutingAfterPrimaryCloseRemote DaemonTest.InterposerDup2OverPrimaryInvalidatesRemote + DaemonTest.InterposerProcMapsNamesRemoteKfdMarker ) foreach(TC IN LISTS RJ_DAEMON_TESTS) rj_add_test( @@ -2717,3 +2721,180 @@ if(RJ_ENABLE_HIP_TESTS AND RJ_HIP_RUNTIME_SUPPORTS_GFX950) "bin/hip_cvt_narrow_test" ) endif() + +# --- rocgdb wave-debugging smoke test (requires rocgdb + hipcc + mirage) --- +# Drives real ROCgdb through `mirage run` to set a GPU kernel breakpoint, stop, +# inspect wave registers, and continue to a correct result (see +# tests/rocgdb/debug_kernel.sh). Gated on the debugger and HIP compiler being +# present; the harness itself skips (printing "SKIP:") if mirage is not found. +find_program( + ROCGDB_EXECUTABLE + NAMES rocgdb + HINTS "${ROCM_PATH}" + PATH_SUFFIXES bin +) +find_program( + HIPCC_EXECUTABLE + NAMES hipcc + HINTS "${ROCM_PATH}" + PATH_SUFFIXES bin +) +# NO_DEFAULT_PATH: only an in-tree Mirage qualifies. An unrelated one installed +# on PATH would be a different build than the librocjitsu.so staged below, and +# the mismatch surfaces as an opaque "enable_debug failed (STATUS_ERROR)" rather +# than as a version error. +# +# A fresh cache entry name (not MIRAGE_EXECUTABLE) is deliberate: find_program is +# a no-op when its cache variable is already set, so any build tree configured +# while this used HINTS -- which does not suppress the default PATH search -- +# would keep an out-of-tree hit forever and NO_DEFAULT_PATH would never apply to +# the very trees it was added for. +# +# build/manylinux/bin is where emulation/mirage/scripts/mirage.sh installs, so it +# belongs beside the two cargo target dirs; PATH_SUFFIXES covers it without +# reopening the default search. +find_program( + RJ_MIRAGE_EXECUTABLE + NAMES mirage + PATHS + "${CMAKE_SOURCE_DIR}/../mirage/target/release" + "${CMAKE_SOURCE_DIR}/../mirage/target/debug" + "${CMAKE_SOURCE_DIR}/../mirage/build/manylinux" + PATH_SUFFIXES bin + NO_DEFAULT_PATH +) +set(MIRAGE_EXECUTABLE "${RJ_MIRAGE_EXECUTABLE}") +# Mirage is as much a prerequisite as rocgdb and hipcc: without it the harness +# has nothing to run the debuggee under. Registering the test anyway produced a +# test that could only skip, or -- worse -- one that ran a Mirage which then +# loaded whatever librocjitsu.so it happened to find, or none at all and exited +# 127 long before reaching ROCgdb. +# A Mirage binary older than Mirage's own sources is not usable here: this +# branch changes the ctl and rocjitsu_sys crates, and a prebuilt binary that +# predates them fails attachment with an opaque "enable_debug failed +# (STATUS_ERROR)". CMake deliberately does not drive cargo, so refuse to +# register rather than test a binary that does not match the tree, and say what +# to run. Configure-time only, so `cargo build` needs a re-run of cmake -- which +# the message states. +# +# No CONFIGURE_DEPENDS: it re-runs cmake when the *set* of matched files changes, +# never when an existing file's mtime does, which is the only thing this gate +# reads -- so it cannot fire for the case that matters and costs a recursive walk +# of the whole mirage tree on every build. +set(_rocgdb_mirage_stale FALSE) +if(MIRAGE_EXECUTABLE) + # mirage is a workspace whose root package is the `mirage` binary itself + # (src/main.rs, declared by the top-level Cargo.toml), so the per-crate + # patterns alone would miss the entry point most likely to change. + file( + GLOB_RECURSE _rocgdb_mirage_sources + "${CMAKE_SOURCE_DIR}/../mirage/*/src/*.rs" + "${CMAKE_SOURCE_DIR}/../mirage/*/Cargo.toml" + "${CMAKE_SOURCE_DIR}/../mirage/src/*.rs" + "${CMAKE_SOURCE_DIR}/../mirage/build.rs" + "${CMAKE_SOURCE_DIR}/../mirage/Cargo.toml" + "${CMAKE_SOURCE_DIR}/../mirage/Cargo.lock" + ) + # Phrased as "the binary is not newer than the source" rather than the + # reverse: CMake's IS_NEWER_THAN is also true when the two timestamps are + # *equal*, so testing the source directly calls a tie stale. Ties are the + # common case after a checkout, a container copy, or a CI cache restore, and + # calling them stale silently deregisters the test with a message telling the + # developer to run a build they already ran. + foreach(_src IN LISTS _rocgdb_mirage_sources) + if(NOT "${MIRAGE_EXECUTABLE}" IS_NEWER_THAN "${_src}") + set(_rocgdb_mirage_stale TRUE) + break() + endif() + endforeach() +endif() + +if( + ROCGDB_EXECUTABLE + AND HIPCC_EXECUTABLE + AND MIRAGE_EXECUTABLE + AND NOT _rocgdb_mirage_stale +) + # Stage the librocjitsu.so this build just produced into a stub ROCm root + # and point Mirage at it. $ROCM_HOME/lib is one of Mirage's documented + # search locations (emulation/mirage/rocjitsu/src/lib.rs kmd_search_dirs), + # and the search is additive, so a stub root cannot shadow anything else. + set(_rocgdb_rocm_home ${CMAKE_CURRENT_BINARY_DIR}/rocgdb_rocm_home) + # Stage Mirage next to the library as /bin/mirage + /lib. + # kmd_search_dirs (emulation/mirage/rocjitsu/src/lib.rs) probes + # /../..{,/..}/rocjitsu/build first and only then /../lib, + # with $ROCM_HOME/lib after both. Run in place from + # emulation/mirage/target/debug, the third of those probes resolves to + # emulation/rocjitsu/build -- the developer's own tree -- so ROCM_HOME never + # got a look in. Running the staged copy puts none of the rocjitsu/build + # probes on a real directory, and /../lib is this build's staged + # librocjitsu.so. + add_custom_command( + OUTPUT + ${_rocgdb_rocm_home}/lib/librocjitsu.so + ${_rocgdb_rocm_home}/bin/mirage + COMMAND ${CMAKE_COMMAND} -E make_directory ${_rocgdb_rocm_home}/lib + COMMAND ${CMAKE_COMMAND} -E make_directory ${_rocgdb_rocm_home}/bin + COMMAND + ${CMAKE_COMMAND} -E copy_if_different $ + ${_rocgdb_rocm_home}/lib/librocjitsu.so + COMMAND + ${CMAKE_COMMAND} -E copy_if_different ${MIRAGE_EXECUTABLE} + ${_rocgdb_rocm_home}/bin/mirage + # copy_if_different leaves the destination's mtime alone when the bytes + # already match, so without this the outputs stay older than their inputs + # and the generator re-issues all four commands -- a byte-compare of a + # 69 MB binary and the shared library -- on every incremental build. + COMMAND + ${CMAKE_COMMAND} -E touch ${_rocgdb_rocm_home}/lib/librocjitsu.so + ${_rocgdb_rocm_home}/bin/mirage + DEPENDS rocjitsu_shared ${MIRAGE_EXECUTABLE} + COMMENT + "Staging mirage + librocjitsu.so for the rocgdb debug smoke test" + VERBATIM + ) + add_custom_target( + rocgdb_demo_rocm_home + ALL + DEPENDS + ${_rocgdb_rocm_home}/lib/librocjitsu.so + ${_rocgdb_rocm_home}/bin/mirage + ) + + rj_add_test( + NAME "RocgdbDebug.KernelBreakpoint" + COMMAND bash "${CMAKE_CURRENT_SOURCE_DIR}/rocgdb/debug_kernel.sh" + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + TIMEOUT 300 + ENVIRONMENT + "MIRAGE_BIN=${_rocgdb_rocm_home}/bin/mirage" + "ROCM_HOME=${_rocgdb_rocm_home}" + SKIP_REGULAR_EXPRESSION "SKIP:" + ) + message( + STATUS + "rocgdb debug smoke test enabled (found ${ROCGDB_EXECUTABLE})" + ) +else() + # One message naming every unmet reason. Reporting only staleness when rocgdb + # is also missing sends the developer to `cargo build`, after which the test + # still does not register and nothing new is printed to say why. + set(_rocgdb_missing "") + if(NOT ROCGDB_EXECUTABLE) + list(APPEND _rocgdb_missing "rocgdb") + endif() + if(NOT HIPCC_EXECUTABLE) + list(APPEND _rocgdb_missing "hipcc") + endif() + if(NOT MIRAGE_EXECUTABLE) + list(APPEND _rocgdb_missing "mirage") + endif() + if(_rocgdb_mirage_stale) + list( + APPEND _rocgdb_missing + "a mirage newer than its sources (run `cargo build` in emulation/mirage, then re-run cmake)" + ) + endif() + list(JOIN _rocgdb_missing ", " _rocgdb_missing) + message(STATUS "rocgdb debug smoke test disabled (need ${_rocgdb_missing})") +endif() diff --git a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp index eb56357cfee3..8607c9504000 100644 --- a/emulation/rocjitsu/tests/amdgpu_vm_test.cpp +++ b/emulation/rocjitsu/tests/amdgpu_vm_test.cpp @@ -79,6 +79,7 @@ namespace { // SOPP encoding: bits[31:23] = 0x17F (SOPP prefix), bits[22:16] = op. constexpr uint32_t SOPP_S_NOP = 0xBF800000; constexpr uint32_t SOPP_S_ENDPGM = 0xBF810000; +constexpr uint32_t SOPP_S_TRAP_1 = 0xBF920001; using namespace rocjitsu; @@ -1612,6 +1613,59 @@ TEST_P(IsaTest, DispatchAndCapacity) { EXPECT_EQ(f.cp()->dispatched_count(), 1u); } +TEST(CommandProcessorTest, DebugSuspendedEmptyQueueDefersNewDispatchUntilResume) { + VmFixture f("cdna4", 1, 2); + const uint32_t code[] = {SOPP_S_ENDPGM}; + uint64_t kernel_object = f.write_kernel(0x1000, code, sizeof(code)); + test::AqlQueue queue(f.mem(), f.cp()); + + // Queue suspension is persistent HQD state. It must block packets submitted + // after an empty queue was suspended, not just pause waves already resident. + f.cp()->set_queue_debug_suspended(/*queue_id=*/1, /*process_id=*/0, true); + queue.dispatch(kernel_object, 64); + (void)f.engine->step(); + EXPECT_EQ(f.cp()->dispatched_count(), 0u); + EXPECT_EQ(f.mem()->read64(test::AqlQueue::DEFAULT_READ_PTR_ADDR), 0u); + + f.cp()->set_queue_debug_suspended(/*queue_id=*/1, /*process_id=*/0, false); + f.engine->run(); + EXPECT_EQ(f.cp()->dispatched_count(), 1u); + EXPECT_EQ(f.mem()->read64(test::AqlQueue::DEFAULT_READ_PTR_ADDR), 1u); +} + +TEST(CommandProcessorTest, DebugResumeWithOnlyResidentWorkDoesNotRescanQueue) { + VmFixture f("cdna4", 1, 2); + std::vector code(amdgpu::ComputeUnitCore::kFunctionalQuantum * 2, SOPP_S_NOP); + code.push_back(SOPP_S_ENDPGM); + uint64_t kernel_object = f.write_kernel(0x1000, code.data(), code.size() * sizeof(uint32_t)); + test::AqlQueue queue(f.mem(), f.cp()); + + queue.dispatch(kernel_object, 64); + ASSERT_TRUE(f.engine->step()); + ASSERT_EQ(f.cp()->dispatched_count(), 1u); + ASSERT_TRUE(f.cu()->has_active_wfs()); + auto *wave = f.cu()->wf(0); + ASSERT_NE(wave, nullptr); + + // Model a command-processor event that was already queued when KFD froze the + // resident wave. Consuming that event while no packet is unread must not + // manufacture deferred work and create a resume/event chain. + f.cp()->set_queue_debug_suspended(/*queue_id=*/1, /*process_id=*/0, true); + wave->set_debug_suspended(true); + f.engine->schedule_event_now(f.cp()->doorbell_event()); + ASSERT_TRUE(f.engine->step()); + const uint64_t passes_before_resume = f.cp()->doorbell_handle_count_for_test(); + + wave->set_debug_suspended(false); + f.cu()->schedule_work_async(); + f.cp()->set_queue_debug_suspended(/*queue_id=*/1, /*process_id=*/0, false); + ASSERT_TRUE(f.engine->step()); + + EXPECT_EQ(f.cp()->doorbell_handle_count_for_test(), passes_before_resume); + f.engine->run(); + EXPECT_FALSE(f.cu()->has_active_wfs()); +} + TEST_P(IsaTest, DispatchWfReturnsNullWhenSlotsExhausted) { // dispatch_wf() promises nullptr (not an out-of-bounds slot) when the CU is full. // The CP relies on can_accept_workgroup() gating, but the API contract must hold @@ -1626,6 +1680,84 @@ TEST_P(IsaTest, DispatchWfReturnsNullWhenSlotsExhausted) { EXPECT_EQ(cu->dispatch_wf(0, 0x1040, 104, 256), nullptr); } +TEST(CommandProcessorTest, DispatchToQuiescedDebugHaltedCuReactivatesEventLoop) { + VmFixture f("cdna4", 2, 2); + test::AqlQueue queue(f.mem(), f.cp()); + + const uint32_t warmup[] = {SOPP_S_ENDPGM}; + uint64_t warmup_ko = f.write_kernel(0x1000, warmup, sizeof(warmup)); + queue.dispatch(warmup_ko, 64); + for (uint32_t i = 0; i < 100 && f.cp()->dispatched_count() != 1; ++i) + ASSERT_TRUE(f.engine->step()); + ASSERT_EQ(f.cp()->dispatched_count(), 1u); + + constexpr uint64_t kTrapPc = 0x8000; + constexpr uint64_t kTrapHandlerPc = 0x9000; + f.mem()->write32(kTrapPc, SOPP_S_TRAP_1); + const uint32_t trap_handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEF800FFu, 0x00002000u, // s_mov_b32 ttmp12, STATUS.HALT + 0xBF900001u, // s_sendmsg sendmsg(MSG_INTERRUPT) + 0xB978F802u, // s_setreg_b32 hwreg(HW_REG_STATUS), ttmp12 + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(trap_handler); ++i) + f.mem()->write32(kTrapHandlerPc + i * 4, trap_handler[i]); + f.cu(0)->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerPc, 0, true}; + }); + f.cu(0)->set_sendmsg_handler([](amdgpu::Wavefront &, uint32_t message) { return message == 1; }); + auto *stopped = f.cu(0)->dispatch_wf(0, kTrapPc, 104, 256); + ASSERT_NE(stopped, nullptr); + f.cu(0)->schedule_work(); + for (uint32_t i = 0; i < 100 && !stopped->debug_halted(); ++i) + ASSERT_TRUE(f.engine->step()); + ASSERT_TRUE(stopped->debug_halted()); + ASSERT_TRUE(f.cu(0)->is_idle()); + + std::vector long_running(amdgpu::ComputeUnitCore::kFunctionalQuantum + 1, SOPP_S_NOP); + long_running.push_back(SOPP_S_ENDPGM); + uint64_t long_ko = + f.write_kernel(0x10000, long_running.data(), long_running.size() * sizeof(uint32_t)); + uint64_t followup_ko = f.write_kernel(0x20000, warmup, sizeof(warmup)); + + hsa_kernel_dispatch_packet_t first{}; + first.header = HSA_PACKET_TYPE_KERNEL_DISPATCH; + first.setup = 1; + first.workgroup_size_x = 64; + first.workgroup_size_y = 1; + first.workgroup_size_z = 1; + first.grid_size_x = 64; + first.grid_size_y = 1; + first.grid_size_z = 1; + first.kernel_object = long_ko; + queue.submit(first); + + hsa_kernel_dispatch_packet_t followup = first; + followup.header |= 1 << HSA_PACKET_HEADER_BARRIER; + followup.kernel_object = followup_ko; + queue.submit(followup); + + amdgpu::Wavefront *followup_wf = nullptr; + for (uint32_t i = 0; i < 100 && f.engine->step(); ++i) { + for (uint32_t slot = 0; slot < f.cu(0)->num_wf_slots(); ++slot) { + auto *wf = f.cu(0)->wf(slot); + if (wf != stopped && wf->dispatch_id() == 3) { + followup_wf = wf; + break; + } + } + if (followup_wf && followup_wf->is_halted()) + break; + } + + ASSERT_NE(followup_wf, nullptr); + EXPECT_TRUE(followup_wf->is_halted()); + EXPECT_TRUE(stopped->debug_halted()); + EXPECT_EQ(f.cp()->dispatched_count(), 3u); +} + TEST_P(IsaTest, VendorSpecificExtKernelDispatch) { VmFixture f(arch(), 1, 8); auto *snap = f.capture_halts(); @@ -2010,9 +2142,9 @@ TEST(ClusterDispatchTest, Rdna4ExtendedDispatchKeepsOrdinaryTtmpWorkgroupIds) { const uint32_t workgroup_x = workgroup_id % 2; const uint32_t workgroup_y = (workgroup_id / 2) % 2; const uint32_t workgroup_z = workgroup_id / 4; - EXPECT_EQ(wf.sgpr(114), 0u); - EXPECT_EQ(wf.sgpr(115), (workgroup_z << 16) | workgroup_y); - EXPECT_EQ(wf.sgpr(117), workgroup_x); + EXPECT_EQ(wf.ttmp(6), 0u); + EXPECT_EQ(wf.ttmp(7), (workgroup_z << 16) | workgroup_y); + EXPECT_EQ(wf.ttmp(9), workgroup_x); } for (bool was_seen : seen) EXPECT_TRUE(was_seen); diff --git a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp index 2fdb186e9a2f..89ca17069255 100644 --- a/emulation/rocjitsu/tests/cdna5_cluster_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_cluster_test.cpp @@ -1534,7 +1534,7 @@ TEST(Gfx1250SimulationTest, DynamicClusterLaunchStateMatchesCompilerAbiWithAlign }; std::vector states; for (const auto &wf : sim.snapshot->snapshots()) - states.push_back({wf.wg_id, wf.sgpr(114), wf.sgpr(115), wf.sgpr(117), wf.sgpr(2), wf.sgpr(3), + states.push_back({wf.wg_id, wf.ttmp(6), wf.ttmp(7), wf.ttmp(9), wf.sgpr(2), wf.sgpr(3), wf.sgpr(6), wf.sgpr(10), wf.sgpr(13)}); std::sort(states.begin(), states.end(), [](const LaunchState &lhs, const LaunchState &rhs) { return lhs.workgroup_id < rhs.workgroup_id; diff --git a/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp b/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp index c9abd168147f..4b8e8f7c296e 100644 --- a/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp +++ b/emulation/rocjitsu/tests/cdna5_dispatch_memory_test.cpp @@ -331,10 +331,10 @@ TEST(Gfx1250SimulationTest, TtmpWorkgroupIdsUseGridCoordinatesFor2DDispatch) { const auto *target = sim.snapshot->by_wg_id(4); ASSERT_NE(target, nullptr); - // TTMP9 (s117) holds grid_wg_id_x; TTMP7 (s115) packs wg_id_y/z. - EXPECT_EQ(target->sgpr(117), 1u); - EXPECT_EQ(target->sgpr(115), 1u); - EXPECT_NE(target->sgpr(116) & (1u << 30), 0u); + // TTMP9 holds grid_wg_id_x; TTMP7 packs wg_id_y/z; TTMP8 bit 30 is grid_yz_valid. + EXPECT_EQ(target->ttmp(9), 1u); + EXPECT_EQ(target->ttmp(7), 1u); + EXPECT_NE(target->ttmp(8) & (1u << 30), 0u); } TEST(Gfx1250SimulationTest, Ttmp8EncodesWaveIdWithinWorkgroup) { @@ -349,7 +349,7 @@ TEST(Gfx1250SimulationTest, Ttmp8EncodesWaveIdWithinWorkgroup) { ASSERT_EQ(sim.snapshot->snapshots().size(), 2u); std::vector ttmp8_values; for (const auto &wf : sim.snapshot->snapshots()) - ttmp8_values.push_back(wf.sgpr(116)); + ttmp8_values.push_back(wf.ttmp(8)); std::sort(ttmp8_values.begin(), ttmp8_values.end()); EXPECT_EQ(ttmp8_values, (std::vector{0, 1u << 25})); } @@ -369,7 +369,7 @@ TEST(Gfx1250SimulationTest, Ttmp8EncodesQueuePacketId) { for (const auto &wf : sim.snapshot->snapshots()) { ASSERT_GE(wf.dispatch_id, 1u); ASSERT_LE(wf.dispatch_id, 2u); - queue_packet_ids[wf.dispatch_id - 1] = wf.sgpr(116) & 0x1FFFFFFu; + queue_packet_ids[wf.dispatch_id - 1] = wf.ttmp(8) & 0x1FFFFFFu; } EXPECT_EQ(queue_packet_ids, (std::array{0, 1})); } diff --git a/emulation/rocjitsu/tests/config_test.cpp b/emulation/rocjitsu/tests/config_test.cpp index 21d29d2ba9ef..bd8b33bf11c4 100644 --- a/emulation/rocjitsu/tests/config_test.cpp +++ b/emulation/rocjitsu/tests/config_test.cpp @@ -64,6 +64,9 @@ TEST(ConfigLoaderTest, LoadCdna4Config) { EXPECT_EQ(xcd->num_shader_engines(), 4u); EXPECT_EQ(xcd->shader_engine(0)->num_compute_units(), 9u); EXPECT_EQ(kmd::drm_cu_active_number(loaded.device.simd_count, loaded.device.simd_per_cu), 256u); + EXPECT_EQ(soc->assign_queue_cp(0), soc->xcd(0)->command_processor()); + EXPECT_EQ(soc->assign_queue_cp(1), soc->xcd(1)->command_processor()); + EXPECT_EQ(soc->assign_queue_cp(soc->num_xcds()), soc->xcd(0)->command_processor()); } TEST(ConfigLoaderTest, LoadRdnaKmdConfigs) { @@ -1214,6 +1217,134 @@ TEST(CheckpointTest, SaveAndRestoreHwregState) { EXPECT_TRUE(restored_wf->fp16_ovfl()); } +// The checkpoint record carries the architectural registers and the TTMPs but +// none of the trap/debug state around them, so a wave captured mid-handler +// would restore without the EXEC restore or the privileged STATUS write that +// leaving the handler performs. Refusing beats resuming the application with +// the trap handler's state installed. +TEST(CheckpointTest, RefusesToSaveTrappedOrDebuggerStoppedWaves) { + const char *json = R"({"max_ticks":10000,"num_threads":1, + "vm":{"arch":"cdna5"}, + "topology":{ + "root":{ + "name":"soc","type":"soc", + "children":[ + {"name":"vram","type":"gpu_memory"}, + {"name":"xcd0","type":"xcd","children":[ + {"name":"l2","type":"l2_cache"}, + {"name":"cp","type":"command_processor"}, + {"name":"se0","type":"shader_engine","children":[ + {"name":"cu[0:1]","type":"compute_unit","config":[ + {"key":"num_wf_slots","value":"1"}, + {"key":"sgprs_per_wf","value":"104"}, + {"key":"vgprs_per_wf","value":"256"}, + {"key":"lds_size_kb","value":"64"} + ]} + ]} + ]} + ] + }, + "links":[ + {"src":"xcd0.cp.req_0","dst":"xcd0.se0.cu0.cpl","latency":1,"weight":2}, + {"src":"xcd0.se0.cu0.req","dst":"xcd0.l2.cpl_0","latency":1,"weight":10} + ] + } + })"; + + auto loaded = config::load_config_from_string(json, rocjitsu::kEmbeddedSchema); + auto *cu = loaded.soc()->xcd(0)->shader_engine(0)->compute_unit(0); + ASSERT_NE(cu, nullptr); + auto *wf = cu->dispatch_wf(0, 0, cu->config().sgprs_per_wf, cu->config().vgprs_per_wf); + ASSERT_NE(wf, nullptr); + + test::ScopedTempFile checkpoint("rocjitsu-checkpoint-"); + // A plain running wave still checkpoints. + EXPECT_NO_THROW( + config::save_checkpoint(checkpoint.path(), *loaded.soc(), 1, loaded.engine_config)); + + wf->set_in_trap_handler(true); + EXPECT_THROW(config::save_checkpoint(checkpoint.path(), *loaded.soc(), 2, loaded.engine_config), + std::runtime_error); + wf->set_in_trap_handler(false); + + wf->set_debug_halted(true); + EXPECT_THROW(config::save_checkpoint(checkpoint.path(), *loaded.soc(), 3, loaded.engine_config), + std::runtime_error); + wf->set_debug_halted(false); + + wf->set_debug_suspended(true); + EXPECT_THROW(config::save_checkpoint(checkpoint.path(), *loaded.soc(), 4, loaded.engine_config), + std::runtime_error); + wf->set_debug_suspended(false); + + // The runtime's own pause is not a debugger stop. A queue throttled to + // queue_percentage 0 carries none of the trap or debugger state the refusals + // above exist to protect, so it must stay checkpointable -- this is the one + // assertion that tells debug_stopped() apart from debug_paused(). + wf->set_runtime_suspended(true); + EXPECT_NO_THROW( + config::save_checkpoint(checkpoint.path(), *loaded.soc(), 5, loaded.engine_config)); + wf->set_runtime_suspended(false); +} + +// wg_coord is dispatch identity, and the flat wg_id cannot stand in for it: the +// grid dimensions needed to unflatten one into the other live in the dispatch +// packet, which is not part of a checkpoint. A restored wave that lost the +// coordinate publishes the wrong workgroup in TTMP8/9/10 at trap entry and can +// no longer be matched to its own CWSR record. +TEST(CheckpointTest, RoundTripsWorkgroupCoordinates) { + const char *json = R"({"max_ticks":10000,"num_threads":1, + "vm":{"arch":"cdna3"}, + "topology":{ + "root":{ + "name":"soc","type":"soc", + "children":[ + {"name":"vram","type":"gpu_memory"}, + {"name":"xcd0","type":"xcd","children":[ + {"name":"l2","type":"l2_cache"}, + {"name":"cp","type":"command_processor"}, + {"name":"se0","type":"shader_engine","children":[ + {"name":"cu[0:1]","type":"compute_unit","config":[ + {"key":"num_wf_slots","value":"1"}, + {"key":"sgprs_per_wf","value":"104"}, + {"key":"vgprs_per_wf","value":"256"}, + {"key":"lds_size_kb","value":"64"} + ]} + ]} + ]} + ] + }, + "links":[ + {"src":"xcd0.cp.req_0","dst":"xcd0.se0.cu0.cpl","latency":1,"weight":2}, + {"src":"xcd0.se0.cu0.req","dst":"xcd0.l2.cpl_0","latency":1,"weight":10} + ] + } + })"; + + auto loaded = config::load_config_from_string(json, rocjitsu::kEmbeddedSchema); + auto *cu = loaded.soc()->xcd(0)->shader_engine(0)->compute_unit(0); + ASSERT_NE(cu, nullptr); + // A flat id that is not any of the coordinates, so restoring wg_id into them + // would not pass either. + auto *wf = cu->dispatch_wf(/*wg_id=*/9, /*pc=*/0x1000, cu->config().sgprs_per_wf, + cu->config().vgprs_per_wf); + ASSERT_NE(wf, nullptr); + wf->set_wg_coord(3, 5, 7); + + test::ScopedTempFile checkpoint("rocjitsu-wg-coord-checkpoint-"); + ASSERT_NO_THROW( + config::save_checkpoint(checkpoint.path(), *loaded.soc(), 1, loaded.engine_config)); + + auto restored = config::restore_checkpoint(checkpoint.path()); + auto *restored_cu = restored.soc()->xcd(0)->shader_engine(0)->compute_unit(0); + ASSERT_NE(restored_cu, nullptr); + ASSERT_EQ(restored_cu->num_wfs(), 1u); + const auto *restored_wf = restored_cu->wf(0); + ASSERT_NE(restored_wf, nullptr); + EXPECT_EQ(restored_wf->wg_id(), 9u); + EXPECT_EQ(restored_wf->wg_coord(), (std::array{3, 5, 7})); +} + TEST(CApiTest, CreateAndDestroyFromString) { const char *json = R"({"max_ticks":10000,"num_threads":1, "vm":{"arch":"cdna3"}, diff --git a/emulation/rocjitsu/tests/daemon_test.cpp b/emulation/rocjitsu/tests/daemon_test.cpp index 847930f61501..da33130f411d 100644 --- a/emulation/rocjitsu/tests/daemon_test.cpp +++ b/emulation/rocjitsu/tests/daemon_test.cpp @@ -482,6 +482,11 @@ TEST_F(DaemonTest, InterposerDup2OverPrimaryInvalidatesRemote) { EXPECT_EQ(r.exit_code, 0) << r.output; } +TEST_F(DaemonTest, InterposerProcMapsNamesRemoteKfdMarker) { + auto r = run_hip_test(interposer_dup_bin(), "InterposerDupTest.ProcMapsNamesRemoteKfdMarker"); + EXPECT_EQ(r.exit_code, 0) << r.output; +} + // --- RCCL collective tests (2-GPU daemon) --- class RcclDaemonTest : public ::testing::Test { diff --git a/emulation/rocjitsu/tests/decode_smoke_test.cpp b/emulation/rocjitsu/tests/decode_smoke_test.cpp index 65a469346e41..91155d30882a 100644 --- a/emulation/rocjitsu/tests/decode_smoke_test.cpp +++ b/emulation/rocjitsu/tests/decode_smoke_test.cpp @@ -1354,6 +1354,36 @@ TEST(FunctionalSchedulingTest, SleepVarYieldsBeforeQuantumExpires) { expect_sleep_yields_before_quantum_expires(ROCJITSU_CODE_ARCH_RDNA4, kSleepVar); } +TEST(FunctionalSchedulingTest, DebugActiveUsesFairQuantum) { + constexpr uint64_t kCodeAddress = 0x3000; + + amdgpu::GpuMemory gpu_mem("functional_debug_mem"); + amdgpu::L2Cache l2("functional_debug_l2"); + for (uint32_t i = 0; i <= amdgpu::ComputeUnitCore::kDebugFunctionalQuantum; ++i) + gpu_mem.write32(kCodeAddress + i * sizeof(uint32_t), S_NOP); + gpu_mem.write32(kCodeAddress + + (amdgpu::ComputeUnitCore::kDebugFunctionalQuantum + 1) * sizeof(uint32_t), + S_ENDPGM_GFX9); + + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA4; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 104; + cfg.vgprs_per_wf = 256; + cfg.lds_size_kb = 64; + + auto cu = amdgpu::ComputeUnitCore::create("functional_debug_cu", cfg, &gpu_mem, &l2); + ASSERT_NE(cu, nullptr); + auto *wf = cu->dispatch_wf(0, kCodeAddress, cfg.sgprs_per_wf, cfg.vgprs_per_wf); + ASSERT_NE(wf, nullptr); + + cu->set_debug_active(true); + EXPECT_TRUE(cu->execute_quantum()); + EXPECT_EQ(wf->pc, + kCodeAddress + amdgpu::ComputeUnitCore::kDebugFunctionalQuantum * sizeof(uint32_t)); + EXPECT_FALSE(wf->is_halted()); +} + // --------------------------------------------------------------------------- // MUBUF lds modifier test: verify that buffer_load_dword with the lds bit set // (bit 16 of dword 0) produces a disassembly string containing " lds". diff --git a/emulation/rocjitsu/tests/halt_snapshot_plugin.h b/emulation/rocjitsu/tests/halt_snapshot_plugin.h index 27a23cbfffa7..48084f5cd996 100644 --- a/emulation/rocjitsu/tests/halt_snapshot_plugin.h +++ b/emulation/rocjitsu/tests/halt_snapshot_plugin.h @@ -22,6 +22,7 @@ #include "simdojo/sim/component.h" +#include #include #include #include @@ -43,17 +44,23 @@ struct WavefrontSnapshot { uint64_t exec = 0; uint64_t vcc = 0; uint32_t status = 0; - uint32_t mode_raw = 0; ///< MODE register at halt. - uint8_t vgpr_msb_mode = 0; ///< Decoded s_set_vgpr_msb layout at halt. - uint64_t lds_size_bytes = 0; ///< Size of the LDS region visible to this wave. - simdojo::ComponentID cu_id = 0; ///< Originating CU component id (for per-CU grouping). - std::vector sgprs; ///< Full physical SGPR block (sgprs_per_wf), so TTMP - ///< slots past num_sgprs remain visible to tests. - std::vector vgprs; ///< [vgpr_block * wf_size], row-major by physical reg. + uint32_t mode_raw = 0; ///< MODE register at halt. + uint8_t vgpr_msb_mode = 0; ///< Decoded s_set_vgpr_msb layout at halt. + uint64_t lds_size_bytes = 0; ///< Size of the LDS region visible to this wave. + simdojo::ComponentID cu_id = 0; ///< Originating CU component id (for per-CU grouping). + std::vector sgprs; ///< Full physical SGPR block (sgprs_per_wf). + std::array ttmps{}; ///< Trap-temporary file (TTMP0-15). + std::vector vgprs; ///< [vgpr_block * wf_size], row-major by physical reg. /// @brief Read a captured SGPR by architectural index. uint32_t sgpr(uint32_t idx) const { return sgprs.at(idx); } + /// @brief Read a captured trap-temporary register. + /// @details TTMPs are a separate register file, not the tail of the SGPR + /// allocation: the ISA decoder routes scalar selectors 108..123 here. Tests + /// that want TTMP7 ask for ttmp(7), not sgpr(115). + uint32_t ttmp(uint32_t idx) const { return ttmps.at(idx); } + /// @brief Read a captured 64-bit SGPR pair (lo at idx, hi at idx+1). uint64_t sgpr64(uint32_t idx) const { return (static_cast(sgprs.at(idx + 1)) << 32) | sgprs.at(idx); @@ -126,15 +133,18 @@ class HaltSnapshotPlugin : public ExecutionPlugin { // to observe physical registers while the wave is still resident at halt. const amdgpu::RegisterAccess regs(wf); - // Capture the full physical SGPR block (sgprs_per_wf), not just the requested - // count: TTMP registers alias into the high slots of the block and tests read - // them by physical index (e.g. TTMP7 at 115, TTMP9 at 117). + // Capture the full physical SGPR block (sgprs_per_wf), not just the + // requested count, so tests can inspect slots past num_sgprs. const uint32_t sbase = wf.sgpr_alloc().base; const uint32_t sgpr_block = wf.cu().sgprs_per_wf(); s.sgprs.reserve(sgpr_block); for (uint32_t i = 0; i < sgpr_block; ++i) s.sgprs.push_back(regs.read_sgpr(sbase + i)); + // TTMPs live in their own file, so capture them separately. + for (uint32_t i = 0; i < s.ttmps.size(); ++i) + s.ttmps[i] = wf.ttmp(i); + // Capture the full physical VGPR block (normal + AccVGPR bank) so tests can // inspect accumulator registers as well as ordinary VGPRs. s.vgpr_block = wf.cu().vgpr_allocation_block_size(); diff --git a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp index d03c676ca05a..5043fcc19436 100644 --- a/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp +++ b/emulation/rocjitsu/tests/instruction_execution_harness_test.cpp @@ -12,10 +12,13 @@ #include "decode_test_util.h" #include "rocjitsu/base/rj_compiler.h" #include "rocjitsu/code/rj_code.h" +#include "rocjitsu/isa/arch/amdgpu/cdna4/isa.h" #include "rocjitsu/isa/arch/amdgpu/cdna5/isa.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna1/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna2/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna3/opcodes.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna4/encodings.h" +#include "rocjitsu/isa/arch/amdgpu/generated/cdna4/machine_insts.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna4/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/cdna5/opcodes.h" #include "rocjitsu/isa/arch/amdgpu/generated/rdna1/opcodes.h" @@ -188,6 +191,29 @@ class Gfx1250MemoryTestCu } }; +class Cdna4MemoryTestCu + : public amdgpu::IsaExecComputeUnit { +public: + using Base = amdgpu::IsaExecComputeUnit; + + Cdna4MemoryTestCu(std::string name, const amdgpu::ComputeUnitCore::Config &config, + amdgpu::GpuMemory *memory, amdgpu::L2Cache *l2) + : Base(std::move(name), config, memory, l2) { + if (l2) + l2->set_backing_memory(memory); + set_memory(memory); + set_l2(l2); + } + + void execute_and_route(Instruction *inst, amdgpu::Wavefront &wf) { + execute_instruction(inst, wf); + if (inst->is_memory_op()) + route_memory_inst(inst, wf); + else + delete inst; + } +}; + /// @brief Check if a mnemonic should be skipped in the execution harness. /// /// Memory instructions require valid addresses and will crash on zeroed state. @@ -737,6 +763,46 @@ TEST(Cdna4Vop3Test, CmpClassF16WritesWave64UpperMaskDword) { } } +TEST(Cdna4Vop3Test, BcntAddsSourceAccumulator) { + for (bool force_scalar : {false, true}) { + ForceScalarGuard guard(force_scalar); + amdgpu::GpuMemory gpu_mem(force_scalar ? "cdna4_bcnt_scalar_mem" : "cdna4_bcnt_simd_mem"); + amdgpu::L2Cache l2(force_scalar ? "cdna4_bcnt_scalar_l2" : "cdna4_bcnt_simd_l2"); + + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA4; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 106; + cfg.vgprs_per_wf = 256; + cfg.lds_size_kb = 64; + + auto cu = amdgpu::ComputeUnitCore::create("cdna4", cfg, &gpu_mem, &l2); + ASSERT_NE(cu, nullptr); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); + ASSERT_NE(wf, nullptr); + + const uint32_t vb = wf->vgpr_alloc().base; + cu->raw_vgpr_reg<64>(vb + 0)[0] = 0x80000001u; + cu->raw_vgpr_reg<64>(vb + 1)[0] = 7u; + wf->set_exec(1); + + const auto words = encode_cdna_vop3(cdna4::kVBcntU32B32Vop3, /*vdst=*/2, + /*src0=*/256, /*src1=*/257, /*src2=*/0); + DecodeResult decoded = decoder->decode(words.data()); + ASSERT_TRUE(decoded.succeeded()); + std::unique_ptr inst = std::move(decoded.value()); + ASSERT_NE(inst, nullptr); + ASSERT_EQ(std::string_view(inst->mnemonic()), "v_bcnt_u32_b32"); + cu->execute_instruction(inst.get(), *wf); + + EXPECT_EQ(cu->raw_vgpr_reg<64>(vb + 2)[0], 9u); + if (!wf->is_halted()) + wf->halt(); + } +} + TEST(CdnaVop3True16Test, B16I16U16OpsUseOpSelAndCdnaDestinationPolicy) { struct ArchCase { rj_code_arch_t arch; @@ -5776,9 +5842,16 @@ TEST(HwregHelperTest, Rdna3TablesNameXmlHwregIds) { auto *wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); ASSERT_NE(wf, nullptr); + // TRAPSTS is backed by Wavefront::trapsts_ on every arch: the GPU trap + // handler reads the excp cause on entry and clears it before s_rfe, so a + // write has to reach wave state rather than report Unsupported. EXPECT_STREQ(amdgpu::hwreg_name(*wf, encode_hwreg(3)), "TRAPSTS"); EXPECT_EQ(amdgpu::write_hwreg_field(*wf, encode_hwreg(3), 1u), - amdgpu::HwregAccessResult::Unsupported); + amdgpu::HwregAccessResult::Success); + uint32_t trapsts = 0; + EXPECT_EQ(amdgpu::read_hwreg_field(*wf, encode_hwreg(3), trapsts), + amdgpu::HwregAccessResult::Success); + EXPECT_EQ(trapsts, 1u); EXPECT_STREQ(amdgpu::hwreg_name(*wf, encode_hwreg(14)), "FLUSH_IB"); EXPECT_EQ(amdgpu::write_hwreg_field(*wf, encode_hwreg(14), 1u), amdgpu::HwregAccessResult::Unsupported); @@ -6063,3 +6136,83 @@ TEST(D16FormatExecution, PackedFormatD16LoadStoreThrowUnimplemented) { } } // namespace + +// FLAT routing is decided per lane against the private aperture, so one wave can +// mix scratch lanes with global ones. The dword-interleaved scratch swizzle is a +// property of the private lanes only: applying its stride instruction-wide put a +// global lane's second dword at addr + wf_size*4 instead of addr + 4. +TEST(Cdna4FlatMixedApertureTest, ScratchSwizzleDoesNotStrideGlobalLanes) { + amdgpu::GpuMemory gpu_mem("cdna4_flat_mixed_mem"); + amdgpu::L2Cache l2("cdna4_flat_mixed_l2"); + + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA4; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 106; + cfg.vgprs_per_wf = 256; + cfg.lds_size_kb = 64; + + Cdna4MemoryTestCu cu("cdna4", cfg, &gpu_mem, &l2); + auto decoder = Decoder::create(ROCJITSU_CODE_ARCH_CDNA4); + ASSERT_NE(decoder, nullptr); + + auto *wf = cu.dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); + ASSERT_NE(wf, nullptr); + + constexpr uint64_t kPrivateBase = 0x0000200000000000ULL; + constexpr uint64_t kScratchBase = 0x8000; + constexpr uint64_t kGlobalAddr = 0x2000; + constexpr uint32_t kScratchWord0 = 0xAA0000A0u; + constexpr uint32_t kScratchWord1 = 0xAA0000A1u; + constexpr uint32_t kGlobalWord0 = 0xBB0000B0u; + constexpr uint32_t kGlobalWord1 = 0xBB0000B1u; + + wf->set_apertures(0, 0, kPrivateBase, kPrivateBase + 0x10000); + wf->set_scratch_base(kScratchBase); + wf->set_exec(0x3u); // lane 0 -> private aperture, lane 1 -> global + + const uint32_t vb = wf->vgpr_alloc().base; + const uint64_t lane_addr[2] = {kPrivateBase, kGlobalAddr}; + const uint32_t lane_data[2][2] = {{kScratchWord0, kScratchWord1}, {kGlobalWord0, kGlobalWord1}}; + for (uint32_t lane = 0; lane < 2; ++lane) { + cu.write_vgpr(vb + 0, lane, static_cast(lane_addr[lane])); + cu.write_vgpr(vb + 1, lane, static_cast(lane_addr[lane] >> 32)); + cu.write_vgpr(vb + 2, lane, lane_data[lane][0]); + cu.write_vgpr(vb + 3, lane, lane_data[lane][1]); + } + + const uint32_t stride = wf->wf_size() * static_cast(sizeof(uint32_t)); + for (uint64_t a : {kGlobalAddr, kGlobalAddr + 4, kGlobalAddr + stride, kScratchBase, + kScratchBase + 4, kScratchBase + stride}) + gpu_mem.write32(a, 0u); + + // flat_store_dwordx2 v[0:1], v[2:3] + cdna4::FlatMachineInst enc{}; + enc.encoding = cdna4::encoding::kFlat >> 3; + enc.op = cdna4::kFlatStoreDwordx2; + enc.seg = 0; // FLAT + enc.addr = 0; + enc.data = 2; + enc.saddr = 0x7F; + const auto words = std::bit_cast>(enc); + + std::unique_ptr store(decode_valid(*decoder, words.data())); + ASSERT_NE(store, nullptr); + ASSERT_EQ(std::string_view(store->mnemonic()), "flat_store_dwordx2"); + cu.execute_and_route(store.release(), *wf); + cu.flush_all(); + + // The global lane stays contiguous even though lane 0 went to scratch. + EXPECT_EQ(gpu_mem.read32(kGlobalAddr), kGlobalWord0); + EXPECT_EQ(gpu_mem.read32(kGlobalAddr + 4), kGlobalWord1); + EXPECT_EQ(gpu_mem.read32(kGlobalAddr + stride), 0u) + << "global lane was strided by the scratch swizzle"; + + // The private lane keeps the dword-interleaved layout rocm-dbgapi reads. + EXPECT_EQ(gpu_mem.read32(kScratchBase), kScratchWord0); + EXPECT_EQ(gpu_mem.read32(kScratchBase + stride), kScratchWord1); + EXPECT_EQ(gpu_mem.read32(kScratchBase + 4), 0u); + + if (!wf->is_halted()) + wf->halt(); +} diff --git a/emulation/rocjitsu/tests/interposer_dup_test.cpp b/emulation/rocjitsu/tests/interposer_dup_test.cpp index a65984dcef3d..0c6c25cdf5a6 100644 --- a/emulation/rocjitsu/tests/interposer_dup_test.cpp +++ b/emulation/rocjitsu/tests/interposer_dup_test.cpp @@ -34,6 +34,8 @@ RJ_DIAGNOSTIC_POP #include #include #include +#include +#include #include #include #include @@ -83,6 +85,31 @@ TEST(InterposerDupTest, DupKeepsKfdRoutingAfterPrimaryClose) { EXPECT_EQ(close(dup_fd), 0); } +TEST(InterposerDupTest, ProcMapsNamesRemoteKfdMarker) { + // The marker only exists on the remote path: RemoteDriver::open() creates it, + // and in local mode there is no RemoteDriver at all. $ROCJITSU_INVOCATION_DIR + // is set for every rocjitsu-launched process regardless of backend, so gate on + // the daemon socket actually being there instead -- otherwise this skips + // nothing under a plain `rocjitsu --config ... --` run and fails for a reason + // that is not a defect. + const char *invocation_dir = getenv("ROCJITSU_INVOCATION_DIR"); + if (invocation_dir == nullptr || *invocation_dir == '\0') + GTEST_SKIP() << "remote backend required"; + if (access((std::string(invocation_dir) + "/daemon.sock").c_str(), F_OK) != 0) + GTEST_SKIP() << "remote backend required"; + + int kfd = open_kfd(); + ASSERT_GE(kfd, 0); + + std::ifstream maps("/proc/self/maps"); + ASSERT_TRUE(maps.is_open()); + std::string contents((std::istreambuf_iterator(maps)), std::istreambuf_iterator()); + EXPECT_NE(contents.find("/dev/kfd"), std::string::npos); + EXPECT_EQ(contents.find("rocjitsu_remote_kfd"), std::string::npos); + + EXPECT_EQ(close(kfd), 0); +} + // fcntl(F_DUPFD_CLOEXEC) is the dup path libdrm uses; it must also preserve KFD // routing on the duplicate. TEST(InterposerDupTest, FcntlDupfdKeepsKfdRouting) { @@ -177,6 +204,26 @@ TEST(InterposerDupTest, Dup3RoutesKfdAndRejectsSameFd) { EXPECT_EQ(close(pipefd[1]), 0); } +TEST(InterposerDupTest, VforkChildCloseKeepsParentKfdRoutable) { + int kfd = open_kfd(); + ASSERT_GE(kfd, 0); + ASSERT_TRUE(kfd_version_ok(kfd)); + + pid_t child = vfork(); + ASSERT_NE(child, -1); + if (child == 0) { + close(kfd); + _exit(0); + } + + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + ASSERT_TRUE(WIFEXITED(status)); + ASSERT_EQ(WEXITSTATUS(status), 0); + EXPECT_TRUE(kfd_version_ok(kfd)); + EXPECT_EQ(close(kfd), 0); +} + // Overwriting the primary KFD fd number via dup2 while a dup keeps the backend // alive must (a) leave the dup routing, and (b) let a fresh open("/dev/kfd") // return a valid, routable KFD fd. This is the reopen-after-overwrite path that diff --git a/emulation/rocjitsu/tests/kfd_ioctl_test.cpp b/emulation/rocjitsu/tests/kfd_ioctl_test.cpp index 317f07ccac09..816648bb85ac 100644 --- a/emulation/rocjitsu/tests/kfd_ioctl_test.cpp +++ b/emulation/rocjitsu/tests/kfd_ioctl_test.cpp @@ -2,10 +2,13 @@ // SPDX-License-Identifier: MIT #include "rocjitsu/config/config_loader.h" +#include "rocjitsu/kmd/linux/cwsr.h" #include "rocjitsu/kmd/linux/kfd_ioctl_utils.h" #include "rocjitsu/kmd/linux/remote_driver.h" #include "rocjitsu/kmd/linux/rpc.h" #include "rocjitsu/kmd/linux/simulated_kfd.h" +#include "rocjitsu/vm/amdgpu/command_processor.h" +#include "rocjitsu/vm/amdgpu/compute_unit.h" #include "rocjitsu/vm/rj_vm.h" #include "rocjitsu/vm/virtual_machine.h" @@ -18,17 +21,22 @@ #include #include +#include #include #include #include +#include +#include #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -40,6 +48,52 @@ namespace { const std::string CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx950_mi355x.json"; constexpr uint32_t kGpuId = 38144; +// A part with no modelled CWSR record layout. gfx1100 is not a debug target: +// kmd::cwsr_layout_modelled() covers gfx942/gfx950 only, and the driver has to +// decline stops there rather than publish a record rocm-dbgapi would misparse. +const std::string RDNA3_CONFIG_PATH = std::string(CONFIG_DIR) + "/gfx1100_w7900.json"; +constexpr uint32_t kRdna3GpuId = 7019; + +class ChildProcessGuard { +public: + explicit ChildProcessGuard(pid_t pid) : pid_(pid) {} + ~ChildProcessGuard() { + if (pid_ <= 0) + return; + kill(pid_, SIGKILL); + int status = 0; + while (waitpid(pid_, &status, 0) == -1 && errno == EINTR) { + } + } + + ChildProcessGuard(const ChildProcessGuard &) = delete; + ChildProcessGuard &operator=(const ChildProcessGuard &) = delete; + + void release() { pid_ = -1; } + +private: + pid_t pid_; +}; + +int daemon_debug_enable(rocjitsu::SimulatedKfd &daemon, uint32_t debugger, + kfd_ioctl_dbg_trap_args &args) { + const std::string proc_path = std::format("/proc/{}", args.pid); + const int proc_fd = ::open(proc_path.c_str(), O_RDONLY | O_DIRECTORY | O_CLOEXEC); + if (proc_fd < 0) + return -errno; + int mem_fd = ::openat(proc_fd, "mem", O_RDWR | O_CLOEXEC); + if (mem_fd < 0) { + const int open_errno = errno; + ::close(proc_fd); + return -open_errno; + } + const int result = daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &args, &mem_fd, proc_fd); + if (mem_fd >= 0) + ::close(mem_fd); + ::close(proc_fd); + return result; +} + uint32_t query_gb_addr_config(const std::string &config_path, uint32_t gpu_id) { auto loaded = rocjitsu::config::load_config(config_path.c_str(), rocjitsu::kEmbeddedSchema); auto root = loaded.take_root(); @@ -76,9 +130,13 @@ uint32_t query_gb_addr_config(const std::string &config_path, uint32_t gpu_id) { class KfdIoctlTest : public ::testing::Test { protected: - void SetUp() override { - setenv("RJ_CONFIG", CONFIG_PATH.c_str(), 1); - loaded_ = rocjitsu::config::load_config(CONFIG_PATH.c_str(), rocjitsu::kEmbeddedSchema); + void SetUp() override { SetUpWithConfig(CONFIG_PATH); } + + // Split out so a fixture can bring up a different part. Uses ASSERT_*, so it + // has to stay void-returning and be called directly from SetUp(). + void SetUpWithConfig(const std::string &config_path) { + setenv("RJ_CONFIG", config_path.c_str(), 1); + loaded_ = rocjitsu::config::load_config(config_path.c_str(), rocjitsu::kEmbeddedSchema); auto root = loaded_.take_root(); auto *soc = dynamic_cast(root.get()); ASSERT_NE(soc, nullptr); @@ -130,6 +188,14 @@ class KfdIoctlTest : public ::testing::Test { std::vector debug_fds_; }; +// Same driver surface, brought up on a part whose CWSR layout is not modelled. +// Deriving does not inherit KfdIoctlTest's cases: TEST_F registers against the +// fixture it names, so only the cases written against this one run here. +class KfdIoctlRdna3Test : public KfdIoctlTest { +protected: + void SetUp() override { SetUpWithConfig(RDNA3_CONFIG_PATH); } +}; + TEST_F(KfdIoctlTest, SetMemoryPolicy) { kfd_ioctl_set_memory_policy_args args{}; args.gpu_id = kGpuId; @@ -375,6 +441,13 @@ TEST_F(KfdIoctlTest, DbgTrapUnknownPidReturnsESRCH) { EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &args), -ESRCH); } +TEST_F(KfdIoctlTest, DbgTrapInvalidPidReturnsESRCH) { + kfd_ioctl_dbg_trap_args args{}; + args.pid = UINT32_MAX; + args.op = KFD_IOC_DBG_TRAP_ENABLE; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &args), -ESRCH); +} + TEST_F(KfdIoctlTest, DbgTrapOpBeforeEnableReturnsEINVAL) { kfd_ioctl_dbg_trap_args args{}; args.pid = static_cast(getpid()); @@ -431,11 +504,11 @@ TEST_F(KfdIoctlTest, DbgTrapDoubleEnableReturnsEALREADY) { } // Hammers ENABLE/DISABLE on one session from many threads to exercise -// debug_mutex_ under ThreadSanitizer. Races are legitimate: a losing ENABLE +// debug_sessions_mutex_ under ThreadSanitizer. Races are legitimate: a losing ENABLE // sees EALREADY and a losing DISABLE sees EINVAL. The invariant is that the // driver serializes them without a data race or torn session state — every call // returns one of the well-defined codes, never a crash or a bogus errno. Uses -// self-debug (target pid == getpid()) so the whole cycle stays on debug_mutex_ +// self-debug (target pid == getpid()) so the whole cycle stays on debug_sessions_mutex_ // and runtime_mutex_. In local mode the session never owns dbg_fd, so a single // shared eventfd can back every ENABLE. TEST_F(KfdIoctlTest, DbgTrapConcurrentEnableDisableIsRaceFree) { @@ -542,19 +615,430 @@ TEST_F(KfdIoctlTest, DbgTrapWatchBadGpuReturnsENODEV) { EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &watch), -ENODEV); } -TEST_F(KfdIoctlTest, DbgTrapAdmittedOpNotYetImplemented) { +TEST_F(KfdIoctlTest, DbgTrapQueryDebugEventReportsIdle) { kfd_ioctl_dbg_trap_args en{}; en.pid = static_cast(getpid()); en.op = KFD_IOC_DBG_TRAP_ENABLE; en.enable.dbg_fd = make_debug_fd(); ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &en), 0); - // QUERY_DEBUG_EVENT is not a HW-op, so the gate ladder admits it; the handler - // itself is added by a later change and currently reports not-implemented. + // QUERY_DEBUG_EVENT is not a HW-op, so it is available before runtime enable. + // EAGAIN is the kernel contract when no exception is pending. kfd_ioctl_dbg_trap_args q{}; q.pid = static_cast(getpid()); q.op = KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT; - EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &q), -ENOSYS); + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &q), -EAGAIN); + + // SEND_RUNTIME_EVENT acknowledges the runtime-enable debugger handshake. + kfd_ioctl_dbg_trap_args event{}; + event.pid = static_cast(getpid()); + event.op = KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &event), 0); +} + +TEST_F(KfdIoctlTest, DbgTrapQueryRuntimeExceptionInfoClampsAndPopulates) { + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK | KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK; + runtime.r_debug = 0x123456789abcdef0ULL; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = make_debug_fd(); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::array buffer; + buffer.fill(0xA5); + kfd_ioctl_dbg_trap_args query{}; + query.pid = static_cast(getpid()); + query.op = KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO; + query.query_exception_info.exception_code = EC_PROCESS_RUNTIME; + query.query_exception_info.info_ptr = reinterpret_cast(buffer.data()); + query.query_exception_info.info_size = sizeof(kfd_runtime_info); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &query), 0); + EXPECT_EQ(query.query_exception_info.info_size, sizeof(kfd_runtime_info)); + + kfd_runtime_info info{}; + std::memcpy(&info, buffer.data(), sizeof(info)); + EXPECT_EQ(info.r_debug, runtime.r_debug); + EXPECT_EQ(info.runtime_state, static_cast(DEBUG_RUNTIME_STATE_ENABLED)); + EXPECT_EQ(info.ttmp_setup, 1u); + EXPECT_TRUE(std::all_of(buffer.begin() + sizeof(info), buffer.end(), + [](uint8_t byte) { return byte == 0xA5; })); +} + +// rocdbgapi has to learn that a process's runtime went away. Otherwise it keeps +// driving queues of a process in teardown, and those ops are gated on the +// runtime being enabled: they answer -EPERM, which rocdbgapi escalates to a +// fatal os_driver::resume_queues failure and GDB to an internal error +// (gdb.rocm/multi-inferior-stress.exp). +// +// The target here debugs itself, which is the one shape that reports without +// blocking: the ack would have to come from the thread already inside this +// ioctl. That keeps the test to what a single process can observe -- the event, +// the notifier, and the toggled state rocdbgapi reads back. +TEST_F(KfdIoctlTest, RuntimeDisableReportsProcessRuntimeTransition) { + const auto pid = static_cast(getpid()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + const int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = pid; + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_PROCESS_RUNTIME); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + // Attaching to an already-enabled runtime reports it through the returned + // runtime_info rather than the notifier, but drain anyway so the read below + // can only be answering the disable. + uint64_t drained = 0; + // EAGAIN is the expected answer -- the notifier is EFD_NONBLOCK and the attach + // does not post to it -- so the result is deliberately not asserted on. + [[maybe_unused]] const ssize_t drained_rc = ::read(notifier, &drained, sizeof(drained)); + + kfd_ioctl_runtime_enable_args disable{}; + disable.mode_mask = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &disable), 0); + + uint64_t notifications = 0; + ASSERT_EQ(::read(notifier, ¬ifications, sizeof(notifications)), + static_cast(sizeof(notifications))) + << strerror(errno); + EXPECT_EQ(notifications, 1u); + + kfd_ioctl_dbg_trap_args query{}; + query.pid = pid; + query.op = KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT; + query.query_debug_event.exception_mask = KFD_EC_MASK(EC_PROCESS_RUNTIME); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &query), 0); + EXPECT_NE(query.query_debug_event.exception_mask & KFD_EC_MASK(EC_PROCESS_RUNTIME), 0u); + + // The state behind the event has to have toggled: rocdbgapi treats a + // runtime_state that reads the same as before as a spurious runtime + // exception and aborts. + kfd_runtime_info info{}; + kfd_ioctl_dbg_trap_args info_query{}; + info_query.pid = pid; + info_query.op = KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO; + info_query.query_exception_info.exception_code = EC_PROCESS_RUNTIME; + info_query.query_exception_info.info_ptr = reinterpret_cast(&info); + info_query.query_exception_info.info_size = sizeof(info); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &info_query), 0); + EXPECT_EQ(info.runtime_state, static_cast(DEBUG_RUNTIME_STATE_DISABLED)); + + // The gate the report exists to warn about still stands for anything that + // would touch hardware. + kfd_ioctl_dbg_trap_args launch_mode{}; + launch_mode.pid = pid; + launch_mode.op = KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE; + launch_mode.launch_mode.launch_mode = KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &launch_mode), -EPERM); + + // A resume naming a queue the process does not have is the one shape that is + // answered instead: it asks nothing of the hardware, and the per-queue INVALID + // bit is how rocdbgapi learns to retire the queue rather than escalating the + // refusal to a fatal error. + constexpr uint32_t kQueueInvalid = uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT; + uint32_t queue_id = 7; + kfd_ioctl_dbg_trap_args resume{}; + resume.pid = pid; + resume.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + resume.resume_queues.queue_array_ptr = reinterpret_cast(&queue_id); + resume.resume_queues.num_queues = 1; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &resume), 0); + EXPECT_NE(queue_id & kQueueInvalid, 0u); +} + +TEST_F(KfdIoctlTest, DbgTrapAttachDetachConfigOpsValidateAndResetState) { + kfd_ioctl_runtime_enable_args rt{}; + rt.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &rt), 0); + + const auto pid = static_cast(getpid()); + auto enable = [&] { + kfd_ioctl_dbg_trap_args en{}; + en.pid = pid; + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = make_debug_fd(); + return driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &en); + }; + ASSERT_EQ(enable(), 0); + + kfd_ioctl_dbg_trap_args flags{}; + flags.pid = pid; + flags.op = KFD_IOC_DBG_TRAP_SET_FLAGS; + flags.set_flags.flags = KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &flags), 0); + EXPECT_EQ(flags.set_flags.flags, 0u); + flags.set_flags.flags = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &flags), 0); + EXPECT_EQ(flags.set_flags.flags, static_cast(KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP)); + + kfd_ioctl_dbg_trap_args mode{}; + mode.pid = pid; + mode.op = KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE; + mode.launch_mode.launch_mode = 2; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &mode), -EINVAL); + mode.launch_mode.launch_mode = KFD_DBG_TRAP_WAVE_LAUNCH_MODE_HALT; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &mode), 0); + + kfd_ioctl_dbg_trap_args override_args{}; + override_args.pid = pid; + override_args.op = KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE; + override_args.launch_override.override_mode = KFD_DBG_TRAP_OVERRIDE_OR; + override_args.launch_override.enable_mask = KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH; + override_args.launch_override.support_request_mask = KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &override_args), 0); + EXPECT_EQ(override_args.launch_override.enable_mask, 0u); + EXPECT_EQ(override_args.launch_override.support_request_mask, + static_cast(KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH)); + + override_args.launch_override.override_mode = 99; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &override_args), -EINVAL); + + kfd_ioctl_dbg_trap_args snapshot{}; + snapshot.pid = pid; + snapshot.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snapshot), 0); + EXPECT_EQ(snapshot.queue_snapshot.num_queues, 0u); + EXPECT_EQ(snapshot.queue_snapshot.entry_size, sizeof(kfd_queue_snapshot_entry)); + + kfd_ioctl_dbg_trap_args queues{}; + queues.pid = pid; + queues.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + std::array queue_ids{17, 23}; + queues.suspend_queues.queue_array_ptr = reinterpret_cast(queue_ids.data()); + queues.suspend_queues.num_queues = queue_ids.size(); + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &queues), 0); + constexpr uint32_t kInvalid = uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT; + EXPECT_EQ(queue_ids, (std::array{17 | kInvalid, 23 | kInvalid})); + queues.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + queues.resume_queues.queue_array_ptr = reinterpret_cast(queue_ids.data()); + queues.resume_queues.num_queues = queue_ids.size(); + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &queues), 0); + EXPECT_EQ(queue_ids, (std::array{17 | kInvalid, 23 | kInvalid})); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = pid; + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &dis), 0); + ASSERT_EQ(enable(), 0); + + flags.set_flags.flags = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &flags), 0); + EXPECT_EQ(flags.set_flags.flags, 0u); + override_args.launch_override.override_mode = KFD_DBG_TRAP_OVERRIDE_OR; + override_args.launch_override.enable_mask = 0; + override_args.launch_override.support_request_mask = KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &override_args), 0); + EXPECT_EQ(override_args.launch_override.enable_mask, 0u); + EXPECT_EQ(override_args.launch_override.support_request_mask, + static_cast(KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH)); +} + +TEST_F(KfdIoctlTest, DbgTrapQueueControlOnlyChangesRequestedQueue) { + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = make_debug_fd(); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::array, 2> rings{std::vector(4096), std::vector(4096)}; + std::array read_pointers{}; + std::array write_pointers{}; + std::array queues{}; + for (size_t index = 0; index < queues.size(); ++index) { + auto &queue = queues[index]; + queue.gpu_id = kGpuId; + queue.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + queue.ring_base_address = reinterpret_cast(rings[index].data()); + queue.ring_size = static_cast(rings[index].size()); + queue.read_pointer_address = reinterpret_cast(&read_pointers[index]); + queue.write_pointer_address = reinterpret_cast(&write_pointers[index]); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &queue), 0); + } + + std::array snapshots{}; + kfd_ioctl_dbg_trap_args snapshot{}; + snapshot.pid = static_cast(getpid()); + snapshot.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + snapshot.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(snapshots.data()); + snapshot.queue_snapshot.num_queues = snapshots.size(); + snapshot.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snapshot), 0); + + uint32_t queue_id = queues[0].queue_id; + kfd_ioctl_dbg_trap_args suspend{}; + suspend.pid = static_cast(getpid()); + suspend.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + suspend.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + suspend.suspend_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &suspend), 1); + + bool requested_suspended = false; + bool unrelated_suspended = false; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + requested_suspended |= + cp->queue_debug_suspended_for_test(queues[0].queue_id, driver_->local_process_id()); + unrelated_suspended |= + cp->queue_debug_suspended_for_test(queues[1].queue_id, driver_->local_process_id()); + }); + EXPECT_TRUE(requested_suspended); + EXPECT_FALSE(unrelated_suspended); + + suspend.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + suspend.resume_queues.queue_array_ptr = reinterpret_cast(&queue_id); + suspend.resume_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &suspend), 1); + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + EXPECT_FALSE( + cp->queue_debug_suspended_for_test(queues[0].queue_id, driver_->local_process_id())); + }); +} + +TEST_F(KfdIoctlTest, DbgTrapWaveLaunchOverrideValidatesRequest) { + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = make_debug_fd(); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + kfd_ioctl_dbg_trap_args request{}; + request.pid = static_cast(getpid()); + request.op = KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE; + request.launch_override.override_mode = KFD_DBG_TRAP_OVERRIDE_REPLACE; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &request), -EINVAL); + + request.launch_override.override_mode = KFD_DBG_TRAP_OVERRIDE_OR; + request.launch_override.support_request_mask = + KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH | KFD_DBG_TRAP_MASK_FP_INVALID; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &request), -EACCES); + + request.launch_override.enable_mask = KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH; + request.launch_override.support_request_mask = KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &request), 0); + EXPECT_EQ(request.launch_override.enable_mask, 0u); + EXPECT_EQ(request.launch_override.support_request_mask, + static_cast(KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH)); +} + +TEST_F(KfdIoctlTest, DbgTrapNodeAddressWatchAllocatesAndFreesSlots) { + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = make_debug_fd(); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::array slots{}; + for (uint32_t index = 0; index < slots.size(); ++index) { + kfd_ioctl_dbg_trap_args watch{}; + watch.pid = static_cast(getpid()); + watch.op = KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH; + watch.set_node_address_watch.gpu_id = kGpuId; + watch.set_node_address_watch.address = 0x1000 + index * 0x100; + watch.set_node_address_watch.mask = ~0xFFu; + watch.set_node_address_watch.mode = KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &watch), 0); + slots[index] = watch.set_node_address_watch.id; + } + EXPECT_EQ(slots, (std::array{0, 1, 2, 3})); + + kfd_ioctl_dbg_trap_args exhausted{}; + exhausted.pid = static_cast(getpid()); + exhausted.op = KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH; + exhausted.set_node_address_watch.gpu_id = kGpuId; + exhausted.set_node_address_watch.mode = KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &exhausted), -ENOMEM); + + kfd_ioctl_dbg_trap_args clear{}; + clear.pid = static_cast(getpid()); + clear.op = KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH; + clear.clear_node_address_watch.gpu_id = kGpuId; + clear.clear_node_address_watch.id = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &clear), 0); + exhausted.set_node_address_watch.address = 0x9000; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &exhausted), 0); + EXPECT_EQ(exhausted.set_node_address_watch.id, 1u); + clear.clear_node_address_watch.id = 4; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &clear), -EINVAL); +} + +TEST(KfdAddressWatchTest, KfdMaskPreservesImplicitUpperCompareBits) { + constexpr uint64_t watched_address = 0x00007FFF12345000ULL; + constexpr auto watch = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + watched_address, 0xFFFFFF80u, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL); + + EXPECT_EQ(watch.mask, 0xFFFFFFFFFFFFFF80ULL); + EXPECT_TRUE(watch.overlaps(watched_address + 4, sizeof(uint32_t))); + EXPECT_FALSE(watch.overlaps(watched_address + 128, sizeof(uint32_t))); + EXPECT_FALSE(watch.overlaps(watched_address ^ (uint64_t{1} << 32), sizeof(uint32_t))) + << "equal low 32 bits must not alias a different upper address"; +} + +TEST(KfdAddressWatchTest, OneAccessReportsEveryMatchingHardwareSlot) { + constexpr uint64_t address = 0x00007FFF12345013ULL; + rocjitsu::KfdProcess::DebugSession session; + session.address_watches[0] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address & ~uint64_t{3}, 0xFFFFFFFCu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL); + session.address_watches[1] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address, 0xFFFFFFFFu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD); + session.address_watches[2] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address, 0xFFFFFFFFu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL); + session.address_watches[3] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address, 0xFFFFFFFFu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ); + + // The mode sets the driver hands down, mirroring on_wave_watchpoint(). + constexpr uint32_t kAll = uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL; + constexpr uint32_t kWriteModes = kAll | (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD); + constexpr uint32_t kReadModes = kAll | (uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ); + EXPECT_EQ(session.matching_address_watch_slots(address, 1, kWriteModes), 0b0111u); + EXPECT_EQ(session.matching_address_watch_slots(address, 1, kReadModes), 0b1101u); +} + +// kfd_ioctl.h documents NONREAD as "write or atomic operations only", and +// rocdbgapi maps the STORE_AND_RMW kind a plain `(gdb) watch` requests onto it +// (os_driver.h). An atomic read-modify-write must therefore trip a NONREAD +// watch: comparing the programmed mode against the access mode for equality +// silently dropped every watchpoint on a variable updated by atomicAdd(). +TEST(KfdAddressWatchTest, AtomicAccessTripsNonreadAndAtomicWatches) { + constexpr uint64_t address = 0x00007FFF12345013ULL; + rocjitsu::KfdProcess::DebugSession session; + session.address_watches[0] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address, 0xFFFFFFFFu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD); + session.address_watches[1] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address, 0xFFFFFFFFu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC); + session.address_watches[2] = rocjitsu::KfdProcess::DebugSession::AddressWatch::from_kfd( + address, 0xFFFFFFFFu, KFD_DBG_TRAP_ADDRESS_WATCH_MODE_READ); + + constexpr uint32_t kAll = uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ALL; + constexpr uint32_t kNonread = uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_NONREAD; + constexpr uint32_t kAtomic = uint32_t{1} << KFD_DBG_TRAP_ADDRESS_WATCH_MODE_ATOMIC; + + EXPECT_EQ(session.matching_address_watch_slots(address, 4, kAll | kNonread | kAtomic), 0b011u) + << "an atomic RMW must trip both the write watch and the atomic watch"; + // A plain write is not an atomic, so it must not trip the ATOMIC-only watch. + EXPECT_EQ(session.matching_address_watch_slots(address, 4, kAll | kNonread), 0b001u); } // Local mode borrows the debugger's own fd (the session does not own it), so @@ -576,6 +1060,50 @@ TEST_F(KfdIoctlTest, DbgTrapLocalDisableLeavesDebuggerFdOpen) { EXPECT_NE(fcntl(fd, F_GETFD), -1) << "local-mode DISABLE must not close the debugger's fd"; } +TEST_F(KfdIoctlTest, DbgTrapDisableResumesStoppedQueue) { + const int fd = make_debug_fd(); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(getpid()); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = fd; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &en), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kGpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + rocjitsu::amdgpu::Wavefront *wave = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (wave != nullptr || cp->compute_units().empty()) + return; + wave = cp->compute_units().front()->dispatch_wf(/*wg_id=*/0, /*pc=*/0x600000000ULL, + /*sgprs=*/16, /*vgprs=*/4); + }); + ASSERT_NE(wave, nullptr); + wave->set_process_id(driver_->local_process_id()); + wave->set_queue_id(create.queue_id); + wave->set_debug_halted(true); + wave->set_debug_suspended(true); + wave->set_debug_single_step(true); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(getpid()); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &dis), 0); + + EXPECT_FALSE(wave->debug_halted()); + EXPECT_FALSE(wave->debug_suspended()); + EXPECT_FALSE(wave->debug_single_step()); +} + // The kernel copies min(user_size, sizeof(runtime_info)) bytes back and reports // the full struct size. An undersized buffer must truncate the copy — never // writing past the caller's buffer — while still reporting sizeof(kfd_runtime_info). @@ -618,7 +1146,7 @@ TEST_F(KfdIoctlTest, DbgTrapEnableOversizedRuntimeInfoPreservesTailInDaemonMode) ASSERT_NE(soc_, nullptr); rocjitsu::SimulatedKfd daemon_driver(*soc_, /*daemon_mode=*/true); - constexpr pid_t kClientPid = 4242; + const pid_t kClientPid = getpid(); uint32_t process_id = daemon_driver.open_process(kClientPid); ASSERT_NE(process_id, 0u); @@ -633,7 +1161,9 @@ TEST_F(KfdIoctlTest, DbgTrapEnableOversizedRuntimeInfoPreservesTailInDaemonMode) std::jthread server([&, server_fd = sv[1]] { for (;;) { rocjitsu::RpcHeader hdr{}; - if (!rocjitsu::rpc_recv_exact(server_fd, &hdr, sizeof(hdr))) + int in_fds[3] = {-1, -1, -1}; + size_t num_in = 3; + if (rocjitsu::rpc_recv_msg(server_fd, &hdr, sizeof(hdr), in_fds, &num_in) <= 0) break; if (hdr.opcode != rocjitsu::RPC_IOCTL) { rocjitsu::RpcHeader resp{}; @@ -658,7 +1188,15 @@ TEST_F(KfdIoctlTest, DbgTrapEnableOversizedRuntimeInfoPreservesTailInDaemonMode) dbg->enable.rinfo_ptr = reinterpret_cast(buf + arg_size); } - const int result = daemon_driver.ioctl(process_id, cmd, buf); + int mem_fd = num_in > 1 ? in_fds[1] : -1; + const int proc_fd = num_in > 2 ? in_fds[2] : -1; + const int result = daemon_driver.ioctl(process_id, cmd, buf, &mem_fd, proc_fd); + if (num_in > 0 && in_fds[0] >= 0) + ::close(in_fds[0]); + if (mem_fd >= 0) + ::close(mem_fd); + if (proc_fd >= 0) + ::close(proc_fd); rocjitsu::RpcHeader resp{}; resp.opcode = rocjitsu::RPC_IOCTL; @@ -843,7 +1381,30 @@ class DbgTrapDaemonTest : public ::testing::Test { cmd.buf_size = buf_size; cmd.shared_handle = -1; cmd.in_handle = in_handle; + cmd.in_mem_handle = -1; + cmd.in_proc_handle = -1; + if (cmd_id == AMDKFD_IOC_DBG_TRAP && in_handle >= 0) { + auto *dbg = static_cast(buf); + if (dbg->op == KFD_IOC_DBG_TRAP_ENABLE) { + cmd.in_proc_handle = ::open("/proc/self", O_RDONLY | O_DIRECTORY | O_CLOEXEC); + if (cmd.in_proc_handle < 0) + return -errno; + // mem_mismatch_path_ lets a test transfer a writable mem fd belonging to + // some other process, which is what the identity check exists to catch. + const char *mem_path = + mem_mismatch_path_.empty() ? "/proc/self/mem" : mem_mismatch_path_.c_str(); + cmd.in_mem_handle = ::open(mem_path, O_RDWR | O_CLOEXEC); + if (cmd.in_mem_handle < 0) { + ::close(cmd.in_proc_handle); + return -errno; + } + } + } rj_vm_execute_as(vm_, process_id_, &cmd); + if (cmd.in_mem_handle >= 0) + ::close(cmd.in_mem_handle); + if (cmd.in_proc_handle >= 0) + ::close(cmd.in_proc_handle); if (in_handle_out != nullptr) *in_handle_out = cmd.in_handle; return cmd.result; @@ -864,11 +1425,86 @@ class DbgTrapDaemonTest : public ::testing::Test { return execute(AMDKFD_IOC_DBG_TRAP, &dis, sizeof(dis), -1, nullptr); } - static constexpr rj_client_pid_t kClientPid = 4242; + const rj_client_pid_t kClientPid = getpid(); rj_vm_t *vm_ = nullptr; uint32_t process_id_ = 0; + std::string mem_mismatch_path_; }; +// The transferred mem fd becomes authoritative for guest reads and CWSR writes, +// so O_RDWR is not enough to accept it -- it also has to name the memory of the +// process whose /proc directory was pinned. A writable mem fd for some other +// live process must be refused, or the daemon would silently redirect both at +// the wrong address space. +TEST_F(DbgTrapDaemonTest, EnableRejectsAMemFdForADifferentProcess) { + // A live child, so /proc//mem exists and is openable for the whole test. + // ChildProcessGuard rather than a hand-rolled reap: every ASSERT_* below + // returns from the test, and only RAII kills and waits on all of those paths. + pid_t other = fork(); + ASSERT_GE(other, 0); + if (other == 0) { + for (;;) + pause(); + _exit(0); + } + ChildProcessGuard other_guard(other); + + const std::string other_mem = std::format("/proc/{}/mem", other); + // Confirm the premise: procfs gives it a different inode from our own. + struct stat ours {}; + struct stat theirs {}; + const util::UniqueHandle self_mem{::open("/proc/self/mem", O_RDWR | O_CLOEXEC)}; + ASSERT_GE(self_mem.get(), 0); + const util::UniqueHandle their_mem{::open(other_mem.c_str(), O_RDWR | O_CLOEXEC)}; + if (their_mem.get() < 0) { + // Hardened kernels can refuse this open outright; the gate is then moot. + GTEST_SKIP() << "cannot open another process's mem: " << strerror(errno); + } + ASSERT_EQ(fstat(self_mem.get(), &ours), 0); + ASSERT_EQ(fstat(their_mem.get(), &theirs), 0); + EXPECT_NE(ours.st_ino, theirs.st_ino); + + int notifier = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(notifier, 0); + util::UniqueHandle notifier_closer{notifier}; + + mem_mismatch_path_ = other_mem; + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(kClientPid); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = 0x0BADF00D; + // -1 rather than a sentinel the assertion would accept: execute() leaves the + // out-param untouched on its own early returns, and initialising it to + // anything else lets "never written" pass as "not adopted". + int in_handle_out = -1; + const int rejected = execute(AMDKFD_IOC_DBG_TRAP, &en, sizeof(en), notifier, &in_handle_out); + EXPECT_EQ(rejected, -ESRCH) << "a writable mem fd for another process was accepted"; + EXPECT_NE(in_handle_out, -1) << "the notifier was adopted by a rejected ENABLE"; + // Only a rejected ENABLE leaves the fd ours to close. If the gate regressed + // and the session took it, dropping ownership here keeps the failure to one + // assertion instead of adding a close() of a descriptor since reissued. + if (rejected == 0) + (void)notifier_closer.release(); + + // The matching fd still works, so the gate rejects the mismatch and not the + // transfer itself. + mem_mismatch_path_.clear(); + int notifier2 = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(notifier2, 0); + util::UniqueHandle notifier2_closer{notifier2}; + kfd_ioctl_dbg_trap_args ok{}; + ok.pid = static_cast(kClientPid); + ok.op = KFD_IOC_DBG_TRAP_ENABLE; + ok.enable.dbg_fd = 0x0BADF00D; + const int accepted = execute(AMDKFD_IOC_DBG_TRAP, &ok, sizeof(ok), notifier2, nullptr); + EXPECT_EQ(accepted, 0); + // Adopted by the session on success, so hand it over; still ours to close if + // the ENABLE failed. + if (accepted == 0) + (void)notifier2_closer.release(); + EXPECT_EQ(disable(), 0); +} + // The transferred fd (in_handle) replaces the client-side dbg_fd in the payload // and the session takes ownership (in_handle cleared so the transport does not // reclaim it). @@ -959,6 +1595,8 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { ASSERT_EQ(socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << strerror(errno); constexpr uint64_t kSentinel = 0x0102030405060708ULL; + constexpr uint64_t kMemorySentinel = 0x8877665544332211ULL; + uint64_t target_memory = 0; std::atomic fds_received{0}; std::atomic in_handle_after{-2}; std::atomic notifier_cloexec{-1}; @@ -971,11 +1609,13 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { std::jthread server([&, server_fd = sv[1]] { for (;;) { rocjitsu::RpcHeader hdr{}; - int in_fds[1] = {-1}; - size_t num_in = 1; + int in_fds[3] = {-1, -1, -1}; + size_t num_in = 3; if (rocjitsu::rpc_recv_msg(server_fd, &hdr, sizeof(hdr), in_fds, &num_in) <= 0) break; int in_fd = (num_in > 0) ? in_fds[0] : -1; + int in_mem_fd = (num_in > 1) ? in_fds[1] : -1; + int in_proc_fd = (num_in > 2) ? in_fds[2] : -1; if (hdr.opcode == rocjitsu::RPC_CLOSE) { rocjitsu::RpcHeader resp{}; @@ -983,6 +1623,10 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { rocjitsu::rpc_send_exact(server_fd, &resp, sizeof(resp)); if (in_fd >= 0) ::close(in_fd); + if (in_mem_fd >= 0) + ::close(in_mem_fd); + if (in_proc_fd >= 0) + ::close(in_proc_fd); break; } if (hdr.opcode != rocjitsu::RPC_IOCTL) { @@ -991,6 +1635,10 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { rocjitsu::rpc_send_exact(server_fd, &resp, sizeof(resp)); if (in_fd >= 0) ::close(in_fd); + if (in_mem_fd >= 0) + ::close(in_mem_fd); + if (in_proc_fd >= 0) + ::close(in_proc_fd); continue; } @@ -998,6 +1646,10 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { if (!rocjitsu::rpc_recv_exact(server_fd, payload.data(), hdr.payload_bytes)) { if (in_fd >= 0) ::close(in_fd); + if (in_mem_fd >= 0) + ::close(in_mem_fd); + if (in_proc_fd >= 0) + ::close(in_proc_fd); break; } auto *ireq = reinterpret_cast(payload.data()); @@ -1005,7 +1657,7 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { // Prove the received descriptor is live and aliases the client's eventfd // by writing a sentinel through it before the handler adopts it. if (in_fd >= 0) { - fds_received.fetch_add(1); + fds_received.store(static_cast(num_in)); // rpc_recv_msg passes MSG_CMSG_CLOEXEC, so the transferred notifier must // arrive close-on-exec and cannot leak through a later exec. int fd_flags = ::fcntl(in_fd, F_GETFD); @@ -1013,6 +1665,11 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { uint64_t s = kSentinel; [[maybe_unused]] ssize_t w = ::write(in_fd, &s, sizeof(s)); } + if (in_mem_fd >= 0) { + [[maybe_unused]] ssize_t w = + ::pwrite(in_mem_fd, &kMemorySentinel, sizeof(kMemorySentinel), + static_cast(reinterpret_cast(&target_memory))); + } rj_vm_cmd_t cmd{}; cmd.cmd = ireq->ioctl_cmd; @@ -1020,10 +1677,16 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { cmd.buf_size = ireq->args_bytes; cmd.shared_handle = -1; cmd.in_handle = in_fd; + cmd.in_mem_handle = in_mem_fd; + cmd.in_proc_handle = in_proc_fd; rj_vm_execute_as(vm_, process_id_, &cmd); in_handle_after.store(cmd.in_handle); if (cmd.in_handle >= 0) ::close(cmd.in_handle); + if (cmd.in_mem_handle >= 0) + ::close(cmd.in_mem_handle); + if (cmd.in_proc_handle >= 0) + ::close(cmd.in_proc_handle); rocjitsu::RpcHeader resp{}; resp.opcode = rocjitsu::RPC_IOCTL; @@ -1050,8 +1713,9 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { en.enable.dbg_fd = static_cast(notifier); ASSERT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &en), 0); - // The client sent exactly one fd via SCM_RIGHTS and the session adopted it. - EXPECT_EQ(fds_received.load(), 1); + // The client sent the notifier, target memory and pinned proc directory; the + // session adopted the first two and the transport reclaimed the identity fd. + EXPECT_EQ(fds_received.load(), 3); EXPECT_EQ(in_handle_after.load(), -1); // The transferred notifier was received close-on-exec (MSG_CMSG_CLOEXEC), so // it cannot leak through a later exec in the daemon. @@ -1063,6 +1727,7 @@ TEST_F(DbgTrapDaemonTest, EnableSendsNotifierFdOverScmRights) { ASSERT_EQ(::read(notifier, &got, sizeof(got)), static_cast(sizeof(got))) << "notifier fd was not transferred: " << strerror(errno); EXPECT_EQ(got, kSentinel); + EXPECT_EQ(target_memory, kMemorySentinel); // Release the adopted fd through the transport for symmetry. kfd_ioctl_dbg_trap_args dis{}; @@ -1236,7 +1901,172 @@ TEST_F(DbgTrapDaemonTest, DeviceSnapshotDispatchMatchesTheLocalContract) { EXPECT_EQ(disable(), 0); } -// --- RemoteDriver DBG_TRAP GET_DEVICE_SNAPSHOT response copy-back --- +// GET_QUEUE_SNAPSHOT through the same production daemon dispatch, over the +// cases the local path pins: a live queue's metadata reconstructed into the +// inline tail, a null buffer with queues to report, and a request that declares +// entries but carries no tail for them. +TEST_F(DbgTrapDaemonTest, QueueSnapshotReconstructsInlineBufferAndValidatesErrors) { + kfd_ioctl_create_queue_args queue{}; + queue.gpu_id = kGpuId; + queue.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + queue.ring_base_address = 0x100000; + queue.ring_size = 4096; + queue.read_pointer_address = 0x200000; + queue.write_pointer_address = 0x200040; + queue.ctx_save_restore_address = 0x300000; + queue.ctx_save_restore_size = 0x8000; + ASSERT_EQ(execute(AMDKFD_IOC_CREATE_QUEUE, &queue, sizeof(queue), -1, nullptr), 0); + + int notifier = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(notifier, 0); + ASSERT_EQ(enable_with_notifier(notifier, nullptr), 0); + + std::array payload{}; + auto *snap = reinterpret_cast(payload.data()); + snap->pid = static_cast(kClientPid); + snap->op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap->queue_snapshot.num_queues = 1; + snap->queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + snap->queue_snapshot.snapshot_buf_ptr = 0xDEADBEEF; // daemon must replace this client pointer + ASSERT_EQ(execute(AMDKFD_IOC_DBG_TRAP, payload.data(), payload.size(), -1, nullptr), 0); + + const auto *entry = reinterpret_cast( + payload.data() + sizeof(kfd_ioctl_dbg_trap_args)); + EXPECT_EQ(snap->queue_snapshot.num_queues, 1u); + EXPECT_EQ(entry->queue_id, queue.queue_id); + EXPECT_EQ(entry->gpu_id, kGpuId); + EXPECT_EQ(entry->ctx_save_restore_address, queue.ctx_save_restore_address); + EXPECT_EQ(entry->exception_status, KFD_EC_MASK(EC_QUEUE_NEW)); + + // A null buffer survives reconstruction (rj_vm.cpp only repoints a non-null + // one), so the driver sees the null the caller sent. With a queue to report + // and nowhere to put it that is -EFAULT, and nothing is written. + constexpr uint8_t kSentinel = 0xAB; + std::array + null_queue_payload; + null_queue_payload.fill(kSentinel); + auto *null_queue = reinterpret_cast(null_queue_payload.data()); + *null_queue = {}; + null_queue->pid = static_cast(kClientPid); + null_queue->op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + null_queue->queue_snapshot.num_queues = 1; + null_queue->queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + ASSERT_EQ(execute(AMDKFD_IOC_DBG_TRAP, null_queue_payload.data(), null_queue_payload.size(), -1, + nullptr), + -EFAULT); + EXPECT_EQ(null_queue->queue_snapshot.snapshot_buf_ptr, 0u); + EXPECT_TRUE(std::all_of(null_queue_payload.begin() + sizeof(kfd_ioctl_dbg_trap_args), + null_queue_payload.end(), + [](uint8_t byte) { return byte == kSentinel; })); + + // The device op reaches the same null the same way, but answers it with + // -EINVAL: kfd_dbg_trap_device_snapshot() validates the buffer before writing + // any output, which is what DeviceSnapshotDispatchMatchesTheLocalContract and + // DbgTrapDeviceSnapshotRejectsNullBufferWithoutWritingOutputs pin. The two ops + // differ here because the drivers they mirror do. + std::array + null_device_payload; + null_device_payload.fill(kSentinel); + auto *null_device = reinterpret_cast(null_device_payload.data()); + *null_device = {}; + null_device->pid = static_cast(kClientPid); + null_device->op = KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT; + null_device->device_snapshot.num_devices = 1; + null_device->device_snapshot.entry_size = sizeof(kfd_dbg_device_info_entry); + ASSERT_EQ(execute(AMDKFD_IOC_DBG_TRAP, null_device_payload.data(), null_device_payload.size(), -1, + nullptr), + -EINVAL); + EXPECT_EQ(null_device->device_snapshot.snapshot_buf_ptr, 0u); + EXPECT_EQ(null_device->device_snapshot.num_devices, 1u) + << "a rejected request must not report a device total"; + EXPECT_EQ(null_device->device_snapshot.entry_size, sizeof(kfd_dbg_device_info_entry)); + EXPECT_TRUE(std::all_of(null_device_payload.begin() + sizeof(kfd_ioctl_dbg_trap_args), + null_device_payload.end(), + [](uint8_t byte) { return byte == kSentinel; })); + + // Entries declared with no tail to hold them: the payload is one arg struct + // short of what num_queues * entry_size demands, so the request is malformed. + kfd_ioctl_dbg_trap_args missing_inline{}; + missing_inline.pid = static_cast(kClientPid); + missing_inline.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + missing_inline.queue_snapshot.num_queues = 1; + missing_inline.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + EXPECT_EQ(execute(AMDKFD_IOC_DBG_TRAP, &missing_inline, sizeof(missing_inline), -1, nullptr), + -EINVAL); + + kfd_ioctl_destroy_queue_args destroy{}; + destroy.queue_id = queue.queue_id; + EXPECT_EQ(execute(AMDKFD_IOC_DESTROY_QUEUE, &destroy, sizeof(destroy), -1, nullptr), 0); + EXPECT_EQ(disable(), 0); +} + +TEST_F(DbgTrapDaemonTest, QueueControlReconstructsRequestedIdsAndReportsInvalidQueues) { + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(execute(AMDKFD_IOC_RUNTIME_ENABLE, &runtime, sizeof(runtime), -1, nullptr), 0); + + kfd_ioctl_create_queue_args queue{}; + queue.gpu_id = kGpuId; + queue.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + queue.ring_base_address = 0x100000; + queue.ring_size = 4096; + queue.read_pointer_address = 0x200000; + queue.write_pointer_address = 0x200040; + queue.ctx_save_restore_address = 0x300000; + queue.ctx_save_restore_size = 0x8000; + ASSERT_EQ(execute(AMDKFD_IOC_CREATE_QUEUE, &queue, sizeof(queue), -1, nullptr), 0); + + int notifier = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(notifier, 0); + ASSERT_EQ(enable_with_notifier(notifier, nullptr), 0); + + // Clear EC_QUEUE_NEW; real KFD rejects suspension until the debugger has + // observed and cleared that queue lifecycle event. + std::array + snapshot_payload{}; + auto *snapshot = reinterpret_cast(snapshot_payload.data()); + snapshot->pid = static_cast(kClientPid); + snapshot->op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot->queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + snapshot->queue_snapshot.num_queues = 1; + snapshot->queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + snapshot->queue_snapshot.snapshot_buf_ptr = 1; + ASSERT_EQ( + execute(AMDKFD_IOC_DBG_TRAP, snapshot_payload.data(), snapshot_payload.size(), -1, nullptr), + 0); + + constexpr uint32_t kMissingQueue = 0x1234; + constexpr uint32_t kInvalid = uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT; + std::array suspend_payload{}; + auto *suspend = reinterpret_cast(suspend_payload.data()); + suspend->pid = static_cast(kClientPid); + suspend->op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + suspend->suspend_queues.queue_array_ptr = 1; + suspend->suspend_queues.num_queues = 2; + auto *suspend_ids = reinterpret_cast(suspend_payload.data() + sizeof(*suspend)); + suspend_ids[0] = queue.queue_id; + suspend_ids[1] = kMissingQueue; + EXPECT_EQ( + execute(AMDKFD_IOC_DBG_TRAP, suspend_payload.data(), suspend_payload.size(), -1, nullptr), 1); + EXPECT_EQ(suspend_ids[0], queue.queue_id); + EXPECT_EQ(suspend_ids[1], kMissingQueue | kInvalid); + + std::array resume_payload{}; + auto *resume = reinterpret_cast(resume_payload.data()); + resume->pid = static_cast(kClientPid); + resume->op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + resume->resume_queues.queue_array_ptr = 1; + resume->resume_queues.num_queues = 1; + auto *resume_id = reinterpret_cast(resume_payload.data() + sizeof(*resume)); + *resume_id = queue.queue_id; + EXPECT_EQ(execute(AMDKFD_IOC_DBG_TRAP, resume_payload.data(), resume_payload.size(), -1, nullptr), + 1); + EXPECT_EQ(*resume_id, queue.queue_id); + + EXPECT_EQ(disable(), 0); +} + +// --- RemoteDriver DBG_TRAP snapshot response copy-back --- // // The client saves the caller's snapshot buffer pointer and capacity // (num_devices * entry_size) before serialization, then on the response only @@ -1304,6 +2134,56 @@ void serve_one_ioctl_reply(int server_fd, int32_t result, size_t arg_struct_size rocjitsu::rpc_send_exact(server_fd, out.data(), out.size()); } +TEST(RemoteDriverDbgQueueControlTest, QueueIdsAndStatusBitsRoundTripInline) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); + + constexpr uint32_t kInvalid = uint32_t{1} << KFD_DBG_QUEUE_INVALID_BIT; + std::array observed{}; + std::jthread server([&, server_fd = sv[1]] { + rocjitsu::RpcHeader header{}; + int received_fds[1] = {-1}; + size_t num_fds = 1; + ASSERT_GT(rocjitsu::rpc_recv_msg(server_fd, &header, sizeof(header), received_fds, &num_fds), + 0); + std::vector request(header.payload_bytes); + ASSERT_TRUE(rocjitsu::rpc_recv_exact(server_fd, request.data(), request.size())); + ASSERT_GE(request.size(), sizeof(rocjitsu::RpcIoctlRequest) + sizeof(kfd_ioctl_dbg_trap_args) + + sizeof(observed)); + auto *args = request.data() + sizeof(rocjitsu::RpcIoctlRequest); + std::memcpy(observed.data(), args + sizeof(kfd_ioctl_dbg_trap_args), sizeof(observed)); + + std::vector response(sizeof(kfd_ioctl_dbg_trap_args) + sizeof(observed)); + std::memcpy(response.data(), args, response.size()); + auto *returned_ids = + reinterpret_cast(response.data() + sizeof(kfd_ioctl_dbg_trap_args)); + returned_ids[1] |= kInvalid; + rocjitsu::RpcHeader response_header{}; + response_header.opcode = rocjitsu::RPC_IOCTL; + response_header.request_id = header.request_id; + response_header.payload_bytes = static_cast(response.size()); + response_header.result = 1; + ASSERT_TRUE(rocjitsu::rpc_send_exact(server_fd, &response_header, sizeof(response_header))); + ASSERT_TRUE(rocjitsu::rpc_send_exact(server_fd, response.data(), response.size())); + ::close(server_fd); + }); + + rocjitsu::RemoteDriver driver(sv[0]); + std::array queue_ids{7, 9}; + kfd_ioctl_dbg_trap_args suspend{}; + suspend.pid = 4242; + suspend.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + suspend.suspend_queues.queue_array_ptr = reinterpret_cast(queue_ids.data()); + suspend.suspend_queues.num_queues = queue_ids.size(); + const uint64_t original_pointer = suspend.suspend_queues.queue_array_ptr; + + EXPECT_EQ(driver.ioctl(AMDKFD_IOC_DBG_TRAP, &suspend), 1); + EXPECT_EQ(observed, (std::array{7, 9})); + EXPECT_EQ(queue_ids, (std::array{7, 9 | kInvalid})); + EXPECT_EQ(suspend.suspend_queues.queue_array_ptr, original_pointer); + server.join(); +} + // A GET_DEVICE_SNAPSHOT that the daemon fails (result != 0) must not copy the // response tail into the caller's snapshot buffer, even though the daemon // returned inline bytes. @@ -1551,6 +2431,41 @@ TEST(RemoteDriverDbgSnapshotTest, StrideWiderThanThePayloadLimitStillFillsEntrie // UINT32_MAX * sizeof(kfd_dbg_device_info_entry) (~480 GiB) and kills the // process on std::bad_alloc. The request must be clamped to what the transport // can carry, and the reply must still land in the caller's buffer. +// Snapshot requests are clamped to the payload ceiling, but QUERY_EXCEPTION_INFO +// takes info_size straight from the caller and SUSPEND/RESUME derive their tail +// from num_queues. Those three were bounded only by UINT32_MAX, so a malformed +// ioctl could drive a multi-gigabyte resize() and a copy out of the caller's +// buffer before the frame was ever sent -- the daemon's 16 MiB limit is checked +// on receipt, far too late to matter. They must be refused, not clamped: the +// daemon recomputes the expected tail from the echoed args, so a short tail with +// an unclamped count is a protocol mismatch that drops the connection. +TEST(RemoteDriverDbgTrapTest, OversizedInlineTailIsRefusedBeforeAllocating) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); + const CloseOnScopeExit server_closer{sv[1]}; + rocjitsu::RemoteDriver rd(sv[0]); + + // Nothing is served: a request this size must be rejected locally, so the + // call cannot block waiting for a reply. + kfd_ioctl_dbg_trap_args info{}; + info.pid = 4242; + info.op = KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO; + info.query_exception_info.info_size = 3u * 1024u * 1024u * 1024u; // 3 GiB + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &info), -E2BIG); + + kfd_ioctl_dbg_trap_args suspend{}; + suspend.pid = 4242; + suspend.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + suspend.suspend_queues.num_queues = 0x4000'0000u; // * 4 bytes = 4 GiB + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &suspend), -E2BIG); + + kfd_ioctl_dbg_trap_args resume{}; + resume.pid = 4242; + resume.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + resume.resume_queues.num_queues = 0x4000'0000u; + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &resume), -E2BIG); +} + TEST(RemoteDriverDbgSnapshotTest, OversizedSnapshotRequestIsClampedToPayloadLimit) { int sv[2]; ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); @@ -1734,71 +2649,279 @@ TEST(RemoteDriverDbgSnapshotTest, SuccessfulSnapshotLeavesUnfilledEntriesAndPadd server.join(); } -// A closed but positive notifier fd cannot be transferred over SCM_RIGHTS: -// sendmsg() rejects it with EBADF at the client. send_ioctl() must surface that -// errno so the interposer reports EBADF, not the EPERM a bare -1 becomes -// (-EPERM == -1). -TEST(RemoteDriverDbgNotifierTest, EnableWithClosedNotifierFdPreservesEbadf) { +// The queue op rides the same request clamp and strided copy-back as the device +// op; these pin the parts where its contract differs. + +// A failed op must not touch the caller's buffer, exactly as it must not for +// the device op -- the reply's tail is ignored entirely. +TEST(RemoteDriverDbgQueueSnapshotTest, FailedSnapshotLeavesCallerBufferUntouched) { int sv[2]; ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); + constexpr uint32_t kRequested = 2; + constexpr uint32_t kEntryBytes = sizeof(kfd_queue_snapshot_entry); + constexpr size_t kCap = 2 * kEntryBytes; + constexpr uint8_t kSentinel = 0xAB; + + std::array caller_buf; + caller_buf.fill(kSentinel); + std::jthread server([&, server_fd = sv[1]] { + const CloseOnScopeExit closer{server_fd}; + serve_one_ioctl_reply(server_fd, -EFAULT, sizeof(kfd_ioctl_dbg_trap_args), kCap, 0xCD); + }); + rocjitsu::RemoteDriver rd(sv[0]); + kfd_ioctl_dbg_trap_args snap{}; + snap.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap.queue_snapshot.num_queues = kRequested; + snap.queue_snapshot.entry_size = kEntryBytes; + snap.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(caller_buf.data()); + + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &snap), -EFAULT); + EXPECT_TRUE(std::all_of(caller_buf.begin(), caller_buf.end(), + [](uint8_t byte) { return byte == kSentinel; })); + // A failed op leaves the caller's own inputs in place rather than the wire + // values the request clamp wrote over them. + EXPECT_EQ(snap.queue_snapshot.num_queues, kRequested); + EXPECT_EQ(snap.queue_snapshot.entry_size, kEntryBytes); + server.join(); +} - // A positive fd number that is already closed: a valid-looking dbg_fd the - // SCM_RIGHTS send must reject. Allocated after the driver so its fd number is - // not reused by the driver's internal eventfd before the send. - int dead_fd = ::eventfd(0, EFD_CLOEXEC); - ASSERT_GE(dead_fd, 0); - ASSERT_EQ(::close(dead_fd), 0); +// Unlike the device op, a null output buffer is not rejected on the request +// path: the local path answers it with success when there are no queues to +// report (SimulatedKfd::debug_queue_snapshot), and the client cannot know that +// before it asks. So the request goes out, and the verdict is reconstructed +// from the queue total that comes back. +TEST(RemoteDriverDbgQueueSnapshotTest, SuccessfulReplyWithNullBufferReturnsEfault) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); - kfd_ioctl_dbg_trap_args en{}; - en.pid = 4242; - en.op = KFD_IOC_DBG_TRAP_ENABLE; - en.enable.dbg_fd = static_cast(dead_fd); + constexpr size_t kCap = sizeof(kfd_queue_snapshot_entry); + std::jthread server([&, server_fd = sv[1]] { + const CloseOnScopeExit closer{server_fd}; + serve_one_ioctl_reply(server_fd, 0, sizeof(kfd_ioctl_dbg_trap_args), kCap, 0xCD); + }); - // The transport rejects the closed fd; the caller must see EBADF, not the bare - // -1 that would surface as EPERM. - EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &en), -EBADF); + rocjitsu::RemoteDriver rd(sv[0]); + kfd_ioctl_dbg_trap_args snap{}; + snap.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap.queue_snapshot.num_queues = 1; + snap.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); - ::close(sv[1]); + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &snap), -EFAULT); + EXPECT_EQ(snap.queue_snapshot.snapshot_buf_ptr, 0u); + server.join(); } -// A daemon-path ENABLE that the daemon fails (result != 0) must not copy the -// response tail into the caller's runtime-info buffer, even though the daemon -// returned inline bytes. Mirrors the GET_DEVICE_SNAPSHOT success gate: a -// rejected notifier fd (-EBADF) leaves caller memory untouched, as local mode does. -TEST(RemoteDriverDbgEnableTest, FailedEnableLeavesCallerRuntimeInfoUntouched) { +// A null buffer with nothing to report is success, not -EFAULT: that is the +// count-only probe, and it is how a debugger learns how large a buffer to +// allocate. Pinning it alongside the case above is what keeps the -EFAULT +// synthesis conditional on the returned total rather than on the null alone. +TEST(RemoteDriverDbgQueueSnapshotTest, NullBufferWithNoQueuesIsTheCountProbe) { int sv[2]; ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); - constexpr size_t kRinfoSize = sizeof(kfd_runtime_info); + std::jthread server([&, server_fd = sv[1]] { + const CloseOnScopeExit closer{server_fd}; + // A daemon whose process owns no queues: the total comes back zero. + serve_one_ioctl_reply(server_fd, 0, sizeof(kfd_ioctl_dbg_trap_args), 0, 0, + [](const rocjitsu::RpcHeader &, kfd_ioctl_dbg_trap_args &echoed) { + echoed.queue_snapshot.num_queues = 0; + }); + }); + + rocjitsu::RemoteDriver rd(sv[0]); + kfd_ioctl_dbg_trap_args snap{}; + snap.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap.queue_snapshot.num_queues = 1; + snap.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + EXPECT_EQ(snap.queue_snapshot.num_queues, 0u); + server.join(); +} + +// The caller's stride is wider than the entry struct, so the tail arrives packed +// at the struct and has to be scattered into the caller's wider slots. Anything +// past the entries the daemon reported -- including the padding inside the one +// slot that is filled -- stays as the caller left it. +TEST(RemoteDriverDbgQueueSnapshotTest, SuccessfulSnapshotScattersIntoTheCallerStride) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); + + constexpr uint32_t kEntryBytes = sizeof(kfd_queue_snapshot_entry); + constexpr uint32_t kStride = kEntryBytes + 16; + constexpr size_t kGuard = 32; constexpr uint8_t kSentinel = 0xAB; constexpr uint8_t kPoison = 0xCD; - const size_t arg_struct_size = sizeof(kfd_ioctl_dbg_trap_args); - - std::vector caller_buf(kRinfoSize, kSentinel); + std::array caller_buf; + caller_buf.fill(kSentinel); std::jthread server([&, server_fd = sv[1]] { - serve_one_ioctl_reply(server_fd, -EBADF, arg_struct_size, kRinfoSize, kPoison); - ::close(server_fd); + const CloseOnScopeExit closer{server_fd}; + // The client transmits the compact stride, so the daemon lays its one entry + // down at kEntryBytes and reports that as entry_size(OUT). + serve_one_ioctl_reply(server_fd, 0, sizeof(kfd_ioctl_dbg_trap_args), kEntryBytes, kPoison, + [](const rocjitsu::RpcHeader &, kfd_ioctl_dbg_trap_args &echoed) { + // Spelled out rather than reaching for kEntryBytes: inside the + // enclosing [&] lambda that name is a captured reference, which + // gcc then demands this lambda capture too and clang rejects as + // an unnecessary capture. + echoed.queue_snapshot.num_queues = 1; + echoed.queue_snapshot.entry_size = + static_cast(sizeof(kfd_queue_snapshot_entry)); + }); }); rocjitsu::RemoteDriver rd(sv[0]); + kfd_ioctl_dbg_trap_args snap{}; + snap.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap.queue_snapshot.num_queues = 1; + snap.queue_snapshot.entry_size = kStride; + snap.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(caller_buf.data()); - // A valid notifier fd so the SCM_RIGHTS send succeeds and the request reaches - // the daemon, which then fails the op with -EBADF. Allocated after the driver - // so its fd number is not reused by the driver's internal eventfd. - int notifier_fd = ::eventfd(0, EFD_CLOEXEC); - ASSERT_GE(notifier_fd, 0); + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + EXPECT_TRUE(std::all_of(caller_buf.begin(), caller_buf.begin() + kEntryBytes, [](uint8_t byte) { + return byte == kPoison; + })) << "the entry did not reach the caller's buffer"; + EXPECT_TRUE(std::all_of(caller_buf.begin() + kEntryBytes, caller_buf.end(), [](uint8_t byte) { + return byte == kSentinel; + })) << "copy-back wrote past the one entry the daemon returned"; + server.join(); +} - kfd_ioctl_dbg_trap_args en{}; - en.pid = 4242; - en.op = KFD_IOC_DBG_TRAP_ENABLE; - en.enable.dbg_fd = static_cast(notifier_fd); - en.enable.rinfo_size = static_cast(kRinfoSize); - en.enable.rinfo_ptr = reinterpret_cast(caller_buf.data()); +// rocdbgapi asks for UINT32_MAX queues the same way libhsakmt asks for +// UINT32_MAX devices, and for the same reason: let the driver report the true +// total. The request clamp has to bound the queue op too, or serializing that +// count reserves a tail no allocator will hand out. +TEST(RemoteDriverDbgQueueSnapshotTest, OversizedRequestIsClampedToPayloadLimit) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); - EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &en), -EBADF); + constexpr uint32_t kEntryBytes = sizeof(kfd_queue_snapshot_entry); + constexpr uint32_t kActualQueues = 1; + constexpr size_t kGuard = 32; + constexpr uint8_t kSentinel = 0xAB; + constexpr uint8_t kPoison = 0xCD; + + std::vector caller_buf(kEntryBytes + kGuard, kSentinel); + std::atomic observed_payload_bytes{0}; + std::atomic observed_num_queues{0}; + + std::jthread server([&, server_fd = sv[1]] { + const CloseOnScopeExit closer{server_fd}; + serve_one_ioctl_reply(server_fd, 0, sizeof(kfd_ioctl_dbg_trap_args), kEntryBytes, kPoison, + [&](const rocjitsu::RpcHeader &request, kfd_ioctl_dbg_trap_args &echoed) { + observed_payload_bytes = request.payload_bytes; + observed_num_queues = echoed.queue_snapshot.num_queues; + echoed.queue_snapshot.num_queues = kActualQueues; + echoed.queue_snapshot.entry_size = kEntryBytes; + }); + }); + + rocjitsu::RemoteDriver rd(sv[0]); + kfd_ioctl_dbg_trap_args snap{}; + snap.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap.queue_snapshot.num_queues = std::numeric_limits::max(); + snap.queue_snapshot.entry_size = kEntryBytes; + snap.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(caller_buf.data()); + + ASSERT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + server.join(); + + EXPECT_LE(observed_payload_bytes.load(), rocjitsu::kMaxPayloadBytes) + << "request exceeded the payload limit the daemon enforces"; + EXPECT_LT(observed_num_queues.load(), std::numeric_limits::max()) + << "UINT32_MAX queue count was transmitted verbatim"; + EXPECT_GT(observed_num_queues.load(), 1000u); + + EXPECT_EQ(snap.queue_snapshot.num_queues, kActualQueues) << "true queue total not reported"; + EXPECT_TRUE(std::all_of(caller_buf.begin(), caller_buf.begin() + kEntryBytes, [](uint8_t byte) { + return byte == kPoison; + })) << "the enumerated entry did not reach the caller"; + EXPECT_TRUE(std::all_of(caller_buf.begin() + kEntryBytes, caller_buf.end(), [](uint8_t byte) { + return byte == kSentinel; + })) << "copy-back wrote past the entries the daemon returned"; +} + +// A closed but positive notifier fd cannot be transferred over SCM_RIGHTS: +// sendmsg() rejects it with EBADF at the client. send_ioctl() must surface that +// errno so the interposer reports EBADF, not the EPERM a bare -1 becomes +// (-EPERM == -1). +TEST(RemoteDriverDbgNotifierTest, EnableWithClosedNotifierFdPreservesEbadf) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); + + rocjitsu::RemoteDriver rd(sv[0]); + + // A positive fd number that is already closed: a valid-looking dbg_fd the + // SCM_RIGHTS send must reject. Allocated after the driver so its fd number is + // not reused by the driver's internal eventfd before the send. + // + // Park it far above the lowest-free-fd range first. open() hands out the + // lowest free descriptor, so a plain close() leaves this number first in line: + // anything else in the process that opens a descriptor between here and the + // send below takes it, the send then succeeds, and the test stops testing + // what it is named for -- it reports whatever the daemon path answers instead, + // and can block waiting for a reply that no one is serving. + int dead_fd = ::eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dead_fd, 0); + constexpr int kParkedFdBase = 4096; + const int parked_fd = ::fcntl(dead_fd, F_DUPFD_CLOEXEC, kParkedFdBase); + if (parked_fd >= 0) { + ASSERT_EQ(::close(dead_fd), 0); + dead_fd = parked_fd; + } + ASSERT_EQ(::close(dead_fd), 0); + + kfd_ioctl_dbg_trap_args en{}; + en.pid = 4242; + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dead_fd); + + // The transport rejects the closed fd; the caller must see EBADF, not the bare + // -1 that would surface as EPERM. + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &en), -EBADF); + + ::close(sv[1]); +} + +// A daemon-path ENABLE that the daemon fails (result != 0) must not copy the +// response tail into the caller's runtime-info buffer, even though the daemon +// returned inline bytes. Mirrors the GET_DEVICE_SNAPSHOT success gate: a +// rejected notifier fd (-EBADF) leaves caller memory untouched, as local mode does. +TEST(RemoteDriverDbgEnableTest, FailedEnableLeavesCallerRuntimeInfoUntouched) { + int sv[2]; + ASSERT_EQ(::socketpair(AF_UNIX, SOCK_STREAM, 0, sv), 0) << ::strerror(errno); + + constexpr size_t kRinfoSize = sizeof(kfd_runtime_info); + constexpr uint8_t kSentinel = 0xAB; + constexpr uint8_t kPoison = 0xCD; + const size_t arg_struct_size = sizeof(kfd_ioctl_dbg_trap_args); + + std::vector caller_buf(kRinfoSize, kSentinel); + + std::jthread server([&, server_fd = sv[1]] { + serve_one_ioctl_reply(server_fd, -EBADF, arg_struct_size, kRinfoSize, kPoison); + ::close(server_fd); + }); + + rocjitsu::RemoteDriver rd(sv[0]); + + // A valid notifier fd so the SCM_RIGHTS send succeeds and the request reaches + // the daemon, which then fails the op with -EBADF. Allocated after the driver + // so its fd number is not reused by the driver's internal eventfd. + int notifier_fd = ::eventfd(0, EFD_CLOEXEC); + ASSERT_GE(notifier_fd, 0); + + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(getpid()); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(notifier_fd); + en.enable.rinfo_size = static_cast(kRinfoSize); + en.enable.rinfo_ptr = reinterpret_cast(caller_buf.data()); + + EXPECT_EQ(rd.ioctl(AMDKFD_IOC_DBG_TRAP, &en), -EBADF); EXPECT_TRUE(std::all_of(caller_buf.begin(), caller_buf.end(), [](uint8_t b) { return b == kSentinel; })) << "failed ENABLE mutated caller runtime-info memory"; @@ -2310,6 +3433,84 @@ TEST_F(KfdIoctlTest, DbgTrapDeviceSnapshotEnumeratesOnlyDescribableDevices) { } } +// The simulator services a debugger by writing a CWSR record rocm-dbgapi parses +// out of /proc//mem, so an agent it cannot produce a record for is not +// debuggable no matter what the driver would advertise for that part. The +// support bit is what rocdbgapi keys agent_t::supports_debugging() on, so +// withholding it declines at attach instead of at every individual wave stop. +TEST(KfdTopologyTest, TrapDebugSupportTracksTheModelledCwsrLayouts) { + struct Part { + uint32_t gfx_target_version; + const char *name; + }; + // Every part the arch-keyed predicate accepts, and a representative spread of + // the ones it does not: an older gfx9, an RDNA3 and the newest gfx12. + constexpr Part kModelled[] = {{90402u, "gfx942"}, {90500u, "gfx950"}}; + constexpr Part kUnmodelled[] = {{90010u, "gfx90a"}, {110000u, "gfx1100"}, {120500u, "gfx1250"}}; + + for (const Part &part : kModelled) { + const rocjitsu::kmd::DebugTopology topology = + rocjitsu::kmd::effective_topology_for(part.gfx_target_version, 0, 0, 0, 0); + EXPECT_NE(topology.capability & HSA_CAP_TRAP_DEBUG_SUPPORT, 0u) << part.name; + EXPECT_TRUE(rocjitsu::kmd::cwsr_layout_modelled_for_gc_ip_version( + rocjitsu::kmd::gc_ip_version_for_gfx_target_version(part.gfx_target_version))) + << part.name; + } + + for (const Part &part : kUnmodelled) { + const rocjitsu::kmd::DebugTopology topology = + rocjitsu::kmd::effective_topology_for(part.gfx_target_version, 0, 0, 0, 0); + EXPECT_EQ(topology.capability & HSA_CAP_TRAP_DEBUG_SUPPORT, 0u) << part.name; + // Only that one bit is withheld: the node still describes the device the + // driver would, so a non-debug consumer sees no difference. + EXPECT_NE(topology.capability & HSA_CAP_ATS_PRESENT, 0u) << part.name; + EXPECT_NE(topology.capability & HSA_CAP_WATCH_POINTS_SUPPORTED, 0u) << part.name; + EXPECT_NE(topology.debug_prop, 0u) << part.name; + } +} + +// The two predicates name the same set through different identities, so a part +// added to one and not the other would silently re-open the gap above. +TEST(KfdTopologyTest, ArchAndGcSpellingsOfTheCwsrGateAgree) { + struct Part { + rj_code_arch_t arch; + uint32_t gfx_target_version; + const char *name; + }; + constexpr Part kParts[] = { + {ROCJITSU_CODE_ARCH_CDNA1, 90002u, "gfx908"}, + {ROCJITSU_CODE_ARCH_CDNA2, 90010u, "gfx90a"}, + {ROCJITSU_CODE_ARCH_CDNA3, 90402u, "gfx942"}, + {ROCJITSU_CODE_ARCH_CDNA4, 90500u, "gfx950"}, + {ROCJITSU_CODE_ARCH_RDNA3, 110000u, "gfx1100"}, + {ROCJITSU_CODE_ARCH_RDNA4, 120000u, "gfx1200"}, + }; + + for (const Part &part : kParts) + EXPECT_EQ(rocjitsu::kmd::cwsr_layout_modelled(part.arch), + rocjitsu::kmd::cwsr_layout_modelled_for_gc_ip_version( + rocjitsu::kmd::gc_ip_version_for_gfx_target_version(part.gfx_target_version))) + << part.name; +} + +// A config may capture a real device's capability word, which carries that +// device's trap-debug bit. Inheriting it would restore exactly the mismatch the +// derived gate closes. +TEST(KfdTopologyTest, CapturedCapabilityCannotReadvertiseUnservicableTrapDebug) { + const uint32_t captured = rocjitsu::kmd::default_non_debug_capability() | + HSA_CAP_TRAP_DEBUG_SUPPORT | HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED; + + const rocjitsu::kmd::DebugTopology unmodelled = + rocjitsu::kmd::effective_topology_for(110000u, captured, 0, 0, 0); + EXPECT_EQ(unmodelled.capability & HSA_CAP_TRAP_DEBUG_SUPPORT, 0u); + EXPECT_NE(unmodelled.capability & HSA_CAP_ATS_PRESENT, 0u) << "the override was discarded"; + + // The same captured word on a part the codec does model passes through. + const rocjitsu::kmd::DebugTopology modelled = + rocjitsu::kmd::effective_topology_for(90500u, captured, 0, 0, 0); + EXPECT_NE(modelled.capability & HSA_CAP_TRAP_DEBUG_SUPPORT, 0u); +} + TEST(KfdTopologyTest, EffectiveTopologyDerivesGfx121Capability2) { const rocjitsu::kmd::DebugTopology topology = rocjitsu::kmd::effective_topology_for(120100u, 0, 0, 0, 0); @@ -2318,4 +3519,1652 @@ TEST(KfdTopologyTest, EffectiveTopologyDerivesGfx121Capability2) { EXPECT_NE(topology.capability2 & HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED, 0u); } +// rocm-dbgapi enumerates the target's compute queues to locate each queue's +// CWSR area (from which it walks wave save state). GET_QUEUE_SNAPSHOT must +// report the ctx_save_restore address/size captured at CREATE_QUEUE. +TEST_F(KfdIoctlTest, DbgTrapQueueSnapshotEnumeratesQueues) { + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(getpid()); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = make_debug_fd(); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &en), 0); + + // No queues yet: the count call reports zero. + kfd_ioctl_dbg_trap_args count0{}; + count0.pid = static_cast(getpid()); + count0.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + count0.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &count0), 0); + EXPECT_EQ(count0.queue_snapshot.num_queues, 0u); + + kfd_ioctl_dbg_trap_args zero_size{}; + zero_size.pid = static_cast(getpid()); + zero_size.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &zero_size), -EINVAL); + + // Create two compute queues with distinct geometry. + std::vector ring1(4096, 0), ring2(8192, 0), rw(4096, 0); + constexpr uint64_t kCwsrVa = 0x123400000ULL; + constexpr uint32_t kCwsrSize = 0x8000; + kfd_ioctl_create_queue_args q1{}; + q1.gpu_id = kGpuId; + q1.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + q1.ring_base_address = reinterpret_cast(ring1.data()); + q1.ring_size = static_cast(ring1.size()); + q1.read_pointer_address = reinterpret_cast(rw.data()); + q1.write_pointer_address = reinterpret_cast(rw.data() + 64); + q1.ctx_save_restore_address = kCwsrVa; + q1.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &q1), 0); + + kfd_ioctl_create_queue_args q2 = q1; + q2.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE; + q2.ring_base_address = reinterpret_cast(ring2.data()); + q2.ring_size = static_cast(ring2.size()); + q2.read_pointer_address = reinterpret_cast(rw.data() + 128); + q2.write_pointer_address = reinterpret_cast(rw.data() + 192); + q2.ctx_save_restore_address += kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &q2), 0); + + // Count reports the total, independent of caller capacity. + kfd_ioctl_dbg_trap_args count1{}; + count1.pid = static_cast(getpid()); + count1.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + count1.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &count1), 0); + ASSERT_EQ(count1.queue_snapshot.num_queues, 2u); + EXPECT_EQ(count1.queue_snapshot.entry_size, sizeof(kfd_queue_snapshot_entry)); + + // A larger input stride is preserved for addressing while entry_size(OUT) is + // clamped. Only one entry is written and the stride tail remains untouched. + constexpr size_t kStride = sizeof(kfd_queue_snapshot_entry) + 16; + std::array partial_buf; + partial_buf.fill(0xA5); + kfd_ioctl_dbg_trap_args snap{}; + snap.pid = static_cast(getpid()); + snap.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snap.queue_snapshot.entry_size = kStride; + snap.queue_snapshot.num_queues = 1; + snap.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(partial_buf.data()); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + EXPECT_EQ(snap.queue_snapshot.num_queues, 2u); + EXPECT_EQ(snap.queue_snapshot.entry_size, sizeof(kfd_queue_snapshot_entry)); + const auto *partial = reinterpret_cast(partial_buf.data()); + EXPECT_EQ(partial->queue_id, q1.queue_id); + EXPECT_TRUE(std::all_of(partial_buf.begin() + sizeof(*partial), partial_buf.end(), + [](uint8_t byte) { return byte == 0xA5; })); + + // UPDATE_QUEUE changes the live ring geometry reported by the kernel ABI. + kfd_ioctl_update_queue_args update{}; + update.queue_id = q1.queue_id; + update.ring_base_address = reinterpret_cast(ring2.data()); + update.ring_size = static_cast(ring2.size()); + update.queue_percentage = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_UPDATE_QUEUE, &update), 0); + uint32_t suspended_queues = 0; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + suspended_queues += + cp->queue_runtime_suspended_for_test(q1.queue_id, driver_->local_process_id()); + }); + EXPECT_EQ(suspended_queues, 1u); + + update.queue_percentage = 100; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_UPDATE_QUEUE, &update), 0); + suspended_queues = 0; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + suspended_queues += + cp->queue_runtime_suspended_for_test(q1.queue_id, driver_->local_process_id()); + }); + EXPECT_EQ(suspended_queues, 0u); + + std::array entries{}; + snap.queue_snapshot.entry_size = sizeof(entries[0]); + snap.queue_snapshot.num_queues = entries.size(); + snap.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(entries.data()); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + const auto &entry = entries[0]; + EXPECT_EQ(entry.queue_id, q1.queue_id); + EXPECT_EQ(entry.gpu_id, kGpuId); + EXPECT_EQ(entry.ctx_save_restore_address, kCwsrVa); + EXPECT_EQ(entry.ctx_save_restore_area_size, kCwsrSize); + EXPECT_EQ(entry.ring_base_address, reinterpret_cast(ring2.data())); + EXPECT_EQ(entry.ring_size, ring2.size()); + EXPECT_EQ(entry.read_pointer_address, q1.read_pointer_address); + EXPECT_EQ(entry.write_pointer_address, q1.write_pointer_address); + EXPECT_EQ(entry.queue_type, static_cast(KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)); + EXPECT_EQ(entry.exception_status, KFD_EC_MASK(EC_QUEUE_NEW)); + EXPECT_EQ(entry.reserved, 0u); + EXPECT_EQ(entries[1].queue_id, q2.queue_id); + EXPECT_EQ(entries[1].queue_type, static_cast(KFD_IOC_QUEUE_TYPE_COMPUTE)); + + snap.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + EXPECT_EQ(entries[0].exception_status, KFD_EC_MASK(EC_QUEUE_NEW)); + snap.queue_snapshot.exception_mask = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + EXPECT_EQ(entries[0].exception_status, 0u); + EXPECT_EQ(entries[1].exception_status, 0u); + + kfd_ioctl_dbg_trap_args null_buffer = snap; + null_buffer.queue_snapshot.snapshot_buf_ptr = 0; + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &null_buffer), -EFAULT); + EXPECT_EQ(null_buffer.queue_snapshot.num_queues, 2u); + + rocjitsu::amdgpu::Wavefront *halted_wave = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (halted_wave != nullptr || cp->compute_units().empty()) + return; + halted_wave = cp->compute_units().front()->dispatch_wf(/*wg_id=*/0, /*pc=*/0x600000000ULL, + /*sgprs=*/16, /*vgprs=*/4); + }); + ASSERT_NE(halted_wave, nullptr); + halted_wave->set_process_id(driver_->local_process_id()); + halted_wave->set_queue_id(q1.queue_id); + halted_wave->set_debug_halted(true); + + // Destroying queues reclaims resident waves and removes their metadata + // without disturbing creation order. + kfd_ioctl_destroy_queue_args dq{}; + dq.queue_id = q1.queue_id; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DESTROY_QUEUE, &dq), 0); + EXPECT_TRUE(halted_wave->is_halted()); + kfd_ioctl_dbg_trap_args count2{}; + count2.pid = static_cast(getpid()); + count2.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + count2.queue_snapshot.entry_size = sizeof(kfd_queue_snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &count2), 0); + EXPECT_EQ(count2.queue_snapshot.num_queues, 1u); + dq.queue_id = q2.queue_id; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DESTROY_QUEUE, &dq), 0); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &count2), 0); + EXPECT_EQ(count2.queue_snapshot.num_queues, 0u); +} + +TEST_F(KfdIoctlTest, DbgTrapRealWaveTrapReportsWhilePeerRunsBeforeExplicitCwsrSuspend) { + constexpr uint64_t kKernelAddress = 0x600000000ULL; + constexpr uint64_t kPeerAddress = 0x600001000ULL; + constexpr uint64_t kTrapHandlerAddress = 0x600080000ULL; + constexpr uint64_t kCwsrAddress = 0x600100000ULL; + constexpr uint32_t kCwsrSize = 0x40000; + constexpr uint32_t kSTrapBreakpoint = 0xBF920001u; + constexpr uint32_t kSNop = 0xBF800000u; + + std::vector code_page(4096); + std::vector peer_page(4096); + std::vector trap_handler_page(4096); + std::vector cwsr(kCwsrSize); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + process->map_pages(kKernelAddress, code_page.data(), code_page.size()); + process->map_pages(kPeerAddress, peer_page.data(), peer_page.size()); + process->map_pages(kTrapHandlerAddress, trap_handler_page.data(), trap_handler_page.size()); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + kfd_ioctl_set_trap_handler_args set_handler{}; + set_handler.gpu_id = kGpuId; + set_handler.tba_addr = kTrapHandlerAddress; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_SET_TRAP_HANDLER, &set_handler), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kGpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + rocjitsu::amdgpu::ComputeUnitCore *cu = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (cu == nullptr && !cp->compute_units().empty()) + cu = cp->compute_units().front(); + }); + ASSERT_NE(cu, nullptr); + + auto *memory = soc_->memory(); + ASSERT_NE(memory, nullptr); + memory->write32(kKernelAddress, kSTrapBreakpoint, driver_->local_process_id()); + for (uint32_t offset = 0; offset < peer_page.size(); offset += sizeof(uint32_t)) + memory->write32(kPeerAddress + offset, kSNop, driver_->local_process_id()); + const uint32_t trap_handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEF800FFu, 0x00002000u, // s_mov_b32 ttmp12, STATUS.HALT + 0xBF900001u, // s_sendmsg sendmsg(MSG_INTERRUPT) + 0xB978F802u, // s_setreg_b32 hwreg(HW_REG_STATUS), ttmp12 + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(trap_handler); ++i) + memory->write32(kTrapHandlerAddress + i * 4, trap_handler[i], driver_->local_process_id()); + auto *wave = cu->dispatch_wf(/*wg_id=*/0, kKernelAddress, /*sgprs=*/16, /*vgprs=*/4); + auto *peer = cu->dispatch_wf(/*wg_id=*/1, kPeerAddress, /*sgprs=*/16, /*vgprs=*/4); + ASSERT_NE(wave, nullptr); + ASSERT_NE(peer, nullptr); + for (auto *resident : {wave, peer}) { + resident->set_process_id(driver_->local_process_id()); + resident->set_queue_id(create.queue_id); + resident->set_dispatch_id(7); + } + + kfd_queue_snapshot_entry snapshot_entry{}; + kfd_ioctl_dbg_trap_args snapshot{}; + snapshot.pid = static_cast(getpid()); + snapshot.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + snapshot.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(&snapshot_entry); + snapshot.queue_snapshot.num_queues = 1; + snapshot.queue_snapshot.entry_size = sizeof(snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snapshot), 0); + + for (uint32_t i = 0; i < 8 && !wave->debug_halted(); ++i) + cu->step(); + ASSERT_TRUE(wave->debug_halted()); + ASSERT_FALSE(peer->debug_halted()); + EXPECT_GT(peer->pc, kPeerAddress); + + uint64_t notifications = 0; + ASSERT_EQ(::read(notifier, ¬ifications, sizeof(notifications)), + static_cast(sizeof(notifications))) + << strerror(errno); + EXPECT_EQ(notifications, 1u); + + kfd_ioctl_dbg_trap_args query{}; + query.pid = static_cast(getpid()); + query.op = KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT; + query.query_debug_event.exception_mask = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &query), 0); + EXPECT_EQ(query.query_debug_event.queue_id, create.queue_id); + EXPECT_EQ(query.query_debug_event.gpu_id, kGpuId); + EXPECT_NE(query.query_debug_event.exception_mask & KFD_EC_MASK(EC_QUEUE_WAVE_TRAP), 0u); + + // Notification alone does not publish queue state. ROCdbgapi explicitly + // suspends the queue before decoding its authoritative CWSR snapshot. + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0u); + uint32_t queue_id = create.queue_id; + kfd_ioctl_dbg_trap_args control{}; + control.pid = static_cast(getpid()); + control.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + control.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.suspend_queues.num_queues = 1; + control.suspend_queues.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0x100u); + EXPECT_NE(memory->read32(kCwsrAddress + 8, driver_->local_process_id()), 0u); + EXPECT_NE(memory->read32(kCwsrAddress + 12, driver_->local_process_id()), 0u); + std::vector states(2); + for (auto &state : states) { + state.num_sgprs = 16; + state.num_vgprs = 4; + } + ASSERT_TRUE( + rocjitsu::kmd::deserialize_queue_cwsr(kCwsrAddress, kCwsrSize, states, [&](uint64_t address) { + return memory->read32(address, driver_->local_process_id()); + })); + auto stopped = std::find_if(states.begin(), states.end(), + [](const auto &state) { return state.wave_stopped; }); + ASSERT_NE(stopped, states.end()); + auto running = std::find_if(states.begin(), states.end(), + [](const auto &state) { return !state.wave_stopped; }); + ASSERT_NE(running, states.end()); + EXPECT_FALSE(stopped->saved_status_halt); + EXPECT_NE(stopped->status & (1u << 13), 0u); + EXPECT_EQ(running->status & (1u << 13), 0u); +} + +// An unfetchable PC is the only wave stop that reaches the debug callbacks +// without going through the decoder, which is what makes it usable on a part +// whose instruction encodings this file does not otherwise touch. The cost is +// that a declined fault here halts the wave and frees its slot, so it cannot +// show whether a declined stop was cleanly undone -- the scalar-load fault +// below is used for that. Returns the resident wave, halted or not. +rocjitsu::amdgpu::Wavefront *fault_a_wave_on_an_unmapped_pc(rocjitsu::SoC *soc, + rocjitsu::SimulatedKfd *driver, + uint64_t unmapped_pc, + uint32_t queue_id) { + rocjitsu::amdgpu::ComputeUnitCore *cu = nullptr; + soc->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (cu == nullptr && !cp->compute_units().empty()) + cu = cp->compute_units().front(); + }); + if (cu == nullptr) + return nullptr; + auto *wave = cu->dispatch_wf(/*wg_id=*/0, unmapped_pc, /*sgprs=*/16, /*vgprs=*/4); + if (wave == nullptr) + return nullptr; + wave->set_process_id(driver->local_process_id()); + wave->set_queue_id(queue_id); + wave->set_dispatch_id(7); + for (uint32_t i = 0; i < 4 && !wave->is_halted() && !wave->debug_halted(); ++i) + cu->step(); + return wave; +} + +// A data-side fault instead: s_load_dword through a null sbase. A declined +// fault leaves this wave running -- the access is re-issued at its own PC and +// retires -- which is what makes it able to tell a stop that was rolled back +// from one that was never attempted. gfx9 encodings, so CDNA fixtures only. +rocjitsu::amdgpu::Wavefront *fault_a_wave_on_a_scalar_load(rocjitsu::SoC *soc, + rocjitsu::SimulatedKfd *driver, + uint64_t kernel_pc, uint32_t queue_id) { + auto *memory = soc->memory(); + if (memory == nullptr) + return nullptr; + const uint32_t pid = driver->local_process_id(); + memory->write32(kernel_pc, 0xC0000000u, pid); // s_load_dword s0, s[0:1], 0x0 + memory->write32(kernel_pc + 4, 0u, pid); // ... its immediate offset + memory->write32(kernel_pc + 8, 0xBF800000u, pid); // s_nop 0 + + rocjitsu::amdgpu::ComputeUnitCore *cu = nullptr; + soc->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (cu == nullptr && !cp->compute_units().empty()) + cu = cp->compute_units().front(); + }); + if (cu == nullptr) + return nullptr; + auto *wave = cu->dispatch_wf(/*wg_id=*/0, kernel_pc, /*sgprs=*/16, /*vgprs=*/4); + if (wave == nullptr) + return nullptr; + wave->set_process_id(pid); + wave->set_queue_id(queue_id); + wave->set_dispatch_id(7); + // sbase = s[0:1] = 0, an address nothing is mapped at. + cu->write_sgpr(wave->sgpr_alloc().base, 0); + cu->write_sgpr(wave->sgpr_alloc().base + 1, 0); + cu->step(); + return wave; +} + +// The CWSR codec reproduces the gfx9.4 record only, so on any other part a +// published record is one rocm-dbgapi would decode against a layout that does +// not match. Declining the stop has to happen before the wave is touched: a +// wave stopped for a record that never appears parks forever, because the only +// thing that could resume it is a debugger reading that record. The fault +// therefore takes its ordinary undebugged path instead. +TEST_F(KfdIoctlRdna3Test, DbgTrapDeclinesWaveStopsOnAPartWithNoModelledCwsrLayout) { + constexpr uint64_t kUnmappedAddress = 0x600200000ULL; + constexpr uint64_t kCwsrAddress = 0x600100000ULL; + constexpr uint32_t kCwsrSize = 0x40000; + + std::vector cwsr(kCwsrSize); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + ASSERT_NE(driver_->local_process_id(), 0u); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kRdna3GpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + auto *wave = fault_a_wave_on_an_unmapped_pc(soc_, driver_, kUnmappedAddress, create.queue_id); + ASSERT_NE(wave, nullptr); + + // Declined, not deferred: the wave halts the way it would with no debugger + // attached, and the callback leaves no half-applied stop behind it. + EXPECT_FALSE(wave->debug_halted()); + EXPECT_TRUE(wave->is_halted()); + EXPECT_EQ(wave->trapsts(), 0u); + + auto *memory = soc_->memory(); + ASSERT_NE(memory, nullptr); + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0u); + + uint64_t notifications = 0; + EXPECT_EQ(::read(notifier, ¬ifications, sizeof(notifications)), -1); + EXPECT_EQ(errno, EAGAIN); +} + +// The stop gate above is the last line of defence, not the first: rocdbgapi asks +// the device snapshot whether an agent is debuggable before it attaches to one. +// Withholding the support bit there declines at the capability boundary, with +// every other agent in the process still usable, rather than letting an attach +// succeed and then declining each individual wave stop behind it. +TEST_F(KfdIoctlRdna3Test, DbgTrapDeviceSnapshotWithholdsTrapDebugOnUnmodelledArch) { + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(getpid()); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = make_debug_fd(); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &en), 0); + + kfd_dbg_device_info_entry entry{}; + kfd_ioctl_dbg_trap_args snap{}; + snap.pid = static_cast(getpid()); + snap.op = KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT; + snap.device_snapshot.entry_size = sizeof(entry); + snap.device_snapshot.num_devices = 1; + snap.device_snapshot.snapshot_buf_ptr = reinterpret_cast(&entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snap), 0); + ASSERT_EQ(snap.device_snapshot.num_devices, 1u); + + ASSERT_FALSE(rocjitsu::kmd::cwsr_layout_modelled_for_gc_ip_version( + rocjitsu::kmd::gc_ip_version_for_gfx_target_version(entry.gfx_target_version))) + << "this fixture is supposed to be a part the CWSR codec does not model"; + EXPECT_EQ(entry.capability & HSA_CAP_TRAP_DEBUG_SUPPORT, 0u) + << "an agent whose CWSR record the simulator cannot produce advertised trap debugging"; + + // Only that claim is withheld. The agent is still enumerated, still carries + // its address-watch description, and is still usable for everything a + // non-debugging client does with it. + EXPECT_EQ(entry.gpu_id, kRdna3GpuId); + EXPECT_NE(entry.capability & HSA_CAP_WATCH_POINTS_SUPPORTED, 0u); + EXPECT_NE(entry.debug_prop, 0u); + EXPECT_NE(entry.simd_count, 0u); +} + +// rocm-dbgapi reaches the same publication through its own request rather than +// through a wave stop, and that route stops the waves first. Without the same +// gate it would strand every resident wave behind the queue error it reports. +TEST_F(KfdIoctlRdna3Test, DbgTrapSuspendQueuesOnUnmodelledArchErrsWithoutStrandingWaves) { + constexpr uint64_t kUnmappedAddress = 0x600200000ULL; + constexpr uint64_t kCwsrAddress = 0x600100000ULL; + constexpr uint32_t kCwsrSize = 0x40000; + + std::vector cwsr(kCwsrSize); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kRdna3GpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + rocjitsu::amdgpu::ComputeUnitCore *cu = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (cu == nullptr && !cp->compute_units().empty()) + cu = cp->compute_units().front(); + }); + ASSERT_NE(cu, nullptr); + auto *wave = cu->dispatch_wf(/*wg_id=*/0, kUnmappedAddress, /*sgprs=*/16, /*vgprs=*/4); + ASSERT_NE(wave, nullptr); + wave->set_process_id(driver_->local_process_id()); + wave->set_queue_id(create.queue_id); + + // SUSPEND_QUEUES rejects a queue still carrying EC_QUEUE_NEW as invalid, so + // acknowledge it the way a debugger does before the request under test. + kfd_queue_snapshot_entry snapshot_entry{}; + kfd_ioctl_dbg_trap_args snapshot{}; + snapshot.pid = static_cast(getpid()); + snapshot.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + snapshot.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(&snapshot_entry); + snapshot.queue_snapshot.num_queues = 1; + snapshot.queue_snapshot.entry_size = sizeof(snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snapshot), 0); + + uint32_t queue_id = create.queue_id; + kfd_ioctl_dbg_trap_args control{}; + control.pid = static_cast(getpid()); + control.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + control.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.suspend_queues.num_queues = 1; + control.suspend_queues.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + EXPECT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 0); + EXPECT_NE(queue_id & KFD_DBG_QUEUE_ERROR_MASK, 0u); + + // Reporting the error and stranding the waves would be strictly worse than + // reporting it alone: the queue would never run again and never be resumable. + EXPECT_FALSE(wave->debug_suspended()); + auto *memory = soc_->memory(); + ASSERT_NE(memory, nullptr); + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0u); +} + +// The positive control for the two cases below: on a modelled part with an area +// the queue's waves fit in, the same fault stops the wave, publishes a record +// and wakes the debugger. Without this the rollback cases could pass by never +// reaching the callback at all. +TEST_F(KfdIoctlTest, DbgTrapMemoryViolationStopsTheWaveAndPublishesItsRecord) { + constexpr uint64_t kKernelAddress = 0x600000000ULL; + constexpr uint64_t kCwsrAddress = 0x600100000ULL; + constexpr uint32_t kCwsrSize = 0x40000; + + std::vector code_page(4096); + std::vector cwsr(kCwsrSize); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + process->map_pages(kKernelAddress, code_page.data(), code_page.size()); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kGpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + auto *wave = fault_a_wave_on_a_scalar_load(soc_, driver_, kKernelAddress, create.queue_id); + ASSERT_NE(wave, nullptr); + + constexpr uint32_t kTrapstsXnackError = 1u << 28; + EXPECT_TRUE(wave->debug_halted()); + EXPECT_NE(wave->trapsts() & kTrapstsXnackError, 0u); + // Stopped past the access: a wave the debugger resumes must not re-run it. + EXPECT_EQ(wave->pc, kKernelAddress + 8); + + auto *memory = soc_->memory(); + ASSERT_NE(memory, nullptr); + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0x100u); + + uint64_t notifications = 0; + ASSERT_EQ(::read(notifier, ¬ifications, sizeof(notifications)), + static_cast(sizeof(notifications))) + << strerror(errno); + EXPECT_EQ(notifications, 1u); +} + +// The arch gate cannot be the only check: on a modelled part serialization can +// still fail, and the wave is already stopped by then because the serializer +// selects waves by debug_stopped(). An area too small for the queue's waves is +// the reachable case -- ROCr sizes it from the largest dispatch it expects, and +// nothing validates it at CREATE_QUEUE. The stop has to come back off the wave. +TEST_F(KfdIoctlTest, DbgTrapUnpublishableStopRollsBackInsteadOfStrandingTheWave) { + constexpr uint64_t kKernelAddress = 0x600000000ULL; + constexpr uint64_t kCwsrAddress = 0x600100000ULL; + // Enough to map, nowhere near enough for a 16-SGPR, 4-VGPR wave plus header, + // control stack and LDS. + constexpr uint32_t kCwsrSize = 0x100; + constexpr uint32_t kTrapstsXnackError = 1u << 28; + + std::vector code_page(4096); + std::vector cwsr(4096); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + process->map_pages(kKernelAddress, code_page.data(), code_page.size()); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_MEMORY_VIOLATION); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kGpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + auto *wave = fault_a_wave_on_a_scalar_load(soc_, driver_, kKernelAddress, create.queue_id); + ASSERT_NE(wave, nullptr); + + // Every field the callback set on the way to the failed publication is back + // where it was, so the wave keeps running exactly as it would with nobody + // debugging it. Leaving debug_halted set would park it with no record for a + // debugger to resume from; leaving TRAPSTS.XNACK_ERROR behind would make the + // next stop report a memory violation that never happened. + EXPECT_FALSE(wave->debug_halted()); + EXPECT_FALSE(wave->is_halted()); + EXPECT_EQ(wave->trapsts() & kTrapstsXnackError, 0u); + EXPECT_EQ(wave->pc, kKernelAddress + 8); + + uint64_t notifications = 0; + EXPECT_EQ(::read(notifier, ¬ifications, sizeof(notifications)), -1); + EXPECT_EQ(errno, EAGAIN); +} + +// A wave parked between MSG_INTERRUPT and s_rfe is still executing the ROCr +// trap handler, under the handler's own EXEC rather than the application's. +// The CWSR record has to carry the interrupted mask -- publishing the handler's +// makes every lane read as active, which inverts `lane apply -active` and +// `-inactive` (gdb.rocm/lane-info.exp). The record is also the resume payload, +// so the reverse shadow matters just as much: an EXEC the debugger edits has to +// reach the wave through the handler's restore instead of overwriting the mask +// the unfinished handler is still running under. +TEST_F(KfdIoctlTest, DbgTrapCwsrShadowsTrapHandlerRegistersAndRoutesDebuggerEdits) { + constexpr uint64_t kKernelAddress = 0x600400000ULL; + constexpr uint64_t kTrapHandlerAddress = 0x600480000ULL; + constexpr uint64_t kCwsrAddress = 0x600500000ULL; + constexpr uint32_t kCwsrSize = 0x40000; + constexpr uint32_t kSTrapBreakpoint = 0xBF920001u; + constexpr uint32_t kSEndpgm = 0xBF810000u; + // Lanes 0, 2 and 4 of a five-lane wave: the shape gdb.rocm/lane-info.exp + // produces, where half the lanes have converged out of the divergent branch. + constexpr uint64_t kInterruptedExec = 0x15ULL; + constexpr uint64_t kHandlerExec = 0xFFFFFFFFULL; + constexpr uint64_t kDebuggerExec = 0x1FULL; + const auto pid = static_cast(getpid()); + + std::vector code_page(4096); + std::vector trap_handler_page(4096); + std::vector cwsr(kCwsrSize); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + process->map_pages(kKernelAddress, code_page.data(), code_page.size()); + process->map_pages(kTrapHandlerAddress, trap_handler_page.data(), trap_handler_page.size()); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + const int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = pid; + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + kfd_ioctl_set_trap_handler_args set_handler{}; + set_handler.gpu_id = kGpuId; + set_handler.tba_addr = kTrapHandlerAddress; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_SET_TRAP_HANDLER, &set_handler), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kGpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + rocjitsu::amdgpu::ComputeUnitCore *cu = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (cu == nullptr && !cp->compute_units().empty()) + cu = cp->compute_units().front(); + }); + ASSERT_NE(cu, nullptr); + auto *memory = soc_->memory(); + ASSERT_NE(memory, nullptr); + + memory->write32(kKernelAddress, kSTrapBreakpoint, driver_->local_process_id()); + memory->write32(kKernelAddress + 4, kSEndpgm, driver_->local_process_id()); + // The clobber stands in for the doorbell exchange the real ROCr handler runs + // through EXEC_LO, and lands before the halt so the snapshot is taken with + // the handler's mask live. + const uint32_t trap_handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEFE00FFu, 0xFFFFFFFFu, // s_mov_b32 exec_lo, 0xffffffff + 0xBEF800FFu, 0x00002000u, // s_mov_b32 ttmp12, STATUS.HALT + 0xBF900001u, // s_sendmsg sendmsg(MSG_INTERRUPT) + 0xB978F802u, // s_setreg_b32 hwreg(HW_REG_STATUS), ttmp12 + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(trap_handler); ++i) + memory->write32(kTrapHandlerAddress + i * 4, trap_handler[i], driver_->local_process_id()); + + auto *wave = cu->dispatch_wf(/*wg_id=*/0, kKernelAddress, /*sgprs=*/16, /*vgprs=*/4); + ASSERT_NE(wave, nullptr); + wave->set_process_id(driver_->local_process_id()); + wave->set_queue_id(create.queue_id); + wave->set_dispatch_id(7); + wave->set_exec(kInterruptedExec); + + // Consume EC_QUEUE_NEW the way rocdbgapi does at attach; until it is cleared + // the queue reads as invalid and cannot be suspended. + kfd_queue_snapshot_entry snapshot_entry{}; + kfd_ioctl_dbg_trap_args snapshot{}; + snapshot.pid = pid; + snapshot.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + snapshot.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(&snapshot_entry); + snapshot.queue_snapshot.num_queues = 1; + snapshot.queue_snapshot.entry_size = sizeof(snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snapshot), 0); + + // Stop between MSG_INTERRUPT and s_rfe. s_rfe is what clears in_trap_handler + // and reinstalls trap_saved_exec_, so this is the window where the live mask + // is the handler's and the debugger can still be handed a snapshot -- the + // queue is suspended below while the wave sits here. + for (uint32_t i = 0; i < 10 && !wave->trap_interrupt_sent(); ++i) + cu->step(); + ASSERT_TRUE(wave->trap_interrupt_sent()); + ASSERT_TRUE(wave->in_trap_handler()); + ASSERT_EQ(wave->exec(), kHandlerExec); + + uint32_t queue_id = create.queue_id; + kfd_ioctl_dbg_trap_args control{}; + control.pid = pid; + control.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + control.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.suspend_queues.num_queues = 1; + control.suspend_queues.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + + std::vector states(1); + states[0].num_sgprs = 16; + states[0].num_vgprs = 4; + ASSERT_TRUE( + rocjitsu::kmd::deserialize_queue_cwsr(kCwsrAddress, kCwsrSize, states, [&](uint64_t address) { + return memory->read32(address, driver_->local_process_id()); + })); + // The debugger sees the application's lanes, and the live register is + // untouched by having published them. + EXPECT_EQ(states[0].exec, kInterruptedExec); + EXPECT_EQ(wave->exec(), kHandlerExec); + + states[0].exec = kDebuggerExec; + ASSERT_TRUE(rocjitsu::kmd::serialize_queue_cwsr(kCwsrAddress, kCwsrSize, states, + [&](uint64_t address, uint32_t value) { + memory->write32(address, value, + driver_->local_process_id()); + }) + .ok); + control.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + control.resume_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.resume_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + + // The edit went to the shadow, so the handler is still running under its own + // mask and only installs the debugger's on s_rfe. + EXPECT_EQ(wave->exec(), kHandlerExec); + + // STATUS is the same contract and the costlier half. Step the s_setreg that + // raises STATUS.HALT -- the handler announcing it wants the wave kept stopped + // -- and take another snapshot before s_rfe consumes it. + constexpr uint32_t kStatusHalt = 1u << 13; + cu->step(); + ASSERT_TRUE(wave->in_trap_handler()); + ASSERT_NE(wave->status_raw() & kStatusHalt, 0u); + + control.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + control.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.suspend_queues.num_queues = 1; + control.suspend_queues.exception_mask = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + ASSERT_TRUE( + rocjitsu::kmd::deserialize_queue_cwsr(kCwsrAddress, kCwsrSize, states, [&](uint64_t address) { + return memory->read32(address, driver_->local_process_id()); + })); + // The wave has not stopped for the debugger yet -- the handler has only asked + // -- so the record describes it as running, exactly as it did before. + EXPECT_FALSE(states[0].wave_stopped); + ASSERT_TRUE(rocjitsu::kmd::serialize_queue_cwsr(kCwsrAddress, kCwsrSize, states, + [&](uint64_t address, uint32_t value) { + memory->write32(address, value, + driver_->local_process_id()); + }) + .ok); + control.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + control.resume_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.resume_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + // Applying that record must not take the handler's HALT away. It used to, and + // s_rfe then resumed a wave the debugger was expecting to catch. + EXPECT_NE(wave->status_raw() & kStatusHalt, 0u); + + for (uint32_t i = 0; i < 4 && wave->in_trap_handler(); ++i) + cu->step(); + EXPECT_FALSE(wave->in_trap_handler()); + EXPECT_TRUE(wave->debug_halted()); + EXPECT_EQ(wave->exec(), kDebuggerExec); +} + +TEST_F(KfdIoctlTest, DbgTrapSingleStepReportsWhilePeerWaveRuns) { + constexpr uint64_t kSteppingAddress = 0x600200000ULL; + constexpr uint64_t kPeerAddress = 0x600201000ULL; + constexpr uint64_t kCwsrAddress = 0x600300000ULL; + constexpr uint32_t kCwsrSize = 0x40000; + constexpr uint32_t kSNop = 0xBF800000u; + constexpr uint32_t kModeDebugEn = 1u << 11; + constexpr uint32_t kTrapAfterInst = 1u << 25; + constexpr uint32_t kStepCount = 5; + constexpr uint64_t kSteppingWaveId = 0x123456789ABCDEF0ULL; + + std::vector stepping_code(4096); + std::vector peer_code(4096); + std::vector cwsr(kCwsrSize); + auto process = driver_->find_process(driver_->local_process_id()); + ASSERT_NE(process, nullptr); + process->map_pages(kSteppingAddress, stepping_code.data(), stepping_code.size()); + process->map_pages(kPeerAddress, peer_code.data(), peer_code.size()); + process->map_pages(kCwsrAddress, cwsr.data(), cwsr.size()); + + kfd_ioctl_runtime_enable_args runtime{}; + runtime.mode_mask = KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_RUNTIME_ENABLE, &runtime), 0); + + const int notifier = eventfd(0, EFD_CLOEXEC | EFD_NONBLOCK); + ASSERT_GE(notifier, 0); + debug_fds_.push_back(notifier); + + kfd_ioctl_dbg_trap_args enable{}; + enable.pid = static_cast(getpid()); + enable.op = KFD_IOC_DBG_TRAP_ENABLE; + enable.enable.dbg_fd = notifier; + enable.enable.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &enable), 0); + + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + create.gpu_id = kGpuId; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + create.ctx_save_restore_address = kCwsrAddress; + create.ctx_save_restore_size = kCwsrSize; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + kfd_queue_snapshot_entry snapshot_entry{}; + kfd_ioctl_dbg_trap_args snapshot{}; + snapshot.pid = static_cast(getpid()); + snapshot.op = KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT; + snapshot.queue_snapshot.exception_mask = KFD_EC_MASK(EC_QUEUE_NEW); + snapshot.queue_snapshot.snapshot_buf_ptr = reinterpret_cast(&snapshot_entry); + snapshot.queue_snapshot.num_queues = 1; + snapshot.queue_snapshot.entry_size = sizeof(snapshot_entry); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &snapshot), 0); + + rocjitsu::amdgpu::ComputeUnitCore *cu = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (cu == nullptr && !cp->compute_units().empty()) + cu = cp->compute_units().front(); + }); + ASSERT_NE(cu, nullptr); + + auto *memory = soc_->memory(); + ASSERT_NE(memory, nullptr); + for (uint32_t step = 0; step < kStepCount; ++step) { + memory->write32(kSteppingAddress + step * sizeof(uint32_t), kSNop, driver_->local_process_id()); + memory->write32(kPeerAddress + step * sizeof(uint32_t), kSNop, driver_->local_process_id()); + } + + auto *stepping = cu->dispatch_wf(/*wg_id=*/0, kSteppingAddress, /*sgprs=*/16, /*vgprs=*/4); + auto *peer = cu->dispatch_wf(/*wg_id=*/1, kPeerAddress, /*sgprs=*/16, /*vgprs=*/4); + ASSERT_NE(stepping, nullptr); + ASSERT_NE(peer, nullptr); + for (auto *wave : {stepping, peer}) { + wave->set_process_id(driver_->local_process_id()); + wave->set_queue_id(create.queue_id); + wave->set_dispatch_id(7); + } + stepping->set_debug_single_step(true); + + for (uint32_t step = 0; step < kStepCount; ++step) { + cu->step(); + + EXPECT_TRUE(stepping->debug_halted()); + EXPECT_EQ(stepping->pc, kSteppingAddress + (step + 1) * sizeof(uint32_t)); + EXPECT_FALSE(peer->debug_halted()); + EXPECT_EQ(peer->pc, kPeerAddress + (step + 1) * sizeof(uint32_t)); + + uint64_t notifications = 0; + ASSERT_EQ(::read(notifier, ¬ifications, sizeof(notifications)), + static_cast(sizeof(notifications))) + << strerror(errno); + EXPECT_EQ(notifications, 1u); + + kfd_ioctl_dbg_trap_args query{}; + query.pid = static_cast(getpid()); + query.op = KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT; + query.query_debug_event.exception_mask = 0; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &query), 0); + EXPECT_EQ(query.query_debug_event.queue_id, create.queue_id); + EXPECT_NE(query.query_debug_event.exception_mask & KFD_EC_MASK(EC_QUEUE_WAVE_TRAP), 0u); + + // A single-step trap signals an interrupt; it does not implicitly save the + // queue. The debugger's explicit suspension below is the publication point. + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0u); + + uint32_t queue_id = create.queue_id; + kfd_ioctl_dbg_trap_args control{}; + control.pid = static_cast(getpid()); + control.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + control.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.suspend_queues.num_queues = 1; + control.suspend_queues.exception_mask = KFD_EC_MASK(EC_QUEUE_WAVE_TRAP); + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + EXPECT_EQ(memory->read32(kCwsrAddress, driver_->local_process_id()), 0x100u); + + // Model rocdbgapi selecting this wave for another scheduler-locked step. + // Its CWSR writes are consumed by RESUME_QUEUES each cycle. + std::vector states(2); + for (auto &state : states) { + state.num_sgprs = 16; + state.num_vgprs = 4; + } + ASSERT_TRUE(rocjitsu::kmd::deserialize_queue_cwsr( + kCwsrAddress, kCwsrSize, states, + [&](uint64_t address) { return memory->read32(address, driver_->local_process_id()); })); + auto selected = std::find_if(states.begin(), states.end(), [&](const auto &state) { + return step == 0 ? state.group_ids[0] == 0 && state.wave_in_group == 0 + : state.wave_id == kSteppingWaveId; + }); + ASSERT_NE(selected, states.end()); + EXPECT_EQ(selected->pc, kSteppingAddress + (step + 1) * sizeof(uint32_t)); + selected->wave_id = kSteppingWaveId; + if (step != 0) { + selected->queue_packet_id = 100 + step; + selected->group_ids = {200 + step, 300 + step, 400 + step}; + selected->wave_in_group = 10 + step; + } + selected->wave_stopped = false; + selected->mode |= kModeDebugEn; + selected->trapsts &= ~kTrapAfterInst; + ASSERT_TRUE(rocjitsu::kmd::serialize_queue_cwsr(kCwsrAddress, kCwsrSize, states, + [&](uint64_t address, uint32_t value) { + memory->write32(address, value, + driver_->local_process_id()); + }) + .ok); + control.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + control.resume_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.resume_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + EXPECT_EQ(stepping->debug_wave_id(), kSteppingWaveId); + if (step != 0) { + EXPECT_EQ(stepping->aql_packet_id(), 100 + step); + } + EXPECT_TRUE(stepping->debug_single_step()); + EXPECT_FALSE(stepping->debug_halted()); + EXPECT_FALSE(peer->debug_halted()); + + if (step + 1 == kStepCount) { + control = {}; + control.pid = static_cast(getpid()); + control.op = KFD_IOC_DBG_TRAP_SUSPEND_QUEUES; + control.suspend_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.suspend_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + ASSERT_TRUE(rocjitsu::kmd::deserialize_queue_cwsr( + kCwsrAddress, kCwsrSize, states, + [&](uint64_t address) { return memory->read32(address, driver_->local_process_id()); })); + auto stopped_peer = std::find_if(states.begin(), states.end(), [&](const auto &state) { + return state.wave_id != kSteppingWaveId; + }); + ASSERT_NE(stopped_peer, states.end()); + stopped_peer->wave_stopped = true; + stopped_peer->mode |= kModeDebugEn; + peer->set_fatal_exception_pending(true); + ASSERT_TRUE(rocjitsu::kmd::serialize_queue_cwsr( + kCwsrAddress, kCwsrSize, states, + [&](uint64_t address, uint32_t value) { + memory->write32(address, value, driver_->local_process_id()); + }) + .ok); + control.op = KFD_IOC_DBG_TRAP_RESUME_QUEUES; + control.resume_queues.queue_array_ptr = reinterpret_cast(&queue_id); + control.resume_queues.num_queues = 1; + ASSERT_EQ(driver_->ioctl(AMDKFD_IOC_DBG_TRAP, &control), 1); + EXPECT_TRUE(peer->debug_halted()); + EXPECT_TRUE(peer->debug_suspended()); + EXPECT_FALSE(peer->debug_single_step()); + bool queue_suspended = false; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + queue_suspended |= + cp->queue_debug_suspended_for_test(create.queue_id, driver_->local_process_id()); + }); + EXPECT_TRUE(queue_suspended); + } + + // Clear the header sentinel only, so the next completion proves that + // notification remains independent from CWSR serialization. + memory->write32(kCwsrAddress, 0, driver_->local_process_id()); + } +} + +TEST_F(KfdIoctlTest, DbgTrapCrossProcessEnableAuthorizedByPtrace) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + _exit(0); + } + ChildProcessGuard child_guard(child); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + uint32_t inferior = daemon.open_process(child); + ASSERT_NE(debugger, 0u); + ASSERT_NE(inferior, 0u); + + auto enable_from_debugger = [&]() { + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = KFD_INVALID_FD; + return daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &en); + }; + + EXPECT_EQ(enable_from_debugger(), -EPERM); + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + ASSERT_TRUE(WIFSTOPPED(status)); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + const int enable_result = daemon_debug_enable(daemon, debugger, en); + if (enable_result != 0) + close(dbg_fd); + ASSERT_EQ(enable_result, 0); + + kfd_ioctl_dbg_trap_args exceptions{}; + exceptions.pid = static_cast(child); + exceptions.op = KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED; + exceptions.set_exceptions_enabled.exception_mask = 0x1234; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &exceptions), 0); + + EXPECT_EQ(ptrace(PTRACE_DETACH, child, nullptr, nullptr), 0); + + daemon.close(debugger); + daemon.close(inferior); +} + +// A session can be enabled before the inferior opens /dev/kfd. Once that +// inferior exits, DISABLE must release the stale session/notifier but still +// return ESRCH, matching the kernel's target-liveness check. +TEST_F(KfdIoctlTest, DbgTrapExitedTargetDisableReturnsESRCHAndReleasesSession) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + _exit(0); + } + ChildProcessGuard child_guard(child); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + ASSERT_NE(debugger, 0u); + // Deliberately do NOT open_process(child): the inferior has not connected to + // /dev/kfd, so it has no KfdProcess. + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + ASSERT_TRUE(WIFSTOPPED(status)); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + ASSERT_EQ(daemon_debug_enable(daemon, debugger, en), 0); + + ASSERT_EQ(kill(child, SIGKILL), 0); + ASSERT_EQ(waitpid(child, &status, 0), child); + + // A pidfd distinguishes this exited target from a future process that reuses + // its numeric pid. DISABLE reaps the stale session and owned notifier. + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(child); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &dis), -ESRCH); + EXPECT_EQ(fcntl(dbg_fd, F_GETFD), -1); + EXPECT_EQ(errno, EBADF); + + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapIdentityChangeDuringAuthorizationReturnsESRCH) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + } + ChildProcessGuard child_guard(child); + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + ASSERT_TRUE(WIFSTOPPED(status)); + + bool hook_ran = false; + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true, [&] { + hook_ran = true; + ASSERT_EQ(kill(child, SIGKILL), 0); + ASSERT_EQ(waitpid(child, &status, 0), child); + }); + uint32_t debugger = daemon.open_process(getpid()); + ASSERT_NE(debugger, 0u); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &en), -ESRCH); + EXPECT_TRUE(hook_ran); + EXPECT_NE(fcntl(dbg_fd, F_GETFD), -1) << "failed ENABLE must not adopt the notifier"; + ::close(dbg_fd); + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapExitedTargetReturnsESRCHBeforePtraceAuthorization) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + } + ChildProcessGuard child_guard(child); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + ASSERT_NE(debugger, 0u); + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + ASSERT_TRUE(WIFSTOPPED(status)); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + ASSERT_EQ(daemon_debug_enable(daemon, debugger, en), 0); + + ASSERT_EQ(kill(child, SIGKILL), 0); + ASSERT_EQ(waitpid(child, &status, 0), child); + + for (int attempt = 0; attempt < 100 && fcntl(dbg_fd, F_GETFD) != -1; ++attempt) + std::this_thread::sleep_for(std::chrono::milliseconds(10)); + EXPECT_EQ(fcntl(dbg_fd, F_GETFD), -1) << "target-exit reaper did not release notifier"; + EXPECT_EQ(errno, EBADF); + + kfd_ioctl_dbg_trap_args op{}; + op.pid = static_cast(child); + op.op = KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &op), -ESRCH); + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapSessionSurvivesTargetKfdConnectionClose) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + } + ChildProcessGuard child_guard(child); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + uint32_t inferior = daemon.open_process(child); + ASSERT_NE(debugger, 0u); + ASSERT_NE(inferior, 0u); + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + ASSERT_EQ(daemon_debug_enable(daemon, debugger, en), 0); + + ASSERT_EQ(daemon.close(inferior), 0); + kfd_ioctl_dbg_trap_args op{}; + op.pid = static_cast(child); + op.op = KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &op), 0); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(child); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &dis), 0); + EXPECT_EQ(ptrace(PTRACE_DETACH, child, nullptr, nullptr), 0); + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapDisableAfterTargetKfdCloseAndExitReturnsESRCH) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + } + ChildProcessGuard child_guard(child); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + uint32_t inferior = daemon.open_process(child); + ASSERT_NE(debugger, 0u); + ASSERT_NE(inferior, 0u); + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + ASSERT_EQ(daemon_debug_enable(daemon, debugger, en), 0); + + ASSERT_EQ(daemon.close(inferior), 0); + ASSERT_EQ(kill(child, SIGKILL), 0); + ASSERT_EQ(waitpid(child, &status, 0), child); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(child); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &dis), -ESRCH); + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &dis), -ESRCH); + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapDisableWithoutSessionReportsZombieAsExited) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) + _exit(0); + + siginfo_t info{}; + ASSERT_EQ(waitid(P_PID, child, &info, WEXITED | WNOWAIT), 0); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + ASSERT_NE(debugger, 0u); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(child); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &dis), -ESRCH); + + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapSessionSurvivesDebuggerKfdConnectionClose) { + pid_t child = fork(); + ASSERT_GE(child, 0); + if (child == 0) { + for (;;) + pause(); + } + ChildProcessGuard child_guard(child); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(getpid()); + ASSERT_NE(debugger, 0u); + + ASSERT_EQ(ptrace(PTRACE_ATTACH, child, nullptr, nullptr), 0) << strerror(errno); + int status = 0; + ASSERT_EQ(waitpid(child, &status, 0), child); + + int dbg_fd = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(dbg_fd, 0); + kfd_ioctl_dbg_trap_args en{}; + en.pid = static_cast(child); + en.op = KFD_IOC_DBG_TRAP_ENABLE; + en.enable.dbg_fd = static_cast(dbg_fd); + ASSERT_EQ(daemon_debug_enable(daemon, debugger, en), 0); + + ASSERT_EQ(daemon.close(debugger), 0); + debugger = daemon.open_process(getpid()); + ASSERT_NE(debugger, 0u); + kfd_ioctl_dbg_trap_args op{}; + op.pid = static_cast(child); + op.op = KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &op), 0); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(child); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + EXPECT_EQ(daemon.ioctl(debugger, AMDKFD_IOC_DBG_TRAP, &dis), 0); + EXPECT_EQ(ptrace(PTRACE_DETACH, child, nullptr, nullptr), 0); + daemon.close(debugger); +} + +TEST_F(KfdIoctlTest, DbgTrapDebuggerExitReapsSessionAndAllowsReenable) { + int debugger_ready[2]; + ASSERT_EQ(pipe2(debugger_ready, O_CLOEXEC), 0); + + pid_t debugger_pid = fork(); + ASSERT_GE(debugger_pid, 0); + if (debugger_pid == 0) { + ::close(debugger_ready[0]); + int target_ready[2]; + if (pipe2(target_ready, O_CLOEXEC) != 0) + _exit(2); + + pid_t target_pid = fork(); + if (target_pid < 0) + _exit(3); + if (target_pid == 0) { + ::close(target_ready[0]); + ::close(debugger_ready[1]); + if (prctl(PR_SET_PTRACER, PR_SET_PTRACER_ANY) != 0) + _exit(4); + const char ready = 1; + if (::write(target_ready[1], &ready, sizeof(ready)) != sizeof(ready)) + _exit(5); + for (;;) + pause(); + } + + auto fail = [&](int code) { + kill(target_pid, SIGKILL); + while (waitpid(target_pid, nullptr, 0) == -1 && errno == EINTR) { + } + _exit(code); + }; + ::close(target_ready[1]); + char ready = 0; + if (::read(target_ready[0], &ready, sizeof(ready)) != sizeof(ready)) + fail(6); + if (ptrace(PTRACE_ATTACH, target_pid, nullptr, nullptr) != 0) + fail(7); + int status = 0; + if (waitpid(target_pid, &status, 0) != target_pid || !WIFSTOPPED(status)) + fail(8); + if (::write(debugger_ready[1], &target_pid, sizeof(target_pid)) != sizeof(target_pid)) + fail(9); + for (;;) + pause(); + } + ChildProcessGuard debugger_guard(debugger_pid); + ::close(debugger_ready[1]); + + pid_t target_pid = 0; + ASSERT_EQ(::read(debugger_ready[0], &target_pid, sizeof(target_pid)), + static_cast(sizeof(target_pid))); + ASSERT_GT(target_pid, 0); + ChildProcessGuard target_guard(target_pid); + ::close(debugger_ready[0]); + + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + uint32_t debugger = daemon.open_process(debugger_pid); + ASSERT_NE(debugger, 0u); + + int first_notifier = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(first_notifier, 0); + kfd_ioctl_dbg_trap_args first_enable{}; + first_enable.pid = static_cast(target_pid); + first_enable.op = KFD_IOC_DBG_TRAP_ENABLE; + first_enable.enable.dbg_fd = static_cast(first_notifier); + ASSERT_EQ(daemon_debug_enable(daemon, debugger, first_enable), 0); + + // A wave stopped for this debugger. Erasing the session is only half of the + // release: a wave left halted with its queue gate shut outlives the debugger + // that stopped it, and nothing else will ever resume it, so the inferior is + // stranded for good. Set both halves of the stop -- the scheduler's flag and + // the architectural STATUS.HALT that s_rfe consults -- because clearing only + // the former re-halts the wave at the handler return. + const uint32_t target_process = daemon.open_process(target_pid); + ASSERT_NE(target_process, 0u); + std::vector ring(4096); + uint64_t read_pointer = 0; + uint64_t write_pointer = 0; + kfd_ioctl_create_queue_args create{}; + // Not kGpuId: this daemon is a bare SimulatedKfd over soc_, with no + // setup_topology() call to rename its single device, so it keeps the + // constructor's default id. Only self-consistency matters here -- the release + // path finds the queue's GPU by the same number this creates it under. + create.gpu_id = 0; + create.queue_type = KFD_IOC_QUEUE_TYPE_COMPUTE_AQL; + create.ring_base_address = reinterpret_cast(ring.data()); + create.ring_size = static_cast(ring.size()); + create.read_pointer_address = reinterpret_cast(&read_pointer); + create.write_pointer_address = reinterpret_cast(&write_pointer); + ASSERT_EQ(daemon.ioctl(target_process, AMDKFD_IOC_CREATE_QUEUE, &create), 0); + + rocjitsu::amdgpu::Wavefront *wave = nullptr; + rocjitsu::amdgpu::CommandProcessor *wave_cp = nullptr; + rocjitsu::amdgpu::ComputeUnitCore *wave_cu = nullptr; + soc_->for_each_cp([&](rocjitsu::amdgpu::CommandProcessor *cp) { + if (wave != nullptr || cp->compute_units().empty()) + return; + wave_cp = cp; + wave_cu = cp->compute_units().front(); + wave = wave_cu->dispatch_wf(/*wg_id=*/0, /*pc=*/0x600000000ULL, + /*sgprs=*/16, /*vgprs=*/4); + }); + ASSERT_NE(wave, nullptr); + ASSERT_NE(wave_cp, nullptr); + ASSERT_NE(wave_cu, nullptr); + // Under the CU's wave-state lock, the same one release_debuggee_state takes: + // the reaper thread is already running, so every access to a wave's debug + // state from here on shares its mutex or races it. + wave_cu->with_wave_state_locked([&] { + wave->set_process_id(target_process); + wave->set_queue_id(create.queue_id); + wave->set_debug_halted(true); + wave->set_debug_suspended(true); + wave->set_debug_single_step(true); + wave->set_status_halt(true); + wave->set_self_halted(true); + }); + wave_cp->set_queue_debug_suspended(create.queue_id, target_process, true); + + ASSERT_EQ(kill(debugger_pid, SIGKILL), 0); + int status = 0; + ASSERT_EQ(waitpid(debugger_pid, &status, 0), debugger_pid); + ASSERT_TRUE(WIFSIGNALED(status)); + debugger_guard.release(); + + for (int attempt = 0; attempt < 100 && fcntl(first_notifier, F_GETFD) != -1; ++attempt) + std::this_thread::sleep_for(std::chrono::milliseconds(10)); + EXPECT_EQ(fcntl(first_notifier, F_GETFD), -1) << "debugger-exit reaper did not release notifier"; + EXPECT_EQ(errno, EBADF); + ASSERT_EQ(kill(target_pid, 0), 0) << "target exited with its debugger"; + + // The reaper runs the same release path an explicit DISABLE does, so the + // stopped wave is running again and its queue can launch. + // + // Poll for the wave rather than reading it once: the closed notifier above is + // not a happens-before for this. The reaper drops the session -- and with it + // the fd -- while still holding debug_sessions_mutex_, then releases the + // debuggee only after unlocking, so the fd can already be gone while the wave + // is still stopped. Sample under the CU's wave-state lock, which is what the + // release itself holds while it writes these fields. + struct WaveStop { + bool debug_halted = true; + bool debug_suspended = true; + bool debug_single_step = true; + bool status_halt = true; + bool self_halted = true; + }; + auto sample = [&] { + return wave_cu->with_wave_state_locked([&] { + return WaveStop{wave->debug_halted(), wave->debug_suspended(), wave->debug_single_step(), + wave->status_halt(), wave->self_halted()}; + }); + }; + WaveStop stop = sample(); + for (int attempt = 0; attempt < 100 && stop.debug_halted; ++attempt) { + std::this_thread::sleep_for(std::chrono::milliseconds(10)); + stop = sample(); + } + EXPECT_FALSE(stop.debug_halted) << "debugger-exit reaper stranded a stopped wave"; + EXPECT_FALSE(stop.debug_suspended); + EXPECT_FALSE(stop.debug_single_step); + EXPECT_FALSE(stop.status_halt) + << "the architectural halt outlived the session, so the wave re-halts at the handler return"; + EXPECT_FALSE(stop.self_halted); + EXPECT_FALSE(wave_cp->queue_debug_suspended_for_test(create.queue_id, target_process)) + << "the queue launch gate stayed shut after the debugger died"; + + ASSERT_EQ(ptrace(PTRACE_ATTACH, target_pid, nullptr, nullptr), 0) << strerror(errno); + ASSERT_EQ(waitpid(target_pid, &status, 0), target_pid); + ASSERT_TRUE(WIFSTOPPED(status)); + + uint32_t replacement_debugger = daemon.open_process(getpid()); + ASSERT_NE(replacement_debugger, 0u); + int replacement_notifier = eventfd(0, EFD_CLOEXEC); + ASSERT_GE(replacement_notifier, 0); + kfd_ioctl_dbg_trap_args replacement_enable{}; + replacement_enable.pid = static_cast(target_pid); + replacement_enable.op = KFD_IOC_DBG_TRAP_ENABLE; + replacement_enable.enable.dbg_fd = static_cast(replacement_notifier); + EXPECT_EQ(daemon_debug_enable(daemon, replacement_debugger, replacement_enable), 0); + + kfd_ioctl_dbg_trap_args dis{}; + dis.pid = static_cast(target_pid); + dis.op = KFD_IOC_DBG_TRAP_DISABLE; + EXPECT_EQ(daemon.ioctl(replacement_debugger, AMDKFD_IOC_DBG_TRAP, &dis), 0); + ASSERT_EQ(ptrace(PTRACE_KILL, target_pid, nullptr, nullptr), 0); + ASSERT_EQ(waitpid(target_pid, &status, 0), target_pid); + target_guard.release(); + daemon.close(debugger); + daemon.close(replacement_debugger); + daemon.close(target_process); +} + +#if defined(__SANITIZE_THREAD__) +#define RJ_TEST_THREAD_SANITIZER 1 +#elif defined(__has_feature) +#if __has_feature(thread_sanitizer) +#define RJ_TEST_THREAD_SANITIZER 1 +#endif +#endif + +TEST_F(KfdIoctlTest, DebugSessionReaperShutdownDoesNotHang) { +#ifdef RJ_TEST_THREAD_SANITIZER + // The child below starts the reaper thread after forking from this + // multi-threaded parent, which ThreadSanitizer refuses outright ("starting new + // threads after multi-threaded fork is not supported") and kills the child + // for. The shutdown this test exists to measure never runs, so the result + // would say nothing about it either way. + GTEST_SKIP() << "starting threads after fork is unsupported under ThreadSanitizer"; +#else + pid_t worker = fork(); + ASSERT_GE(worker, 0); + if (worker == 0) { + alarm(5); + for (int iteration = 0; iteration < 250; ++iteration) { + rocjitsu::SimulatedKfd daemon(*soc_, /*daemon_mode=*/true); + } + _exit(0); + } + + int status = 0; + ASSERT_EQ(waitpid(worker, &status, 0), worker); + ASSERT_TRUE(WIFEXITED(status)); + EXPECT_EQ(WEXITSTATUS(status), 0); +#endif +} + } // namespace diff --git a/emulation/rocjitsu/tests/rocgdb/add_one.hip b/emulation/rocjitsu/tests/rocgdb/add_one.hip new file mode 100644 index 000000000000..fed80bee4075 --- /dev/null +++ b/emulation/rocjitsu/tests/rocgdb/add_one.hip @@ -0,0 +1,39 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT +// +// Minimal HIP workload used by the rocgdb wave-debugging demo and CI harness +// (tests/rocgdb/debug_kernel.sh). It launches a single `add_one` kernel over one +// 64-lane wavefront and prints a deterministic result, so a debugger can set a +// breakpoint on `add_one`, inspect the stopped wave, single-step, and continue +// to a known-good output ("add_one done: host[0]=1 host[63]=1"). +// +// Build with device debug info for the emulated target, e.g.: +// hipcc --offload-arch=gfx950 -g -O0 -o add_one add_one.hip +#include +#include + +__global__ void add_one(int *data, int n) { + int i = blockIdx.x * blockDim.x + threadIdx.x; + if (i < n) + data[i] += 1; +} + +int main() { + const int n = 64; + int *d = nullptr; + if (hipMalloc(&d, n * sizeof(int)) != hipSuccess) { + std::fprintf(stderr, "hipMalloc failed\n"); + return 1; + } + if (hipMemset(d, 0, n * sizeof(int)) != hipSuccess) + return 2; + add_one<<>>(d, n); + if (hipDeviceSynchronize() != hipSuccess) + return 3; + int host[n]; + if (hipMemcpy(host, d, n * sizeof(int), hipMemcpyDeviceToHost) != hipSuccess) + return 4; + hipFree(d); + std::printf("add_one done: host[0]=%d host[63]=%d\n", host[0], host[n - 1]); + return 0; +} diff --git a/emulation/rocjitsu/tests/rocgdb/bad_access.hip b/emulation/rocjitsu/tests/rocgdb/bad_access.hip new file mode 100644 index 000000000000..2df500587159 --- /dev/null +++ b/emulation/rocjitsu/tests/rocgdb/bad_access.hip @@ -0,0 +1,35 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT +// +// Minimal HIP workload that deliberately faults, used by the rocgdb +// wave-debugging CI harness (tests/rocgdb/debug_kernel.sh) to exercise GPU +// memory-violation reporting. The kernel stores through a pointer to an +// unmapped device address, which the emulator reports to the debugger as a +// memory access fault (rocm-dbgapi WAVE_STOP_REASON_MEMORY_VIOLATION -> SIGSEGV). +// +// Build with device debug info for the emulated target, e.g.: +// hipcc --offload-arch=gfx950 -g -O0 -o bad_access bad_access.hip +#include +#include + +__global__ void bad_access(int *data, int n) { + int i = blockIdx.x * blockDim.x + threadIdx.x; + // A wild, never-mapped device address. The store below faults. + int *wild = reinterpret_cast(0x0000dead0000ULL); + if (i < n) + wild[i] = data[i] + 1; +} + +int main() { + const int n = 64; + int *d = nullptr; + if (hipMalloc(&d, n * sizeof(int)) != hipSuccess) + return 1; + if (hipMemset(d, 0, n * sizeof(int)) != hipSuccess) + return 2; + bad_access<<>>(d, n); + (void)hipDeviceSynchronize(); + hipFree(d); + std::printf("bad_access done\n"); + return 0; +} diff --git a/emulation/rocjitsu/tests/rocgdb/debug_kernel.sh b/emulation/rocjitsu/tests/rocgdb/debug_kernel.sh new file mode 100755 index 000000000000..40af71aa47e0 --- /dev/null +++ b/emulation/rocjitsu/tests/rocgdb/debug_kernel.sh @@ -0,0 +1,506 @@ +#!/usr/bin/env bash + +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# rocgdb wave-debugging demo + CI harness for the rocjitsu emulator. +# +# Compiles the demo HIP kernel with device debug info, then drives real ROCgdb +# through `mirage run` to: set a breakpoint on the GPU kernel `add_one`, run, +# stop at the wave, read PC/EXEC and the instruction at PC, single-step, and +# continue the kernel to completion. It asserts the expected markers so it can +# double as a CI smoke test for the full mirage + rocjitsu + rocm-dbgapi + ROCgdb +# stack. +# +# Exit codes: +# 0 success (all debug markers observed) OR a required tool is missing and +# $ROCGDB_DEMO_REQUIRE is not set (skipped) +# 77 skipped (missing tool) when $ROCGDB_DEMO_REQUIRE=1 uses exit 1 instead +# 1 failure (a marker was missing or the run errored) +# +# Environment: +# MIRAGE_BIN path to the mirage binary (default: search PATH and the +# repo's target/{debug,release}) +# ROCJITSU_LIB path to librocjitsu.so (default: mirage auto-discovers) +# MIRAGE_PROFILE mirage profile / GPU target (default: mi350x = gfx950) +# OFFLOAD_ARCH hipcc --offload-arch (default: gfx950, must match profile) +# ROCGDB_DEMO_REQUIRE if set, missing tools fail (exit 1) instead of skipping +set -uo pipefail + +here="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" +profile="${MIRAGE_PROFILE:-mi350x}" +arch="${OFFLOAD_ARCH:-gfx950}" + +# CTest matches the whole output against SKIP_REGULAR_EXPRESSION "SKIP:" (see +# the RocgdbDebug.KernelBreakpoint registration in tests/CMakeLists.txt), and a +# match reports the entire seven-scenario run skipped regardless of the exit +# status. So the literal string "SKIP:" must be emitted only from here, where it +# always means a test-wide prerequisite is missing and the run stops +# immediately. A mid-run scenario that cannot proceed sets fail=1 instead -- +# printing the token from there would hide every result the run had already +# produced. Anchoring the CMake regex is not an alternative: cmsys anchors to +# the start of the whole output blob, not per line, which would break this +# function instead. +skip() { + echo "SKIP: $1" + [[ -n "${ROCGDB_DEMO_REQUIRE:-}" ]] && exit 1 + exit 0 +} + +# --- Locate tools ----------------------------------------------------------- +# MIRAGE_BIN is authoritative when set, never advisory. ctest points it at the +# staged /bin/mirage precisely so mirage resolves *this* build's +# librocjitsu.so; falling through to PATH when the staged copy is missing or not +# executable would run some other mirage against some other library and report +# the result as this build's, which is the failure the staging exists to prevent. +find_mirage() { + if [[ -n "${MIRAGE_BIN:-}" ]]; then echo "${MIRAGE_BIN}"; return; fi + if command -v mirage >/dev/null 2>&1; then command -v mirage; return; fi + for c in "$here/../../../mirage/target/debug/mirage" \ + "$here/../../../mirage/target/release/mirage"; do + [[ -x "$c" ]] && { echo "$c"; return; } + done +} + +# Checked here rather than inside find_mirage: that runs in a command +# substitution, where `exit` would leave only the subshell and the empty result +# would be reported as a skip. +if [[ -n "${MIRAGE_BIN:-}" && ! -x "${MIRAGE_BIN}" ]]; then + echo "FAIL: MIRAGE_BIN=${MIRAGE_BIN} is not an executable file" >&2 + exit 1 +fi +mirage_bin="$(find_mirage)" +[[ -z "$mirage_bin" ]] && skip "mirage binary not found (set MIRAGE_BIN)" +command -v hipcc >/dev/null 2>&1 || skip "hipcc not found" +command -v rocgdb >/dev/null 2>&1 || skip "rocgdb not found" + +# Python ROCm SDK environments keep runtime and development libraries in +# sibling wheel directories rather than a conventional ROCM_HOME/lib. Pass +# those directories through Mirage so the HIP workload can resolve +# libamdhip64 and the HSA runtime without relying on the caller's environment. +runtime_library_path="${LD_LIBRARY_PATH:-}" +venv_prefix="$(cd "$(dirname "$(command -v rocgdb)")/.." 2>/dev/null && pwd || true)" +for sdk_lib in \ + "$venv_prefix/lib/python"*/site-packages/_rocm_sdk_core/lib \ + "$venv_prefix/lib/python"*/site-packages/_rocm_sdk_devel/lib; do + [[ -d "$sdk_lib" ]] || continue + runtime_library_path="${runtime_library_path:+$runtime_library_path:}$sdk_lib" +done +mirage_runtime_args=() +if [[ -n "$runtime_library_path" ]]; then + mirage_runtime_args+=(--env "LD_LIBRARY_PATH=$runtime_library_path") +fi + +# --- Build the demo kernel -------------------------------------------------- +workdir="$(mktemp -d)" +trap 'rm -rf "$workdir"' EXIT +app="$workdir/add_one" +echo "building $here/add_one.hip (--offload-arch=$arch -g -O0)" +if ! hipcc --offload-arch="$arch" -g -O0 -o "$app" "$here/add_one.hip" 2>"$workdir/build.log"; then + cat "$workdir/build.log" >&2 + skip "hipcc could not build for $arch" +fi + +# --- Drive ROCgdb through mirage -------------------------------------------- +echo "running rocgdb under: $mirage_bin run --profile $profile" +# The gating flow exercises the full core: stop at the kernel, inspect wave +# state, single-step three instructions (asserting the PC advances each time), +# and continue to a correct result. Single-stepping is also covered +# deterministically by the engine unit test +# WaveDebugTest.SingleStepExecutesOneInstructionThenReports. +# +# The `print/x $pc` before and after each stepi lets the assertions below verify +# the wave advanced by real instruction boundaries rather than running away. +# +# Output is captured to a file rather than $(...) command substitution: `mirage +# run` execs under a PTY whose forwarded fds keep a bash command substitution +# blocked waiting for EOF, so a file redirect is used instead. stdin is taken +# from /dev/null so the PTY setup does not block when run non-interactively +# (e.g. under CI); rocgdb --batch needs no input. +outfile="$workdir/rocgdb.out" +timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex 'break add_one' \ + -ex 'run' \ + -ex 'info registers pc exec' \ + -ex 'x/i $pc' \ + -ex 'print/x $pc' \ + -ex 'stepi' \ + -ex 'print/x $pc' \ + -ex 'stepi' \ + -ex 'print/x $pc' \ + -ex 'stepi' \ + -ex 'print/x $pc' \ + -ex 'continue' \ + "$app" "$outfile" 2>&1 +status=$? +out="$(cat "$outfile")" +echo "--------------------------------------------------------------------" +echo "$out" +echo "--------------------------------------------------------------------" + +if [[ $status -ne 0 ]]; then + echo "FAIL: rocgdb run exited with status $status" >&2 + exit 1 +fi + +# --- Assert the debug markers ---------------------------------------------- +fail=0 + +# The two scenarios whose inferior faults on purpose (SIGILL, SIGSEGV) are not +# held to `exit 0` the way the clean scenarios are -- rocgdb's batch status for a +# run that ends on a fatal GPU signal is not something this harness pins down, +# and guessing it would make the test fail on a healthy stack. What must never +# pass silently is the run never producing a whole log, so reject everything from +# 124 up. +# +# The status is mirage's, not rocgdb's: every scenario runs `timeout N mirage run +# -- rocgdb ...`, and mirage forwards the guest's status masked to 8 bits +# (ctl/src/lib.rs), reporting 128+signo for a signalled guest and 127 when it +# could not spawn the command at all. On top of that `timeout` uses 124 for a +# kill and 125 for its own failure, and the shell uses 126/127 for a command it +# could not execute. rocgdb itself only ever exits 0 or 1, so nothing legitimate +# reaches 124 and everything at or above it means the markers below would be +# matched against a truncated log. +check_not_killed() { # + if [[ $1 -ge 124 ]]; then + echo "FAIL: $2 rocgdb run did not complete (status $1)" >&2 + fail=1 + fi +} + +check() { # + if grep -qaE "$1" <<<"$out"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi +} + +check 'hit Breakpoint 1, .*add_one .*at .*:[0-9]+' 'stopped at the GPU kernel breakpoint' +check '^pc +0x[0-9a-f]+' 'read the wave PC register' +check '^exec +0xffffffffffffffff' 'read the wave EXEC mask (all 64 lanes)' +check '=> 0x[0-9a-f]+ <.*add_one.*>:' 'disassembled the instruction at PC' +check 'add_one done: host\[0\]=1 host\[63\]=1' 'kernel produced the correct result after continue' +check 'Inferior 1 .*exited normally' 'inferior exited normally' + +# Single-step assertion: the four `print/x $pc` values (at the breakpoint and +# after each of three stepi) must be strictly increasing. A runaway wave would +# either overshoot (fewer than four values, having exited) or repeat a PC. +mapfile -t pcs < <(grep -aoE '\$[0-9]+ = 0x[0-9a-f]+' <<<"$out" | grep -aoE '0x[0-9a-f]+') +if [[ ${#pcs[@]} -lt 4 ]]; then + echo " MISSING: four PC samples across three stepi (got ${#pcs[@]}: ${pcs[*]:-none})" >&2 + fail=1 +else + strictly_increasing=1 + for ((i = 1; i < 4; i++)); do + # 64-bit compare via bash arithmetic (PCs fit in a signed 64-bit range here). + if (( $((pcs[i])) <= $((pcs[i - 1])) )); then + strictly_increasing=0 + break + fi + done + if [[ $strictly_increasing -eq 1 ]]; then + echo " ok: PC advanced across three single-steps (${pcs[0]} -> ${pcs[1]} -> ${pcs[2]} -> ${pcs[3]})" + else + echo " MISSING: strictly increasing PC across single-steps (got ${pcs[*]})" >&2 + fail=1 + fi +fi + +# The interior breakpoint, the displaced-step check and the watchpoint check all +# want the line that actually stores to data[i]. Derive it rather than spell it +# out three times: adding a licence header to add_one.hip moves it, and two of +# the scenarios below would then fail on a line number instead of on behaviour. +store_line="$(grep -nE 'data\[i\] \+= 1' "$here/add_one.hip" | head -1 | cut -d: -f1)" +[[ -z "$store_line" ]] && store_line=18 + +# --- Second scenario: interior breakpoint + continue (displaced stepping) ----- +# Continuing past a breakpoint whose original instruction dbgapi cannot simulate +# forces amd_dbgapi_displaced_stepping: dbgapi copies the instruction into the +# per-queue debugger memory reserved in the CWSR header, steps it there, and +# resumes. This asserts that reserved region exists and the emulator executes +# from it (otherwise dbgapi aborts: "Per-queue memory reserved for the debugger +# is missing"). +echo "running rocgdb (interior breakpoint + continue) ..." +outfile2="$workdir/rocgdb2.out" +timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex "break add_one.hip:${store_line}" \ + -ex 'run' \ + -ex 'info registers pc' \ + -ex 'continue' \ + "$app" "$outfile2" 2>&1 +status2=$? +out2="$(cat "$outfile2")" +echo "--------------------------------------------------------------------" +echo "$out2" +echo "--------------------------------------------------------------------" +if [[ $status2 -ne 0 ]]; then + echo "FAIL: interior-breakpoint rocgdb run exited with status $status2" >&2 + fail=1 +fi +check2() { # (checks the second run's output) + if grep -qaE "$1" <<<"$out2"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi +} +check2 "hit Breakpoint 1, .*add_one .*at .*:${store_line}" 'stopped at the interior line breakpoint' +check2 'add_one done: host\[0\]=1 host\[63\]=1' 'kernel completed after displaced-stepping the breakpoint' +check2 'Inferior 1 .*exited normally' 'inferior exited normally after interior breakpoint' +if grep -qaE 'Per-queue memory reserved for the debugger is missing' <<<"$out2"; then + echo " FAIL: dbgapi could not find the reserved debugger memory" >&2 + fail=1 +fi + +# --- Third scenario: GPU address watchpoint ----------------------------------- +# Capture the device buffer address at a host breakpoint on the launch line, +# then set a hardware watchpoint on it from GPU context (at the kernel +# breakpoint) and continue. The kernel's `data[i] += 1` store must trip the +# watchpoint, which exercises SET_NODE_ADDRESS_WATCH + the memory-pipeline watch +# check + the addr_watch TRAPSTS reporting. Both breakpoints are set before +# `run` so the pending kernel breakpoint resolves as the code object loads and +# the host breakpoint (on the launch line, before the launch executes) lets us +# read the device pointer `d` — no hard-coded VA. +launch_line="$(grep -nE 'add_one<<<' "$here/add_one.hip" | head -1 | cut -d: -f1)" +[[ -z "$launch_line" ]] && launch_line=30 +echo "running rocgdb (GPU address watchpoint, launch line $launch_line) ..." +outfile3="$workdir/rocgdb3.out" +timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex "break add_one.hip:${launch_line}" \ + -ex 'break add_one' \ + -ex 'run' \ + -ex 'set $waddr = (unsigned long)d' \ + -ex 'continue' \ + -ex 'watch *(int*)$waddr' \ + -ex 'continue' \ + "$app" "$outfile3" 2>&1 +status3=$? +out3="$(cat "$outfile3")" +echo "--------------------------------------------------------------------" +echo "$out3" +echo "--------------------------------------------------------------------" +if [[ $status3 -ne 0 ]]; then + echo "FAIL: watchpoint rocgdb run exited with status $status3" >&2 + fail=1 +fi +check3() { # (checks the third run's output) + if grep -qaE "$1" <<<"$out3"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi +} +check3 'hit (Hardware )?watchpoint [0-9]+' 'the GPU address watchpoint triggered' +check3 'Old value = 0' 'watchpoint captured the pre-write value' +check3 'New value = 1' 'watchpoint captured the post-write value' +check3 "add_one .*at .*:${store_line}" 'stopped at the store that wrote the watched address' + +# --- Fourth scenario: illegal instruction ------------------------------------- +# Single-step once past the entry breakpoint to a clean instruction boundary, +# overwrite that instruction with an undecodable opcode, and continue. The wave +# fetching it must raise an illegal-instruction exception (SIGILL) reported at +# that PC, exercising the CU's illegal-instruction path + EC_QUEUE_WAVE_ILLEGAL_ +# INSTRUCTION + TRAPSTS.illegal_inst. +echo "running rocgdb (illegal instruction) ..." +outfile4="$workdir/rocgdb4.out" +timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex 'break add_one' \ + -ex 'run' \ + -ex 'stepi' \ + -ex 'set {unsigned int}$pc = 0xffffffff' \ + -ex 'continue' \ + -ex 'info registers pc' \ + "$app" "$outfile4" 2>&1 +status4=$? +check_not_killed "$status4" "illegal-instruction" +out4="$(cat "$outfile4")" +echo "--------------------------------------------------------------------" +echo "$out4" +echo "--------------------------------------------------------------------" +check4() { # (checks the fourth run's output) + if grep -qaE "$1" <<<"$out4"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi +} +check4 'SIGILL, Illegal instruction' 'the illegal instruction raised SIGILL' +check4 '^pc +0x[0-9a-f]+ +0x[0-9a-f]+ <.*add_one' 'stopped at the faulting GPU instruction' +if grep -qaE 'misaligned pc|corrupted state' <<<"$out4"; then + echo " FAIL: the reported wave state was corrupted" >&2 + fail=1 +fi + +# --- Fifth scenario: memory violation ----------------------------------------- +# Run a kernel that stores through a wild (never-mapped) device pointer. The +# emulator must report the fault to the debugger as a memory violation (SIGSEGV), +# exercising the CU's unmapped-access detection + EC_QUEUE_WAVE_MEMORY_VIOLATION + +# TRAPSTS.xnack_error. Uses a second demo kernel (bad_access.hip). +badapp="$workdir/bad_access" +if hipcc --offload-arch="$arch" -g -O0 -o "$badapp" "$here/bad_access.hip" 2>"$workdir/badbuild.log"; then + echo "running rocgdb (memory violation) ..." + outfile5="$workdir/rocgdb5.out" + timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex 'break bad_access' \ + -ex 'run' \ + -ex 'continue' \ + "$badapp" "$outfile5" 2>&1 + status5=$? + check_not_killed "$status5" "memory-violation" + out5="$(cat "$outfile5")" + echo "--------------------------------------------------------------------" + echo "$out5" + echo "--------------------------------------------------------------------" + check5() { # (checks the fifth run's output) + if grep -qaE "$1" <<<"$out5"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi + } + check5 'SIGSEGV, Segmentation fault|MEMORY_VIOLATION|memory violation' \ + 'the wild store raised a memory violation' + check5 'bad_access .*at .*:[0-9]+' 'stopped in the faulting kernel' +else + cat "$workdir/badbuild.log" >&2 + echo "FAIL: could not build bad_access.hip for $arch" >&2 + fail=1 +fi + +# --- Sixth scenario: private/scratch variable reads --------------------------- +# At the kernel breakpoint, read scratch-resident kernel arguments and locals +# (`data`, `n`) and a dereferenced device value (`data[0]`). This exercises the +# full private-memory path: the emulator stores scratch in the hardware +# dword-interleaved layout, publishes scratch_backing_memory_location + +# COMPUTE_TMPRING_SIZE and the flat_scratch register into the CWSR, and +# rocm-dbgapi resolves the DWARF private_lane locations against it. A regression +# shows up as "Cannot access memory at address private_lane#..." or the dbgapi +# warning "flat_scratch may be corrupted, private memory access is disabled". +echo "running rocgdb (private/scratch variable reads) ..." +outfile6="$workdir/rocgdb6.out" +timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex 'break add_one' \ + -ex 'run' \ + -ex 'print data' \ + -ex 'print n' \ + -ex 'print data[0]' \ + -ex 'info args' \ + -ex 'continue' \ + "$app" "$outfile6" 2>&1 +status6=$? +out6="$(cat "$outfile6")" +echo "--------------------------------------------------------------------" +echo "$out6" +echo "--------------------------------------------------------------------" +# Tested after the log is echoed, the way scenarios 2, 3 and 7 do it, so the +# diagnosis is not printed above the output that explains it. +if [[ $status6 -ne 0 ]]; then + echo "FAIL: private/scratch rocgdb run exited with status $status6" >&2 + fail=1 +fi +check6() { # (checks the sixth run's output) + if grep -qaE "$1" <<<"$out6"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi +} +check6 '\$1 = \(int \*\) 0x[0-9a-f]+' 'scratch-resident pointer arg `data` resolves' +check6 '\$2 = 64' 'scratch-resident scalar arg `n` resolves to 64' +check6 '\$3 = 0' 'dereferenced device value data[0] reads back 0' +check6 'n = 64' '`info args` reports the scratch-resident argument' +# A wave that faults or runs away during the final `continue` still lets rocgdb +# exit 0, so the status check above cannot stand in for these. +check6 'add_one done: host\[0\]=1 host\[63\]=1' 'kernel completed after the scratch reads' +check6 'Inferior 1 .*exited normally' 'inferior exited normally after the scratch reads' +if grep -qaE 'Cannot access memory at address private_lane|flat_scratch may be corrupted' <<<"$out6"; then + echo " FAIL: scratch/private memory was not readable" >&2 + fail=1 +fi + +# --- Seventh scenario: multi-wave workgroup correlation ----------------------- +# Launch one workgroup of 128 threads (two 64-lane wavefronts) and break inside +# the kernel. Both waves of the workgroup trap; the emulator serializes them +# together (atomic capture once the queue quiesces) so rocm-dbgapi decodes a +# stable control stack and correlates each wave to workgroup (0,0,0) at its +# position (/0 and /1). Reading the scratch-resident `local` in each wave must +# return that wave's own value (thread 0 -> 3, thread 64 -> 451), which +# exercises the per-wave scratch scoreboard mapping. A regression shows up as a +# dbgapi fatal ("not in the same workgroup as the group_leader" / +# "os_queue_packet_id ... not within"), a crash, or identical/again-corrupted +# per-wave values. +mwapp="$workdir/multi_wave" +if hipcc --offload-arch="$arch" -g -O0 -o "$mwapp" "$here/multi_wave.hip" 2>"$workdir/mwbuild.log"; then + echo "running rocgdb (multi-wave workgroup correlation) ..." + # Break on the store line so both waves have computed `i` and `local`. + mw_line="$(grep -nE 'data\[i\] = local' "$here/multi_wave.hip" | head -1 | cut -d: -f1)" + [[ -z "$mw_line" ]] && mw_line=19 + outfile7="$workdir/rocgdb7.out" + timeout 180 "$mirage_bin" run --profile "$profile" "${mirage_runtime_args[@]}" -- \ + rocgdb --batch \ + -ex 'set breakpoint pending on' \ + -ex "break multi_wave.hip:${mw_line}" \ + -ex 'run' \ + -ex 'info threads' \ + -ex 'thread apply all -q print local' \ + -ex 'delete breakpoints' \ + -ex 'continue' \ + "$mwapp" "$outfile7" 2>&1 + status7=$? + out7="$(cat "$outfile7")" + echo "--------------------------------------------------------------------" + echo "$out7" + echo "--------------------------------------------------------------------" + if [[ $status7 -ne 0 ]]; then + echo "FAIL: multi-wave rocgdb run exited with status $status7" >&2 + fail=1 + fi + check7() { # (checks the seventh run's output) + if grep -qaE "$1" <<<"$out7"; then + echo " ok: $2" + else + echo " MISSING: $2 (/$1/)" >&2 + fail=1 + fi + } + check7 "hit Breakpoint 1, .*multi_wave .*at .*:${mw_line}" 'both waves stop at the kernel breakpoint' + check7 'AMDGPU Wave .*\(0,0,0\)/0' 'wave 0 correlated to workgroup (0,0,0) position 0' + check7 'AMDGPU Wave .*\(0,0,0\)/1' 'wave 1 correlated to workgroup (0,0,0) position 1' + check7 '= 3' 'wave 0 scratch read: local == 3 (global thread 0)' + check7 '= 451' 'wave 1 scratch read: local == 451 (global thread 64)' + check7 'multi_wave done: h\[0\]=3 h\[64\]=451' 'kernel produced the correct per-thread results' + check7 'Inferior 1 .*exited normally' 'inferior exited normally after multi-wave debug' + if grep -qaE 'not in the same workgroup as the group_leader|os_queue_packet_id .* is not within|Segmentation fault' <<<"$out7"; then + echo " FAIL: multi-wave correlation aborted (dbgapi grouping/packet-id fault or crash)" >&2 + fail=1 + fi +else + cat "$workdir/mwbuild.log" >&2 + echo "FAIL: could not build multi_wave.hip for $arch" >&2 + fail=1 +fi + +if [[ $fail -ne 0 ]]; then + echo "FAIL: one or more debug markers were missing" >&2 + exit 1 +fi +echo "PASS: rocgdb debugged the emulated GPU kernel end to end" diff --git a/emulation/rocjitsu/tests/rocgdb/multi_wave.hip b/emulation/rocjitsu/tests/rocgdb/multi_wave.hip new file mode 100644 index 000000000000..117e5e86e417 --- /dev/null +++ b/emulation/rocjitsu/tests/rocgdb/multi_wave.hip @@ -0,0 +1,34 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT +// +// Multi-wave debugging demo for the rocgdb CI harness (debug_kernel.sh). +// +// Launches a single workgroup of 128 threads = two 64-lane wavefronts, so a +// breakpoint traps both waves of one workgroup at once. Each thread derives a +// deterministic value from its global id, letting the harness assert that +// rocm-dbgapi correlates each wave to the right workgroup/position and that +// per-wave scratch (private) reads return each wave's own values. + +#include +#include + +__global__ void multi_wave(int *data, int n) { + int i = blockIdx.x * blockDim.x + threadIdx.x; + int local = i * 7 + 3; + if (i < n) + data[i] = local; +} + +int main() { + const int n = 128; // one workgroup, 128 threads => two wavefronts + int *d = nullptr; + if (hipMalloc(&d, n * sizeof(int)) != hipSuccess) + return 1; + hipLaunchKernelGGL(multi_wave, dim3(1), dim3(128), 0, 0, d, n); + hipDeviceSynchronize(); + int h[128]; + hipMemcpy(h, d, n * sizeof(int), hipMemcpyDeviceToHost); + printf("multi_wave done: h[0]=%d h[64]=%d h[127]=%d\n", h[0], h[64], h[127]); + hipFree(d); + return 0; +} diff --git a/emulation/rocjitsu/tests/shared_infra_test.cpp b/emulation/rocjitsu/tests/shared_infra_test.cpp index 7e692d37c5c5..b3b4801d3524 100644 --- a/emulation/rocjitsu/tests/shared_infra_test.cpp +++ b/emulation/rocjitsu/tests/shared_infra_test.cpp @@ -75,6 +75,7 @@ #include "rocjitsu/isa/arch/amdgpu/rdna4/isa.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_flat.h" #include "rocjitsu/isa/arch/amdgpu/shared/addr_calc_scalar.h" +#include "rocjitsu/isa/arch/amdgpu/shared/alu_exceptions.h" #include "rocjitsu/isa/arch/amdgpu/shared/dpp_sdwa_ops.h" #include "rocjitsu/isa/arch/amdgpu/shared/mma_exec.h" #include "rocjitsu/isa/decoder.h" @@ -106,7 +107,9 @@ #include #include #include +#include #include +#include namespace { @@ -880,6 +883,33 @@ TEST(L2CacheTest, UcStoreInvalidatesResidentLineBeforeAtomicRmw) { EXPECT_EQ(second_old, 0u); } +TEST(L2CacheTest, AtomicRmwRefetchesLinesCachedByAnotherXcd) { + amdgpu::GpuMemory mem("test_mem"); + amdgpu::L2Cache first_l2("first_l2"); + amdgpu::L2Cache second_l2("second_l2"); + first_l2.set_backing_memory(&mem); + second_l2.set_backing_memory(&mem); + + constexpr uint64_t kAddr = 0x2040; + mem.write32(kAddr, 1); + + auto atomic_add = [&](amdgpu::L2Cache &l2, uint32_t increment) { + uint32_t old_value = 0; + l2.atomic_rmw(kAddr, sizeof(uint32_t), [&](uint8_t *line, uint32_t offset) { + std::memcpy(&old_value, line + offset, sizeof(old_value)); + const uint32_t new_value = old_value + increment; + std::memcpy(line + offset, &new_value, sizeof(new_value)); + }); + return old_value; + }; + + EXPECT_EQ(atomic_add(first_l2, 0), 1u); + EXPECT_EQ(atomic_add(second_l2, 0), 1u); + EXPECT_EQ(atomic_add(first_l2, 1), 1u); + EXPECT_EQ(atomic_add(second_l2, 1), 2u); + EXPECT_EQ(mem.read32(kAddr), 3u); +} + TEST(L2CacheTest, UcReadFlushesDirtyResidentLine) { amdgpu::GpuMemory mem("test_mem"); amdgpu::L2Cache l2("test_l2"); @@ -1733,6 +1763,69 @@ TEST(GpuMemoryTest, BlockAccessRechecksTranslationAfterSparseFallbackPage) { EXPECT_TRUE(std::equal(kWriteData.begin() + 8, kWriteData.end(), second_page.begin())); } +TEST(GpuMemoryTest, CopyBlockTransfersPageableClientMemoryAcrossPageBoundaries) { + amdgpu::GpuMemory mem("test_mem"); + constexpr uint32_t kVmid = 10; + constexpr uint64_t kGpuAddr = 0x100000 + KfdProcess::kPageSize - 11; + constexpr size_t kSize = KfdProcess::kPageSize + 37; + + std::array first_page{}; + std::array second_page{}; + std::array third_page{}; + KfdProcess::PageTable page_table; + std::shared_mutex page_table_mutex; + const uint64_t first_page_number = kGpuAddr >> amdgpu::GpuMemory::PAGE_SHIFT; + page_table[first_page_number] = {first_page.data(), amdgpu::Mtype::RW}; + page_table[first_page_number + 1] = {second_page.data(), amdgpu::Mtype::RW}; + page_table[first_page_number + 2] = {third_page.data(), amdgpu::Mtype::RW}; + mem.register_process(kVmid, &page_table, &page_table_mutex); + mem.set_process_client_pid(kVmid, getpid()); + + std::vector host_source(kSize + 19); + auto source = std::span(host_source).subspan(7, kSize); + for (size_t i = 0; i < source.size(); ++i) + source[i] = static_cast((i * 37 + 11) & 0xff); + + ASSERT_TRUE( + mem.copy_block(kGpuAddr, reinterpret_cast(source.data()), source.size(), kVmid)); + std::vector gpu_result(kSize); + mem.read_block(kGpuAddr, std::span(gpu_result), kVmid); + EXPECT_TRUE(std::equal(source.begin(), source.end(), gpu_result.begin())); + + std::vector host_destination(kSize + 23, 0); + auto destination = std::span(host_destination).subspan(13, kSize); + ASSERT_TRUE(mem.copy_block(reinterpret_cast(destination.data()), kGpuAddr, + destination.size(), kVmid)); + EXPECT_TRUE(std::equal(source.begin(), source.end(), destination.begin())); +} + +TEST(GpuMemoryTest, AuthorizedProcMemAccessesAnonymousTargetMemory) { + amdgpu::GpuMemory mem("test_mem"); + constexpr uint32_t kVmid = 11; + KfdProcess::PageTable page_table; + std::shared_mutex page_table_mutex; + mem.register_process(kVmid, &page_table, &page_table_mutex); + + const int target_mem_fd = ::open("/proc/self/mem", O_RDWR | O_CLOEXEC); + ASSERT_GE(target_mem_fd, 0); + mem.set_process_mem_fd(kVmid, target_mem_fd); + ::close(target_mem_fd); + + std::array target = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF}; + const uint64_t address = reinterpret_cast(target.data()); + EXPECT_TRUE(mem.is_fetchable(address, kVmid)); + + std::array readback{}; + mem.read_block(address, std::span(readback), kVmid); + EXPECT_EQ(readback, target); + + std::array replacement{}; + std::ranges::fill(replacement, 0xA5); + mem.write_block(address, std::span(replacement), kVmid); + EXPECT_EQ(target, replacement); +} + TEST(L1VectorCacheTest, UcDwordx4RoundTripPreservesVectorTransaction) { amdgpu::GpuMemory mem("test_mem"); amdgpu::L2Cache l2("test_l2"); @@ -1763,6 +1856,41 @@ TEST(L1VectorCacheTest, UcDwordx4RoundTripPreservesVectorTransaction) { EXPECT_EQ(std::memcmp(load_bytes.data() + sizeof(kLane0), kLane1.data(), sizeof(kLane1)), 0); } +TEST(L1VectorCacheTest, ScratchDwordCrossesInterleaveBoundary) { + amdgpu::GpuMemory mem("test_mem"); + amdgpu::L2Cache l2("test_l2"); + amdgpu::L1VectorCache l1(&l2); + l2.set_backing_memory(&mem); + + constexpr uint64_t kAddr = 0x7A01; + constexpr uint32_t kScratchStride = 64 * sizeof(uint32_t); + constexpr uint32_t kInitialValue = 0x55443322; + constexpr uint32_t kStoredValue = 0x87654321; + mem.write8(kAddr, 0x22); + mem.write8(kAddr + 1, 0x33); + mem.write8(kAddr + 2, 0x44); + mem.write8((kAddr & ~uint64_t{3}) + kScratchStride, 0x55); + + uint64_t addrs[64] = {}; + addrs[0] = kAddr; + std::array bytes{}; + l1.load(addrs, /*lane_mask=*/0x1, /*elem_size=*/4, /*num_elems=*/1, bytes.data(), + amdgpu::Mtype::UC, /*non_temporal=*/false, /*request_l1_bypass=*/false, + cdna3::Isa::WF_SIZE, /*vmid=*/0, kScratchStride); + uint32_t value = 0; + std::memcpy(&value, bytes.data(), sizeof(value)); + EXPECT_EQ(value, kInitialValue); + + std::memcpy(bytes.data(), &kStoredValue, sizeof(kStoredValue)); + l1.store(addrs, /*lane_mask=*/0x1, /*elem_size=*/4, /*num_elems=*/1, bytes.data(), + amdgpu::Mtype::UC, /*non_temporal=*/false, cdna3::Isa::WF_SIZE, /*vmid=*/0, + kScratchStride); + EXPECT_EQ(mem.read8(kAddr), 0x21); + EXPECT_EQ(mem.read8(kAddr + 1), 0x43); + EXPECT_EQ(mem.read8(kAddr + 2), 0x65); + EXPECT_EQ(mem.read8((kAddr & ~uint64_t{3}) + kScratchStride), 0x87); +} + TEST(L1VectorCacheTest, PartialElementMasksSkipMaskedLoads) { amdgpu::GpuMemory mem("test_mem"); amdgpu::L2Cache l2("test_l2"); @@ -1784,7 +1912,7 @@ TEST(L1VectorCacheTest, PartialElementMasksSkipMaskedLoads) { std::array bytes{}; l1.load(addrs, /*lane_mask=*/0x3, /*elem_size=*/4, /*num_elems=*/4, bytes.data(), amdgpu::Mtype::UC, /*non_temporal=*/false, /*request_l1_bypass=*/false, - cdna3::Isa::WF_SIZE, /*vmid=*/0, kElementMasks); + cdna3::Isa::WF_SIZE, /*vmid=*/0, /*addr_stride=*/0, kElementMasks); std::array lane0{}; std::array lane1{}; @@ -1813,7 +1941,7 @@ TEST(L1VectorCacheTest, PartialElementMasksDropSkippedStores) { constexpr std::array kElementMasks = {0x1, 0x1, 0x0, 0x0}; l1.store(addrs, /*lane_mask=*/0x1, /*elem_size=*/4, /*num_elems=*/4, bytes.data(), amdgpu::Mtype::UC, /*non_temporal=*/false, cdna3::Isa::WF_SIZE, /*vmid=*/0, - kElementMasks); + /*addr_stride=*/0, kElementMasks); EXPECT_EQ(mem.read32(kAddr), kStored[0]); EXPECT_EQ(mem.read32(kAddr + 4), kStored[1]); @@ -1843,7 +1971,7 @@ TEST(L1VectorCacheTest, PartialElementMasksCoalesceFullyValidLanes) { l1.store(addrs, /*lane_mask=*/0x7, /*elem_size=*/4, /*num_elems=*/4, store_bytes.data(), amdgpu::Mtype::UC, /*non_temporal=*/false, cdna3::Isa::WF_SIZE, /*vmid=*/0, - kElementMasks); + /*addr_stride=*/0, kElementMasks); EXPECT_EQ(l1.store_l2_writes(), 3u); EXPECT_EQ(l2.backing_write_transactions(), 3u); EXPECT_EQ(mem.read32(kAddr + 0), kLane0[0]); @@ -1862,7 +1990,7 @@ TEST(L1VectorCacheTest, PartialElementMasksCoalesceFullyValidLanes) { std::array load_bytes{}; l1.load(addrs, /*lane_mask=*/0x7, /*elem_size=*/4, /*num_elems=*/4, load_bytes.data(), amdgpu::Mtype::UC, /*non_temporal=*/false, /*request_l1_bypass=*/false, - cdna3::Isa::WF_SIZE, /*vmid=*/0, kElementMasks); + cdna3::Isa::WF_SIZE, /*vmid=*/0, /*addr_stride=*/0, kElementMasks); EXPECT_EQ(l2.backing_read_transactions(), 3u); EXPECT_EQ(std::memcmp(load_bytes.data(), kLane0.data(), sizeof(kLane0)), 0); EXPECT_EQ(std::memcmp(load_bytes.data() + sizeof(kLane0), kLane1.data(), sizeof(kLane1)), 0); @@ -2135,10 +2263,12 @@ TEST(CuFactoryTest, CdnaAccVgprsAreClearedOnRedispatch) { const uint32_t acc_last = acc0 + kCdnaAccVgprsPerWf - 1; cu->write_vgpr(acc0, 0, 0xFFFFFFFFu); cu->write_vgpr(acc_last, 0, 0xDEADBEEFu); + wf->set_status_raw(0xFFFFFFFFu); wf->halt(); wf = cu->dispatch_wf(0, 0, cfg.sgprs_per_wf, cfg.vgprs_per_wf); ASSERT_NE(wf, nullptr); + EXPECT_EQ(wf->status_raw(), 0u); EXPECT_EQ(cu->read_vgpr(wf->vgpr_alloc().base + amdgpu::ACC_VGPR_OFFSET, 0), 0u); EXPECT_EQ( @@ -3778,12 +3908,13 @@ TEST(ScratchAddrCalcTest, FlatScratchUsesWavefrontBase) { constexpr uint64_t SCRATCH_BASE = 0x1'0000'0000ULL; wf->set_scratch_base(SCRATCH_BASE); - // Write a 32-bit offset into VGPR[0] lane 0. + // Write the same per-lane private byte offset into VGPR[0] for lanes 0 and 1. uint32_t vbase = wf->vgpr_alloc().base; cu->write_vgpr(vbase, 0, 0x100); // lane 0: offset 0x100 + cu->write_vgpr(vbase, 1, 0x100); // lane 1: offset 0x100 - // Set EXEC so only lane 0 is active. - wf->set_exec(1ULL); + // Set EXEC so lanes 0 and 1 are active. + wf->set_exec(0x3ULL); // Build a FlatScratchMachineInst with seg=1 (SCRATCH), sve=1 (VADDR enabled), // saddr=0x7F (no SADDR), offset=0x10. @@ -3797,9 +3928,55 @@ TEST(ScratchAddrCalcTest, FlatScratchUsesWavefrontBase) { amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); amdgpu::addr_calc::flat_calculate_addresses(inst, *wf, d); - EXPECT_EQ(d.lane_mask, 1ULL); - // scratch_base (0x1_0000_0000) + VGPR (0x100) + offset (0x10) = 0x1_0000_0110 - EXPECT_EQ(d.per_lane_addr[0], SCRATCH_BASE + 0x100 + 0x10); + EXPECT_EQ(d.lane_mask, 0x3ULL); + // Scratch is stored in the hardware dword-interleaved ("swizzled") layout that + // rocm-dbgapi reads (rocdbgapi memory.cpp private_swizzled): + // addr = scratch_base + (off/4)*lane_count*4 + lane*4 + off%4 + // with off = VGPR + offset = 0x100 + 0x10 = 0x110 and lane_count = 64: + // (0x110/4)*64*4 = 0x44 * 256 = 0x4400; lane 0 -> +0, lane 1 -> +4. + constexpr uint64_t kSwizzledBase = SCRATCH_BASE + 0x4400; + EXPECT_EQ(d.per_lane_addr[0], kSwizzledBase + 0); + EXPECT_EQ(d.per_lane_addr[1], kSwizzledBase + 4); + EXPECT_TRUE(d.scratch_swizzle); + EXPECT_EQ(d.scratch_addr_stride, 64u * sizeof(uint32_t)); +} + +TEST(ScratchAddrCalcTest, FlatScratchSignExtendsScalarStackOffset) { + amdgpu::GpuMemory mem("signed_scratch_mem"); + amdgpu::L2Cache l2("signed_scratch_l2"); + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = ROCJITSU_CODE_ARCH_CDNA4; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = 104; + cfg.vgprs_per_wf = 16; + cfg.lds_size_kb = 64; + auto cu = amdgpu::ComputeUnitCore::create("signed_scratch_cu", cfg, &mem, &l2); + ASSERT_NE(cu, nullptr); + + auto *wf = cu->dispatch_wf(0, 0, 104, 16); + ASSERT_NE(wf, nullptr); + constexpr uint64_t kScratchBase = 0x1'0000'0000ULL; + wf->set_scratch_base(kScratchBase); + wf->set_exec(1); + + const uint32_t vbase = wf->vgpr_alloc().base; + const uint32_t sbase = wf->sgpr_alloc().base; + cu->write_vgpr(vbase, 0, 0x40); + cu->write_sgpr(sbase + 32, static_cast(-0x20)); + + cdna4::FlatScratchMachineInst inst{}; + inst.seg = 1; + inst.sve = 1; + inst.saddr = 32; + inst.addr = 0; + inst.offset = 0; + + amdgpu::VectorMemState d(amdgpu::GLOBAL_MEM); + amdgpu::addr_calc::flat_calculate_addresses(inst, *wf, d); + + // Private offset is 0x40 + (-0x20) = 0x20. In the wave64 dword-swizzled + // layout lane 0 therefore starts 8 rows (8 * 64 * 4 bytes) above the base. + EXPECT_EQ(d.per_lane_addr[0], kScratchBase + 0x800); } TEST(ScratchAddrCalcTest, FlatGlobalDoesNotUseScratchBase) { @@ -4933,4 +5110,28 @@ TEST(RdnaVectorLaneReadTest, ReadlaneFamilyUsesDecodedSourceVgprPerWave) { } } +// A VOP3 output modifier scales the result. INEXACT must be derived from the +// scaled exact value, not by comparing the scaled result against the unscaled +// product -- that comparison is unequal for every nonzero product as soon as +// any modifier is present, and a spurious INEXACT with MODE.excp_en set stops +// the wave for the debugger on arithmetic that was exact. +TEST(AluExceptionTest, OutputModifierDoesNotFabricateInexact) { + constexpr uint32_t kInexact = 1u << 5; + + // 2.0 * 3.0 == 6.0 exactly, and stays exact under every OMOD scale. + EXPECT_EQ(amdgpu::classify_mul_f32(2.0f, 3.0f) & kInexact, 0u); + for (float scale : {2.0f, 4.0f, 0.5f}) + EXPECT_EQ(amdgpu::classify_mul_f32(2.0f, 3.0f, scale) & kInexact, 0u) << "omod scale " << scale; + + // A genuinely inexact product stays reported, with and without a modifier. + EXPECT_EQ(amdgpu::classify_mul_f32(1.1f, 1.1f) & kInexact, kInexact); + EXPECT_EQ(amdgpu::classify_mul_f32(1.1f, 1.1f, 2.0f) & kInexact, kInexact); + + // NaN compares unequal to itself, so an exactness test that does not exclude + // non-finite values reports INEXACT for it even with no modifier at all. + const float nan = std::numeric_limits::quiet_NaN(); + EXPECT_EQ(amdgpu::classify_mul_f32(nan, 3.0f) & kInexact, 0u); + EXPECT_EQ(amdgpu::classify_mul_f32(nan, 3.0f, 2.0f) & kInexact, 0u); +} + } // namespace diff --git a/emulation/rocjitsu/tests/simdojo_sim_test.cpp b/emulation/rocjitsu/tests/simdojo_sim_test.cpp index 62af7800f35f..e28703e079d1 100644 --- a/emulation/rocjitsu/tests/simdojo_sim_test.cpp +++ b/emulation/rocjitsu/tests/simdojo_sim_test.cpp @@ -688,6 +688,33 @@ TEST(TerminationTest, RequestExitWakesAllPartitions) { EXPECT_EQ(exit_status.reason, ExitReason::EXIT_REQUEST); } +// Regression: the host thread calling request_exit() must not touch the partition +// contexts while the engine thread is destroying them in shutdown(). The daemon does +// exactly this - teardown() requests exit while the VM thread may already be shutting +// down after the guest exited - which TSan caught as a data race and a use-after-free +// on the partition's idle_wakeup_ flag. +TEST(TerminationTest, RequestExitRacingShutdownIsSafe) { + // Single-threaded mode is what arms the wake path that dereferences contexts_[0]. + // Iterate: the two threads must interleave inside the narrow shutdown window. + for (int iter = 0; iter < 200; ++iter) { + SimulationEngine engine({.num_threads = 1}); + auto root = std::make_unique("root"); + root->add_child(std::make_unique("c0", 4)); + engine.topology().set_root(std::move(root)); + engine.create(); + + // Mirrors rj_vm_run(): run to self-termination, then tear the contexts down. + std::thread runner([&engine]() { + engine.run(); + engine.shutdown(); + }); + + // Mirrors the daemon teardown path landing concurrently with that shutdown. + engine.request_exit("test stop"); + runner.join(); + } +} + TEST(TerminationTest, StepModeConsistency) { SimulationEngine engine({.num_threads = 1}); auto root = std::make_unique("root"); diff --git a/emulation/rocjitsu/tests/sparse_memory_test.cpp b/emulation/rocjitsu/tests/sparse_memory_test.cpp index b524c005cbca..e173e0b6d265 100644 --- a/emulation/rocjitsu/tests/sparse_memory_test.cpp +++ b/emulation/rocjitsu/tests/sparse_memory_test.cpp @@ -113,6 +113,34 @@ TEST(SparseMemoryTest, UnalignedBlockRoundTripCrossesPageBoundary) { EXPECT_EQ(memory.num_pages(), 2u); } +TEST(SparseMemoryTest, HasPageSeesPagesWrittenThroughEveryStripe) { + simdojo::SparseMemory memory("memory"); + constexpr uint64_t kPageSize = simdojo::SparseMemory::PAGE_SIZE; + + // has_page() has to use the same key the storage does -- the aligned byte + // address, not the page number. Keying it on `addr >> PAGE_SHIFT` reported + // every page above the first as absent, which made GpuMemory::is_fetchable() + // deny instruction fetches that were backed only by sparse memory. + const uint64_t addr = 0x400000u + 37u; + EXPECT_FALSE(memory.has_page(addr)); + memory.write8(addr, 0x5Au); + EXPECT_TRUE(memory.has_page(addr)); + + // Every offset within the page reports the same backing, and the neighbours + // stay absent. + EXPECT_TRUE(memory.has_page(addr & ~simdojo::SparseMemory::PAGE_MASK)); + EXPECT_TRUE(memory.has_page((addr & ~simdojo::SparseMemory::PAGE_MASK) + kPageSize - 1)); + EXPECT_FALSE(memory.has_page(addr + kPageSize)); + EXPECT_FALSE(memory.has_page(addr - kPageSize)); + + // Spread across many pages so the answer cannot come from one lucky stripe: + // the old page-number key collided with the aligned key only at address 0. + for (uint64_t page = 0; page < 64; ++page) + memory.write8(page * kPageSize + 8u, static_cast(page)); + for (uint64_t page = 0; page < 64; ++page) + EXPECT_TRUE(memory.has_page(page * kPageSize + 8u)) << "page " << page; +} + TEST(SparseMemoryThreadingTest, ConcurrentOverlappingBlocksRemainAtomicPerPage) { simdojo::SparseMemory memory("memory"); diff --git a/emulation/rocjitsu/tests/sysfs_test.cpp b/emulation/rocjitsu/tests/sysfs_test.cpp index 767e66ccd12a..f484aedf0a8c 100644 --- a/emulation/rocjitsu/tests/sysfs_test.cpp +++ b/emulation/rocjitsu/tests/sysfs_test.cpp @@ -12,6 +12,8 @@ #include "rocjitsu/kmd/linux/sysfs.h" #include "rocjitsu/config/config_loader.h" +#include "rocjitsu/kmd/linux/amdgpu_properties.h" +#include "rocjitsu/kmd/linux/cwsr.h" #include "rocjitsu/kmd/linux/kfd_topology.h" #include "rocjitsu/vm/soc.h" @@ -143,8 +145,15 @@ TEST(SysfsTopologyDebugCapabilityTest, PerGfxipDebugBitsMatchDriver) { const uint32_t cap2 = static_cast(props["capability2"]); const uint64_t dp = props["debug_prop"]; - // Base trap-debugger support is advertised on every simulated GPU. - EXPECT_TRUE(cap & HSA_CAP_TRAP_DEBUG_SUPPORT); + // Base trap-debugger support is advertised on every GPU the CWSR codec can + // produce a record for, and withheld on the rest: rocdbgapi reads wave state + // out of the save area, so an agent whose record layout the simulator does + // not model cannot be serviced and must be declined at attach rather than at + // every wave stop. The sub-capabilities below stay driver-derived either + // way; they describe a support that is simply no longer claimed. + EXPECT_EQ(static_cast(cap & HSA_CAP_TRAP_DEBUG_SUPPORT), + rocjitsu::kmd::cwsr_layout_modelled_for_gc_ip_version( + rocjitsu::kmd::gc_ip_version_for_gfx_target_version(e.gfx_target_version))); EXPECT_TRUE(cap & HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED); EXPECT_TRUE(cap & HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED); EXPECT_TRUE(cap & HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED); @@ -170,7 +179,10 @@ TEST(SysfsTopologyDebugCapabilityTest, PerGfxipDebugBitsMatchDriver) { } TEST(SysfsTopologyDebugCapabilityTest, ExplicitCapabilityAndDebugPropArePreserved) { - Sysfs::GpuInfo gpu = make_gpu_info(110000u /* gfx1100 */); + // gfx942, so the trap-debug bit survives the override and this stays a test + // about the override rather than about the CWSR gate; the gfx1100 case is + // CapturedCapabilityCannotReadvertiseUnservicableTrapDebug's. + Sysfs::GpuInfo gpu = make_gpu_info(90402u /* gfx942 */); gpu.capability = HSA_CAP_TRAP_DEBUG_SUPPORT; gpu.capability2 = HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED; gpu.debug_prop = HSA_DBG_DISPATCH_INFO_ALWAYS_VALID; @@ -496,8 +508,21 @@ TEST(SysfsTopologyDebugCapabilityTest, ConfigTopologyMatchesRealHardware) { // The synthetic topology re-derives the HSA_CAP_ASIC_REVISION field from the // config's revision_id, so compare the feature bits with that field masked // out (the captured dumps carry the physical part's revision there). - const uint32_t asic_mask = static_cast(HSA_CAP_ASIC_REVISION_MASK); + // + // HSA_CAP_TRAP_DEBUG_SUPPORT is masked out for a different reason: it is the + // one bit the simulator deliberately does not reproduce faithfully. A part + // whose CWSR record layout the codec cannot produce is not debuggable here + // however debuggable the physical device is, so the bit is withheld and + // checked below against the gate instead of against the dump. + const uint32_t asic_mask = static_cast(HSA_CAP_ASIC_REVISION_MASK) | + static_cast(HSA_CAP_TRAP_DEBUG_SUPPORT); EXPECT_EQ(static_cast(props["capability"]) & ~asic_mask, e->capability & ~asic_mask); + EXPECT_TRUE(e->capability & HSA_CAP_TRAP_DEBUG_SUPPORT) + << "the physical part advertises it, so the simulator's value is a real deviation"; + EXPECT_EQ( + static_cast(static_cast(props["capability"]) & HSA_CAP_TRAP_DEBUG_SUPPORT), + kmd::cwsr_layout_modelled_for_gc_ip_version( + kmd::gc_ip_version_for_gfx_target_version(loaded.device.gfx_target_version))); EXPECT_EQ(static_cast(props["capability2"]), e->capability2); EXPECT_EQ(props["debug_prop"], e->debug_prop); } diff --git a/emulation/rocjitsu/tests/wave_debug_test.cpp b/emulation/rocjitsu/tests/wave_debug_test.cpp new file mode 100644 index 000000000000..60e3b7b9bf86 --- /dev/null +++ b/emulation/rocjitsu/tests/wave_debug_test.cpp @@ -0,0 +1,1435 @@ +// Copyright (c) 2026 Advanced Micro Devices, Inc. +// SPDX-License-Identifier: MIT + +/// @file wave_debug_test.cpp +/// @brief Wave-level KFD debugger groundwork, exercised through the compute unit. + +#include "rocjitsu/vm/amdgpu/compute_unit.h" +#include "rocjitsu/vm/amdgpu/gpu_memory.h" +#include "rocjitsu/vm/amdgpu/l2_cache.h" +#include "rocjitsu/vm/amdgpu/spi.h" +#include "rocjitsu/vm/amdgpu/wavefront.h" + +#include "rocjitsu/kmd/linux/cwsr.h" + +#include + +#include +#include +#include +#include +#include +#include +#include + +namespace { + +using namespace rocjitsu; + +constexpr uint32_t SGPRS_PER_WF = 106; +constexpr uint32_t VGPRS_PER_WF = 64; +constexpr uint32_t kKernelAddr = 0x1000; +constexpr uint32_t kTrapHandlerAddr = 0x2000; +constexpr uint32_t kSTrapBreakpoint = 0xBF920001u; // s_trap 1 (rocm-dbgapi breakpoint) +constexpr uint32_t kSTrapSeven = 0xBF92AB07u; // s_trap 0xab07 (trap id is low 8 bits) +constexpr uint32_t kGfx1250STrap = 0xBF900003u; // s_trap 3 on gfx12.5 +constexpr uint32_t kSEndpgm = 0xBF810000u; // s_endpgm + +struct WaveDebugFixture { + amdgpu::GpuMemory gpu_mem; + amdgpu::L2Cache l2; + std::unique_ptr cu; + amdgpu::Wavefront *wf = nullptr; + + explicit WaveDebugFixture(rj_code_arch_t arch = ROCJITSU_CODE_ARCH_CDNA4) + : gpu_mem("wave_debug_mem"), l2("wave_debug_l2") { + amdgpu::ComputeUnitCore::Config cfg{}; + cfg.arch = arch; + cfg.num_wf_slots = 1; + cfg.sgprs_per_wf = SGPRS_PER_WF; + cfg.vgprs_per_wf = VGPRS_PER_WF; + cfg.lds_size_kb = 64; + cu = amdgpu::ComputeUnitCore::create("cu_wave_debug", cfg, &gpu_mem, &l2); + } + + amdgpu::Wavefront *dispatch(uint64_t pc) { + wf = cu->dispatch_wf(0, pc, SGPRS_PER_WF, VGPRS_PER_WF); + return wf; + } +}; + +TEST(WaveDebugTest, STrapExecutesConfiguredTrapHandlerInstructions) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + // Assembled for gfx950. The handler writes a proof value to TTMP4, + // advances the saved PC, restores STATUS.HALT, emits MSG_INTERRUPT, and + // returns through s_rfe_b64. + const uint32_t handler[] = { + 0xBEF000FFu, 0x12345678u, // s_mov_b32 ttmp4, 0x12345678 + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEF800FFu, 0x00002000u, // s_mov_b32 ttmp12, STATUS.HALT + 0xBF900001u, // s_sendmsg sendmsg(MSG_INTERRUPT) + 0xB978F802u, // s_setreg_b32 hwreg(HW_REG_STATUS), ttmp12 + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0x3000, true}; + }); + uint32_t interrupt_count = 0; + fx.cu->set_sendmsg_handler([&](amdgpu::Wavefront &, uint32_t message) { + if (message == 1) + ++interrupt_count; + return message == 1; + }); + uint32_t completion_count = 0; + fx.cu->set_trap_completion_handler([&](amdgpu::Wavefront &) { ++completion_count; }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + + fx.cu->step(); + ASSERT_TRUE(wf->in_trap_handler()); + EXPECT_EQ(wf->pc, kTrapHandlerAddr); + EXPECT_EQ(wf->ttmp(0), kKernelAddr); + EXPECT_EQ(wf->ttmp(1), 1u << 16); + EXPECT_EQ(wf->ttmp(14), 0x3000u); + + for (int i = 0; i < 7; ++i) + fx.cu->step(); + + EXPECT_FALSE(wf->in_trap_handler()); + EXPECT_TRUE(wf->debug_halted()); + EXPECT_EQ(wf->pc, kKernelAddr + 4); + EXPECT_EQ(wf->ttmp(4), 0x12345678u); + EXPECT_EQ(interrupt_count, 1u); + EXPECT_EQ(completion_count, 1u); +} + +// The ROCr handler temporarily reuses EXEC_LO for MSG_GET_DOORBELL. The wave +// must be reported with the interrupted lane mask, not the handler's doorbell +// response, or resuming a breakpoint changes which lanes execute user code. +TEST(WaveDebugTest, TrapHandlerRestoresInterruptedExecBeforeReporting) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + const uint32_t handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEFE00FFu, 0x80000000u, // s_mov_b32 exec_lo, 0x80000000 + 0xBF90000Au, // s_sendmsg sendmsg(MSG_GET_DOORBELL) + 0xBEF800FFu, 0x00002000u, // s_mov_b32 ttmp12, STATUS.HALT + 0xBF900001u, // s_sendmsg sendmsg(MSG_INTERRUPT) + 0xB978F802u, // s_setreg_b32 hwreg(HW_REG_STATUS), ttmp12 + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, true}; + }); + fx.cu->set_sendmsg_handler([](amdgpu::Wavefront &wave, uint32_t message) { + if (message == 10) + wave.set_exec((wave.exec() & 0xFFFFFFFF00000000ULL) | 7u); + return message == 1 || message == 10; + }); + + constexpr uint64_t kInterruptedExec = 0x00FF00FF00FF00FFULL; + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_exec(kInterruptedExec); + + for (int i = 0; i < 9 && !wf->debug_halted(); ++i) + fx.cu->step(); + + ASSERT_TRUE(wf->debug_halted()); + EXPECT_EQ(wf->exec(), kInterruptedExec); +} + +// Restoring the interrupted EXEC belongs to returning from the handler, not to +// stopping for a debugger. A handler that returns without stopping the wave +// used to leave its own mask installed, and nothing later put the +// application's back: the kernel ran on with every lane active, silently +// un-diverging a branch. gdb.rocm/lane-info.exp catches it as lanes that had +// converged out of a branch being reported active again. +TEST(WaveDebugTest, TrapHandlerRestoresInterruptedExecWhenReturningWithoutStopping) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + // Same shape as the handler above with the halt removed, so the wave runs on + // after s_rfe instead of stopping. + const uint32_t handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEFE00FFu, 0x80000000u, // s_mov_b32 exec_lo, 0x80000000 + 0xBF90000Au, // s_sendmsg sendmsg(MSG_GET_DOORBELL) + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, true}; + }); + fx.cu->set_sendmsg_handler([](amdgpu::Wavefront &wave, uint32_t message) { + if (message == 10) + wave.set_exec((wave.exec() & 0xFFFFFFFF00000000ULL) | 7u); + return message == 1 || message == 10; + }); + + // Lanes 0, 2 and 4 of a five-lane wave, the shape lane-info.exp produces. + constexpr uint64_t kInterruptedExec = 0x15ULL; + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_exec(kInterruptedExec); + + for (int i = 0; i < 6 && wf->pc == kKernelAddr; ++i) + fx.cu->step(); + // Every assertion below is satisfied by a wave that never entered the handler + // at all -- EXEC is unmodified, nothing halts it for the debugger, and + // s_endpgm ends it. Anchor on the handler actually running, or a regression + // that stops dispatching into it passes this test. + ASSERT_TRUE(wf->in_trap_handler()); + for (int i = 0; i < 6 && wf->in_trap_handler(); ++i) + fx.cu->step(); + + ASSERT_FALSE(wf->in_trap_handler()); + EXPECT_FALSE(wf->debug_halted()); + EXPECT_EQ(wf->exec(), kInterruptedExec); + + // Run the wave off the end. Leaving one resident past the fixture is not + // inert: the CU pool-allocates decoded instructions and frees the pool with + // the decoder. + for (int i = 0; i < 4 && !wf->is_halted(); ++i) + fx.cu->step(); + EXPECT_TRUE(wf->is_halted()); +} + +TEST(WaveDebugTest, UnmappedInstructionFetchReportsMemoryViolationAtBranchTarget) { + WaveDebugFixture fx; + constexpr uint32_t kProcessId = 7; + constexpr uint64_t kBranchTarget = 0x100; + std::vector kernel_page(amdgpu::GpuMemory::PAGE_SIZE); + KfdProcess::PageTable page_table; + std::shared_mutex page_table_mutex; + page_table[kKernelAddr >> amdgpu::GpuMemory::PAGE_SHIFT] = {kernel_page.data(), + amdgpu::Mtype::RW}; + fx.gpu_mem.register_process(kProcessId, &page_table, &page_table_mutex); + + fx.gpu_mem.write32(kKernelAddr, 0xBE801D00u, kProcessId); // s_setpc_b64 s[0:1] + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_process_id(kProcessId); + fx.cu->write_sgpr(wf->sgpr_alloc().base, static_cast(kBranchTarget)); + fx.cu->write_sgpr(wf->sgpr_alloc().base + 1, 0); + + uint64_t fault_address = 0; + fx.cu->set_memory_violation_handler( + [&](amdgpu::Wavefront &faulting_wave, uint64_t address, bool is_write) { + EXPECT_EQ(&faulting_wave, wf); + EXPECT_FALSE(is_write); + fault_address = address; + faulting_wave.debug_trap(0); + return true; + }); + + fx.cu->step(); + EXPECT_EQ(wf->pc, kBranchTarget); + EXPECT_FALSE(wf->debug_halted()); + + fx.cu->step(); + EXPECT_EQ(fault_address, kBranchTarget); + EXPECT_TRUE(wf->debug_halted()); + EXPECT_EQ(wf->pc, kBranchTarget); + + fx.gpu_mem.unregister_process(kProcessId); +} + +TEST(WaveDebugTest, UnmappedScalarLoadReportsMemoryViolationAfterInstruction) { + WaveDebugFixture fx; + constexpr uint32_t kProcessId = 7; + std::vector kernel_page(amdgpu::GpuMemory::PAGE_SIZE); + KfdProcess::PageTable page_table; + std::shared_mutex page_table_mutex; + page_table[kKernelAddr >> amdgpu::GpuMemory::PAGE_SHIFT] = {kernel_page.data(), + amdgpu::Mtype::RW}; + fx.gpu_mem.register_process(kProcessId, &page_table, &page_table_mutex); + + fx.gpu_mem.write32(kKernelAddr, 0xC0000000u, kProcessId); // s_load_dword s0, s[0:1] + fx.gpu_mem.write32(kKernelAddr + 4, 0, kProcessId); // immediate offset 0 + fx.gpu_mem.write32(kKernelAddr + 8, 0xBF800000u, kProcessId); // s_nop 0 + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + wave->set_process_id(kProcessId); + fx.cu->set_debug_active(true); + + uint64_t fault_address = ~uint64_t{0}; + fx.cu->set_memory_violation_handler( + [&](amdgpu::Wavefront &faulting_wave, uint64_t address, bool is_write) { + EXPECT_EQ(&faulting_wave, wave); + EXPECT_FALSE(is_write); + fault_address = address; + faulting_wave.debug_trap(0); + return true; + }); + + fx.cu->step(); + EXPECT_EQ(fault_address, 0u); + EXPECT_TRUE(wave->debug_halted()); + EXPECT_EQ(wave->pc, kKernelAddr + 8); + + fx.gpu_mem.unregister_process(kProcessId); +} + +// Runtime suspension (queue_percentage 0) and debugger suspension overlap in +// time and are lifted by different actors. Representing both with one wave bit +// let a runtime resume clear a debugger pause, and a debugger or CWSR resume +// clear an active runtime pause -- in either case the wave started running +// while something still meant it to be stopped. +TEST(WaveDebugTest, RuntimeAndDebuggerSuspensionDoNotClobberEachOther) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSEndpgm); + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + ASSERT_FALSE(wave->debug_paused()); + + // Both reasons applied; releasing either one alone must not resume the wave. + wave->set_runtime_suspended(true); + wave->set_debug_suspended(true); + EXPECT_TRUE(wave->debug_paused()); + + wave->set_debug_suspended(false); + EXPECT_TRUE(wave->runtime_suspended()); + EXPECT_TRUE(wave->debug_paused()) << "a debugger resume lifted the runtime pause"; + + wave->set_runtime_suspended(false); + EXPECT_FALSE(wave->debug_paused()); + + // And the other way round. + wave->set_runtime_suspended(true); + wave->set_debug_suspended(true); + wave->set_runtime_suspended(false); + EXPECT_TRUE(wave->debug_suspended()); + EXPECT_TRUE(wave->debug_paused()) << "a runtime resume lifted the debugger pause"; + + // A halt is a third, independent reason. + wave->set_debug_suspended(false); + wave->set_debug_halted(true); + EXPECT_TRUE(wave->debug_paused()); +} + +// Trap entry and CWSR must agree on where a wave's dispatch identity lives, or +// rocm-dbgapi correlates the stopped wave to the wrong workgroup. On the gfx9 +// layout that is TTMP8/9/10 = workgroup id x/y/z, which is exactly what +// cwsr.cpp serializes; trap entry used to write the flat wg_id() into TTMP8 and +// zero the other two. +TEST(WaveDebugTest, TrapEntryPublishesTheWorkgroupCoordinateCwsrSerializes) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + fx.gpu_mem.write32(kTrapHandlerAddr, kSEndpgm); + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, true}; + }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_wg_coord(3, 5, 7); + + fx.cu->step(); + ASSERT_TRUE(wf->in_trap_handler()); + + const auto &wg = wf->wg_coord(); + EXPECT_EQ(wf->ttmp(8), wg[0]); + EXPECT_EQ(wf->ttmp(9), wg[1]); + EXPECT_EQ(wf->ttmp(10), wg[2]); + EXPECT_EQ(wf->ttmp(9), 5u) << "the y coordinate was zeroed on trap entry"; + EXPECT_EQ(wf->ttmp(10), 7u) << "the z coordinate was zeroed on trap entry"; +} + +// S_SENDMSGHALT halts the wave -- that is the instruction, not a debugger +// artefact. It has to publish the architectural STATUS.HALT and not only the +// scheduler's private flag, because s_rfe reads STATUS.HALT on the way out of +// the handler to decide whether the wave stays stopped. With only the private +// flag set, s_rfe saw 0 for a wave s_sendmsghalt had already halted and left +// single-step armed, so resuming took an extra step. +TEST(WaveDebugTest, SendmsghaltPublishesArchitecturalStatusHalt) { + WaveDebugFixture fx; + constexpr uint32_t kStatusHalt = 1u << 13; + constexpr uint32_t kSSendmsghaltInterrupt = 0xBF910001u; // s_sendmsghalt sendmsg(MSG_INTERRUPT) + + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + const uint32_t handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + kSSendmsghaltInterrupt, // s_sendmsghalt sendmsg(MSG_INTERRUPT) + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, true}; + }); + fx.cu->set_sendmsg_handler([](amdgpu::Wavefront &, uint32_t message) { return message == 1; }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_debug_single_step(true); + + fx.cu->step(); // s_trap -> handler + ASSERT_TRUE(wf->in_trap_handler()); + ASSERT_EQ(wf->status_raw() & kStatusHalt, 0u) << "STATUS.HALT set before s_sendmsghalt"; + + for (int i = 0; i < 3 && !wf->debug_halted(); ++i) + fx.cu->step(); + + EXPECT_TRUE(wf->debug_halted()); + EXPECT_NE(wf->status_raw() & kStatusHalt, 0u) + << "s_sendmsghalt halted the wave without publishing STATUS.HALT"; + // Which instruction raised the bit is the only thing that separates this stop + // from a handler that raised HALT with s_setreg and then returned. The two + // want opposite treatment on resume and are identical in the CWSR record. + EXPECT_TRUE(wf->self_halted()) + << "s_sendmsghalt raised STATUS.HALT without recording that it did"; +} + +// The other origin of STATUS.HALT. The ROCr handler raises it through s_setreg +// on the way out, and there the bit means "keep this wave stopped" -- so a +// resume must not clear it. Nothing in the CWSR record distinguishes that from +// a wave halted at s_sendmsghalt, which wants exactly the opposite, so the +// provenance marker has to come out clear on this path. +TEST(WaveDebugTest, HandlerSetregHaltIsNotAttributedToSendmsghalt) { + WaveDebugFixture fx; + constexpr uint32_t kStatusHalt = 1u << 13; + + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + // SOPK s_setreg_imm32_b32 (op 20), hwreg id 2 = STATUS, offset 13, size 1 -- + // simm16 = 2 | (13 << 6) = 0x342. This is the ROCr handler's halt sequence. + const uint32_t handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBA000342u, 0x00000001u, // s_setreg_imm32_b32 hwreg(STATUS, 13, 1), 1 + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, true}; + }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + + fx.cu->step(); // s_trap -> handler + ASSERT_TRUE(wf->in_trap_handler()); + + for (int i = 0; i < 4 && !wf->debug_halted(); ++i) + fx.cu->step(); + + ASSERT_NE(wf->status_raw() & kStatusHalt, 0u) << "the handler's s_setreg did not raise HALT"; + EXPECT_FALSE(wf->self_halted()) + << "a handler-raised HALT was attributed to s_sendmsghalt, so a resume would clear it " + "and lose the breakpoint"; +} + +// Provenance is per stop, not per wave. A marker left behind by a resumed +// s_sendmsghalt would make the *next* stop -- one the handler halted with +// s_setreg -- look self-halted, and the resume after that would clear a HALT it +// must leave alone. +TEST(WaveDebugTest, SelfHaltedMarkerDoesNotSurviveTheStopThatSetIt) { + WaveDebugFixture fx; + constexpr uint32_t kSSendmsghaltInterrupt = 0xBF910001u; + + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + const uint32_t handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + kSSendmsghaltInterrupt, // s_sendmsghalt sendmsg(MSG_INTERRUPT) + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, true}; + }); + fx.cu->set_sendmsg_handler([](amdgpu::Wavefront &, uint32_t message) { return message == 1; }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + + fx.cu->step(); // s_trap -> handler + for (int i = 0; i < 3 && !wf->self_halted(); ++i) + fx.cu->step(); + ASSERT_TRUE(wf->self_halted()); + + // What a debugger resume does: drop both halves of the stop, then let the + // handler return. + wf->set_status_halt(false); + wf->set_self_halted(false); + wf->set_debug_halted(false); + for (int i = 0; i < 3 && wf->in_trap_handler(); ++i) + fx.cu->step(); + ASSERT_FALSE(wf->in_trap_handler()) << "the handler never returned"; + EXPECT_FALSE(wf->self_halted()); + + for (int i = 0; i < 4 && !wf->is_halted(); ++i) + fx.cu->step(); + EXPECT_TRUE(wf->is_halted()); +} + +// S_SENDMSGHALT with nobody attached. The instruction halts the wave whether or +// not a debugger is there to resume it, so the flags it raises must be exactly +// the same ones a debugger stop raises -- and no more. What this pins is that +// an undebugged run does not diverge: the halt is a stop, not a corruption. The +// wave keeps the interrupted EXEC rather than running on under the handler's +// mask, its slot is not silently retired behind the halt, and clearing the two +// halves of the stop -- which is all a session release does -- puts it back on +// the scheduler and lets it retire. +TEST(WaveDebugTest, SendmsghaltWithoutADebugSessionHaltsAndStaysReleasable) { + WaveDebugFixture fx; + constexpr uint32_t kStatusHalt = 1u << 13; + constexpr uint32_t kSSendmsghaltInterrupt = 0xBF910001u; + constexpr uint64_t kApplicationExec = 0x5u; + + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + // The handler runs under its own mask, the way the real one does on its way + // to MSG_INTERRUPT, so a lost EXEC restore is visible here. + const uint32_t handler[] = { + 0x806C846Cu, // s_add_u32 ttmp0, ttmp0, 4 + 0x826D806Du, // s_addc_u32 ttmp1, ttmp1, 0 + 0xBEFE00FFu, + 0x80000000u, // s_mov_b32 exec_lo, 0x80000000 + kSSendmsghaltInterrupt, // s_sendmsghalt sendmsg(MSG_INTERRUPT) + 0xBE801F6Cu, // s_rfe_b64 ttmp[0:1] + }; + for (uint32_t i = 0; i < std::size(handler); ++i) + fx.gpu_mem.write32(kTrapHandlerAddr + i * 4, handler[i]); + + // debug_enabled clear: no debugger, so TTMP13 bit 23 stays 0 and nothing in + // the driver is watching this wave. + fx.cu->set_trap_handler_resolver([](const amdgpu::Wavefront &) { + return amdgpu::ComputeUnitCore::TrapHandlerConfig{kTrapHandlerAddr, 0, false}; + }); + fx.cu->set_sendmsg_handler([](amdgpu::Wavefront &, uint32_t message) { return message == 1; }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_exec(kApplicationExec); + + fx.cu->step(); // s_trap -> handler + ASSERT_TRUE(wf->in_trap_handler()); + + for (int i = 0; i < 6 && !wf->debug_halted(); ++i) + fx.cu->step(); + + EXPECT_TRUE(wf->debug_halted()) << "s_sendmsghalt did not halt an undebugged wave"; + EXPECT_NE(wf->status_raw() & kStatusHalt, 0u); + EXPECT_TRUE(wf->self_halted()) + << "an undebugged s_sendmsghalt must record provenance too, or the release below " + "leaves STATUS.HALT set and the wave re-halts at s_rfe"; + EXPECT_FALSE(wf->is_halted()) << "the slot was retired behind a wave that is only stopped"; + + // Stepping a stopped wave must not advance it, with or without a debugger. + const uint64_t stopped_pc = wf->pc; + fx.cu->step(); + EXPECT_EQ(wf->pc, stopped_pc); + + // What a session release does: drop both halves of the stop. Nothing else is + // needed to make the wave runnable again. + wf->set_status_halt(false); + wf->set_self_halted(false); + wf->set_debug_halted(false); + for (int i = 0; i < 3 && wf->in_trap_handler(); ++i) + fx.cu->step(); + ASSERT_FALSE(wf->in_trap_handler()) << "the handler never returned"; + EXPECT_EQ(wf->exec(), kApplicationExec) + << "the application resumed under the handler's EXEC mask"; + + for (int i = 0; i < 4 && !wf->is_halted(); ++i) + fx.cu->step(); + EXPECT_TRUE(wf->is_halted()) << "the wave never retired, so its dispatch cannot complete"; +} + +// The CWSR codec reproduces the gfx9.4 record layout only, and the differences +// elsewhere are not confined to one field. Serializing a wave from an +// unmodelled architecture would hand rocm-dbgapi an image it decodes against a +// different layout, so the codec has to say plainly which ones it covers. +TEST(WaveDebugTest, CwsrLayoutIsModelledOnlyForTheGfx94Parts) { + EXPECT_TRUE(kmd::cwsr_layout_modelled(ROCJITSU_CODE_ARCH_CDNA3)); // gfx942 + EXPECT_TRUE(kmd::cwsr_layout_modelled(ROCJITSU_CODE_ARCH_CDNA4)); // gfx950 + + // gfx908 saves an ACC-VGPR block and gfx908/gfx90a keep the packet id in + // TTMP6, so being gfx9 is not enough. + EXPECT_FALSE(kmd::cwsr_layout_modelled(ROCJITSU_CODE_ARCH_CDNA1)); + EXPECT_FALSE(kmd::cwsr_layout_modelled(ROCJITSU_CODE_ARCH_CDNA2)); + + // RDNA and GFX12.5 differ in the control stack, the COMPUTE_RELAUNCH fields, + // the wave size behind the VGPR stride, and where dispatch identity lives. + for (rj_code_arch_t arch : + {ROCJITSU_CODE_ARCH_RDNA1, ROCJITSU_CODE_ARCH_RDNA2, ROCJITSU_CODE_ARCH_RDNA3, + ROCJITSU_CODE_ARCH_RDNA3_5, ROCJITSU_CODE_ARCH_RDNA4, ROCJITSU_CODE_ARCH_CDNA5}) + EXPECT_FALSE(kmd::cwsr_layout_modelled(arch)) << "arch " << static_cast(arch); +} + +// TRAPSTS.EXCP is architecturally sticky, so "the bit changed" is not the same +// question as "this instruction raised the cause". Delivering on the rising +// edge went permanently quiet for any cause already latched -- including every +// cause raised before a debugger attached, since the handler declines then. +TEST(WaveDebugTest, EnabledExceptionIsDeliveredAfterAnEarlierDisabledOccurrence) { + WaveDebugFixture fx; + constexpr uint32_t kInvalidCause = 1u << 0; + constexpr uint32_t kOverflowCause = 1u << 3; + constexpr uint32_t kModeExcpEnShift = 12; + // v_mul_f32 v0, v0, v0 (VOP2 op 5, src0 = v0 = 256, vsrc1 = v0, vdst = v0) + constexpr uint32_t kVMulF32V0 = 0x0A000000u | 256u; + constexpr float kHuge = 1e38f; + + fx.gpu_mem.write32(kKernelAddr, kVMulF32V0); + fx.gpu_mem.write32(kKernelAddr + 4, kVMulF32V0); + fx.gpu_mem.write32(kKernelAddr + 8, kSEndpgm); + + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + wave->set_exec(1ULL); + const uint32_t vbase = wave->vgpr_alloc().base; + + uint32_t handler_calls = 0; + fx.cu->set_alu_exception_handler([&](amdgpu::Wavefront &) { + ++handler_calls; + return false; // observe delivery without stopping the wave + }); + + // First occurrence with overflow *not* enabled. Some other cause is enabled + // so the instruction takes the exception-aware path and latches TRAPSTS -- + // with no enable at all the generated body takes a SIMD fast path that skips + // the sticky update, which would not exercise the sticky-bit problem. + wave->set_mode_raw(kInvalidCause << kModeExcpEnShift); + fx.cu->write_vgpr(vbase + 0, 0, std::bit_cast(kHuge)); + fx.cu->step(); + EXPECT_EQ(handler_calls, 0u) << "overflow is not enabled yet"; + ASSERT_NE(wave->trapsts() & kOverflowCause, 0u) << "overflow was not latched"; + + // Software now enables overflow and repeats the operation. Hardware traps on + // this occurrence; a rising-edge test cannot, because the bit is already set. + wave->set_mode_raw(kOverflowCause << kModeExcpEnShift); + fx.cu->write_vgpr(vbase + 0, 0, std::bit_cast(kHuge)); + fx.cu->step(); + EXPECT_EQ(handler_calls, 1u) << "second, enabled occurrence was not delivered"; +} + +// debug_active_ is CU-wide, so the memory probe also runs for waves belonging to +// a process nobody is debugging. When the handler declines the stop for such a +// wave the access must still be issued -- discarding it silently lost stores and +// left loads' destination registers stale in an undebugged process. +TEST(WaveDebugTest, DeclinedMemoryViolationStillIssuesTheAccess) { + WaveDebugFixture fx; + constexpr uint32_t kProcessId = 11; + constexpr uint64_t kPageSize = amdgpu::GpuMemory::PAGE_SIZE; + constexpr uint64_t kUnmappedAddr = 0x900000; + + std::vector kernel_page(kPageSize); + KfdProcess::PageTable page_table; + std::shared_mutex page_table_mutex; + page_table[kKernelAddr >> amdgpu::GpuMemory::PAGE_SHIFT] = {kernel_page.data(), + amdgpu::Mtype::RW}; + fx.gpu_mem.register_process(kProcessId, &page_table, &page_table_mutex); + + fx.gpu_mem.write32(kKernelAddr, 0xC0000000u, kProcessId); // s_load_dword s0, s[0:1] + fx.gpu_mem.write32(kKernelAddr + 4, 0, kProcessId); // immediate offset 0 + fx.gpu_mem.write32(kKernelAddr + 8, 0xBF800000u, kProcessId); // s_nop 0 + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + wave->set_process_id(kProcessId); + // Another process turned debugging on for this CU; this wave is not debugged. + fx.cu->set_debug_active(true); + + // The declined access is expected to reach the pipeline, so the cache + // hierarchy needs its functional writeback path wired up. + fx.l2.set_backing_memory(&fx.gpu_mem); + + ASSERT_FALSE(fx.gpu_mem.is_mapped(kUnmappedAddr, kProcessId)); + const uint32_t sbase = wave->sgpr_alloc().base; + fx.cu->write_sgpr(sbase + 0, static_cast(kUnmappedAddr)); + fx.cu->write_sgpr(sbase + 1, static_cast(kUnmappedAddr >> 32)); + // A recognisable value at the unmapped address, which falls through to sparse + // backing, so a load that really issued can be told from one that did not. + fx.gpu_mem.write32(kUnmappedAddr, 0xFEEDFACEu, kProcessId); + + bool handler_called = false; + fx.cu->set_memory_violation_handler([&](amdgpu::Wavefront &, uint64_t, bool) { + handler_called = true; + return false; // no debug session for this wave's process + }); + + fx.cu->step(); + + EXPECT_TRUE(handler_called); + EXPECT_FALSE(wave->debug_halted()); + EXPECT_EQ(wave->pc, kKernelAddr + 8); + // The load was issued rather than discarded, so s0 holds what memory held. + EXPECT_EQ(fx.cu->read_sgpr(sbase + 0), 0xFEEDFACEu); + + fx.gpu_mem.unregister_process(kProcessId); +} + +// A multi-byte access that starts on a mapped page can still run off the end of +// it. Checking only the first byte let such an access through with no +// EC_QUEUE_WAVE_MEMORY_VIOLATION, so the whole touched range is validated. +TEST(WaveDebugTest, ScalarLoadStraddlingIntoUnmappedPageReportsMemoryViolation) { + WaveDebugFixture fx; + constexpr uint32_t kProcessId = 9; + constexpr uint64_t kPageSize = amdgpu::GpuMemory::PAGE_SIZE; + constexpr uint64_t kDataAddr = 0x40000; + + std::vector kernel_page(kPageSize); + std::vector data_page(kPageSize); + KfdProcess::PageTable page_table; + std::shared_mutex page_table_mutex; + page_table[kKernelAddr >> amdgpu::GpuMemory::PAGE_SHIFT] = {kernel_page.data(), + amdgpu::Mtype::RW}; + // Exactly one data page is mapped; the page above it deliberately is not. + page_table[kDataAddr >> amdgpu::GpuMemory::PAGE_SHIFT] = {data_page.data(), amdgpu::Mtype::RW}; + fx.gpu_mem.register_process(kProcessId, &page_table, &page_table_mutex); + + fx.gpu_mem.write32(kKernelAddr, 0xC0040000u, kProcessId); // s_load_dwordx2 s[0:1], s[0:1] + fx.gpu_mem.write32(kKernelAddr + 4, 0, kProcessId); // immediate offset 0 + fx.gpu_mem.write32(kKernelAddr + 8, 0xBF800000u, kProcessId); // s_nop 0 + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + wave->set_process_id(kProcessId); + fx.cu->set_debug_active(true); + + // Wired up so that failing to detect the straddle lets the access proceed + // through the pipeline, and the test then fails on the missing violation + // rather than on unbacked cache plumbing. + fx.l2.set_backing_memory(&fx.gpu_mem); + + // The last four bytes of the mapped page: the first dword is mapped, the + // second runs into the unmapped page above. + const uint64_t straddle = kDataAddr + kPageSize - 4; + ASSERT_TRUE(fx.gpu_mem.is_mapped(straddle, kProcessId)); + ASSERT_FALSE(fx.gpu_mem.is_mapped(straddle + 4, kProcessId)); + const uint32_t sbase = wave->sgpr_alloc().base; + fx.cu->write_sgpr(sbase + 0, static_cast(straddle)); + fx.cu->write_sgpr(sbase + 1, static_cast(straddle >> 32)); + + uint64_t fault_address = ~uint64_t{0}; + fx.cu->set_memory_violation_handler( + [&](amdgpu::Wavefront &faulting_wave, uint64_t address, bool is_write) { + EXPECT_EQ(&faulting_wave, wave); + EXPECT_FALSE(is_write); + fault_address = address; + faulting_wave.debug_trap(0); + return true; + }); + + fx.cu->step(); + EXPECT_EQ(fault_address, straddle); + EXPECT_TRUE(wave->debug_halted()); + + fx.gpu_mem.unregister_process(kProcessId); +} + +// Linked gfx950 code forms helper addresses as GETPC plus a signed rel32 +// relocation. The 64-bit sum can have a 0x1ffff high dword even though it +// denotes an address relative to the loaded code object. SWAPPC must relocate +// that value to the dispatch load bias and preserve the architectural return +// address for SETPC. +TEST(WaveDebugTest, SwappcResolvesLinkedRel32AndSetpcReturns) { + WaveDebugFixture fx; + constexpr uint64_t kLoadBias = 0x7FFF00000000ULL; + constexpr uint64_t kCallerPc = kLoadBias + 0xA3A8; + constexpr uint64_t kCalleePc = kLoadBias + 0x8D60; + + fx.gpu_mem.write32(kCallerPc, 0xBE9E1E00u); // s_swappc_b64 s[30:31], s[0:1] + fx.gpu_mem.write32(kCallerPc + 4, kSEndpgm); + fx.gpu_mem.write32(kCalleePc, 0xBE801D1Eu); // s_setpc_b64 s[30:31] + + auto *wf = fx.dispatch(kCallerPc); + ASSERT_NE(wf, nullptr); + wf->set_code_load_bias(kLoadBias); + // Linked gfx950 calls place GETPC, ADD_LO, ADDC_HI, then SWAPPC. At SWAPPC + // the relocation base is therefore 16 bytes behind the current PC. + const int32_t rel32 = static_cast(kCalleePc - (kCallerPc - 16)); + const uint64_t encoded_target = 0x0001FFFF00000000ULL | static_cast(rel32); + fx.cu->write_sgpr(wf->sgpr_alloc().base + 0, static_cast(encoded_target)); + fx.cu->write_sgpr(wf->sgpr_alloc().base + 1, static_cast(encoded_target >> 32)); + + fx.cu->step(); + EXPECT_EQ(wf->pc, kCalleePc); + EXPECT_EQ(wf->debug_read_sgpr(30), static_cast(kCallerPc + 4)); + EXPECT_EQ(wf->debug_read_sgpr(31), static_cast((kCallerPc + 4) >> 32)); + + fx.cu->step(); + EXPECT_EQ(wf->pc, kCallerPc + 4); +} + +// A single-stepped wave (rocm-dbgapi MODE.debug_en=1) executes exactly one +// instruction and is then handed to the single-step completion handler, which +// re-stops it. The engine must not run past that one instruction. +TEST(WaveDebugTest, SingleStepExecutesOneInstructionThenReports) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, 0xBF800000u); // s_nop 0 + fx.gpu_mem.write32(kKernelAddr + 4, 0xBF800000u); // s_nop 0 + fx.gpu_mem.write32(kKernelAddr + 8, kSEndpgm); + + uint32_t step_count = 0; + fx.cu->set_single_step_handler([&](amdgpu::Wavefront &w) { + ++step_count; + w.set_debug_halted(true); // re-stop after the step, as the driver does + return true; + }); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_debug_single_step(true); + + // One engine step runs exactly one instruction, then the handler re-stops it. + fx.cu->step(); + EXPECT_EQ(step_count, 1u); + EXPECT_EQ(wf->pc, kKernelAddr + 4); + EXPECT_TRUE(wf->debug_halted()); + + // While halted, stepping the CU makes no further progress. + fx.cu->step(); + EXPECT_EQ(step_count, 1u); + EXPECT_EQ(wf->pc, kKernelAddr + 4); + + // Resuming single-step runs the next instruction and re-stops again. + wf->set_debug_halted(false); + wf->set_debug_single_step(true); + fx.cu->step(); + EXPECT_EQ(step_count, 2u); + EXPECT_EQ(wf->pc, kKernelAddr + 8); + EXPECT_TRUE(wf->debug_halted()); +} + +// Without a debugger the s_trap is a no-op: the wave advances past it and runs +// to completion. This keeps kernels that embed traps in unreached paths from +// aborting the emulator when no debugger is attached. +TEST(WaveDebugTest, STrapWithoutDebuggerIsNoOp) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSTrapBreakpoint); + fx.gpu_mem.write32(kKernelAddr + 4, kSEndpgm); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + + fx.cu->step(); // s_trap -> no handler -> no-op, PC advances + EXPECT_FALSE(wf->debug_halted()); + EXPECT_EQ(wf->pc, kKernelAddr + 4); + + fx.cu->step(); // s_endpgm -> wave halts + EXPECT_TRUE(wf->is_halted()); +} + +TEST(WaveDebugTest, IllegalInstructionStopsWaveUnderDebugger) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, 0xFFFFFFFFu); + uint32_t illegal_count = 0; + fx.cu->set_illegal_inst_handler([&](amdgpu::Wavefront &wave) { + ++illegal_count; + wave.set_fatal_exception_pending(true); + wave.set_debug_halted(true); + return true; + }); + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + fx.cu->step(); + EXPECT_EQ(illegal_count, 1u); + EXPECT_TRUE(wave->debug_halted()); + EXPECT_TRUE(wave->fatal_exception_pending()); + EXPECT_EQ(wave->pc, kKernelAddr); + wave->reset(); + EXPECT_FALSE(wave->fatal_exception_pending()); +} + +TEST(WaveDebugTest, IllegalInstructionWithoutDebuggerHalts) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, 0xFFFFFFFFu); + auto *wave = fx.dispatch(kKernelAddr); + ASSERT_NE(wave, nullptr); + fx.cu->step(); + EXPECT_TRUE(wave->is_halted()); +} + +TEST(WaveDebugTest, STrapWithoutConfiguredHandlerAdvancesPcWithoutChangingWaveState) { + WaveDebugFixture fx; + fx.gpu_mem.write32(kKernelAddr, kSTrapSeven); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + wf->set_status_raw(0x12345678u); + wf->set_trapsts(0x87654321u); + + fx.cu->step(); + + EXPECT_EQ(wf->pc, kKernelAddr + 4); + EXPECT_EQ(wf->status_raw(), 0x12345678u); + EXPECT_EQ(wf->trapsts(), 0x87654321u); + EXPECT_EQ(wf->trap_id(), 0u); + EXPECT_FALSE(wf->debug_halted()); +} + +TEST(WaveDebugTest, Gfx1250TrapWithoutConfiguredHandlerAdvancesPc) { + WaveDebugFixture fx(ROCJITSU_CODE_ARCH_CDNA5); + fx.gpu_mem.write32(kKernelAddr, kGfx1250STrap); + + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + fx.cu->step(); + + EXPECT_EQ(wf->pc, kKernelAddr + 4); + EXPECT_FALSE(wf->debug_halted()); +} + +// The trap temporary registers and trap status register round-trip, and reset() +// (slot reuse) clears all debugger state. +TEST(WaveDebugTest, TrapRegistersRoundTripAndReset) { + WaveDebugFixture fx; + auto *wf = fx.dispatch(kKernelAddr); + ASSERT_NE(wf, nullptr); + + for (uint32_t i = 0; i < 16; ++i) + wf->set_ttmp(i, 0x1000 + i); + for (uint32_t i = 0; i < 16; ++i) + EXPECT_EQ(wf->ttmp(i), 0x1000 + i); + EXPECT_EQ(wf->ttmp(16), 0u); // out of range reads zero + + wf->set_trapsts(0xDEAD); + EXPECT_EQ(wf->trapsts(), 0xDEADu); + wf->set_queue_id(42); + EXPECT_EQ(wf->queue_id(), 42u); + + wf->debug_trap(7); + EXPECT_TRUE(wf->debug_halted()); + EXPECT_EQ(wf->trap_id(), 7u); + + wf->reset(); + EXPECT_FALSE(wf->debug_halted()); + EXPECT_FALSE(wf->debug_single_step()); + EXPECT_EQ(wf->trap_id(), 0u); + EXPECT_EQ(wf->trapsts(), 0u); + EXPECT_EQ(wf->queue_id(), 0u); + for (uint32_t i = 0; i < 16; ++i) + EXPECT_EQ(wf->ttmp(i), 0u); +} + +// ----------------------------------------------------------------------------- +// CWSR serialization round-trip: parse the serialized area back with the exact +// formulas rocm-dbgapi uses (projects/rocdbgapi/src/architecture.cpp gfx9/mi +// cwsr_record_t) and confirm the header invariants and every register offset. +// ----------------------------------------------------------------------------- + +struct ParsedWave { + uint64_t pc = 0, exec = 0, vcc = 0, wave_id = 0; + uint32_t status = 0, trapsts = 0, mode = 0, m0 = 0, ttmp6 = 0, ttmp11 = 0; + bool first = false, last = false; + uint32_t group[3] = {}; + std::vector sgprs; + std::vector vgprs; + std::vector lds; +}; + +// Walk the CWSR area exactly as rocm-dbgapi's control_stack_iterate + +// register_address do, asserting the contiguity invariants dbgapi enforces. +std::vector parse_cwsr(const std::map &mem, uint64_t base) { + auto rd = [&](uint64_t va) -> uint32_t { + auto it = mem.find(va); + return it == mem.end() ? 0u : it->second; + }; + auto rd64 = [&](uint64_t va) -> uint64_t { + return rd(va) | (static_cast(rd(va + 4)) << 32); + }; + + const uint32_t cs_off = rd(base + 0); + const uint32_t cs_size = rd(base + 4); + const uint32_t ws_off = rd(base + 8); + const uint32_t ws_size = rd(base + 12); + + // dbgapi: control_stack_end must equal wave_area_begin. + EXPECT_EQ(base + cs_off + cs_size, base + ws_off - ws_size); + + std::vector out; + uint64_t last_wave_area = base + ws_off; + uint32_t state = 0; + const uint32_t words = cs_size / 4; + for (uint32_t i = 2; i < words; ++i) { + uint32_t rl = rd(base + cs_off + i * 4); + if (rl & (1u << 30)) + continue; // event + if (rl & (1u << 31)) { + state = rl; + continue; + } + const uint32_t vgprs_field = state & 0x3F; + const uint32_t sgprs_field = (state >> 6) & 0x7; + const uint32_t accum = (state >> 24) & 0x3F; + const uint32_t vgpr_count = (accum + 1) * 4; + const uint32_t acc = (vgprs_field + 1) * 8 - vgpr_count; + const uint32_t sgpr_count = (sgprs_field + 1) * 16 - 16; + const uint32_t lds_size = ((state >> 9) & 0xFF) * 1280; + + const uint64_t save = last_wave_area - 64; + const uint64_t register_area_end = save - ((rl & (1u << 17)) ? lds_size : 0); + const uint64_t hwregs = register_area_end - 32 * 4; + const uint64_t ttmps = register_area_end - 16 * 4; + const uint64_t sgprs_addr = hwregs - sgpr_count * 4; + const uint64_t accv = sgprs_addr - acc * 256; + const uint64_t vgprs_addr = accv - static_cast(vgpr_count) * 256; + + ParsedWave pw; + pw.last = rl & (1u << 16); + pw.first = rl & (1u << 17); + pw.m0 = rd(hwregs + 0 * 4); + pw.pc = rd64(hwregs + 1 * 4); + pw.exec = rd64(hwregs + 3 * 4); + pw.status = rd(hwregs + 5 * 4); + pw.trapsts = rd(hwregs + 6 * 4); + pw.mode = rd(hwregs + 9 * 4); + pw.wave_id = rd64(ttmps + 4 * 4); + pw.ttmp6 = rd(ttmps + 6 * 4); + pw.group[0] = rd(ttmps + 8 * 4); + pw.group[1] = rd(ttmps + 9 * 4); + pw.group[2] = rd(ttmps + 10 * 4); + pw.ttmp11 = rd(ttmps + 11 * 4); + const uint32_t vcc_lo_slot = std::min(108, sgpr_count) - 2; + pw.vcc = rd64(sgprs_addr + vcc_lo_slot * 4); + pw.sgprs.resize(sgpr_count); + for (uint32_t s = 0; s < sgpr_count; ++s) + pw.sgprs[s] = rd(sgprs_addr + s * 4); + pw.vgprs.resize(static_cast(vgpr_count) * 64); + for (uint32_t r = 0; r < vgpr_count; ++r) + for (uint32_t l = 0; l < 64; ++l) + pw.vgprs[r * 64 + l] = rd(vgprs_addr + r * 256 + l * 4); + if (pw.first) { + pw.lds.resize(lds_size); + for (uint32_t byte = 0; byte < lds_size; ++byte) + pw.lds[byte] = + static_cast(rd(register_area_end + (byte & ~3u)) >> ((byte & 3u) * 8)); + } + out.push_back(std::move(pw)); + last_wave_area = vgprs_addr; + } + // dbgapi: the walk must bottom out exactly at wave_area_begin. + EXPECT_EQ(last_wave_area, base + ws_off - ws_size); + return out; +} + +kmd::CwsrWaveState make_wave(uint64_t id, uint64_t pc) { + kmd::CwsrWaveState w; + w.pc = pc; + w.exec = 0xF0F0F0F0ULL; + w.vcc = 0xABCD1234ULL; + w.status = (1u << 13); // HALT + w.trapsts = 0; + w.mode = 0; + w.m0 = 0x55; + w.wave_id = id; + w.group_ids = {1, 2, 3}; + w.wave_in_group = 0; + w.queue_packet_id = 7; + w.trap_id = 1; + w.wave_stopped = true; + w.num_sgprs = 16; + w.num_vgprs = 4; + w.sgprs.resize(w.num_sgprs); + for (uint32_t s = 0; s < w.num_sgprs; ++s) + w.sgprs[s] = 0x1000 + s; + w.vgprs.resize(static_cast(w.num_vgprs) * 64); + for (uint32_t r = 0; r < w.num_vgprs; ++r) + for (uint32_t l = 0; l < 64; ++l) + w.vgprs[r * 64 + l] = (r << 16) | l; + return w; +} + +TEST(WaveDebugTest, CwsrSerializationRoundTripsThroughDbgapiLayout) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; // 256 KiB + + std::map mem; + auto write32 = [&](uint64_t va, uint32_t val) { mem[va] = val; }; + + std::vector waves = {make_wave(0xAA01, 0x2000), make_wave(0xAA02, 0x2040), + make_wave(0xAA03, 0x2080)}; + waves[0].wave_in_group = 0; + waves[0].is_first_in_group = true; + waves[0].is_last_in_group = false; + waves[1].wave_in_group = 1; + waves[1].is_first_in_group = false; + waves[1].is_last_in_group = true; + waves[2].group_ids[0] = 2; + waves[2].is_first_in_group = true; + waves[2].is_last_in_group = true; + waves[0].lds = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88}; + waves[2].lds = {0xA1, 0xB2, 0xC3, 0xD4, 0xE5, 0xF6, 0x07, 0x18}; + + kmd::CwsrLayout layout = kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, waves, write32); + ASSERT_TRUE(layout.ok); + + std::vector parsed = parse_cwsr(mem, kCtxBase); + ASSERT_EQ(parsed.size(), waves.size()); + + for (size_t i = 0; i < waves.size(); ++i) { + const auto &in = waves[i]; + const auto &out = parsed[i]; + EXPECT_EQ(out.pc, in.pc) << "wave " << i; + EXPECT_EQ(out.exec, in.exec); + EXPECT_EQ(out.status, in.status); + EXPECT_EQ(out.mode, in.mode); + EXPECT_EQ(out.m0, in.m0); + EXPECT_EQ(out.wave_id, in.wave_id); + EXPECT_EQ(out.vcc, in.vcc); + EXPECT_EQ(out.group[0], in.group_ids[0]); + EXPECT_EQ(out.group[1], in.group_ids[1]); + EXPECT_EQ(out.group[2], in.group_ids[2]); + EXPECT_EQ(out.first, i == 0 || i == 2); + EXPECT_EQ(out.last, i == 1 || i == 2); + // TTMP6: wave_stopped (bit30) and trap id (bits 25:28). + EXPECT_TRUE(out.ttmp6 & (1u << 30)); + EXPECT_EQ((out.ttmp6 >> 25) & 0xF, in.trap_id); + // TTMP11: trap-handler-setup (bit31) and packet id (bits 6:30). + EXPECT_TRUE(out.ttmp11 & (1u << 31)); + EXPECT_EQ((out.ttmp11 >> 6) & 0x1FFFFFF, in.queue_packet_id); + // Meaningful scalars and vectors round-trip. + for (uint32_t s = 0; s < in.num_sgprs; ++s) + EXPECT_EQ(out.sgprs[s], in.sgprs[s]) << "sgpr " << s; + for (uint32_t r = 0; r < in.num_vgprs; ++r) + for (uint32_t l = 0; l < 64; ++l) + EXPECT_EQ(out.vgprs[r * 64 + l], in.vgprs[r * 64 + l]) << "vgpr " << r << " lane " << l; + if (in.is_first_in_group) { + ASSERT_GE(out.lds.size(), in.lds.size()); + EXPECT_TRUE(std::equal(in.lds.begin(), in.lds.end(), out.lds.begin())); + } else { + EXPECT_TRUE(out.lds.empty()); + } + } + + const auto original_mem = mem; + auto invalid = make_wave(1, 0x3000); + invalid.num_vgprs = 257; + EXPECT_FALSE(kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, {invalid}, write32).ok); + EXPECT_EQ(mem, original_mem); + + EXPECT_FALSE(kmd::serialize_queue_cwsr(kCtxBase + 1, kAreaSize, waves, write32).ok); + EXPECT_FALSE(kmd::serialize_queue_cwsr(UINT64_MAX - 3, kAreaSize, waves, write32).ok); + EXPECT_FALSE( + kmd::serialize_queue_cwsr(kCtxBase, layout.wave_state_offset - 1, waves, write32).ok); + EXPECT_EQ(mem, original_mem); +} + +// rocm-dbgapi carves 32-byte instruction buffers out of a per-queue "debugger +// memory" region declared in the context-save header (debug_offset/size at byte +// 16/20). It aborts displaced stepping if that region is absent, so the +// serializer must reserve a non-zero, in-bounds, non-overlapping region. +TEST(WaveDebugTest, CwsrReservesDebuggerMemoryForDisplacedStepping) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; // 256 KiB + + std::map mem; + auto write32 = [&](uint64_t va, uint32_t val) { mem[va] = val; }; + auto rd = [&](uint64_t va) -> uint32_t { + auto it = mem.find(va); + return it == mem.end() ? 0u : it->second; + }; + + std::vector waves = {make_wave(0xAA01, 0x2000)}; + kmd::CwsrLayout layout = kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, waves, write32); + ASSERT_TRUE(layout.ok); + + // The header advertises the region dbgapi reads (kfd_context_save_area_header + // debug_offset/size). + EXPECT_EQ(rd(kCtxBase + 16), layout.debug_offset); + EXPECT_EQ(rd(kCtxBase + 20), layout.debug_size); + + // Non-zero, or dbgapi aborts with "reserved memory is missing". + EXPECT_NE(layout.debug_offset, 0u); + EXPECT_NE(layout.debug_size, 0u); + // 64-byte aligned (DEBUGGER_BYTES_ALIGN) so each 32-byte chunk is aligned. + EXPECT_EQ(layout.debug_offset % 64u, 0u); + EXPECT_EQ(layout.debug_size % 64u, 0u); + // Sits above the wave area (no overlap) and inside the save area. + EXPECT_GE(layout.debug_offset, layout.wave_state_offset); + EXPECT_LE(layout.debug_offset + layout.debug_size, kAreaSize); + // Holds enough 32-byte chunks for dbgapi's park + terminating buffers plus a + // per-wave displaced-step buffer. + EXPECT_GE(layout.debug_size / 32u, waves.size() + 2); +} + +// FLAT_SCRATCH and VCC are written into aliased slots at the top of the saved +// SGPR block. num_sgprs is accepted up to 106, so those slots overlap real +// SGPR indices: serialization overwrote s102/s103 with FLAT_SCRATCH and +// deserialization read the alias bytes back as if they were registers, while +// flat_scratch itself was never restored at all. A round trip therefore +// corrupted live register state and lost the scratch base. +TEST(WaveDebugTest, CwsrRoundTripPreservesAliasedSgprsAndFlatScratch) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; + // The full saved block. CDNA3/CDNA4 default to 112 SGPRs per wave + // (config_loader default_sgprs_per_wf), so a wave that uses the whole + // allocation is the ordinary case, not an extreme one. + constexpr uint32_t kMaxAcceptedSgprs = kmd::kCwsrSavedSgprSlots; + constexpr uint64_t kFlatScratch = 0x0000DEAD0000BEEFULL; + + std::map mem; + auto write32 = [&](uint64_t va, uint32_t val) { mem[va] = val; }; + auto read32 = [&](uint64_t va) -> uint32_t { + auto it = mem.find(va); + return it == mem.end() ? 0u : it->second; + }; + + std::vector in = {make_wave(0xCC01, 0x3000)}; + in[0].num_sgprs = kMaxAcceptedSgprs; + in[0].sgprs.resize(kMaxAcceptedSgprs); + for (uint32_t s = 0; s < kMaxAcceptedSgprs; ++s) + in[0].sgprs[s] = 0xA5A50000u + s; + in[0].flat_scratch = kFlatScratch; + in[0].vcc = 0x0123456789ABCDEFULL; + + ASSERT_TRUE(kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, in, write32).ok); + + std::vector out(1); + out[0].num_sgprs = in[0].num_sgprs; + out[0].num_vgprs = in[0].num_vgprs; + ASSERT_TRUE(kmd::deserialize_queue_cwsr(kCtxBase, kAreaSize, out, read32)); + + EXPECT_EQ(out[0].flat_scratch, kFlatScratch) << "flat_scratch was not restored"; + EXPECT_EQ(out[0].vcc, in[0].vcc); + + // FLAT_SCRATCH occupies s102/s103 and VCC s106/s107. Only the slots an alias + // actually covers may be lost: clamping at the gfx9.4 architected count of + // 102 instead would also drop s104 and s105, which sit *between* the two + // pairs and are ordinary registers. That is why the predicate is an explicit + // slot test and not a bound. + for (uint32_t s = 0; s < kMaxAcceptedSgprs; ++s) { + if (kmd::cwsr_sgpr_slot_is_aliased(s)) + EXPECT_EQ(out[0].sgprs[s], 0u) << "aliased slot " << s << " decoded as an SGPR"; + else + EXPECT_EQ(out[0].sgprs[s], in[0].sgprs[s]) << "sgpr " << s << " did not survive"; + } + // Pin the two slots the "everything at or above 102 is an alias" shortcut + // would silently drop, so a future simplification back to a bound fails here. + EXPECT_EQ(out[0].sgprs[104], in[0].sgprs[104]); + EXPECT_EQ(out[0].sgprs[105], in[0].sgprs[105]); +} + +// The saved block is 112 slots, and CDNA3/CDNA4 default to exactly that many +// SGPRs per wave. When the codec accepted only 106 the geometry for a +// default-configured wave came back not-ok, so the whole queue's CWSR publish +// failed and the debugger saw no waves at all -- reachable from any CDNA4 +// config that simply omits sgprs_per_wf. +TEST(WaveDebugTest, CwsrAcceptsTheFullDefaultSgprAllocation) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; + + std::map mem; + auto write32 = [&](uint64_t va, uint32_t val) { mem[va] = val; }; + + std::vector in = {make_wave(0xCC02, 0x3000)}; + in[0].num_sgprs = kmd::kCwsrSavedSgprSlots; + in[0].sgprs.assign(kmd::kCwsrSavedSgprSlots, 0u); + EXPECT_TRUE(kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, in, write32).ok) + << "a wave using the default " << kmd::kCwsrSavedSgprSlots << "-SGPR allocation was rejected"; + + // One past the block is genuinely out of range and must still be refused + // rather than written past the end of the SGPR area. + mem.clear(); + in[0].num_sgprs = kmd::kCwsrSavedSgprSlots + 1; + in[0].sgprs.assign(in[0].num_sgprs, 0u); + EXPECT_FALSE(kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, in, write32).ok); + EXPECT_TRUE(mem.empty()) << "a rejected image still wrote to the ctx-save area"; +} + +TEST(WaveDebugTest, CwsrDeserializeRecoversSerializedWaveState) { + // serialize_queue_cwsr followed by deserialize_queue_cwsr must round-trip the + // register state the resume path reads back (the debugger writes its edits + // straight into this area, and resume reloads them onto the live wave). + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; // 256 KiB + + std::map mem; + auto write32 = [&](uint64_t va, uint32_t val) { mem[va] = val; }; + auto read32 = [&](uint64_t va) -> uint32_t { + auto it = mem.find(va); + return it == mem.end() ? 0u : it->second; + }; + + std::vector in = {make_wave(0xBB01, 0x3000), make_wave(0xBB02, 0x3080)}; + // Give the second wave MODE.debug_en set so the round-trip preserves it (the + // resume path uses this bit to select single-step). + in[1].mode = (1u << 11); + + ASSERT_TRUE(kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, in, write32).ok); + + // Reload: supply only the per-wave geometry (num_sgprs/num_vgprs) so the + // decoder reproduces the exact layout, then read the values back. + std::vector out; + for (const auto &w : in) { + kmd::CwsrWaveState g; + g.num_sgprs = w.num_sgprs; + g.num_vgprs = w.num_vgprs; + out.push_back(g); + } + ASSERT_TRUE(kmd::deserialize_queue_cwsr(kCtxBase, kAreaSize, out, read32)); + ASSERT_EQ(out.size(), in.size()); + + for (size_t i = 0; i < in.size(); ++i) { + EXPECT_EQ(out[i].pc, in[i].pc) << "wave " << i; + EXPECT_EQ(out[i].exec, in[i].exec); + EXPECT_EQ(out[i].vcc, in[i].vcc); + EXPECT_EQ(out[i].status, in[i].status); + EXPECT_EQ(out[i].mode, in[i].mode); + EXPECT_EQ(out[i].m0, in[i].m0); + EXPECT_EQ(out[i].wave_id, in[i].wave_id); + EXPECT_EQ(out[i].wave_stopped, in[i].wave_stopped); + EXPECT_EQ(out[i].spi_ttmps_setup, in[i].spi_ttmps_setup); + EXPECT_EQ(out[i].group_ids, in[i].group_ids); + EXPECT_EQ(out[i].wave_in_group, in[i].wave_in_group); + EXPECT_EQ(out[i].queue_packet_id, in[i].queue_packet_id); + for (uint32_t s = 0; s < in[i].num_sgprs; ++s) + EXPECT_EQ(out[i].sgprs[s], in[i].sgprs[s]) << "wave " << i << " sgpr " << s; + for (uint32_t r = 0; r < in[i].num_vgprs; ++r) + for (uint32_t l = 0; l < 64; ++l) + EXPECT_EQ(out[i].vgprs[r * 64 + l], in[i].vgprs[r * 64 + l]) + << "wave " << i << " vgpr " << r << " lane " << l; + } +} + +TEST(WaveDebugTest, CwsrBulkCodecMatchesDwordCodecAndPublishesHeaderLast) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; + std::vector waves = {make_wave(0xCC01, 0x4000), make_wave(0xCC02, 0x4080)}; + + std::map dwords; + const auto reference = + kmd::serialize_queue_cwsr(kCtxBase, kAreaSize, waves, + [&](uint64_t address, uint32_t value) { dwords[address] = value; }); + ASSERT_TRUE(reference.ok); + + std::vector bulk_image(reference.wave_state_offset); + std::vector> writes; + const auto bulk = kmd::serialize_queue_cwsr_bulk( + kCtxBase, kAreaSize, waves, [&](uint64_t address, std::span bytes) { + writes.emplace_back(address, bytes.size()); + const size_t offset = static_cast(address - kCtxBase); + ASSERT_LE(offset + bytes.size(), bulk_image.size()); + std::memcpy(bulk_image.data() + offset, bytes.data(), bytes.size()); + }); + ASSERT_TRUE(bulk.ok); + EXPECT_EQ(bulk.control_stack_offset, reference.control_stack_offset); + EXPECT_EQ(bulk.control_stack_size, reference.control_stack_size); + EXPECT_EQ(bulk.wave_state_offset, reference.wave_state_offset); + EXPECT_EQ(bulk.wave_state_size, reference.wave_state_size); + EXPECT_EQ(bulk.debug_offset, reference.debug_offset); + EXPECT_EQ(bulk.debug_size, reference.debug_size); + + ASSERT_EQ(writes.size(), 2u); + EXPECT_EQ(writes[0].first, kCtxBase + reference.control_stack_offset); + EXPECT_EQ(writes[0].second, reference.wave_state_offset - reference.control_stack_offset); + EXPECT_EQ(writes[1], (std::pair{kCtxBase, 10 * sizeof(uint32_t)})); + + for (uint32_t offset = 0; offset < reference.wave_state_offset; offset += sizeof(uint32_t)) { + uint32_t actual = 0; + std::memcpy(&actual, bulk_image.data() + offset, sizeof(actual)); + auto expected = dwords.find(kCtxBase + offset); + EXPECT_EQ(actual, expected == dwords.end() ? 0u : expected->second) << "offset " << offset; + } +} + +TEST(WaveDebugTest, CwsrBulkDeserializeRoundTripsAndRejectsCorruptHeader) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kAreaSize = 0x40000; + std::vector input = {make_wave(0xDD01, 0x5000), make_wave(0xDD02, 0x5080)}; + input[1].mode = 1u << 11; + + std::vector image(kAreaSize); + ASSERT_TRUE(kmd::serialize_queue_cwsr_bulk(kCtxBase, kAreaSize, input, + [&](uint64_t address, std::span bytes) { + std::memcpy(image.data() + (address - kCtxBase), + bytes.data(), bytes.size()); + }) + .ok); + + auto geometry_only = [&] { + std::vector states(input.size()); + for (size_t index = 0; index < input.size(); ++index) { + states[index].num_sgprs = input[index].num_sgprs; + states[index].num_vgprs = input[index].num_vgprs; + } + return states; + }; + auto read_block = [&](uint64_t address, std::span bytes) { + std::memcpy(bytes.data(), image.data() + (address - kCtxBase), bytes.size()); + }; + + auto output = geometry_only(); + ASSERT_TRUE(kmd::deserialize_queue_cwsr_bulk(kCtxBase, kAreaSize, output, read_block)); + ASSERT_EQ(output.size(), input.size()); + for (size_t index = 0; index < input.size(); ++index) { + EXPECT_EQ(output[index].pc, input[index].pc); + EXPECT_EQ(output[index].exec, input[index].exec); + EXPECT_EQ(output[index].vcc, input[index].vcc); + EXPECT_EQ(output[index].mode, input[index].mode); + EXPECT_EQ(output[index].wave_id, input[index].wave_id); + EXPECT_EQ(output[index].group_ids, input[index].group_ids); + EXPECT_EQ(output[index].sgprs, input[index].sgprs); + EXPECT_EQ(output[index].vgprs, input[index].vgprs); + } + + image[8] ^= 1; + output = geometry_only(); + EXPECT_FALSE(kmd::deserialize_queue_cwsr_bulk(kCtxBase, kAreaSize, output, read_block)); +} + +TEST(WaveDebugTest, CwsrBulkCodecUsesConstantBlockOperationsAtFullScale) { + constexpr uint64_t kCtxBase = 0x400000000ULL; + constexpr uint32_t kWaveCount = 1024; + constexpr uint32_t kAreaSize = 80 * 1024 * 1024; + std::vector waves(kWaveCount); + for (uint32_t index = 0; index < kWaveCount; ++index) { + auto &wave = waves[index]; + wave.pc = 0x1000 + index * 4; + wave.wave_id = index + 1; + wave.group_ids[0] = index / 4; + wave.wave_in_group = index % 4; + wave.queue_packet_id = 1; + wave.num_sgprs = 106; + wave.num_vgprs = 256; + wave.sgprs.resize(wave.num_sgprs, index); + wave.vgprs.resize(static_cast(wave.num_vgprs) * 64, index); + } + + size_t write_calls = 0; + size_t bytes_written = 0; + const auto layout = kmd::serialize_queue_cwsr_bulk(kCtxBase, kAreaSize, waves, + [&](uint64_t, std::span bytes) { + ++write_calls; + bytes_written += bytes.size(); + }); + ASSERT_TRUE(layout.ok); + EXPECT_EQ(write_calls, 2u); + EXPECT_EQ(bytes_written, + layout.wave_state_offset - layout.control_stack_offset + 10 * sizeof(uint32_t)); + EXPECT_GT(layout.wave_state_size, 64u * 1024u * 1024u); +} + +} // namespace diff --git a/emulation/rocjitsu/tests/xcd_distribution_test.cpp b/emulation/rocjitsu/tests/xcd_distribution_test.cpp index ff8aa303e514..fd2b5aa650b0 100644 --- a/emulation/rocjitsu/tests/xcd_distribution_test.cpp +++ b/emulation/rocjitsu/tests/xcd_distribution_test.cpp @@ -34,10 +34,10 @@ namespace { using namespace rocjitsu; -const std::string CONFIG_PATH = test::config_path("gfx950_cdna4.json"); +const std::string CONFIG_PATH = test::config_path("gfx950_mi355x.json"); constexpr uint32_t kTotalXcds = 8; -constexpr uint32_t kCusPerXcd = 32; // 4 SEs x 8 CUs +constexpr uint32_t kCusPerXcd = 36; // 4 SEs x 9 CUs constexpr uint32_t kTotalCus = kTotalXcds * kCusPerXcd; constexpr uint64_t kKdAddr = 0x10000; constexpr uint32_t kWavefrontSize = 64; @@ -96,7 +96,7 @@ TEST(XcdDistributionTest, SingleQueueGridLandsOnOneXcd) { ASSERT_EQ(fx.soc->num_xcds(), kTotalXcds); ASSERT_EQ(fx.soc->all_cus().size(), kTotalCus); - auto *cp = fx.soc->assign_queue_cp(); + auto *cp = fx.soc->assign_queue_cp(/*queue_ordinal=*/0); ASSERT_NE(cp, nullptr); test::AqlQueue queue(fx.memory, cp); queue.dispatch(kKdAddr, kTotalCus * kWavefrontSize, kWavefrontSize); @@ -128,7 +128,7 @@ TEST(XcdDistributionTest, QueuesRotateAcrossXcds) { constexpr uint32_t kWgsPerQueue = kCusPerXcd; std::vector> queues; for (uint32_t qi = 0; qi < kTotalXcds; ++qi) { - auto *cp = fx.soc->assign_queue_cp(); + auto *cp = fx.soc->assign_queue_cp(qi); ASSERT_NE(cp, nullptr); uint64_t ring = 0xF0000000ULL + qi * 0x100000ULL; queues.push_back(std::make_unique(fx.memory, cp, ring, 4096, ring + 0x10000, @@ -154,7 +154,7 @@ TEST(XcdDistributionTest, CounterAccumulatesAcrossDispatchesOnOneQueue) { ASSERT_EQ(fx.soc->num_xcds(), kTotalXcds); ASSERT_EQ(fx.soc->all_cus().size(), kTotalCus); - auto *cp = fx.soc->assign_queue_cp(); + auto *cp = fx.soc->assign_queue_cp(/*queue_ordinal=*/0); ASSERT_NE(cp, nullptr); const uint32_t xi = assigned_xcd_index(*fx.soc, cp); diff --git a/emulation/rocjitsu/tools/repeat_rocgdb_test.sh b/emulation/rocjitsu/tools/repeat_rocgdb_test.sh new file mode 100755 index 000000000000..f42742ebca78 --- /dev/null +++ b/emulation/rocjitsu/tools/repeat_rocgdb_test.sh @@ -0,0 +1,76 @@ +#!/usr/bin/env bash +# +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT +# +# Run one or more gdb.rocm files repeatedly, serially, and report how many +# iterations were clean. Concurrent Mirage sessions collide, so iterations never +# overlap -- and neither may two copies of this script, which the lock below +# enforces across processes. +# +# Usage: repeat_rocgdb_test.sh [test.exp ...] +set -uo pipefail + +usage() { + echo "Usage: $(basename "$0") [test.exp ...]" >&2 + exit 2 +} + +[ $# -ge 3 ] || usage +case $1 in + '' | *[!0-9]*) usage ;; +esac +[ "$1" -ge 1 ] || usage + +iterations=$1 +outdir=$2 +shift 2 + +# run_rocgdb_official.py is a sibling and resolves everything else -- suite, gdb, +# venv, binaries under test -- itself, so this knows no layout beyond its own +# directory and adds no second source of truth for any path. +here=$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd) || exit 1 + +mkdir -p "$outdir" || exit 1 + +# Serialize against any other copy of this script. Overlapping runs create +# overlapping Mirage sessions, which collide and report failures that are not +# real -- the one thing a flake count must not do. +exec 9>"$outdir/.repeat.lock" +if ! flock -n 9; then + echo "another repeat_rocgdb_test.sh holds $outdir/.repeat.lock" >&2 + exit 2 +fi + +passed=0 +for i in $(seq 1 "$iterations"); do + run="$outdir/iter-$(printf '%03d' "$i")" + rm -rf "$run" + python3 "$here/run_rocgdb_official.py" --output "$run" --tests "$@" > "$run.console" 2>&1 + rc=$? + if [ $rc -eq 0 ]; then + passed=$((passed + 1)) + echo "iter $i: PASS" + else + echo "iter $i: FAIL (rc=$rc)" + # run_rocgdb_official.py owns the pass/fail classification; read the + # summary it wrote rather than re-deriving one from gdb.sum. + python3 -c 'import json,sys +try: + result = json.load(open(sys.argv[1])) +except (OSError, ValueError): + sys.exit(0) +for record in result.get("records", []): + if not record.get("passed"): + bad = record.get("bad_statuses") or {} + detail = " ".join(f"{k}={v}" for k, v in sorted(bad.items())) + # Bound out of the f-string: the snippet is inside a single-quoted shell + # word, so an inner "..." subscript would have to be backslash-escaped, + # and a backslash there is a Python syntax error -- the reporter would + # die on exactly the iterations it exists to explain. + name = record.get("test") + print(f" {name} {detail}".rstrip())' "$run/result.json" + fi +done +echo "clean iterations: $passed/$iterations" +[ "$passed" -eq "$iterations" ] diff --git a/emulation/rocjitsu/tools/run_rocgdb_official.py b/emulation/rocjitsu/tools/run_rocgdb_official.py new file mode 100644 index 000000000000..91b28e70eff5 --- /dev/null +++ b/emulation/rocjitsu/tools/run_rocgdb_official.py @@ -0,0 +1,471 @@ +#!/usr/bin/env python3 + +# Copyright (c) 2026 Advanced Micro Devices, Inc. +# SPDX-License-Identifier: MIT + +"""Run each official gdb.rocm test in a fresh verified Mirage daemon session.""" + +from __future__ import annotations + +import argparse +import collections +import datetime as dt +import hashlib +import json +import os +from pathlib import Path +import re +import shutil +import signal +import subprocess +import sys +import time + +# Every path below is resolved at startup from the repository this script lives +# in, an environment variable, or a command-line flag -- in that order of +# increasing precedence. Nothing is hard-coded to one developer's checkout, so +# the same run is reproducible in CI and in a second worktree. +SESSION_ROOT = Path(f"/run/user/{os.getuid()}/mirage/session") + +# Resolved by configure() before main() does any work. +ROOT = Path() +SUITE_ROOT = Path() +TESTSUITE = Path() +TEST_DIR = Path() +MIRAGE = Path() +ROCJITSU = Path() +VENV = Path() +SDK = Path() +CORE = Path() +GDB = Path() + + +def default_root() -> Path: + """Repository root, inferred from this file's location.""" + return Path(__file__).resolve().parents[3] + + +def env_path(name: str, fallback: Path) -> Path: + value = os.environ.get(name) + return Path(value).expanduser() if value else fallback + + +def find_sdk_package(venv: Path, package: str) -> Path: + """Locate a _rocm_sdk_* package without pinning the interpreter version.""" + matches = sorted(venv.glob(f"lib/python3.*/site-packages/{package}")) + return matches[-1] if matches else venv / f"lib/python3/site-packages/{package}" + + +def configure(args: argparse.Namespace) -> None: + global ROOT, SUITE_ROOT, TESTSUITE, TEST_DIR, MIRAGE, ROCJITSU, VENV, SDK, CORE, GDB + ROOT = (args.root or env_path("ROCM_SYSTEMS_ROOT", default_root())).resolve() + SUITE_ROOT = ( + args.rocgdb_suite or env_path("ROCGDB_SUITE", Path("/tmp/ROCgdb-tests")) + ).resolve() + TESTSUITE = SUITE_ROOT / "gdb/testsuite" + TEST_DIR = TESTSUITE / "gdb.rocm" + MIRAGE = args.mirage or ROOT / "emulation/mirage/target/debug/mirage" + ROCJITSU = args.rocjitsu or ROOT / "emulation/rocjitsu/build/librocjitsu.so" + VENV = ( + args.venv or env_path("ROCM_SDK_VENV", ROOT / "emulation/mirage/.venv-mi350") + ).resolve() + SDK = find_sdk_package(VENV, "_rocm_sdk_devel") + CORE = find_sdk_package(VENV, "_rocm_sdk_core") + GDB = (args.gdb or env_path("ROCGDB", Path("/tmp/ROCgdb-build/gdb/gdb"))).resolve() + + +STATUS_RE = re.compile( + r"^(PASS|FAIL|XFAIL|XPASS|KFAIL|KPASS|UNRESOLVED|UNTESTED|UNSUPPORTED|ERROR|WARNING):", + re.MULTILINE, +) +BAD_STATUSES = { + "FAIL", + "UNRESOLVED", + "ERROR", +} + + +def utc_stamp() -> str: + return dt.datetime.now(dt.timezone.utc).strftime("%Y%m%dT%H%M%SZ") + + +def sha256(path: Path) -> str: + digest = hashlib.sha256() + with path.open("rb") as stream: + for chunk in iter(lambda: stream.read(1024 * 1024), b""): + digest.update(chunk) + return digest.hexdigest() + + +def git(*args: str, cwd: Path) -> str: + return subprocess.check_output(["git", "-C", str(cwd), *args], text=True).strip() + + +def copy_if_present(source: Path, destination: Path) -> None: + if source.exists() or source.is_symlink(): + destination.parent.mkdir(parents=True, exist_ok=True) + shutil.copy2(source, destination, follow_symlinks=True) + + +def existing_sessions() -> set[Path]: + """Session directories present before a test launches.""" + if not SESSION_ROOT.exists(): + return set() + return {definition.parent for definition in SESSION_ROOT.glob("*/def.json")} + + +def fresh_session(before: set[Path]) -> Path | None: + """The session this test created, identified by set difference. + + Picking "newest by mtime" instead looks correct until something else on the + machine creates a session mid-test -- a second copy of this script, or a + stray `mirage run`. The newest directory is then somebody else's, and the + run both mis-attributes the health check and stops a session it does not + own, which shows up as an unrelated test failing with an empty gdb.sum. + Identify the session positively, and refuse to guess when ambiguous. + """ + appeared = sorted(existing_sessions() - before) + if not appeared: + return None + if len(appeared) > 1: + print( + "warning: several sessions appeared during one test " + f"({', '.join(path.name for path in appeared)}); " + "another mirage run is active and results are not trustworthy", + file=sys.stderr, + ) + return None + return appeared[0] + + +def snapshot_session(session_dir: Path, output: Path) -> dict[str, object]: + evidence = output / "session" + evidence.mkdir(parents=True, exist_ok=True) + paths = { + "def.json": session_dir / "def.json", + "health-before-stop.json": session_dir / "health.json", + "rj_config.json": session_dir / "rj_config.json", + "exec-def.json": session_dir / "exec/e-000000/def.json", + "exec-status.json": session_dir / "exec/e-000000/status.json", + "daemon.pid": session_dir / "node/0/pid", + # The daemon hosts the emulated KFD, so anything the driver reports + # about a failing test is here and nowhere else: its stderr does not + # reach the test console. It has to be copied before the stop below, + # which removes the whole session directory -- taking it afterwards + # captures nothing at all, which is worse than missing the last few + # lines of shutdown output. + "host.log": session_dir / "node/0/host.log", + } + for destination, source in paths.items(): + copy_if_present(source, evidence / destination) + + session_definition: dict[str, object] = {} + try: + session_definition = json.loads((session_dir / "def.json").read_text()) + except (OSError, json.JSONDecodeError): + pass + session_id = str(session_definition.get("id", session_dir.name)) + daemon_mode = session_definition.get("daemon") is True + + daemon_pid: int | None = None + daemon_alive = False + try: + daemon_pid = int((session_dir / "node/0/pid").read_text().strip()) + os.kill(daemon_pid, 0) + daemon_alive = True + process = subprocess.run( + ["ps", "-p", str(daemon_pid), "-o", "pid,lstart,etime,stat,args"], + text=True, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + check=False, + ) + (evidence / "daemon-process.txt").write_text(process.stdout) + except (OSError, ValueError): + pass + + stop = subprocess.run( + [str(MIRAGE), "session", "stop", session_id], + cwd=ROOT, + text=True, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + check=False, + ) + (evidence / "stop.log").write_text(stop.stdout) + return { + "id": session_id, + "daemon_mode": daemon_mode, + "daemon_pid": daemon_pid, + "daemon_alive_before_stop": daemon_alive, + "stop_rc": stop.returncode, + } + + +def parse_summary(path: Path) -> tuple[collections.Counter[str], bool]: + if not path.is_file(): + return collections.Counter(), False + text = path.read_text(errors="replace") + statuses = collections.Counter(STATUS_RE.findall(text)) + summary = text.rpartition("=== gdb Summary ===")[2] + complete = bool(summary) and "gdb version" in summary + return statuses, complete + + +def main() -> int: + parser = argparse.ArgumentParser( + description="Run each official gdb.rocm test in a fresh verified Mirage daemon session." + ) + parser.add_argument("--output", type=Path) + parser.add_argument("--timeout", type=int, default=600) + parser.add_argument("--stop-after-failure", action="store_true") + parser.add_argument("--root", type=Path, help="rocm-systems checkout under test") + parser.add_argument("--rocgdb-suite", type=Path, help="ROCgdb source checkout") + parser.add_argument("--gdb", type=Path, help="ROCgdb binary to drive") + parser.add_argument("--venv", type=Path, help="venv holding the ROCm SDK wheels") + parser.add_argument("--mirage", type=Path, help="mirage binary") + parser.add_argument("--rocjitsu", type=Path, help="librocjitsu.so under test") + parser.add_argument( + "--tests", + nargs="+", + metavar="NAME.exp", + help="run only these gdb.rocm files (default: all of them)", + ) + parser.add_argument( + "--rj-log", + default="/dev/null", + help="RJ_LOG_FILE for the traced process; %(default)s discards it. " + "Pass a directory to keep one log per test.", + ) + parser.add_argument( + "--expect-tests", + type=int, + help="fail unless the suite holds exactly this many .exp files", + ) + args = parser.parse_args() + configure(args) + + required = [TEST_DIR, MIRAGE, ROCJITSU, SDK, CORE, GDB] + missing = [str(path) for path in required if not path.exists()] + if missing: + print("missing required paths:", *missing, sep="\n", file=sys.stderr) + return 2 + + available = sorted(path.name for path in TEST_DIR.glob("*.exp")) + if args.expect_tests is not None and len(available) != args.expect_tests: + print( + f"expected {args.expect_tests} gdb.rocm files, found {len(available)}", + file=sys.stderr, + ) + return 2 + if args.tests: + unknown = sorted(set(args.tests) - set(available)) + if unknown: + print("no such gdb.rocm files:", *unknown, sep="\n", file=sys.stderr) + return 2 + tests = sorted(args.tests) + else: + tests = available + if not tests: + print(f"no .exp files under {TEST_DIR}", file=sys.stderr) + return 2 + total = len(tests) + + output = args.output or ROOT / "rocgdb-official-logs" / f"run-{utc_stamp()}" + output = output.resolve() + output.mkdir(parents=True, exist_ok=False) + + manifest = { + "started_at": dt.datetime.now(dt.timezone.utc).isoformat(), + "workspace_commit": git("rev-parse", "HEAD", cwd=ROOT), + "workspace_branch": git("branch", "--show-current", cwd=ROOT), + "rocgdb_commit": git("rev-parse", "HEAD", cwd=SUITE_ROOT), + "rocgdb_gdb": str(GDB), + "mirage": str(MIRAGE), + "mirage_sha256": sha256(MIRAGE), + "rocjitsu": str(ROCJITSU), + "rocjitsu_sha256": sha256(ROCJITSU), + "sdk": str(SDK), + "core": str(CORE), + "profile": "mi350x", + "daemon_required": True, + "per_file_timeout_seconds": args.timeout, + "tests": tests, + } + (output / "manifest.json").write_text(json.dumps(manifest, indent=2) + "\n") + (output / "test-manifest.txt").write_text("\n".join(tests) + "\n") + + aggregate: collections.Counter[str] = collections.Counter() + records: list[dict[str, object]] = [] + failures = 0 + ld_path = f"{CORE / 'lib'}:{SDK / 'lib'}" + tool_path = f"{SDK / 'lib/llvm/bin'}:{os.environ.get('PATH', '')}" + runflags = ( + f"GDB={GDB} CC_FOR_TARGET=gcc CXX_FOR_TARGET=g++ " + f"HIP_COMPILER_FOR_TARGET={VENV / 'bin/amdclang++'}" + ) + + for index, test in enumerate(tests, start=1): + name = test.removesuffix(".exp") + test_output = output / f"{index:02d}-{name}" + test_output.mkdir() + sessions_before = existing_sessions() + start = time.monotonic() + rj_log_root = Path(args.rj_log) + rj_log = ( + rj_log_root / f"{name}.log" if rj_log_root.is_dir() else Path(args.rj_log) + ) + command = [ + "setsid", + "--wait", + "timeout", + "-k", + "10", + str(args.timeout), + str(MIRAGE), + "run", + "--daemon", + "--keep-session", + "--profile", + "mi350x", + "--env", + f"LD_LIBRARY_PATH={ld_path}", + "--", + "env", + f"ROCM_PATH={SDK}", + "HCC_AMDGPU_TARGET=gfx950", + f"PATH={tool_path}", + f"LD_LIBRARY_PATH={ld_path}", + f"RJ_LOG_FILE={rj_log}", + "make", + "check", + f"RUNTESTFLAGS={runflags}", + f"TESTS=gdb.rocm/{test}", + ] + (test_output / "command.json").write_text(json.dumps(command, indent=2) + "\n") + subprocess.run( + ["make", "clean"], + cwd=TESTSUITE, + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL, + check=False, + ) + for stale_output in (TESTSUITE / "gdb.log", TESTSUITE / "gdb.sum"): + stale_output.unlink(missing_ok=True) + with (test_output / "console.log").open("w") as console: + process = subprocess.run( + command, + cwd=TESTSUITE, + stdout=console, + stderr=subprocess.STDOUT, + check=False, + ) + elapsed = round(time.monotonic() - start, 3) + copy_if_present(TESTSUITE / "gdb.log", test_output / "gdb.log") + copy_if_present(TESTSUITE / "gdb.sum", test_output / "gdb.sum") + session_dir = fresh_session(sessions_before) + session = ( + snapshot_session(session_dir, test_output) + if session_dir is not None + else { + "id": None, + "daemon_mode": False, + "daemon_pid": None, + "daemon_alive_before_stop": False, + "stop_rc": None, + } + ) + statuses, summary_complete = parse_summary(test_output / "gdb.sum") + aggregate.update(statuses) + bad = { + key: value + for key, value in statuses.items() + if key in BAD_STATUSES and value + } + # Count the assertions that actually ran. A file can legitimately report + # nothing but UNSUPPORTED (an unmet `require`), so this is not a + # per-file pass condition -- but a file that emitted no status at all + # verified nothing, and a whole suite of them means the harness is + # broken rather than the code being correct. Recorded per file and + # enforced across the run below. + executed = sum(statuses.values()) + passed = ( + process.returncode == 0 + and summary_complete + and not bad + and session["daemon_mode"] is True + and session["daemon_alive_before_stop"] is True + ) + record = { + "index": index, + "test": f"gdb.rocm/{test}", + "rc": process.returncode, + "elapsed_seconds": elapsed, + "summary_complete": summary_complete, + "executed_assertions": executed, + "statuses": dict(sorted(statuses.items())), + "bad_statuses": bad, + "session": session, + "passed": passed, + } + records.append(record) + (test_output / "result.json").write_text(json.dumps(record, indent=2) + "\n") + print( + f"[{index:02d}/{total}] {test}: {'PASS' if passed else 'FAIL'} " + f"rc={process.returncode} elapsed={elapsed:.1f}s statuses={dict(statuses)} " + f"session={session['id']}", + flush=True, + ) + if not passed: + failures += 1 + if args.stop_after_failure: + break + + # A suite that ran to completion without executing a single assertion is a + # harness failure wearing a success: every file would report rc=0, a + # well-formed summary and no bad statuses. Refuse to call that a pass. + total_executed = sum(aggregate.values()) + silent = [ + record["test"] for record in records if record["executed_assertions"] == 0 + ] + if silent: + print( + f"warning: {len(silent)} file(s) produced no test status at all: " + + ", ".join(silent), + file=sys.stderr, + ) + + result = { + "completed_at": dt.datetime.now(dt.timezone.utc).isoformat(), + "executed_assertions": total_executed, + "files_with_no_status": silent, + "planned_files": len(tests), + "completed_files": len(records), + "passed_files": sum(bool(record["passed"]) for record in records), + "failed_files": failures, + "aggregate_statuses": dict(sorted(aggregate.items())), + "all_passed": ( + len(records) == len(tests) and failures == 0 and total_executed > 0 + ), + "records": records, + } + (output / "result.json").write_text(json.dumps(result, indent=2) + "\n") + with (output / "summary.tsv").open("w") as summary: + summary.write("index\ttest\tpassed\trc\telapsed_seconds\tPASS\tbad\tsession\n") + for record in records: + bad_count = sum(record["bad_statuses"].values()) + summary.write( + f"{record['index']}\t{record['test']}\t{record['passed']}\t{record['rc']}\t" + f"{record['elapsed_seconds']}\t{record['statuses'].get('PASS', 0)}\t{bad_count}\t" + f"{record['session']['id']}\n" + ) + print( + f"output={output} completed={len(records)}/{total} passed={result['passed_files']} " + f"failed={failures} aggregate={dict(aggregate)}", + flush=True, + ) + return 0 if result["all_passed"] else 1 + + +if __name__ == "__main__": + raise SystemExit(main()) From c3c9641073a049eff457d34eab174175caaa59a4 Mon Sep 17 00:00:00 2001 From: Tony Gutierrez Date: Wed, 19 Aug 2026 13:56:40 -0700 Subject: [PATCH 26/27] rocjitsu: Point the XCD distribution test at the config that exists The test named a gfx950 config that had been renamed out from under it, and described a part with 32 CUs per XCD. Both facts came from the same commit: aligning the MI350X configs with the captured KFD topology renamed gfx950_cdna4.json to gfx950_mi355x.json and widened a shader array from eight CUs to nine. Neither branch touched the other's files, so the merge was clean and the breakage appeared only once both were on develop -- every test in the suite threw before reaching an assertion, because the fixture could not open its config at all. Name the config that ships and derive the geometry from it: four shader engines of nine CUs is 36 per XCD and 288 across the eight, which is what the topology instantiates. The active-CU count the driver reports is still 256, since 1024 SIMDs at four per CU excludes the harvested slots, but nothing here models a harvest mask and every instantiated slot is schedulable -- so the count these tests must agree with is the physical one. Signed-off-by: Tony Gutierrez (cherry picked from commit efa24f23c925a10f54ab0411786e74390f433b92) --- emulation/rocjitsu/tests/xcd_distribution_test.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/emulation/rocjitsu/tests/xcd_distribution_test.cpp b/emulation/rocjitsu/tests/xcd_distribution_test.cpp index fd2b5aa650b0..cc88b6665d19 100644 --- a/emulation/rocjitsu/tests/xcd_distribution_test.cpp +++ b/emulation/rocjitsu/tests/xcd_distribution_test.cpp @@ -89,7 +89,7 @@ uint32_t assigned_xcd_index(const SoC &soc, const amdgpu::CommandProcessor *cp) // // This pins CURRENT behavior, which is a fidelity gap: a multi-XCD part running // as one partition spreads a dispatch over every XCD. The topology here -// advertises 256 CUs, so a single-queue application reaches an eighth of them. +// instantiates 288 CUs, so a single-queue application reaches an eighth of them. // Follow-on work in this stack flips this expectation to an even spread. TEST(XcdDistributionTest, SingleQueueGridLandsOnOneXcd) { XcdDistributionFixture fx; From c3f419555a6e5c48932cd6490d2db0e6d74d1481 Mon Sep 17 00:00:00 2001 From: Tony G Date: Wed, 19 Aug 2026 16:03:29 -0700 Subject: [PATCH 27/27] [rocjitsu] Translate gfx1250 lane-banked and kernarg-supplied indirect calls (#10376) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ## Motivation hipTensor and rocThrust gfx1250 objects were refused at code-object load time with indirect branch or call target recovery is not implemented for relocated kernel text on s_swap_pc_i64. A refused object leaves HIP holding an invalid kernel handle, so the failure surfaced as a segfault rather than a diagnostic: the hipTensor smoke suite lost bilinear_contraction, scale_contraction_with_unary_ops and trinary_scale_contraction, and rocThrust lost the whole binary_search set. Separately, translating large device libraries was slow enough to matter at load time — an 8.3 MB hipTensor object took 510 s and 2.4 GB on unmodified develop, against a 30 s and 4096 MiB per-object budget. ## Technical details Three independent causes. First, patch_recovered_builder_fixups regenerated a recovered builder's delta into the pair the consumer reads; since append_pc_delta_builder emits only the add and leaves the original getpc in place, a lane-banked dispatcher — which builds the address in a scratch pair, stashes it through v_writelane_b32 and restores it into a different pair — got an add against whatever the consumer's register happened to hold, and a getpc/add pairing the next translation read as a code address naming no body (117 of 4640 fixups on one object). PcValue and IndirectCallFixup now carry the producer's pair alongside the consumer's, and that pair is part of the rewritten-region reuse key, so two consumers sharing a range while naming different pairs can no longer silently inherit one replacement. Second, the kernarg admission was fenced off from objects defining device functions; rocPRIM's trampoline_kernel calls a device function pointer the host wrote into kernarg, and admitting it promises every externally resolvable .text symbol still names its body. That obligation is now discharged by adopting the exported bodies, triggered on the admission's own fact rather than a proxy — a kernarg-supplied target cannot be recovered, so translation cannot fold the transfer and both passes see the identical set, which keeps the adopted set a fixed point. Third, run_block_dataflow popped a FIFO seeded in block-index order; recovered indirect-call edges give a shared callee block one predecessor per call site (5,646 on the largest object), so that O(predecessors × pairs) join was recomputed ~151 times per block — 84.8 M visits per round. Reverse-postorder scheduling reduces that to 558 k and the object from 556.8 s to 29.4 s, with output byte-identical because the least fixed point of a monotone join does not depend on visit order. The lane-recovery retained-fact bound also rises to 1<<26, which the 4.65/4.70 MB contraction objects need to avoid abandoning recovery wholesale. (cherry picked from commit 8b7763ef5e20574b8fdfdf711ad9573eb8b17963) --- .../analysis/indirect_branch_discovery.cpp | 98 +++++++++++- .../analysis/indirect_branch_discovery.h | 16 +- .../rocjitsu/code/dbt/binary_translator.cpp | 58 +++++++- .../code/patch/kernel_text_layout.cpp | 22 ++- .../rocjitsu/tests/analysis/liveness_test.cpp | 20 ++- .../dbt/support/translate_test_support.cpp | 10 +- .../dbt/support/translate_test_support.h | 7 +- .../tests/dbt/translate_gfx1250_test.cpp | 140 ++++++++++++++++++ 8 files changed, 343 insertions(+), 28 deletions(-) diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp index 4750f91b1b82..fd7c90e90b3c 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.cpp @@ -180,6 +180,16 @@ enum class ScalarSop2Op { struct PcValue { int64_t offset = 0; uint64_t source_getpc_offset = 0; + /// @brief Low SGPR of the pair the producing `s_getpc_b64` wrote. + /// + /// @details Not always the pair the eventual consumer reads. A lane-banked dispatcher builds + /// the address in a scratch pair, stashes it through `v_writelane_b32`, and restores it into a + /// different pair before the transfer. patch_recovered_builder_fixups regenerates only the add + /// half and leaves the original getpc in place, so its replacement has to name this pair: + /// naming the consumer's would pair a fresh add against a getpc that writes something else and + /// materialize an address derived from an unrelated register. Fully determined by + /// source_getpc_offset, so carrying it splits no lattice value that was previously merged. + uint16_t source_sreg = 0; uint64_t source_recovery_begin_offset = 0; uint64_t source_recovery_end_offset = 0; /// @brief False once a non-chain instruction was observed inside the recovery @@ -1197,6 +1207,7 @@ instruction_index_for_offset(std::span insts, uint64_t .source_call_offset = ctx.insts[inst_index]->src_loc(), .source_target_offset = static_cast(value.offset), .source_call_sreg = pair_lo, + .source_builder_sreg = value.source_sreg, .source_is_call = ctx.facts[inst_index].swappc_sdst.has_value(), .source_return_sreg = ctx.facts[inst_index].swappc_sdst.value_or(0), }; @@ -1800,6 +1811,7 @@ void scan_block(AnalysisContext &ctx, size_t block_index, std::vector(next_offset), .source_getpc_offset = inst.src_loc(), + .source_sreg = pair_lo, .source_recovery_begin_offset = next_offset, .source_recovery_end_offset = next_offset}); continue; @@ -1945,16 +1957,67 @@ void scan_block(AnalysisContext &ctx, size_t block_index, std::vector> entry_pairs(blocks.size()); - std::deque worklist; + + // Visit blocks in reverse postorder. The least fixed point of this monotone + // join does not depend on the visit order, but the order decides how many + // times it is recomputed. A recovered indirect call gives its shared callee + // block one predecessor per call site -- thousands of them on a large device + // library -- and popping in block-index order then re-evaluates that + // O(predecessors x pairs) join once for every predecessor that happens to be + // processed after it. Reverse postorder evaluates a predecessor before its + // successors wherever the graph is acyclic, so a block is normally recomputed + // only for its back edges. On the largest hipTensor object this is the + // difference between 84.8M block visits and 558k, and between 264 s and 0.7 s + // per round. + // + // The order is a pure function of the block graph: roots are tried in + // ascending block index, successors in their stored order, and the root loop + // covers every block, so blocks unreachable from any earlier root still + // receive a position and are still seeded onto the worklist below. + std::vector rpo_order; + rpo_order.reserve(blocks.size()); + { + std::vector visited(blocks.size(), 0); + std::vector> stack; + for (size_t root = 0; root < blocks.size(); ++root) { + if (visited[root]) + continue; + visited[root] = 1; + stack.emplace_back(root, 0); + while (!stack.empty()) { + const size_t node = stack.back().first; + size_t &next_successor = stack.back().second; + if (next_successor < blocks[node].successors.size()) { + const size_t successor = blocks[node].successors[next_successor++]; + if (successor < blocks.size() && !visited[successor]) { + visited[successor] = 1; + stack.emplace_back(successor, 0); + } + continue; + } + rpo_order.push_back(node); + stack.pop_back(); + } + } + } + std::ranges::reverse(rpo_order); + std::vector rpo_position(blocks.size(), 0); + for (size_t position = 0; position < rpo_order.size(); ++position) + rpo_position[rpo_order[position]] = position; + + // Keyed by reverse-postorder position so the lowest position is always popped + // next. Positions are unique, so this is a total order and the pop sequence is + // fully determined by the block graph. + std::set worklist; std::vector on_worklist(blocks.size(), false); for (size_t block_index = 0; block_index < blocks.size(); ++block_index) { - worklist.push_back(block_index); + worklist.insert(rpo_position[block_index]); on_worklist[block_index] = true; } while (!worklist.empty()) { - const size_t block_index = worklist.front(); - worklist.pop_front(); + const size_t block_index = rpo_order[*worklist.begin()]; + worklist.erase(worklist.begin()); on_worklist[block_index] = false; LatticeFacts new_entry; @@ -2040,7 +2103,7 @@ void scan_block(AnalysisContext &ctx, size_t block_index, std::vector) + 3 * sizeof(void *) - @@ -2805,6 +2889,7 @@ void recover_vector_lane_stashed_pcs(AnalysisContext &ctx, const std::vector(inst.size()); builders.set_builder(*facts.getpc_sdst, PcValue{.offset = static_cast(next_offset), .source_getpc_offset = inst.src_loc(), + .source_sreg = *facts.getpc_sdst, .source_recovery_begin_offset = next_offset, .source_recovery_end_offset = next_offset}); continue; @@ -3365,6 +3450,7 @@ void recover_signed_delta_templates(const AnalysisContext &ctx, .offset = static_cast(getpc_next) + static_cast(static_cast(literal)) + 4, .source_getpc_offset = getpc_inst.src_loc(), + .source_sreg = *pair_lo, .source_recovery_begin_offset = getpc_next, .source_recovery_end_offset = sub_consumer->recovery_end, }; diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.h b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.h index 81a6655f84af..c1a15c7417aa 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.h +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/indirect_branch_discovery.h @@ -43,8 +43,20 @@ struct IndirectCallFixup { uint64_t source_recovery_end_offset = 0; ///< One-past-end source byte of builder code. uint64_t source_call_offset = 0; ///< Source offset of the setpc/swappc consumer. uint64_t source_target_offset = 0; ///< Recovered source branch target offset. - uint16_t source_call_sreg = 0; ///< Low SGPR of the recovered PC pair. - bool source_is_call = false; ///< Whether the consumer is a call-like swappc. + uint16_t source_call_sreg = 0; ///< Low SGPR the consumer reads the PC pair from. + /// @brief Low SGPR of the pair the builder range itself writes. + /// + /// @details Usually the same pair the consumer reads, and for a plain getpc/add/swappc chain + /// it always is. A lane-banked dispatcher breaks the two apart: it builds the address in a + /// scratch pair, stashes it with `v_writelane_b32`, and restores it into the consumer's pair + /// with `v_readlane_b32` much later. patch_recovered_builder_fixups regenerates only the add + /// half of the builder and leaves the original `s_getpc_b64` where it is, so the replacement + /// has to name the pair that getpc writes. Naming the consumer's pair instead emits an add + /// against a getpc that wrote a different register: it corrupts the consumer's pair, breaks + /// the stash the dispatcher still reads back, and leaves a getpc/add pairing that the next + /// translation's relocation lattice reads as a code address naming no body at all. + uint16_t source_builder_sreg = 0; + bool source_is_call = false; ///< Whether the consumer is a call-like swappc. /// @brief True when the recovered fact for this consumer was incomplete: at least /// one predecessor path left the PC pair at an unconstrained value. The concrete /// targets are still valid for relocation and liveness, but the consumer must NOT diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp index 97b29abf8d3e..b67e6675ec30 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/binary_translator.cpp @@ -1003,7 +1003,10 @@ scope_relocatable_pc_builders(std::span blocks) { .source_recovery_end_offset = builder.source_recovery_end_offset, .source_call_offset = builder.source_getpc_offset, .source_target_offset = target, - .source_call_sreg = builder.source_sreg}); + // A whole-scope builder has no consumer at all, so the two registers + // are necessarily the producer's pair. + .source_call_sreg = builder.source_sreg, + .source_builder_sreg = builder.source_sreg}); } } return builder_fixups; @@ -2478,10 +2481,13 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob // incoming SGPR-pair facts that call establishes, turning otherwise recoverable getpc flows // unresolved. const auto text_function_symbol_offsets = discover_text_function_symbol_offsets(obj); - // Fences the kernarg admission below. Admitting an externally supplied pointer in an object that - // DOES define device functions drags in the rest of that problem -- those bodies would have to be - // adopted as roots or they are dropped, and their resource envelope propagated into every - // descriptor that can enter them. Where the object defines none, that obligation is vacuous. + // One of the two ways the kernarg admission below is satisfied. An object that defines no device + // function has nothing a kernarg pointer could name locally, so the admission carries no + // obligation at all. An object that DOES define them is no longer fenced off: the obligation -- + // that those bodies are adopted as roots rather than dropped -- is instead discharged directly, + // by adopting every exported body whenever object_admits_kernarg_supplied_transfer holds. See + // that predicate for why triggering on the admission's own fact keeps the adopted set stable + // across passes. // Both walk the whole symbol table, and most objects never reach the code that needs them, so // pay for them on first use. Doing it eagerly cost about 2x the translation time across the // packaged-HSACO corpus -- enough on its own to exhaust the sanitizer job's budget. @@ -2752,6 +2758,9 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob // covered here; that case still refuses, which is the pre-existing behavior. std::vector adopted_roots; std::unordered_set address_taken_offsets; + // Set inside the adoption block below and read again by the kernarg admission further + // down, which must rest on exactly the fact that adopted the roots satisfying it. + bool object_admits_kernarg_supplied_transfer = false; { // How many scopes would emit each block on their own. A body reached by one scope already has // a single placement, so its address is unambiguous and nothing needs adopting. A body reached @@ -2827,7 +2836,39 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob }); // Same predicate the promise uses, so a permission is never granted without the roots // that satisfy it being adopted. - if (object_produces_code_addresses && object_has_indirect_transfer) { + // The kernarg admission below grants the same promise the producer permission does -- that + // every externally resolvable `.text` symbol still names its body -- so it needs the same + // roots, or replace_text() refuses the object for a body no scope reaches. rocPRIM's + // trampoline_kernel is the case: it calls a device function pointer the host wrote into + // kernarg, and its object also defines device-function bodies, one of which is an unreferenced + // __cxa_pure_virtual stub that nothing emits. + // + // Trigger on the admission's own fact rather than a proxy. A kernarg-supplied target cannot be + // recovered -- no dataflow fact names a value the host wrote -- so translation cannot fold such + // a transfer into a direct call, and it survives verbatim into the output. The second pass + // therefore sees the identical set and adopts identically. object_has_indirect_transfer is NOT + // a substitute: it counts recovered transfers too, and those DO become direct calls, so gating + // on it adopts less the second time round and moves `.text` (measured: 36 idempotence failures + // across the packaged-kpack corpus). + // + // The three cheap tests run first because the fixpoint is expensive -- an InstDefUse and two + // RegisterSet expansions per instruction, per predecessor edge, per sweep -- and running it for + // every scope of every object measured as a 22% translation-time regression. + object_admits_kernarg_supplied_transfer = [&] { + if (externally_resolvable_text_function_offsets().empty() || !object_has_indirect_transfer) + return false; + if (std::ranges::none_of(descriptor_translations, [](const KdTranslation &translation) { + return translation.source_has_kernarg_segment_ptr; + })) + return false; + return std::ranges::any_of(scopes, [&](const KernelTranslationScope &scope) { + return scope.translation != nullptr && + !kernarg_supplied_indirect_targets(scope.blocks, scope.entry, *scope.translation) + .empty(); + }); + }(); + if ((object_produces_code_addresses && object_has_indirect_transfer) || + object_admits_kernarg_supplied_transfer) { for (const uint64_t target : externally_resolvable_text_function_offsets()) adopt(target); } @@ -3459,8 +3500,11 @@ TranslatedCodeObject BinaryTranslator::translate_impl(const AmdGpuCodeObject &ob std::optional> kernarg_supplied_cache; const auto kernarg_supplied_targets = [&]() -> const std::unordered_set & { if (!kernarg_supplied_cache) { + // Either the object defines no body a kernarg pointer could name, or the bodies it does + // export were adopted above under the very same fact this admission rests on. kernarg_supplied_cache = - scope.translation != nullptr && object_defines_no_device_function() + scope.translation != nullptr && + (object_defines_no_device_function() || object_admits_kernarg_supplied_transfer) ? kernarg_supplied_indirect_targets(scope.blocks, scope.entry, *scope.translation) : std::unordered_set{}; } diff --git a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/kernel_text_layout.cpp b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/kernel_text_layout.cpp index 869a5fb908e2..e1882f701aff 100644 --- a/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/kernel_text_layout.cpp +++ b/emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/patch/kernel_text_layout.cpp @@ -989,7 +989,7 @@ TextRelocationResult patch_recovered_indirect_fixups(std::vector &text, TextRelocationResult patch_recovered_builder_fixups(std::vector &text, const KernelTextLayout &layout, rj_code_arch_t arch) { - std::unordered_map> rewritten_regions; + std::unordered_map> rewritten_regions; std::vector compact_builder_fallbacks; for (const IndirectCallFixup &fixup : layout.recovered_builder_fixups) { auto target_target = target_for_source_offset(layout, fixup.source_target_offset); @@ -1012,11 +1012,15 @@ TextRelocationResult patch_recovered_builder_fixups(std::vector &text, // One source-side builder may feed multiple consumers. Only the first one // rewrites the range, so reuse is valid only when every consumer asks for - // the same replacement -- same target, same byte range, and the same drain - // requirement, which changes the words emitted. + // the same replacement. Every input the emitted words depend on has to be in + // this key: the target and byte range, the drain requirement, and the SGPR + // pair the add is written against. Omitting the pair let a second consumer + // that names a different builder register silently inherit the first + // consumer's replacement, which a lane-banked dispatcher can produce because + // its producer and consumer pairs differ. const auto rewrite_key = std::tuple{fixup.target_recovery_end_offset, static_cast(*target_target), - fixup.source_requires_xcnt_drain}; + fixup.source_requires_xcnt_drain, fixup.source_builder_sreg}; auto [rewrite_it, inserted] = rewritten_regions.emplace(fixup.target_recovery_begin_offset, rewrite_key); if (!inserted) { @@ -1063,8 +1067,14 @@ TextRelocationResult patch_recovered_builder_fixups(std::vector &text, // direct transfer -- so predicting who needs to stay visible gets it wrong. Widening // unconditionally and falling back when it does not fit is both simpler and measurably // better: on RCCL it takes the unaccounted-builder count on re-translation from 32 to 0. + // + // The pair named is the one the builder's own getpc wrote, not the one its consumer reads. + // The replacement covers only the delta half and leaves that getpc in place, so any other + // pair would be added to whatever it happened to hold. The two coincide for a direct + // getpc/add/swappc chain and diverge for a lane-banked dispatcher, which restores the address + // into a different pair between the two. const size_t replacement_begin = replacement_words.size(); - if (!append_pc_delta_builder(replacement_words, arch, fixup.source_call_sreg, delta, + if (!append_pc_delta_builder(replacement_words, arch, fixup.source_builder_sreg, delta, /*prefer_literal64=*/true)) { return relocation_error( fixup.source_call_offset, @@ -1078,7 +1088,7 @@ TextRelocationResult patch_recovered_builder_fixups(std::vector &text, // something wrong. Widening the range is not available here: the patcher writes in place. if ((replacement_words.size() * sizeof(uint32_t)) > recovery_size) { replacement_words.resize(replacement_begin); - if (!append_pc_delta_builder(replacement_words, arch, fixup.source_call_sreg, delta)) { + if (!append_pc_delta_builder(replacement_words, arch, fixup.source_builder_sreg, delta)) { return relocation_error( fixup.source_call_offset, "target ISA cannot encode canonical recovered indirect branch builder", diff --git a/emulation/rocjitsu/tests/analysis/liveness_test.cpp b/emulation/rocjitsu/tests/analysis/liveness_test.cpp index 3abc68e015ba..591de6a9a927 100644 --- a/emulation/rocjitsu/tests/analysis/liveness_test.cpp +++ b/emulation/rocjitsu/tests/analysis/liveness_test.cpp @@ -2313,7 +2313,13 @@ TEST(CfgAnalysis, Gfx1250CarriesLaneStashAcrossProvenBlockBoundary) { auto *consumer = block_starting_at(blocks, 52); ASSERT_NE(consumer, nullptr); ASSERT_EQ(consumer->static_indirect_call_fixups().size(), 1u); - EXPECT_EQ(consumer->static_indirect_call_fixups()[0].source_target_offset, 60u); + const IndirectCallFixup &restored = consumer->static_indirect_call_fixups()[0]; + EXPECT_EQ(restored.source_target_offset, 60u); + // This stash restores into the pair the getpc wrote, so the producer and consumer registers + // coincide. Pinning that is the counterpart to the split case below: the rewrite must name the + // producer, and when the two are equal that has to stay indistinguishable from naming either. + EXPECT_EQ(restored.source_builder_sreg, 0u); + EXPECT_EQ(restored.source_call_sreg, 0u); } TEST(CfgAnalysis, Gfx1250UnreachablePostRocrAbortBlockDoesNotPoisonLaneStash) { @@ -3078,7 +3084,14 @@ TEST(CfgAnalysis, Gfx1250LaneRestoreReachesConsumerAcrossBranch) { auto *consumer = block_starting_at(blocks, 52); ASSERT_NE(consumer, nullptr); ASSERT_EQ(consumer->static_indirect_call_fixups().size(), 1u); - EXPECT_EQ(consumer->static_indirect_call_fixups()[0].source_target_offset, 60u); + const IndirectCallFixup &restored = consumer->static_indirect_call_fixups()[0]; + EXPECT_EQ(restored.source_target_offset, 60u); + // Here the stash restores into a different pair than the getpc wrote, and the rewrite regenerates + // the add against the producer. Asserting both is what makes this a discovery-path check: the + // layout-level test builds its fixup by hand, so it would still pass if PcValue propagation or + // fixup_for_value dropped the producer pair on the way through. + EXPECT_EQ(restored.source_builder_sreg, 0u); + EXPECT_EQ(restored.source_call_sreg, 20u); } TEST(CfgAnalysis, Gfx1250PcPairCopyReachesConsumer) { @@ -3115,6 +3128,9 @@ TEST(CfgAnalysis, Gfx1250PcPairCopyReachesConsumer) { } ASSERT_NE(copied_call, nullptr); EXPECT_EQ(copied_call->source_target_offset, 28u); + // Same producer/consumer split, reached by a register-pair copy rather than a lane stash. + EXPECT_EQ(copied_call->source_builder_sreg, kSourceSreg); + EXPECT_EQ(copied_call->source_call_sreg, kCopiedSreg); } TEST(CfgAnalysis, Gfx1250DirectCallOverwritesPcBuilderInReturnPair) { diff --git a/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp b/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp index ebc7211e9f0f..fb50d66642e5 100644 --- a/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp +++ b/emulation/rocjitsu/tests/dbt/support/translate_test_support.cpp @@ -105,7 +105,7 @@ static std::vector make_kernel_descriptor_bytes(int64_t entry_offset) { std::vector make_minimal_amdgpu_elf_with_descriptor_after_text( const std::vector &text_words, std::optional text_function_words, size_t text_function_offset_words, std::optional function_pointer_table_target_words, - bool name_function_pointer_table_with_symbol) { + bool name_function_pointer_table_with_symbol, bool export_text_function) { if (text_function_words && text_function_offset_words + *text_function_words > text_words.size()) throw std::invalid_argument("text function extent exceeds .text fixture"); if (function_pointer_table_target_words && @@ -130,7 +130,8 @@ std::vector make_minimal_amdgpu_elf_with_descriptor_after_text( std::vector strtab{'\0'}; const uint32_t kd_symbol_name = add_elf_name(strtab, "kernel.kd"); - const uint32_t text_symbol_name = text_function_words ? add_elf_name(strtab, "kernel") : 0; + const uint32_t text_symbol_name = + text_function_words ? add_elf_name(strtab, export_text_function ? "device_fn" : "kernel") : 0; const uint32_t table_symbol_name = has_table ? add_elf_name(strtab, "function_table") : 0; // The kernel descriptor requires 8-byte alignment (tests reinterpret_cast the @@ -225,8 +226,9 @@ std::vector make_minimal_amdgpu_elf_with_descriptor_after_text( syms[2].st_name = text_symbol_name; // Real device functions are LOCAL and appear only in .symtab. Offset zero is the kernel entry, // which function discovery excludes; a non-zero offset names a callee body. - syms[2].st_info = elf_symbol_info(text_function_offset_words == 0 ? kElfSymbolBindGlobal - : kElfSymbolBindLocal, + syms[2].st_info = elf_symbol_info((text_function_offset_words == 0 || export_text_function) + ? kElfSymbolBindGlobal + : kElfSymbolBindLocal, kElfSymbolTypeFunc); syms[2].st_shndx = 1; syms[2].st_value = text_vaddr + text_function_offset_words * sizeof(uint32_t); diff --git a/emulation/rocjitsu/tests/dbt/support/translate_test_support.h b/emulation/rocjitsu/tests/dbt/support/translate_test_support.h index 4d7dcd8080d8..8219d96dbf7d 100644 --- a/emulation/rocjitsu/tests/dbt/support/translate_test_support.h +++ b/emulation/rocjitsu/tests/dbt/support/translate_test_support.h @@ -48,11 +48,16 @@ void write_kernel_descriptor_for_test(void *descriptor, const TestKernelDescript uint16_t append_elf_section_for_test(std::vector &image, Elf64_Shdr section, std::span contents); +/// @param export_text_function Give the `.text` function global binding and a name of its own. +/// @details A device function is LOCAL and shares the fixture's "kernel" name by default, which +/// object_defines_only_kernels() then pairs with the "kernel.kd" descriptor and counts as a kernel. +/// Set this when the object must look like one that defines a device function a host could have +/// taken the address of -- the shape the kernarg admission has to handle. [[nodiscard]] std::vector make_minimal_amdgpu_elf_with_descriptor_after_text( const std::vector &text_words, std::optional text_function_words = std::nullopt, size_t text_function_offset_words = 0, std::optional function_pointer_table_target_words = std::nullopt, - bool name_function_pointer_table_with_symbol = true); + bool name_function_pointer_table_with_symbol = true, bool export_text_function = false); [[nodiscard]] std::vector make_minimal_amdgpu_elf_with_descriptor_after_text(); /// @brief One sized `STT_FUNC` body in the fixture's `.text`. struct TestTextFunction { diff --git a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp index c1f3402c97af..a353e719ad15 100644 --- a/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp +++ b/emulation/rocjitsu/tests/dbt/translate_gfx1250_test.cpp @@ -2579,6 +2579,64 @@ TEST(BinaryTranslatorE2E, Gfx1250AdmitsKernargLoadedIndirectCallTarget) { EXPECT_TRUE(translate_kernarg_fixture(words, /*enable_kernarg=*/true).ok()); } +// The admission in an object that DOES define a device function. The fixtures above are +// kernel-only, so object_defines_only_kernels() already holds and +// object_admits_kernarg_supplied_transfer is never consulted -- they cannot tell whether that path +// works. Here an exported body sits past the kernel and no edge reaches it, which is the shape +// rocPRIM's trampoline_kernel objects have: the admission turns on the strict symbol requirement, +// so the body has to be adopted or replace_text() refuses the object for a symbol naming nothing. +// Both halves are asserted, because adopting the body and keeping the partition a fixed point are +// separate obligations and only the second is visible on a re-translation. +TEST(BinaryTranslatorE2E, Gfx1250AdmitsKernargTargetInObjectDefiningAnExportedDeviceFunction) { + constexpr size_t kFunctionOffsetWords = 4; + constexpr size_t kFunctionWords = 2; + const std::vector words = { + kernarg_load_word(0), + kernarg_load_word(1), + rocjitsu::build_s_swappc_b64(kKernargReturnSreg, kKernargTargetSreg, + ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), + // Unreachable exported body: nothing branches or calls here, so only adoption can emit it. + rocjitsu::build_s_nop(0, ROCJITSU_CODE_ARCH_CDNA5), + rocjitsu::build_s_endpgm(ROCJITSU_CODE_ARCH_CDNA5), + }; + auto image = rocjitsu::test_support::make_minimal_amdgpu_elf_with_descriptor_after_text( + words, kFunctionWords, kFunctionOffsetWords, /*function_pointer_table_target_words=*/ + std::nullopt, /*name_function_pointer_table_with_symbol=*/true, + /*export_text_function=*/true); + rocjitsu::enable_kernarg_segment_ptr_sgpr(image); + + rocjitsu::AmdGpuCodeObject source(image.data(), image.size()); + ASSERT_TRUE(source.is_valid()); + // Non-vacuity, asserted rather than assumed: if this object still looked kernel-only the older + // fence would admit the transfer and the case below would prove nothing about the new path. + ASSERT_FALSE(rocjitsu::object_defines_only_kernels(source)); + ASSERT_FALSE(rocjitsu::discover_externally_resolvable_text_function_offsets(source).empty()); + + rocjitsu::BinaryTranslator translator( + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + const auto first = translator.translate(source); + ASSERT_TRUE(first.ok()) << (first.diagnostics.empty() ? "" : first.diagnostics.front().message); + + // The exported symbol must still name a body rather than have been undefined or dropped. + rocjitsu::AmdGpuCodeObject translated(first.elf_bytes.data(), first.elf_bytes.size()); + ASSERT_TRUE(translated.is_valid()); + const auto exported = rocjitsu::discover_externally_resolvable_text_function_offsets(translated); + EXPECT_FALSE(exported.empty()); + + // Adoption keyed off anything the first pass changes would move `.text` here. + rocjitsu::BinaryTranslator second_translator( + ROCJITSU_CODE_ARCH_CDNA5, ROCJITSU_CODE_ARCH_CDNA5, 0, + gfx1250_revision_options(rocjitsu::ProcessorRevision::Gfx1250B0, + rocjitsu::ProcessorRevision::Gfx1250A0)); + const auto second = second_translator.translate(translated); + ASSERT_TRUE(second.ok()) << (second.diagnostics.empty() ? "" + : second.diagnostics.front().message); + EXPECT_EQ(first.elf_bytes, second.elf_bytes); +} + // The same words with no kernarg segment pointer in the descriptor. Nothing then supplies the // pair, so the transfer has no provenance and must be refused -- this is what separates "the host // wrote it" from "this object simply never computed it", which an undefined live-in also satisfies. @@ -13075,6 +13133,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteKeepsTheXcntDrain) { .target_end = 8 * kWord}); layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, .source_call_sreg = kPcSreg, + .source_builder_sreg = kPcSreg, .source_requires_xcnt_drain = true, .target_getpc_offset = 0, .target_recovery_begin_offset = kWord, @@ -13110,6 +13169,7 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteOmitsAnUnneededXcntDrain .target_end = 8 * kWord}); layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, .source_call_sreg = kPcSreg, + .source_builder_sreg = kPcSreg, .target_getpc_offset = 0, .target_recovery_begin_offset = kWord, .target_recovery_end_offset = 4 * kWord}); @@ -13128,6 +13188,84 @@ TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteOmitsAnUnneededXcntDrain kPcSreg, kPcSreg, kLiteral64Operand)); } +TEST(BinaryTranslatorE2E, Gfx1250RecoveredBuilderRewriteNamesTheBuilderPairNotTheConsumerPair) { + // A lane-banked dispatcher builds the callee address in a scratch pair, stashes it through + // v_writelane_b32, and restores it into a different pair before the transfer. The rewrite + // regenerates only the delta half and leaves the original s_get_pc_i64 in place, so it has to + // add into the pair that getpc wrote. Naming the consumer's pair instead would add the delta to + // whatever that register happened to hold, leave the stash carrying a bare PC, and pair the + // fresh add with an unrelated earlier getpc that the next pass reads as a code address. + constexpr uint64_t kWord = sizeof(uint32_t); + constexpr uint16_t kBuilderSreg = 4; + constexpr uint16_t kConsumerSreg = 56; + constexpr uint16_t kLiteral64Operand = 254; + std::vector text(8 * kWord, 0); + rocjitsu::KernelTextLayout layout; + layout.body_end = text.size(); + layout.blocks.push_back( + {.source_start = 0, .source_end = 4 * kWord, .target_start = 0, .target_end = 4 * kWord}); + layout.blocks.push_back({.source_start = 4 * kWord, + .source_end = 8 * kWord, + .target_start = 4 * kWord, + .target_end = 8 * kWord}); + layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, + .source_call_sreg = kConsumerSreg, + .source_builder_sreg = kBuilderSreg, + .target_getpc_offset = 0, + .target_recovery_begin_offset = kWord, + .target_recovery_end_offset = 4 * kWord}); + + const auto patched = + rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); + ASSERT_TRUE(patched.ok) << patched.message; + + uint32_t first = 0; + std::memcpy(&first, text.data() + kWord, sizeof(first)); + EXPECT_EQ(first, rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSAddNcU64Sop2, + kBuilderSreg, kBuilderSreg, kLiteral64Operand)); + EXPECT_NE(first, rocjitsu::build_sop2_encoding(ROCJITSU_CODE_ARCH_CDNA5, cdna5::kSAddNcU64Sop2, + kConsumerSreg, kConsumerSreg, kLiteral64Operand)); +} + +TEST(BinaryTranslatorE2E, RecoveredBuilderReuseRejectsDisagreeingBuilderPair) { + // The replacement is an add written against the builder's own SGPR pair, so two consumers that + // share a range while naming different pairs need different words. Reuse compares a key rather + // than the words themselves, so the pair has to be part of that key: without it the second + // consumer silently inherits an add against the first consumer's register. A lane-banked + // dispatcher produces exactly this shape, because its producer and consumer pairs differ. + constexpr uint64_t kWord = sizeof(uint32_t); + constexpr uint16_t kConsumerSreg = 8; + constexpr uint16_t kBuilderSregA = 4; + constexpr uint16_t kBuilderSregB = 56; + std::vector text(8 * kWord, 0); + rocjitsu::KernelTextLayout layout; + layout.body_end = text.size(); + layout.blocks.push_back( + {.source_start = 0, .source_end = 4 * kWord, .target_start = 0, .target_end = 4 * kWord}); + layout.blocks.push_back({.source_start = 4 * kWord, + .source_end = 8 * kWord, + .target_start = 4 * kWord, + .target_end = 8 * kWord}); + layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, + .source_call_sreg = kConsumerSreg, + .source_builder_sreg = kBuilderSregA, + .target_getpc_offset = 0, + .target_recovery_begin_offset = kWord, + .target_recovery_end_offset = 4 * kWord}); + layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, + .source_call_sreg = kConsumerSreg, + .source_builder_sreg = kBuilderSregB, + .target_getpc_offset = 0, + .target_recovery_begin_offset = kWord, + .target_recovery_end_offset = 4 * kWord}); + + const auto patched = + rocjitsu::patch_recovered_builder_fixups(text, layout, ROCJITSU_CODE_ARCH_CDNA5); + EXPECT_FALSE(patched.ok); + EXPECT_NE(patched.message.find("incompatible replacements"), std::string::npos) + << patched.message; +} + TEST(BinaryTranslatorE2E, RecoveredBuilderReuseRejectsDisagreeingXcntDrain) { // Only the first consumer of a shared range writes the replacement, so a // second consumer that wants different words must not be silently dropped. @@ -13144,11 +13282,13 @@ TEST(BinaryTranslatorE2E, RecoveredBuilderReuseRejectsDisagreeingXcntDrain) { .target_end = 8 * kWord}); layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, .source_call_sreg = kPcSreg, + .source_builder_sreg = kPcSreg, .target_getpc_offset = 0, .target_recovery_begin_offset = kWord, .target_recovery_end_offset = 4 * kWord}); layout.recovered_builder_fixups.push_back({.source_target_offset = 4 * kWord, .source_call_sreg = kPcSreg, + .source_builder_sreg = kPcSreg, .source_requires_xcnt_drain = true, .target_getpc_offset = 0, .target_recovery_begin_offset = kWord,